Home
last modified time | relevance | path

Searched refs:CMP_CR1_OPE_MASK (Results 1 – 25 of 26) sorted by relevance

12

/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_cmp.c84 …nt8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK)); in CMP_Init()
99 tmp8 |= CMP_CR1_OPE_MASK; in CMP_Init()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_cmp.c84 …nt8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK)); in CMP_Init()
99 tmp8 |= CMP_CR1_OPE_MASK; in CMP_Init()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h632 #define CMP_CR1_OPE_MASK (0x2U) macro
634 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h917 #define CMP_CR1_OPE_MASK (0x2U) macro
923 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h1183 #define CMP_CR1_OPE_MASK (0x2U) macro
1185 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h1183 #define CMP_CR1_OPE_MASK (0x2U) macro
1185 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h998 #define CMP_CR1_OPE_MASK (0x2U) macro
1000 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h6583 #define CMP_CR1_OPE_MASK (0x2U) macro
6591 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h764 #define CMP_CR1_OPE_MASK 0x2u macro
767 …_OPE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
DMKW40Z4_extension.h2177 #define CMP_RD_CR1_OPE(base) ((CMP_CR1_REG(base) & CMP_CR1_OPE_MASK) >> CMP_CR1_OPE_SHIFT)
2181 #define CMP_WR_CR1_OPE(base, value) (CMP_RMW_CR1(base, CMP_CR1_OPE_MASK, CMP_CR1_OPE(value)))
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h927 #define CMP_CR1_OPE_MASK (0x2U) macro
929 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h998 #define CMP_CR1_OPE_MASK (0x2U) macro
1000 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h764 #define CMP_CR1_OPE_MASK 0x2u macro
767 …_OPE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h764 #define CMP_CR1_OPE_MASK 0x2u macro
767 …_OPE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h5977 #define CMP_CR1_OPE_MASK (0x2U) macro
5983 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h4835 #define CMP_CR1_OPE_MASK (0x2U) macro
4841 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h5981 #define CMP_CR1_OPE_MASK (0x2U) macro
5987 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h4829 #define CMP_CR1_OPE_MASK (0x2U) macro
4835 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h5630 #define CMP_CR1_OPE_MASK (0x2U) macro
5636 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h8769 #define CMP_CR1_OPE_MASK (0x2U) macro
8777 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h8751 #define CMP_CR1_OPE_MASK (0x2U) macro
8759 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h8591 #define CMP_CR1_OPE_MASK (0x2U) macro
8599 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h9807 #define CMP_CR1_OPE_MASK (0x2U) macro
9815 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h9780 #define CMP_CR1_OPE_MASK (0x2U) macro
9788 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h11145 #define CMP_CR1_OPE_MASK (0x2U) macro
11153 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)

12