Home
last modified time | relevance | path

Searched refs:CMP_CR1_INV_MASK (Results 1 – 25 of 26) sorted by relevance

12

/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_cmp.c84 …tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_… in CMP_Init()
91 tmp8 |= CMP_CR1_INV_MASK; in CMP_Init()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_cmp.c84 …tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_… in CMP_Init()
91 tmp8 |= CMP_CR1_INV_MASK; in CMP_Init()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h638 #define CMP_CR1_INV_MASK (0x8U) macro
640 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h931 #define CMP_CR1_INV_MASK (0x8U) macro
937 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h1189 #define CMP_CR1_INV_MASK (0x8U) macro
1191 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h1189 #define CMP_CR1_INV_MASK (0x8U) macro
1191 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h1004 #define CMP_CR1_INV_MASK (0x8U) macro
1006 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h6601 #define CMP_CR1_INV_MASK (0x8U) macro
6607 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h772 #define CMP_CR1_INV_MASK 0x8u macro
775 …_INV(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
DMKW40Z4_extension.h2215 #define CMP_RD_CR1_INV(base) ((CMP_CR1_REG(base) & CMP_CR1_INV_MASK) >> CMP_CR1_INV_SHIFT)
2219 #define CMP_WR_CR1_INV(base, value) (CMP_RMW_CR1(base, CMP_CR1_INV_MASK, CMP_CR1_INV(value)))
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h933 #define CMP_CR1_INV_MASK (0x8U) macro
935 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h1004 #define CMP_CR1_INV_MASK (0x8U) macro
1006 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h772 #define CMP_CR1_INV_MASK 0x8u macro
775 …_INV(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h772 #define CMP_CR1_INV_MASK 0x8u macro
775 …_INV(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h5991 #define CMP_CR1_INV_MASK (0x8U) macro
5997 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h4849 #define CMP_CR1_INV_MASK (0x8U) macro
4855 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h5995 #define CMP_CR1_INV_MASK (0x8U) macro
6001 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h4843 #define CMP_CR1_INV_MASK (0x8U) macro
4849 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h5644 #define CMP_CR1_INV_MASK (0x8U) macro
5650 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h8787 #define CMP_CR1_INV_MASK (0x8U) macro
8793 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h8769 #define CMP_CR1_INV_MASK (0x8U) macro
8775 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h8607 #define CMP_CR1_INV_MASK (0x8U) macro
8613 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h9825 #define CMP_CR1_INV_MASK (0x8U) macro
9831 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h9796 #define CMP_CR1_INV_MASK (0x8U) macro
9802 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h11163 #define CMP_CR1_INV_MASK (0x8U) macro
11169 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)

12