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Searched refs:CMP_CR0_HYSTCTR_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_cmp.c114 tmp8 = base->CR0 & ~(uint8_t)CMP_CR0_HYSTCTR_MASK; in CMP_Init()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_cmp.c114 tmp8 = base->CR0 & ~(uint8_t)CMP_CR0_HYSTCTR_MASK; in CMP_Init()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h621 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
623 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h884 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
892 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h1172 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
1174 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h1172 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
1174 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h987 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
989 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h6547 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
6555 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h751 #define CMP_CR0_HYSTCTR_MASK 0x3u macro
754 …(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
DMKW40Z4_extension.h2075 #define CMP_RD_CR0_HYSTCTR(base) ((CMP_CR0_REG(base) & CMP_CR0_HYSTCTR_MASK) >> CMP_CR0_HYSTCTR_SHI…
2079 #define CMP_WR_CR0_HYSTCTR(base, value) (CMP_RMW_CR0(base, CMP_CR0_HYSTCTR_MASK, CMP_CR0_HYSTCTR(va…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h916 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
918 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h987 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
989 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h751 #define CMP_CR0_HYSTCTR_MASK 0x3u macro
754 …(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h751 #define CMP_CR0_HYSTCTR_MASK 0x3u macro
754 …(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h5944 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
5952 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h4802 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
4810 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h5948 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
5956 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h4796 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
4804 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h5597 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
5605 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h8733 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
8741 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h8715 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
8723 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h8558 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
8566 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h9771 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
9779 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h9747 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
9755 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h11109 #define CMP_CR0_HYSTCTR_MASK (0x3U) macro
11117 … (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)

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