1 /*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <zephyr/device.h>
9 #include <zephyr/init.h>
10 #include <soc.h>
11 #include <zephyr/linker/sections.h>
12 #include <zephyr/linker/linker-defs.h>
13 #if defined(CONFIG_SOC_MIMXRT1189_CM7)
14 #include <zephyr/cache.h>
15 #elif defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
16 #include <fsl_cache.h>
17 #endif
18 #include <fsl_clock.h>
19 #include <fsl_gpc.h>
20 #include <fsl_pmu.h>
21 #include <fsl_dcdc.h>
22 #include <fsl_ele_base_api.h>
23 #include <fsl_trdc.h>
24 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
25 #include <cmsis_core.h>
26
27 /*
28 * Set ELE_STICK_FAILED_STS to 0 when ELE status check is not required,
29 * which is useful when debug reset, where the core has already get the
30 * TRDC ownership at first time and ELE is not able to release TRDC
31 * ownership again for the following TRDC ownership request.
32 */
33 #define ELE_STICK_FAILED_STS 1
34
35 #if ELE_STICK_FAILED_STS
36 #define ELE_IS_FAILED(x) (x != kStatus_Success)
37 #else
38 #define ELE_IS_FAILED(x) false
39 #endif
40
41 #define ELE_TRDC_AON_ID 0x74
42 #define ELE_TRDC_WAKEUP_ID 0x78
43 #define ELE_CORE_CM33_ID 0x1
44 #define ELE_CORE_CM7_ID 0x2
45
46 #ifdef CONFIG_INIT_ARM_PLL
47 static const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
48 #if defined(CONFIG_SOC_MIMXRT1189_CM33) || defined(CONFIG_SOC_MIMXRT1189_CM7)
49 /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
50 .postDivider = kCLOCK_PllPostDiv2,
51 /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
52 .loopDivider = 132,
53 #else
54 #error "Unknown SOC, no pll configuration defined"
55 #endif
56 };
57 #endif
58
59 const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = {
60 /* Enable Sys Pll1 divide-by-2 clock or not */
61 .pllDiv2En = 1,
62 /* Enable Sys Pll1 divide-by-5 clock or not */
63 .pllDiv5En = 1,
64 /* Spread spectrum parameter */
65 .ss = NULL,
66 /* Enable spread spectrum or not */
67 .ssEnable = false,
68 };
69
70 const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = {
71 /* Denominator of spread spectrum */
72 .mfd = 268435455,
73 /* Spread spectrum parameter */
74 .ss = NULL,
75 /* Enable spread spectrum or not */
76 .ssEnable = false,
77 };
78
79 /* Function Name : board_flexspi_clock_safe_config
80 * Description : FLEXSPI clock source safe configuration weak function.
81 * Called before clock source configuration.
82 * Note : Users need override this function to change FLEXSPI clock source to stable
83 * source when executing code on FLEXSPI memory(XIP). If XIP, the function
84 * should runs in RAM and move the FLEXSPI clock source to a stable clock
85 * to avoid instruction/data fetch issue during clock updating.
86 */
board_flexspi_clock_safe_config(void)87 __attribute__((weak)) void board_flexspi_clock_safe_config(void)
88 {
89 }
90
91 /**
92 * @brief Initialize the system clock
93 */
clock_init(void)94 static ALWAYS_INLINE void clock_init(void)
95 {
96 clock_root_config_t rootCfg = {0};
97
98 /* Init OSC RC 400M */
99 CLOCK_OSC_EnableOscRc400M();
100 CLOCK_OSC_GateOscRc400M(false);
101
102 #if CONFIG_CPU_CORTEX_M7
103 /* Switch both core to OscRC400M first */
104 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M;
105 rootCfg.div = 1;
106 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
107 #endif
108
109 #if CONFIG_CPU_CORTEX_M33
110 rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M;
111 rootCfg.div = 2;
112 CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg);
113 #endif
114
115 #if CONFIG_CPU_CORTEX_M7
116 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_CORE0, kDCDC_1P0Target1P1V);
117 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_CORE1, kDCDC_1P0Target1P1V);
118 /* FBB need to be enabled in OverDrive(OD) mode */
119 PMU_EnableFBB(ANADIG_PMU, true);
120 #endif
121
122 /* Config CLK_1M */
123 CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
124
125 /* Init OSC RC 24M */
126 CLOCK_OSC_EnableOscRc24M(true);
127
128 /* Config OSC 24M */
129 ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) |
130 ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) |
131 ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
132
133 /* Wait for 24M OSC to be stable. */
134 while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
135 (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) {
136 }
137
138 /* Call function board_flexspi_clock_safe_config() to move FlexSPI clock to a stable
139 * clock source to avoid instruction/data fetch issue when updating PLL if XIP
140 * (execute code on FLEXSPI memory).
141 */
142 board_flexspi_clock_safe_config();
143
144 #ifdef CONFIG_INIT_ARM_PLL
145 /* Init Arm Pll. */
146 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
147 #endif
148
149 /* Init Sys Pll1. */
150 CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN);
151
152 /* Init Sys Pll2. */
153 CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
154 /* Init System Pll2 pfd0. */
155 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
156 /* Init System Pll2 pfd1. */
157 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
158 /* Init System Pll2 pfd2. */
159 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
160 /* Init System Pll2 pfd3. */
161 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
162
163 /* Init Sys Pll3. */
164 CLOCK_InitSysPll3();
165 /* Init System Pll3 pfd0. */
166 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22);
167 /* Init System Pll3 pfd1. */
168 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 33);
169 /* Init System Pll3 pfd2. */
170 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 22);
171 /* Init System Pll3 pfd3. */
172 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 18);
173
174 /* Bypass Audio Pll. */
175 CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
176 /* DeInit Audio Pll. */
177 CLOCK_DeinitAudioPll();
178
179 #if defined(CONFIG_SOC_MIMXRT1189_CM7)
180 /* Module clock root configurations. */
181 /* Configure M7 using ARM_PLL_CLK */
182 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
183 rootCfg.div = 1;
184 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
185 #endif
186
187 #if defined(CONFIG_SOC_MIMXRT1189_CM33)
188 /* Configure M33 using SYS_PLL3_CLK */
189 rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out;
190 rootCfg.div = 2;
191 CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg);
192 #endif
193
194 /* Configure BUS_AON using SYS_PLL2_CLK */
195 rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out;
196 rootCfg.div = 4;
197 CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg);
198
199 /* Configure BUS_WAKEUP using SYS_PLL2_CLK */
200 rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out;
201 rootCfg.div = 4;
202 CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg);
203
204 /* Configure WAKEUP_AXI using SYS_PLL3_CLK */
205 rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out;
206 rootCfg.div = 2;
207 CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg);
208
209 /* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */
210 rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2;
211 rootCfg.div = 3;
212 CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg);
213
214 #if CONFIG_CPU_CORTEX_M33
215 /* Configure M33_SYSTICK using OSC_24M */
216 rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut;
217 rootCfg.div = 240;
218 CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg);
219 #endif
220
221 #if CONFIG_CPU_CORTEX_M7
222 /* Configure M7_SYSTICK using OSC_24M */
223 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut;
224 rootCfg.div = 240;
225 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
226 #endif
227
228 #if defined(CONFIG_UART_MCUX_LPUART) && \
229 (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1)) \
230 || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2)))
231 /* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */
232 rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2;
233 rootCfg.div = 10;
234 #endif
235
236 #if defined(CONFIG_I2C_MCUX_LPI2C) && \
237 (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1)) \
238 || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c2)))
239 /* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */
240 rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2;
241 rootCfg.div = 4;
242 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg);
243 #endif
244
245 #if defined(CONFIG_I2C_MCUX_LPI2C) && \
246 (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c3)) \
247 || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c4)))
248 /* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */
249 rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2;
250 rootCfg.div = 4;
251 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0304, &rootCfg);
252 #endif
253
254 #if defined(CONFIG_I2C_MCUX_LPI2C) && \
255 (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c5)) \
256 || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c6)))
257 /* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */
258 rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2;
259 rootCfg.div = 4;
260 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg);
261 #endif
262
263 #if defined(CONFIG_SPI_MCUX_LPSPI) && \
264 (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) \
265 || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi2)))
266 /* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */
267 rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1;
268 rootCfg.div = 2;
269 CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg);
270 #endif
271
272 #if defined(CONFIG_COUNTER_MCUX_GPT)
273
274 #if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpt1)))
275 /* Configure GPT1 using SYS_PLL3_DIV2_CLK */
276 rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2;
277 rootCfg.div = 1;
278 CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
279 #endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpt1)) */
280
281 #if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpt2)))
282 /* Configure GPT2 using SYS_PLL3_DIV2_CLK */
283 rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2;
284 rootCfg.div = 1;
285 CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
286 #endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpt2)) */
287
288 #endif /* CONFIG_COUNTER_MCUX_GPT */
289
290 #ifdef CONFIG_MCUX_ACMP
291
292 #if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp1)) \
293 || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp2)) \
294 || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp3)) \
295 || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp4)))
296 /* Configure ACMP using MuxSysPll3Out */
297 rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxSysPll3Out;
298 rootCfg.div = 2;
299 CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
300 #endif
301
302 #endif /* CONFIG_MCUX_ACMP */
303
304 #if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
305 /* Configure ENET using SYS_PLL1_DIV2_CLK */
306 rootCfg.mux = kCLOCK_ENET_ClockRoot_MuxSysPll1Div2;
307 rootCfg.div = 4;
308 CLOCK_SetRootClock(kCLOCK_Root_Enet, &rootCfg);
309
310 /* Configure TMR_1588 using SYS_PLL3_CLK */
311 rootCfg.mux = kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out;
312 rootCfg.div = 2;
313 CLOCK_SetRootClock(kCLOCK_Root_Tmr_1588, &rootCfg);
314
315 /* Configure NETC using SYS_PLL3_PFD3_CLK */
316 rootCfg.mux = kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3;
317 rootCfg.div = 2;
318 CLOCK_SetRootClock(kCLOCK_Root_Netc, &rootCfg);
319
320 /* Configure MAC0 using SYS_PLL1_DIV2_CLK */
321 rootCfg.mux = kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2;
322 rootCfg.div = 10;
323 CLOCK_SetRootClock(kCLOCK_Root_Mac0, &rootCfg);
324
325 /* Configure MAC1 using SYS_PLL1_DIV2_CLK */
326 rootCfg.mux = kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2;
327 rootCfg.div = 4;
328 CLOCK_SetRootClock(kCLOCK_Root_Mac1, &rootCfg);
329
330 /* Configure MAC2 using SYS_PLL1_DIV2_CLK */
331 rootCfg.mux = kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2;
332 rootCfg.div = 4;
333 CLOCK_SetRootClock(kCLOCK_Root_Mac2, &rootCfg);
334
335 /* Configure MAC3 using SYS_PLL1_DIV2_CLK */
336 rootCfg.mux = kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2;
337 rootCfg.div = 4;
338 CLOCK_SetRootClock(kCLOCK_Root_Mac3, &rootCfg);
339
340 /* Configure MAC4 using SYS_PLL1_DIV2_CLK */
341 rootCfg.mux = kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2;
342 rootCfg.div = 10;
343 CLOCK_SetRootClock(kCLOCK_Root_Mac4, &rootCfg);
344
345 /* Set NETC PORT Ref clock source. */
346 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &=
347 ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK;
348 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &=
349 ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK;
350 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &=
351 ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK;
352 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &=
353 ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK;
354 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &=
355 ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK;
356
357 /* Set TMR 1588 Ref clock source. */
358 BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |=
359 BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK;
360 #endif
361
362 #ifdef CONFIG_CAN_MCUX_FLEXCAN
363
364 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan1), okay)
365 /* Configure CAN1 using MuxSysPll3Out */
366 rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxSysPll3Out;
367 rootCfg.div = 6;
368 CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
369 #endif
370
371 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan2), okay)
372 /* Configure CAN2 using MuxSysPll3Out */
373 rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxSysPll3Out;
374 rootCfg.div = 6;
375 CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
376 #endif
377
378 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan3), okay)
379 /* Configure CAN3 using MuxSysPll3Out */
380 rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxSysPll3Out;
381 rootCfg.div = 6;
382 CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
383 #endif
384
385 #endif /* CONFIG_CAN_MCUX_FLEXCAN */
386
387 #if defined(CONFIG_MCUX_LPTMR_TIMER) || defined(CONFIG_COUNTER_MCUX_LPTMR)
388
389 #if DT_NODE_HAS_STATUS(DT_NODELABEL(lptmr1), okay)
390 /* Configure LPTIMER1 using SYS_PLL3_DIV2_CLK */
391 rootCfg.mux = kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2;
392 rootCfg.div = 3;
393 CLOCK_SetRootClock(kCLOCK_Root_Lptimer1, &rootCfg);
394 #endif
395
396 #if DT_NODE_HAS_STATUS(DT_NODELABEL(lptmr2), okay)
397 /* Configure LPTIMER2 using SYS_PLL3_DIV2_CLK */
398 rootCfg.mux = kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2;
399 rootCfg.div = 3;
400 CLOCK_SetRootClock(kCLOCK_Root_Lptimer2, &rootCfg);
401 #endif
402
403 #if DT_NODE_HAS_STATUS(DT_NODELABEL(lptmr3), okay)
404 /* Configure LPTIMER3 using SYS_PLL3_DIV2_CLK */
405 rootCfg.mux = kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2;
406 rootCfg.div = 3;
407 CLOCK_SetRootClock(kCLOCK_Root_Lptimer3, &rootCfg);
408 #endif
409
410 #endif /* CONFIG_MCUX_LPTMR_TIMER || CONFIG_COUNTER_MCUX_LPTMR */
411
412 #if !(DT_NODE_HAS_COMPAT(DT_PARENT(DT_CHOSEN(zephyr_flash)), nxp_imx_flexspi_nor)) && \
413 defined(CONFIG_MEMC_MCUX_FLEXSPI) && DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay)
414 /* Configure FLEXSPI1 using SYS_PLL3_PFD0_CLK */
415 rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0;
416 rootCfg.div = 3;
417 CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
418 #endif
419
420 #ifdef CONFIG_HAS_MCUX_TPM
421
422 #if DT_NODE_HAS_STATUS(DT_NODELABEL(tpm2), okay)
423 /* Configure TPM2 using SYS_PLL3_DIV2_CLK */
424 rootCfg.mux = kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2;
425 rootCfg.div = 3;
426 CLOCK_SetRootClock(kCLOCK_Root_Tpm2, &rootCfg);
427 #endif
428
429 #if DT_NODE_HAS_STATUS(DT_NODELABEL(tpm4), okay)
430 /* Configure TPM4 using SYS_PLL3_DIV2_CLK */
431 rootCfg.mux = kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2;
432 rootCfg.div = 3;
433 CLOCK_SetRootClock(kCLOCK_Root_Tpm4, &rootCfg);
434 #endif
435
436 #if DT_NODE_HAS_STATUS(DT_NODELABEL(tpm5), okay)
437 /* Configure TPM5 using SYS_PLL3_DIV2_CLK */
438 rootCfg.mux = kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2;
439 rootCfg.div = 3;
440 CLOCK_SetRootClock(kCLOCK_Root_Tpm5, &rootCfg);
441 #endif
442
443 #if DT_NODE_HAS_STATUS(DT_NODELABEL(tpm6), okay)
444 /* Configure TPM6 using SYS_PLL3_DIV2_CLK */
445 rootCfg.mux = kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2;
446 rootCfg.div = 3;
447 CLOCK_SetRootClock(kCLOCK_Root_Tpm6, &rootCfg);
448 #endif
449
450 #endif /* CONFIG_HAS_MCUX_TPM */
451
452 #ifdef CONFIG_DT_HAS_NXP_MCUX_I3C_ENABLED
453
454 #if DT_NODE_HAS_STATUS(DT_NODELABEL(i3c1), okay)
455 /* Configure I3C1 using SYS_PLL3_DIV2_CLK */
456 rootCfg.mux = kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2;
457 rootCfg.div = 10;
458 CLOCK_SetRootClock(kCLOCK_Root_I3c1, &rootCfg);
459 #endif
460
461 #if DT_NODE_HAS_STATUS(DT_NODELABEL(i3c2), okay)
462 /* Configure I3C2 using SYS_PLL3_DIV2_CLK */
463 rootCfg.mux = kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2;
464 rootCfg.div = 10;
465 CLOCK_SetRootClock(kCLOCK_Root_I3c2, &rootCfg);
466 #endif
467
468 #endif /* CONFIG_DT_HAS_NXP_MCUX_I3C_ENABLED */
469
470 /* Keep core clock ungated during WFI */
471 CCM->LPCG[1].LPM0 = 0x33333333;
472 CCM->LPCG[1].LPM1 = 0x33333333;
473 /* Keep the system clock running so SYSTICK can wake up
474 * the system from wfi.
475 */
476 GPC_CM_SetNextCpuMode(0, kGPC_RunMode);
477 GPC_CM_SetNextCpuMode(1, kGPC_RunMode);
478 GPC_CM_EnableCpuSleepHold(0, false);
479 GPC_CM_EnableCpuSleepHold(1, false);
480
481 #if !defined(CONFIG_PM)
482 /* Enable the AHB clock while the CM7 is sleeping to allow debug access
483 * to TCM
484 */
485 BLK_CTRL_S_AONMIX->M7_CFG |= BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK;
486 #endif
487 }
488
489 /**
490 * @brief Initialize the system clock
491 */
trdc_enable_all_access(void)492 static ALWAYS_INLINE void trdc_enable_all_access(void)
493 {
494 status_t sts;
495 uint8_t i, j;
496
497 /* Get ELE FW status */
498 do {
499 uint32_t ele_fw_sts;
500
501 sts = ELE_BaseAPI_GetFwStatus(MU_RT_S3MUA, &ele_fw_sts);
502 } while (sts != kStatus_Success);
503
504 do {
505 #if defined(CONFIG_SOC_MIMXRT1189_CM33)
506 /* Release TRDC A to CM33 core */
507 sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ELE_CORE_CM33_ID);
508 #elif defined(CONFIG_SOC_MIMXRT1189_CM7)
509 /* Release TRDC A to CM7 core */
510 sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ELE_CORE_CM7_ID);
511 #endif
512 } while (ELE_IS_FAILED(sts));
513
514 /* Release TRDC W to CM33 core */
515 do {
516 #if defined(CONFIG_SOC_MIMXRT1189_CM33)
517 /* Release TRDC A to CM33 core */
518 sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ELE_CORE_CM33_ID);
519 #elif defined(CONFIG_SOC_MIMXRT1189_CM7)
520 /* Release TRDC A to CM7 core */
521 sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ELE_CORE_CM7_ID);
522 #endif
523 } while (ELE_IS_FAILED(sts));
524
525 /* Enable all access modes for MBC and MRC of TRDCA and TRDCW */
526 trdc_hardware_config_t hwConfig;
527 trdc_memory_access_control_config_t memAccessConfig;
528
529 (void)memset(&memAccessConfig, 0, sizeof(memAccessConfig));
530 memAccessConfig.nonsecureUsrX = 1U;
531 memAccessConfig.nonsecureUsrW = 1U;
532 memAccessConfig.nonsecureUsrR = 1U;
533 memAccessConfig.nonsecurePrivX = 1U;
534 memAccessConfig.nonsecurePrivW = 1U;
535 memAccessConfig.nonsecurePrivR = 1U;
536 memAccessConfig.secureUsrX = 1U;
537 memAccessConfig.secureUsrW = 1U;
538 memAccessConfig.secureUsrR = 1U;
539 memAccessConfig.securePrivX = 1U;
540 memAccessConfig.securePrivW = 1U;
541 memAccessConfig.securePrivR = 1U;
542
543 TRDC_GetHardwareConfig(TRDC1, &hwConfig);
544 for (i = 0U; i < hwConfig.mrcNumber; i++) {
545 for (j = 0U; j < 8; j++) {
546 TRDC_MrcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
547 }
548 }
549
550 for (i = 0U; i < hwConfig.mbcNumber; i++) {
551 for (j = 0U; j < 8; j++) {
552 TRDC_MbcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
553 }
554 }
555
556 TRDC_GetHardwareConfig(TRDC2, &hwConfig);
557 for (i = 0U; i < hwConfig.mrcNumber; i++) {
558 for (j = 0U; j < 8; j++) {
559 TRDC_MrcSetMemoryAccessConfig(TRDC2, &memAccessConfig, i, j);
560 }
561 }
562
563 for (i = 0U; i < hwConfig.mbcNumber; i++) {
564 for (j = 0U; j < 8; j++) {
565 TRDC_MbcSetMemoryAccessConfig(TRDC2, &memAccessConfig, i, j);
566 }
567 }
568 }
569
570 /**
571 *
572 * @brief Perform basic hardware initialization
573 *
574 * Initialize the interrupt controller device drivers.
575 * Also initialize the timer device driver, if required.
576 * If dual core operation is enabled, the second core image will be loaded to RAM
577 *
578 * @return 0
579 */
580
soc_early_init_hook(void)581 void soc_early_init_hook(void)
582 {
583 /* Initialize system clock */
584 clock_init();
585 /* Get trdc and enable all access modes for MBC and MRC of TRDCA and TRDCW */
586 trdc_enable_all_access();
587
588 /* Enable data cache */
589 #if defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
590 XCACHE_EnableCache(XCACHE_PC);
591 XCACHE_EnableCache(XCACHE_PS);
592 #elif defined(CONFIG_SOC_MIMXRT1189_CM7)
593 sys_cache_instr_enable();
594 sys_cache_data_enable();
595 #endif
596 __ISB();
597 __DSB();
598 }
599
600 #ifdef CONFIG_SOC_RESET_HOOK
soc_reset_hook(void)601 void soc_reset_hook(void)
602 {
603 SystemInit();
604 }
605 #endif
606
