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Searched refs:CFG (Results 1 – 25 of 48) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/imxrt6xx/
Dfsl_usart.c233 base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | in USART_Init()
283 base->CFG &= ~(USART_CFG_ENABLE_MASK); in USART_Deinit()
355 if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) in USART_SetBaudRate()
357 if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) in USART_SetBaudRate()
428 base->CFG &= ~(USART_CFG_ENABLE_MASK); in USART_Enable32kMode()
431 base->CFG |= USART_CFG_MODE32K_MASK; in USART_Enable32kMode()
443 base->CFG &= ~(USART_CFG_MODE32K_MASK); in USART_Enable32kMode()
450 base->CFG |= USART_CFG_ENABLE_MASK; in USART_Enable32kMode()
471 temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); in USART_Enable9bitMode()
473 base->CFG = temp; in USART_Enable9bitMode()
[all …]
Dfsl_puf.h291 base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ in PUF_BlockSetKey()
298 base->CFG |= PUF_CFG_PUF_BLOCK_SET_KEY_MASK; /* block set key */ in PUF_BlockSetKey()
305 base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ in PUF_BlockEnroll()
312 base->CFG |= PUF_CFG_PUF_BLOCK_ENROLL_MASK; /* block enroll */ in PUF_BlockEnroll()
Dfsl_i2c.h531 base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; in I2C_MasterEnable()
535 base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; in I2C_MasterEnable()
926 base->CFG = I2C_CFG_SLVEN(enable); in I2C_SlaveEnable()
Dfsl_dma.h441 base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; in DMA_EnableChannelPeriphRq()
454 base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; in DMA_DisableChannelPeriphRq()
498 base->CHANNEL[channel].CFG = in DMA_SetChannelPriority()
499 …(base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(p… in DMA_SetChannelPriority()
512 … return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> in DMA_GetChannelPriority()
Dfsl_usart.h356 base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; in USART_EnableMatchAddress()
361 base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; in USART_EnableMatchAddress()
512 base->CFG |= USART_CFG_CTSEN_MASK; in USART_EnableCTS()
516 base->CFG &= ~USART_CFG_CTSEN_MASK; in USART_EnableCTS()
Dfsl_spi.c200 tmpConfig = base->CFG; in SPI_MasterInit()
215 base->CFG = tmpConfig; in SPI_MasterInit()
312 tmpConfig = base->CFG; in SPI_SlaveInit()
323 base->CFG = tmpConfig; in SPI_SlaveInit()
360 base->CFG &= ~(SPI_CFG_ENABLE_MASK); in SPI_Deinit()
485 if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) in SPI_MasterTransferCreateHandle()
Dfsl_dma.c179 tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); in DMA_ConfigureChannelTrigger()
181 base->CHANNEL[channel].CFG = tmpReg; in DMA_ConfigureChannelTrigger()
620 tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); in DMA_SetChannelConfig()
629 base->CHANNEL[channel].CFG = tmpReg; in DMA_SetChannelConfig()
980 if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) in DMA_StartTransfer()
Dfsl_puf.c89 conf->puf_sram_base->CFG |= PUF_ENABLE_CTRL; in puf_powerOn()
146 conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; in PUF_PowerCycle()
213 conf->puf_sram_base->CFG |= PUF_SRAM_CTRL_CFG_CKGATING(conf->CKGATING); in PUF_Init()
256 conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; in PUF_Deinit()
Dfsl_lpadc.c123 base->CFG = tmp32; in LPADC_Init()
490 base->CFG |= ADC_CFG_CALOFS_MASK; in LPADC_EnableCalibration()
494 base->CFG &= ~ADC_CFG_CALOFS_MASK; in LPADC_EnableCalibration()
Dfsl_spi.h405 base->CFG |= SPI_CFG_ENABLE_MASK; in SPI_Enable()
409 base->CFG &= ~SPI_CFG_ENABLE_MASK; in SPI_Enable()
/hal_nxp-2.7.6/mcux/drivers/lpc/
Dfsl_usart.c233 base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | in USART_Init()
283 base->CFG &= ~(USART_CFG_ENABLE_MASK); in USART_Deinit()
355 if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) in USART_SetBaudRate()
357 if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) in USART_SetBaudRate()
428 base->CFG &= ~(USART_CFG_ENABLE_MASK); in USART_Enable32kMode()
431 base->CFG |= USART_CFG_MODE32K_MASK; in USART_Enable32kMode()
443 base->CFG &= ~(USART_CFG_MODE32K_MASK); in USART_Enable32kMode()
450 base->CFG |= USART_CFG_ENABLE_MASK; in USART_Enable32kMode()
471 temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); in USART_Enable9bitMode()
473 base->CFG = temp; in USART_Enable9bitMode()
[all …]
Dfsl_puf.h291 base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ in PUF_BlockSetKey()
298 base->CFG |= PUF_CFG_PUF_BLOCK_SET_KEY_MASK; /* block set key */ in PUF_BlockSetKey()
305 base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ in PUF_BlockEnroll()
312 base->CFG |= PUF_CFG_PUF_BLOCK_ENROLL_MASK; /* block enroll */ in PUF_BlockEnroll()
Dfsl_i2c.h531 base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; in I2C_MasterEnable()
535 base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; in I2C_MasterEnable()
926 base->CFG = I2C_CFG_SLVEN(enable); in I2C_SlaveEnable()
Dfsl_dma.h441 base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; in DMA_EnableChannelPeriphRq()
454 base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; in DMA_DisableChannelPeriphRq()
498 base->CHANNEL[channel].CFG = in DMA_SetChannelPriority()
499 …(base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(p… in DMA_SetChannelPriority()
512 … return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> in DMA_GetChannelPriority()
Dfsl_usart.h356 base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; in USART_EnableMatchAddress()
361 base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; in USART_EnableMatchAddress()
512 base->CFG |= USART_CFG_CTSEN_MASK; in USART_EnableCTS()
516 base->CFG &= ~USART_CFG_CTSEN_MASK; in USART_EnableCTS()
Dfsl_spi.c200 tmpConfig = base->CFG; in SPI_MasterInit()
215 base->CFG = tmpConfig; in SPI_MasterInit()
312 tmpConfig = base->CFG; in SPI_SlaveInit()
323 base->CFG = tmpConfig; in SPI_SlaveInit()
360 base->CFG &= ~(SPI_CFG_ENABLE_MASK); in SPI_Deinit()
485 if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) in SPI_MasterTransferCreateHandle()
Dfsl_dma.c179 tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); in DMA_ConfigureChannelTrigger()
181 base->CHANNEL[channel].CFG = tmpReg; in DMA_ConfigureChannelTrigger()
620 tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); in DMA_SetChannelConfig()
629 base->CHANNEL[channel].CFG = tmpReg; in DMA_SetChannelConfig()
980 if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) in DMA_StartTransfer()
Dfsl_puf.c89 conf->puf_sram_base->CFG |= PUF_ENABLE_CTRL; in puf_powerOn()
146 conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; in PUF_PowerCycle()
213 conf->puf_sram_base->CFG |= PUF_SRAM_CTRL_CFG_CKGATING(conf->CKGATING); in PUF_Init()
256 conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; in PUF_Deinit()
Dfsl_lpadc.c123 base->CFG = tmp32; in LPADC_Init()
490 base->CFG |= ADC_CFG_CALOFS_MASK; in LPADC_EnableCalibration()
494 base->CFG &= ~ADC_CFG_CALOFS_MASK; in LPADC_EnableCalibration()
Dfsl_spi.h405 base->CFG |= SPI_CFG_ENABLE_MASK; in SPI_Enable()
409 base->CFG &= ~SPI_CFG_ENABLE_MASK; in SPI_Enable()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_adc.c75 tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */ in ADC_Init()
94 base->CFG = tmp32; in ADC_Init()
232 if (0U != (ADC_CFG_ADTRG_MASK & base->CFG)) in ADC_DoAutoCalibration()
369 tmp32 = base->CFG & ~ADC_CFG_AVGS_MASK; in ADC_SetHardwareAverageConfig()
371 base->CFG = tmp32; in ADC_SetHardwareAverageConfig()
Dfsl_puf.h291 base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ in PUF_BlockSetKey()
298 base->CFG |= PUF_CFG_PUF_BLOCK_SET_KEY_MASK; /* block set key */ in PUF_BlockSetKey()
305 base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ in PUF_BlockEnroll()
312 base->CFG |= PUF_CFG_PUF_BLOCK_ENROLL_MASK; /* block enroll */ in PUF_BlockEnroll()
Dfsl_puf.c89 conf->puf_sram_base->CFG |= PUF_ENABLE_CTRL; in puf_powerOn()
146 conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; in PUF_PowerCycle()
213 conf->puf_sram_base->CFG |= PUF_SRAM_CTRL_CFG_CKGATING(conf->CKGATING); in PUF_Init()
256 conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; in PUF_Deinit()
Dfsl_adc.h359 base->CFG |= ADC_CFG_ADTRG_MASK; in ADC_EnableHardwareTrigger()
363 base->CFG &= ~ADC_CFG_ADTRG_MASK; in ADC_EnableHardwareTrigger()
Dfsl_lpadc.c123 base->CFG = tmp32; in LPADC_Init()
490 base->CFG |= ADC_CFG_CALOFS_MASK; in LPADC_EnableCalibration()
494 base->CFG &= ~ADC_CFG_CALOFS_MASK; in LPADC_EnableCalibration()

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