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/hal_nxp-2.7.6/mcux/drivers/imxrt6xx/
Dfsl_acmp.c87 … tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK | in ACMP_Init()
112 base->C0 = tmp32; in ACMP_Init()
179 base->C0 = ((base->C0 | CMP_C0_EN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_Enable()
183 base->C0 &= ~(CMP_C0_EN_MASK | CMP_C0_CFx_MASK); in ACMP_Enable()
203 base->C0 = ((base->C0 | CMP_C0_LINKEN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableLinkToDAC()
207 base->C0 &= ~(CMP_C0_LINKEN_MASK | CMP_C0_CFx_MASK); in ACMP_EnableLinkToDAC()
267 base->C0 = ((base->C0 | CMP_C0_DMAEN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableDMA()
271 base->C0 &= ~(CMP_C0_DMAEN_MASK | CMP_C0_CFx_MASK); in ACMP_EnableDMA()
288 base->C0 = ((base->C0 | CMP_C0_WE_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableWindowMode()
292 base->C0 &= ~(CMP_C0_WE_MASK | CMP_C0_CFx_MASK); in ACMP_EnableWindowMode()
[all …]
/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_acmp.c87 … tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK | in ACMP_Init()
112 base->C0 = tmp32; in ACMP_Init()
179 base->C0 = ((base->C0 | CMP_C0_EN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_Enable()
183 base->C0 &= ~(CMP_C0_EN_MASK | CMP_C0_CFx_MASK); in ACMP_Enable()
203 base->C0 = ((base->C0 | CMP_C0_LINKEN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableLinkToDAC()
207 base->C0 &= ~(CMP_C0_LINKEN_MASK | CMP_C0_CFx_MASK); in ACMP_EnableLinkToDAC()
267 base->C0 = ((base->C0 | CMP_C0_DMAEN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableDMA()
271 base->C0 &= ~(CMP_C0_DMAEN_MASK | CMP_C0_CFx_MASK); in ACMP_EnableDMA()
288 base->C0 = ((base->C0 | CMP_C0_WE_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableWindowMode()
292 base->C0 &= ~(CMP_C0_WE_MASK | CMP_C0_CFx_MASK); in ACMP_EnableWindowMode()
[all …]
Dfsl_dac.c81 tmp8 = base->C0 & (uint8_t)(~(DAC_C0_DACRFS_MASK | DAC_C0_LPEN_MASK)); in DAC_Init()
90 base->C0 = tmp8; in DAC_Init()
149 tmp8 = base->C0 & (uint8_t)(~DAC_C0_DACTRGSEL_MASK); in DAC_SetBufferConfig()
154 base->C0 = tmp8; in DAC_SetBufferConfig()
251 base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */ in DAC_EnableBufferInterrupts()
267 base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */ in DAC_DisableBufferInterrupts()
Dfsl_dac.h191 base->C0 |= (uint8_t)DAC_C0_DACEN_MASK; in DAC_Enable()
195 base->C0 &= (uint8_t)(~DAC_C0_DACEN_MASK); in DAC_Enable()
285 base->C0 |= DAC_C0_DACSWTRG_MASK; in DAC_DoSoftwareTriggerBuffer()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_acmp.c87 … tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK | in ACMP_Init()
112 base->C0 = tmp32; in ACMP_Init()
179 base->C0 = ((base->C0 | CMP_C0_EN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_Enable()
183 base->C0 &= ~(CMP_C0_EN_MASK | CMP_C0_CFx_MASK); in ACMP_Enable()
203 base->C0 = ((base->C0 | CMP_C0_LINKEN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableLinkToDAC()
207 base->C0 &= ~(CMP_C0_LINKEN_MASK | CMP_C0_CFx_MASK); in ACMP_EnableLinkToDAC()
267 base->C0 = ((base->C0 | CMP_C0_DMAEN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableDMA()
271 base->C0 &= ~(CMP_C0_DMAEN_MASK | CMP_C0_CFx_MASK); in ACMP_EnableDMA()
288 base->C0 = ((base->C0 | CMP_C0_WE_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableWindowMode()
292 base->C0 &= ~(CMP_C0_WE_MASK | CMP_C0_CFx_MASK); in ACMP_EnableWindowMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MIMXRT1176/
Dfsl_acmp.c87 … tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK | in ACMP_Init()
112 base->C0 = tmp32; in ACMP_Init()
179 base->C0 = ((base->C0 | CMP_C0_EN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_Enable()
183 base->C0 &= ~(CMP_C0_EN_MASK | CMP_C0_CFx_MASK); in ACMP_Enable()
203 base->C0 = ((base->C0 | CMP_C0_LINKEN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableLinkToDAC()
207 base->C0 &= ~(CMP_C0_LINKEN_MASK | CMP_C0_CFx_MASK); in ACMP_EnableLinkToDAC()
267 base->C0 = ((base->C0 | CMP_C0_DMAEN_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableDMA()
271 base->C0 &= ~(CMP_C0_DMAEN_MASK | CMP_C0_CFx_MASK); in ACMP_EnableDMA()
288 base->C0 = ((base->C0 | CMP_C0_WE_MASK) & ~CMP_C0_CFx_MASK); in ACMP_EnableWindowMode()
292 base->C0 &= ~(CMP_C0_WE_MASK | CMP_C0_CFx_MASK); in ACMP_EnableWindowMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h741 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h1122 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
1143 #define DAC_C0_REG(base) ((base)->C0)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h1122 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
1143 #define DAC_C0_REG(base) ((base)->C0)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h1122 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
1143 #define DAC_C0_REG(base) ((base)->C0)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h1383 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h1464 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h2267 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h2271 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ member
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h1248 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h7398 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h1177 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h1248 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h6451 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h5526 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h6455 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h5520 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h6336 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ member
/hal_nxp-2.7.6/mcux/devices/MIMXRT685S/
DMIMXRT685S_dsp.h4585 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x8 */ member
DMIMXRT685S_cm33.h9328 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x8 */ member

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