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Searched refs:B0 (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-2.7.6/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/
Dfsl_xcvr_common_config.c463 …init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(END_OF_RX_WU_26MHZ) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU),
464 ….end_of_seq_init_32mhz = B3(END_OF_RX_WD) | B2(END_OF_RX_WU) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU),
467 .lpps_ctrl_init = B3(102) | B2(40) | B1(0) | B0(0),
470 .tsm_fast_ctrl2_init_26mhz = B3(102 + ADD_FOR_26MHZ) | B2(40 + ADD_FOR_26MHZ) | B1(66) | B0(8),
471 .tsm_fast_ctrl2_init_32mhz = B3(102) | B2(40) | B1(66) | B0(8),
478 ….recycle_count_init_26mhz = B3(0) | B2(0x1C + ADD_FOR_26MHZ) | B1(0x06) | B0(0x66 + ADD_FOR_26MHZ),
479 .recycle_count_init_26mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66),
481 ….tsm_timing_00_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_hf_en */
482 ….tsm_timing_01_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_adcdac_…
483 .tsm_timing_02_init = B3(END_OF_RX_WD) | B2(0x00) | B1(0xFF) | B0(0xFF), /* bb_ldo_bba_en */
[all …]
Dfsl_xcvr_ant_config.c110 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
112 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
Dfsl_xcvr_ble_config.c106 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
108 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
Dfsl_xcvr_zgbe_config.c93 ….tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments a…
95 .tsm_timing_35_init = B0(ZGBE_TX_DIG_EN_ASSERT),
Dfsl_xcvr_gfsk_bt_0p3_h_0p5_config.c92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
94 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
Dfsl_xcvr_gfsk_bt_0p5_h_0p32_config.c92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
94 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
Dfsl_xcvr_gfsk_bt_0p5_h_0p7_config.c92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ),
94 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
Dfsl_xcvr_gfsk_bt_0p5_h_1p0_config.c91 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ),
93 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
Dfsl_xcvr_gfsk_bt_0p7_h_0p5_config.c92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
94 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
Dfsl_xcvr_msk_config.c92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
94 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
Dfsl_xcvr_gfsk_bt_0p5_h_0p5_config.c105 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
107 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
/hal_nxp-2.7.6/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/
Dfsl_xcvr.c998 temp |= B0(END_OF_TX_WU - 4) | B1(END_OF_TX_WU + 1); /* (sy_pd_cycle_slip_ld_ft_en) */ in XCVR_Configure()
1008 temp &= ~(B0(0xFF)); in XCVR_Configure()
1011 temp |= B0(END_OF_TX_WU - 2 - 8); /* Adjust for data padding time */ in XCVR_Configure()
1015 temp |= B0(END_OF_TX_WU - 2); /* No data padding adjustment */ in XCVR_Configure()
1024 …XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | B0(TX_DIG_EN_ASSERT_MSK500); /* LSbyte is mo… in XCVR_Configure()
Dfsl_xcvr.h68 #define B0(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0xFFU) macro