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Searched refs:ADC_SC1_ADCH_MASK (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_adc12.c245 tmp32 = (base->SC1[channelGroup] & ~(ADC_SC1_ADCH_MASK | ADC_SC1_AIEN_MASK)); in ADC12_SetChannelConfig()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h379 #define ADC_SC1_ADCH_MASK (0x1FU) macro
381 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h450 #define ADC_SC1_ADCH_MASK (0x1FU) macro
486 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h417 #define ADC_SC1_ADCH_MASK (0x1FU) macro
419 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h568 #define ADC_SC1_ADCH_MASK (0x1FU) macro
604 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h417 #define ADC_SC1_ADCH_MASK (0x1FU) macro
419 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h568 #define ADC_SC1_ADCH_MASK (0x1FU) macro
604 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h568 #define ADC_SC1_ADCH_MASK (0x1FU) macro
604 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h337 #define ADC_SC1_ADCH_MASK (0x1FU) macro
339 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h460 #define ADC_SC1_ADCH_MASK (0x1FU) macro
497 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h299 #define ADC_SC1_ADCH_MASK 0x1Fu macro
302 …H(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
DMKW40Z4_extension.h238 #define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADC…
242 #define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_AD…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h336 #define ADC_SC1_ADCH_MASK (0x1FU) macro
338 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h337 #define ADC_SC1_ADCH_MASK (0x1FU) macro
339 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h299 #define ADC_SC1_ADCH_MASK 0x1Fu macro
302 …H(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h299 #define ADC_SC1_ADCH_MASK 0x1Fu macro
302 …H(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h708 #define ADC_SC1_ADCH_MASK (0x1FU) macro
744 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h518 #define ADC_SC1_ADCH_MASK (0x1FU) macro
554 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h708 #define ADC_SC1_ADCH_MASK (0x1FU) macro
744 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h512 #define ADC_SC1_ADCH_MASK (0x1FU) macro
548 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h472 #define ADC_SC1_ADCH_MASK (0x1FU) macro
508 … (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)