| /hal_nxp-2.7.6/mcux/drivers/kinetis/ |
| D | fsl_adc12.c | 101 uint32_t CLP1 = ((base->CLP1 & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT); in ADC12_GetCalibrationStatus()
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| /hal_nxp-2.7.6/mcux/devices/MKL25Z4/ |
| D | MKL25Z4.h | 525 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
527 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MK22F51212/ |
| D | MK22F51212.h | 766 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
768 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKW24D5/ |
| D | MKW24D5.h | 563 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
565 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKE14F16/ |
| D | MKE14F16.h | 835 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
837 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKW22D5/ |
| D | MKW22D5.h | 563 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
565 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKE16F16/ |
| D | MKE16F16.h | 835 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
837 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKE18F16/ |
| D | MKE18F16.h | 835 #define ADC_CLP1_CLP1_MASK (0x1FFU) macro
837 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKW31Z4/ |
| D | MKW31Z4.h | 483 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
485 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MK64F12/ |
| D | MK64F12.h | 831 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
833 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKW40Z4/ |
| D | MKW40Z4.h | 459 #define ADC_CLP1_CLP1_MASK 0x7Fu macro
462 …(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
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| D | MKW40Z4_extension.h | 1475 #define ADC_RD_CLP1_CLP1(base) ((ADC_CLP1_REG(base) & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT)
1479 #define ADC_WR_CLP1_CLP1(base, value) (ADC_RMW_CLP1(base, ADC_CLP1_CLP1_MASK, ADC_CLP1_CLP1(value)))
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| /hal_nxp-2.7.6/mcux/devices/MKW21Z4/ |
| D | MKW21Z4.h | 482 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
484 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKW41Z4/ |
| D | MKW41Z4.h | 483 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
485 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKW20Z4/ |
| D | MKW20Z4.h | 459 #define ADC_CLP1_CLP1_MASK 0x7Fu macro
462 …(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKW30Z4/ |
| D | MKW30Z4.h | 459 #define ADC_CLP1_CLP1_MASK 0x7Fu macro
462 …(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKV56F24/ |
| D | MKV56F24.h | 1024 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
1026 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MK80F25615/ |
| D | MK80F25615.h | 834 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
836 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MKV58F24/ |
| D | MKV58F24.h | 1024 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
1026 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MK82F25615/ |
| D | MK82F25615.h | 828 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
830 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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| /hal_nxp-2.7.6/mcux/devices/MK66F18/ |
| D | MK66F18.h | 788 #define ADC_CLP1_CLP1_MASK (0x7FU) macro
790 … (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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