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Searched refs:ADC_CFG1_ADIV_MASK (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_adc12.c145 tmp32 = (base->CFG1 & ~(ADC_CFG1_ADICLK_MASK | ADC_CFG1_ADIV_MASK | ADC_CFG1_MODE_MASK)); in ADC12_Init()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h405 #define ADC_CFG1_ADIV_MASK (0x60U) macro
407 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h540 #define ADC_CFG1_ADIV_MASK (0x60U) macro
548 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h443 #define ADC_CFG1_ADIV_MASK (0x60U) macro
445 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h644 #define ADC_CFG1_ADIV_MASK (0x60U) macro
652 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h443 #define ADC_CFG1_ADIV_MASK (0x60U) macro
445 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h644 #define ADC_CFG1_ADIV_MASK (0x60U) macro
652 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h644 #define ADC_CFG1_ADIV_MASK (0x60U) macro
652 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h363 #define ADC_CFG1_ADIV_MASK (0x60U) macro
365 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h558 #define ADC_CFG1_ADIV_MASK (0x60U) macro
566 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h328 #define ADC_CFG1_ADIV_MASK 0x60u macro
331 …(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
DMKW40Z4_extension.h428 #define ADC_RD_CFG1_ADIV(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
432 #define ADC_WR_CFG1_ADIV(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADIV_MASK, ADC_CFG1_ADIV(value)))
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h362 #define ADC_CFG1_ADIV_MASK (0x60U) macro
364 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h363 #define ADC_CFG1_ADIV_MASK (0x60U) macro
365 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h328 #define ADC_CFG1_ADIV_MASK 0x60u macro
331 …(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h328 #define ADC_CFG1_ADIV_MASK 0x60u macro
331 …(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h798 #define ADC_CFG1_ADIV_MASK (0x60U) macro
806 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h608 #define ADC_CFG1_ADIV_MASK (0x60U) macro
616 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h798 #define ADC_CFG1_ADIV_MASK (0x60U) macro
806 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h602 #define ADC_CFG1_ADIV_MASK (0x60U) macro
610 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h562 #define ADC_CFG1_ADIV_MASK (0x60U) macro
570 … (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)