1 /**************************************************************************//** 2 * @file pdma.h 3 * @version V1.00 4 * @brief PDMA driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __PDMA_H__ 10 #define __PDMA_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup PDMA_Driver PDMA Driver 23 @{ 24 */ 25 26 /** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants 27 @{ 28 */ 29 #define PDMA_CH_MAX 16UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ 30 31 /*---------------------------------------------------------------------------------------------------------*/ 32 /* Operation Mode Constant Definitions */ 33 /*---------------------------------------------------------------------------------------------------------*/ 34 #define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */ 35 #define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */ 36 #define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */ 37 38 /*---------------------------------------------------------------------------------------------------------*/ 39 /* Data Width Constant Definitions */ 40 /*---------------------------------------------------------------------------------------------------------*/ 41 #define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */ 42 #define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */ 43 #define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */ 44 45 /*---------------------------------------------------------------------------------------------------------*/ 46 /* Address Attribute Constant Definitions */ 47 /*---------------------------------------------------------------------------------------------------------*/ 48 #define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */ 49 #define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */ 50 #define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */ 51 #define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */ 52 53 /*---------------------------------------------------------------------------------------------------------*/ 54 /* Burst Mode Constant Definitions */ 55 /*---------------------------------------------------------------------------------------------------------*/ 56 #define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */ 57 #define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */ 58 59 #define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */ 60 #define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */ 61 #define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */ 62 #define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */ 63 #define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */ 64 #define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */ 65 #define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */ 66 #define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */ 67 68 /*---------------------------------------------------------------------------------------------------------*/ 69 /* Table Interrupt Disable Constant Definitions */ 70 /*---------------------------------------------------------------------------------------------------------*/ 71 #define PDMA_TBINTDIS_ENABLE (0x0UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Enabled \hideinitializer */ 72 #define PDMA_TBINTDIS_DISABLE (0x1UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Disabled \hideinitializer */ 73 74 /*---------------------------------------------------------------------------------------------------------*/ 75 /* Peripheral Transfer Mode Constant Definitions */ 76 /*---------------------------------------------------------------------------------------------------------*/ 77 #define PDMA_MEM 0UL /*!<DMA Connect to Memory \hideinitializer */ 78 #define PDMA_USB_TX 2UL /*!<DMA Connect to USB_TX \hideinitializer */ 79 #define PDMA_USB_RX 3UL /*!<DMA Connect to USB_RX \hideinitializer */ 80 #define PDMA_UART0_TX 4UL /*!<DMA Connect to UART0_TX \hideinitializer */ 81 #define PDMA_UART0_RX 5UL /*!<DMA Connect to UART0_RX \hideinitializer */ 82 #define PDMA_UART1_TX 6UL /*!<DMA Connect to UART1_TX \hideinitializer */ 83 #define PDMA_UART1_RX 7UL /*!<DMA Connect to UART1_RX \hideinitializer */ 84 #define PDMA_UART2_TX 8UL /*!<DMA Connect to UART2_TX \hideinitializer */ 85 #define PDMA_UART2_RX 9UL /*!<DMA Connect to UART2_RX \hideinitializer */ 86 #define PDMA_UART3_TX 10UL /*!<DMA Connect to UART3_TX \hideinitializer */ 87 #define PDMA_UART3_RX 11UL /*!<DMA Connect to UART3_RX \hideinitializer */ 88 #define PDMA_UART4_TX 12UL /*!<DMA Connect to UART4_TX \hideinitializer */ 89 #define PDMA_UART4_RX 13UL /*!<DMA Connect to UART4_RX \hideinitializer */ 90 #define PDMA_UART5_TX 14UL /*!<DMA Connect to UART5_TX \hideinitializer */ 91 #define PDMA_UART5_RX 15UL /*!<DMA Connect to UART5_RX \hideinitializer */ 92 #define PDMA_USCI0_TX 16UL /*!<DMA Connect to USCI0_TX \hideinitializer */ 93 #define PDMA_USCI0_RX 17UL /*!<DMA Connect to USCI0_RX \hideinitializer */ 94 #define PDMA_QSPI0_TX 20UL /*!<DMA Connect to QSPI0_TX \hideinitializer */ 95 #define PDMA_QSPI0_RX 21UL /*!<DMA Connect to QSPI0_RX \hideinitializer */ 96 #define PDMA_SPI0_TX 22UL /*!<DMA Connect to SPI0_TX \hideinitializer */ 97 #define PDMA_SPI0_RX 23UL /*!<DMA Connect to SPI0_RX \hideinitializer */ 98 #define PDMA_SPI1_TX 24UL /*!<DMA Connect to SPI1_TX \hideinitializer */ 99 #define PDMA_SPI1_RX 25UL /*!<DMA Connect to SPI1_RX \hideinitializer */ 100 #define PDMA_SPI2_TX 26UL /*!<DMA Connect to SPI2_TX \hideinitializer */ 101 #define PDMA_SPI2_RX 27UL /*!<DMA Connect to SPI2_RX \hideinitializer */ 102 #define PDMA_SPI3_TX 28UL /*!<DMA Connect to SPI3_TX \hideinitializer */ 103 #define PDMA_SPI3_RX 29UL /*!<DMA Connect to SPI3_RX \hideinitializer */ 104 #define PDMA_QSPI1_TX 30UL /*!<DMA Connect to QSPI1_TX \hideinitializer */ 105 #define PDMA_QSPI1_RX 31UL /*!<DMA Connect to QSPI1_RX \hideinitializer */ 106 #define PDMA_EPWM0_P1_RX 32UL /*!<DMA Connect to EPWM0_P1 \hideinitializer */ 107 #define PDMA_EPWM0_P2_RX 33UL /*!<DMA Connect to EPWM0_P2 \hideinitializer */ 108 #define PDMA_EPWM0_P3_RX 34UL /*!<DMA Connect to EPWM0_P3 \hideinitializer */ 109 #define PDMA_EPWM1_P1_RX 35UL /*!<DMA Connect to EPWM1_P1 \hideinitializer */ 110 #define PDMA_EPWM1_P2_RX 36UL /*!<DMA Connect to EPWM1_P2 \hideinitializer */ 111 #define PDMA_EPWM1_P3_RX 37UL /*!<DMA Connect to PWM1_P3 \hideinitializer */ 112 #define PDMA_I2C0_TX 38UL /*!<DMA Connect to I2C0_TX \hideinitializer */ 113 #define PDMA_I2C0_RX 39UL /*!<DMA Connect to I2C0_RX \hideinitializer */ 114 #define PDMA_I2C1_TX 40UL /*!<DMA Connect to I2C1_TX \hideinitializer */ 115 #define PDMA_I2C1_RX 41UL /*!<DMA Connect to I2C1_RX \hideinitializer */ 116 #define PDMA_I2C2_TX 42UL /*!<DMA Connect to I2C2_TX \hideinitializer */ 117 #define PDMA_I2C2_RX 43UL /*!<DMA Connect to I2C2_RX \hideinitializer */ 118 #define PDMA_I2S0_TX 44UL /*!<DMA Connect to I2S0_TX \hideinitializer */ 119 #define PDMA_I2S0_RX 45UL /*!<DMA Connect to I2S0_RX \hideinitializer */ 120 #define PDMA_TMR0 46UL /*!<DMA Connect to TMR0 \hideinitializer */ 121 #define PDMA_TMR1 47UL /*!<DMA Connect to TMR1 \hideinitializer */ 122 #define PDMA_TMR2 48UL /*!<DMA Connect to TMR2 \hideinitializer */ 123 #define PDMA_TMR3 49UL /*!<DMA Connect to TMR3 \hideinitializer */ 124 #define PDMA_EADC0_RX 50UL /*!<DMA Connect to EADC0_RX \hideinitializer */ 125 #define PDMA_DAC0_TX 51UL /*!<DMA Connect to DAC0_TX \hideinitializer */ 126 #define PDMA_DAC1_TX 52UL /*!<DMA Connect to DAC1_TX \hideinitializer */ 127 #define PDMA_EPWM0_CH0_TX 53UL /*!<DMA Connect to EPWM0_CH0_TX \hideinitializer */ 128 #define PDMA_EPWM0_CH1_TX 54UL /*!<DMA Connect to EPWM0_CH1_TX \hideinitializer */ 129 #define PDMA_EPWM0_CH2_TX 55UL /*!<DMA Connect to EPWM0_CH2_TX \hideinitializer */ 130 #define PDMA_EPWM0_CH3_TX 56UL /*!<DMA Connect to EPWM0_CH3_TX \hideinitializer */ 131 #define PDMA_EPWM0_CH4_TX 57UL /*!<DMA Connect to EPWM0_CH4_TX \hideinitializer */ 132 #define PDMA_EPWM0_CH5_TX 58UL /*!<DMA Connect to EPWM0_CH5_TX \hideinitializer */ 133 #define PDMA_EPWM1_CH0_TX 59UL /*!<DMA Connect to EPWM1_CH0_TX \hideinitializer */ 134 #define PDMA_EPWM1_CH1_TX 60UL /*!<DMA Connect to EPWM1_CH1_TX \hideinitializer */ 135 #define PDMA_EPWM1_CH2_TX 61UL /*!<DMA Connect to EPWM1_CH2_TX \hideinitializer */ 136 #define PDMA_EPWM1_CH3_TX 62UL /*!<DMA Connect to EPWM1_CH3_TX \hideinitializer */ 137 #define PDMA_EPWM1_CH4_TX 63UL /*!<DMA Connect to EPWM1_CH4_TX \hideinitializer */ 138 #define PDMA_EPWM1_CH5_TX 64UL /*!<DMA Connect to EPWM1_CH5_TX \hideinitializer */ 139 #define PDMA_UART6_TX 66UL /*!<DMA Connect to UART6_TX \hideinitializer */ 140 #define PDMA_UART6_RX 67UL /*!<DMA Connect to UART6_RX \hideinitializer */ 141 #define PDMA_UART7_TX 68UL /*!<DMA Connect to UART7_TX \hideinitializer */ 142 #define PDMA_UART7_RX 69UL /*!<DMA Connect to UART7_RX \hideinitializer */ 143 #define PDMA_EADC1_RX 70UL /*!<DMA Connect to EADC1_RX \hideinitializer */ 144 #define PDMA_ACMP0 71UL /*!<DMA Connect to ACMP0 \hideinitializer */ 145 #define PDMA_ACMP1 72UL /*!<DMA Connect to ACMP1 \hideinitializer */ 146 #define PDMA_PSIO_TX 73UL /*!<DMA Connect to PSIO_TX \hideinitializer */ 147 #define PDMA_PSIO_RX 74UL /*!<DMA Connect to PSIO_RX \hideinitializer */ 148 #define PDMA_I2C3_TX 75UL /*!<DMA Connect to I2C3_TX \hideinitializer */ 149 #define PDMA_I2C3_RX 76UL /*!<DMA Connect to I2C3_RX \hideinitializer */ 150 #define PDMA_I2C4_TX 77UL /*!<DMA Connect to I2C4_TX \hideinitializer */ 151 #define PDMA_I2C4_RX 78UL /*!<DMA Connect to I2C4_RX \hideinitializer */ 152 #define PDMA_I2S1_TX 79UL /*!<DMA Connect to I2S1_TX \hideinitializer */ 153 #define PDMA_I2S1_RX 80UL /*!<DMA Connect to I2S1_RX \hideinitializer */ 154 #define PDMA_EINT0 81UL /*!<DMA Connect to EINT0 \hideinitializer */ 155 #define PDMA_EINT1 82UL /*!<DMA Connect to EINT1 \hideinitializer */ 156 #define PDMA_EINT2 83UL /*!<DMA Connect to EINT2 \hideinitializer */ 157 #define PDMA_EINT3 84UL /*!<DMA Connect to EINT3 \hideinitializer */ 158 #define PDMA_EINT4 85UL /*!<DMA Connect to EINT4 \hideinitializer */ 159 #define PDMA_EINT5 86UL /*!<DMA Connect to EINT5 \hideinitializer */ 160 #define PDMA_EINT6 87UL /*!<DMA Connect to EINT6 \hideinitializer */ 161 #define PDMA_EINT7 88UL /*!<DMA Connect to EINT7 \hideinitializer */ 162 #define PDMA_UART8_TX 89UL /*!<DMA Connect to UART8_TX \hideinitializer */ 163 #define PDMA_UART8_RX 90UL /*!<DMA Connect to UART8_RX \hideinitializer */ 164 #define PDMA_UART9_TX 91UL /*!<DMA Connect to UART9_TX \hideinitializer */ 165 #define PDMA_UART9_RX 92UL /*!<DMA Connect to UART9_RX \hideinitializer */ 166 #define PDMA_EADC2_RX 93UL /*!<DMA Connect to EADC2_RX \hideinitializer */ 167 #define PDMA_ACMP2 94UL /*!<DMA Connect to ACMP2 \hideinitializer */ 168 #define PDMA_ACMP3 95UL /*!<DMA Connect to ACMP3 \hideinitializer */ 169 #define PDMA_SPI4_TX 96UL /*!<DMA Connect to SPI4_TX \hideinitializer */ 170 #define PDMA_SPI4_RX 97UL /*!<DMA Connect to SPI4_RX \hideinitializer */ 171 #define PDMA_SPI5_TX 98UL /*!<DMA Connect to SPI5_TX \hideinitializer */ 172 #define PDMA_SPI5_RX 99UL /*!<DMA Connect to SPI5_RX \hideinitializer */ 173 #define PDMA_SPI6_TX 100UL /*!<DMA Connect to SPI6_TX \hideinitializer */ 174 #define PDMA_SPI6_RX 101UL /*!<DMA Connect to SPI6_RX \hideinitializer */ 175 #define PDMA_SPI7_TX 102UL /*!<DMA Connect to SPI7_TX \hideinitializer */ 176 #define PDMA_SPI7_RX 103UL /*!<DMA Connect to SPI7_RX \hideinitializer */ 177 #define PDMA_SPI8_TX 104UL /*!<DMA Connect to SPI8_TX \hideinitializer */ 178 #define PDMA_SPI8_RX 105UL /*!<DMA Connect to SPI8_RX \hideinitializer */ 179 #define PDMA_SPI9_TX 106UL /*!<DMA Connect to SPI9_TX \hideinitializer */ 180 #define PDMA_SPI9_RX 107UL /*!<DMA Connect to SPI9_RX \hideinitializer */ 181 #define PDMA_SPI10_TX 108UL /*!<DMA Connect to SPI10_TX \hideinitializer */ 182 #define PDMA_SPI10_RX 109UL /*!<DMA Connect to SPI10_RX \hideinitializer */ 183 #define PDMA_BMC_G0_TX 110UL /*!<DMA Connect to BMC_G0_TX \hideinitializer */ 184 #define PDMA_BMC_G1_TX 111UL /*!<DMA Connect to BMC_G1_TX \hideinitializer */ 185 #define PDMA_BMC_G2_TX 112UL /*!<DMA Connect to BMC_G2_TX \hideinitializer */ 186 #define PDMA_BMC_G3_TX 113UL /*!<DMA Connect to BMC_G3_TX \hideinitializer */ 187 #define PDMA_BMC_G4_TX 114UL /*!<DMA Connect to BMC_G4_TX \hideinitializer */ 188 #define PDMA_BMC_G5_TX 115UL /*!<DMA Connect to BMC_G5_TX \hideinitializer */ 189 #define PDMA_BMC_G6_TX 116UL /*!<DMA Connect to BMC_G6_TX \hideinitializer */ 190 #define PDMA_BMC_G7_TX 117UL /*!<DMA Connect to BMC_G7_TX \hideinitializer */ 191 192 /*---------------------------------------------------------------------------------------------------------*/ 193 /* Interrupt Type Constant Definitions */ 194 /*---------------------------------------------------------------------------------------------------------*/ 195 #define PDMA_INT_TRANS_DONE 0x00000000UL /*!<Transfer Done Interrupt \hideinitializer */ 196 #define PDMA_INT_TEMPTY 0x00000001UL /*!<Table Empty Interrupt \hideinitializer */ 197 #define PDMA_INT_TIMEOUT 0x00000002UL /*!<Timeout Interrupt \hideinitializer */ 198 #define PDMA_INT_ALIGN 0x00000003UL /*!<Transfer Alignment Interrupt \hideinitializer */ 199 200 201 /*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */ 202 203 /** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions 204 @{ 205 */ 206 207 /** 208 * @brief Get PDMA Interrupt Status 209 * 210 * @param[in] pdma The pointer of the specified PDMA module 211 * 212 * @return None 213 * 214 * @details This macro gets the interrupt status. 215 * \hideinitializer 216 */ 217 #define PDMA_GET_INT_STATUS(pdma) ((uint32_t)((pdma)->INTSTS)) 218 219 /** 220 * @brief Get Transfer Done Interrupt Status 221 * 222 * @param[in] pdma The pointer of the specified PDMA module 223 * 224 * @return None 225 * 226 * @details Get the transfer done Interrupt status. 227 * \hideinitializer 228 */ 229 #define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS)) 230 231 /** 232 * @brief Clear Transfer Done Interrupt Status 233 * 234 * @param[in] pdma The pointer of the specified PDMA module 235 * 236 * @param[in] u32Mask The channel mask 237 * 238 * @return None 239 * 240 * @details Clear the transfer done Interrupt status. 241 * \hideinitializer 242 */ 243 #define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask))) 244 245 /** 246 * @brief Get Target Abort Interrupt Status 247 * 248 * @param[in] pdma The pointer of the specified PDMA module 249 * 250 * @return None 251 * 252 * @details Get the target abort Interrupt status. 253 * \hideinitializer 254 */ 255 #define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS)) 256 257 /** 258 * @brief Clear Target Abort Interrupt Status 259 * 260 * @param[in] pdma The pointer of the specified PDMA module 261 * 262 * @param[in] u32Mask The channel mask 263 * 264 * @return None 265 * 266 * @details Clear the target abort Interrupt status. 267 * \hideinitializer 268 */ 269 #define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask))) 270 271 /** 272 * @brief Get Alignment Interrupt Status 273 * 274 * @param[in] pdma The pointer of the specified PDMA module 275 * 276 * @return None 277 * 278 * @details Get Alignment Interrupt status. 279 * \hideinitializer 280 */ 281 #define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN)) 282 283 /** 284 * @brief Clear Alignment Interrupt Status 285 * 286 * @param[in] pdma The pointer of the specified PDMA module 287 * @param[in] u32Mask The channel mask 288 * 289 * @return None 290 * 291 * @details Clear the Alignment Interrupt status. 292 * \hideinitializer 293 */ 294 #define PDMA_CLR_ALIGN_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask))) 295 296 /** 297 * @brief Clear Timeout Interrupt Status 298 * 299 * @param[in] pdma The pointer of the specified PDMA module 300 * @param[in] u32Ch The selected channel 301 * 302 * @return None 303 * 304 * @details Clear the selected channel timeout interrupt status. 305 * \hideinitializer 306 */ 307 #define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1UL << ((u32Ch) + 8UL)))) 308 309 /** 310 * @brief Check Channel Status 311 * 312 * @param[in] pdma The pointer of the specified PDMA module 313 * @param[in] u32Ch The selected channel 314 * 315 * @retval 0 Idle state 316 * @retval 1 Busy state 317 * 318 * @details Check the selected channel is busy or not. 319 * \hideinitializer 320 */ 321 #define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1UL << (u32Ch)))? 1 : 0) 322 323 /** 324 * @brief Set Source Address 325 * 326 * @param[in] pdma The pointer of the specified PDMA module 327 * @param[in] u32Ch The selected channel 328 * @param[in] u32Addr The selected address 329 * 330 * @return None 331 * 332 * @details This macro set the selected channel source address. 333 * \hideinitializer 334 */ 335 #define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr))) 336 337 /** 338 * @brief Set Destination Address 339 * 340 * @param[in] pdma The pointer of the specified PDMA module 341 * @param[in] u32Ch The selected channel 342 * @param[in] u32Addr The selected address 343 * 344 * @return None 345 * 346 * @details This macro set the selected channel destination address. 347 * \hideinitializer 348 */ 349 #define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr))) 350 351 /** 352 * @brief Set Transfer Count 353 * 354 * @param[in] pdma The pointer of the specified PDMA module 355 * @param[in] u32Ch The selected channel 356 * @param[in] u32TransCount Transfer Count 357 * 358 * @return None 359 * 360 * @details This macro set the selected channel transfer count. 361 * \hideinitializer 362 */ 363 #define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos))) 364 365 /** 366 * @brief Set Scatter-gather descriptor Address 367 * 368 * @param[in] pdma The pointer of the specified PDMA module 369 * @param[in] u32Ch The selected channel 370 * @param[in] u32Addr The descriptor address 371 * 372 * @return None 373 * 374 * @details This macro set the selected channel scatter-gather descriptor address. 375 * \hideinitializer 376 */ 377 #define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].NEXT = (u32Addr) - ((pdma)->SCATBA))) 378 379 /** 380 * @brief Stop the channel 381 * 382 * @param[in] pdma The pointer of the specified PDMA module 383 * @param[in] u32Ch The selected channel 384 * 385 * @return None 386 * 387 * @details This macro stop the selected channel. 388 * \hideinitializer 389 */ 390 #define PDMA_STOP(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) 391 392 /** 393 * @brief Pause the channel 394 * 395 * @param[in] pdma The pointer of the specified PDMA module 396 * @param[in] u32Ch The selected channel 397 * 398 * @return None 399 * 400 * @details This macro pause the selected channel. 401 */ 402 #define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) 403 404 /** 405 * @brief Reset the channel 406 * 407 * @param[in] pdma The pointer of the specified PDMA module 408 * @param[in] u32Ch The selected channel 409 * 410 * @return None 411 * 412 * @details This macro reset the selected channel. 413 */ 414 #define PDMA_RESET(pdma, u32Ch) ((uint32_t)((pdma)->CHRST = (1UL << (u32Ch)))) 415 416 /*---------------------------------------------------------------------------------------------------------*/ 417 /* Define PDMA functions prototype */ 418 /*---------------------------------------------------------------------------------------------------------*/ 419 void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask); 420 void PDMA_Close(PDMA_T * pdma); 421 void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); 422 void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); 423 void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); 424 void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); 425 void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask); 426 void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask); 427 void PDMA_SetTimeOut(PDMA_T * pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); 428 void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch); 429 void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); 430 void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); 431 void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); 432 void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount); 433 434 435 /*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ 436 437 /*@}*/ /* end of group PDMA_Driver */ 438 439 /*@}*/ /* end of group Standard_Driver */ 440 441 #ifdef __cplusplus 442 } 443 #endif 444 445 #endif /* __PDMA_H__ */ 446 447
