1 /****************************************************************************//**
2 * @file i2c.h
3 * @version V1.00
4 * @brief M2L31 series I2C driver header file
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __I2C_H__
10 #define __I2C_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup I2C_Driver I2C Driver
23 @{
24 */
25
26 /** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
27 @{
28 */
29
30 #define I2C_TIMEOUT_ERR (-1L) /*!< I2C operation abort due to timeout error \hideinitializer */
31
32 /*---------------------------------------------------------------------------------------------------------*/
33 /* I2C_CTL constant definitions. */
34 /*---------------------------------------------------------------------------------------------------------*/
35 #define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits \hideinitializer */
36 #define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits \hideinitializer */
37 #define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits \hideinitializer */
38 #define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits \hideinitializer */
39 #define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit \hideinitializer */
40 #define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits \hideinitializer */
41 #define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
42 #define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
43 #define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit \hideinitializer */
44
45 /*---------------------------------------------------------------------------------------------------------*/
46 /* I2C GCMode constant definitions. */
47 /*---------------------------------------------------------------------------------------------------------*/
48 #define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode \hideinitializer */
49 #define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode \hideinitializer */
50
51 /*---------------------------------------------------------------------------------------------------------*/
52 /* I2C SMBUS constant definitions. */
53 /*---------------------------------------------------------------------------------------------------------*/
54 #define I2C_SMBH_ENABLE 1 /*!< Enable SMBus Host Mode enable \hideinitializer */
55 #define I2C_SMBD_ENABLE 0 /*!< Enable SMBus Device Mode enable \hideinitializer */
56 #define I2C_PECTX_ENABLE 1 /*!< Enable SMBus Packet Error Check Transmit function \hideinitializer */
57 #define I2C_PECTX_DISABLE 0 /*!< Disable SMBus Packet Error Check Transmit function \hideinitializer */
58
59 /*---------------------------------------------------------------------------------------------------------*/
60 /* I2C Data Phase Bit Count constant definitions. */
61 /*---------------------------------------------------------------------------------------------------------*/
62 #define I2C_DATA_PHASE_BIT_6 (0x1UL << I2C_CTL0_DPBITSEL_Pos) /*!< Setting data phase bit count to 6 bit \hideinitializer */
63 #define I2C_DATA_PHASE_BIT_7 (0x2UL << I2C_CTL0_DPBITSEL_Pos) /*!< Setting data phase bit count to 7 bit \hideinitializer */
64 #define I2C_DATA_PHASE_BIT_8 (0x3UL << I2C_CTL0_DPBITSEL_Pos) /*!< Setting data phase bit count to 8 bit \hideinitializer */
65
66 /*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
67
68 extern int32_t g_I2C_i32ErrCode;
69
70 /** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
71 @{
72 */
73 /**
74 * @brief The macro is used to set I2C bus condition at One Time
75 *
76 * @param[in] i2c Specify I2C port
77 * @param[in] u8Ctrl A byte writes to I2C control register
78 *
79 * @return None
80 *
81 * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
82 * \hideinitializer
83 */
84 #define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3C) | (u8Ctrl))
85
86 /**
87 * @brief The macro is used to set START condition of I2C Bus
88 *
89 * @param[in] i2c Specify I2C port
90 *
91 * @return None
92 *
93 * @details Set the I2C bus START condition in I2C_CTL register.
94 * \hideinitializer
95 */
96 #define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 | I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
97
98 /**
99 * @brief The macro is used to wait I2C bus status get ready
100 *
101 * @param[in] i2c Specify I2C port
102 *
103 * @return None
104 *
105 * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
106 * \hideinitializer
107 */
108 #define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
109
110 /**
111 * @brief The macro is used to Read I2C Bus Data Register
112 *
113 * @param[in] i2c Specify I2C port
114 *
115 * @return A byte of I2C data register
116 *
117 * @details I2C controller read data from bus and save it in I2C_DAT register.
118 * \hideinitializer
119 */
120 #define I2C_GET_DATA(i2c) ((i2c)->DAT)
121
122 /**
123 * @brief Write a Data to I2C Data Register
124 *
125 * @param[in] i2c Specify I2C port
126 * @param[in] u8Data A byte that writes to data register
127 *
128 * @return None
129 *
130 * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
131 * \hideinitializer
132 */
133 #define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
134
135 /**
136 * @brief Get I2C Bus status code
137 *
138 * @param[in] i2c Specify I2C port
139 *
140 * @return I2C status code
141 *
142 * @details To get this status code to monitor I2C bus event.
143 * \hideinitializer
144 */
145 #define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
146
147 /**
148 * @brief Get Time-out flag from I2C Bus
149 *
150 * @param[in] i2c Specify I2C port
151 *
152 * @retval 0 I2C Bus time-out is not happened
153 * @retval 1 I2C Bus time-out is happened
154 *
155 * @details When I2C bus occurs time-out event, the time-out flag will be set.
156 * \hideinitializer
157 */
158 #define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
159
160 /**
161 * @brief To get wake-up flag from I2C Bus
162 *
163 * @param[in] i2c Specify I2C port
164 *
165 * @retval 0 Chip is not woken-up from power-down mode
166 * @retval 1 Chip is woken-up from power-down mode
167 *
168 * @details I2C bus occurs wake-up event, wake-up flag will be set.
169 * \hideinitializer
170 */
171 #define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
172
173 /**
174 * @brief To clear wake-up flag
175 *
176 * @param[in] i2c Specify I2C port
177 *
178 * @return None
179 *
180 * @details If wake-up flag is set, use this macro to clear it.
181 * \hideinitializer
182 */
183 #define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
184
185 /**
186 * @brief To get wake-up address frame ACK done flag from I2C Bus
187 *
188 * @param[in] i2c Specify I2C port
189 *
190 * @retval 0 The ACK bit cycle of address match frame is not done
191 * @retval 1 The ACK bit cycle of address match frame is done in power-down
192 *
193 * @details I2C bus occurs wake-up event and address frame ACK is done, this flag will be set.
194 * \hideinitializer
195 */
196 #define I2C_GET_WAKEUP_DONE(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKAKDONE_Msk) == I2C_WKSTS_WKAKDONE_Msk ? 1 : 0)
197
198 /**
199 * @brief To clear address frame ACK done flag
200 *
201 * @param[in] i2c Specify I2C port
202 *
203 * @return None
204 *
205 * @details If wake-up done is set, use this macro to clear it.
206 * \hideinitializer
207 */
208 #define I2C_CLEAR_WAKEUP_DONE(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKAKDONE_Msk)
209
210 /**
211 * @brief To get read/write status bit in address wakeup frame
212 *
213 * @param[in] i2c Specify I2C port
214 *
215 * @retval 0 Write command be record on the address match wakeup frame
216 * @retval 1 Read command be record on the address match wakeup frame.
217 *
218 * @details I2C bus occurs wake-up event and address frame is received, this bit will record read/write status.
219 * \hideinitializer
220 */
221 #define I2C_GET_WAKEUP_WR_STATUS(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WRSTSWK_Msk) == I2C_WKSTS_WRSTSWK_Msk ? 1 : 0)
222
223 /**
224 * @brief To get SMBus Status
225 *
226 * @param[in] i2c Specify I2C port
227 *
228 * @return SMBus status
229 *
230 * @details To get the Bus Management status of I2C_BUSSTS register
231 * \hideinitializer
232 *
233 */
234 #define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
235
236 /**
237 * @brief Get SMBus CRC value
238 *
239 * @param[in] i2c Specify I2C port
240 *
241 * @return Packet error check byte value
242 *
243 * @details The CRC check value after a transmission or a reception by count by using CRC8
244 * \hideinitializer
245 */
246 #define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
247
248 /**
249 * @brief Set SMBus Bytes number of Transmission or reception
250 *
251 * @param[in] i2c Specify I2C port
252 * @param[in] u32PktSize Transmit / Receive bytes
253 *
254 * @return None
255 *
256 * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
257 * \hideinitializer
258 */
259 #define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
260
261 /**
262 * @brief Enable SMBus Alert function
263 *
264 * @param[in] i2c Specify I2C port
265 *
266 * @return None
267 *
268 * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
269 * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
270 * \hideinitializer
271 */
272 #define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
273
274 /**
275 * @brief Disable SMBus Alert pin function
276 *
277 * @param[in] i2c Specify I2C port
278 *
279 * @return None
280 *
281 * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
282 * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
283 * \hideinitializer
284 */
285 #define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
286
287 /**
288 * @brief Set SMBus SUSCON pin is output mode
289 *
290 * @param[in] i2c Specify I2C port
291 *
292 * @return None
293 *
294 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
295 *
296 * \hideinitializer
297 */
298 #define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
299
300 /**
301 * @brief Set SMBus SUSCON pin is input mode
302 *
303 * @param[in] i2c Specify I2C port
304 *
305 * @return None
306 *
307 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
308 *
309 * \hideinitializer
310 */
311 #define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
312
313 /**
314 * @brief Set SMBus SUSCON pin output high state
315 *
316 * @param[in] i2c Specify I2C port
317 *
318 * @return None
319 *
320 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
321 * \hideinitializer
322 */
323 #define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
324
325
326 /**
327 * @brief Set SMBus SUSCON pin output low state
328 *
329 * @param[in] i2c Specify I2C port
330 *
331 * @return None
332 *
333 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
334 * \hideinitializer
335 */
336 #define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
337
338 /**
339 * @brief Enable SMBus Acknowledge control by manual
340 *
341 * @param[in] i2c Specify I2C port
342 *
343 * @return None
344 *
345 * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
346 * \hideinitializer
347 */
348 #define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
349
350 /**
351 * @brief Disable SMBus Acknowledge control by manual
352 *
353 * @param[in] i2c Specify I2C port
354 *
355 * @return None
356 *
357 * @details Disable acknowledge response control by user.
358 * \hideinitializer
359 */
360 #define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
361
362 /**
363 * @brief Enable SMBus Acknowledge manual interrupt
364 *
365 * @param[in] i2c Specify I2C port
366 *
367 * @return None
368 *
369 * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
370 * \hideinitializer
371 */
372 #define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
373
374 /**
375 * @brief Disable SMBus Acknowledge manual interrupt
376 *
377 * @param[in] i2c Specify I2C port
378 *
379 * @return None
380 *
381 * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
382 * \hideinitializer
383 */
384 #define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
385
386 /**
387 * @brief Enable SMBus PEC clear at REPEAT START
388 *
389 * @param[in] i2c Specify I2C port
390 *
391 * @return None
392 *
393 * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.
394 * \hideinitializer
395 */
396 #define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
397
398 /**
399 * @brief Disable SMBus PEC clear at Repeat START
400 *
401 * @param[in] i2c Specify I2C port
402 *
403 * @return None
404 *
405 * @details This function is used to disable the condition of Repeat START can clear the PEC calculation.
406 * \hideinitializer
407 */
408 #define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
409
410 /**
411 * @brief Enable RX PDMA function.
412 * @param[in] i2c The pointer of the specified I2C module.
413 * @return None.
414 * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
415 * \hideinitializer
416 */
417 #define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
418
419 /**
420 * @brief Enable TX PDMA function.
421 * @param[in] i2c The pointer of the specified I2C module.
422 * @return None.
423 * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
424 * \hideinitializer
425 */
426 #define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
427
428 /**
429 * @brief Disable RX PDMA transfer.
430 * @param[in] i2c The pointer of the specified I2C module.
431 * @return None.
432 * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
433 * \hideinitializer
434 */
435 #define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
436
437 /**
438 * @brief Disable TX PDMA transfer.
439 * @param[in] i2c The pointer of the specified I2C module.
440 * @return None.
441 * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
442 * \hideinitializer
443 */
444 #define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
445
446 /**
447 * @brief Enable PDMA stretch function.
448 * @param[in] i2c The pointer of the specified I2C module.
449 * @return None.
450 * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
451 * \hideinitializer
452 */
453 #define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
454
455 /**
456 * @brief Disable PDMA stretch function.
457 * @param[in] i2c The pointer of the specified I2C module.
458 * @return None.
459 * @details I2C will send STOP after PDMA transfers done automatically.
460 * \hideinitializer
461 */
462 #define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
463
464 /**
465 * @brief Reset PDMA function.
466 * @param[in] i2c The pointer of the specified I2C module.
467 * @return None.
468 * @details I2C PDMA engine will be reset after this function is called.
469 * \hideinitializer
470 */
471 #define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
472
473 /*---------------------------------------------------------------------------------------------------------*/
474 /* inline functions */
475 /*---------------------------------------------------------------------------------------------------------*/
476
477 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
478 __STATIC_INLINE void I2C_STOP(I2C_T *i2c);
479
480 /**
481 * @brief The macro is used to set STOP condition of I2C Bus
482 *
483 * @param[in] i2c Specify I2C port
484 *
485 * @return None
486 *
487 * @details Set the I2C bus STOP condition in I2C_CTL register.
488 */
I2C_STOP(I2C_T * i2c)489 __STATIC_INLINE void I2C_STOP(I2C_T *i2c)
490 {
491 uint32_t u32TimeOutCount = SystemCoreClock;
492
493 (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);
494 while(i2c->CTL0 & I2C_CTL0_STO_Msk)
495 {
496 u32TimeOutCount--;
497 if(u32TimeOutCount == 0) break;
498 }
499 }
500
501 void I2C_ClearTimeoutFlag(I2C_T *i2c);
502 void I2C_Close(I2C_T *i2c);
503 void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
504 void I2C_DisableInt(I2C_T *i2c);
505 void I2C_EnableInt(I2C_T *i2c);
506 uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
507 uint32_t I2C_GetIntFlag(I2C_T *i2c);
508 uint32_t I2C_GetStatus(I2C_T *i2c);
509 uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
510 uint8_t I2C_GetData(I2C_T *i2c);
511 void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
512 void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
513 uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
514 void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
515 void I2C_DisableTimeout(I2C_T *i2c);
516 void I2C_EnableWakeup(I2C_T *i2c);
517 void I2C_DisableWakeup(I2C_T *i2c);
518 void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
519 void I2C_EnableTwoBufferMode(I2C_T *i2c, uint32_t u32BitCount);
520 void I2C_DisableTwoBufferMode(I2C_T *i2c);
521 uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data);
522 uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);
523 uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
524 uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);
525 uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
526 uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);
527 uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
528 uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);
529 uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
530 uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);
531 uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
532 uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);
533 uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
534 void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag);
535 void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
536 void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
537 void I2C_SMBusClose(I2C_T *i2c);
538 void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
539 uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
540 void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
541 void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
542 void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
543
544 /*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
545
546 /*@}*/ /* end of group I2C_Driver */
547
548 /*@}*/ /* end of group Standard_Driver */
549
550 #ifdef __cplusplus
551 }
552 #endif
553
554 #endif
555
556 /*** (C) COPYRIGHT 2023 Nuvoton Technology Corp. ***/
557
