1 /**************************************************************************//** 2 * @file hbi.h 3 * @version V1.00 4 * @brief M460 series HBI driver header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __HBI_H__ 10 #define __HBI_H__ 11 12 /*---------------------------------------------------------------------------------------------------------*/ 13 /* Include related headers */ 14 /*---------------------------------------------------------------------------------------------------------*/ 15 16 #ifdef __cplusplus 17 extern "C" 18 { 19 #endif 20 21 22 /** @addtogroup Standard_Driver Standard Driver 23 @{ 24 */ 25 26 /** @addtogroup HyperBus Interface Driver 27 @{ 28 */ 29 30 31 /** @addtogroup HBI_EXPORTED_CONSTANTS HBI Exported Constants 32 @{ 33 */ 34 35 /*---------------------------------------------------------------------------------------------------------*/ 36 /* HyperRAM memory mapping address*/ 37 #define HYPERRAM_BASE 0x80000000 38 /*---------------------------------------------------------------------------------------------------------*/ 39 /* HyperRAM Register Space constant definitions 40 Register Space Range: 41 0x0000_0000 = Identification Register 0 42 0x0000_0002 = Identification Register 1 43 0x0000_1000 = Configuration Register 0 44 0x0000_1002 = Configuration Register 1 45 */ 46 #define HYPERRAM_ID_REG0 0x00000000 47 #define HYPERRAM_ID_REG1 0x00000002 48 #define HYPERRAM_CONFIG_REG0 0x00001000 49 #define HYPERRAM_CONFIG_REG1 0x00001002 50 /*---------------------------------------------------------------------------------------------------------*/ 51 /* HBI_CMD constant definitions 52 0001 = Reset HyperRAM 53 0010 = Read HyperRAM regsiter (16-Bit, Read Data[15:0] 54 0101 = Exit From Hybrid Sleep and deep power down 55 0111 = Write HyperRAM regsiter (16-Bit, Write Data[15:0] 56 1000 = Read 2 Bytes (Read Data[15:0]) from HyperRAM 57 1001 = Read 4 Bytes (Read Data[31:0]) from HyperRAM 58 1100 = Write 1 Byte (Write Data[7:0]) to HyperRAM 59 1101 = Write 2 Bytes (Write Data[15:0]) to HyperRAM 60 1110 = Write 3 Byte (Write Data[23:0]) to HyperRAM 61 1111 = Write 4 Byte (Write Data[31:0]) to HyperRAM 62 */ 63 /*---------------------------------------------------------------------------------------------------------*/ 64 #define HBI_CMD_RESET_HRAM 0x1 65 #define HBI_CMD_READ_HRAM_REGISTER 0x2 66 #define HBI_CMD_EXIT_HS_PD 0x5 67 #define HBI_CMD_WRITE_HRAM_REGISTER 0x7 68 #define HBI_CMD_READ_HRAM_2_BYTE 0x8 69 #define HBI_CMD_READ_HRAM_4_BYTE 0x9 70 #define HBI_CMD_WRITE_HRAM_1_BYTE 0xC 71 #define HBI_CMD_WRITE_HRAM_2_BYTE 0xD 72 #define HBI_CMD_WRITE_HRAM_3_BYTE 0xE 73 #define HBI_CMD_WRITE_HRAM_4_BYTE 0xF 74 #define HBI_CMD_HRAM_IDLE 0x0 75 /*---------------------------------------------------------------------------------------------------------*/ 76 /* HBI_CONFIG: Chip Select Setup Time to Next CK Rising Edge constant definitions 77 00 = 1.5 HCLK cycles. 78 01 = 2.5 HCLK cycles. 79 10 = 3.5 HCLK cycles. 80 11 = 4.5 HCLK cycles. 81 */ 82 /*---------------------------------------------------------------------------------------------------------*/ 83 #define HBI_CONFIG_CSST_1_5_HCLK (0x0 << HBI_CONFIG_CSST_Pos) 84 #define HBI_CONFIG_CSST_2_5_HCLK (0x1 << HBI_CONFIG_CSST_Pos) 85 #define HBI_CONFIG_CSST_3_5_HCLK (0x2 << HBI_CONFIG_CSST_Pos) 86 #define HBI_CONFIG_CSST_4_5_HCLK (0x3 << HBI_CONFIG_CSST_Pos) 87 /*---------------------------------------------------------------------------------------------------------*/ 88 /* HBI_CONFIG: Initial Access Time constant definitions 89 0000 = 5 HCLK cycles. 90 0001 = 6 HCLK cycles. 91 0010 = 7 HCLK cycles. 92 1110 = 3 HCLK cycles. 93 1111 = 4 HCLK cycles. 94 */ 95 /*---------------------------------------------------------------------------------------------------------*/ 96 #define HBI_CONFIG_ACCT_5_CK (0x0 << HBI_CONFIG_ACCT_Pos) 97 #define HBI_CONFIG_ACCT_6_CK (0x1 << HBI_CONFIG_ACCT_Pos) 98 #define HBI_CONFIG_ACCT_7_CK (0x2 << HBI_CONFIG_ACCT_Pos) 99 #define HBI_CONFIG_ACCT_3_CK (0xE << HBI_CONFIG_ACCT_Pos) 100 #define HBI_CONFIG_ACCT_4_CK (0xF << HBI_CONFIG_ACCT_Pos) 101 /*---------------------------------------------------------------------------------------------------------*/ 102 /* HBI_CONFIG: Chip Select Hold Time After CK Falling Edge constant definitions 103 00 = 0.5 HCLK cycles. 104 01 = 1.5 HCLK cycles. 105 10 = 2.5 HCLK cycles. 106 11 = 3.5 HCLK cycles. 107 */ 108 /*---------------------------------------------------------------------------------------------------------*/ 109 #define HBI_CONFIG_CSH_0_5_HCLK (0x0 << HBI_CONFIG_CSH_Pos) 110 #define HBI_CONFIG_CSH_1_5_HCLK (0x1 << HBI_CONFIG_CSH_Pos) 111 #define HBI_CONFIG_CSH_2_5_HCLK (0x2 << HBI_CONFIG_CSH_Pos) 112 #define HBI_CONFIG_CSH_3_5_HCLK (0x3 << HBI_CONFIG_CSH_Pos) 113 /*---------------------------------------------------------------------------------------------------------*/ 114 /* HBI_CONFIG: Burst Group Size constant definitions 115 00 = 128 Bytes. 116 01 = 64 Bytes. 117 10 = 16 Bytes. 118 11 = 32 Bytes. 119 */ 120 /*---------------------------------------------------------------------------------------------------------*/ 121 #define HBI_CONFIG_BGSIZE_128 (0x0 << HBI_CONFIG_BGSIZE_Pos) 122 #define HBI_CONFIG_BGSIZE_64 (0x1 << HBI_CONFIG_BGSIZE_Pos) 123 #define HBI_CONFIG_BGSIZE_16 (0x2 << HBI_CONFIG_BGSIZE_Pos) 124 #define HBI_CONFIG_BGSIZE_32 (0x3 << HBI_CONFIG_BGSIZE_Pos) 125 /*---------------------------------------------------------------------------------------------------------*/ 126 /* HBI_CONFIG: Endian Condition on the Hyper Bus Data Pipe constant definitions 127 0 = Little-Endian. 128 1 = Big-Endian. 129 */ 130 /*---------------------------------------------------------------------------------------------------------*/ 131 #define HBI_CONFIG_LITTLE_ENDIAN (0x0 << HBI_CONFIG_ENDIAN_Pos) 132 #define HBI_CONFIG_BIG_ENDIAN (0x1 << HBI_CONFIG_ENDIAN_Pos) 133 /*---------------------------------------------------------------------------------------------------------*/ 134 /* HBI_CONFIG: Hyper Bus Clock Divider constant definitions 135 0 = Hyper Bus Clock rate is HCLK/2. 136 1 = Hyper Bus Clock rate is HCLK/4. 137 */ 138 /*---------------------------------------------------------------------------------------------------------*/ 139 #define HBI_CONFIG_CKDIV_HCLK_DIV2 (0x0 << HBI_CONFIG_CKDIV_Pos) 140 #define HBI_CONFIG_CKDIV_HCLK_DIV4 (0x1 << HBI_CONFIG_CKDIV_Pos) 141 /*---------------------------------------------------------------------------------------------------------*/ 142 143 /*---------------------------------------------------------------------------------------------------------*/ 144 /* HBI Define Error Code */ 145 /*---------------------------------------------------------------------------------------------------------*/ 146 extern int32_t g_HBI_i32ErrCode; 147 #define HBI_TIMEOUT SystemCoreClock /*!< HBI time-out counter (1 second time-out) */ 148 #define HBI_OK ( 0L) /*!< HBI operation OK */ 149 #define HBI_ERR_FAIL (-1L) /*!< HBI operation failed */ 150 #define HBI_ERR_TIMEOUT (-2L) /*!< HBI operation abort due to timeout error */ 151 #define HBI_ERR_ALIGN (-3L) /*!< HBI operation aligment error */ 152 153 154 /*---------------------------------------------------------------------------------------------------------*/ 155 /* Define Macros and functions */ 156 /*---------------------------------------------------------------------------------------------------------*/ 157 /** 158 * @brief Set HBI Chip Select Setup Time to Next CK Rising Edge 159 * @param[in] u8Value Chip Select Setup Time to Next CK Rising Edge. 160 * - \ref HBI_CONFIG_CSST_1_5_HCLK : 1.5 HCLK cycles 161 * - \ref HBI_CONFIG_CSST_2_5_HCLK : 2.5 HCLK cycles 162 * - \ref HBI_CONFIG_CSST_3_5_HCLK : 3.5 HCLK cycles 163 * - \ref HBI_CONFIG_CSST_4_5_HCLK : 4.5 HCLK cycles 164 * @return None 165 * @details This macro set HBI Chip Select Setup Time to Next CK Rising Edge 166 * \hideinitializer 167 */ 168 #define HBI_CONFIG_SET_CSST(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_CSST_Msk))) | u8Value) 169 170 /** 171 * @brief Set HBI Initial Access Time 172 * @param[in] u8Value Initial Access Time. 173 * - \ref HBI_CONFIG_ACCT_5_CK : 5 CK cycles 174 * - \ref HBI_CONFIG_ACCT_6_CK : 6 CK cycles 175 * - \ref HBI_CONFIG_ACCT_7_CK : 7 CK cycles 176 * - \ref HBI_CONFIG_ACCT_3_CK : 3 CK cycles 177 * - \ref HBI_CONFIG_ACCT_4_CK : 4 CK cycles 178 * @return None 179 * @details This macro set HBI Initial Access Time 180 * \hideinitializer 181 */ 182 #define HBI_CONFIG_SET_ACCT(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_ACCT_Msk))) | u8Value) 183 184 /** 185 * @brief Set HBI Chip Select Hold Time After CK Falling Edge 186 * @param[in] u8Value Chip Select Hold Time After CK Falling Edge. 187 * - \ref HBI_CONFIG_CSH_0_5_HCLK : 0.5 HCLK cycles 188 * - \ref HBI_CONFIG_CSH_1_5_HCLK : 1.5 HCLK cycles 189 * - \ref HBI_CONFIG_CSH_2_5_HCLK : 2.5 HCLK cycles 190 * - \ref HBI_CONFIG_CSH_3_5_HCLK : 3.5 HCLK cycles 191 * @return None 192 * @details This macro set HBI Chip Select Hold Time After CK Falling Edge 193 * \hideinitializer 194 */ 195 #define HBI_CONFIG_SET_CSH(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_CSH_Msk))) | u8Value) 196 197 /** 198 * @brief Set HBI Chip Select High between Transaction 199 * @param[in] u8Value Set Chip Select High between Transaction as u8Value HCLK cycles 200 u8Value must be 1 ~ 16 201 * @return None 202 * @details This macro set HBI Chip Select High between Transaction. 203 * \hideinitializer 204 */ 205 #define HBI_CONFIG_SET_CSHI(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_CSHI_Msk))) | ((u8Value-1) << HBI_CONFIG_CSHI_Pos)) 206 207 /** 208 * @brief Set HBI Burst Group Size 209 * @param[in] u8Value Burst Group Size. 210 * - \ref HBI_CONFIG_BGSIZE_128 : 128 Bytes 211 * - \ref HBI_CONFIG_BGSIZE_64 : 64 Bytes 212 * - \ref HBI_CONFIG_BGSIZE_16 : 16 Bytes 213 * - \ref HBI_CONFIG_BGSIZE_32 : 32 Bytes 214 * @return None 215 * @details This macro set HBI Burst Group Size 216 * \hideinitializer 217 */ 218 #define HBI_CONFIG_SET_BGSIZE(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_BGSIZE_Msk))) | u8Value) 219 220 /** 221 * @brief Set HBI Endian Condition on the Hyper Bus Data Pipe 222 * @param[in] u8Value Endian Condition on the Hyper Bus Data Pipe. 223 * - \ref HBI_CONFIG_LITTLE_ENDIAN : Little-Endian 224 * - \ref HBI_CONFIG_BIG_ENDIAN : Big-Endian 225 * @return None 226 * @details This macro set HBI Endian Condition on the Hyper Bus Data Pipe 227 * \hideinitializer 228 */ 229 #define HBI_CONFIG_SET_ENDIAN(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_ENDIAN_Msk))) | u8Value) 230 231 /** 232 * @brief Set HBI Hyper Bus Clock Divider 233 * @param[in] u8Value Hyper Bus Clock Divider. 234 * - \ref HBI_CONFIG_CKDIV_HCLK_DIV2 : HCLK/2 235 * - \ref HBI_CONFIG_CKDIV_HCLK_DIV4 : HCLK/4 236 * @return None 237 * @details This macro set Hyper Bus Clock Divider 238 * \hideinitializer 239 */ 240 #define HBI_CONFIG_SET_CKDIV(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_CKDIV_Msk))) | u8Value) 241 242 /** 243 * @brief Set HBI Chip Select Maximum Low Time 244 * @param[in] u32CsMaxLT Set HBI Chip Select Maximum Low Time as u32CsMaxLT HCLK cycles. 245 u32CsMaxLT must be 1 ~ 2048 246 * @return None 247 * @details This macro set HBI Chip Select Maximum Low Time. 248 * \hideinitializer 249 */ 250 #define HBI_CONFIG_SET_CSMAXLT(u32CsMaxLT) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_CSMAXLT_Msk))) | ((u32CsMaxLT-1) << HBI_CONFIG_CSMAXLT_Pos)) 251 252 /** 253 * @brief Enable HyperBus Operation Done Interrupt 254 * @param[in] None 255 * @return None 256 * @details This macro enable HyperBus Operation Done Interrupt. 257 * \hideinitializer 258 */ 259 #define HBI_ENABLE_INT (HBI->INTEN |= HBI_INTEN_OPINTEN_Msk) 260 261 /** 262 * @brief Disable HyperBus Operation Done Interrupt 263 * @param[in] None 264 * @return None 265 * @details This macro disable HyperBus Operation Done Interrupt. 266 * \hideinitializer 267 */ 268 #define HBI_DISABLE_INT (HBI->INTEN &= ~HBI_INTEN_OPINTEN_Msk) 269 270 /////////////////// 271 /** 272 * @brief Get HyperBus Operation Done Interrupt 273 * @param[in] None 274 * @return 0 = HyperBus operation is busy. 275 * 1 = HyperBus operation is done. 276 * @details This macro Get HyperBus Operation Done Interrupt. 277 * \hideinitializer 278 */ 279 #define HBI_GET_INTSTS ((HBI->INTSTS & HBI_INTSTS_OPDONE_Msk)? 1:0) 280 281 /*---------------------------------------------------------------------------------------------------------*/ 282 /* Define Function Prototypes */ 283 /*---------------------------------------------------------------------------------------------------------*/ 284 void HBI_ResetHyperRAM(void); 285 void HBI_ExitHSAndDPD(void); 286 int32_t HBI_ReadHyperRAMReg(uint32_t u32Addr); 287 int32_t HBI_WriteHyperRAMReg(uint32_t u32Addr, uint32_t u32Value); 288 uint32_t HBI_Read2Byte(uint32_t u32Addr); 289 uint32_t HBI_Read4Byte(uint32_t u32Addr); 290 void HBI_Write1Byte(uint32_t u32Addr, uint8_t u8Data); 291 void HBI_Write2Byte(uint32_t u32Addr, uint16_t u16Data); 292 void HBI_Write3Byte(uint32_t u32Addr, uint32_t u32Data); 293 void HBI_Write4Byte(uint32_t u32Addr, uint32_t u32Data); 294 295 /*@}*/ /* end of group HBI_EXPORTED_FUNCTIONS */ 296 297 /*@}*/ /* end of group HBI_Driver */ 298 299 /*@}*/ /* end of group Standard_Driver */ 300 301 #ifdef __cplusplus 302 } 303 #endif 304 305 #endif /* __HBI_H__ */ 306
