1 /**************************************************************************//** 2 * @file epwm.h 3 * @version V1.00 4 * @brief EPWM driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EPWM_H__ 10 #define __EPWM_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup EPWM_Driver EPWM Driver 23 @{ 24 */ 25 26 /** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants 27 @{ 28 */ 29 #define EPWM_CHANNEL_NUM (6U) /*!< EPWM channel number \hideinitializer */ 30 #define EPWM_CH_0_MASK (0x1U) /*!< EPWM channel 0 mask \hideinitializer */ 31 #define EPWM_CH_1_MASK (0x2U) /*!< EPWM channel 1 mask \hideinitializer */ 32 #define EPWM_CH_2_MASK (0x4U) /*!< EPWM channel 2 mask \hideinitializer */ 33 #define EPWM_CH_3_MASK (0x8U) /*!< EPWM channel 3 mask \hideinitializer */ 34 #define EPWM_CH_4_MASK (0x10U) /*!< EPWM channel 4 mask \hideinitializer */ 35 #define EPWM_CH_5_MASK (0x20U) /*!< EPWM channel 5 mask \hideinitializer */ 36 37 /*---------------------------------------------------------------------------------------------------------*/ 38 /* Counter Type Constant Definitions */ 39 /*---------------------------------------------------------------------------------------------------------*/ 40 #define EPWM_UP_COUNTER (0U) /*!< Up counter type \hideinitializer */ 41 #define EPWM_DOWN_COUNTER (1U) /*!< Down counter type \hideinitializer */ 42 #define EPWM_UP_DOWN_COUNTER (2U) /*!< Up-Down counter type \hideinitializer */ 43 44 /*---------------------------------------------------------------------------------------------------------*/ 45 /* Aligned Type Constant Definitions */ 46 /*---------------------------------------------------------------------------------------------------------*/ 47 #define EPWM_EDGE_ALIGNED (1U) /*!< EPWM working in edge aligned type(down count) \hideinitializer */ 48 #define EPWM_CENTER_ALIGNED (2U) /*!< EPWM working in center aligned type \hideinitializer */ 49 50 /*---------------------------------------------------------------------------------------------------------*/ 51 /* Output Level Constant Definitions */ 52 /*---------------------------------------------------------------------------------------------------------*/ 53 #define EPWM_OUTPUT_NOTHING (0U) /*!< EPWM output nothing \hideinitializer */ 54 #define EPWM_OUTPUT_LOW (1U) /*!< EPWM output low \hideinitializer */ 55 #define EPWM_OUTPUT_HIGH (2U) /*!< EPWM output high \hideinitializer */ 56 #define EPWM_OUTPUT_TOGGLE (3U) /*!< EPWM output toggle \hideinitializer */ 57 58 /*---------------------------------------------------------------------------------------------------------*/ 59 /* Synchronous Start Function Control Constant Definitions */ 60 /*---------------------------------------------------------------------------------------------------------*/ 61 #define EPWM_SSCTL_SSRC_EPWM0 (0U<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 \hideinitializer */ 62 #define EPWM_SSCTL_SSRC_EPWM1 (1U<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 \hideinitializer */ 63 #define EPWM_SSCTL_SSRC_BPWM0 (2UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 \hideinitializer */ 64 #define EPWM_SSCTL_SSRC_BPWM1 (3UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 \hideinitializer */ 65 66 /*---------------------------------------------------------------------------------------------------------*/ 67 /* Trigger Source Select Constant Definitions */ 68 /*---------------------------------------------------------------------------------------------------------*/ 69 #define EPWM_TRG_ADC_EVEN_ZERO (0U) /*!< EPWM trigger ADC while counter of even channel matches zero point \hideinitializer */ 70 #define EPWM_TRG_ADC_EVEN_PERIOD (1U) /*!< EPWM trigger ADC while counter of even channel matches period point \hideinitializer */ 71 #define EPWM_TRG_ADC_EVEN_ZERO_PERIOD (2U) /*!< EPWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */ 72 #define EPWM_TRG_ADC_EVEN_COMPARE_UP (3U) /*!< EPWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */ 73 #define EPWM_TRG_ADC_EVEN_COMPARE_DOWN (4U) /*!< EPWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */ 74 #define EPWM_TRG_ADC_ODD_ZERO (5U) /*!< EPWM trigger ADC while counter of odd channel matches zero point \hideinitializer */ 75 #define EPWM_TRG_ADC_ODD_PERIOD (6U) /*!< EPWM trigger ADC while counter of odd channel matches period point \hideinitializer */ 76 #define EPWM_TRG_ADC_ODD_ZERO_PERIOD (7U) /*!< EPWM trigger ADC while counter of odd channel matches zero or period point \hideinitializer */ 77 #define EPWM_TRG_ADC_ODD_COMPARE_UP (8U) /*!< EPWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */ 78 #define EPWM_TRG_ADC_ODD_COMPARE_DOWN (9U) /*!< EPWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */ 79 #define EPWM_TRG_ADC_CH_0_FREE_CMP_UP (10U) /*!< EPWM trigger ADC while counter of channel 0 matches up count to free comparator point \hideinitializer */ 80 #define EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN (11U) /*!< EPWM trigger ADC while counter of channel 0 matches down count to free comparator point \hideinitializer */ 81 #define EPWM_TRG_ADC_CH_2_FREE_CMP_UP (12U) /*!< EPWM trigger ADC while counter of channel 2 matches up count to free comparator point \hideinitializer */ 82 #define EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN (13U) /*!< EPWM trigger ADC while counter of channel 2 matches down count to free comparator point \hideinitializer */ 83 #define EPWM_TRG_ADC_CH_4_FREE_CMP_UP (14U) /*!< EPWM trigger ADC while counter of channel 4 matches up count to free comparator point \hideinitializer */ 84 #define EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN (15U) /*!< EPWM trigger ADC while counter of channel 4 matches down count to free comparator point \hideinitializer */ 85 #define EPWM_TRG_ADC_EVEN_IFA (16U) /*!< EPWM trigger ADC while counter of even channel interrupt flag accumulator interrupt \hideinitializer */ 86 #define EPWM_TRG_ADC_ODD_IFA (17U) /*!< EPWM trigger ADC while counter of odd channel interrupt flag accumulator interrupt \hideinitializer */ 87 88 #define EPWM_TRIGGER_DAC_ZERO (0x1U) /*!< EPWM trigger DAC while counter down count to 0 \hideinitializer */ 89 #define EPWM_TRIGGER_DAC_PERIOD (0x100U) /*!< EPWM trigger DAC while counter matches (PERIOD + 1) \hideinitializer */ 90 #define EPWM_TRIGGER_DAC_COMPARE_UP (0x10000U) /*!< EPWM trigger DAC while counter up count to CMPDAT \hideinitializer */ 91 #define EPWM_TRIGGER_DAC_COMPARE_DOWN (0x1000000U) /*!< EPWM trigger DAC while counter down count to CMPDAT \hideinitializer */ 92 93 /*---------------------------------------------------------------------------------------------------------*/ 94 /* Fail brake Control Constant Definitions */ 95 /*---------------------------------------------------------------------------------------------------------*/ 96 #define EPWM_FB_EDGE_ACMP0 (EPWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ 97 #define EPWM_FB_EDGE_ACMP1 (EPWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ 98 #define EPWM_FB_EDGE_ACMP2 (EPWM_BRKCTL0_1_CPO2EBEN_Msk) /*!< Comparator 2 as edge-detect fault brake source \hideinitializer */ 99 #define EPWM_FB_EDGE_ACMP3 (EPWM_BRKCTL0_1_CPO3EBEN_Msk) /*!< Comparator 3 as edge-detect fault brake source \hideinitializer */ 100 #define EPWM_FB_EDGE_BKP0 (EPWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source \hideinitializer */ 101 #define EPWM_FB_EDGE_BKP1 (EPWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source \hideinitializer */ 102 #define EPWM_FB_EDGE_ADCRM0 (EPWM_BRKCTL0_1_EADC0EBEN_Msk) /*!< ADC0 Result Monitor (ADCRM) as edge-detect fault brake source \hideinitializer */ 103 #define EPWM_FB_EDGE_ADCRM1 (EPWM_BRKCTL0_1_EADC1EBEN_Msk) /*!< ADC1 Result Monitor (ADCRM) as edge-detect fault brake source \hideinitializer */ 104 #define EPWM_FB_EDGE_ADCRM2 (EPWM_BRKCTL0_1_EADC2EBEN_Msk) /*!< ADC2 Result Monitor (ADCRM) as edge-detect fault brake source \hideinitializer */ 105 #define EPWM_FB_EDGE_SYS_CSS (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ 106 #define EPWM_FB_EDGE_SYS_BOD (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ 107 #define EPWM_FB_EDGE_SYS_RAM (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ 108 #define EPWM_FB_EDGE_SYS_COR (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ 109 110 #define EPWM_FB_LEVEL_ACMP0 (EPWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ 111 #define EPWM_FB_LEVEL_ACMP1 (EPWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ 112 #define EPWM_FB_LEVEL_ACMP2 (EPWM_BRKCTL0_1_CPO2LBEN_Msk) /*!< Comparator 2 as level-detect fault brake source \hideinitializer */ 113 #define EPWM_FB_LEVEL_ACMP3 (EPWM_BRKCTL0_1_CPO3LBEN_Msk) /*!< Comparator 3 as level-detect fault brake source \hideinitializer */ 114 #define EPWM_FB_LEVEL_BKP0 (EPWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source \hideinitializer */ 115 #define EPWM_FB_LEVEL_BKP1 (EPWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source \hideinitializer */ 116 #define EPWM_FB_LEVEL_ADCRM0 (EPWM_BRKCTL0_1_EADC0LBEN_Msk) /*!< ADC0 Result Monitor (ADCRM) as level-detect fault brake source \hideinitializer */ 117 #define EPWM_FB_LEVEL_ADCRM1 (EPWM_BRKCTL0_1_EADC1LBEN_Msk) /*!< ADC1 Result Monitor (ADCRM) as level-detect fault brake source \hideinitializer */ 118 #define EPWM_FB_LEVEL_ADCRM2 (EPWM_BRKCTL0_1_EADC2LBEN_Msk) /*!< ADC2 Result Monitor (ADCRM) as level-detect fault brake source \hideinitializer */ 119 #define EPWM_FB_LEVEL_SYS_CSS (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ 120 #define EPWM_FB_LEVEL_SYS_BOD (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ 121 #define EPWM_FB_LEVEL_SYS_RAM (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ 122 #define EPWM_FB_LEVEL_SYS_COR (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ 123 124 #define EPWM_FB_EDGE (0U) /*!< edge-detect fault brake \hideinitializer */ 125 #define EPWM_FB_LEVEL (8U) /*!< level-detect fault brake \hideinitializer */ 126 127 /*---------------------------------------------------------------------------------------------------------*/ 128 /* Leading Edge Blanking Control Constant Definitions */ 129 /*---------------------------------------------------------------------------------------------------------*/ 130 #define EPWM_LEBCTL_TRGTYPE_RISING (0U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising Edge \hideinitializer */ 131 #define EPWM_LEBCTL_TRGTYPE_FALLING (1U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Falling Edge \hideinitializer */ 132 #define EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING (2U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising or Falling Edge \hideinitializer */ 133 #define EPWM_LEBCTL_SRCEN0 (EPWM_LEBCTL_SRCEN0_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 Enable \hideinitializer */ 134 #define EPWM_LEBCTL_SRCEN2 (EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 Enable \hideinitializer */ 135 #define EPWM_LEBCTL_SRCEN4 (EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH4 Enable \hideinitializer */ 136 #define EPWM_LEBCTL_SRCEN0_2 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH2 Enable \hideinitializer */ 137 #define EPWM_LEBCTL_SRCEN0_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH4 Enable \hideinitializer */ 138 #define EPWM_LEBCTL_SRCEN2_4 (EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */ 139 #define EPWM_LEBCTL_SRCEN0_2_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0, EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */ 140 141 /*---------------------------------------------------------------------------------------------------------*/ 142 /* Capture Control Constant Definitions */ 143 /*---------------------------------------------------------------------------------------------------------*/ 144 #define EPWM_CAPTURE_INT_RISING_LATCH (1U) /*!< EPWM capture interrupt if channel has rising transition \hideinitializer */ 145 #define EPWM_CAPTURE_INT_FALLING_LATCH (0x100U) /*!< EPWM capture interrupt if channel has falling transition \hideinitializer */ 146 147 #define EPWM_CAPTURE_PDMA_RISING_LATCH (0x2U) /*!< EPWM capture rising latched data transfer by PDMA \hideinitializer */ 148 #define EPWM_CAPTURE_PDMA_FALLING_LATCH (0x4U) /*!< EPWM capture falling latched data transfer by PDMA \hideinitializer */ 149 #define EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6U) /*!< EPWM capture rising and falling latched data transfer by PDMA \hideinitializer */ 150 151 /*---------------------------------------------------------------------------------------------------------*/ 152 /* Duty Interrupt Type Constant Definitions */ 153 /*---------------------------------------------------------------------------------------------------------*/ 154 #define EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (1U << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM duty interrupt triggered if down count match comparator \hideinitializer */ 155 #define EPWM_DUTY_INT_UP_COUNT_MATCH_CMP (1U << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM duty interrupt triggered if up down match comparator \hideinitializer */ 156 157 /*---------------------------------------------------------------------------------------------------------*/ 158 /* Interrupt Flag Accumulator Constant Definitions */ 159 /*---------------------------------------------------------------------------------------------------------*/ 160 #define EPWM_IFA_ZERO_POINT (0U) /*!< EPWM counter equal to zero \hideinitializer */ 161 #define EPWM_IFA_PERIOD_POINT (1U) /*!< EPWM counter equal to period \hideinitializer */ 162 #define EPWM_IFA_COMPARE_UP_COUNT_POINT (2U) /*!< EPWM counter up count to comparator value \hideinitializer */ 163 #define EPWM_IFA_COMPARE_DOWN_COUNT_POINT (3U) /*!< EPWM counter down count to comparator value \hideinitializer */ 164 165 /*---------------------------------------------------------------------------------------------------------*/ 166 /* Load Mode Constant Definitions */ 167 /*---------------------------------------------------------------------------------------------------------*/ 168 #define EPWM_LOAD_MODE_IMMEDIATE (1U << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM immediately load mode \hideinitializer */ 169 #define EPWM_LOAD_MODE_WINDOW (1U << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM window load mode \hideinitializer */ 170 #define EPWM_LOAD_MODE_CENTER (1U << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM center load mode \hideinitializer */ 171 172 /*---------------------------------------------------------------------------------------------------------*/ 173 /* Synchronize Control Constant Definitions */ 174 /*---------------------------------------------------------------------------------------------------------*/ 175 #define EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0U) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */ 176 #define EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1U) /*!< Synchronize source from counter equal to 0 \hideinitializer */ 177 #define EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2U) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */ 178 #define EPWM_SYNC_OUT_DISABLE (3U) /*!< SYNC_OUT will not be generated \hideinitializer */ 179 #define EPWM_PHS_DIR_DECREMENT (0U) /*!< EPWM counter count decrement \hideinitializer */ 180 #define EPWM_PHS_DIR_INCREMENT (1U) /*!< EPWM counter count increment \hideinitializer */ 181 182 /*---------------------------------------------------------------------------------------------------------*/ 183 /* Noise Filter Clock Divide Select Constant Definitions */ 184 /*---------------------------------------------------------------------------------------------------------*/ 185 #define EPWM_NF_CLK_DIV_1 (0U) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */ 186 #define EPWM_NF_CLK_DIV_2 (1U) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */ 187 #define EPWM_NF_CLK_DIV_4 (2U) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */ 188 #define EPWM_NF_CLK_DIV_8 (3U) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */ 189 #define EPWM_NF_CLK_DIV_16 (4U) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */ 190 #define EPWM_NF_CLK_DIV_32 (5U) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */ 191 #define EPWM_NF_CLK_DIV_64 (6U) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */ 192 #define EPWM_NF_CLK_DIV_128 (7U) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */ 193 194 /*---------------------------------------------------------------------------------------------------------*/ 195 /* Clock Source Select Constant Definitions */ 196 /*---------------------------------------------------------------------------------------------------------*/ 197 #define EPWM_CLKSRC_EPWM_CLK (0U) /*!< EPWM Clock source selects to EPWM0_CLK or EPWM1_CLK \hideinitializer */ 198 #define EPWM_CLKSRC_TIMER0 (1U) /*!< EPWM Clock source selects to TIMER0 overflow \hideinitializer */ 199 #define EPWM_CLKSRC_TIMER1 (2U) /*!< EPWM Clock source selects to TIMER1 overflow \hideinitializer */ 200 #define EPWM_CLKSRC_TIMER2 (3U) /*!< EPWM Clock source selects to TIMER2 overflow \hideinitializer */ 201 #define EPWM_CLKSRC_TIMER3 (4U) /*!< EPWM Clock source selects to TIMER3 overflow \hideinitializer */ 202 203 /*---------------------------------------------------------------------------------------------------------*/ 204 /* Fault Detect Clock Source Select Constant Definitions */ 205 /*---------------------------------------------------------------------------------------------------------*/ 206 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_1 (0UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 1 \hideinitializer */ 207 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_2 (1UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 2 \hideinitializer */ 208 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_4 (2UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 4 \hideinitializer */ 209 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_8 (3UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 8 \hideinitializer */ 210 211 212 /*@}*/ /* end of group EPWM_EXPORTED_CONSTANTS */ 213 214 215 /** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions 216 @{ 217 */ 218 219 /** 220 * @brief This macro enable complementary mode 221 * @param[in] epwm The pointer of the specified EPWM module 222 * @return None 223 * @details This macro is used to enable complementary mode of EPWM module. 224 * \hideinitializer 225 */ 226 #define EPWM_ENABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 | (0x7ul<<EPWM_CTL1_OUTMODE0_Pos)) 227 228 /** 229 * @brief This macro disable complementary mode, and enable independent mode. 230 * @param[in] epwm The pointer of the specified EPWM module 231 * @return None 232 * @details This macro is used to disable complementary mode of EPWM module. 233 * \hideinitializer 234 */ 235 #define EPWM_DISABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 & ~(0x7ul<<EPWM_CTL1_OUTMODE0_Pos)) 236 237 /** 238 * @brief This macro enable group mode 239 * @param[in] epwm The pointer of the specified EPWM module 240 * @return None 241 * @details This macro is used to enable group mode of EPWM module. 242 * \hideinitializer 243 */ 244 #define EPWM_ENABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) 245 246 /** 247 * @brief This macro disable group mode 248 * @param[in] epwm The pointer of the specified EPWM module 249 * @return None 250 * @details This macro is used to disable group mode of EPWM module. 251 * \hideinitializer 252 */ 253 #define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) 254 255 /** 256 * @brief Enable timer synchronous start counting function of specified channel(s) 257 * @param[in] epwm The pointer of the specified EPWM module 258 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 259 * Bit 0 represents channel 0, bit 1 represents channel 1... 260 * @param[in] u32SyncSrc Synchronous start source selection, valid values are: 261 * - \ref EPWM_SSCTL_SSRC_EPWM0 262 * - \ref EPWM_SSCTL_SSRC_EPWM1 263 * - \ref EPWM_SSCTL_SSRC_BPWM0 264 * - \ref EPWM_SSCTL_SSRC_BPWM1 265 * @return None 266 * @details This macro is used to enable timer synchronous start counting function of specified channel(s). 267 * \hideinitializer 268 */ 269 #define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) 270 271 /** 272 * @brief Disable timer synchronous start counting function of specified channel(s) 273 * @param[in] epwm The pointer of the specified EPWM module 274 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 275 * Bit 0 represents channel 0, bit 1 represents channel 1... 276 * @return None 277 * @details This macro is used to disable timer synchronous start counting function of specified channel(s). 278 * \hideinitializer 279 */ 280 #define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ 281 do{ \ 282 int i;\ 283 for(i = 0; i < 6; i++) { \ 284 if((u32ChannelMask) & (1 << i)) \ 285 (epwm)->SSCTL &= ~(1UL << i); \ 286 } \ 287 }while(0) 288 289 /** 290 * @brief This macro enable EPWM counter synchronous start counting function. 291 * @param[in] epwm The pointer of the specified EPWM module 292 * @return None 293 * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. 294 * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). 295 * \hideinitializer 296 */ 297 #define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) 298 299 /** 300 * @brief This macro enable output inverter of specified channel(s) 301 * @param[in] epwm The pointer of the specified EPWM module 302 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 303 * Bit 0 represents channel 0, bit 1 represents channel 1... 304 * @return None 305 * @details This macro is used to enable output inverter of specified channel(s). 306 * \hideinitializer 307 */ 308 #define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) 309 310 /** 311 * @brief This macro get captured rising data 312 * @param[in] epwm The pointer of the specified EPWM module 313 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 314 * @return None 315 * @details This macro is used to get captured rising data of specified channel. 316 * \hideinitializer 317 */ 318 #define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) 319 320 /** 321 * @brief This macro get captured falling data 322 * @param[in] epwm The pointer of the specified EPWM module 323 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 324 * @return None 325 * @details This macro is used to get captured falling data of specified channel. 326 * \hideinitializer 327 */ 328 #define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) 329 330 /** 331 * @brief This macro mask output logic to high or low 332 * @param[in] epwm The pointer of the specified EPWM module 333 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 334 * Bit 0 represents channel 0, bit 1 represents channel 1... 335 * @param[in] u32LevelMask Output logic to high or low 336 * @return None 337 * @details This macro is used to mask output logic to high or low of specified channel(s). 338 * @note If u32ChannelMask parameter is 0, then mask function will be disabled. 339 * \hideinitializer 340 */ 341 #define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ 342 { \ 343 (epwm)->MSKEN = (u32ChannelMask); \ 344 (epwm)->MSK = (u32LevelMask); \ 345 } 346 347 /** 348 * @brief This macro set the prescaler of the selected channel 349 * @param[in] epwm The pointer of the specified EPWM module 350 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 351 * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF 352 * @return None 353 * @details This macro is used to set the prescaler of specified channel. 354 * @note The clock of EPWM counter is divided by (u32Prescaler + 1). 355 * \hideinitializer 356 */ 357 #define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum)] = (u32Prescaler)) 358 359 /** 360 * @brief This macro get the prescaler of the selected channel 361 * @param[in] epwm The pointer of the specified EPWM module 362 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 363 * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF 364 * @details This macro is used to get the prescaler of specified channel. 365 * @note The clock of EPWM counter is divided by (u32Prescaler + 1). 366 * \hideinitializer 367 */ 368 #define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum)]) 369 370 /** 371 * @brief This macro set the comparator of the selected channel 372 * @param[in] epwm The pointer of the specified EPWM module 373 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 374 * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF 375 * @return None 376 * @details This macro is used to set the comparator of specified channel. 377 * @note This new setting will take effect on next EPWM period. 378 * \hideinitializer 379 */ 380 #define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) 381 382 /** 383 * @brief This macro get the comparator of the selected channel 384 * @param[in] epwm The pointer of the specified EPWM module 385 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 386 * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF 387 * @details This macro is used to get the comparator of specified channel. 388 * \hideinitializer 389 */ 390 #define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) 391 392 /** 393 * @brief This macro set the free trigger comparator of the selected channel 394 * @param[in] epwm The pointer of the specified EPWM module 395 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 396 * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF 397 * @return None 398 * @details This macro is used to set the free trigger comparator of specified channel. 399 * @note This new setting will take effect on next EPWM period. 400 * \hideinitializer 401 */ 402 #define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) 403 404 /** 405 * @brief This macro set the period of the selected channel 406 * @param[in] epwm The pointer of the specified EPWM module 407 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 408 * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF 409 * @return None 410 * @details This macro is used to set the period of specified channel. 411 * @note This new setting will take effect on next EPWM period. 412 * @note EPWM counter will stop if period length set to 0. 413 * \hideinitializer 414 */ 415 #define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) 416 417 /** 418 * @brief This macro get the period of the selected channel 419 * @param[in] epwm The pointer of the specified EPWM module 420 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 421 * @return Return the period of specified channel. Valid values are between 0~0xFFFF 422 * @details This macro is used to get the period of specified channel. 423 * \hideinitializer 424 */ 425 #define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) 426 427 /** 428 * @brief This macro set the EPWM aligned type 429 * @param[in] epwm The pointer of the specified EPWM module 430 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 431 * Bit 0 represents channel 0, bit 1 represents channel 1... 432 * @param[in] u32AlignedType EPWM aligned type, valid values are: 433 * - \ref EPWM_EDGE_ALIGNED 434 * - \ref EPWM_CENTER_ALIGNED 435 * @return None 436 * @details This macro is used to set the EPWM aligned type of specified channel(s). 437 * \hideinitializer 438 */ 439 #define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ 440 do{ \ 441 int i; \ 442 for(i = 0; i < 6; i++) { \ 443 if((u32ChannelMask) & (1 << i)) \ 444 (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ 445 } \ 446 }while(0) 447 448 /** 449 * @brief Set load window of window loading mode for specified channel(s) 450 * @param[in] epwm The pointer of the specified EPWM module 451 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 452 * Bit 0 represents channel 0, bit 1 represents channel 1... 453 * @return None 454 * @details This macro is used to set load window of window loading mode for specified channel(s). 455 * \hideinitializer 456 */ 457 #define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) 458 459 /** 460 * @brief Trigger synchronous event from specified channel(s) 461 * @param[in] epwm The pointer of the specified EPWM module 462 * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 463 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 464 * @return None 465 * @details This macro is used to trigger synchronous event from specified channel(s). 466 * \hideinitializer 467 */ 468 #define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1))) 469 470 /** 471 * @brief Clear counter of specified channel(s) 472 * @param[in] epwm The pointer of the specified EPWM module 473 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 474 * Bit 0 represents channel 0, bit 1 represents channel 1... 475 * @return None 476 * @details This macro is used to clear counter of specified channel(s). 477 * \hideinitializer 478 */ 479 #define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) 480 481 /** 482 * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) 483 * @param[in] epwm The pointer of the specified EPWM module 484 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 485 * Bit 0 represents channel 0, bit 1 represents channel 1... 486 * @param[in] u32ZeroLevel output level at zero point, valid values are: 487 * - \ref EPWM_OUTPUT_NOTHING 488 * - \ref EPWM_OUTPUT_LOW 489 * - \ref EPWM_OUTPUT_HIGH 490 * - \ref EPWM_OUTPUT_TOGGLE 491 * @param[in] u32CmpUpLevel output level at compare up point, valid values are: 492 * - \ref EPWM_OUTPUT_NOTHING 493 * - \ref EPWM_OUTPUT_LOW 494 * - \ref EPWM_OUTPUT_HIGH 495 * - \ref EPWM_OUTPUT_TOGGLE 496 * @param[in] u32PeriodLevel output level at period(center) point, valid values are: 497 * - \ref EPWM_OUTPUT_NOTHING 498 * - \ref EPWM_OUTPUT_LOW 499 * - \ref EPWM_OUTPUT_HIGH 500 * - \ref EPWM_OUTPUT_TOGGLE 501 * @param[in] u32CmpDownLevel output level at compare down point, valid values are: 502 * - \ref EPWM_OUTPUT_NOTHING 503 * - \ref EPWM_OUTPUT_LOW 504 * - \ref EPWM_OUTPUT_HIGH 505 * - \ref EPWM_OUTPUT_TOGGLE 506 * @return None 507 * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). 508 * \hideinitializer 509 */ 510 #define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ 511 do{ \ 512 int i; \ 513 for(i = 0; i < 6; i++) { \ 514 if((u32ChannelMask) & (1 << i)) { \ 515 (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ 516 (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ 517 (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ 518 (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ 519 } \ 520 } \ 521 }while(0) 522 523 /** 524 * @brief Trigger brake event from specified channel(s) 525 * @param[in] epwm The pointer of the specified EPWM module 526 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 527 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 528 * @param[in] u32BrakeType Type of brake trigger. 529 * - \ref EPWM_FB_EDGE 530 * - \ref EPWM_FB_LEVEL 531 * @return None 532 * @details This macro is used to trigger brake event from specified channel(s). 533 * \hideinitializer 534 */ 535 #define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) 536 537 /** 538 * @brief Set Dead zone clock source 539 * @param[in] epwm The pointer of the specified EPWM module 540 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 541 * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). 542 * @return None 543 * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. 544 * @note The write-protection function should be disabled before using this function. 545 * \hideinitializer 546 */ 547 #define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ 548 ((epwm)->DTCTL = (((epwm)->DTCTL & ~(1UL << (EPWM_DTCTL_DTCKSEL0_Pos + ((u32ChannelNum) >> 1U)))) | \ 549 ((u32AfterPrescaler) << (EPWM_DTCTL_DTCKSEL0_Pos + ((u32ChannelNum) >> 1U))))) 550 551 /*---------------------------------------------------------------------------------------------------------*/ 552 /* Define EPWM functions prototype */ 553 /*---------------------------------------------------------------------------------------------------------*/ 554 uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); 555 uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); 556 void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); 557 void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); 558 void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); 559 void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 560 void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); 561 int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt); 562 void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum); 563 void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 564 uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 565 void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 566 void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); 567 void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 568 uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 569 void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); 570 void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); 571 void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); 572 void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); 573 void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); 574 void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); 575 void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 576 void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); 577 void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); 578 void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 579 void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 580 void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 581 uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 582 void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); 583 void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); 584 void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 585 uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 586 void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); 587 void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); 588 void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); 589 uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); 590 void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); 591 void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); 592 void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 593 uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 594 void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); 595 void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); 596 void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 597 uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 598 void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); 599 void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); 600 void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 601 void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 602 void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 603 uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 604 void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 605 void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 606 void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); 607 void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); 608 void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 609 uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 610 void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 611 void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 612 void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); 613 void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); 614 void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); 615 void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); 616 void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); 617 void EPWM_EnableSyncPinInverse(EPWM_T *epwm); 618 void EPWM_DisableSyncPinInverse(EPWM_T *epwm); 619 void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); 620 void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); 621 void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); 622 void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); 623 void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); 624 void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); 625 void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); 626 uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 627 void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 628 void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel); 629 void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum); 630 void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); 631 void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); 632 void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle); 633 void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum); 634 void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt); 635 void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum); 636 void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 637 void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 638 void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 639 uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 640 641 /*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ 642 643 /*@}*/ /* end of group EPWM_Driver */ 644 645 /*@}*/ /* end of group Standard_Driver */ 646 647 #ifdef __cplusplus 648 } 649 #endif 650 651 #endif /* __EPWM_H__ */ 652 653
