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Searched refs:CLK_PLLCTL_FBDIV_Pos (Results 1 – 5 of 5) sorted by relevance

/hal_nuvoton-latest/m48x/Devices/M480/Include/
Dclk_reg.h1446 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK… macro
1447 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK…
/hal_nuvoton-latest/m46x/Devices/M460/Include/
Dclk_reg.h2086 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK… macro
2087 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK…
/hal_nuvoton-latest/dts/m46x/
Dclk_reg.h2090 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK… macro
2091 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK…
/hal_nuvoton-latest/m46x/StdDriver/src/
Dclk.c1144 ((u32MinNF - 2UL) << CLK_PLLCTL_FBDIV_Pos); in CLK_EnablePLL()
1434 u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; in CLK_GetPLLClockFreq()
/hal_nuvoton-latest/m48x/StdDriver/src/
Dclk.c1225 u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; in CLK_GetPLLClockFreq()