1 /**************************************************************************//**
2 * @file clk.h
3 * @version V1.0
4 * @brief M2L31 series CLK driver header file
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved.
8 ******************************************************************************/
9 #ifndef __CLK_H__
10 #define __CLK_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup CLK_Driver CLK Driver
23 @{
24 */
25
26 /** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
27 @{
28 */
29
30 #define FREQ_1MHZ 1000000UL /*!< 1 MHz \hideinitializer */
31 #define FREQ_2MHZ 2000000UL /*!< 2 MHz \hideinitializer */
32 #define FREQ_4MHZ 4000000UL /*!< 4 MHz \hideinitializer */
33 #define FREQ_8MHZ 8000000UL /*!< 8 MHz \hideinitializer */
34 #define FREQ_25MHZ 25000000UL /*!< 25 MHz \hideinitializer */
35 #define FREQ_36MHZ 36000000UL /*!< 36 MHz \hideinitializer */
36 #define FREQ_48MHZ 48000000UL /*!< 48 MHz \hideinitializer */
37 #define FREQ_50MHZ 50000000UL /*!< 50 MHz \hideinitializer */
38 #define FREQ_64MHZ 64000000UL /*!< 64 MHz \hideinitializer */
39 #define FREQ_72MHZ 72000000UL /*!< 72 MHz \hideinitializer */
40 #define FREQ_80MHZ 80000000UL /*!< 80 MHz \hideinitializer */
41 #define FREQ_96MHZ 96000000UL /*!< 96 MHz \hideinitializer */
42 #define FREQ_100MHZ 100000000UL /*!< 100 MHz \hideinitializer */
43 #define FREQ_120MHZ 120000000UL /*!< 120 MHz \hideinitializer */
44 #define FREQ_125MHZ 125000000UL /*!< 125 MHz \hideinitializer */
45 #define FREQ_144MHZ 144000000UL /*!< 144 MHz \hideinitializer */
46 #define FREQ_160MHZ 160000000UL /*!< 160 MHz \hideinitializer */
47 #define FREQ_192MHZ 192000000UL /*!< 192 MHz \hideinitializer */
48 #define FREQ_200MHZ 200000000UL /*!< 200 MHz \hideinitializer */
49 #define FREQ_240MHZ 240000000UL /*!< 240 MHz \hideinitializer */
50 #define FREQ_250MHZ 250000000UL /*!< 250 MHz \hideinitializer */
51 #define FREQ_492MHZ 492000000UL /*!< 492 MHz \hideinitializer */
52 #define FREQ_500MHZ 500000000UL /*!< 500 MHz \hideinitializer */
53
54 /*---------------------------------------------------------------------------------------------------------*/
55 /* PWRCTL constant definitions. (Write-protection) */
56 /*---------------------------------------------------------------------------------------------------------*/
57 #define CLK_PWRCTL_MIRCFSEL_1M (0x0UL << CLK_PWRCTL_MIRCFSEL_Pos) /*!< Select MIRC clock to 1 MHz \hideinitializer */
58 #define CLK_PWRCTL_MIRCFSEL_2M (0x1UL << CLK_PWRCTL_MIRCFSEL_Pos) /*!< Select MIRC clock to 2 MHz \hideinitializer */
59 #define CLK_PWRCTL_MIRCFSEL_4M (0x2UL << CLK_PWRCTL_MIRCFSEL_Pos) /*!< Select MIRC clock to 4 MHz \hideinitializer */
60 #define CLK_PWRCTL_MIRCFSEL_8M (0x3UL << CLK_PWRCTL_MIRCFSEL_Pos) /*!< Select MIRC clock to 8 MHz \hideinitializer */
61
62 /*---------------------------------------------------------------------------------------------------------*/
63 /* CLKSEL0 constant definitions. (Write-protection) */
64 /*---------------------------------------------------------------------------------------------------------*/
65 #define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from high speed crystal \hideinitializer */
66 #define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from low speed crystal \hideinitializer */
67 #define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from PLL \hideinitializer */
68 #define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from low speed oscillator \hideinitializer */
69 #define CLK_CLKSEL0_HCLKSEL_MIRC (0x5UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from middle speed oscillator \hideinitializer */
70 #define CLK_CLKSEL0_HCLKSEL_HIRC48M (0x6UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from 48 MHz high speed oscillator \hideinitializer */
71 #define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from high speed oscillator \hideinitializer */
72
73 #define CLK_CLKSEL0_HCLK0SEL_HXT (0x0UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from high speed crystal \hideinitializer */
74 #define CLK_CLKSEL0_HCLK0SEL_LXT (0x1UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from low speed crystal \hideinitializer */
75 #define CLK_CLKSEL0_HCLK0SEL_PLL (0x2UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from PLL \hideinitializer */
76 #define CLK_CLKSEL0_HCLK0SEL_LIRC (0x3UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from low speed oscillator \hideinitializer */
77 #define CLK_CLKSEL0_HCLK0SEL_MIRC (0x5UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from middle speed oscillator \hideinitializer */
78 #define CLK_CLKSEL0_HCLK0SEL_HIRC48M (0x6UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from 48 MHz high speed oscillator \hideinitializer */
79 #define CLK_CLKSEL0_HCLK0SEL_HIRC (0x7UL << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< Select HCLK0 clock source from high speed oscillator \hideinitializer */
80
81 #define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from high speed crystal \hideinitializer */
82 #define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from low speed crystal \hideinitializer */
83 #define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HXT/2 \hideinitializer */
84 #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HCLK/2 \hideinitializer */
85 #define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HIRC/2 \hideinitializer */
86 #define CLK_CLKSEL0_STCLKSEL_HCLK (0x1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK0 \hideinitializer */
87 #define CLK_CLKSEL0_STCLKSEL_HCLK0 (0x1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK0 \hideinitializer */
88
89 #define CLK_CLKSEL0_HCLK1SEL_HIRC (0x0UL << CLK_CLKSEL0_HCLK1SEL_Pos) /*!< Select HCLK1 clock source from high speed oscillator \hideinitializer */
90 #define CLK_CLKSEL0_HCLK1SEL_MIRC (0x1UL << CLK_CLKSEL0_HCLK1SEL_Pos) /*!< Select HCLK1 clock source from middle speed oscillator \hideinitializer */
91 #define CLK_CLKSEL0_HCLK1SEL_LXT (0x2UL << CLK_CLKSEL0_HCLK1SEL_Pos) /*!< Select HCLK1 clock source from low speed crystal \hideinitializer */
92 #define CLK_CLKSEL0_HCLK1SEL_LIRC (0x3UL << CLK_CLKSEL0_HCLK1SEL_Pos) /*!< Select HCLK1 clock source from low speed oscillator \hideinitializer */
93 #define CLK_CLKSEL0_HCLK1SEL_HIRC48M_DIV2 (0x4UL << CLK_CLKSEL0_HCLK1SEL_Pos) /*!< Select HCLK1 clock source from 48 MHz high speed oscillator / 2 \hideinitializer */
94
95 #define CLK_CLKSEL0_USBSEL_HIRC48M (0x0UL << CLK_CLKSEL0_USBSEL_Pos) /*!< Select USB clock source from 48 MHz high speed oscillator \hideinitializer */
96 #define CLK_CLKSEL0_USBSEL_PLL (0x1UL << CLK_CLKSEL0_USBSEL_Pos) /*!< Select USB clock source from PLL \hideinitializer */
97
98 #define CLK_CLKSEL0_EADC0SEL_PLL (0x1UL << CLK_CLKSEL0_EADC0SEL_Pos) /*!< Select EADC0 clock source from PLL \hideinitializer */
99 #define CLK_CLKSEL0_EADC0SEL_HCLK (0x2UL << CLK_CLKSEL0_EADC0SEL_Pos) /*!< Select EADC0 clock source from HCLK0 \hideinitializer */
100 #define CLK_CLKSEL0_EADC0SEL_HCLK0 (0x2UL << CLK_CLKSEL0_EADC0SEL_Pos) /*!< Select EADC0 clock source from HCLK0 \hideinitializer */
101 #define CLK_CLKSEL0_EADC0SEL_HIRC (0x3UL << CLK_CLKSEL0_EADC0SEL_Pos) /*!< Select EADC0 clock source from HIRC \hideinitializer */
102
103 #define CLK_CLKSEL0_CANFD0SEL_HXT (0x0UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from HXT \hideinitializer */
104 #define CLK_CLKSEL0_CANFD0SEL_HIRC48M (0x1UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from 48 MHz high speed oscillator \hideinitializer */
105 #define CLK_CLKSEL0_CANFD0SEL_HCLK (0x2UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from HCLK0 \hideinitializer */
106 #define CLK_CLKSEL0_CANFD0SEL_HCLK0 (0x2UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from HCLK0 \hideinitializer */
107 #define CLK_CLKSEL0_CANFD0SEL_HIRC (0x3UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from HIRC \hideinitializer */
108
109 #define CLK_CLKSEL0_CANFD1SEL_HXT (0x0UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from HXT \hideinitializer */
110 #define CLK_CLKSEL0_CANFD1SEL_HIRC48M (0x1UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from 48 MHz high speed oscillator \hideinitializer */
111 #define CLK_CLKSEL0_CANFD1SEL_HCLK (0x2UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from HCLK0 \hideinitializer */
112 #define CLK_CLKSEL0_CANFD1SEL_HCLK0 (0x2UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from HCLK0 \hideinitializer */
113 #define CLK_CLKSEL0_CANFD1SEL_HIRC (0x3UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from HIRC \hideinitializer */
114
115 /*---------------------------------------------------------------------------------------------------------*/
116 /* CLKSEL1 constant definitions. */
117 /*---------------------------------------------------------------------------------------------------------*/
118 #define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed crystal \hideinitializer */
119 #define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from low speed crystal \hideinitializer */
120 #define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK0 \hideinitializer */
121 #define CLK_CLKSEL1_CLKOSEL_HCLK0 (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK0 \hideinitializer */
122 #define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from high speed oscillator \hideinitializer */
123 #define CLK_CLKSEL1_CLKOSEL_LIRC (0x4UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from low speed oscillator \hideinitializer */
124 #define CLK_CLKSEL1_CLKOSEL_HIRC48M (0x5UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from 48 MHz high speed oscillator \hideinitializer */
125 #define CLK_CLKSEL1_CLKOSEL_PLL (0x6UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from PLL \hideinitializer */
126 #define CLK_CLKSEL1_CLKOSEL_MIRC (0x7UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from middle speed oscillator \hideinitializer */
127
128 #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal \hideinitializer */
129 #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal \hideinitializer */
130 #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 \hideinitializer */
131 #define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from external trigger \hideinitializer */
132 #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */
133 #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */
134
135 #define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal \hideinitializer */
136 #define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal \hideinitializer */
137 #define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 \hideinitializer */
138 #define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger \hideinitializer */
139 #define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */
140 #define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */
141
142 #define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal \hideinitializer */
143 #define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal \hideinitializer */
144 #define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 \hideinitializer */
145 #define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger \hideinitializer */
146 #define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */
147 #define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */
148
149 #define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal \hideinitializer */
150 #define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal \hideinitializer */
151 #define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 \hideinitializer */
152 #define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger \hideinitializer */
153 #define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */
154 #define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */
155
156 #define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK0/2048 \hideinitializer */
157 #define CLK_CLKSEL1_WWDTSEL_HCLK0_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK0/2048 \hideinitializer */
158 #define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from low speed oscillator \hideinitializer */
159
160
161 /*---------------------------------------------------------------------------------------------------------*/
162 /* CLKSEL2 constant definitions. */
163 /*---------------------------------------------------------------------------------------------------------*/
164 #define CLK_CLKSEL2_EPWM0SEL_HCLK (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from HCLK0 \hideinitializer */
165 #define CLK_CLKSEL2_EPWM0SEL_HCLK0 (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from HCLK0 \hideinitializer */
166 #define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */
167
168 #define CLK_CLKSEL2_EPWM1SEL_HCLK (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from HCLK0 \hideinitializer */
169 #define CLK_CLKSEL2_EPWM1SEL_HCLK0 (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from HCLK0 \hideinitializer */
170 #define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */
171
172 #define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed crystal \hideinitializer */
173 #define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PLL \hideinitializer */
174 #define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PCLK0 \hideinitializer */
175 #define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed oscillator \hideinitializer */
176
177 #define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed crystal \hideinitializer */
178 #define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLL \hideinitializer */
179 #define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK1 \hideinitializer */
180 #define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */
181 #define CLK_CLKSEL2_SPI0SEL_HIRC48M (0x4UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from 48MHz high speed oscillator \hideinitializer */
182
183 #define CLK_CLKSEL2_TKSEL_HIRC (0x0UL << CLK_CLKSEL2_TKSEL_Pos) /*!< Select TK clock source from HCLK0 \hideinitializer */
184 #define CLK_CLKSEL2_TKSEL_MIRC (0x1UL << CLK_CLKSEL2_TKSEL_Pos) /*!< Select TK clock source from PCLK0 \hideinitializer */
185
186 #define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed crystal \hideinitializer */
187 #define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLL \hideinitializer */
188 #define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK0 \hideinitializer */
189 #define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */
190 #define CLK_CLKSEL2_SPI1SEL_HIRC48M (0x4UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from 48MHz high speed oscillator \hideinitializer */
191
192
193 /*---------------------------------------------------------------------------------------------------------*/
194 /* CLKSEL3 constant definitions. */
195 /*---------------------------------------------------------------------------------------------------------*/
196 #define CLK_CLKSEL3_PWM0SEL_HCLK (0x0UL << CLK_CLKSEL3_PWM0SEL_Pos) /*!< Select PWM0 clock source from HCLK0 \hideinitializer */
197 #define CLK_CLKSEL3_PWM0SEL_HCLK0 (0x0UL << CLK_CLKSEL3_PWM0SEL_Pos) /*!< Select PWM0 clock source from HCLK0 \hideinitializer */
198 #define CLK_CLKSEL3_PWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL3_PWM0SEL_Pos) /*!< Select PWM0 clock source from PCLK0 \hideinitializer */
199
200 #define CLK_CLKSEL3_PWM1SEL_HCLK (0x0UL << CLK_CLKSEL3_PWM1SEL_Pos) /*!< Select PWM1 clock source from HCLK0 \hideinitializer */
201 #define CLK_CLKSEL3_PWM1SEL_HCLK0 (0x0UL << CLK_CLKSEL3_PWM1SEL_Pos) /*!< Select PWM1 clock source from HCLK0 \hideinitializer */
202 #define CLK_CLKSEL3_PWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL3_PWM1SEL_Pos) /*!< Select PWM1 clock source from PCLK1 \hideinitializer */
203
204 #define CLK_CLKSEL3_SPI2SEL_HXT (0x0UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed crystal \hideinitializer */
205 #define CLK_CLKSEL3_SPI2SEL_PLL (0x1UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLL \hideinitializer */
206 #define CLK_CLKSEL3_SPI2SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK1 \hideinitializer */
207 #define CLK_CLKSEL3_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */
208 #define CLK_CLKSEL3_SPI2SEL_HIRC48M (0x4UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from 48MHz high speed oscillator \hideinitializer */
209
210 #define CLK_CLKSEL3_SPI3SEL_HXT (0x0UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed crystal \hideinitializer */
211 #define CLK_CLKSEL3_SPI3SEL_PLL (0x1UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLL \hideinitializer */
212 #define CLK_CLKSEL3_SPI3SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK0 \hideinitializer */
213 #define CLK_CLKSEL3_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */
214 #define CLK_CLKSEL3_SPI3SEL_HIRC48M (0x4UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from 48MHz high speed oscillator \hideinitializer */
215
216
217 /*---------------------------------------------------------------------------------------------------------*/
218 /* CLKSEL4 constant definitions. */
219 /*---------------------------------------------------------------------------------------------------------*/
220 #define CLK_CLKSEL4_UART0SEL_HXT (0x0UL << CLK_CLKSEL4_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal \hideinitializer */
221 #define CLK_CLKSEL4_UART0SEL_PLL (0x1UL << CLK_CLKSEL4_UART0SEL_Pos) /*!< Select UART0 clock source from PLL \hideinitializer */
222 #define CLK_CLKSEL4_UART0SEL_LXT (0x2UL << CLK_CLKSEL4_UART0SEL_Pos) /*!< Select UART0 clock source from low speed crystal \hideinitializer */
223 #define CLK_CLKSEL4_UART0SEL_HIRC (0x3UL << CLK_CLKSEL4_UART0SEL_Pos) /*!< Select UART0 clock source from high speed oscillator \hideinitializer */
224 #define CLK_CLKSEL4_UART0SEL_MIRC (0x4UL << CLK_CLKSEL4_UART0SEL_Pos) /*!< Select UART0 clock source from middle speed oscillator \hideinitializer */
225 #define CLK_CLKSEL4_UART0SEL_HIRC48M (0x5UL << CLK_CLKSEL4_UART0SEL_Pos) /*!< Select UART0 clock source from 48MHz high speed oscillator \hideinitializer */
226
227 #define CLK_CLKSEL4_UART1SEL_HXT (0x0UL << CLK_CLKSEL4_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal \hideinitializer */
228 #define CLK_CLKSEL4_UART1SEL_PLL (0x1UL << CLK_CLKSEL4_UART1SEL_Pos) /*!< Select UART1 clock source from PLL \hideinitializer */
229 #define CLK_CLKSEL4_UART1SEL_LXT (0x2UL << CLK_CLKSEL4_UART1SEL_Pos) /*!< Select UART1 clock source from low speed crystal \hideinitializer */
230 #define CLK_CLKSEL4_UART1SEL_HIRC (0x3UL << CLK_CLKSEL4_UART1SEL_Pos) /*!< Select UART1 clock source from high speed oscillator \hideinitializer */
231 #define CLK_CLKSEL4_UART1SEL_MIRC (0x4UL << CLK_CLKSEL4_UART1SEL_Pos) /*!< Select UART1 clock source from middle speed oscillator \hideinitializer */
232 #define CLK_CLKSEL4_UART1SEL_HIRC48M (0x5UL << CLK_CLKSEL4_UART1SEL_Pos) /*!< Select UART1 clock source from 48MHz high speed oscillator \hideinitializer */
233
234 #define CLK_CLKSEL4_UART2SEL_HXT (0x0UL << CLK_CLKSEL4_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal \hideinitializer */
235 #define CLK_CLKSEL4_UART2SEL_PLL (0x1UL << CLK_CLKSEL4_UART2SEL_Pos) /*!< Select UART2 clock source from PLL \hideinitializer */
236 #define CLK_CLKSEL4_UART2SEL_LXT (0x2UL << CLK_CLKSEL4_UART2SEL_Pos) /*!< Select UART2 clock source from low speed crystal \hideinitializer */
237 #define CLK_CLKSEL4_UART2SEL_HIRC (0x3UL << CLK_CLKSEL4_UART2SEL_Pos) /*!< Select UART2 clock source from high speed oscillator \hideinitializer */
238 #define CLK_CLKSEL4_UART2SEL_MIRC (0x4UL << CLK_CLKSEL4_UART2SEL_Pos) /*!< Select UART2 clock source from middle speed oscillator \hideinitializer */
239 #define CLK_CLKSEL4_UART2SEL_HIRC48M (0x5UL << CLK_CLKSEL4_UART2SEL_Pos) /*!< Select UART2 clock source from 48MHz high speed oscillator \hideinitializer */
240
241 #define CLK_CLKSEL4_UART3SEL_HXT (0x0UL << CLK_CLKSEL4_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal \hideinitializer */
242 #define CLK_CLKSEL4_UART3SEL_PLL (0x1UL << CLK_CLKSEL4_UART3SEL_Pos) /*!< Select UART3 clock source from PLL \hideinitializer */
243 #define CLK_CLKSEL4_UART3SEL_LXT (0x2UL << CLK_CLKSEL4_UART3SEL_Pos) /*!< Select UART3 clock source from low speed crystal \hideinitializer */
244 #define CLK_CLKSEL4_UART3SEL_HIRC (0x3UL << CLK_CLKSEL4_UART3SEL_Pos) /*!< Select UART3 clock source from high speed oscillator \hideinitializer */
245 #define CLK_CLKSEL4_UART3SEL_MIRC (0x4UL << CLK_CLKSEL4_UART3SEL_Pos) /*!< Select UART3 clock source from middle speed oscillator \hideinitializer */
246 #define CLK_CLKSEL4_UART3SEL_HIRC48M (0x5UL << CLK_CLKSEL4_UART3SEL_Pos) /*!< Select UART3 clock source from 48MHz high speed oscillator \hideinitializer */
247
248 #define CLK_CLKSEL4_UART4SEL_HXT (0x0UL << CLK_CLKSEL4_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal \hideinitializer */
249 #define CLK_CLKSEL4_UART4SEL_PLL (0x1UL << CLK_CLKSEL4_UART4SEL_Pos) /*!< Select UART4 clock source from PLL \hideinitializer */
250 #define CLK_CLKSEL4_UART4SEL_LXT (0x2UL << CLK_CLKSEL4_UART4SEL_Pos) /*!< Select UART4 clock source from low speed crystal \hideinitializer */
251 #define CLK_CLKSEL4_UART4SEL_HIRC (0x3UL << CLK_CLKSEL4_UART4SEL_Pos) /*!< Select UART4 clock source from high speed oscillator \hideinitializer */
252 #define CLK_CLKSEL4_UART4SEL_MIRC (0x4UL << CLK_CLKSEL4_UART4SEL_Pos) /*!< Select UART4 clock source from middle speed oscillator \hideinitializer */
253 #define CLK_CLKSEL4_UART4SEL_HIRC48M (0x5UL << CLK_CLKSEL4_UART4SEL_Pos) /*!< Select UART4 clock source from 48MHz high speed oscillator \hideinitializer */
254
255 #define CLK_CLKSEL4_UART5SEL_HXT (0x0UL << CLK_CLKSEL4_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal \hideinitializer */
256 #define CLK_CLKSEL4_UART5SEL_PLL (0x1UL << CLK_CLKSEL4_UART5SEL_Pos) /*!< Select UART5 clock source from PLL \hideinitializer */
257 #define CLK_CLKSEL4_UART5SEL_LXT (0x2UL << CLK_CLKSEL4_UART5SEL_Pos) /*!< Select UART5 clock source from low speed crystal \hideinitializer */
258 #define CLK_CLKSEL4_UART5SEL_HIRC (0x3UL << CLK_CLKSEL4_UART5SEL_Pos) /*!< Select UART5 clock source from high speed oscillator \hideinitializer */
259 #define CLK_CLKSEL4_UART5SEL_MIRC (0x4UL << CLK_CLKSEL4_UART5SEL_Pos) /*!< Select UART5 clock source from middle speed oscillator \hideinitializer */
260 #define CLK_CLKSEL4_UART5SEL_HIRC48M (0x5UL << CLK_CLKSEL4_UART5SEL_Pos) /*!< Select UART5 clock source from 48MHz high speed oscillator \hideinitializer */
261
262 #define CLK_CLKSEL4_UART6SEL_HXT (0x0UL << CLK_CLKSEL4_UART6SEL_Pos) /*!< Select UART6 clock source from high speed crystal \hideinitializer */
263 #define CLK_CLKSEL4_UART6SEL_PLL (0x1UL << CLK_CLKSEL4_UART6SEL_Pos) /*!< Select UART6 clock source from PLL \hideinitializer */
264 #define CLK_CLKSEL4_UART6SEL_LXT (0x2UL << CLK_CLKSEL4_UART6SEL_Pos) /*!< Select UART6 clock source from low speed crystal \hideinitializer */
265 #define CLK_CLKSEL4_UART6SEL_HIRC (0x3UL << CLK_CLKSEL4_UART6SEL_Pos) /*!< Select UART6 clock source from high speed oscillator \hideinitializer */
266 #define CLK_CLKSEL4_UART6SEL_MIRC (0x4UL << CLK_CLKSEL4_UART6SEL_Pos) /*!< Select UART6 clock source from middle speed oscillator \hideinitializer */
267 #define CLK_CLKSEL4_UART6SEL_HIRC48M (0x5UL << CLK_CLKSEL4_UART6SEL_Pos) /*!< Select UART6 clock source from 48MHz high speed oscillator \hideinitializer */
268
269 #define CLK_CLKSEL4_UART7SEL_HXT (0x0UL << CLK_CLKSEL4_UART7SEL_Pos) /*!< Select UART7 clock source from high speed crystal \hideinitializer */
270 #define CLK_CLKSEL4_UART7SEL_PLL (0x1UL << CLK_CLKSEL4_UART7SEL_Pos) /*!< Select UART7 clock source from PLL \hideinitializer */
271 #define CLK_CLKSEL4_UART7SEL_LXT (0x2UL << CLK_CLKSEL4_UART7SEL_Pos) /*!< Select UART7 clock source from low speed crystal \hideinitializer */
272 #define CLK_CLKSEL4_UART7SEL_HIRC (0x3UL << CLK_CLKSEL4_UART7SEL_Pos) /*!< Select UART7 clock source from high speed oscillator \hideinitializer */
273 #define CLK_CLKSEL4_UART7SEL_MIRC (0x4UL << CLK_CLKSEL4_UART7SEL_Pos) /*!< Select UART7 clock source from middle speed oscillator \hideinitializer */
274 #define CLK_CLKSEL4_UART7SEL_HIRC48M (0x5UL << CLK_CLKSEL4_UART7SEL_Pos) /*!< Select UART7 clock source from 48MHz high speed oscillator \hideinitializer */
275
276
277 /*---------------------------------------------------------------------------------------------------------*/
278 /* CLKDIV0 constant definitions. */
279 /*---------------------------------------------------------------------------------------------------------*/
280 #define CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << CLK_CLKDIV0_HCLK0DIV_Pos) /*!< CLKDIV0 Setting for HCLK0 clock divider. It could be 1~16 \hideinitializer */
281 #define CLK_CLKDIV0_HCLK0(x) (((x) - 1UL) << CLK_CLKDIV0_HCLK0DIV_Pos) /*!< CLKDIV0 Setting for HCLK0 clock divider. It could be 1~16 \hideinitializer */
282 #define CLK_CLKDIV0_USB(x) (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */
283 #define CLK_CLKDIV0_UART0(x) (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */
284 #define CLK_CLKDIV0_UART1(x) (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */
285 #define CLK_CLKDIV0_EADC0(x) (((x) - 1UL) << CLK_CLKDIV0_EADC0DIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 \hideinitializer */
286
287
288 /*---------------------------------------------------------------------------------------------------------*/
289 /* CLKDIV4 constant definitions. */
290 /*---------------------------------------------------------------------------------------------------------*/
291 #define CLK_CLKDIV4_UART2(x) (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */
292 #define CLK_CLKDIV4_UART3(x) (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */
293 #define CLK_CLKDIV4_UART4(x) (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */
294 #define CLK_CLKDIV4_UART5(x) (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */
295 #define CLK_CLKDIV4_UART6(x) (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLKDIV4 Setting for UART6 clock divider. It could be 1~16 \hideinitializer */
296 #define CLK_CLKDIV4_UART7(x) (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLKDIV4 Setting for UART7 clock divider. It could be 1~16 \hideinitializer */
297
298
299 /*---------------------------------------------------------------------------------------------------------*/
300 /* CLKDIV5 constant definitions. */
301 /*---------------------------------------------------------------------------------------------------------*/
302 #define CLK_CLKDIV5_CANFD0(x) (((x) - 1UL) << CLK_CLKDIV5_CANFD0DIV_Pos) /*!< CLKDIV5 Setting for CANFD0 clock divider. It could be 1~16 \hideinitializer */
303 #define CLK_CLKDIV5_CANFD1(x) (((x) - 1UL) << CLK_CLKDIV5_CANFD1DIV_Pos) /*!< CLKDIV5 Setting for CANFD1 clock divider. It could be 1~16 \hideinitializer */
304
305
306 /*---------------------------------------------------------------------------------------------------------*/
307 /* PCLKDIV constant definitions. */
308 /*---------------------------------------------------------------------------------------------------------*/
309 #define CLK_PCLKDIV_PCLK0DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
310 #define CLK_PCLKDIV_PCLK0DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
311 #define CLK_PCLKDIV_PCLK0DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
312 #define CLK_PCLKDIV_PCLK0DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
313 #define CLK_PCLKDIV_PCLK0DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
314
315 #define CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
316 #define CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
317 #define CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
318 #define CLK_PCLKDIV_APB0DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
319 #define CLK_PCLKDIV_APB0DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
320
321 #define CLK_PCLKDIV_PCLK1DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
322 #define CLK_PCLKDIV_PCLK1DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
323 #define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
324 #define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
325 #define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
326
327 #define CLK_PCLKDIV_APB1DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
328 #define CLK_PCLKDIV_APB1DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
329 #define CLK_PCLKDIV_APB1DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
330 #define CLK_PCLKDIV_APB1DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
331 #define CLK_PCLKDIV_APB1DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
332
333
334 /*---------------------------------------------------------------------------------------------------------*/
335 /* PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO */
336 /*---------------------------------------------------------------------------------------------------------*/
337 #define CLK_PLLCTL_PLLSRC_HXT (0x0UL << CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is HXT. 1MHz < FIN/NR < 8MHz \hideinitializer */
338 #define CLK_PLLCTL_PLLSRC_HIRC (0x1UL << CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is HIRC. 1MHz < FIN/NR < 8MHz \hideinitializer */
339
340 #define CLK_PLLCTL_NF(x) (((x)-2UL)<<CLK_PLLCTL2_FBDIV_Pos) /*!< x must be constant and 2 <= x <= 255. 100MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */
341 #define CLK_PLLCTL_NR(x) (((x)-1UL)<<CLK_PLLCTL2_INDIV_Pos) /*!< x must be constant and 1 <= x <= 32. 1MHz < FIN/NR < 8MHz \hideinitializer */
342
343 #define CLK_PLLCTL_NO_1 (0x0UL << CLK_PLLCTL2_OUTDIV_Pos) /*!< For output divider is 1 \hideinitializer */
344 #define CLK_PLLCTL_NO_2 (0x1UL << CLK_PLLCTL2_OUTDIV_Pos) /*!< For output divider is 2 \hideinitializer */
345 #define CLK_PLLCTL_NO_4 (0x3UL << CLK_PLLCTL2_OUTDIV_Pos) /*!< For output divider is 4 \hideinitializer */
346
347 #define CLK_PLLCTL_48MHz (CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 16UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output \hideinitializer */
348 #define CLK_PLLCTL_64MHz (CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 64MHz PLL output \hideinitializer */
349 #define CLK_PLLCTL_72MHz (CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output \hideinitializer */
350 #define CLK_PLLCTL_80MHz (CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output \hideinitializer */
351 #define CLK_PLLCTL_96MHz (CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 48UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 96MHz PLL output \hideinitializer */
352 #define CLK_PLLCTL_144MHz (CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output \hideinitializer */
353 #define CLK_PLLCTL_160MHz (CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output \hideinitializer */
354 #define CLK_PLLCTL_192MHz (CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output \hideinitializer */
355
356
357 /*---------------------------------------------------------------------------------------------------------*/
358 /* MODULE constant definitions. */
359 /*---------------------------------------------------------------------------------------------------------*/
360
361 /* APBCLK(31:29)|CLKSEL(28:26)|CLKSEL_Msk(25:23) |CLKSEL_Pos(22:18)|CLKDIV(17:16)|CLKDIV_Msk(15:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
362
363 #define MODULE_APBCLK(x) (((x) >> 29) & 0x07UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2, 0x4:AHBCLK1, 0x5:LPSCC_CLKEN0 \hideinitializer */
364 #define MODULE_CLKSEL(x) (((x) >> 26) & 0x07UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4, 0x5:LPSCC_CLKSEL0 \hideinitializer */
365 #define MODULE_CLKSEL_Msk(x) (((x) >> 23) & 0x07UL) /*!< Calculate CLKSEL mask BIT NUMBER on MODULE index \hideinitializer */
366 #define MODULE_CLKSEL_Pos(x) (((x) >> 18) & 0x1FUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
367 #define MODULE_CLKDIV(x) (((x) >> 16) & 0x03UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV4, 0x2:CLKDIV5, 0x3:LPSCC_CLKDIV0 \hideinitializer */
368 #define MODULE_CLKDIV_Msk(x) (((x) >> 10) & 0x3FUL) /*!< Calculate CLKDIV mask BIT NUMBER on MODULE index \hideinitializer */
369 #define MODULE_CLKDIV_Pos(x) (((x) >> 5) & 0x1FUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
370 #define MODULE_IP_EN_Pos(x) (((x) >> 0) & 0x1FUL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index \hideinitializer */
371 #define MODULE_NoMsk (0x0UL) /*!< Not mask on MODULE index \hideinitializer */
372 #define NA MODULE_NoMsk /*!< Not Available \hideinitializer */
373
374 #define MODULE_APBCLK_ENC(x) (((x) & 0x07UL) << 29) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2, 0x4:AHBCLK1, 0x5:LPSCC_CLKEN0 \hideinitializer */
375 #define MODULE_CLKSEL_ENC(x) (((x) & 0x07UL) << 26) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4, 0x5:LPSCC_CLKSEL0 \hideinitializer */
376 #define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 23) /*!< CLKSEL mask BIT NUMBER on MODULE index \hideinitializer */
377 #define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1FUL) << 18) /*!< CLKSEL position offset on MODULE index \hideinitializer */
378 #define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 16) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV4, 0x2:CLKDIV5, 0x3:LPSCC_CLKDIV0 \hideinitializer */
379 #define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0x3FUL) << 10) /*!< CLKDIV mask BIT NUMBER on MODULE index \hideinitializer */
380 #define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1FUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */
381 #define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1FUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */
382
383 /* AHBCLK */
384 /* CLKEN reg | CLKSEL reg | CLKSEL mask | CLKSEL pos | CLKDIV reg | CLKDIV mask | CLKDIV pos | CLKEN pos */
385 #define PDMA0_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(1UL<<0)) /*!< PDMA0 Module */
386 #define ISP_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(2UL<<0)) /*!< ISP Module */
387 #define EBI_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(3UL<<0)) /*!< EBI Module */
388 #define ST_MODULE ((0UL<<29)|(0UL<<26) |(3UL<<23) |(3UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(4UL<<0)) /*!< ST Module */
389 #define CRC_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(7UL<<0)) /*!< CRC Module */
390 #define CRPT_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(12UL<<0)) /*!< CRPT Module */
391 #define KS_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(13UL<<0)) /*!< KS Module */
392 #define USBH_MODULE ((0UL<<29)|(0UL<<26) |(1UL<<23) |(8UL<<18) |(0UL<<16) |(4UL<<10) |(4UL<<5) |(16UL<<0)) /*!< USBH Module */
393 #define GPA_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(24UL<<0)) /*!< GPA Module */
394 #define GPB_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(25UL<<0)) /*!< GPB Module */
395 #define GPC_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(26UL<<0)) /*!< GPC Module */
396 #define GPD_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(27UL<<0)) /*!< GPD Module */
397 #define GPE_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(28UL<<0)) /*!< GPE Module */
398 #define GPF_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(29UL<<0)) /*!< GPF Module */
399 #define GPG_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(30UL<<0)) /*!< GPG Module */
400 #define GPH_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(31UL<<0)) /*!< GPH Module */
401
402 /* APBCLK0 */
403 #define RTC_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(1UL<<0)) /*!< RTC Module */
404 #define TMR0_MODULE ((1UL<<29)|(1UL<<26) |(3UL<<23) |(8UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(2UL<<0)) /*!< TMR0 Module */
405 #define TMR1_MODULE ((1UL<<29)|(1UL<<26) |(3UL<<23) |(12UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(3UL<<0)) /*!< TMR1 Module */
406 #define TMR2_MODULE ((1UL<<29)|(1UL<<26) |(3UL<<23) |(16UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(4UL<<0)) /*!< TMR2 Module */
407 #define TMR3_MODULE ((1UL<<29)|(1UL<<26) |(3UL<<23) |(20UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(5UL<<0)) /*!< TMR3 Module */
408 #define CLKO_MODULE ((1UL<<29)|(1UL<<26) |(4UL<<23) |(4UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(6UL<<0)) /*!< CLKO Module */
409 #define ACMP01_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(7UL<<0)) /*!< ACMP01 Module */
410 #define I2C0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(8UL<<0)) /*!< I2C0 Module */
411 #define I2C1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(9UL<<0)) /*!< I2C1 Module */
412 #define I2C2_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(10UL<<0)) /*!< I2C2 Module */
413 #define I2C3_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(11UL<<0)) /*!< I2C3 Module */
414 #define QSPI0_MODULE ((1UL<<29)|(2UL<<26) |(2UL<<23) |(2UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(12UL<<0)) /*!< QSPI0 Module */
415 #define SPI0_MODULE ((1UL<<29)|(2UL<<26) |(3UL<<23) |(4UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(13UL<<0)) /*!< SPI0 Module */
416 #define SPI1_MODULE ((1UL<<29)|(2UL<<26) |(3UL<<23) |(12UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(14UL<<0)) /*!< SPI1 Module */
417 #define SPI2_MODULE ((1UL<<29)|(3UL<<26) |(3UL<<23) |(8UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(15UL<<0)) /*!< SPI2 Module */
418 #define UART0_MODULE ((1UL<<29)|(4UL<<26) |(3UL<<23) |(0UL<<18) |(0UL<<16) |(4UL<<10) |(8UL<<5) |(16UL<<0)) /*!< UART0 Module */
419 #define UART1_MODULE ((1UL<<29)|(4UL<<26) |(3UL<<23) |(4UL<<18) |(0UL<<16) |(4UL<<10) |(12UL<<5) |(17UL<<0)) /*!< UART1 Module */
420 #define UART2_MODULE ((1UL<<29)|(4UL<<26) |(3UL<<23) |(8UL<<18) |(1UL<<16) |(4UL<<10) |(0UL<<5) |(18UL<<0)) /*!< UART2 Module */
421 #define UART3_MODULE ((1UL<<29)|(4UL<<26) |(3UL<<23) |(12UL<<18) |(1UL<<16) |(4UL<<10) |(4UL<<5) |(19UL<<0)) /*!< UART3 Module */
422 #define UART4_MODULE ((1UL<<29)|(4UL<<26) |(3UL<<23) |(16UL<<18) |(1UL<<16) |(4UL<<10) |(8UL<<5) |(20UL<<0)) /*!< UART4 Module */
423 #define UART5_MODULE ((1UL<<29)|(4UL<<26) |(3UL<<23) |(20UL<<18) |(1UL<<16) |(4UL<<10) |(12UL<<5) |(21UL<<0)) /*!< UART5 Module */
424 #define UART6_MODULE ((1UL<<29)|(4UL<<26) |(3UL<<23) |(24UL<<18) |(1UL<<16) |(4UL<<10) |(16UL<<5) |(22UL<<0)) /*!< UART6 Module */
425 #define UART7_MODULE ((1UL<<29)|(4UL<<26) |(3UL<<23) |(28UL<<18) |(1UL<<16) |(4UL<<10) |(20UL<<5) |(23UL<<0)) /*!< UART7 Module */
426 #define OTG_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(26UL<<0)) /*!< OTG Module */
427 #define USBD_MODULE ((1UL<<29)|(0UL<<26) |(1UL<<23) |(8UL<<18) |(0UL<<16) |(4UL<<10) |(4UL<<5) |(27UL<<0)) /*!< USBD Module */
428 #define EADC0_MODULE ((1UL<<29)|(0UL<<26) |(2UL<<23) |(10UL<<18) |(0UL<<16) |(8UL<<10) |(16UL<<5) |(28UL<<0)) /*!< EADC0 Module */
429 #define TRNG_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(31UL<<0)) /*!< TRNG Module */
430
431 /* APBCLK1 */
432 #define SPI3_MODULE ((2UL<<29)|(3UL<<26) |(3UL<<23) |(12UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(6UL<<0)) /*!< SPI3 Module */
433 #define USCI0_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(8UL<<0)) /*!< USCI0 Module */
434 #define USCI1_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(9UL<<0)) /*!< USCI1 Module */
435 #define WWDT_MODULE ((2UL<<29)|(1UL<<26) |(2UL<<23) |(30UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(11UL<<0)) /*!< WWDT Module */
436 #define DAC_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(12UL<<0)) /*!< DAC Module */
437 #define EPWM0_MODULE ((2UL<<29)|(2UL<<26) |(1UL<<23) |(0UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(16UL<<0)) /*!< EPWM0 Module */
438 #define EPWM1_MODULE ((2UL<<29)|(2UL<<26) |(1UL<<23) |(1UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(17UL<<0)) /*!< EPWM1 Module */
439 #define EQEI0_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(22UL<<0)) /*!< EQEI0 Module */
440 #define EQEI1_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(23UL<<0)) /*!< EQEI1 Module */
441 #define TK_MODULE ((2UL<<29)|(2UL<<26) |(1UL<<23) |(7UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(25UL<<0)) /*!< TK Module */
442 #define ECAP0_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(26UL<<0)) /*!< ECAP0 Module */
443 #define ECAP1_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(27UL<<0)) /*!< ECAP1 Module */
444
445 /* APBCLK2 */
446 #define ACMP2_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(7UL<<0)) /*!< ACMP2 Module */
447 #define PWM0_MODULE ((3UL<<29)|(3UL<<26) |(1UL<<23) |(6UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(8UL<<0)) /*!< PWM0 Module */
448 #define PWM1_MODULE ((3UL<<29)|(3UL<<26) |(1UL<<23) |(7UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(9UL<<0)) /*!< PWM1 Module */
449 #define UTCPD0_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(15UL<<0)) /*!< UTCPD0 Module */
450
451 /* AHBCLK1 */
452 #define CANRAM0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(16UL<<0)) /*!< CANRAM0 Module */
453 #define CANRAM1_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(17UL<<0)) /*!< CANRAM1 Module */
454 #define CANFD0_MODULE ((4UL<<29)|(0UL<<26) |(2UL<<23) |(24UL<<18) |(2UL<<16) |(4UL<<10) |(0UL<<5) |(20UL<<0)) /*!< CANFD0 Module */
455 #define CANFD1_MODULE ((4UL<<29)|(0UL<<26) |(2UL<<23) |(26UL<<18) |(2UL<<16) |(4UL<<10) |(4UL<<5) |(21UL<<0)) /*!< CANFD1 Module */
456 #define HCLK1_MODULE ((4UL<<29)|(0UL<<26) |(3UL<<23) |(12UL<<18) |(3UL<<16) |(4UL<<10) |(0UL<<5) |(28UL<<0)) /*!< HCLK1 Module */
457
458 /* LPSCC_CLKEN0 */
459 #define LPPDMA0_MODULE ((5UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(0UL<<0)) /*!< LPPDMA0 Module */
460 #define LPGPIO_MODULE ((5UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(1UL<<0)) /*!< LPGPIO Module */
461 #define LPSRAM_MODULE ((5UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(2UL<<0)) /*!< LPSRAM Module */
462 #define WDT_MODULE ((5UL<<29)|(5UL<<26) |(2UL<<23) |(24UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(16UL<<0)) /*!< WDT Module */
463 #define LPSPI0_MODULE ((5UL<<29)|(5UL<<26) |(2UL<<23) |(2UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(17UL<<0)) /*!< LPSPI0 Module */
464 #define LPI2C0_MODULE ((5UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(18UL<<0)) /*!< LPI2C0 Module */
465 #define LPUART0_MODULE ((5UL<<29)|(5UL<<26) |(2UL<<23) |(0UL<<18) |(3UL<<16) |(4UL<<10) |(8UL<<5) |(19UL<<0)) /*!< LPUART0 Module */
466 #define LPTMR0_MODULE ((5UL<<29)|(5UL<<26) |(3UL<<23) |(8UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(20UL<<0)) /*!< LPTMR0 Module */
467 #define LPTMR1_MODULE ((5UL<<29)|(5UL<<26) |(3UL<<23) |(12UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(21UL<<0)) /*!< LPTMR1 Module */
468 #define TTMR0_MODULE ((5UL<<29)|(5UL<<26) |(2UL<<23) |(4UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(22UL<<0)) /*!< TTMR0 Module */
469 #define TTMR1_MODULE ((5UL<<29)|(5UL<<26) |(2UL<<23) |(6UL<<18) |(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(23UL<<0)) /*!< TTMR1 Module */
470 #define LPADC0_MODULE ((5UL<<29)|(5UL<<26) |(2UL<<23) |(16UL<<18) |(3UL<<16) |(4UL<<10) |(16UL<<5) |(24UL<<0)) /*!< LPADC0 Module */
471 #define OPA_MODULE ((5UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<23)|(MODULE_NoMsk<<18)|(MODULE_NoMsk<<16)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5) |(27UL<<0)) /*!< OPA Module */
472
473 /*---------------------------------------------------------------------------------------------------------*/
474 /* PDMSEL constant definitions. */
475 /*---------------------------------------------------------------------------------------------------------*/
476 #define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Normal Power-down mode 0 \hideinitializer */
477 #define CLK_PMUCTL_PDMSEL_NPD0 (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Normal Power-down mode 0 \hideinitializer */
478 #define CLK_PMUCTL_PDMSEL_NPD1 (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Normal Power-down mode 1 \hideinitializer */
479 #define CLK_PMUCTL_PDMSEL_NPD2 (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Normal Power-down mode 2 \hideinitializer */
480 #define CLK_PMUCTL_PDMSEL_NPD3 (0x3UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Normal Power-down mode 3 \hideinitializer */
481 #define CLK_PMUCTL_PDMSEL_NPD4 (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Normal Power-down mode 4 \hideinitializer */
482 #define CLK_PMUCTL_PDMSEL_NPD5 (0x5UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Normal Power-down mode 5 \hideinitializer */
483 #define CLK_PMUCTL_PDMSEL_SPD0 (0x8UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 0 \hideinitializer */
484 #define CLK_PMUCTL_PDMSEL_SPD1 (0x9UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 1 \hideinitializer */
485 #define CLK_PMUCTL_PDMSEL_SPD2 (0xAUL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode 2 \hideinitializer */
486 #define CLK_PMUCTL_PDMSEL_DPD0 (0xCUL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Deep Power-down mode 0 \hideinitializer */
487 #define CLK_PMUCTL_PDMSEL_DPD1 (0xDUL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Deep Power-down mode 1 \hideinitializer */
488
489 /*---------------------------------------------------------------------------------------------------------*/
490 /* LSRETSEL constant definitions. */
491 /*---------------------------------------------------------------------------------------------------------*/
492 #define CLK_SPDLSRETSEL_NO (0x0UL << CLK_PMUCTL_LSRETSEL_Pos) /*!< No LPSRAM retention when chip enter NPD3/NPD4/NPD5/SPDx mode \hideinitializer */
493 #define CLK_SPDLSRETSEL_8K (0x1UL << CLK_PMUCTL_LSRETSEL_Pos) /*!< 8K LPSRAM retention when chip enter NPD3/NPD4/NPD5/SPDx mode \hideinitializer */
494
495 /*---------------------------------------------------------------------------------------------------------*/
496 /* WKTMRIS constant definitions. */
497 /*---------------------------------------------------------------------------------------------------------*/
498 #define CLK_PMUWKCTL_WKTMRIS_512 (0x0UL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 LIRC clocks (16 ms) \hideinitializer */
499 #define CLK_PMUWKCTL_WKTMRIS_1024 (0x1UL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 LIRC clocks (32 ms) \hideinitializer */
500 #define CLK_PMUWKCTL_WKTMRIS_2048 (0x2UL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 2048 LIRC clocks (64 ms) \hideinitializer */
501 #define CLK_PMUWKCTL_WKTMRIS_4096 (0x3UL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 LIRC clocks (128 ms) \hideinitializer */
502 #define CLK_PMUWKCTL_WKTMRIS_8192 (0x4UL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 LIRC clocks (256 ms) \hideinitializer */
503 #define CLK_PMUWKCTL_WKTMRIS_16384 (0x5UL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 LIRC clocks (512 ms) \hideinitializer */
504 #define CLK_PMUWKCTL_WKTMRIS_32768 (0x6UL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 32768 LIRC clocks (1024 ms) \hideinitializer */
505 #define CLK_PMUWKCTL_WKTMRIS_65536 (0x7UL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 LIRC clocks (2048 ms) \hideinitializer */
506 #define CLK_PMUWKCTL_WKTMRIS_131072 (0x8UL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 131072 LIRC clocks (4096 ms) \hideinitializer */
507 #define CLK_PMUWKCTL_WKTMRIS_262144 (0x9UL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 262144 LIRC clocks (8192 ms) \hideinitializer */
508 #define CLK_PMUWKCTL_WKTMRIS_524288 (0xAUL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 524288 LIRC clocks (16384 ms) \hideinitializer */
509 #define CLK_PMUWKCTL_WKTMRIS_1048576 (0xBUL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1048576 LIRC clocks (32768 ms) \hideinitializer */
510 #define CLK_PMUWKCTL_WKTMRIS_2097152 (0xCUL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 2097152 LIRC clocks (65536 ms) \hideinitializer */
511 #define CLK_PMUWKCTL_WKTMRIS_4194304 (0xDUL << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4194304 LIRC clocks (131072 ms) \hideinitializer */
512
513 /*---------------------------------------------------------------------------------------------------------*/
514 /* SWKDBCLKSEL constant definitions. */
515 /*---------------------------------------------------------------------------------------------------------*/
516 #define CLK_PWDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */
517 #define CLK_PWDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */
518 #define CLK_PWDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */
519 #define CLK_PWDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */
520 #define CLK_PWDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */
521 #define CLK_PWDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */
522 #define CLK_PWDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */
523 #define CLK_PWDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */
524 #define CLK_PWDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */
525 #define CLK_PWDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */
526 #define CLK_PWDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */
527 #define CLK_PWDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */
528 #define CLK_PWDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */
529 #define CLK_PWDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */
530 #define CLK_PWDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */
531 #define CLK_PWDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */
532
533 /*---------------------------------------------------------------------------------------------------------*/
534 /* DPD Pin (WKPIN) Rising/Falling Edge Wake-up Enable constant definitions. */
535 /*---------------------------------------------------------------------------------------------------------*/
536 #define CLK_DPDWKPIN_0 (0x0UL) /*!< Wake-up pin0 (GPC.0) at Deep Power-down mode */
537 #define CLK_DPDWKPIN_1 (0x1UL) /*!< Wake-up pin1 (GPB.0) at Deep Power-down mode */
538 #define CLK_DPDWKPIN_2 (0x2UL) /*!< Wake-up pin2 (GPB.2) at Deep Power-down mode */
539 #define CLK_DPDWKPIN_3 (0x3UL) /*!< Wake-up pin3 (GPB.12) at Deep Power-down mode */
540 #define CLK_DPDWKPIN_4 (0x4UL) /*!< Wake-up pin4 (GPF.6) at Deep Power-down mode */
541 #define CLK_DPDWKPIN_5 (0x5UL) /*!< Wake-up pin5 (GPA.12) at Deep Power-down mode */
542
543 #define CLK_DPDWKPIN_DISABLE (0x0UL)
544 #define CLK_DPDWKPIN_RISING (0x1UL)
545 #define CLK_DPDWKPIN_FALLING (0x2UL)
546 #define CLK_DPDWKPIN_BOTHEDGE (0x3UL)
547
548 #define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN0_Msk) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */
549 #define CLK_DISABLE_DPDWKPIN0(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN0_Msk) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */
550 #define CLK_DISABLE_DPDWKPIN1(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN1_Msk) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */
551 #define CLK_DISABLE_DPDWKPIN2(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN2_Msk) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */
552 #define CLK_DISABLE_DPDWKPIN3(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN3_Msk) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */
553 #define CLK_DISABLE_DPDWKPIN4(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN4_Msk) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */
554 #define CLK_DISABLE_DPDWKPIN5(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKPINEN5_Msk) /*!< Disable Wake-up pin5 (GPA.12) at Deep Power-down mode \hideinitializer */
555 #define CLK_DISABLE_SPDACMP(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_ACMPWKEN_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */
556 #define CLK_ENABLE_SPDACMP(void) (CLK->PMUWKCTL |= CLK_PMUWKCTL_ACMPWKEN_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */
557 #define CLK_DISABLE_RTCWK(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
558 #define CLK_ENABLE_RTCWK(void) (CLK->PMUWKCTL |= CLK_PMUWKCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
559
560 /*---------------------------------------------------------------------------------------------------------*/
561 /* SPD Pin (WKIO) Rising/Falling Edge Wake-up Enable constant definitions. */
562 /*---------------------------------------------------------------------------------------------------------*/
563 #define CLK_SPDWKPIN_ENABLE (0x1UL << CLK_PAPWCTL_WKEN0_Pos) /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */
564 #define CLK_SPDWKPIN_RISING (0x1UL << CLK_PAPWCTL_PRWKEN0_Pos) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */
565 #define CLK_SPDWKPIN_FALLING (0x1UL << CLK_PAPWCTL_PFWKEN0_Pos) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */
566 #define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << CLK_PAPWCTL_DBEN0_Pos) /*!< Enable Standby power-down pin De-bounce function \hideinitializer */
567 #define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << CLK_PAPWCTL_DBEN0_Pos) /*!< Disable Standby power-down pin De-bounce function \hideinitializer */
568
569 #define CLK_SPDSRETSEL_NO (0x0UL << CLK_PMUCTL_SRETSEL_Pos) /*!< No SRAM retention when chip enter NPD3/NPD4/NPD5/SPDx mode \hideinitializer */
570 #define CLK_SPDSRETSEL_8K (0x1UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 8K SRAM retention when chip enter NPD3/NPD4/NPD5/SPDx mode \hideinitializer */
571 #define CLK_SPDSRETSEL_24K (0x2UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 24K SRAM retention when chip enter NPD3/NPD4/NPD5/SPDx mode \hideinitializer */
572 #define CLK_SPDSRETSEL_40K (0x3UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 40K SRAM retention when chip enter NPD3/NPD4/NPD5/SPDx mode \hideinitializer */
573 #define CLK_SPDSRETSEL_72K (0x4UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 72K SRAM retention when chip enter NPD3/NPD4/NPD5/SPDx mode \hideinitializer */
574 #define CLK_SPDSRETSEL_104K (0x5UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 104K SRAM retention when chip enter NPD3/NPD4/NPD5/SPDx mode \hideinitializer */
575 #define CLK_SPDSRETSEL_168K (0x6UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 168K SRAM retention when chip enter NPD3/NPD4/NPD5/SPDx mode \hideinitializer */
576
577 #define CLK_DISABLE_WKTMR(void) (CLK->PMUWKCTL &= ~CLK_PMUWKCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
578 #define CLK_ENABLE_WKTMR(void) (CLK->PMUWKCTL |= CLK_PMUWKCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */
579
580 #define CLK_TIMEOUT_ERR (-1) /*!< Clock timeout error value \hideinitializer */
581
582 /*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
583
584 extern int32_t g_CLK_i32ErrCode;
585
586 /** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
587 @{
588 */
589
590 /**
591 * @brief Set Wake-up Timer Time-out Interval
592 *
593 * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be
594 * - \ref CLK_PMUWKCTL_WKTMRIS_512
595 * - \ref CLK_PMUWKCTL_WKTMRIS_1024
596 * - \ref CLK_PMUWKCTL_WKTMRIS_2048
597 * - \ref CLK_PMUWKCTL_WKTMRIS_4096
598 * - \ref CLK_PMUWKCTL_WKTMRIS_8192
599 * - \ref CLK_PMUWKCTL_WKTMRIS_16384
600 * - \ref CLK_PMUWKCTL_WKTMRIS_32768
601 * - \ref CLK_PMUWKCTL_WKTMRIS_65536
602 * - \ref CLK_PMUWKCTL_WKTMRIS_131072
603 * - \ref CLK_PMUWKCTL_WKTMRIS_262144
604 * - \ref CLK_PMUWKCTL_WKTMRIS_524288
605 * - \ref CLK_PMUWKCTL_WKTMRIS_1048576
606 * - \ref CLK_PMUWKCTL_WKTMRIS_2097152
607 * - \ref CLK_PMUWKCTL_WKTMRIS_4194304
608 *
609 * @return None
610 *
611 * @details This function set Wake-up Timer Time-out Interval.
612 *
613 * \hideinitializer
614 */
615 #define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUWKCTL = (CLK->PMUWKCTL & ~CLK_PMUWKCTL_WKTMRIS_Msk) | u32Interval)
616
617 /**
618 * @brief Set De-bounce Sampling Cycle Time
619 *
620 * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be
621 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_1
622 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_2
623 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_4
624 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_8
625 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_16
626 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_32
627 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_64
628 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_128
629 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_256
630 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_2x256
631 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_4x256
632 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_8x256
633 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_16x256
634 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_32x256
635 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_64x256
636 * - \ref CLK_PWDBCTL_SWKDBCLKSEL_128x256
637 *
638 * @return None
639 *
640 * @details This function set Set De-bounce Sampling Cycle Time.
641 *
642 * \hideinitializer
643 */
644 #define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->PWDBCTL = (u32CycleSel))
645
646 /*---------------------------------------------------------------------------------------------------------*/
647 /* static inline functions */
648 /*---------------------------------------------------------------------------------------------------------*/
649 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
650 __STATIC_INLINE int32_t CLK_SysTickDelay(uint32_t us);
651 __STATIC_INLINE int32_t CLK_SysTickLongDelay(uint32_t us);
652
653 /**
654 * @brief This function execute delay function.
655 * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
656 * 72MHz => 233016us, 50MHz => 335544us,
657 * 48MHz => 349525us, 28MHz => 699050us ...
658 * @return Delay success or not
659 * @retval 0 Success, target delay time reached
660 * @retval CLK_TIMEOUT_ERR Delay function execute failed due to SysTick stop working
661 * @details Use the SysTick to generate the delay time and the unit is in us.
662 * The SysTick clock source is from HCLK, i.e the same as system core clock.
663 */
CLK_SysTickDelay(uint32_t us)664 __STATIC_INLINE int32_t CLK_SysTickDelay(uint32_t us)
665 {
666 /* The u32TimeOutCnt value must be greater than the max delay time of 1398ms if HCLK=12MHz */
667 uint32_t u32TimeOutCnt = SystemCoreClock * 2;
668
669 SysTick->LOAD = us * CyclesPerUs;
670 SysTick->VAL = 0x0UL;
671 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
672
673 /* Waiting for down-count to zero */
674 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
675 {
676 if(--u32TimeOutCnt == 0)
677 {
678 break;
679 }
680 }
681
682 /* Disable SysTick counter */
683 SysTick->CTRL = 0UL;
684
685 if(u32TimeOutCnt == 0)
686 return CLK_TIMEOUT_ERR;
687 else
688 return 0;
689 }
690
691 /**
692 * @brief This function execute long delay function.
693 * @param[in] us Delay time.
694 * @return Delay success or not
695 * @retval 0 Success, target delay time reached
696 * @retval CLK_TIMEOUT_ERR Delay function execute failed due to SysTick stop working
697 * @details Use the SysTick to generate the long delay time and the UNIT is in us.
698 * The SysTick clock source is from HCLK, i.e the same as system core clock.
699 * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
700 */
CLK_SysTickLongDelay(uint32_t us)701 __STATIC_INLINE int32_t CLK_SysTickLongDelay(uint32_t us)
702 {
703 /* The u32TimeOutCnt value must be greater than the max delay time of 1398ms if HCLK=12MHz */
704 uint32_t u32TimeOutCnt = SystemCoreClock * 2;
705 uint32_t delay;
706
707 /* It should <= 349525us for each delay loop */
708 delay = 349525UL;
709
710 do
711 {
712 if(us > delay)
713 {
714 us -= delay;
715 }
716 else
717 {
718 delay = us;
719 us = 0UL;
720 }
721
722 SysTick->LOAD = delay * CyclesPerUs;
723 SysTick->VAL = (0x0UL);
724 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
725
726 /* Waiting for down-count to zero */
727 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
728 {
729 if(--u32TimeOutCnt == 0)
730 {
731 break;
732 }
733 }
734
735 /* Disable SysTick counter */
736 SysTick->CTRL = 0UL;
737
738 if(u32TimeOutCnt == 0)
739 return CLK_TIMEOUT_ERR;
740 else
741 return 0;
742 }
743 while(us > 0UL);
744 }
745
746
747 void CLK_DisableCKO(void);
748 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
749 void CLK_PowerDown(void);
750 void CLK_Idle(void);
751 uint32_t CLK_GetHXTFreq(void);
752 uint32_t CLK_GetLXTFreq(void);
753 uint32_t CLK_GetHCLKFreq(void);
754 uint32_t CLK_GetPCLK0Freq(void);
755 uint32_t CLK_GetPCLK1Freq(void);
756 uint32_t CLK_GetCPUFreq(void);
757 uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
758 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
759 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
760 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
761 void CLK_EnableXtalRC(uint32_t u32ClkMask);
762 void CLK_DisableXtalRC(uint32_t u32ClkMask);
763 void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
764 void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
765 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
766 void CLK_DisablePLL(void);
767 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
768 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
769 void CLK_DisableSysTick(void);
770 void CLK_SetPowerDownMode(uint32_t u32PDMode);
771 void CLK_EnableDPDWKPin(uint32_t u32Pin, uint32_t u32TriggerType);
772 uint32_t CLK_GetPMUWKSrc(void);
773 void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
774 uint32_t CLK_GetPLLClockFreq(void);
775 uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
776 uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
777 uint32_t CLK_GetMIRCFreq(void);
778 void CLK_DisableMIRC(void);
779 uint32_t CLK_EnableMIRC(uint32_t u32MircFreq);
780 uint32_t CLK_GetHCLK1Freq(void);
781 uint32_t CLK_GetPCLK2Freq(void);
782
783 /*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
784
785 /*@}*/ /* end of group CLK_Driver */
786
787 /*@}*/ /* end of group Standard_Driver */
788
789 #ifdef __cplusplus
790 }
791 #endif
792
793 #endif /* __CLK_H__ */
794
795 /*** (C) COPYRIGHT 2023 Nuvoton Technology Corp. ***/
796
