1 /**************************************************************************//** 2 * @file trng_reg.h 3 * @version V1.00 4 * @brief TRNG register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __TRNG_REG_H__ 10 #define __TRNG_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** @addtogroup REGISTER Control Register 17 18 @{ 19 20 */ 21 22 23 /*---------------------- True Random Number Generator -------------------------*/ 24 /** 25 @addtogroup TRNG True Random Number Generator(TRNG) 26 Memory Mapped Structure for TRNG Controller 27 @{ */ 28 29 typedef struct 30 { 31 32 33 /** 34 * @var TRNG_T::CTL 35 * Offset: 0x00 TRNG Control Register 36 * --------------------------------------------------------------------------------------------------- 37 * |Bits |Field |Descriptions 38 * | :----: | :----: | :---- | 39 * |[0] |LDOEN |LDO Enable Bit 40 * | | |0 = LDO Disabled. 41 * | | |1 = LDO Enabled. 42 * |[1] |NRST |Negative-edge Trigger Reset 43 * | | |0 = Keep reset. 44 * | | |1 = No reset. 45 * |[2] |TRNGEN |True Random Number Generator Macro Enable Bit 46 * | | |0 = TRNG macro Disabled. 47 * | | |1 = TRNG macro Enabled. 48 * |[3] |START |True Random Number Generator Start 49 * | | |0 = No effect. 50 * | | |1 = Start TRNG. 51 * | | |Note: Do not enable START (TRNG_CTL[3]) and KATEN (TRNG_CTL[24]) at the same time 52 * | | |This bit is always 0 when it is read back. 53 * |[5:4] |MODE |Random Bit Generator Output Selection 54 * | | |00 = Output data is from entropy (32-bits). 55 * | | |01 = Output data is from NRBG (128-bits). 56 * | | |10 = Output data is from DRBG (128-bits). 57 * | | |11 = Reserved. 58 * |[8] |INSTANT |CTR_DRBG User Manual Instant Function 59 * | | |0 = No effect. 60 * | | |1 = Enable CTR_DRBG instant function. 61 * |[9] |RESEED |CTR_DRBG User Manual Reseed Function 62 * | | |0 = No effect. 63 * | | |1 = Enable CTR_DRBG reseed function. 64 * |[10] |UPDATE |CTR_DRBG User Manual Update Function 65 * | | |0 = No effect. 66 * | | |1 = Enable CTR_DRBG update function. 67 * |[24] |KATEN |CTR_DRBG Known Answer Test Enable Bit 68 * | | |0 = Disabled. 69 * | | |1 = Enabled. 70 * | | |Note: Do not enable START (TRNG_CTL[3]) and KATEN (TRNG_CTL[24]) at the same time. 71 * |[26:25] |KATSEL |CTR_DRBG Known Answer Test Selection 72 * | | |0 = Instantiation testing. 73 * | | |1 = Reseed testing. 74 * | | |2 = Generation testing. 75 * | | |Others = reserved. 76 * |[30] |ERRIEN |TRNG Error Interrupt Enable Bit 77 * | | |0 = Error interrupt Disabled. 78 * | | |1 = Error interrupt Enabled. 79 * |[31] |DVIEN |Data Valid Interrupt Enable Bit 80 * | | |0 = Interrupt Disabled. 81 * | | |1 = Interrupt Enabled. 82 * @var TRNG_T::CFG 83 * Offset: 0x04 TRNG Configure Register 84 * --------------------------------------------------------------------------------------------------- 85 * |Bits |Field |Descriptions 86 * | :----: | :----: | :---- | 87 * |[25:0] |RESEED_INTERVAL|Reseed Interval 88 * | | |Maximum number of requests between reseeds. 89 * | | |The value is 1 ~ 2^25 . 90 * | | |Note: If users select out of this range (1 ~ 2^25 ), reseed_interval will be set the maximum value = 2^25. 91 * |[31:28] |CTRLEN |CTR_DRBG Bits Length Per Request 92 * | | |CTR_DRBG bits length per request = (2^CTRLEN -4) x block length. 93 * | | |CTR_DRBG block length is 128-bits (2^7). 94 * | | |CTRLEN is 4~12. 95 * | | |Note: If users select out of this range (4~12), CTRLEN will be set the maximum value = 12. 96 * @var TRNG_T::STS 97 * Offset: 0x08 TRNG Status Register 98 * --------------------------------------------------------------------------------------------------- 99 * |Bits |Field |Descriptions 100 * | :----: | :----: | :---- | 101 * |[0] |LDORDY |LDO Ready Signal 102 * | | |0 = LDO is not ready. 103 * | | |1 = LDO is ready. 104 * |[1] |TRNGRDY |TRNG Ready Signal 105 * | | |0 = True random number generator is not ready. 106 * | | |1 = True random number generator is ready. 107 * |[4] |ESSUT |Entropy Source Start-Up Test 108 * | | |0 = Entropy source is still under testing or test fail. 109 * | | |1 = Test pass. 110 * |[5] |ESRCT |Entropy Source Repetition Count Test 111 * | | |0 = Entropy source is still under testing or test fail. 112 * | | |1 = Test pass. 113 * |[6] |ESAPT |Entropy Source Adaptive Proportion Test 114 * | | |0 = Entropy source is still under testing or test fail. 115 * | | |1 = Test pass. 116 * |[27] |KATPASS |CTR_DRBG Known Answer Test Pass 117 * | | |0 = Test fail. 118 * | | |1 = Test pass. 119 * | | |Note: When users enable KATEN (TRNG_CTL[24]), they can check this bit after DVIF (TRNG_STS[31]) become '1'. 120 * |[30] |ERRIF |TRNG Error Interrupt Flag 121 * | | |0 = No TRNG error. 122 * | | |1 = TRNGRDY became '0' over 1ms , TRNG error interrupt. 123 * |[31] |DVIF |Data Valid Interrupt Flag 124 * | | |0 = Data is invalid. 125 * | | |1 = Data is valid. A valid random number can be read form TRNG_DATAx. 126 * | | |Note: This bit is cleared to '0' by reading TRNG_DATA0 ~ TRNG_DATA3. 127 * | | |If MODE (TRNG_CTL[5:4]) = '00', this bit is cleared to '0' by reading TRNG_DATA0. 128 * @var TRNG_T::DATA0 129 * Offset: 0x0C TRNG Data Output Word 0 Register 130 * --------------------------------------------------------------------------------------------------- 131 * |Bits |Field |Descriptions 132 * | :----: | :----: | :---- | 133 * |[31:0] |DATA |True Random Number Generator Data (Read Only) 134 * | | |The DATA stores the output data generated by TRNG, it can be read when DVIF (TRNG_STS[31]) become 1 and can be read only once. 135 * | | |TRNG_DATA0 stores Entropy / NRBG word 0 / DRBG word 0. 136 * | | |TRNG_DATA1 stores NRBG word 1 / DRBG word 1. 137 * | | |TRNG_DATA2 stores NRBG word 2 / DRBG word 2. 138 * | | |TRNG_DATA3 stores NRBG word 3 / DRBG word 3. 139 * @var TRNG_T::DATA1 140 * Offset: 0x10 TRNG Data Output Word 1 Register 141 * --------------------------------------------------------------------------------------------------- 142 * |Bits |Field |Descriptions 143 * | :----: | :----: | :---- | 144 * |[31:0] |DATA |True Random Number Generator Data (Read Only) 145 * | | |The DATA stores the output data generated by TRNG, it can be read when DVIF (TRNG_STS[31]) become 1 and can be read only once. 146 * | | |TRNG_DATA0 stores Entropy / NRBG word 0 / DRBG word 0. 147 * | | |TRNG_DATA1 stores NRBG word 1 / DRBG word 1. 148 * | | |TRNG_DATA2 stores NRBG word 2 / DRBG word 2. 149 * | | |TRNG_DATA3 stores NRBG word 3 / DRBG word 3. 150 * @var TRNG_T::DATA2 151 * Offset: 0x14 TRNG Data Output Word 2 Register 152 * --------------------------------------------------------------------------------------------------- 153 * |Bits |Field |Descriptions 154 * | :----: | :----: | :---- | 155 * |[31:0] |DATA |True Random Number Generator Data (Read Only) 156 * | | |The DATA stores the output data generated by TRNG, it can be read when DVIF (TRNG_STS[31]) become 1 and can be read only once. 157 * | | |TRNG_DATA0 stores Entropy / NRBG word 0 / DRBG word 0. 158 * | | |TRNG_DATA1 stores NRBG word 1 / DRBG word 1. 159 * | | |TRNG_DATA2 stores NRBG word 2 / DRBG word 2. 160 * | | |TRNG_DATA3 stores NRBG word 3 / DRBG word 3. 161 * @var TRNG_T::DATA3 162 * Offset: 0x18 TRNG Data Output Word 3 Register 163 * --------------------------------------------------------------------------------------------------- 164 * |Bits |Field |Descriptions 165 * | :----: | :----: | :---- | 166 * |[31:0] |DATA |True Random Number Generator Data (Read Only) 167 * | | |The DATA stores the output data generated by TRNG, it can be read when DVIF (TRNG_STS[31]) become 1 and can be read only once. 168 * | | |TRNG_DATA0 stores Entropy / NRBG word 0 / DRBG word 0. 169 * | | |TRNG_DATA1 stores NRBG word 1 / DRBG word 1. 170 * | | |TRNG_DATA2 stores NRBG word 2 / DRBG word 2. 171 * | | |TRNG_DATA3 stores NRBG word 3 / DRBG word 3. 172 */ 173 __IO uint32_t CTL; /*!< [0x0000] TRNG Control Register */ 174 __IO uint32_t CFG; /*!< [0x0004] TRNG Configure Register */ 175 __I uint32_t STS; /*!< [0x0008] TRNG Status Register */ 176 __I uint32_t DATA[4]; /*!< [0x000c-0x0018] TRNG Data Output Word 0 Register */ 177 178 } TRNG_T; 179 180 /** 181 @addtogroup TRNG_CONST TRNG Bit Field Definition 182 Constant Definitions for TRNG Controller 183 @{ */ 184 185 #define TRNG_CTL_LDOEN_Pos (0) /*!< TRNG_T::CTL: LDOEN Position */ 186 #define TRNG_CTL_LDOEN_Msk (0x1ul << TRNG_CTL_LDOEN_Pos) /*!< TRNG_T::CTL: LDOEN Mask */ 187 188 #define TRNG_CTL_NRST_Pos (1) /*!< TRNG_T::CTL: NRST Position */ 189 #define TRNG_CTL_NRST_Msk (0x1ul << TRNG_CTL_NRST_Pos) /*!< TRNG_T::CTL: NRST Mask */ 190 191 #define TRNG_CTL_TRNGEN_Pos (2) /*!< TRNG_T::CTL: TRNGEN Position */ 192 #define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */ 193 194 #define TRNG_CTL_START_Pos (3) /*!< TRNG_T::CTL: START Position */ 195 #define TRNG_CTL_START_Msk (0x1ul << TRNG_CTL_START_Pos) /*!< TRNG_T::CTL: START Mask */ 196 197 #define TRNG_CTL_MODE_Pos (4) /*!< TRNG_T::CTL: MODE Position */ 198 #define TRNG_CTL_MODE_Msk (0x3ul << TRNG_CTL_MODE_Pos) /*!< TRNG_T::CTL: MODE Mask */ 199 200 #define TRNG_CTL_INSTANT_Pos (8) /*!< TRNG_T::CTL: INSTANT Position */ 201 #define TRNG_CTL_INSTANT_Msk (0x1ul << TRNG_CTL_INSTANT_Pos) /*!< TRNG_T::CTL: INSTANT Mask */ 202 203 #define TRNG_CTL_RESEED_Pos (9) /*!< TRNG_T::CTL: RESEED Position */ 204 #define TRNG_CTL_RESEED_Msk (0x1ul << TRNG_CTL_RESEED_Pos) /*!< TRNG_T::CTL: RESEED Mask */ 205 206 #define TRNG_CTL_UPDATE_Pos (10) /*!< TRNG_T::CTL: UPDATE Position */ 207 #define TRNG_CTL_UPDATE_Msk (0x1ul << TRNG_CTL_UPDATE_Pos) /*!< TRNG_T::CTL: UPDATE Mask */ 208 209 #define TRNG_CTL_KATEN_Pos (24) /*!< TRNG_T::CTL: KATEN Position */ 210 #define TRNG_CTL_KATEN_Msk (0x1ul << TRNG_CTL_KATEN_Pos) /*!< TRNG_T::CTL: KATEN Mask */ 211 212 #define TRNG_CTL_KATSEL_Pos (25) /*!< TRNG_T::CTL: KATSEL Position */ 213 #define TRNG_CTL_KATSEL_Msk (0x3ul << TRNG_CTL_KATSEL_Pos) /*!< TRNG_T::CTL: KATSEL Mask */ 214 215 #define TRNG_CTL_ERRIEN_Pos (30) /*!< TRNG_T::CTL: ERRIEN Position */ 216 #define TRNG_CTL_ERRIEN_Msk (0x1ul << TRNG_CTL_ERRIEN_Pos) /*!< TRNG_T::CTL: ERRIEN Mask */ 217 218 #define TRNG_CTL_DVIEN_Pos (31) /*!< TRNG_T::CTL: DVIEN Position */ 219 #define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */ 220 221 #define TRNG_CFG_RESEED_INTERVAL_Pos (0) /*!< TRNG_T::CFG: RESEED_INTERVAL Position */ 222 #define TRNG_CFG_RESEED_INTERVAL_Msk (0x3fffffful << TRNG_CFG_RESEED_INTERVAL_Pos) /*!< TRNG_T::CFG: RESEED_INTERVAL Mask */ 223 224 #define TRNG_CFG_CTRLEN_Pos (28) /*!< TRNG_T::CFG: CTRLEN Position */ 225 #define TRNG_CFG_CTRLEN_Msk (0xful << TRNG_CFG_CTRLEN_Pos) /*!< TRNG_T::CFG: CTRLEN Mask */ 226 227 #define TRNG_STS_LDORDY_Pos (0) /*!< TRNG_T::STS: LDORDY Position */ 228 #define TRNG_STS_LDORDY_Msk (0x1ul << TRNG_STS_LDORDY_Pos) /*!< TRNG_T::STS: LDORDY Mask */ 229 230 #define TRNG_STS_TRNGRDY_Pos (1) /*!< TRNG_T::STS: TRNGRDY Position */ 231 #define TRNG_STS_TRNGRDY_Msk (0x1ul << TRNG_STS_TRNGRDY_Pos) /*!< TRNG_T::STS: TRNGRDY Mask */ 232 233 #define TRNG_STS_ESSUT_Pos (4) /*!< TRNG_T::STS: ESSUT Position */ 234 #define TRNG_STS_ESSUT_Msk (0x1ul << TRNG_STS_ESSUT_Pos) /*!< TRNG_T::STS: ESSUT Mask */ 235 236 #define TRNG_STS_ESRCT_Pos (5) /*!< TRNG_T::STS: ESRCT Position */ 237 #define TRNG_STS_ESRCT_Msk (0x1ul << TRNG_STS_ESRCT_Pos) /*!< TRNG_T::STS: ESRCT Mask */ 238 239 #define TRNG_STS_ESAPT_Pos (6) /*!< TRNG_T::STS: ESAPT Position */ 240 #define TRNG_STS_ESAPT_Msk (0x1ul << TRNG_STS_ESAPT_Pos) /*!< TRNG_T::STS: ESAPT Mask */ 241 242 #define TRNG_STS_KATPASS_Pos (27) /*!< TRNG_T::STS: KATPASS Position */ 243 #define TRNG_STS_KATPASS_Msk (0x1ul << TRNG_STS_KATPASS_Pos) /*!< TRNG_T::STS: KATPASS Mask */ 244 245 #define TRNG_STS_ERRIF_Pos (30) /*!< TRNG_T::STS: ERRIF Position */ 246 #define TRNG_STS_ERRIF_Msk (0x1ul << TRNG_STS_ERRIF_Pos) /*!< TRNG_T::STS: ERRIF Mask */ 247 248 #define TRNG_STS_DVIF_Pos (31) /*!< TRNG_T::STS: DVIF Position */ 249 #define TRNG_STS_DVIF_Msk (0x1ul << TRNG_STS_DVIF_Pos) /*!< TRNG_T::STS: DVIF Mask */ 250 251 #define TRNG_DATA0_DATA_Pos (0) /*!< TRNG_T::DATA0: DATA Position */ 252 #define TRNG_DATA0_DATA_Msk (0xfffffffful << TRNG_DATA0_DATA_Pos) /*!< TRNG_T::DATA0: DATA Mask */ 253 254 #define TRNG_DATA1_DATA_Pos (0) /*!< TRNG_T::DATA1: DATA Position */ 255 #define TRNG_DATA1_DATA_Msk (0xfffffffful << TRNG_DATA1_DATA_Pos) /*!< TRNG_T::DATA1: DATA Mask */ 256 257 #define TRNG_DATA2_DATA_Pos (0) /*!< TRNG_T::DATA2: DATA Position */ 258 #define TRNG_DATA2_DATA_Msk (0xfffffffful << TRNG_DATA2_DATA_Pos) /*!< TRNG_T::DATA2: DATA Mask */ 259 260 #define TRNG_DATA3_DATA_Pos (0) /*!< TRNG_T::DATA3: DATA Position */ 261 #define TRNG_DATA3_DATA_Msk (0xfffffffful << TRNG_DATA3_DATA_Pos) /*!< TRNG_T::DATA3: DATA Mask */ 262 263 /**@}*/ /* TRNG_CONST */ 264 /**@}*/ /* end of TRNG register group */ 265 /**@}*/ /* end of REGISTER group */ 266 267 #if defined ( __CC_ARM ) 268 #pragma no_anon_unions 269 #endif 270 271 #endif /* __TRNG_REG_H__ */
