1 /**************************************************************************//** 2 * @file psio_reg.h 3 * @version V3.00 4 * @brief PSIO register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 10 #ifndef __PSIO_REG_H__ 11 #define __PSIO_REG_H__ 12 13 #if defined ( __CC_ARM ) 14 #pragma anon_unions 15 #endif 16 17 /** 18 @addtogroup REGISTER Control Register 19 @{ 20 */ 21 22 /** 23 @addtogroup PSIO Programmable Serial IO (PSIO) 24 Memory Mapped Structure for PSIO Controller 25 @{ */ 26 27 typedef struct 28 { 29 /** 30 * @var SCCT_T::SCCTL 31 * Offset: 0x20/0x28/0x30/0x38 PSIO Slot Controller n Control Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[3:0] |INISLOT |Initial Slot Period 36 * | | |The initial slot of the repeat period. 37 * | | |0000 = No use. 38 * | | |0001 = SLOT0. 39 * | | |0010 = SLOT1. 40 * | | |0011 = SLOT2. 41 * | | |0100 = SLOT3. 42 * | | |0101 = SLOT4. 43 * | | |0110 = SLOT5. 44 * | | |0111 = SLOT6. 45 * | | |1000 = SLOT7. 46 * | | |Others = Reserved. 47 * |[7:4] |ENDSLOT |End Slot Period 48 * | | |The end slot of the repeat period. 49 * | | |0000 = No use. 50 * | | |0001 = SLOT0. 51 * | | |0010 = SLOT1. 52 * | | |0011 = SLOT2. 53 * | | |0100 = SLOT3. 54 * | | |0101 = SLOT4. 55 * | | |0110 = SLOT5. 56 * | | |0111 = SLOT6. 57 * | | |1000 = SLOT7. 58 * | | |Others = Reserved. 59 * |[13:8] |SPLCNT |Slot Period Loop Count 60 * | | |000000 ~ 111110 is loop count. 61 * | | |000000 = Slot period loop count function is disable. 62 * | | |000001 = Repeat selection loop once, which means total go through selected repeat slots 2 times. 63 * | | |111111 = Loop until stop PSIO slot controller. 64 * | | |Note 1: If setting this register 111111 with PDMA mode and OUTPUT mode, it will stop automatically when PDMA is finish and output data in shift register is finished. 65 * | | |Note 2: If setting this register 111111 with PDMA mode and INPUT mode, it will stop automatically when PDMA is finish. 66 * | | |Note 3: If PSIO receives stop instruction during repeat mode, it will stop only when the current loop is finished. 67 * |[15:14] |TRIGSRC |PSIO_SCn Trigger Source 68 * | | |00 = Trigger by software. 69 * | | |01 = Trigger PSIO_SCn when related PSIO_PIN occurred falling edge. 70 * | | |10 = Trigger PSIO_SCn when related PSIO_PIN occurred rising edge. 71 * | | |11 = Trigger PSIO_SCn when related PSIO_PIN occurred rising edge or falling edge. 72 * | | |Note 1: PSIO slot controller pin can only be trigger by related pins which is setting from SCSEL(PSIOn_GENCTL[25:24]). 73 * | | |Note 2: Configuring rising or falling signal trigger PSIO, the signal need to hold for at least two PSIO_CLK for de-bounce or PSIO will not be triggered. 74 * |[16] |START |PSIO_SCn Start 75 * | | |0 = No use. 76 * | | |1 = Start PSIO_SCn to count and active related PSIO_PIN. 77 * | | |Note: this bit is always read as 0. 78 * |[17] |REPEAT |Whole Repeat Mode 79 * | | |Slot controller repeats counting forever. 80 * | | |0 = Repeat mode disabled. 81 * | | |1 = Repeat mode enabled. 82 * | | |Note 1: If this bit is enabled with PDMA mode, slot controller will stop automatically when the PDMA finish transferring number of data. 83 * | | |Note 2: If PSIO receives stop instruction during repeat mode, it will stop only when the current loop is finished. 84 * |[18] |STOP |PSIO_SCn Stop 85 * | | |0 = No use. 86 * | | |1 = Stop PSIO_SCn. 87 * | | |Note: This bit is always read as 0. 88 * |[24] |BUSY |PSIO_SCn Busy Flag 89 * | | |0 = PSIO_SCn is not busy. 90 * | | |1 = PSIO_SCn is busy. 91 * | | |Note: This bit will be set to 1 when slot controller starts to count automatically and it will be cleared to 0 automatically when slot controller stops counting, too. 92 * |[25] |IDLE |PSIO_SCn Idle Flag 93 * | | |0 = PSIO_SCn is not IDLE. 94 * | | |1 = PSIO_SCn is IDLE. 95 * | | |Note 1: This bit will be cleared to 0 when slot controller starts to count automatically. 96 * | | |Note 2: This bit will be set to 1 when configuring it 1 by software. 97 * | | |Note 3: This bit is set to distinguish INTERVAL(PSIOn_GENCTL[5:4]) and INITIAL(PSIOn_GENCTL[3:2]). 98 * @var SCCT_T::SCSLOT 99 * Offset: 0x24/0x2C/0x34/0x3C PSIO Slot Controller n Slot Register 100 * --------------------------------------------------------------------------------------------------- 101 * |Bits |Field |Descriptions 102 * | :----: | :----: | :---- | 103 * |[3:0] |SLOT0 |PSIO Slot Controller Slot0 Tick Count 104 * | | |0 to 15. 105 * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. 106 * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. 107 * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. 108 * |[7:4] |SLOT1 |PSIO Slot Controller Slot1 Tick Count 109 * | | |0 to 15. 110 * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. 111 * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. 112 * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. 113 * |[11:8] |SLOT2 |PSIO Slot Controller Slot2 Tick Count 114 * | | |0 to 15. 115 * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. 116 * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. 117 * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. 118 * |[15:12] |SLOT3 |PSIO Slot Controller Slot3 Tick Count 119 * | | |0 to 15. 120 * | | |Note1: Filling in all 0 to this field indicates to disable this slot. 121 * | | |Note2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. 122 * | | |Note3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. 123 * |[19:16] |SLOT4 |PSIO Slot Controller Slot4 Tick Count 124 * | | |0 to 15. 125 * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. 126 * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. 127 * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. 128 * |[23:20] |SLOT5 |PSIO Slot Controller Slot5 Tick Count 129 * | | |0 to 15 130 * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. 131 * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. 132 * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. 133 * |[27:24] |SLOT6 |PSIO Slot Controller Slot6 Tick Count 134 * | | |0 to 15 135 * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. 136 * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. 137 * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. 138 * |[31:28] |SLOT7 |PSIO Slot Controller Slot7 Tick Count 139 * | | |0 to 15. 140 * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. 141 * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. 142 * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. 143 */ 144 __IO uint32_t SCCTL; /*!< PSIO Slot Counter n Control register */ 145 __IO uint32_t SCSLOT; /*!< PSIO Slot Counter n Slot Register */ 146 147 } SCCT_T; 148 149 typedef struct 150 { 151 /** 152 * @var GNCT_T::GENCTL 153 * Offset: 0x40/0x60/0x80/0xA0/0xC0/0xE0/0x100/0x120 PSIOn General Control Register 154 * --------------------------------------------------------------------------------------------------- 155 * |Bits |Field |Descriptions 156 * | :----: | :----: | :---- | 157 * |[1:0] |IOMODE |IO Mode 158 * | | |I/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point. 159 * | | |00 = Input mode. 160 * | | |01 = Output mode. 161 * | | |10 = Open-drain mode. 162 * | | |11 = Quasi-bidirectional mode. 163 * | | |Note 1: When slot controller stops counting, it will switch to the current I/O mode setting. 164 * | | |Note 2: When PSIO uses quasi-bidirectional mode or open-drain mode to trigger slot controller, the initial or interval output state need to be set output high level, or the pin will not be trigger. 165 * |[3:2] |INITIAL |Initial Output 166 * | | |The output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1. 167 * | | |00 = Low level. 168 * | | |01 = High level. 169 * | | |10 = Last output. 170 * | | |11 = Toggle. 171 * | | |Note 1: Only when IOMODE is not input mode, then this register is effective. 172 * | | |Note 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]) is high. 173 * |[5:4] |INTERVAL |Interval Output 174 * | | |The output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0. 175 * | | |00 = Low level. 176 * | | |01 = High level. 177 * | | |10 = Last output. 178 * | | |11 = Toggle. 179 * | | |Note 1: Only when IOMODE is not input mode, then this register is effective. 180 * | | |Note 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]) is low. 181 * |[11:8] |SW0CP |Switch0 Check Point 182 * | | |0000 = No use. 183 * | | |0001 = CHECK POINT 0. 184 * | | |0010 = CHECK POINT 1. 185 * | | |0011 = CHECK POINT 2. 186 * | | |0100 = CHECK POINT 3. 187 * | | |0101 = CHECK POINT 4. 188 * | | |0110 = CHECK POINT 5. 189 * | | |0111 = CHECK POINT 6. 190 * | | |1000 = CHECK POINT 7. 191 * | | |Others = Reserved. 192 * |[15:12] |SW1CP |Switch1 Check Point 193 * | | |0000 = No use. 194 * | | |0001 = CHECK POINT 0. 195 * | | |0010 = CHECK POINT 1. 196 * | | |0011 = CHECK POINT 2. 197 * | | |0100 = CHECK POINT 3. 198 * | | |0101 = CHECK POINT 4. 199 * | | |0110 = CHECK POINT 5. 200 * | | |0111 = CHECK POINT 6. 201 * | | |1000 = CHECK POINT 7. 202 * | | |Others = Reserved. 203 * |[17:16] |MODESW0 |Mode Switch0 Point 204 * | | |Mode at the switch0 point 205 * | | |00 = Input mode. 206 * | | |01 = Output mode. 207 * | | |10 = Open-drain mode. 208 * | | |11 = Quasi-bidirectional mode. 209 * |[19:18] |MODESW1 |Mode Switch1 Point 210 * | | |Mode at the switch1 point 211 * | | |00 = Input mode. 212 * | | |01 = Output mode. 213 * | | |10 = Open-drain mode. 214 * | | |11 = Quasi-bidirectional mode. 215 * |[25:24] |SCSEL |Slot Controller Selection 216 * | | |Select slot controller for check point. 217 * | | |00 = SLOT CONTROLLER0. 218 * | | |01 = SLOT CONTROLLER1. 219 * | | |10 = SLOT CONTROLLER2. 220 * | | |11 = SLOT CONTROLLER3. 221 * |[26] |PINEN |Pin Enable Bit 222 * | | |0 = Pin Disabled. 223 * | | |1 = Pin Enabled. 224 * @var GNCT_T::DATCTL 225 * Offset: 0x44/0x64/0x84/0xA4/0xC4/0xE4/0x104/0x124 PSIOn Data Control Register 226 * --------------------------------------------------------------------------------------------------- 227 * |Bits |Field |Descriptions 228 * | :----: | :----: | :---- | 229 * |[4:0] |OUTDATWD |Output Data Width 230 * | | |Indicate the data width of OUTPUT DATA register. 231 * | | |Output data size = OUTDATWD +1. 232 * | | |e.g. 233 * | | |5'b00000 = 1 bit. 234 * | | |5'b11111 = 32 bit. 235 * |[12:8] |INDATWD |Input Data Width 236 * | | |Indicate the data width of INPUT DATA register. 237 * | | |Input data size = INDATWD +1. 238 * | | |e.g. 239 * | | |5'b00000 = 1 bit. 240 * | | |5'b11111 = 32 bit. 241 * |[16] |ORDER |Order 242 * | | |The order of output data and input data. 243 * | | |0 = Data transfer start form LSB. 244 * | | |1 = Data transfer start form MSB. 245 * |[25:24] |OUTDEPTH |Output Data Depth 246 * | | |Represent the data depth of the output buffer, when data width is larger than 16-bit, this setting can be ignored. 247 * | | |When the data width is between 9-bit and 16 bit, 248 * | | |0 = OUTDEPTH [0], the data depth is 1. 249 * | | |1 = OUTDEPTH [0], the data depth is 2. 250 * | | |When the data width is less than or equal to 8-bit, 251 * | | |0 = OUTDEPTH, the data depth is 1. 252 * | | |1 = OUTDEPTH, the data depth is 2. 253 * | | |2 = OUTDEPTH, the data depth is 3. 254 * | | |3 = OUTDEPTH, the data depth is 4. 255 * | | |Note 1: The output data depth impacts when the output data empty flag and output under flow data flag is set to 1. 256 * | | |Note 2: There is no difference of data depth no matter using software program data or PDMA program data. 257 * |[29:28] |INDEPTH |Input Data Depth 258 * | | |Represent the data depth of the input buffer, when data width is larger than 16-bit, this setting can be ignored. 259 * | | |When the data width is between 9-bit and 16 bit, 260 * | | |0 = INDEPTH[0], the data depth is 1. 261 * | | |1 = INDEPTH[0], the data depth is 2. 262 * | | |When the data width is less than or equal to 8-bit, 263 * | | |0 = INDEPTH, the data depth is 1. 264 * | | |1 = INDEPTH, the data depth is 2. 265 * | | |2 = INDEPTH, the data depth is 3. 266 * | | |3 = INDEPTH, the data depth is 4. 267 * | | |Note 1: The input data depth impacts when the input data full flag and input data over flow flag is set to 1. 268 * | | |Note 2: There is no difference of data depth no matter using software program data or PDMA program data. 269 * @var GNCT_T::INSTS 270 * Offset: 0x48/0x68/0x88/0xA8/0xC8/0xE8/0x108/0x128 PSIOn Input Status Register 271 * --------------------------------------------------------------------------------------------------- 272 * |Bits |Field |Descriptions 273 * | :----: | :----: | :---- | 274 * |[7:0] |INSTS |Input Status 275 * | | |Status input buffer. This register can be read clear. 276 * | | |Note: When the valid bit is set, the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update. 277 * @var GNCT_T::INDAT 278 * Offset: 0x4C/0x6C/0x8C/0xAC/0xCC/0xEC/0x10C/0x12C PSIOn Input Data Register 279 * --------------------------------------------------------------------------------------------------- 280 * |Bits |Field |Descriptions 281 * | :----: | :----: | :---- | 282 * |[31:0] |INDAT |Input Data Buffer 283 * | | |This register can be read clear. 284 * | | |Note: The input data sample time is according to the slot length. 285 * | | |The sampling time is near 3/4 slot. 286 * | | |When the slot length is 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, PSIO sample input data when the slot controller count to 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9. 287 * @var GNCT_T::OUTDAT 288 * Offset: 0x50/0x70/0x90/0xB0/0xD0/0xF0/0x110/0x130 PSIOn Output Data Register 289 * --------------------------------------------------------------------------------------------------- 290 * |Bits |Field |Descriptions 291 * | :----: | :----: | :---- | 292 * |[31:0] |OUTDAT |Output Data Buffer 293 * | | |This field is used to configure output data. 294 * @var GNCT_T::CPCTL0 295 * Offset: 0x54/0x74/0x94/0xB4/0xD4/0xF4/0x114/0x134 PSIOn Check Point Control Register 0 296 * --------------------------------------------------------------------------------------------------- 297 * |Bits |Field |Descriptions 298 * | :----: | :----: | :---- | 299 * |[2:0] |CKPT0 |Check Point 0 300 * | | |0000 = No use. 301 * | | |0001 = SLOT0. 302 * | | |0010 = SLOT1. 303 * | | |0011 = SLOT2. 304 * | | |0100 = SLOT3. 305 * | | |0101 = SLOT4. 306 * | | |0110 = SLOT5. 307 * | | |0111 = SLOT6. 308 * | | |1000 = SLOT7. 309 * | | |Others = Reserved. 310 * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. 311 * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. 312 * |[6:4] |CKPT1 |Check Point 1 313 * | | |0000 = No use. 314 * | | |0001 = SLOT0. 315 * | | |0010 = SLOT1. 316 * | | |0011 = SLOT2. 317 * | | |0100 = SLOT3. 318 * | | |0101 = SLOT4. 319 * | | |0110 = SLOT5. 320 * | | |0111 = SLOT6. 321 * | | |1000 = SLOT7. 322 * | | |Others = Reserved. 323 * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. 324 * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. 325 * |[10:8] |CKPT2 |Check Point 2 326 * | | |0000 = No use. 327 * | | |0001 = SLOT0. 328 * | | |0010 = SLOT1. 329 * | | |0011 = SLOT2. 330 * | | |0100 = SLOT3. 331 * | | |0101 = SLOT4. 332 * | | |0110 = SLOT5. 333 * | | |0111 = SLOT6. 334 * | | |1000 = SLOT7. 335 * | | |Others = Reserved. 336 * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. 337 * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. 338 * |[14:12] |CKPT3 |Check Point 3 339 * | | |0000 = No use. 340 * | | |0001 = SLOT0. 341 * | | |0010 = SLOT1. 342 * | | |0011 = SLOT2. 343 * | | |0100 = SLOT3. 344 * | | |0101 = SLOT4. 345 * | | |0110 = SLOT5. 346 * | | |0111 = SLOT6. 347 * | | |1000 = SLOT7. 348 * | | |Others = Reserved. 349 * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. 350 * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. 351 * |[18:16] |CKPT4 |Check Point 4 352 * | | |0000 = No use. 353 * | | |0001 = SLOT0. 354 * | | |0010 = SLOT1. 355 * | | |0011 = SLOT2. 356 * | | |0100 = SLOT3. 357 * | | |0101 = SLOT4. 358 * | | |0110 = SLOT5. 359 * | | |0111 = SLOT6. 360 * | | |1000 = SLOT7. 361 * | | |Others = Reserved. 362 * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. 363 * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. 364 * |[22:20] |CKPT5 |Check Point 5 365 * | | |0000 = No use. 366 * | | |0001 = SLOT0. 367 * | | |0010 = SLOT1. 368 * | | |0011 = SLOT2. 369 * | | |0100 = SLOT3. 370 * | | |0101 = SLOT4. 371 * | | |0110 = SLOT5. 372 * | | |0111 = SLOT6. 373 * | | |1000 = SLOT7. 374 * | | |Others = Reserved. 375 * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. 376 * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. 377 * |[26:24] |CKPT6 |Check Point 6 378 * | | |0000 = No use. 379 * | | |0001 = SLOT0. 380 * | | |0010 = SLOT1. 381 * | | |0011 = SLOT2. 382 * | | |0100 = SLOT3. 383 * | | |0101 = SLOT4. 384 * | | |0110 = SLOT5. 385 * | | |0111 = SLOT6. 386 * | | |1000 = SLOT7. 387 * | | |Others = Reserved. 388 * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. 389 * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. 390 * |[30:28] |CKPT7 |Check Point 7 391 * | | |This field is used to link check point and slot controller slot. 392 * | | |0000 = No use. 393 * | | |0001 = SLOT0. 394 * | | |0010 = SLOT1. 395 * | | |0011 = SLOT2. 396 * | | |0100 = SLOT3. 397 * | | |0101 = SLOT4. 398 * | | |0110 = SLOT5. 399 * | | |0111 = SLOT6. 400 * | | |1000 = SLOT7. 401 * | | |Others = Reserved. 402 * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. 403 * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. 404 * @var GNCT_T::CPCTL1 405 * Offset: 0x58/0x78/0x98/0xB8/0xD8/0xF8/0x118/0x138 PSIOn Check Point Control Register 1 406 * --------------------------------------------------------------------------------------------------- 407 * |Bits |Field |Descriptions 408 * | :----: | :----: | :---- | 409 * |[2:0] |CKPT0ACT |Check Point 0 Action 410 * | | |Select check point action at check point0. 411 * | | |000 = Output level low. 412 * | | |001 = Output level high. 413 * | | |010 = Output from data buffer. 414 * | | |011 = Output toggle. 415 * | | |100 = Input data buffer. 416 * | | |101 = Input status. 417 * | | |110 = Input status record and update. 418 * | | |Others = Reserved. 419 * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). 420 * |[6:4] |CKPT1ACT |Check Point 1 Action 421 * | | |Select check point action at check point1. 422 * | | |000 = Output level low. 423 * | | |001 = Output level high. 424 * | | |010 = Output from data buffer. 425 * | | |011 = Output toggle. 426 * | | |100 = Input data buffer. 427 * | | |101 = Input status. 428 * | | |110 = Input status record and update. 429 * | | |Others = Reserved. 430 * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). 431 * |[10:8] |CKPT2ACT |Check Point 2 Action 432 * | | |Select check point action at check point2. 433 * | | |000 = Output level low. 434 * | | |001 = Output level high. 435 * | | |010 = Output from data buffer. 436 * | | |011 = Output toggle. 437 * | | |100 = Input data buffer. 438 * | | |101 = Input status. 439 * | | |110 = Input status record and update. 440 * | | |Others = Reserved. 441 * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). 442 * |[14:12] |CKPT3ACT |Check Point 3 Action 443 * | | |Select check point action at check point3. 444 * | | |000 = Output level low. 445 * | | |001 = Output level high. 446 * | | |010 = Output from data buffer. 447 * | | |011 = Output toggle. 448 * | | |100 = Input data buffer. 449 * | | |101 = Input status. 450 * | | |110 = Input status record and update. 451 * | | |Others = Reserved. 452 * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). 453 * |[18:16] |CKPT4ACT |Check Point 4 Action 454 * | | |Select check point action at check point4. 455 * | | |000 = Output level low. 456 * | | |001 = Output level high. 457 * | | |010 = Output from data buffer. 458 * | | |011 = Output toggle. 459 * | | |100 = Input data buffer. 460 * | | |101 = Input status. 461 * | | |110 = Input status record and update. 462 * | | |Others = Reserved. 463 * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). 464 * |[22:20] |CKPT5ACT |Check Point 5 Action 465 * | | |Select check point action at check point5. 466 * | | |000 = Output level low. 467 * | | |001 = Output level high. 468 * | | |010 = Output from data buffer. 469 * | | |011 = Output toggle. 470 * | | |100 = Input data buffer. 471 * | | |101 = Input status. 472 * | | |110 = Input status record and update. 473 * | | |Others = Reserved. 474 * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). 475 * |[26:24] |CKPT6ACT |Check Point 6 Action 476 * | | |Select check point action at check point6. 477 * | | |000 = Output level low. 478 * | | |001 = Output level high. 479 * | | |010 = Output from data buffer. 480 * | | |011 = Output toggle. 481 * | | |100 = Input data buffer. 482 * | | |101 = Input status. 483 * | | |110 = Input status record and update. 484 * | | |Others = Reserved. 485 * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). 486 * |[30:28] |CKPT7ACT |Check Point 7 Action 487 * | | |Select check point action at check point7. 488 * | | |000 = Output level low. 489 * | | |001 = Output level high. 490 * | | |010 = Output from data buffer. 491 * | | |011 = Output toggle. 492 * | | |100 = Input data buffer. 493 * | | |101 = Input status. 494 * | | |110 = Input status record and update. 495 * | | |Others = Reserved. 496 * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). 497 */ 498 __IO uint32_t GENCTL; /*!< PSIOn General Control Register */ 499 __IO uint32_t DATCTL; /*!< PSIOn Data Control Register */ 500 __I uint32_t INSTS; /*!< PSIOn Input Status Register */ 501 __I uint32_t INDAT; /*!< PSIOn Input Data Register */ 502 __O uint32_t OUTDAT; /*!< PSIOn Output Data Register */ 503 __IO uint32_t CPCTL0; /*!< PSIOn Check Point Control Register 0 */ 504 __IO uint32_t CPCTL1; /*!< PSIOn Check Point Control Register 1 */ 505 __I uint32_t RESERVE0[1]; 506 } GNCT_T; 507 508 typedef struct 509 { 510 /** 511 * @var PSIO_T::INTCTL 512 * Offset: 0x00 PSIO Interrupt Control Register 513 * --------------------------------------------------------------------------------------------------- 514 * |Bits |Field |Descriptions 515 * | :----: | :----: | :---- | 516 * |[2:0] |CONI0SS |Configurable Interrupt 0 Slot Selection 517 * | | |0000 = No use. 518 * | | |0001 = SLOT0. 519 * | | |0010 = SLOT1. 520 * | | |0011 = SLOT2. 521 * | | |0100 = SLOT3. 522 * | | |0101 = SLOT4. 523 * | | |0110 = SLOT5. 524 * | | |0111 = SLOT6. 525 * | | |1000 = SLOT7. 526 * | | |Others = Reserved. 527 * |[6:4] |CONI1SS |Configurable Interrupt 1 Slot Selection 528 * | | |0000 = No use. 529 * | | |0001 = SLOT0. 530 * | | |0010 = SLOT1. 531 * | | |0011 = SLOT2. 532 * | | |0100 = SLOT3. 533 * | | |0101 = SLOT4. 534 * | | |0110 = SLOT5. 535 * | | |0111 = SLOT6. 536 * | | |1000 = SLOT7. 537 * | | |Others = Reserved. 538 * |[9:8] |CONI0SCS |Configurable Interrupt 0 Slot Controller Selection 539 * | | |Select Slot controller for interrupt 0. 540 * | | |00 = Slot controller 0. 541 * | | |01 = Slot controller 1. 542 * | | |10 = Slot controller 2. 543 * | | |11 = Slot controller 3. 544 * |[13:12] |CONI1SCS |Configurable Interrupt 1 Slot Controller Selection 545 * | | |Select Slot controller for interrupt 1. 546 * | | |00 = Slot controller 0. 547 * | | |01 = Slot controller 1. 548 * | | |10 = Slot controller 2. 549 * | | |11 = Slot controller 3. 550 * @var PSIO_T::INTEN 551 * Offset: 0x04 PSIO Interrupt Enable Register 552 * --------------------------------------------------------------------------------------------------- 553 * |Bits |Field |Descriptions 554 * | :----: | :----: | :---- | 555 * |[0] |CON0IE |Configurable Interrupt 0 Enable Bit 556 * | | |This field is used to enable selective interrupt 0. 557 * | | |0 = Selective interrupt 0 Disabled. 558 * | | |1 = Selective interrupt 0 Enabled. 559 * |[1] |CON1IE |Configurable Interrupt 1 Enable Bit 560 * | | |This field is used to enable selective interrupt 1. 561 * | | |0 = Selective interrupt 1 Disabled. 562 * | | |1 = Selective interrupt 1 Enabled. 563 * |[2] |MISMATIE |Mismatch Interrupt Enable Bit 564 * | | |This field is used to enable mismatch interrupt. 565 * | | |0 = Mismatch interrupt Disabled. 566 * | | |1 = Mismatch interrupt Enabled. 567 * |[3] |TERRIE |Transfer Error Interrupt Enable Bit 568 * | | |This field is used to enable transfer error interrupt. 569 * | | |0 = Transfer error interrupt Disabled. 570 * | | |1 = Transfer error interrupt Enabled. 571 * |[4] |SC0IE |Slot Controller 0 Done Interrupt Enable Bit 572 * | | |This field is used to enable Slot controller 0 finish interrupt. 573 * | | |0 = Slot controller 0 finish interrupt Disabled. 574 * | | |1 = Slot controller 0 finish interrupt Enabled. 575 * |[5] |SC1IE |Slot Controller 1 Done Interrupt Enable Bit 576 * | | |This field is used to enable Slot controller 1 finish interrupt. 577 * | | |0 = Slot controller 1 finish interrupt Disabled. 578 * | | |1 = Slot controller 1 finish interrupt Enabled. 579 * |[6] |SC2IE |Slot Controller 2 Done Interrupt Enable Bit 580 * | | |This field is used to enable Slot controller 2 finish interrupt. 581 * | | |0 = Slot controller 2 finish interrupt Disabled. 582 * | | |1 = Slot controller 2 finish interrupt Enabled. 583 * |[7] |SC3IE |Slot Controller 3 Done Interrupt Enable Bit 584 * | | |This field is used to enable Slot controller 3 finish interrupt. 585 * | | |0 = Slot controller 3 finish interrupt Disabled. 586 * | | |1 = Slot controller 3 finish interrupt Enabled. 587 * @var PSIO_T::INTSTS 588 * Offset: 0x08 PSIO Interrupt Status Register 589 * --------------------------------------------------------------------------------------------------- 590 * |Bits |Field |Descriptions 591 * | :----: | :----: | :---- | 592 * |[0] |CON0IF |Configurable Interrupt 0 Flag 593 * | | |The setting interrupt is trigger at the end of the check point of the pin. 594 * | | |0 = Condition in PSIO_INTCTL is not triggered. 595 * | | |1 = Condition in PSIO_INTCTL is triggered. 596 * | | |Note: This bit can be cleared by writing 1. 597 * |[1] |CON1IF |Configurable Interrupt 1 Flag 598 * | | |The setting interrupt is trigger at the end of the check point of the pin. 599 * | | |0 = Condition in PSIO_INTCTL is not triggered. 600 * | | |1 = Condition in PSIO_INTCTL is triggered. 601 * | | |Note: This bit can be cleared by writing 1. 602 * |[2] |MISMATIF |Mismatch Interrupt Flag 603 * | | |This flag shows the amounts of data are not the same in each pins with PDMA enabled. 604 * | | |If this situation happens, all slot controllers stop counting. 605 * | | |0 = Each pin with PDMA enabled receive or transfer data in the same rate. 606 * | | |1 = Each pin with PDMA enabled receive or transfer data in different rate. 607 * | | |Note 1: This flag is only effective on the pin with PDMA enabled. 608 * | | |Note 2: This bit can be cleared by writing 1. 609 * |[3] |TERRIF |Transfer Error Interrupt Status Flag 610 * | | |This field is used for transfer error interrupt status flag. 611 * | | |The transfer error states is at PSIO_TRANSTS register which includes input data overflow flag INOVERn (PSIO_TRANSTS[29,25,21,17,13,9,5,1] and output data underflow flag OUTUFn (PSIO_TRANSTS[31,27,23,19,15,11,7,3]). 612 * | | |0 = Transfer error interrupt did not occur. 613 * | | |1 = Transfer error interrupt occurred. 614 * | | |Note 1: This field is the status flag of INOVER or OUTUFER. 615 * | | |Note 2: This bit can only be cleared by writing 1 to coordinate transfer error. 616 * |[4] |SC0IF |Slot Controller 0 Done Interrupt Status Flag 617 * | | |This field is used for slot controller 0 finish interrupt status flag. 618 * | | |0 = Slot controller 0 done interrupt did not occur. 619 * | | |1 = Slot controller 0 done interrupt occurred. 620 * | | |Note: This bit can be cleared by writing 1. 621 * |[5] |SC1IF |Slot Controller 1 Done Interrupt Status Flag 622 * | | |This field is used for slot controller 1 finish interrupt status flag. 623 * | | |0 = Slot controller 1 done interrupt did not occur. 624 * | | |1 = Slot controller 1 done interrupt occurred. 625 * | | |Note: This bit can be cleared by writing 1. 626 * |[6] |SC2IF |Slot Controller 2 Done Interrupt Status Flag 627 * | | |This field is used for slot controller 2 finish interrupt status flag. 628 * | | |0 = Slot controller 2 done interrupt did not occur. 629 * | | |1 = Slot controller 2 done interrupt occurred. 630 * | | |Note: This bit can be cleared by writing 1. 631 * |[7] |SC3IF |Slot Controller 3 Done Interrupt Status Flag 632 * | | |This field is used for slot controller 3 finish interrupt status flag. 633 * | | |0 = Slot controller 3 done interrupt did not occur. 634 * | | |1 = Slot controller 3 done interrupt occurred. 635 * | | |Note: This bit can be cleared by writing 1. 636 * @var PSIO_T::TRANSTS 637 * Offset: 0x0C PSIO Transfer Status Register 638 * --------------------------------------------------------------------------------------------------- 639 * |Bits |Field |Descriptions 640 * | :----: | :----: | :---- | 641 * |[0] |INFULL0 |Input Data Full Flag0 (Read Only) 642 * | | |0 = The pin0 input data is empty. 643 * | | |1 = The pin0 input data is full. 644 * | | |Note: This bit will be cleared automatically when related slot controller started and pin enabled. 645 * |[1] |INOVER0 |Input Data Overflow Flag0 646 * | | |0 = The pin0 input data does not occur overflow. 647 * | | |1 = The pin0 input data occurs overflow. 648 * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. 649 * | | |Note 2: When overflow happens, related slot controller will be stopped. 650 * | | |Note 3: This bit can be cleared by configure 1 to it. 651 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 652 * |[2] |OUTEPY0 |Output Data Empty Flag0 (Read Only) 653 * | | |0 = The pin0 output data is full. 654 * | | |1 = The pin0 output data is empty. 655 * |[3] |OUTUF0 |Output Data Underflow Flag0 656 * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1. 657 * | | |0 = The pin0 output data is not underflow. 658 * | | |1 = The pin0 output data is underflow. 659 * | | |Note 1: When output data shortage happened, it will output 0. 660 * | | |Note 2: When underflow happens, related slot controller will be stopped. 661 * | | |Note 3: This bit can be cleared by configure 1 to it. 662 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 663 * |[4] |INFULL1 |Input Data Full Flag1 (Read Only) 664 * | | |0 = The pin1 input data is empty. 665 * | | |1 = The pin1 input data is full. 666 * | | |Note: This bit will be cleared automatically when related slot controller started and pin enabled. 667 * |[5] |INOVER1 |Input Data Overflow Flag1 668 * | | |0 = The pin1 input data does not occur overflow. 669 * | | |1 = The pin1 input data occurs overflow. 670 * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. 671 * | | |Note 2: When overflow happens, related slot controller will be stopped. 672 * | | |Note 3: This bit can be cleared by configure 1 to it. 673 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 674 * |[6] |OUTEPY1 |Output Data Empty Flag1 (Read Only) 675 * | | |0 = The pin1 output data is full. 676 * | | |1 = The pin1 output data is empty. 677 * |[7] |OUTUF1 |Output Data Underflow Flag1 678 * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. 679 * | | |0 = The pin1 output data is not underflow. 680 * | | |1 = The pin1 output data is underflow. 681 * | | |Note 1: When output data shortage happened, it will output 0. 682 * | | |Note 2: When underflow happens, related slot controller will be stopped. 683 * | | |Note 3: This bit can be cleared by configure 1 to it. 684 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 685 * |[8] |INFULL2 |Input Data Full Flag2 (Read Only) 686 * | | |0 = The pin2 input data is empty. 687 * | | |1 = The pin2 input data is full. 688 * | | |Note: This bit will be cleared automatically when related slot controller started and pin is enabled. 689 * |[9] |INOVER2 |Input Data Overflow Flag2 690 * | | |0 = The pin2 input data does not occur overflow. 691 * | | |1 = The pin2 input data occurs overflow. 692 * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. 693 * | | |Note 2: When overflow happens, related slot controller will be stopped. 694 * | | |Note 3: This bit can be cleared by configure 1 to it. 695 * | | |Note 4: This bit will be cleared automatically when related slot controller start and pin enabled. 696 * |[10] |OUTEPY2 |Output Data Empty Flag2 (Read Only) 697 * | | |0 = The pin2 output data is full. 698 * | | |1 = The pin2 output data is empty. 699 * |[11] |OUTUF2 |Output Data Underflow Flag2 700 * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. 701 * | | |0 = The pin3 output data is not underflow. 702 * | | |1 = The pin3 output data is underflow. 703 * | | |Note 1: When output data shortage happened, it will output 0. 704 * | | |Note 2: When underflow happens, related slot controller will be stopped. 705 * | | |Note 3: This bit can be cleared by configure 1 to it. 706 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 707 * |[12] |INFULL3 |Input Data Full Flag3 (Read Only) 708 * | | |0 = The pin3 input data is empty. 709 * | | |1 = The pin3 input data is full. 710 * | | |Note: This bit will be cleared automatically when related slot controller started and pin is enabled. 711 * |[13] |INOVER3 |Input Data Overflow Flag3 712 * | | |0 = The pin3 input data does not occur overflow. 713 * | | |1 = The pin3 input data occurs overflow. 714 * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. 715 * | | |Note 2: When overflow happens, related slot controller will be stopped. 716 * | | |Note 3: This bit can be cleared by configure 1 to it. 717 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 718 * |[14] |OUTEPY3 |Output Data Empty Flag3 (Read Only) 719 * | | |0 = The pin3 output data is full. 720 * | | |1 = The pin3 output data is empty. 721 * |[15] |OUTUF3 |Output Data Underflow Flag3 722 * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. 723 * | | |0 = The pin3 output data is not underflow. 724 * | | |1 = The pin3 output data is underflow. 725 * | | |Note 1: When output data shortage happened, it will output 0. 726 * | | |Note 2: When underflow happens, related slot controller will be stopped. 727 * | | |Note 3: This bit can be cleared by configure 1 to it. 728 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 729 * |[16] |INFULL4 |Input Data Full Flag4 (Read Only) 730 * | | |0 = The pin4 input data is empty. 731 * | | |1 = The pin4 input data is full. 732 * | | |Note: This bit will be cleared automatically when related slot controller started and pin is enabled. 733 * |[17] |INOVER4 |Input Data Overflow Flag4 734 * | | |0 = The pin4 input data does not occur overflow. 735 * | | |1 = The pin4 input data occurs overflow. 736 * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. 737 * | | |Note 2: When overflow happens, related slot controller will be stopped. 738 * | | |Note 3: This bit can be cleared by configure 1 to it. 739 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 740 * |[18] |OUTEPY4 |Output Data Empty Flag4 (Read Only) 741 * | | |0 = The pin4 output data is full. 742 * | | |1 = The pin4 output data is empty. 743 * |[19] |OUTUF4 |Output Data Underflow Flag4 744 * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. 745 * | | |0 = The pin4 output data is not underflow. 746 * | | |1 = The pin4 output data is underflow. 747 * | | |Note 1: When output data shortage happened, it will output 0. 748 * | | |Note 2: When underflow happens, related slot controller will be stopped. 749 * | | |Note 3: This bit can be cleared by configure 1 to it. 750 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 751 * |[20] |INFULL5 |Input Data Full Flag5 (Read Only) 752 * | | |0 = The pin5 input data is empty. 753 * | | |1 = The pin5 input data is full. 754 * | | |Note: This bit will be cleared automatically when related slot controller started and pin enabled. 755 * |[21] |INOVER5 |Input Data Overflow Flag5 756 * | | |0 = The pin5 input data does not occur overflow. 757 * | | |1 = The pin5 input data occurs overflow. 758 * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. 759 * | | |Note 2: When overflow happens, related slot controller will be stopped. 760 * | | |Note 3: This bit can be cleared by configure 1 to it. 761 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 762 * |[22] |OUTEPY5 |Output Data Empty Flag5 (Read Only) 763 * | | |0 = The pin5 output data is full. 764 * | | |1 = The pin5 output data is empty. 765 * |[23] |OUTUF5 |Output Data Underflow Flag5 766 * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. 767 * | | |0 = The pin5 output data is not underflow. 768 * | | |1 = The pin5 output data is underflow. 769 * | | |Note 1: When output data shortage happened, it will output 0. 770 * | | |Note 2: When underflow happens, related slot controller will be stopped. 771 * | | |Note 3: This bit can be cleared by configure 1 to it. 772 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin is enabled. 773 * |[24] |INFULL6 |Input Data Full Flag6 (Read Only) 774 * | | |0 = The pin6 input data is empty. 775 * | | |1 = The pin6 input data is full. 776 * | | |Note: This bit will be cleared automatically when related slot controller started and pin enabled. 777 * |[25] |INOVER6 |Input Data Overflow Flag6 778 * | | |0 = The pin6 input data does not occur overflow. 779 * | | |1 = The pin6 input data occurs overflow. 780 * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. 781 * | | |Note 2: When overflow happens, related slot controller will be stopped. 782 * | | |Note 3: This bit can be cleared by configure 1 to it. 783 * | | |Note 4: This bit will be cleared automatically when related slot controller start and pin enabled. 784 * |[26] |OUTEPY6 |Output Data Empty Flag6 (Read Only) 785 * | | |0 = The pin6 output data is full. 786 * | | |1 = The pin6 output data is empty. 787 * |[27] |OUTUF6 |Output Data Underflow Flag6 788 * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. 789 * | | |0 = The pin6 output data is not underflow. 790 * | | |1 = The pin6 output data is underflow. 791 * | | |Note 1: When output data shortage happened, it will output 0. 792 * | | |Note 2: When underflow happens, related slot controller will be stopped. 793 * | | |Note 3: This bit can be cleared by configure 1 to it. 794 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 795 * |[28] |INFULL7 |Input Data Full Flag7 (Read Only) 796 * | | |0 = The pin7 input data is empty. 797 * | | |1 = The pin7 input data is full. 798 * | | |Note: This bit will be cleared automatically when related slot controller started and pin enabled. 799 * |[29] |INOVER7 |Input Data Overflow Flag7 800 * | | |0 = The pin7 input data does not occur overflow. 801 * | | |1 = The pin7 input data occurs overflow. 802 * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. 803 * | | |Note 2: When overflow happens, related slot controller will be stopped. 804 * | | |Note 3: This bit can be cleared by configure 1 to it. 805 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 806 * |[30] |OUTEPY7 |Output Data Empty Flag7 (Read Only) 807 * | | |0 = The pin7 output data is full. 808 * | | |1 = The pin7 output data is empty. 809 * |[31] |OUTUF7 |Output Data Underflow Flag7 810 * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. 811 * | | |0 = The pin7 output data is not underflow. 812 * | | |1 = The pin7 output data is underflow. 813 * | | |Note 1: When output data shortage happened, it will output 0. 814 * | | |Note 2: When underflow happens, related slot controller will be stopped. 815 * | | |Note 3: This bit can be cleared by configure 1 to it. 816 * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. 817 * @var PSIO_T::ISSTS 818 * Offset: 0x10 PSIO Input Status State Register 819 * --------------------------------------------------------------------------------------------------- 820 * |Bits |Field |Descriptions 821 * | :----: | :----: | :---- | 822 * |[0] |VALID0 |Input Status Valid 0 823 * | | |0 = The pin 0 input status is not ready. 824 * | | |1 = The pin 0 input status is ready. 825 * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. 826 * |[1] |INSTSOV0 |Input Status Overflow 0 827 * | | |0 = The pin 0 input status does not overflow. 828 * | | |1 = The pin 0 input status occur overflow. 829 * | | |Note: This overflow bit can be cleared by writing 1. 830 * |[2] |VALID1 |Input Status Valid 1 831 * | | |0 = The pin 1 input status is not ready. 832 * | | |1 = The pin 1 input status is ready. 833 * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. 834 * |[3] |INSTSOV1 |Input Status Overflow 1 835 * | | |0 = The pin 1 input status does not overflow. 836 * | | |1 = The pin 1 input status occur overflow. 837 * | | |Note: This overflow bit can be cleared by writing 1. 838 * |[4] |VALID2 |Input Status Valid 2 839 * | | |0 = The pin 2 input status is not ready. 840 * | | |1 = The pin 2 input status is ready. 841 * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. 842 * |[5] |INSTSOV2 |Input Status Overflow 2 843 * | | |0 = The pin 2 input status does not overflow. 844 * | | |1 = The pin 2 input status occur overflow. 845 * | | |Note: This overflow bit can be cleared by writing 1. 846 * |[6] |VALID3 |Input Status Valid 3 847 * | | |0 = The pin 3 input status is not ready. 848 * | | |1 = The pin 3 input status is ready. 849 * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. 850 * |[7] |INSTSOV3 |Input Status Overflow 3 851 * | | |0 = The pin 3 input status does not overflow. 852 * | | |1 = The pin 3 input status occur overflow. 853 * | | |Note: This overflow bit can be cleared by writing 1. 854 * |[8] |VALID4 |Input Status Valid 4 855 * | | |0 = The pin 4 input status is not ready. 856 * | | |1 = The pin 4 input status is ready. 857 * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. 858 * |[9] |INSTSOV4 |Input Status Overflow 4 859 * | | |0 = The pin 4 input status does not overflow. 860 * | | |1 = The pin 4 input status occur overflow. 861 * | | |Note: This overflow bit can be cleared by writing 1. 862 * |[10] |VALID5 |Input Status Valid 5 863 * | | |0 = The pin 5 input status is not ready. 864 * | | |1 = The pin 5 input status is ready. 865 * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. 866 * |[11] |INSTSOV5 |Input Status Overflow 5 867 * | | |0 = The pin 5 input status does not overflow. 868 * | | |1 = The pin 5 input status occur overflow. 869 * | | |Note: This overflow bit can be cleared by writing 1. 870 * |[12] |VALID6 |Input Status Valid 6 871 * | | |0 = The pin 6 input status is not ready. 872 * | | |1 = The pin 6 input status is ready. 873 * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. 874 * |[13] |INSTSOV6 |Input Status Overflow 6 875 * | | |0 = The pin 6 input status does not overflow. 876 * | | |1 = The pin 6 input status occur overflow. 877 * | | |Note: This overflow bit can be cleared by writing 1. 878 * |[14] |VALID7 |Input Status Valid 7 879 * | | |0 = The pin7 input status is not ready. 880 * | | |1 = The pin7 input status is ready. 881 * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. 882 * |[15] |INSTSOV7 |Input Status Overflow 7 883 * | | |0 = The pin7 input status does not overflow. 884 * | | |1 = The pin7 input status occur overflow. 885 * | | |Note: This overflow bit can be cleared by writing 1. 886 * @var PSIO_T::PDMACTL 887 * Offset: 0x14 PSIO PDMA Control Register 888 * --------------------------------------------------------------------------------------------------- 889 * |Bits |Field |Descriptions 890 * | :----: | :----: | :---- | 891 * |[0] |OPIN0EN |Output PDMA Pin0 Enable Bit 892 * | | |0 = Pin0 output PDMA function Disabled. 893 * | | |1 = Pin0 output PDMA function Enabled. 894 * |[1] |OPIN1EN |Output PDMA Pin1 Enable Bit 895 * | | |0 = Pin1 output PDMA function Disabled. 896 * | | |1 = Pin1 output PDMA function Enabled. 897 * |[2] |OPIN2EN |Output PDMA Pin2 Enable Bit 898 * | | |0 = Pin2 output PDMA function Disabled. 899 * | | |1 = Pin2 output PDMA function Enabled. 900 * |[3] |OPIN3EN |Output PDMA Pin3 Enable Bit 901 * | | |0 = Pin3 output PDMA function Disabled. 902 * | | |1 = Pin3 output PDMA function Enabled. 903 * |[4] |OPIN4EN |Output PDMA Pin4 Enable Bit 904 * | | |0 = Pin4 output PDMA function Disabled. 905 * | | |1 = Pin4 output PDMA function Enabled. 906 * |[5] |OPIN5EN |Output PDMA Pin5 Enable Bit 907 * | | |0 = Pin5 output PDMA function Disabled. 908 * | | |1 = Pin5 output PDMA function Enabled. 909 * |[6] |OPIN6EN |Output PDMA Pin6 Enable Bit 910 * | | |0 = Pin6 output PDMA function Disabled. 911 * | | |1 = Pin6 output PDMA function Enabled. 912 * |[7] |OPIN7EN |Output PDMA Pin7 Enable Bit 913 * | | |0 = Pin7 output PDMA function Disabled. 914 * | | |1 = Pin7 output PDMA function Enabled. 915 * |[8] |IPIN0EN |Input PDMA Pin0 Enable Bit 916 * | | |0 = Pin0 input PDMA function Disabled. 917 * | | |1 = Pin0 input PDMA function Enabled. 918 * |[9] |IPIN1EN |Input PDMA Pin1 Enable Bit 919 * | | |0 = Pin1 input PDMA function Disabled. 920 * | | |1 = Pin1 input PDMA function Enabled. 921 * |[10] |IPIN2EN |Input PDMA Pin2 Enable Bit 922 * | | |0 = Pin2 input PDMA function Disabled. 923 * | | |1 = Pin2 input PDMA function Enabled. 924 * |[11] |IPIN3EN |Input PDMA Pin3 Enable Bit 925 * | | |0 = Pin3 input PDMA function Disabled. 926 * | | |1 = Pin3 input PDMA function Enabled. 927 * |[12] |IPIN4EN |Input PDMA Pin4 Enable Bit 928 * | | |0 = Pin4 input PDMA function Disabled. 929 * | | |1 = Pin4 input PDMA function Enabled. 930 * |[13] |IPIN5EN |Input PDMA Pin5 Enable Bit 931 * | | |0 = Pin5 input PDMA function Disabled. 932 * | | |1 = Pin5 input PDMA function Enabled. 933 * |[14] |IPIN6EN |Input PDMA Pin6 Enable Bit 934 * | | |0 = Pin6 input PDMA function Disabled. 935 * | | |1 = Pin6 input PDMA function Enabled. 936 * |[15] |IPIN7EN |Input PDMA Pin7 Enable Bit 937 * | | |0 = Pin7 input PDMA function Disabled. 938 * | | |1 = Pin7 input PDMA function Enabled. 939 * |[19:16] |OUTNUM |PDMA Output Current Number (Read Only) 940 * | | |0000 = PDMA IDLE. 941 * | | |0001 = Pin 0. 942 * | | |0010 = Pin 1. 943 * | | |0011 = Pin 2. 944 * | | |0100 = Pin 3. 945 * | | |0101 = Pin 4. 946 * | | |0110 = Pin 5. 947 * | | |0111 = Pin 6. 948 * | | |1000 = Pin 7. 949 * | | |1001 = PDMA WAIT. 950 * | | |Others = Reserved. 951 * | | |This register shows the current pin number of output register write by PDMA. 952 * |[21:20] |OUTSCSEL |PDMA Output Data Slot Controller Selection 953 * | | |00 = Slot controller 0. 954 * | | |01 = Slot controller 1. 955 * | | |10 = Slot controller 2. 956 * | | |11 = Slot controller 3. 957 * |[27:24] |INNUM |PDMA Input Current Number (Read Only) 958 * | | |0000 = PDMA IDLE. 959 * | | |0001 = Pin 0. 960 * | | |0010 = Pin 1. 961 * | | |0011 = Pin 2. 962 * | | |0100 = Pin 3. 963 * | | |0101 = Pin 4. 964 * | | |0110 = Pin 5. 965 * | | |0111 = Pin 6. 966 * | | |1000 = Pin 7. 967 * | | |1001 = PDMA WAIT. 968 * | | |Others = reserved. 969 * | | |This register shows the current pin number of input register read by PDMA. 970 * |[29:28] |INSCSEL |PDMA Input Data Slot Controller Selection 971 * | | |00 = Slot controller 0. 972 * | | |01 = Slot controller 1. 973 * | | |10 = Slot controller 2. 974 * | | |11 = Slot controller 3. 975 * @var PSIO_T::PODAT 976 * Offset: 0x18 PSIO PDMA Output Data Register 977 * --------------------------------------------------------------------------------------------------- 978 * |Bits |Field |Descriptions 979 * | :----: | :----: | :---- | 980 * |[31:0] |PDMAOUT |PDMA Output Data 981 * | | |This register is used for PSIO with PDMA single mode, and set PDMA with fixed address. 982 * | | |When PSIO in PDMA mode, setting PDMA to write data to this register. 983 * | | |The data in this register will be placed to corresponding PSIOn_OUTDAT register in order, when Output Data Empty Flag is 1 and PDMA mode enabled. 984 * @var PSIO_T::PIDAT 985 * Offset: 0x1C PSIO PDMA Input Data Register 986 * --------------------------------------------------------------------------------------------------- 987 * |Bits |Field |Descriptions 988 * | :----: | :----: | :---- | 989 * |[31:0] |PDMAIN |PDMA Input Data 990 * | | |This register is used for PSIO with PDMA single mode, and set PDMA with fixed address. 991 * | | |When PSIO in PDMA mode, setting PDMA to read data from this register. 992 * | | |The data in this register will be updated from corresponding PSIOn_INDAT register in order, when Input Data Full Flag is 1 and PDMA mode enable. 993 */ 994 __IO uint32_t INTCTL; /*!< [0x0000] PSIO Interrupt Control Register */ 995 __IO uint32_t INTEN; /*!< [0x0004] PSIO Interrupt Enable Register */ 996 __IO uint32_t INTSTS; /*!< [0x0008] PSIO Interrupt Status Register */ 997 __IO uint32_t TRANSTS; /*!< [0x000c] PSIO Transfer Status Register */ 998 __IO uint32_t ISSTS; /*!< [0x0010] PSIO Input Status State Register */ 999 __IO uint32_t PDMACTL; /*!< [0x0014] PSIO PDMA Control Register */ 1000 __O uint32_t PODAT; /*!< [0x0018] PSIO PDMA Output Data Register */ 1001 __IO uint32_t PIDAT; /*!< [0x001c] PSIO PDMA Input Data Register */ 1002 SCCT_T SCCT[4]; /*!< [0x0020 ~ 0x0048] PSIO Slot Controller n Registers */ 1003 GNCT_T GNCT[8]; /*!< [0x0040 ~ 0x0138] PSIOn Control Registers */ 1004 } PSIO_T; 1005 1006 /** 1007 @addtogroup PSIO_CONST PSIO Bit Field Definition 1008 Constant Definitions for PSIO Controller 1009 @{ */ 1010 1011 #define PSIO_INTCTL_CONI0SS_Pos (0) /*!< PSIO_T::INTCTL: INT0CSEL Position */ 1012 #define PSIO_INTCTL_CONI0SS_Msk (0xful << PSIO_INTCTL_CONI0SS_Pos) /*!< PSIO_T::INTCTL: INT0CSEL Mask */ 1013 1014 #define PSIO_INTCTL_CONI1SS_Pos (4) /*!< PSIO_T::INTCTL: INT1CSEL Position */ 1015 #define PSIO_INTCTL_CONI1SS_Msk (0xful << PSIO_INTCTL_CONI1SS_Pos) /*!< PSIO_T::INTCTL: INT1CSEL Mask */ 1016 1017 #define PSIO_INTCTL_CONI0SCS_Pos (8) /*!< PSIO_T::INTCTL: INT0SSEL Position */ 1018 #define PSIO_INTCTL_CONI0SCS_Msk (0x3ul << PSIO_INTCTL_CONI0SCS_Pos) /*!< PSIO_T::INTCTL: INT0SSEL Mask */ 1019 1020 #define PSIO_INTCTL_CONI1SCS_Pos (12) /*!< PSIO_T::INTCTL: INT1SSEL Position */ 1021 #define PSIO_INTCTL_CONI1SCS_Msk (0x3ul << PSIO_INTCTL_CONI1SCS_Pos) /*!< PSIO_T::INTCTL: INT1SSEL Mask */ 1022 1023 #define PSIO_INTEN_CON0IE_Pos (0) /*!< PSIO_T::INTEN: INTEN0 Position */ 1024 #define PSIO_INTEN_CON0IE_Msk (0x1ul << PSIO_INTEN_CON0IE_Pos) /*!< PSIO_T::INTEN: INTEN0 Mask */ 1025 1026 #define PSIO_INTEN_CON1IE_Pos (1) /*!< PSIO_T::INTEN: INTEN1 Position */ 1027 #define PSIO_INTEN_CON1IE_Msk (0x1ul << PSIO_INTEN_CON1IE_Pos) /*!< PSIO_T::INTEN: INTEN1 Mask */ 1028 1029 #define PSIO_INTEN_MISMATIE_Pos (2) /*!< PSIO_T::INTEN: MISMATIE Position */ 1030 #define PSIO_INTEN_MISMATIE_Msk (0x1ul << PSIO_INTEN_MISMATIE_Pos) /*!< PSIO_T::INTEN: MISMATIE Mask */ 1031 1032 #define PSIO_INTEN_TERRIE_Pos (3) /*!< PSIO_T::INTEN: TERRIE Position */ 1033 #define PSIO_INTEN_TERRIE_Msk (0x1ul << PSIO_INTEN_TERRIE_Pos) /*!< PSIO_T::INTEN: TERRIE Mask */ 1034 1035 #define PSIO_INTEN_SC0IE_Pos (4) /*!< PSIO_T::INTEN: SC0IE Position */ 1036 #define PSIO_INTEN_SC0IE_Msk (0x1ul << PSIO_INTEN_SC0IE_Pos) /*!< PSIO_T::INTEN: SC0IE Mask */ 1037 1038 #define PSIO_INTEN_SC1IE_Pos (5) /*!< PSIO_T::INTEN: SC1IE Position */ 1039 #define PSIO_INTEN_SC1IE_Msk (0x1ul << PSIO_INTEN_SC1IE_Pos) /*!< PSIO_T::INTEN: SC1IE Mask */ 1040 1041 #define PSIO_INTEN_SC2IE_Pos (6) /*!< PSIO_T::INTEN: SC2IE Position */ 1042 #define PSIO_INTEN_SC2IE_Msk (0x1ul << PSIO_INTEN_SC2IE_Pos) /*!< PSIO_T::INTEN: SC2IE Mask */ 1043 1044 #define PSIO_INTEN_SC3IE_Pos (7) /*!< PSIO_T::INTEN: SC3IE Position */ 1045 #define PSIO_INTEN_SC3IE_Msk (0x1ul << PSIO_INTEN_SC3IE_Pos) /*!< PSIO_T::INTEN: SC3IE Mask */ 1046 1047 #define PSIO_INTSTS_CON0IF_Pos (0) /*!< PSIO_T::INTSTS: INTIF0 Position */ 1048 #define PSIO_INTSTS_CON0IF_Msk (0x1ul << PSIO_INTSTS_CON0IF_Pos) /*!< PSIO_T::INTSTS: INTIF0 Mask */ 1049 1050 #define PSIO_INTSTS_CON1IF_Pos (1) /*!< PSIO_T::INTSTS: INTIF1 Position */ 1051 #define PSIO_INTSTS_CON1IF_Msk (0x1ul << PSIO_INTSTS_CON1IF_Pos) /*!< PSIO_T::INTSTS: INTIF1 Mask */ 1052 1053 #define PSIO_INTSTS_MISMATIF_Pos (2) /*!< PSIO_T::INTSTS: MISMATIF Position */ 1054 #define PSIO_INTSTS_MISMATIF_Msk (0x1ul << PSIO_INTSTS_MISMATIF_Pos) /*!< PSIO_T::INTSTS: MISMATIF Mask */ 1055 1056 #define PSIO_INTSTS_TERRIF_Pos (3) /*!< PSIO_T::INTSTS: TERRIF Position */ 1057 #define PSIO_INTSTS_TERRIF_Msk (0x1ul << PSIO_INTSTS_TERRIF_Pos) /*!< PSIO_T::INTSTS: TERRIF Mask */ 1058 1059 #define PSIO_INTSTS_SC0IF_Pos (4) /*!< PSIO_T::INTSTS: SC0IF Position */ 1060 #define PSIO_INTSTS_SC0IF_Msk (0x1ul << PSIO_INTSTS_SC0IF_Pos) /*!< PSIO_T::INTSTS: SC0IF Mask */ 1061 1062 #define PSIO_INTSTS_SC1IF_Pos (5) /*!< PSIO_T::INTSTS: SC1IF Position */ 1063 #define PSIO_INTSTS_SC1IF_Msk (0x1ul << PSIO_INTSTS_SC1IF_Pos) /*!< PSIO_T::INTSTS: SC1IF Mask */ 1064 1065 #define PSIO_INTSTS_SC2IF_Pos (6) /*!< PSIO_T::INTSTS: SC2IF Position */ 1066 #define PSIO_INTSTS_SC2IF_Msk (0x1ul << PSIO_INTSTS_SC2IF_Pos) /*!< PSIO_T::INTSTS: SC2IF Mask */ 1067 1068 #define PSIO_INTSTS_SC3IF_Pos (7) /*!< PSIO_T::INTSTS: SC3IF Position */ 1069 #define PSIO_INTSTS_SC3IF_Msk (0x1ul << PSIO_INTSTS_SC3IF_Pos) /*!< PSIO_T::INTSTS: SC3IF Mask */ 1070 1071 #define PSIO_TRANSTS_INFULL0_Pos (0) /*!< PSIO_T::TRANSTS: INFULL0 Position */ 1072 #define PSIO_TRANSTS_INFULL0_Msk (0x1ul << PSIO_TRANSTS_INFULL0_Pos) /*!< PSIO_T::TRANSTS: INFULL0 Mask */ 1073 1074 #define PSIO_TRANSTS_INOVER0_Pos (1) /*!< PSIO_T::TRANSTS: INOVER0 Position */ 1075 #define PSIO_TRANSTS_INOVER0_Msk (0x1ul << PSIO_TRANSTS_INOVER0_Pos) /*!< PSIO_T::TRANSTS: INOVER0 Mask */ 1076 1077 #define PSIO_TRANSTS_OUTEPY0_Pos (2) /*!< PSIO_T::TRANSTS: OUTEPY0 Position */ 1078 #define PSIO_TRANSTS_OUTEPY0_Msk (0x1ul << PSIO_TRANSTS_OUTEPY0_Pos) /*!< PSIO_T::TRANSTS: OUTEPY0 Mask */ 1079 1080 #define PSIO_TRANSTS_OUTUF0_Pos (3) /*!< PSIO_T::TRANSTS: OUTUF0 Position */ 1081 #define PSIO_TRANSTS_OUTUF0_Msk (0x1ul << PSIO_TRANSTS_OUTUF0_Pos) /*!< PSIO_T::TRANSTS: OUTUF0 Mask */ 1082 1083 #define PSIO_TRANSTS_INFULL1_Pos (4) /*!< PSIO_T::TRANSTS: INFULL1 Position */ 1084 #define PSIO_TRANSTS_INFULL1_Msk (0x1ul << PSIO_TRANSTS_INFULL1_Pos) /*!< PSIO_T::TRANSTS: INFULL1 Mask */ 1085 1086 #define PSIO_TRANSTS_INOVER1_Pos (5) /*!< PSIO_T::TRANSTS: INOVER1 Position */ 1087 #define PSIO_TRANSTS_INOVER1_Msk (0x1ul << PSIO_TRANSTS_INOVER1_Pos) /*!< PSIO_T::TRANSTS: INOVER1 Mask */ 1088 1089 #define PSIO_TRANSTS_OUTEPY1_Pos (6) /*!< PSIO_T::TRANSTS: OUTEPY1 Position */ 1090 #define PSIO_TRANSTS_OUTEPY1_Msk (0x1ul << PSIO_TRANSTS_OUTEPY1_Pos) /*!< PSIO_T::TRANSTS: OUTEPY1 Mask */ 1091 1092 #define PSIO_TRANSTS_OUTUF1_Pos (7) /*!< PSIO_T::TRANSTS: OUTUF1 Position */ 1093 #define PSIO_TRANSTS_OUTUF1_Msk (0x1ul << PSIO_TRANSTS_OUTUF1_Pos) /*!< PSIO_T::TRANSTS: OUTUF1 Mask */ 1094 1095 #define PSIO_TRANSTS_INFULL2_Pos (8) /*!< PSIO_T::TRANSTS: INFULL2 Position */ 1096 #define PSIO_TRANSTS_INFULL2_Msk (0x1ul << PSIO_TRANSTS_INFULL2_Pos) /*!< PSIO_T::TRANSTS: INFULL2 Mask */ 1097 1098 #define PSIO_TRANSTS_INOVER2_Pos (9) /*!< PSIO_T::TRANSTS: INOVER2 Position */ 1099 #define PSIO_TRANSTS_INOVER2_Msk (0x1ul << PSIO_TRANSTS_INOVER2_Pos) /*!< PSIO_T::TRANSTS: INOVER2 Mask */ 1100 1101 #define PSIO_TRANSTS_OUTEPY2_Pos (10) /*!< PSIO_T::TRANSTS: OUTEPY2 Position */ 1102 #define PSIO_TRANSTS_OUTEPY2_Msk (0x1ul << PSIO_TRANSTS_OUTEPY2_Pos) /*!< PSIO_T::TRANSTS: OUTEPY2 Mask */ 1103 1104 #define PSIO_TRANSTS_OUTUF2_Pos (11) /*!< PSIO_T::TRANSTS: OUTUF2 Position */ 1105 #define PSIO_TRANSTS_OUTUF2_Msk (0x1ul << PSIO_TRANSTS_OUTUF2_Pos) /*!< PSIO_T::TRANSTS: OUTUF2 Mask */ 1106 1107 #define PSIO_TRANSTS_INFULL3_Pos (12) /*!< PSIO_T::TRANSTS: INFULL3 Position */ 1108 #define PSIO_TRANSTS_INFULL3_Msk (0x1ul << PSIO_TRANSTS_INFULL3_Pos) /*!< PSIO_T::TRANSTS: INFULL3 Mask */ 1109 1110 #define PSIO_TRANSTS_INOVER3_Pos (13) /*!< PSIO_T::TRANSTS: INOVER3 Position */ 1111 #define PSIO_TRANSTS_INOVER3_Msk (0x1ul << PSIO_TRANSTS_INOVER3_Pos) /*!< PSIO_T::TRANSTS: INOVER3 Mask */ 1112 1113 #define PSIO_TRANSTS_OUTEPY3_Pos (14) /*!< PSIO_T::TRANSTS: OUTEPY3 Position */ 1114 #define PSIO_TRANSTS_OUTEPY3_Msk (0x1ul << PSIO_TRANSTS_OUTEPY3_Pos) /*!< PSIO_T::TRANSTS: OUTEPY3 Mask */ 1115 1116 #define PSIO_TRANSTS_OUTUF3_Pos (15) /*!< PSIO_T::TRANSTS: OUTUF3 Position */ 1117 #define PSIO_TRANSTS_OUTUF3_Msk (0x1ul << PSIO_TRANSTS_OUTUF3_Pos) /*!< PSIO_T::TRANSTS: OUTUF3 Mask */ 1118 1119 #define PSIO_TRANSTS_INFULL4_Pos (16) /*!< PSIO_T::TRANSTS: INFULL4 Position */ 1120 #define PSIO_TRANSTS_INFULL4_Msk (0x1ul << PSIO_TRANSTS_INFULL4_Pos) /*!< PSIO_T::TRANSTS: INFULL4 Mask */ 1121 1122 #define PSIO_TRANSTS_INOVER4_Pos (17) /*!< PSIO_T::TRANSTS: INOVER4 Position */ 1123 #define PSIO_TRANSTS_INOVER4_Msk (0x1ul << PSIO_TRANSTS_INOVER4_Pos) /*!< PSIO_T::TRANSTS: INOVER4 Mask */ 1124 1125 #define PSIO_TRANSTS_OUTEPY4_Pos (18) /*!< PSIO_T::TRANSTS: OUTEPY4 Position */ 1126 #define PSIO_TRANSTS_OUTEPY4_Msk (0x1ul << PSIO_TRANSTS_OUTEPY4_Pos) /*!< PSIO_T::TRANSTS: OUTEPY4 Mask */ 1127 1128 #define PSIO_TRANSTS_OUTUF4_Pos (19) /*!< PSIO_T::TRANSTS: OUTUF4 Position */ 1129 #define PSIO_TRANSTS_OUTUF4_Msk (0x1ul << PSIO_TRANSTS_OUTUF4_Pos) /*!< PSIO_T::TRANSTS: OUTUF4 Mask */ 1130 1131 #define PSIO_TRANSTS_INFULL5_Pos (20) /*!< PSIO_T::TRANSTS: INFULL5 Position */ 1132 #define PSIO_TRANSTS_INFULL5_Msk (0x1ul << PSIO_TRANSTS_INFULL5_Pos) /*!< PSIO_T::TRANSTS: INFULL5 Mask */ 1133 1134 #define PSIO_TRANSTS_INOVER5_Pos (21) /*!< PSIO_T::TRANSTS: INOVER5 Position */ 1135 #define PSIO_TRANSTS_INOVER5_Msk (0x1ul << PSIO_TRANSTS_INOVER5_Pos) /*!< PSIO_T::TRANSTS: INOVER5 Mask */ 1136 1137 #define PSIO_TRANSTS_OUTEPY5_Pos (22) /*!< PSIO_T::TRANSTS: OUTEPY5 Position */ 1138 #define PSIO_TRANSTS_OUTEPY5_Msk (0x1ul << PSIO_TRANSTS_OUTEPY5_Pos) /*!< PSIO_T::TRANSTS: OUTEPY5 Mask */ 1139 1140 #define PSIO_TRANSTS_OUTUF5_Pos (23) /*!< PSIO_T::TRANSTS: OUTUF5 Position */ 1141 #define PSIO_TRANSTS_OUTUF5_Msk (0x1ul << PSIO_TRANSTS_OUTUF5_Pos) /*!< PSIO_T::TRANSTS: OUTUF5 Mask */ 1142 1143 #define PSIO_TRANSTS_INFULL6_Pos (24) /*!< PSIO_T::TRANSTS: INFULL6 Position */ 1144 #define PSIO_TRANSTS_INFULL6_Msk (0x1ul << PSIO_TRANSTS_INFULL6_Pos) /*!< PSIO_T::TRANSTS: INFULL6 Mask */ 1145 1146 #define PSIO_TRANSTS_INOVER6_Pos (25) /*!< PSIO_T::TRANSTS: INOVER6 Position */ 1147 #define PSIO_TRANSTS_INOVER6_Msk (0x1ul << PSIO_TRANSTS_INOVER6_Pos) /*!< PSIO_T::TRANSTS: INOVER6 Mask */ 1148 1149 #define PSIO_TRANSTS_OUTEPY6_Pos (26) /*!< PSIO_T::TRANSTS: OUTEPY6 Position */ 1150 #define PSIO_TRANSTS_OUTEPY6_Msk (0x1ul << PSIO_TRANSTS_OUTEPY6_Pos) /*!< PSIO_T::TRANSTS: OUTEPY6 Mask */ 1151 1152 #define PSIO_TRANSTS_OUTUF6_Pos (27) /*!< PSIO_T::TRANSTS: OUTUF6 Position */ 1153 #define PSIO_TRANSTS_OUTUF6_Msk (0x1ul << PSIO_TRANSTS_OUTUF6_Pos) /*!< PSIO_T::TRANSTS: OUTUF6 Mask */ 1154 1155 #define PSIO_TRANSTS_INFULL7_Pos (28) /*!< PSIO_T::TRANSTS: INFULL7 Position */ 1156 #define PSIO_TRANSTS_INFULL7_Msk (0x1ul << PSIO_TRANSTS_INFULL7_Pos) /*!< PSIO_T::TRANSTS: INFULL7 Mask */ 1157 1158 #define PSIO_TRANSTS_INOVER7_Pos (29) /*!< PSIO_T::TRANSTS: INOVER7 Position */ 1159 #define PSIO_TRANSTS_INOVER7_Msk (0x1ul << PSIO_TRANSTS_INOVER7_Pos) /*!< PSIO_T::TRANSTS: INOVER7 Mask */ 1160 1161 #define PSIO_TRANSTS_OUTEPY7_Pos (30) /*!< PSIO_T::TRANSTS: OUTEPY7 Position */ 1162 #define PSIO_TRANSTS_OUTEPY7_Msk (0x1ul << PSIO_TRANSTS_OUTEPY7_Pos) /*!< PSIO_T::TRANSTS: OUTEPY7 Mask */ 1163 1164 #define PSIO_TRANSTS_OUTUF7_Pos (31) /*!< PSIO_T::TRANSTS: OUTUF7 Position */ 1165 #define PSIO_TRANSTS_OUTUF7_Msk (0x1ul << PSIO_TRANSTS_OUTUF7_Pos) /*!< PSIO_T::TRANSTS: OUTUF7 Mask */ 1166 1167 #define PSIO_ISSTS_VALID0_Pos (0) /*!< PSIO_T::ISSTS: VALID0 Position */ 1168 #define PSIO_ISSTS_VALID0_Msk (0x1ul << PSIO_ISSTS_VALID0_Pos) /*!< PSIO_T::ISSTS: VALID0 Mask */ 1169 1170 #define PSIO_ISSTS_INSTSOV0_Pos (1) /*!< PSIO_T::ISSTS: INSTSOV0 Position */ 1171 #define PSIO_ISSTS_INSTSOV0_Msk (0x1ul << PSIO_ISSTS_INSTSOV0_Pos) /*!< PSIO_T::ISSTS: INSTSOV0 Mask */ 1172 1173 #define PSIO_ISSTS_VALID1_Pos (2) /*!< PSIO_T::ISSTS: VALID1 Position */ 1174 #define PSIO_ISSTS_VALID1_Msk (0x1ul << PSIO_ISSTS_VALID1_Pos) /*!< PSIO_T::ISSTS: VALID1 Mask */ 1175 1176 #define PSIO_ISSTS_INSTSOV1_Pos (3) /*!< PSIO_T::ISSTS: INSTSOV1 Position */ 1177 #define PSIO_ISSTS_INSTSOV1_Msk (0x1ul << PSIO_ISSTS_INSTSOV1_Pos) /*!< PSIO_T::ISSTS: INSTSOV1 Mask */ 1178 1179 #define PSIO_ISSTS_VALID2_Pos (4) /*!< PSIO_T::ISSTS: VALID2 Position */ 1180 #define PSIO_ISSTS_VALID2_Msk (0x1ul << PSIO_ISSTS_VALID2_Pos) /*!< PSIO_T::ISSTS: VALID2 Mask */ 1181 1182 #define PSIO_ISSTS_INSTSOV2_Pos (5) /*!< PSIO_T::ISSTS: INSTSOV2 Position */ 1183 #define PSIO_ISSTS_INSTSOV2_Msk (0x1ul << PSIO_ISSTS_INSTSOV2_Pos) /*!< PSIO_T::ISSTS: INSTSOV2 Mask */ 1184 1185 #define PSIO_ISSTS_VALID3_Pos (6) /*!< PSIO_T::ISSTS: VALID3 Position */ 1186 #define PSIO_ISSTS_VALID3_Msk (0x1ul << PSIO_ISSTS_VALID3_Pos) /*!< PSIO_T::ISSTS: VALID3 Mask */ 1187 1188 #define PSIO_ISSTS_INSTSOV3_Pos (7) /*!< PSIO_T::ISSTS: INSTSOV3 Position */ 1189 #define PSIO_ISSTS_INSTSOV3_Msk (0x1ul << PSIO_ISSTS_INSTSOV3_Pos) /*!< PSIO_T::ISSTS: INSTSOV3 Mask */ 1190 1191 #define PSIO_ISSTS_VALID4_Pos (8) /*!< PSIO_T::ISSTS: VALID4 Position */ 1192 #define PSIO_ISSTS_VALID4_Msk (0x1ul << PSIO_ISSTS_VALID4_Pos) /*!< PSIO_T::ISSTS: VALID4 Mask */ 1193 1194 #define PSIO_ISSTS_INSTSOV4_Pos (9) /*!< PSIO_T::ISSTS: INSTSOV4 Position */ 1195 #define PSIO_ISSTS_INSTSOV4_Msk (0x1ul << PSIO_ISSTS_INSTSOV4_Pos) /*!< PSIO_T::ISSTS: INSTSOV4 Mask */ 1196 1197 #define PSIO_ISSTS_VALID5_Pos (10) /*!< PSIO_T::ISSTS: VALID5 Position */ 1198 #define PSIO_ISSTS_VALID5_Msk (0x1ul << PSIO_ISSTS_VALID5_Pos) /*!< PSIO_T::ISSTS: VALID5 Mask */ 1199 1200 #define PSIO_ISSTS_INSTSOV5_Pos (11) /*!< PSIO_T::ISSTS: INSTSOV5 Position */ 1201 #define PSIO_ISSTS_INSTSOV5_Msk (0x1ul << PSIO_ISSTS_INSTSOV5_Pos) /*!< PSIO_T::ISSTS: INSTSOV5 Mask */ 1202 1203 #define PSIO_ISSTS_VALID6_Pos (12) /*!< PSIO_T::ISSTS: VALID6 Position */ 1204 #define PSIO_ISSTS_VALID6_Msk (0x1ul << PSIO_ISSTS_VALID6_Pos) /*!< PSIO_T::ISSTS: VALID6 Mask */ 1205 1206 #define PSIO_ISSTS_INSTSOV6_Pos (13) /*!< PSIO_T::ISSTS: INSTSOV6 Position */ 1207 #define PSIO_ISSTS_INSTSOV6_Msk (0x1ul << PSIO_ISSTS_INSTSOV6_Pos) /*!< PSIO_T::ISSTS: INSTSOV6 Mask */ 1208 1209 #define PSIO_ISSTS_VALID7_Pos (14) /*!< PSIO_T::ISSTS: VALID7 Position */ 1210 #define PSIO_ISSTS_VALID7_Msk (0x1ul << PSIO_ISSTS_VALID7_Pos) /*!< PSIO_T::ISSTS: VALID7 Mask */ 1211 1212 #define PSIO_ISSTS_INSTSOV7_Pos (15) /*!< PSIO_T::ISSTS: INSTSOV7 Position */ 1213 #define PSIO_ISSTS_INSTSOV7_Msk (0x1ul << PSIO_ISSTS_INSTSOV7_Pos) /*!< PSIO_T::ISSTS: INSTSOV7 Mask */ 1214 1215 #define PSIO_PDMACTL_OPIN0EN_Pos (0) /*!< PSIO_T::PDMACTL: OPIN0EN Position */ 1216 #define PSIO_PDMACTL_OPIN0EN_Msk (0x1ul << PSIO_PDMACTL_OPIN0EN_Pos) /*!< PSIO_T::PDMACTL: OPIN0EN Mask */ 1217 1218 #define PSIO_PDMACTL_OPIN1EN_Pos (1) /*!< PSIO_T::PDMACTL: OPIN1EN Position */ 1219 #define PSIO_PDMACTL_OPIN1EN_Msk (0x1ul << PSIO_PDMACTL_OPIN1EN_Pos) /*!< PSIO_T::PDMACTL: OPIN1EN Mask */ 1220 1221 #define PSIO_PDMACTL_OPIN2EN_Pos (2) /*!< PSIO_T::PDMACTL: OPIN2EN Position */ 1222 #define PSIO_PDMACTL_OPIN2EN_Msk (0x1ul << PSIO_PDMACTL_OPIN2EN_Pos) /*!< PSIO_T::PDMACTL: OPIN2EN Mask */ 1223 1224 #define PSIO_PDMACTL_OPIN3EN_Pos (3) /*!< PSIO_T::PDMACTL: OPIN3EN Position */ 1225 #define PSIO_PDMACTL_OPIN3EN_Msk (0x1ul << PSIO_PDMACTL_OPIN3EN_Pos) /*!< PSIO_T::PDMACTL: OPIN3EN Mask */ 1226 1227 #define PSIO_PDMACTL_OPIN4EN_Pos (4) /*!< PSIO_T::PDMACTL: OPIN4EN Position */ 1228 #define PSIO_PDMACTL_OPIN4EN_Msk (0x1ul << PSIO_PDMACTL_OPIN4EN_Pos) /*!< PSIO_T::PDMACTL: OPIN4EN Mask */ 1229 1230 #define PSIO_PDMACTL_OPIN5EN_Pos (5) /*!< PSIO_T::PDMACTL: OPIN5EN Position */ 1231 #define PSIO_PDMACTL_OPIN5EN_Msk (0x1ul << PSIO_PDMACTL_OPIN5EN_Pos) /*!< PSIO_T::PDMACTL: OPIN5EN Mask */ 1232 1233 #define PSIO_PDMACTL_OPIN6EN_Pos (6) /*!< PSIO_T::PDMACTL: OPIN6EN Position */ 1234 #define PSIO_PDMACTL_OPIN6EN_Msk (0x1ul << PSIO_PDMACTL_OPIN6EN_Pos) /*!< PSIO_T::PDMACTL: OPIN6EN Mask */ 1235 1236 #define PSIO_PDMACTL_OPIN7EN_Pos (7) /*!< PSIO_T::PDMACTL: OPIN7EN Position */ 1237 #define PSIO_PDMACTL_OPIN7EN_Msk (0x1ul << PSIO_PDMACTL_OPIN7EN_Pos) /*!< PSIO_T::PDMACTL: OPIN7EN Mask */ 1238 1239 #define PSIO_PDMACTL_IPIN0EN_Pos (8) /*!< PSIO_T::PDMACTL: IPIN0EN Position */ 1240 #define PSIO_PDMACTL_IPIN0EN_Msk (0x1ul << PSIO_PDMACTL_IPIN0EN_Pos) /*!< PSIO_T::PDMACTL: IPIN0EN Mask */ 1241 1242 #define PSIO_PDMACTL_IPIN1EN_Pos (9) /*!< PSIO_T::PDMACTL: IPIN1EN Position */ 1243 #define PSIO_PDMACTL_IPIN1EN_Msk (0x1ul << PSIO_PDMACTL_IPIN1EN_Pos) /*!< PSIO_T::PDMACTL: IPIN1EN Mask */ 1244 1245 #define PSIO_PDMACTL_IPIN2EN_Pos (10) /*!< PSIO_T::PDMACTL: IPIN2EN Position */ 1246 #define PSIO_PDMACTL_IPIN2EN_Msk (0x1ul << PSIO_PDMACTL_IPIN2EN_Pos) /*!< PSIO_T::PDMACTL: IPIN2EN Mask */ 1247 1248 #define PSIO_PDMACTL_IPIN3EN_Pos (11) /*!< PSIO_T::PDMACTL: IPIN3EN Position */ 1249 #define PSIO_PDMACTL_IPIN3EN_Msk (0x1ul << PSIO_PDMACTL_IPIN3EN_Pos) /*!< PSIO_T::PDMACTL: IPIN3EN Mask */ 1250 1251 #define PSIO_PDMACTL_IPIN4EN_Pos (12) /*!< PSIO_T::PDMACTL: IPIN4EN Position */ 1252 #define PSIO_PDMACTL_IPIN4EN_Msk (0x1ul << PSIO_PDMACTL_IPIN4EN_Pos) /*!< PSIO_T::PDMACTL: IPIN4EN Mask */ 1253 1254 #define PSIO_PDMACTL_IPIN5EN_Pos (13) /*!< PSIO_T::PDMACTL: IPIN5EN Position */ 1255 #define PSIO_PDMACTL_IPIN5EN_Msk (0x1ul << PSIO_PDMACTL_IPIN5EN_Pos) /*!< PSIO_T::PDMACTL: IPIN5EN Mask */ 1256 1257 #define PSIO_PDMACTL_IPIN6EN_Pos (14) /*!< PSIO_T::PDMACTL: IPIN6EN Position */ 1258 #define PSIO_PDMACTL_IPIN6EN_Msk (0x1ul << PSIO_PDMACTL_IPIN6EN_Pos) /*!< PSIO_T::PDMACTL: IPIN6EN Mask */ 1259 1260 #define PSIO_PDMACTL_IPIN7EN_Pos (15) /*!< PSIO_T::PDMACTL: IPIN7EN Position */ 1261 #define PSIO_PDMACTL_IPIN7EN_Msk (0x1ul << PSIO_PDMACTL_IPIN7EN_Pos) /*!< PSIO_T::PDMACTL: IPIN7EN Mask */ 1262 1263 #define PSIO_PDMACTL_OUTNUM_Pos (16) /*!< PSIO_T::PDMACTL: OUTNUM Position */ 1264 #define PSIO_PDMACTL_OUTNUM_Msk (0xful << PSIO_PDMACTL_OUTNUM_Pos) /*!< PSIO_T::PDMACTL: OUTNUM Mask */ 1265 1266 #define PSIO_PDMACTL_OUTSCSEL_Pos (20) /*!< PSIO_T::PDMACTL: OUTSCSEL Position */ 1267 #define PSIO_PDMACTL_OUTSCSEL_Msk (0x3ul << PSIO_PDMACTL_OUTSCSEL_Pos) /*!< PSIO_T::PDMACTL: OUTSCSEL Mask */ 1268 1269 #define PSIO_PDMACTL_INNUM_Pos (24) /*!< PSIO_T::PDMACTL: INNUM Position */ 1270 #define PSIO_PDMACTL_INNUM_Msk (0xful << PSIO_PDMACTL_INNUM_Pos) /*!< PSIO_T::PDMACTL: INNUM Mask */ 1271 1272 #define PSIO_PDMACTL_INSCSEL_Pos (28) /*!< PSIO_T::PDMACTL: INSCSEL Position */ 1273 #define PSIO_PDMACTL_INSCSEL_Msk (0x3ul << PSIO_PDMACTL_INSCSEL_Pos) /*!< PSIO_T::PDMACTL: INSCSEL Mask */ 1274 1275 #define PSIO_PODAT_PDMAOUT_Pos (0) /*!< PSIO_T::PODAT: PDMAOUT Position */ 1276 #define PSIO_PODAT_PDMAOUT_Msk (0xfffffffful << PSIO_PODAT_PDMAOUT_Pos) /*!< PSIO_T::PODAT: PDMAOUT Mask */ 1277 1278 #define PSIO_PIDAT_PDMAIN_Pos (0) /*!< PSIO_T::PIDAT: PDMAIN Position */ 1279 #define PSIO_PIDAT_PDMAIN_Msk (0xfffffffful << PSIO_PIDAT_PDMAIN_Pos) /*!< PSIO_T::PIDAT: PDMAIN Mask */ 1280 1281 #define PSIO_SCCT_SCCTL_INISLOT_Pos (0) /*!< PSIO_T::SCCTL: INISLOT Position */ 1282 #define PSIO_SCCT_SCCTL_INISLOT_Msk (0xful << PSIO_SCCT_SCCTL_INISLOT_Pos) /*!< PSIO_T::SCCTL: INISLOT Mask */ 1283 1284 #define PSIO_SCCT_SCCTL_ENDSLOT_Pos (4) /*!< PSIO_T::SCCTL: ENDSLOT Position */ 1285 #define PSIO_SCCT_SCCTL_ENDSLOT_Msk (0xful << PSIO_SCCT_SCCTL_ENDSLOT_Pos) /*!< PSIO_T::SCCTL: ENDSLOT Mask */ 1286 1287 #define PSIO_SCCT_SCCTL_SPLCNT_Pos (8) /*!< PSIO_T::SCCTL: SPLCNT Position */ 1288 #define PSIO_SCCT_SCCTL_SPLCNT_Msk (0x3ful << PSIO_SCCT_SCCTL_SPLCNT_Pos) /*!< PSIO_T::SCCTL: SPLCNT Mask */ 1289 1290 #define PSIO_SCCT_SCCTL_TRIGSRC_Pos (14) /*!< PSIO_T::SCCTL: TRIGSRC Position */ 1291 #define PSIO_SCCT_SCCTL_TRIGSRC_Msk (0x3ul << PSIO_SCCT_SCCTL_TRIGSRC_Pos) /*!< PSIO_T::SCCTL: TRIGSRC Mask */ 1292 1293 #define PSIO_SCCT_SCCTL_START_Pos (16) /*!< PSIO_T::SCCTL: START Position */ 1294 #define PSIO_SCCT_SCCTL_START_Msk (0x1ul << PSIO_SCCT_SCCTL_START_Pos) /*!< PSIO_T::SCCTL: START Mask */ 1295 1296 #define PSIO_SCCT_SCCTL_REPEAT_Pos (17) /*!< PSIO_T::SCCTL: REPEAT Position */ 1297 #define PSIO_SCCT_SCCTL_REPEAT_Msk (0x1ul << PSIO_SCCT_SCCTL_REPEAT_Pos) /*!< PSIO_T::SCCTL: REPEAT Mask */ 1298 1299 #define PSIO_SCCT_SCCTL_STOP_Pos (18) /*!< PSIO_T::SCCTL: STOP Position */ 1300 #define PSIO_SCCT_SCCTL_STOP_Msk (0x1ul << PSIO_SCCT_SCCTL_STOP_Pos) /*!< PSIO_T::SCCTL: STOP Mask */ 1301 1302 #define PSIO_SCCT_SCCTL_BUSY_Pos (24) /*!< PSIO_T::SCCTL: BUSY Position */ 1303 #define PSIO_SCCT_SCCTL_BUSY_Msk (0x1ul << PSIO_SCCT_SCCTL_BUSY_Pos) /*!< PSIO_T::SCCTL: BUSY Mask */ 1304 1305 #define PSIO_SCCT_SCCTL_IDLE_Pos (25) /*!< PSIO_T::SCCTL: IDLE Position */ 1306 #define PSIO_SCCT_SCCTL_IDLE_Msk (0x1ul << PSIO_SCCT_SCCTL_IDLE_Pos) /*!< PSIO_T::SCCTL: IDLE Mask */ 1307 1308 #define PSIO_SCCT_SCSLOT_SLOT0CNT_Pos (0) /*!< PSIO_T::SCSLOT: SLOT0CNT Position */ 1309 #define PSIO_SCCT_SCSLOT_SLOT0CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT0CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT0CNT Mask */ 1310 1311 #define PSIO_SCCT_SCSLOT_SLOT1CNT_Pos (4) /*!< PSIO_T::SCSLOT: SLOT1CNT Position */ 1312 #define PSIO_SCCT_SCSLOT_SLOT1CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT1CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT1CNT Mask */ 1313 1314 #define PSIO_SCCT_SCSLOT_SLOT2CNT_Pos (8) /*!< PSIO_T::SCSLOT: SLOT2CNT Position */ 1315 #define PSIO_SCCT_SCSLOT_SLOT2CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT2CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT2CNT Mask */ 1316 1317 #define PSIO_SCCT_SCSLOT_SLOT3CNT_Pos (12) /*!< PSIO_T::SCSLOT: SLOT3CNT Position */ 1318 #define PSIO_SCCT_SCSLOT_SLOT3CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT3CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT3CNT Mask */ 1319 1320 #define PSIO_SCCT_SCSLOT_SLOT4CNT_Pos (16) /*!< PSIO_T::SCSLOT: SLOT4CNT Position */ 1321 #define PSIO_SCCT_SCSLOT_SLOT4CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT4CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT4CNT Mask */ 1322 1323 #define PSIO_SCCT_SCSLOT_SLOT5CNT_Pos (20) /*!< PSIO_T::SCSLOT: SLOT5CNT Position */ 1324 #define PSIO_SCCT_SCSLOT_SLOT5CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT5CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT5CNT Mask */ 1325 1326 #define PSIO_SCCT_SCSLOT_SLOT6CNT_Pos (24) /*!< PSIO_T::SCSLOT: SLOT6CNT Position */ 1327 #define PSIO_SCCT_SCSLOT_SLOT6CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT6CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT6CNT Mask */ 1328 1329 #define PSIO_SCCT_SCSLOT_SLOT7CNT_Pos (28) /*!< PSIO_T::SCSLOT: SLOT7CNT Position */ 1330 #define PSIO_SCCT_SCSLOT_SLOT7CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT7CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT7CNT Mask */ 1331 1332 #define PSIO_GNCT_GENCTL_IOMODE_Pos (0) /*!< PSIO_T::GENCTL: IOMODE Position */ 1333 #define PSIO_GNCT_GENCTL_IOMODE_Msk (0x3ul << PSIO_GNCT_GENCTL_IOMODE_Pos) /*!< PSIO_T::GENCTL: IOMODE Mask */ 1334 1335 #define PSIO_GNCT_GENCTL_INITIAL_Pos (2) /*!< PSIO_T::GENCTL: INITIAL Position */ 1336 #define PSIO_GNCT_GENCTL_INITIAL_Msk (0x3ul << PSIO_GNCT_GENCTL_INITIAL_Pos) /*!< PSIO_T::GENCTL: INITIAL Mask */ 1337 1338 #define PSIO_GNCT_GENCTL_INTERVAL_Pos (4) /*!< PSIO_T::GENCTL: INTERVAL Position */ 1339 #define PSIO_GNCT_GENCTL_INTERVAL_Msk (0x3ul << PSIO_GNCT_GENCTL_INTERVAL_Pos) /*!< PSIO_T::GENCTL: INTERVAL Mask */ 1340 1341 #define PSIO_GNCT_GENCTL_SW0CP_Pos (8) /*!< PSIO_T::GENCTL: SW0CP Position */ 1342 #define PSIO_GNCT_GENCTL_SW0CP_Msk (0xful << PSIO_GNCT_GENCTL_SW0CP_Pos) /*!< PSIO_T::GENCTL: SW0CP Mask */ 1343 1344 #define PSIO_GNCT_GENCTL_SW1CP_Pos (12) /*!< PSIO_T::GENCTL: SW1CP Position */ 1345 #define PSIO_GNCT_GENCTL_SW1CP_Msk (0xful << PSIO_GNCT_GENCTL_SW1CP_Pos) /*!< PSIO_T::GENCTL: SW1CP Mask */ 1346 1347 #define PSIO_GNCT_GENCTL_MODESW0_Pos (16) /*!< PSIO_T::GENCTL: MODESW0 Position */ 1348 #define PSIO_GNCT_GENCTL_MODESW0_Msk (0x3ul << PSIO_GNCT_GENCTL_MODESW0_Pos) /*!< PSIO_T::GENCTL: MODESW0 Mask */ 1349 1350 #define PSIO_GNCT_GENCTL_MODESW1_Pos (18) /*!< PSIO_T::GENCTL: MODESW1 Position */ 1351 #define PSIO_GNCT_GENCTL_MODESW1_Msk (0x3ul << PSIO_GNCT_GENCTL_MODESW1_Pos) /*!< PSIO_T::GENCTL: MODESW1 Mask */ 1352 1353 #define PSIO_GNCT_GENCTL_SCSEL_Pos (24) /*!< PSIO_T::GENCTL: SCSEL Position */ 1354 #define PSIO_GNCT_GENCTL_SCSEL_Msk (0x3ul << PSIO_GNCT_GENCTL_SCSEL_Pos) /*!< PSIO_T::GENCTL: SCSEL Mask */ 1355 1356 #define PSIO_GNCT_GENCTL_PINEN_Pos (26) /*!< PSIO_T::GENCTL: PINEN Position */ 1357 #define PSIO_GNCT_GENCTL_PINEN_Msk (0x1ul << PSIO_GNCT_GENCTL_PINEN_Pos) /*!< PSIO_T::GENCTL: PINEN Mask */ 1358 1359 #define PSIO_GNCT_DATCTL_OUTDATWD_Pos (0) /*!< PSIO_T::DATCTL: OUTDATWD Position */ 1360 #define PSIO_GNCT_DATCTL_OUTDATWD_Msk (0x1ful << PSIO_GNCT_DATCTL_OUTDATWD_Pos) /*!< PSIO_T::DATCTL: OUTDATWD Mask */ 1361 1362 #define PSIO_GNCT_DATCTL_INDATWD_Pos (8) /*!< PSIO_T::DATCTL: INDATWD Position */ 1363 #define PSIO_GNCT_DATCTL_INDATWD_Msk (0x1ful << PSIO_GNCT_DATCTL_INDATWD_Pos) /*!< PSIO_T::DATCTL: INDATWD Mask */ 1364 1365 #define PSIO_GNCT_DATCTL_ORDER_Pos (16) /*!< PSIO_T::DATCTL: ORDER Position */ 1366 #define PSIO_GNCT_DATCTL_ORDER_Msk (0x1ul << PSIO_GNCT_DATCTL_ORDER_Pos) /*!< PSIO_T::DATCTL: ORDER Mask */ 1367 1368 #define PSIO_GNCT_DATCTL_OUTDEPTH_Pos (24) /*!< PSIO_T::DATCTL: OUTDEPTH Position */ 1369 #define PSIO_GNCT_DATCTL_OUTDEPTH_Msk (0x3ul << PSIO_GNCT_DATCTL_OUTDEPTH_Pos) /*!< PSIO_T::DATCTL: OUTDEPTH Mask */ 1370 1371 #define PSIO_GNCT_DATCTL_INDEPTH_Pos (28) /*!< PSIO_T::DATCTL: INDEPTH Position */ 1372 #define PSIO_GNCT_DATCTL_INDEPTH_Msk (0x3ul << PSIO_GNCT_DATCTL_INDEPTH_Pos) /*!< PSIO_T::DATCTL: INDEPTH Mask */ 1373 1374 #define PSIO_GNCT_INSTS_INSTS_Pos (0) /*!< PSIO_T::INSTS: INSTS Position */ 1375 #define PSIO_GNCT_INSTS_INSTS_Msk (0xfful << PSIO_GNCT_INSTS_INSTS_Pos) /*!< PSIO_T::INSTS: INSTS Mask */ 1376 1377 #define PSIO_GNCT_INDAT_INDAT_Pos (0) /*!< PSIO_T::INDAT: INDAT Position */ 1378 #define PSIO_GNCT_INDAT_INDAT_Msk (0xfffffffful << PSIO_GNCT_INDAT_INDAT_Pos) /*!< PSIO_T::INDAT: INDAT Mask */ 1379 1380 #define PSIO_GNCT_OUTDAT_OUTDAT_Pos (0) /*!< PSIO_T::OUTDAT: OUTDAT Position */ 1381 #define PSIO_GNCT_OUTDAT_OUTDAT_Msk (0xfffffffful << PSIO_GNCT_OUTDAT_OUTDAT_Pos) /*!< PSIO_T::OUTDAT: OUTDAT Mask */ 1382 1383 #define PSIO_GNCT_CPCTL0_CKPT0_Pos (0) /*!< PSIO_T::CPCTL0: CKPT0 Position */ 1384 #define PSIO_GNCT_CPCTL0_CKPT0_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT0_Pos) /*!< PSIO_T::CPCTL0: CKPT0 Mask */ 1385 1386 #define PSIO_GNCT_CPCTL0_CKPT1_Pos (4) /*!< PSIO_T::CPCTL0: CKPT1 Position */ 1387 #define PSIO_GNCT_CPCTL0_CKPT1_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT1_Pos) /*!< PSIO_T::CPCTL0: CKPT1 Mask */ 1388 1389 #define PSIO_GNCT_CPCTL0_CKPT2_Pos (8) /*!< PSIO_T::CPCTL0: CKPT2 Position */ 1390 #define PSIO_GNCT_CPCTL0_CKPT2_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT2_Pos) /*!< PSIO_T::CPCTL0: CKPT2 Mask */ 1391 1392 #define PSIO_GNCT_CPCTL0_CKPT3_Pos (12) /*!< PSIO_T::CPCTL0: CKPT3 Position */ 1393 #define PSIO_GNCT_CPCTL0_CKPT3_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT3_Pos) /*!< PSIO_T::CPCTL0: CKPT3 Mask */ 1394 1395 #define PSIO_GNCT_CPCTL0_CKPT4_Pos (16) /*!< PSIO_T::CPCTL0: CKPT4 Position */ 1396 #define PSIO_GNCT_CPCTL0_CKPT4_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT4_Pos) /*!< PSIO_T::CPCTL0: CKPT4 Mask */ 1397 1398 #define PSIO_GNCT_CPCTL0_CKPT5_Pos (20) /*!< PSIO_T::CPCTL0: CKPT5 Position */ 1399 #define PSIO_GNCT_CPCTL0_CKPT5_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT5_Pos) /*!< PSIO_T::CPCTL0: CKPT5 Mask */ 1400 1401 #define PSIO_GNCT_CPCTL0_CKPT6_Pos (24) /*!< PSIO_T::CPCTL0: CKPT6 Position */ 1402 #define PSIO_GNCT_CPCTL0_CKPT6_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT6_Pos) /*!< PSIO_T::CPCTL0: CKPT6 Mask */ 1403 1404 #define PSIO_GNCT_CPCTL0_CKPT7_Pos (28) /*!< PSIO_T::CPCTL0: CKPT7 Position */ 1405 #define PSIO_GNCT_CPCTL0_CKPT7_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT7_Pos) /*!< PSIO_T::CPCTL0: CKPT7 Mask */ 1406 1407 #define PSIO_GNCT_CPCTL1_CKPT0ACT_Pos (0) /*!< PSIO_T::CPCTL1: CKPT0ACT Position */ 1408 #define PSIO_GNCT_CPCTL1_CKPT0ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT0ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT0ACT Mask */ 1409 1410 #define PSIO_GNCT_CPCTL1_CKPT1ACT_Pos (4) /*!< PSIO_T::CPCTL1: CKPT1ACT Position */ 1411 #define PSIO_GNCT_CPCTL1_CKPT1ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT1ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT1ACT Mask */ 1412 1413 #define PSIO_GNCT_CPCTL1_CKPT2ACT_Pos (8) /*!< PSIO_T::CPCTL1: CKPT2ACT Position */ 1414 #define PSIO_GNCT_CPCTL1_CKPT2ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT2ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT2ACT Mask */ 1415 1416 #define PSIO_GNCT_CPCTL1_CKPT3ACT_Pos (12) /*!< PSIO_T::CPCTL1: CKPT3ACT Position */ 1417 #define PSIO_GNCT_CPCTL1_CKPT3ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT3ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT3ACT Mask */ 1418 1419 #define PSIO_GNCT_CPCTL1_CKPT4ACT_Pos (16) /*!< PSIO_T::CPCTL1: CKPT4ACT Position */ 1420 #define PSIO_GNCT_CPCTL1_CKPT4ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT4ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT4ACT Mask */ 1421 1422 #define PSIO_GNCT_CPCTL1_CKPT5ACT_Pos (20) /*!< PSIO_T::CPCTL1: CKPT5ACT Position */ 1423 #define PSIO_GNCT_CPCTL1_CKPT5ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT5ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT5ACT Mask */ 1424 1425 #define PSIO_GNCT_CPCTL1_CKPT6ACT_Pos (24) /*!< PSIO_T::CPCTL1: CKPT6ACT Position */ 1426 #define PSIO_GNCT_CPCTL1_CKPT6ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT6ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT6ACT Mask */ 1427 1428 #define PSIO_GNCT_CPCTL1_CKPT7ACT_Pos (28) /*!< PSIO_T::CPCTL1: CKPT7ACT Position */ 1429 #define PSIO_GNCT_CPCTL1_CKPT7ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT7ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT7ACT Mask */ 1430 1431 /**@}*/ /* PSIO_CONST */ 1432 /**@}*/ /* end of PSIO register group */ 1433 /**@}*/ /* end of REGISTER group */ 1434 1435 #if defined ( __CC_ARM ) 1436 #pragma no_anon_unions 1437 #endif 1438 1439 #endif /* __PSIO_REG_H__ */ 1440
