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Searched refs:OTG (Results 1 – 11 of 11) sorted by relevance

/hal_nuvoton-3.7.0/m46x/StdDriver/inc/
Dotg.h61 #define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
70 #define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
80 #define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
89 #define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
98 #define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
107 #define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
116 #define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
125 #define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
136 #define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u3…
147 #define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((…
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/hal_nuvoton-3.7.0/m48x/StdDriver/inc/
Dotg.h61 #define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
70 #define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
80 #define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
89 #define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
98 #define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
107 #define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
116 #define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
125 #define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
136 #define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u3…
147 #define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((…
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/hal_nuvoton-3.7.0/m2l31x/StdDriver/inc/
Dotg.h61 #define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
70 #define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
80 #define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
89 #define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
98 #define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
107 #define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
116 #define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
125 #define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
136 #define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u3…
147 #define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((…
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/hal_nuvoton-3.7.0/m46x/StdDriver/src/
Dusbd.c464 OTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk); in USBD_StandardRequest()
/hal_nuvoton-3.7.0/m48x/StdDriver/src/
Dusbd.c466 OTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk); in USBD_StandardRequest()
/hal_nuvoton-3.7.0/m2l31x/StdDriver/src/
Dusbd.c473 OTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk); in USBD_StandardRequest()
/hal_nuvoton-3.7.0/m48x/Devices/M480/Include/
DM480.h408 #define OTG ((OTG_T *) OTG_BASE) macro
/hal_nuvoton-3.7.0/m2l31x/Devices/M2L31/Include/
DM2L31.h495 #define OTG ((OTG_T *) OTG_BASE) macro
/hal_nuvoton-3.7.0/m46x/Devices/M460/Include/
Dm460.h490 #define OTG ((OTG_T *) OTG_BASE) macro
/hal_nuvoton-3.7.0/m48x/Devices/M480/Source/IAR/
Dstartup_M480.s104 DCD USBOTG_IRQHandler ; 55: USB OTG
/hal_nuvoton-3.7.0/m48x/Devices/M480/Source/ARM/
Dstartup_M480.s125 DCD USBOTG_IRQHandler ; 55: USB OTG