1 /**************************************************************************//** 2 * @file m460.h 3 * @version V3.00 4 * @brief M460 peripheral access layer header file. 5 * This file contains all the peripheral register's definitions, 6 * bits definitions and memory mapping for NuMicro M460 MCU. 7 * 8 * @copyright SPDX-License-Identifier: Apache-2.0 9 * @copyright (C) 2022 Nuvoton Technology Corp. All rights reserved. 10 *****************************************************************************/ 11 /** 12 \mainpage NuMicro M460 Driver Reference Guide 13 * 14 * <b>Introduction</b> 15 * 16 * This user manual describes the usage of M460 Series MCU device driver 17 * 18 * <b>Disclaimer</b> 19 * 20 * The Software is furnished "AS IS", without warranty as to performance or results, and 21 * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all 22 * warranties, express, implied or otherwise, with regard to the Software, its use, or 23 * operation, including without limitation any and all warranties of merchantability, fitness 24 * for a particular purpose, and non-infringement of intellectual property rights. 25 * 26 * <b>Important Notice</b> 27 * 28 * Nuvoton Products are neither intended nor warranted for usage in systems or equipment, 29 * any malfunction or failure of which may cause loss of human life, bodily injury or severe 30 * property damage. Such applications are deemed, "Insecure Usage". 31 * 32 * Insecure usage includes, but is not limited to: equipment for surgical implementation, 33 * atomic energy control instruments, airplane or spaceship instruments, the control or 34 * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal 35 * instruments, all types of safety devices, and other applications intended to support or 36 * sustain life. 37 * 38 * All Insecure Usage shall be made at customer's risk, and in the event that third parties 39 * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify 40 * the damages and liabilities thus incurred by Nuvoton. 41 * 42 * Please note that all data and specifications are subject to change without notice. All the 43 * trademarks of products and companies mentioned in this datasheet belong to their respective 44 * owners. 45 * 46 * <b>Copyright Notice</b> 47 * 48 * Copyright (C) 2022~2023 Nuvoton Technology Corp. All rights reserved. 49 */ 50 #ifndef __M460_H__ 51 #define __M460_H__ 52 53 #ifdef __cplusplus 54 extern "C" { 55 #endif 56 57 /******************************************************************************/ 58 /* Processor and Core Peripherals */ 59 /******************************************************************************/ 60 /** @addtogroup CMSIS_Device Device CMSIS Definitions 61 Configuration of the Cortex-M4 Processor and Core Peripherals 62 @{ 63 */ 64 65 /** 66 * @details Interrupt Number Definition. 67 */ 68 typedef enum IRQn 69 { 70 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ 71 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 72 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ 73 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ 74 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ 75 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ 76 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ 77 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ 78 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ 79 80 /****** M460 Specific Interrupt Numbers ********************************************************/ 81 82 BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ 83 IRC_IRQn = 1, /*!< Internal RC Interrupt */ 84 PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ 85 RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ 86 CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ 87 ISP_IRQn = 5, /*!< FMC ISP Interrupt */ 88 RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ 89 TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */ 90 WDT_IRQn = 8, /*!< Watchdog timer Interrupt */ 91 WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */ 92 EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ 93 EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ 94 EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ 95 EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ 96 EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ 97 EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ 98 GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ 99 GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ 100 GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ 101 GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ 102 GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ 103 GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ 104 QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ 105 SPI0_IRQn = 23, /*!< SPI0 Interrupt */ 106 BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ 107 EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ 108 EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ 109 EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ 110 BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ 111 EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ 112 EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ 113 EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ 114 TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ 115 TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ 116 TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ 117 TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ 118 UART0_IRQn = 36, /*!< UART 0 Interrupt */ 119 UART1_IRQn = 37, /*!< UART 1 Interrupt */ 120 I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ 121 I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ 122 PDMA0_IRQn = 40, /*!< Peripheral DMA 0 Interrupt */ 123 DAC_IRQn = 41, /*!< DAC Interrupt */ 124 EADC00_IRQn = 42, /*!< EADC00 Interrupt */ 125 EADC01_IRQn = 43, /*!< EADC01 Interrupt */ 126 ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ 127 ACMP23_IRQn = 45, /*!< Analog Comparator 2 and 3 Interrupt */ 128 EADC02_IRQn = 46, /*!< EADC02 Interrupt */ 129 EADC03_IRQn = 47, /*!< EADC03 Interrupt */ 130 UART2_IRQn = 48, /*!< UART2 Interrupt */ 131 UART3_IRQn = 49, /*!< UART3 Interrupt */ 132 QSPI1_IRQn = 50, /*!< QSPI1 Interrupt */ 133 SPI1_IRQn = 51, /*!< SPI1 Interrupt */ 134 SPI2_IRQn = 52, /*!< SPI2 Interrupt */ 135 USBD_IRQn = 53, /*!< USB device Interrupt */ 136 USBH_IRQn = 54, /*!< USB host Interrupt */ 137 USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ 138 BMC_IRQn = 56, /*!< BMC Interrupt */ 139 SPI5_IRQn = 57, /*!< SPI5 Interrupt */ 140 SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ 141 SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ 142 SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ 143 GPJ_IRQn = 61, /*!< GPIO Port J Interrupt */ 144 SPI3_IRQn = 62, /*!< SPI3 Interrupt */ 145 SPI4_IRQn = 63, /*!< SPI4 Interrupt */ 146 EMAC0_TXRX_IRQn = 66, /*!< Ethernet MAC 0 Interrupt */ 147 SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */ 148 USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */ 149 I2S0_IRQn = 68, /*!< I2S0 Interrupt */ 150 I2S1_IRQn = 69, /*!< I2S1 Interrupt */ 151 SPI6_IRQn = 70, /*!< SPI6 Interrupt */ 152 CRPT_IRQn = 71, /*!< CRPT Interrupt */ 153 GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ 154 EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ 155 UART4_IRQn = 74, /*!< UART4 Interrupt */ 156 UART5_IRQn = 75, /*!< UART5 Interrupt */ 157 USCI0_IRQn = 76, /*!< USCI0 Interrupt */ 158 SPI7_IRQn = 77, /*!< SPI7 Interrupt */ 159 BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ 160 BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ 161 SPIM_IRQn = 80, /*!< SPIM Interrupt */ 162 CCAP_IRQn = 81, /*!< CCAP Interrupt */ 163 I2C2_IRQn = 82, /*!< I2C2 Interrupt */ 164 I2C3_IRQn = 83, /*!< I2C3 Interrupt */ 165 EQEI0_IRQn = 84, /*!< EQEI0 Interrupt */ 166 EQEI1_IRQn = 85, /*!< EQEI1 Interrupt */ 167 ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ 168 ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ 169 GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ 170 EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ 171 SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */ 172 PSIO_IRQn = 91, /*!< PSIO Interrupt */ 173 HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */ 174 USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */ 175 ECAP2_IRQn = 94, /*!< ECAP2 Interrupt */ 176 ECAP3_IRQn = 95, /*!< ECAP3 Interrupt */ 177 KPI_IRQn = 96, /*!< Keypad Interface Interrupt */ 178 HBI_IRQn = 97, /*!< HBI Interrupt */ 179 PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */ 180 UART8_IRQn = 99, /*!< UART8 Interrupt */ 181 UART9_IRQn = 100, /*!< UART9 Interrupt */ 182 TRNG_IRQn = 101, /*!< TRNG Interrupt */ 183 UART6_IRQn = 102, /*!< UART6 Interrupt */ 184 UART7_IRQn = 103, /*!< UART7 Interrupt */ 185 EADC10_IRQn = 104, /*!< EADC10 Interrupt */ 186 EADC11_IRQn = 105, /*!< EADC11 Interrupt */ 187 EADC12_IRQn = 106, /*!< EADC12 Interrupt */ 188 EADC13_IRQn = 107, /*!< EADC13 Interrupt */ 189 SPI8_IRQn = 108, /*!< SPI8 Interrupt */ 190 KS_IRQn = 109, /*!< Keystore Interrupt */ 191 GPI_IRQn = 110, /*!< GPIO Port I Interrupt */ 192 SPI9_IRQn = 111, /*!< SPI9 Interrupt */ 193 CANFD00_IRQn = 112, /*!< CANFD00 Interrupt */ 194 CANFD01_IRQn = 113, /*!< CANFD01 Interrupt */ 195 CANFD10_IRQn = 114, /*!< CANFD10 Interrupt */ 196 CANFD11_IRQn = 115, /*!< CANFD11 Interrupt */ 197 EQEI2_IRQn = 116, /*!< EQEI2 Interrupt */ 198 EQEI3_IRQn = 117, /*!< EQEI3 Interrupt */ 199 I2C4_IRQn = 118, /*!< I2C4 Interrupt */ 200 SPI10_IRQn = 119, /*!< SPI10 Interrupt */ 201 CANFD20_IRQn = 120, /*!< CANFD20 Interrupt */ 202 CANFD21_IRQn = 121, /*!< CANFD21 Interrupt */ 203 CANFD30_IRQn = 122, /*!< CANFD30 Interrupt */ 204 CANFD31_IRQn = 123, /*!< CANFD31 Interrupt */ 205 EADC20_IRQn = 124, /*!< EADC20 Interrupt */ 206 EADC21_IRQn = 125, /*!< EADC21 Interrupt */ 207 EADC22_IRQn = 126, /*!< EADC22 Interrupt */ 208 EADC23_IRQn = 127, /*!< EADC23 Interrupt */ 209 } 210 IRQn_Type; 211 212 213 /* 214 * ========================================================================== 215 * ----------- Processor and Core Peripheral Section ------------------------ 216 * ========================================================================== 217 */ 218 219 /* Configuration of the Cortex-M4 Processor and Core Peripherals */ 220 #define __CM4_REV 0x0201UL /*!< Core Revision r2p1 */ 221 #define __NVIC_PRIO_BITS 4UL /*!< Number of Bits used for Priority Levels */ 222 #define __Vendor_SysTickConfig 0UL /*!< Set to 1 if different SysTick Config is used */ 223 #define __MPU_PRESENT 1UL /*!< MPU present or not */ 224 #ifdef __FPU_PRESENT 225 #undef __FPU_PRESENT 226 #define __FPU_PRESENT 1UL /*!< FPU present or not */ 227 #else 228 #define __FPU_PRESENT 1UL /*!< FPU present or not */ 229 #endif 230 231 /*@}*/ /* end of group CMSIS_Device */ 232 233 234 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 235 #include "system_m460.h" /* System include file */ 236 #include <stdint.h> 237 238 239 240 #if defined ( __CC_ARM ) 241 #pragma anon_unions 242 #endif 243 244 /******************************************************************************/ 245 /* Register definitions */ 246 /******************************************************************************/ 247 248 #include "sys_reg.h" 249 #include "clk_reg.h" 250 #include "fmc_reg.h" 251 #include "gpio_reg.h" 252 #include "pdma_reg.h" 253 #include "timer_reg.h" 254 #include "wdt_reg.h" 255 #include "wwdt_reg.h" 256 #include "rtc_reg.h" 257 #include "epwm_reg.h" 258 #include "bpwm_reg.h" 259 #include "eqei_reg.h" 260 #include "ecap_reg.h" 261 #include "uart_reg.h" 262 #include "emac_reg.h" 263 #include "sc_reg.h" 264 #include "i2s_reg.h" 265 #include "spi_reg.h" 266 #include "qspi_reg.h" 267 #include "spim_reg.h" 268 #include "i2c_reg.h" 269 #include "uuart_reg.h" 270 #include "uspi_reg.h" 271 #include "ui2c_reg.h" 272 #include "canfd_reg.h" 273 #include "sdh_reg.h" 274 #include "ebi_reg.h" 275 #include "usbd_reg.h" 276 #include "hsusbd_reg.h" 277 #include "usbh_reg.h" 278 #include "hsusbh_reg.h" 279 #include "otg_reg.h" 280 #include "hsotg_reg.h" 281 #include "crc_reg.h" 282 #include "crypto_reg.h" 283 #include "trng_reg.h" 284 #include "eadc_reg.h" 285 #include "dac_reg.h" 286 #include "acmp_reg.h" 287 #include "ccap_reg.h" 288 #include "keystore_reg.h" 289 #include "kpi_reg.h" 290 #include "psio_reg.h" 291 #include "hbi_reg.h" 292 #include "bmc_reg.h" 293 294 /** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base 295 Memory Mapped Structure for Peripherals 296 @{ 297 */ 298 /* Peripheral and SRAM base address */ 299 #define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */ 300 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */ 301 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */ 302 303 #define TCM_BASE (PERIPH_BASE + 0xBE000) 304 305 /*!< AHB peripherals */ 306 //HCLK 307 // CPU,CRC,EBI,EMC,FMC,PDMA,SD0,SD1,CRPT,SPIM,SRAM,HSUSBD, HSUSBH, USBH 308 #define SYS_BASE (PERIPH_BASE + 0x00000UL) 309 #define CLK_BASE (PERIPH_BASE + 0x00200UL) 310 #define NMI_BASE (PERIPH_BASE + 0x00300UL) 311 #define GPIOA_BASE (PERIPH_BASE + 0x04000UL) 312 #define GPIOB_BASE (PERIPH_BASE + 0x04040UL) 313 #define GPIOC_BASE (PERIPH_BASE + 0x04080UL) 314 #define GPIOD_BASE (PERIPH_BASE + 0x040C0UL) 315 #define GPIOE_BASE (PERIPH_BASE + 0x04100UL) 316 #define GPIOF_BASE (PERIPH_BASE + 0x04140UL) 317 #define GPIOG_BASE (PERIPH_BASE + 0x04180UL) 318 #define GPIOH_BASE (PERIPH_BASE + 0x041C0UL) 319 #define GPIOI_BASE (PERIPH_BASE + 0x04200UL) 320 #define GPIOJ_BASE (PERIPH_BASE + 0x04240UL) 321 #define GPIO_INT_BASE (PERIPH_BASE + 0x04450UL) 322 #define GPIO_PIN_DATA_BASE (PERIPH_BASE + 0x04800UL) 323 #define SPIM_BASE (PERIPH_BASE + 0x07000UL) 324 #define PDMA0_BASE (PERIPH_BASE + 0x08000UL) 325 #define PDMA1_BASE (PERIPH_BASE + 0x18000UL) 326 #define USBH_BASE (PERIPH_BASE + 0x09000UL) 327 #define HSUSBH_BASE (PERIPH_BASE + 0x1A000UL) 328 #define EMAC_BASE (PERIPH_BASE + 0x12000UL) 329 #define FMC_BASE (PERIPH_BASE + 0x0C000UL) 330 #define SDH0_BASE (PERIPH_BASE + 0x0D000UL) 331 #define SDH1_BASE (PERIPH_BASE + 0x0E000UL) 332 #define EBI_BASE (PERIPH_BASE + 0x10000UL) 333 #define HSUSBD_BASE (PERIPH_BASE + 0x19000UL) 334 #define CCAP_BASE (PERIPH_BASE + 0x30000UL) 335 #define CRC_BASE (PERIPH_BASE + 0x31000UL) 336 #define CRPT_BASE (PERIPH_BASE + 0x32000UL) 337 #define KS_BASE (PERIPH_BASE + 0x35000UL) 338 #define TAMPER_BASE (PERIPH_BASE + 0xE1000UL) 339 #define HBI_BASE (PERIPH_BASE + 0xCE000UL) 340 #define BMC_BASE (PERIPH_BASE + 0x1B000UL) 341 342 //PCLK0 343 // BPWM0,QSPI0,ECAP2,I2C0/2/4,I2S0,OPA,EPWM0,EQEI0/2,SC0/2,SPI1/3/5/7/9,TMR01,UR0/2/4/6/8,USBD,USCI0,WDT 344 345 /*!< APB0 peripherals */ 346 #define WDT_BASE (PERIPH_BASE + 0x40000UL) 347 #define WWDT_BASE (PERIPH_BASE + 0x40100UL) 348 #define OPA_BASE (PERIPH_BASE + 0x46000UL) 349 #define I2S0_BASE (PERIPH_BASE + 0x48000UL) 350 #define EADC1_BASE (PERIPH_BASE + 0x4B000UL) 351 #define TIMER0_BASE (PERIPH_BASE + 0x50000UL) 352 #define TIMER1_BASE (PERIPH_BASE + 0x50100UL) 353 #define EPWM0_BASE (PERIPH_BASE + 0x58000UL) 354 #define BPWM0_BASE (PERIPH_BASE + 0x5A000UL) 355 #define QSPI0_BASE (PERIPH_BASE + 0x60000UL) 356 #define SPI1_BASE (PERIPH_BASE + 0x62000UL) 357 #define SPI3_BASE (PERIPH_BASE + 0x64000UL) 358 #define SPI5_BASE (PERIPH_BASE + 0x66000UL) 359 #define SPI7_BASE (PERIPH_BASE + 0x68000UL) 360 #define SPI9_BASE (PERIPH_BASE + 0x6C000UL) 361 #define UART0_BASE (PERIPH_BASE + 0x70000UL) 362 #define UART2_BASE (PERIPH_BASE + 0x72000UL) 363 #define UART4_BASE (PERIPH_BASE + 0x74000UL) 364 #define UART6_BASE (PERIPH_BASE + 0x76000UL) 365 #define UART8_BASE (PERIPH_BASE + 0x78000UL) 366 #define I2C0_BASE (PERIPH_BASE + 0x80000UL) 367 #define I2C2_BASE (PERIPH_BASE + 0x82000UL) 368 #define CANFD0_BASE (PERIPH_BASE + 0x20000UL) 369 #define CANFD2_BASE (PERIPH_BASE + 0x28000UL) 370 #define EQEI0_BASE (PERIPH_BASE + 0xB0000UL) 371 #define ECAP0_BASE (PERIPH_BASE + 0xB4000UL) 372 #define USCI0_BASE (PERIPH_BASE + 0xD0000UL) 373 374 375 376 //PCLK1 377 // ACMP01/23,EADC0/1/2,BPWM1,DAC,ECAP1/3,I2C1/3,I2S1,OTG,HSOTG,EPWM1,QEI1/3,RTC,SC1,SPI0/2/4/6/8/10,QSPI1,TMR23,UR1/3/5/7/9,PSIO 378 379 /*!< APB1 peripherals */ 380 #define RTC_BASE (PERIPH_BASE + 0x41000UL) 381 #define EADC0_BASE (PERIPH_BASE + 0x43000UL) 382 #define ACMP01_BASE (PERIPH_BASE + 0x45000UL) 383 #define I2S1_BASE (PERIPH_BASE + 0x49000UL) 384 #define USBD_BASE (PERIPH_BASE + 0xC0000UL) 385 #define EADC1_BASE (PERIPH_BASE + 0x4B000UL) 386 #define OTG_BASE (PERIPH_BASE + 0x4D000UL) 387 #define HSOTG_BASE (PERIPH_BASE + 0x4F000UL) 388 #define TIMER2_BASE (PERIPH_BASE + 0x51000UL) 389 #define TIMER3_BASE (PERIPH_BASE + 0x51100UL) 390 #define EADC2_BASE (PERIPH_BASE + 0x97000UL) 391 #define EPWM1_BASE (PERIPH_BASE + 0x59000UL) 392 #define BPWM1_BASE (PERIPH_BASE + 0x5B000UL) 393 #define SPI0_BASE (PERIPH_BASE + 0x61000UL) 394 #define SPI2_BASE (PERIPH_BASE + 0x63000UL) 395 #define SPI4_BASE (PERIPH_BASE + 0x65000UL) 396 #define SPI6_BASE (PERIPH_BASE + 0x67000UL) 397 #define QSPI1_BASE (PERIPH_BASE + 0x69000UL) 398 #define SPI8_BASE (PERIPH_BASE + 0x6B000UL) 399 #define SPI10_BASE (PERIPH_BASE + 0x6D000UL) 400 #define UART1_BASE (PERIPH_BASE + 0x71000UL) 401 #define UART3_BASE (PERIPH_BASE + 0x73000UL) 402 #define UART5_BASE (PERIPH_BASE + 0x75000UL) 403 #define UART7_BASE (PERIPH_BASE + 0x77000UL) 404 #define UART9_BASE (PERIPH_BASE + 0x79000UL) 405 #define I2C1_BASE (PERIPH_BASE + 0x81000UL) 406 #define CANFD1_BASE (PERIPH_BASE + 0x24000UL) 407 #define CANFD3_BASE (PERIPH_BASE + 0x2C000UL) 408 #define EQEI1_BASE (PERIPH_BASE + 0xB1000UL) 409 #define ECAP1_BASE (PERIPH_BASE + 0xB5000UL) 410 #define TRNG_BASE (PERIPH_BASE + 0xB9000UL) 411 #define ECAP2_BASE (PERIPH_BASE + 0xB6000UL) 412 #define ECAP3_BASE (PERIPH_BASE + 0xB7000UL) 413 #define EQEI2_BASE (PERIPH_BASE + 0xB2000UL) 414 #define EQEI3_BASE (PERIPH_BASE + 0xB3000UL) 415 #define I2C3_BASE (PERIPH_BASE + 0x83000UL) 416 #define I2C4_BASE (PERIPH_BASE + 0x84000UL) 417 #define SC0_BASE (PERIPH_BASE + 0x90000UL) 418 #define SC1_BASE (PERIPH_BASE + 0x91000UL) 419 #define SC2_BASE (PERIPH_BASE + 0x92000UL) 420 #define DAC0_BASE (PERIPH_BASE + 0x47000UL) 421 #define DAC1_BASE (PERIPH_BASE + 0x47040UL) 422 #define DACDBG_BASE (PERIPH_BASE + 0x47FECUL) 423 #define OPA0_BASE (PERIPH_BASE + 0x46000UL) 424 425 #define KPI_BASE (PERIPH_BASE + 0x0C2000UL) 426 #define PSIO_BASE (PERIPH_BASE + 0x0C3000UL) 427 #define ACMP23_BASE (PERIPH_BASE + 0x0C9000UL) 428 429 430 431 /*@}*/ /* end of group PERIPHERAL_MEM_MAP */ 432 433 434 /** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer 435 The Declaration of Peripherals 436 @{ 437 */ 438 439 #define TCM ((TCM_T *) TCM_BASE) 440 #define SYS ((SYS_T *) SYS_BASE) 441 #define CLK ((CLK_T *) CLK_BASE) 442 #define NMI ((NMI_T *) NMI_BASE) 443 #define PA ((GPIO_T *) GPIOA_BASE) 444 #define PB ((GPIO_T *) GPIOB_BASE) 445 #define PC ((GPIO_T *) GPIOC_BASE) 446 #define PD ((GPIO_T *) GPIOD_BASE) 447 #define PE ((GPIO_T *) GPIOE_BASE) 448 #define PF ((GPIO_T *) GPIOF_BASE) 449 #define PG ((GPIO_T *) GPIOG_BASE) 450 #define PH ((GPIO_T *) GPIOH_BASE) 451 #define PI ((GPIO_T *) GPIOI_BASE) 452 #define PJ ((GPIO_T *) GPIOJ_BASE) 453 #define GPA ((GPIO_T *) GPIOA_BASE) 454 #define GPB ((GPIO_T *) GPIOB_BASE) 455 #define GPC ((GPIO_T *) GPIOC_BASE) 456 #define GPD ((GPIO_T *) GPIOD_BASE) 457 #define GPE ((GPIO_T *) GPIOE_BASE) 458 #define GPF ((GPIO_T *) GPIOF_BASE) 459 #define GPG ((GPIO_T *) GPIOG_BASE) 460 #define GPH ((GPIO_T *) GPIOH_BASE) 461 #define GPI ((GPIO_T *) GPIOI_BASE) 462 #define GPJ ((GPIO_T *) GPIOJ_BASE) 463 #define GPIO ((GPIO_INT_T *) GPIO_INT_BASE) 464 #define PDMA0 ((PDMA_T *) PDMA0_BASE) 465 #define PDMA1 ((PDMA_T *) PDMA1_BASE) 466 #define USBH ((USBH_T *) USBH_BASE) 467 #define HSUSBH ((HSUSBH_T *) HSUSBH_BASE) 468 #define EMAC ((EMAC_T *) EMAC_BASE) 469 #define FMC ((FMC_T *) FMC_BASE) 470 #define SDH0 ((SDH_T *) SDH0_BASE) 471 #define SDH1 ((SDH_T *) SDH1_BASE) 472 #define EBI ((EBI_T *) EBI_BASE) 473 #define CRC ((CRC_T *) CRC_BASE) 474 #define TAMPER ((TAMPER_T *) TAMPER_BASE) 475 #define KS ((KS_T *) KS_BASE) 476 #define HBI ((HBI_T *) HBI_BASE) 477 #define WDT ((WDT_T *) WDT_BASE) 478 #define WWDT ((WWDT_T *) WWDT_BASE) 479 #define RTC ((RTC_T *) RTC_BASE) 480 #define EADC0 ((EADC_T *) EADC0_BASE) 481 #define EADC1 ((EADC_T *) EADC1_BASE) 482 #define EADC2 ((EADC_T *) EADC2_BASE) 483 #define ACMP01 ((ACMP_T *) ACMP01_BASE) 484 #define ACMP23 ((ACMP_T *) ACMP23_BASE) 485 #define KPI ((KPI_T *) KPI_BASE) 486 487 #define I2S0 ((I2S_T *) I2S0_BASE) 488 #define I2S1 ((I2S_T *) I2S1_BASE) 489 #define USBD ((USBD_T *) USBD_BASE) 490 #define OTG ((OTG_T *) OTG_BASE) 491 #define HSUSBD ((HSUSBD_T *)HSUSBD_BASE) 492 #define HSOTG ((HSOTG_T *) HSOTG_BASE) 493 #define TIMER0 ((TIMER_T *) TIMER0_BASE) 494 #define TIMER1 ((TIMER_T *) TIMER1_BASE) 495 #define TIMER2 ((TIMER_T *) TIMER2_BASE) 496 #define TIMER3 ((TIMER_T *) TIMER3_BASE) 497 #define EPWM0 ((EPWM_T *) EPWM0_BASE) 498 #define EPWM1 ((EPWM_T *) EPWM1_BASE) 499 #define BPWM0 ((BPWM_T *) BPWM0_BASE) 500 #define BPWM1 ((BPWM_T *) BPWM1_BASE) 501 #define ECAP0 ((ECAP_T *) ECAP0_BASE) 502 #define ECAP1 ((ECAP_T *) ECAP1_BASE) 503 #define ECAP2 ((ECAP_T *) ECAP2_BASE) 504 #define ECAP3 ((ECAP_T *) ECAP3_BASE) 505 #define EQEI0 ((EQEI_T *) EQEI0_BASE) 506 #define EQEI1 ((EQEI_T *) EQEI1_BASE) 507 #define EQEI2 ((EQEI_T *) EQEI2_BASE) 508 #define EQEI3 ((EQEI_T *) EQEI3_BASE) 509 #define QSPI0 ((QSPI_T *) QSPI0_BASE) 510 #define QSPI1 ((QSPI_T *) QSPI1_BASE) 511 #define SPI0 ((SPI_T *) SPI0_BASE) 512 #define SPI1 ((SPI_T *) SPI1_BASE) 513 #define SPI2 ((SPI_T *) SPI2_BASE) 514 #define SPI3 ((SPI_T *) SPI3_BASE) 515 #define SPI4 ((SPI_T *) SPI4_BASE) 516 #define SPI5 ((SPI_T *) SPI5_BASE) 517 #define SPI6 ((SPI_T *) SPI6_BASE) 518 #define SPI7 ((SPI_T *) SPI7_BASE) 519 #define SPI8 ((SPI_T *) SPI8_BASE) 520 #define SPI9 ((SPI_T *) SPI9_BASE) 521 #define SPI10 ((SPI_T *) SPI10_BASE) 522 #define UART0 ((UART_T *) UART0_BASE) 523 #define UART1 ((UART_T *) UART1_BASE) 524 #define UART2 ((UART_T *) UART2_BASE) 525 #define UART3 ((UART_T *) UART3_BASE) 526 #define UART4 ((UART_T *) UART4_BASE) 527 #define UART5 ((UART_T *) UART5_BASE) 528 #define UART6 ((UART_T *) UART6_BASE) 529 #define UART7 ((UART_T *) UART7_BASE) 530 #define UART8 ((UART_T *) UART8_BASE) 531 #define UART9 ((UART_T *) UART9_BASE) 532 #define I2C0 ((I2C_T *) I2C0_BASE) 533 #define I2C1 ((I2C_T *) I2C1_BASE) 534 #define I2C2 ((I2C_T *) I2C2_BASE) 535 #define I2C3 ((I2C_T *) I2C3_BASE) 536 #define I2C4 ((I2C_T *) I2C4_BASE) 537 #define SC0 ((SC_T *) SC0_BASE) 538 #define SC1 ((SC_T *) SC1_BASE) 539 #define SC2 ((SC_T *) SC2_BASE) 540 #define CANFD0 ((CANFD_T *) CANFD0_BASE) 541 #define CANFD1 ((CANFD_T *) CANFD1_BASE) 542 #define CANFD2 ((CANFD_T *) CANFD2_BASE) 543 #define CANFD3 ((CANFD_T *) CANFD3_BASE) 544 #define CRPT ((CRPT_T *) CRPT_BASE) 545 #define TRNG ((TRNG_T *) TRNG_BASE) 546 #define SPIM ((volatile SPIM_T *) SPIM_BASE) 547 #define DAC0 ((DAC_T *) DAC0_BASE) 548 #define DAC1 ((DAC_T *) DAC1_BASE) 549 #define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */ 550 #define OPA ((OPA_T *) OPA_BASE) 551 #define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */ 552 #define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */ 553 #define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */ 554 #define CCAP ((CCAP_T *) CCAP_BASE) 555 #define PSIO ((PSIO_T *) PSIO_BASE) 556 #define BMC ((BMC_T *) BMC_BASE) 557 558 /*@}*/ /* end of group ERIPHERAL_DECLARATION */ 559 560 /** @addtogroup IO_ROUTINE I/O Routines 561 The Declaration of I/O Routines 562 @{ 563 */ 564 565 typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type 566 typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type 567 typedef volatile unsigned int vu32; ///< Define 32-bit unsigned volatile data type 568 569 /** 570 * @brief Get a 8-bit unsigned value from specified address 571 * @param[in] addr Address to get 8-bit data from 572 * @return 8-bit unsigned value stored in specified address 573 */ 574 #define M8(addr) (*((vu8 *) (addr))) 575 576 /** 577 * @brief Get a 16-bit unsigned value from specified address 578 * @param[in] addr Address to get 16-bit data from 579 * @return 16-bit unsigned value stored in specified address 580 * @note The input address must be 16-bit aligned 581 */ 582 #define M16(addr) (*((vu16 *) (addr))) 583 584 /** 585 * @brief Get a 32-bit unsigned value from specified address 586 * @param[in] addr Address to get 32-bit data from 587 * @return 32-bit unsigned value stored in specified address 588 * @note The input address must be 32-bit aligned 589 */ 590 #define M32(addr) (*((vu32 *) (addr))) 591 592 /** 593 * @brief Set a 32-bit unsigned value to specified I/O port 594 * @param[in] port Port address to set 32-bit data 595 * @param[in] value Value to write to I/O port 596 * @return None 597 * @note The output port must be 32-bit aligned 598 */ 599 #define outpw(port,value) *((volatile unsigned int *)(port)) = (value) 600 601 /** 602 * @brief Get a 32-bit unsigned value from specified I/O port 603 * @param[in] port Port address to get 32-bit data from 604 * @return 32-bit unsigned value stored in specified I/O port 605 * @note The input port must be 32-bit aligned 606 */ 607 #define inpw(port) (*((volatile unsigned int *)(port))) 608 609 /** 610 * @brief Set a 16-bit unsigned value to specified I/O port 611 * @param[in] port Port address to set 16-bit data 612 * @param[in] value Value to write to I/O port 613 * @return None 614 * @note The output port must be 16-bit aligned 615 */ 616 #define outps(port,value) *((volatile unsigned short *)(port)) = (value) 617 618 /** 619 * @brief Get a 16-bit unsigned value from specified I/O port 620 * @param[in] port Port address to get 16-bit data from 621 * @return 16-bit unsigned value stored in specified I/O port 622 * @note The input port must be 16-bit aligned 623 */ 624 #define inps(port) (*((volatile unsigned short *)(port))) 625 626 /** 627 * @brief Set a 8-bit unsigned value to specified I/O port 628 * @param[in] port Port address to set 8-bit data 629 * @param[in] value Value to write to I/O port 630 * @return None 631 */ 632 #define outpb(port,value) *((volatile unsigned char *)(port)) = (value) 633 634 /** 635 * @brief Get a 8-bit unsigned value from specified I/O port 636 * @param[in] port Port address to get 8-bit data from 637 * @return 8-bit unsigned value stored in specified I/O port 638 */ 639 #define inpb(port) (*((volatile unsigned char *)(port))) 640 641 /** 642 * @brief Set a 32-bit unsigned value to specified I/O port 643 * @param[in] port Port address to set 32-bit data 644 * @param[in] value Value to write to I/O port 645 * @return None 646 * @note The output port must be 32-bit aligned 647 */ 648 #define outp32(port,value) *((volatile unsigned int *)(port)) = (value) 649 650 /** 651 * @brief Get a 32-bit unsigned value from specified I/O port 652 * @param[in] port Port address to get 32-bit data from 653 * @return 32-bit unsigned value stored in specified I/O port 654 * @note The input port must be 32-bit aligned 655 */ 656 #define inp32(port) (*((volatile unsigned int *)(port))) 657 658 /** 659 * @brief Set a 16-bit unsigned value to specified I/O port 660 * @param[in] port Port address to set 16-bit data 661 * @param[in] value Value to write to I/O port 662 * @return None 663 * @note The output port must be 16-bit aligned 664 */ 665 #define outp16(port,value) *((volatile unsigned short *)(port)) = (value) 666 667 /** 668 * @brief Get a 16-bit unsigned value from specified I/O port 669 * @param[in] port Port address to get 16-bit data from 670 * @return 16-bit unsigned value stored in specified I/O port 671 * @note The input port must be 16-bit aligned 672 */ 673 #define inp16(port) (*((volatile unsigned short *)(port))) 674 675 /** 676 * @brief Set a 8-bit unsigned value to specified I/O port 677 * @param[in] port Port address to set 8-bit data 678 * @param[in] value Value to write to I/O port 679 * @return None 680 */ 681 #define outp8(port,value) *((volatile unsigned char *)(port)) = (value) 682 683 /** 684 * @brief Get a 8-bit unsigned value from specified I/O port 685 * @param[in] port Port address to get 8-bit data from 686 * @return 8-bit unsigned value stored in specified I/O port 687 */ 688 #define inp8(port) (*((volatile unsigned char *)(port))) 689 690 691 /*@}*/ /* end of group IO_ROUTINE */ 692 693 /******************************************************************************/ 694 /* Legacy Constants */ 695 /******************************************************************************/ 696 /** @addtogroup Legacy_Constants Legacy Constants 697 Legacy Constants 698 @{ 699 */ 700 701 #ifndef NULL 702 #define NULL (0) ///< NULL pointer 703 #endif 704 705 /** 706 * Avoid redefined warning in the integration with RTOS, so change to enum{ FALSE, TRUE } 707 * #define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value 708 * #define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value 709 */ 710 #ifndef TRUE 711 enum { FALSE, TRUE }; 712 #endif 713 714 #define ENABLE (1UL) ///< Enable, define to use in API parameters 715 #define DISABLE (0UL) ///< Disable, define to use in API parameters 716 717 /* Define one bit mask */ 718 #define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer 719 #define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer 720 #define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer 721 #define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer 722 #define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer 723 #define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer 724 #define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer 725 #define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer 726 #define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer 727 #define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer 728 #define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer 729 #define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer 730 #define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer 731 #define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer 732 #define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer 733 #define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer 734 #define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer 735 #define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer 736 #define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer 737 #define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer 738 #define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer 739 #define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer 740 #define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer 741 #define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer 742 #define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer 743 #define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer 744 #define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer 745 #define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer 746 #define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer 747 #define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer 748 #define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer 749 #define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer 750 751 /* Byte Mask Definitions */ 752 #define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer 753 #define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer 754 #define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer 755 #define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer 756 757 #define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ 758 #define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ 759 #define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ 760 #define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ 761 762 /*@}*/ /* end of group Legacy_Constants */ 763 764 765 /******************************************************************************/ 766 /* Peripheral header files */ 767 /******************************************************************************/ 768 #include "sys.h" 769 #include "clk.h" 770 771 #include "kpi.h" 772 #include "rng.h" 773 #include "keystore.h" 774 #include "acmp.h" 775 #include "dac.h" 776 #include "uart.h" 777 #include "usci_spi.h" 778 #include "gpio.h" 779 #include "ccap.h" 780 #include "ecap.h" 781 #include "hbi.h" 782 #include "eqei.h" 783 #include "timer.h" 784 #include "timer_pwm.h" 785 #include "pdma.h" 786 #include "crypto.h" 787 #include "trng.h" 788 #include "fmc.h" 789 #include "spim.h" 790 #include "i2c.h" 791 #include "i2s.h" 792 #include "epwm.h" 793 #include "eadc.h" 794 #include "bpwm.h" 795 #include "wdt.h" 796 #include "wwdt.h" 797 #include "crc.h" 798 #include "ebi.h" 799 #include "usci_i2c.h" 800 #include "scuart.h" 801 #include "sc.h" 802 #include "spi.h" 803 #include "qspi.h" 804 #include "canfd.h" 805 #include "rtc.h" 806 #include "usci_uart.h" 807 #include "sdh.h" 808 #include "usbd.h" 809 #include "hsusbd.h" 810 #include "otg.h" 811 #include "hsotg.h" 812 #include "psio.h" 813 #include "bmc.h" 814 815 816 #ifdef __cplusplus 817 } 818 #endif 819 820 #endif /* __M460_H__ */ 821 822
