Searched refs:CLK_PLLCTL2_OUTDIV_Pos (Results 1 – 3 of 3) sorted by relevance
343 #define CLK_PLLCTL_NO_1 (0x0UL << CLK_PLLCTL2_OUTDIV_Pos) /*!< For output divider is 1 \h…344 #define CLK_PLLCTL_NO_2 (0x1UL << CLK_PLLCTL2_OUTDIV_Pos) /*!< For output divider is 2 \h…345 #define CLK_PLLCTL_NO_4 (0x3UL << CLK_PLLCTL2_OUTDIV_Pos) /*!< For output divider is 4 \h…
1089 CLK->PLLCTL2 = (u32Outdiv << CLK_PLLCTL2_OUTDIV_Pos) | in CLK_EnablePLL()1383 u32NO = au8NoTbl[((u32Pll2Reg & CLK_PLLCTL2_OUTDIV_Msk) >> CLK_PLLCTL2_OUTDIV_Pos)]; in CLK_GetPLLClockFreq()
1906 #define CLK_PLLCTL2_OUTDIV_Pos (14) /*!< CLK… macro1907 #define CLK_PLLCTL2_OUTDIV_Msk (0x3ul << CLK_PLLCTL2_OUTDIV_Pos) /*!< CLK…
