1 /**************************************************************************//** 2 * @file clk_reg.h 3 * @version V1.00 4 * @brief CLK register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CLK_REG_H__ 10 #define __CLK_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup CLK System Clock Controller (CLK) 23 Memory Mapped Structure for CLK Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var CLK_T::PWRCTL 32 * Offset: 0x00 System Power-down Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |HXTEN |HXT Enable Bit (Write Protect) 37 * | | |0 = 4~32 MHz external high speed crystal (HXT) Disabled. 38 * | | |1 = 4~32 MHz external high speed crystal (HXT) Enabled. 39 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 40 * | | |Note 2: When HXT is enabled, PF.2(XT1_OUT) and PF.3(XT1_IN) must be set as input mode. 41 * |[1] |LXTEN |LXT Enable Bit (Write Protect) 42 * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled. 43 * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled. 44 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 45 * | | |Note 2: When LXT is enabled, PF.4(X32_OUT) and PF.5(X32_IN) must be set as input mode. 46 * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) 47 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. 48 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. 49 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 50 * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) 51 * | | |0 = 32 kHz internal low speed RC oscillator (LIRC) Disabled. 52 * | | |1 = 32 kHz internal low speed RC oscillator (LIRC) Enabled. 53 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 54 * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) 55 * | | |0 = Power-down mode wake-up interrupt Disabled. 56 * | | |1 = Power-down mode wake-up interrupt Enabled. 57 * | | |Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high. 58 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 59 * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status 60 * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. 61 * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. 62 * | | |Note 1: Write 1 to clear the bit to 0. 63 * | | |Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 64 * |[7] |PDEN |System Power-down Enable (Write Protect) 65 * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. 66 * | | |When chip wakes up from Power-down mode, this bit is auto cleared 67 * | | |Users need to set this bit again for next Power-down. 68 * | | |In Power-down mode, HXT, HIRC and the HIRC48M will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. 69 * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection 70 * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. 71 * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI. 72 * | | |1 = Chip enters Power-down mode after CPU sleep command WFI. 73 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 74 * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) 75 * | | |0 = Select INV type. 76 * | | |1 = Select GM type. 77 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 78 * |[15:14] |HIRC48MSTBS|HIRC48M Stable Count Select (Write Protect ) 79 * | | |00 = HIRC48M stable count is 1024 clocks. 80 * | | |01 = HIRC48M stable count is 512 clocks. 81 * | | |Others = Reserved. 82 * | | |Note: Thes bits are write protected. Refer to the SYS_REGLCTL register. 83 * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect ) 84 * | | |00 = HIRC stable count is 64 clocks. 85 * | | |01 = HIRC stable count is 24 clocks. 86 * | | |Others = Reserved. 87 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 88 * |[18] |HIRC48MEN |HIRC48M Enable Bit (Write Protect) 89 * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48M) Disabled. 90 * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48M) Enabled. 91 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 92 * |[22:20] |HXTGAIN |HXT Gain Control Bit (Write Protect) 93 * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally 94 * | | |If gain control is enabled, crystal will consume more power than gain control off. 95 * | | |000 = HXT frequency is from 1 MHz to 4 MHz. 96 * | | |001 = HXT frequency is from 8 MHz to 12 MHz. 97 * | | |010 = HXT frequency is from 12 MHz to 16 MHz. 98 * | | |011 = HXT frequency is from 16 MHz to 24 MHz. 99 * | | |100 = HXT frequency is from 24 MHz to 32 MHz. 100 * | | |101 = Reserved. 101 * | | |110 = Reserved. 102 * | | |111 = Reserved. 103 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 104 * |[25:24] |MIRCSTBS |MIRC Stable Count Select (Write Protect ) 105 * | | |00 = MIRC stable count is 128 clocks. 106 * | | |01 = MIRC stable count is 32 clocks. 107 * | | |Others = Reserved. 108 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 109 * |[26] |MIRCEN |MIRC Enable Bit (Write Protect) 110 * | | |0 = 1/2/4/8 MHz internal multiple speed RC oscillator (MIRC) Disabled. 111 * | | |1 = 1/2/4/8 MHz internal multiple speed RC oscillator (MIRC) Enabled. 112 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 113 * |[30:28] |MIRCFSEL |MIRC Frequency Select Bits (Write Protect) 114 * | | |000 = Internal middle speed RC oscillator frerquency is 1 MHz. 115 * | | |001 = Internal middle speed RC oscillator frerquency is 2 MHz. 116 * | | |010 = Internal middle speed RC oscillator frerquency is 4 MHz. 117 * | | |011 = Internal middle speed RC oscillator frerquency is 8 MHz. 118 * | | |Others = Reserved. 119 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 120 * |[31] |HXTMD |HXT Bypass Mode (Write Protect) 121 * | | |0 = HXT work as crystal mode. PF.2 and PF.3 are configured as external high speed crystal (HXT) pins. 122 * | | |1 = HXT works as external clock mode. PF.3 is configured as external clock input pin. 123 * | | |Note 1: When HXTMD = 1, PF.3 MFP should be set as GPIO mode 124 * | | |The DC characteristic of XT1_IN is the same as GPIO. 125 * | | |Note 2: This bit is write protected. Refer to the SYS_REGCTL register. 126 * @var CLK_T::AHBCLK0 127 * Offset: 0x04 AHB Devices Clock Enable Control Register 0 128 * --------------------------------------------------------------------------------------------------- 129 * |Bits |Field |Descriptions 130 * | :----: | :----: | :---- | 131 * |[1] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit 132 * | | |0 = PDMA0 peripheral clock Disabled. 133 * | | |1 = PDMA0 peripheral clock Enabled. 134 * |[2] |ISPCKEN |RRAM ISP Controller Clock Enable Bit 135 * | | |0 = RRAM ISP peripheral clock Disabled. 136 * | | |1 = RRAM ISP peripheral clock Enabled. 137 * |[3] |EBICKEN |EBI Controller Clock Enable Bit 138 * | | |0 = EBI peripheral clock Disabled. 139 * | | |1 = EBI peripheral clock Enabled. 140 * |[4] |STCKEN |System Tick Clock Enable Bit 141 * | | |0 = System tick clock Disabled. 142 * | | |1 = System tick clock Enabled. 143 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit 144 * | | |0 = CRC peripheral clock Disabled. 145 * | | |1 = CRC peripheral clock Enabled. 146 * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit 147 * | | |0 = Cryptographic Accelerator clock Disabled. 148 * | | |1 = Cryptographic Accelerator clock Enabled. 149 * |[13] |KSCKEN |Key Store Clock Enable Bit 150 * | | |0 = Key Store clock Disabled. 151 * | | |1 = Key Store clock Enabled. 152 * |[15] |RMCIDLE |RRAM Memory Controller Clock Enable Bit in IDLE Mode 153 * | | |0 = RMC clock Disabled when chip is under IDLE mode. 154 * | | |1 = RMC clock Enabled when chip is under IDLE mode. 155 * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit 156 * | | |0 = USB HOST peripheral clock Disabled. 157 * | | |1 = USB HOST peripheral clock Enabled. 158 * |[23] |RMCFDIS |RMC Clock Force Disable Bit 159 * | | |0 = RMC clock Enabled. 160 * | | |1 = RMC clock force Disable to save power. 161 * | | |Note: User should make sure program no RRAM access during this bit is 1 162 * |[24] |GPACKEN |GPIOA Clock Enable Bit 163 * | | |0 = GPIOA port clock Disabled. 164 * | | |1 = GPIOA port clock Enabled. 165 * |[25] |GPBCKEN |GPIOB Clock Enable Bit 166 * | | |0 = GPIOB port clock Disabled. 167 * | | |1 = GPIOB port clock Enabled. 168 * |[26] |GPCCKEN |GPIOC Clock Enable Bit 169 * | | |0 = GPIOC port clock Disabled. 170 * | | |1 = GPIOC port clock Enabled. 171 * |[27] |GPDCKEN |GPIOD Clock Enable Bit 172 * | | |0 = GPIOD port clock Disabled. 173 * | | |1 = GPIOD port clock Enabled. 174 * |[28] |GPECKEN |GPIOE Clock Enable Bit 175 * | | |0 = GPIOE port clock Disabled. 176 * | | |1 = GPIOE port clock Enabled. 177 * |[29] |GPFCKEN |GPIOF Clock Enable Bit 178 * | | |0 = GPIOF port clock Disabled. 179 * | | |1 = GPIOF port clock Enabled. 180 * |[30] |GPGCKEN |GPIOG Clock Enable Bit 181 * | | |0 = GPIOG port clock Disabled. 182 * | | |1 = GPIOG port clock Enabled. 183 * |[31] |GPHCKEN |GPIOH Clock Enable Bit 184 * | | |0 = GPIOH port clock Disabled. 185 * | | |1 = GPIOH port clock Enabled. 186 * @var CLK_T::APBCLK0 187 * Offset: 0x08 APB Devices Clock Enable Control Register 0 188 * --------------------------------------------------------------------------------------------------- 189 * |Bits |Field |Descriptions 190 * | :----: | :----: | :---- | 191 * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit 192 * | | |This bit is used to control the RTC APB clock only. 193 * | | |The RTC peripheral clock source is selected from RTCCKSEL (RTC_LXTCTL[7]) 194 * | | |It can be selected to external low speed crystal oscillator (LXT) or internal low speed RC oscillator (LIRC). 195 * | | |0 = RTC clock Disabled. 196 * | | |1 = RTC clock Enabled. 197 * |[2] |TMR0CKEN |Timer0 Clock Enable Bit 198 * | | |0 = Timer0 clock Disabled. 199 * | | |1 = Timer0 clock Enabled. 200 * |[3] |TMR1CKEN |Timer1 Clock Enable Bit 201 * | | |0 = Timer1 clock Disabled. 202 * | | |1 = Timer1 clock Enabled. 203 * |[4] |TMR2CKEN |Timer2 Clock Enable Bit 204 * | | |0 = Timer2 clock Disabled. 205 * | | |1 = Timer2 clock Enabled. 206 * |[5] |TMR3CKEN |Timer3 Clock Enable Bit 207 * | | |0 = Timer3 clock Disabled. 208 * | | |1 = Timer3 clock Enabled. 209 * |[6] |CLKOCKEN |CLKO Clock Enable Bit 210 * | | |0 = CLKO clock Disabled. 211 * | | |1 = CLKO clock Enabled. 212 * |[7] |ACMP01CKEN|ACMP01 Clock Enable Bit 213 * | | |0 = ACMP01 clock Disabled. 214 * | | |1 = ACMP01 clock Enabled. 215 * |[8] |I2C0CKEN |I2C0 Clock Enable Bit 216 * | | |0 = I2C0 clock Disabled. 217 * | | |1 = I2C0 clock Enabled. 218 * |[9] |I2C1CKEN |I2C1 Clock Enable Bit 219 * | | |0 = I2C1 clock Disabled. 220 * | | |1 = I2C1 clock Enabled. 221 * |[10] |I2C2CKEN |I2C2 Clock Enable Bit 222 * | | |0 = I2C2 clock Disabled. 223 * | | |1 = I2C2 clock Enabled. 224 * |[11] |I2C3CKEN |I2C3 Clock Enable Bit 225 * | | |0 = I2C3 clock Disabled. 226 * | | |1 = I2C3 clock Enabled. 227 * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit 228 * | | |0 = QSPI0 clock Disabled. 229 * | | |1 = QSPI0 clock Enabled. 230 * |[13] |SPI0CKEN |SPI0 Clock Enable Bit 231 * | | |0 = SPI0 clock Disabled. 232 * | | |1 = SPI0 clock Enabled. 233 * |[14] |SPI1CKEN |SPI1 Clock Enable Bit 234 * | | |0 = SPI1 clock Disabled. 235 * | | |1 = SPI1 clock Enabled. 236 * |[15] |SPI2CKEN |SPI2 Clock Enable Bit 237 * | | |0 = SPI2 clock Disabled. 238 * | | |1 = SPI2 clock Enabled. 239 * |[16] |UART0CKEN |UART0 Clock Enable Bit 240 * | | |0 = UART0 clock Disabled. 241 * | | |1 = UART0 clock Enabled. 242 * |[17] |UART1CKEN |UART1 Clock Enable Bit 243 * | | |0 = UART1 clock Disabled. 244 * | | |1 = UART1 clock Enabled. 245 * |[18] |UART2CKEN |UART2 Clock Enable Bit 246 * | | |0 = UART2 clock Disabled. 247 * | | |1 = UART2 clock Enabled. 248 * |[19] |UART3CKEN |UART3 Clock Enable Bit 249 * | | |0 = UART3 clock Disabled. 250 * | | |1 = UART3 clock Enabled. 251 * |[20] |UART4CKEN |UART4 Clock Enable Bit 252 * | | |0 = UART4 clock Disabled. 253 * | | |1 = UART4 clock Enabled. 254 * |[21] |UART5CKEN |UART5 Clock Enable Bit 255 * | | |0 = UART5 clock Disabled. 256 * | | |1 = UART5 clock Enabled. 257 * |[22] |UART6CKEN |UART6 Clock Enable Bit 258 * | | |0 = UART6 clock Disabled. 259 * | | |1 = UART6 clock Enabled. 260 * |[23] |UART7CKEN |UART7 Clock Enable Bit 261 * | | |0 = UART7 clock Disabled. 262 * | | |1 = UART7 clock Enabled. 263 * |[26] |OTGCKEN |USB OTG Clock Enable Bit 264 * | | |0 = USB OTG clock Disabled. 265 * | | |1 = USB OTG clock Enabled. 266 * |[27] |USBDCKEN |USB Device Clock Enable Bit 267 * | | |0 = USB device clock Disabled. 268 * | | |1 = USB device clock Enabled. 269 * |[28] |EADC0CKEN |EADC0 Clock Enable Bit 270 * | | |0 = EADC0 clock Disabled. 271 * | | |1 = EADC0 clock Enabled. 272 * |[31] |TRNGCKEN |TRNG Clock Enable Bit 273 * | | |0 = TRNG clock Disabled. 274 * | | |1 = TRNG clock Enabled. 275 * @var CLK_T::APBCLK1 276 * Offset: 0x0C APB Devices Clock Enable Control Register 1 277 * --------------------------------------------------------------------------------------------------- 278 * |Bits |Field |Descriptions 279 * | :----: | :----: | :---- | 280 * |[6] |SPI3CKEN |SPI3 Clock Enable Bit 281 * | | |0 = SPI3 clock Disabled. 282 * | | |1 = SPI3 clock Enabled. 283 * |[8] |USCI0CKEN |USCI0 Clock Enable Bit 284 * | | |0 = USCI0 clock Disabled. 285 * | | |1 = USCI0 clock Enabled. 286 * |[9] |USCI1CKEN |USCI1 Clock Enable Bit 287 * | | |0 = USCI1 clock Disabled. 288 * | | |1 = USCI1 clock Enabled. 289 * |[11] |WWDTCKEN |Window Watchdog Timer Clock Enable Bit (Write Protect) 290 * | | |0 = Window Watchdog timer clock Disabled. 291 * | | |1 = Window Watchdog timer clock Enabled. 292 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 293 * |[12] |DACEN |DAC Clock Enable Bit 294 * | | |0 = DAC clock Disabled. 295 * | | |1 = DAC clock Enabled. 296 * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit 297 * | | |0 = EPWM0 clock Disabled. 298 * | | |1 = EPWM0 clock Enabled. 299 * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit 300 * | | |0 = EPWM1 clock Disabled. 301 * | | |1 = EPWM1 clock Enabled. 302 * |[22] |EQEI0CKEN |EQEI0 Clock Enable Bit 303 * | | |0 = EQEI0 clock Disabled. 304 * | | |1 = EQEI0 clock Enabled. 305 * |[23] |EQEI1CKEN |EQEI1 Clock Enable Bit 306 * | | |0 = EQEI1 clock Disabled. 307 * | | |1 = EQEI1 clock Enabled. 308 * |[25] |TKCKEN |TK Clock Enable Bit 309 * | | |0 = TK clock Disabled. 310 * | | |1 = TK clock Enabled. 311 * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit 312 * | | |0 = ECAP0 clock Disabled. 313 * | | |1 = ECAP0 clock Enabled. 314 * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit 315 * | | |0 = ECAP1 clock Disabled. 316 * | | |1 = ECAP1 clock Enabled. 317 * @var CLK_T::CLKSEL0 318 * Offset: 0x10 Clock Source Select Control Register 0 319 * --------------------------------------------------------------------------------------------------- 320 * |Bits |Field |Descriptions 321 * | :----: | :----: | :---- | 322 * |[2:0] |HCLK0SEL |HCLK0 Clock Source Selection (Write Protect) 323 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. 324 * | | |000 = Clock source from HXT. 325 * | | |001 = Clock source from LXT. 326 * | | |010 = Clock source from PLL. 327 * | | |011 = Clock source from LIRC. 328 * | | |101 = Clock source from MIRC. 329 * | | |110 = Clock source from HIRC48M. 330 * | | |111 = Clock source from HIRC. 331 * | | |Other = Reserved. 332 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 333 * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect) 334 * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. 335 * | | |000 = Clock source from HXT. 336 * | | |001 = Clock source from LXT. 337 * | | |010 = Clock source from HXT/2. 338 * | | |011 = Clock source from HCLK/2. 339 * | | |111 = Clock source from HIRC/2. 340 * | | |Others = Reserved. 341 * | | |Note: if SysTick clock source is not from CPU clock (i.e 342 * | | |SYST_CTRL[2] = 0), SysTick clock source must be less than or equal to CPU clock divided by 2. 343 * |[8] |USBSEL |USB Clock Source Selection (Write Protect) 344 * | | |0 = Clock source from HIRC48M. 345 * | | |1 = Clock source from PLL. 346 * |[11:10] |EADC0SEL |EADC0 Clock Source Selection (Write Protect) 347 * | | |01 = Clock source from PLL. 348 * | | |10 = Clock source from SRHCLK0. 349 * | | |11 = Clock source from HIRC. 350 * | | |Others = Reserved. 351 * |[14:12] |HCLK1SEL |HCLK1 Clock Source Selection (Write Protect) 352 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. 353 * | | |000 = Clock source from HIRC. 354 * | | |001 = Clock source from MIRC. 355 * | | |010 = Clock source from LXT. 356 * | | |011 = Clock source from LIRC. 357 * | | |100 = Clock source from HIRC48M_divider2. 358 * | | |Others = Reserved. 359 * | | |Note: HIRC48M_divider2 is not work at NPD3/NPD4/NPD5/SPD0~2/DPD0~1 power down mode, change to another clk source if needed. 360 * |[25:24] |CANFD0SEL |CANFD0 Clock Source Selection (Write Protect) 361 * | | |00 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 362 * | | |01 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 363 * | | |10 = Clock source from SRHCLK0. 364 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 365 * |[27:26] |CANFD1SEL |CANFD1 Clock Source Selection (Write Protect) 366 * | | |00 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 367 * | | |01 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 368 * | | |10 = Clock source from HCLK0. 369 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 370 * @var CLK_T::CLKSEL1 371 * Offset: 0x14 Clock Source Select Control Register 1 372 * --------------------------------------------------------------------------------------------------- 373 * |Bits |Field |Descriptions 374 * | :----: | :----: | :---- | 375 * |[7:4] |CLKOSEL |Clock Divider Clock Source Selection 376 * | | |0000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 377 * | | |0001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 378 * | | |0010 = Clock source from HCLK0. 379 * | | |0011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 380 * | | |0100 = Clock source from 32 kHz internal high speed RC oscillator (LIRC). 381 * | | |0101 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M).. 382 * | | |0110 = Clock source from PLL. 383 * | | |0111 = Clock source from 1/2/4/8 MHz internal miltiple speed RC oscillator (MIRC). 384 * | | |others = Reserved. 385 * | | |Note: CLKOSEL can only be changed under CLKOCKEN = 0. 386 * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection 387 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 388 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 389 * | | |010 = Clock source from PCLK0. 390 * | | |011 = Clock source from external clock TM0 pin. 391 * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 392 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 393 * | | |Others = Reserved. 394 * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection 395 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 396 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 397 * | | |010 = Clock source from PCLK0. 398 * | | |011 = Clock source from external clock TM1 pin. 399 * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 400 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 401 * | | |Others = Reserved. 402 * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection 403 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 404 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 405 * | | |010 = Clock source from PCLK1. 406 * | | |011 = Clock source from external clock TM2 pin. 407 * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 408 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 409 * | | |Others = Reserved. 410 * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection 411 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 412 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 413 * | | |010 = Clock source from PCLK1. 414 * | | |011 = Clock source from external clock TM3 pin. 415 * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 416 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 417 * | | |Others = Reserved. 418 * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection 419 * | | |10 = Clock source from HCLK/2048. 420 * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 421 * | | |Others = Reserved. 422 * @var CLK_T::CLKSEL2 423 * Offset: 0x18 Clock Source Select Control Register 2 424 * --------------------------------------------------------------------------------------------------- 425 * |Bits |Field |Descriptions 426 * | :----: | :----: | :---- | 427 * |[0] |EPWM0SEL |EPWM0 Clock Source Selection 428 * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. 429 * | | |0 = Clock source from SRHCLK0. 430 * | | |1 = Clock source from PCLK0. 431 * |[1] |EPWM1SEL |EPWM1 Clock Source Selection 432 * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. 433 * | | |0 = Clock source from SRHCLK0. 434 * | | |1 = Clock source from PCLK1. 435 * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection 436 * | | |00 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 437 * | | |01 = Clock source from PLL. 438 * | | |10 = Clock source from PCLK0. 439 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 440 * |[6:4] |SPI0SEL |SPI0 Clock Source Selection 441 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 442 * | | |001 = Clock source from PLL. 443 * | | |010 = Clock source from PCLK1. 444 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 445 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 446 * | | |Others = Reserved. 447 * |[7] |TKSEL |TK Clock Source Selection 448 * | | |00 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 449 * | | |01 = Clock source from 1/2/4/8 MHz internal middle speed RC oscillator (MIRC). 450 * | | |Note: The TKSEL cannot be changed when TK is operating 451 * | | |Used should make TK disable before change TKSEL, and reset TK after change TKSEL. 452 * |[14:12] |SPI1SEL |SPI1 Clock Source Selection 453 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 454 * | | |001 = Clock source from PLL. 455 * | | |010 = Clock source from PCLK0. 456 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 457 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 458 * | | |Others = Reserved. 459 * @var CLK_T::CLKSEL3 460 * Offset: 0x1C Clock Source Select Control Register 3 461 * --------------------------------------------------------------------------------------------------- 462 * |Bits |Field |Descriptions 463 * | :----: | :----: | :---- | 464 * |[6] |PWM0SEL |PWM0 Clock Source Selection 465 * | | |The peripheral clock source of PWM0 is defined by PWM0SEL. 466 * | | |0 = Clock source from SRHCLK0. 467 * | | |1 = Clock source from PCLK0. 468 * |[7] |PWM1SEL |PWM1 Clock Source Selection 469 * | | |The peripheral clock source of PWM1 is defined by PWM1SEL. 470 * | | |0 = Clock source from SRHCLK0. 471 * | | |1 = Clock source from PCLK1. 472 * |[10:8] |SPI2SEL |SPI2 Clock Source Selection 473 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 474 * | | |001 = Clock source from PLL. 475 * | | |010 = Clock source from PCLK1. 476 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 477 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 478 * | | |Others = Reserved. 479 * |[14:12] |SPI3SEL |SPI3 Clock Source Selection 480 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 481 * | | |001 = Clock source from PLL. 482 * | | |010 = Clock source from PCLK0. 483 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 484 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 485 * | | |Others = Reserved. 486 * @var CLK_T::CLKDIV0 487 * Offset: 0x20 Clock Divider Number Register 0 488 * --------------------------------------------------------------------------------------------------- 489 * |Bits |Field |Descriptions 490 * | :----: | :----: | :---- | 491 * |[3:0] |HCLK0DIV |HCLK0 Clock Divide Number from HCLK0 Clock Source 492 * | | |HCLK0 clock frequency = (HCLK0 clock source frequency) / (HCLK0DIV + 1). 493 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 494 * |[7:4] |USBDIV |USB Clock Divide Number from USB Clock 495 * | | |USB clock frequency = (USB clock source frequency) / (USBDIV + 1). 496 * |[11:8] |UART0DIV |UART0 Clock Divide Number from UART0 Clock Source 497 * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). 498 * |[15:12] |UART1DIV |UART1 Clock Divide Number from UART1 Clock Source 499 * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). 500 * |[23:16] |EADC0DIV |EADC0 Clock Divide Number from EADC0 Clock Source 501 * | | |EADC0 clock frequency = (EADC0 clock source frequency) / (EADC0DIV + 1). 502 * @var CLK_T::CLKDIV4 503 * Offset: 0x30 Clock Divider Number Register 4 504 * --------------------------------------------------------------------------------------------------- 505 * |Bits |Field |Descriptions 506 * | :----: | :----: | :---- | 507 * |[3:0] |UART2DIV |UART2 Clock Divide Number from UART2 Clock Source 508 * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). 509 * |[7:4] |UART3DIV |UART3 Clock Divide Number from UART3 Clock Source 510 * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). 511 * |[11:8] |UART4DIV |UART4 Clock Divide Number from UART4 Clock Source 512 * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). 513 * |[15:12] |UART5DIV |UART5 Clock Divide Number from UART5 Clock Source 514 * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). 515 * |[19:16] |UART6DIV |UART6 Clock Divide Number from UART6 Clock Source 516 * | | |UART6 clock frequency = (UART6 clock source frequency) / (UART6DIV + 1). 517 * |[23:20] |UART7DIV |UART7 Clock Divide Number from UART7 Clock Source 518 * | | |UART7 clock frequency = (UART7 clock source frequency) / (UART7DIV + 1). 519 * @var CLK_T::PCLKDIV 520 * Offset: 0x34 APB Clock Divider Register 521 * --------------------------------------------------------------------------------------------------- 522 * |Bits |Field |Descriptions 523 * | :----: | :----: | :---- | 524 * |[2:0] |APB0DIV |APB0 Clock Divider 525 * | | |APB0 clock can be divided from HCLK0. 526 * | | |000 = PCLK0 frequency is HCLK0. 527 * | | |001= PCLK0 frequency is 1/2 HCLK0. 528 * | | |010 = PCLK0 frequency is 1/4 HCLK0. 529 * | | |011 = PCLK0 frequency is 1/8 HCLK0. 530 * | | |100 = PCLK0 frequency is 1/16 HCLK0. 531 * | | |Others = Reserved. 532 * |[6:4] |APB1DIV |APB1 Clock Divider 533 * | | |APB1 clock can be divided from HCLK0. 534 * | | |000 = PCLK1 frequency is HCLK0. 535 * | | |001 = PCLK1 frequency is 1/2 HCLK0. 536 * | | |010 = PCLK1 frequency is 1/4 HCLK0. 537 * | | |011 = PCLK1 frequency is 1/8 HCLK0. 538 * | | |100 = PCLK1 frequency is 1/16 HCLK0. 539 * | | |Others = Reserved. 540 * @var CLK_T::APBCLK2 541 * Offset: 0x38 APB Devices Clock Enable Control Register 2 542 * --------------------------------------------------------------------------------------------------- 543 * |Bits |Field |Descriptions 544 * | :----: | :----: | :---- | 545 * |[7] |ACMP2CKEN |ACMP2 Clock Enable Bit 546 * | | |0 = ACMP2 clock Disabled. 547 * | | |1 = ACMP2 clock Enabled. 548 * |[8] |PWM0CKEN |PWM0 Clock Enable Bit 549 * | | |0 = PWM0 clock Disabled. 550 * | | |1 = PWM0 clock Enabled. 551 * |[9] |PWM1CKEN |PWM1 Clock Enable Bit 552 * | | |0 = PWM1 clock Disabled. 553 * | | |1 = PWM1 clock Enabled. 554 * |[15] |UTCPD0CKEN|UTCPD0 Clock Enable Bit 555 * | | |0 = UTCPD0 clock Disabled. 556 * | | |1 = UTCPD0 clock Enabled. 557 * @var CLK_T::CLKDIV5 558 * Offset: 0x3C Clock Divider Number Register 5 559 * --------------------------------------------------------------------------------------------------- 560 * |Bits |Field |Descriptions 561 * | :----: | :----: | :---- | 562 * |[3:0] |CANFD0DIV |CANFD0 Clock Divide Number from CANFD0 Clock Source 563 * | | |CANFD0 clock frequency = (CANFD0 clock source frequency) / (CANFD0DIV + 1). 564 * |[7:4] |CANFD1DIV |CANFD1 Clock Divide Number from CANFD1 Clock Source 565 * | | |CANFD1 clock frequency = (CANFD1 clock source frequency) / (CANFD1DIV + 1). 566 * @var CLK_T::PLLCTL 567 * Offset: 0x40 PLL Control Register 568 * --------------------------------------------------------------------------------------------------- 569 * |Bits |Field |Descriptions 570 * | :----: | :----: | :---- | 571 * |[16] |PD |Power-down Mode (Write Protect) 572 * | | |0 = PLL is in normal mode. 573 * | | |1 = PLL is in Power-down mode (default). 574 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 575 * |[17] |BP |PLL Bypass Control (Write Protect) 576 * | | |0 = PLL is in normal mode (default). 577 * | | |1 = PLL clock output is same as PLL input clock FIN. 578 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 579 * |[18] |OE |PLL FOUT Enable Control (Write Protect) 580 * | | |0 = PLL FOUT Enabled. 581 * | | |1 = PLL FOUT is fixed low. 582 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 583 * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) 584 * | | |0 = PLL source clock from 4~32 MHz external high-speed crystal oscillator (HXT). 585 * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). 586 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 587 * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) 588 * | | |0 = PLL stable time is 2500 PLL source clock (suitable for source clock is equal to or less than 12 MHz). 589 * | | |1 = PLL stable time is 7000 PLL source clock (suitable for source clock is larger than 12 MHz). 590 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 591 * @var CLK_T::PLLCTL2 592 * Offset: 0x44 PLL Control Register 2 593 * --------------------------------------------------------------------------------------------------- 594 * |Bits |Field |Descriptions 595 * | :----: | :----: | :---- | 596 * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) 597 * | | |Refer to the formulas below the table. 598 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 599 * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) 600 * | | |Refer to the formulas below the table. 601 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 602 * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) 603 * | | |Refer to the formulas below the table. 604 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 605 * |[27:16] |FRDIV |PLL Fractional Divider Control (Write Protect) 606 * | | |Refer to the formulas below the table. 607 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 608 * @var CLK_T::CLKSEL4 609 * Offset: 0x48 Clock Source Select Control Register 4 610 * --------------------------------------------------------------------------------------------------- 611 * |Bits |Field |Descriptions 612 * | :----: | :----: | :---- | 613 * |[2:0] |UART0SEL |UART0 Clock Source Selection 614 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 615 * | | |001 = Clock source from PLL. 616 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 617 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 618 * | | |100 = Clock source from 1/2/4/8 MHz internal middle speed RC oscillator (MIRC). 619 * | | |101 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 620 * | | |Others = Reserved. 621 * |[6:4] |UART1SEL |UART1 Clock Source Selection 622 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 623 * | | |001 = Clock source from PLL. 624 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 625 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 626 * | | |100 = Clock source from 1/2/4/8 MHz internal middle speed RC oscillator (MIRC). 627 * | | |101 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 628 * | | |Others = Reserved. 629 * |[10:8] |UART2SEL |UART2 Clock Source Selection 630 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 631 * | | |001 = Clock source from PLL. 632 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 633 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 634 * | | |100 = Clock source from 1/2/4/8 MHz internal middle speed RC oscillator (MIRC). 635 * | | |101 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 636 * | | |Others = Reserved. 637 * |[14:12] |UART3SEL |UART3 Clock Source Selection 638 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 639 * | | |001 = Clock source from PLL. 640 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 641 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 642 * | | |100 = Clock source from 1/2/4/8 MHz internal middle speed RC oscillator (MIRC). 643 * | | |101 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 644 * | | |Others = Reserved. 645 * |[18:16] |UART4SEL |UART4 Clock Source Selection 646 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 647 * | | |001 = Clock source from PLL. 648 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 649 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 650 * | | |100 = Clock source from 1/2/4/8 MHz internal middle speed RC oscillator (MIRC). 651 * | | |101 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 652 * | | |Others = Reserved. 653 * |[22:20] |UART5SEL |UART5 Clock Source Selection 654 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 655 * | | |001 = Clock source from PLL. 656 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 657 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 658 * | | |100 = Clock source from 1/2/4/8 MHz internal middle speed RC oscillator (MIRC). 659 * | | |101 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 660 * | | |Others = Reserved. 661 * |[26:24] |UART6SEL |UART6 Clock Source Selection 662 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 663 * | | |001 = Clock source from PLL. 664 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 665 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 666 * | | |100 = Clock source from 1/2/4/8 MHz internal middle speed RC oscillator (MIRC). 667 * | | |101 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 668 * | | |Others = Reserved. 669 * |[30:28] |UART7SEL |UART7 Clock Source Selection 670 * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). 671 * | | |001 = Clock source from PLL. 672 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 673 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 674 * | | |100 = Clock source from 1/2/4/8 MHz internal middle speed RC oscillator (MIRC). 675 * | | |101 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 676 * | | |Others = Reserved. 677 * @var CLK_T::STATUS 678 * Offset: 0x50 Clock Status Monitor Register 679 * --------------------------------------------------------------------------------------------------- 680 * |Bits |Field |Descriptions 681 * | :----: | :----: | :---- | 682 * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) 683 * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. 684 * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. 685 * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) 686 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. 687 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. 688 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) 689 * | | |0 = Internal PLL clock is not stable or disabled. 690 * | | |1 = Internal PLL clock is stable and enabled. 691 * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) 692 * | | |0 = 32 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. 693 * | | |1 = 32 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. 694 * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) 695 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. 696 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. 697 * |[5] |MIRCSTB |MIRC Clock Source Stable Flag (Read Only) 698 * | | |0 = 1/2/4/8 MHz internal high speed RC oscillator (MIRC) clock is not stable or disabled. 699 * | | |1 = 1/2/4/8 MHz internal high speed RC oscillator (MIRC) clock is stable and enabled. 700 * |[6] |HIRC48MSTB|HIRC48M Clock Source Stable Flag (Read Only) 701 * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48M) clock is not stable or disabled. 702 * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48M) clock is stable and enabled. 703 * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) 704 * | | |This bit is updated when software switches system clock source 705 * | | |If switch target clock is stable, this bit will be set to 0 706 * | | |If switch target clock is not stable, this bit will be set to 1. 707 * | | |0 = Clock switching success. 708 * | | |1 = Clock switching failure. 709 * | | |Note: This bit is read only 710 * | | |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. 711 * @var CLK_T::AHBCLK1 712 * Offset: 0x58 AHB Devices Clock Enable Control Register 1 713 * --------------------------------------------------------------------------------------------------- 714 * |Bits |Field |Descriptions 715 * | :----: | :----: | :---- | 716 * |[16] |CANRAM0EN |CANFD0 Message SRAM Clock Enable Bit 717 * | | |0 = CANFD0 Message SRAM clock Disabled. 718 * | | |1 = CANFD0 Message SRAM clock Enabled. 719 * |[17] |CANRAM1EN |CANFD1 Message SRAM Clock Enable Bit 720 * | | |0 = CANFD1 Message SRAM clock Disabled. 721 * | | |1 = CANFD1 Message SRAM clock Enabled. 722 * |[20] |CANFD0CKEN|CANFD0 Clock Enable Bit 723 * | | |0 = CANFD0 clock Disabled. 724 * | | |1 = CANFD0 clock Enabled. 725 * |[21] |CANFD1CKEN|CANFD1 Clock Enable Bit 726 * | | |0 = CANFD1 clock Disabled. 727 * | | |1 = CANFD1 clock Enabled. 728 * |[28] |HCLK1EN |HCLK1 Clock Enable Bit 729 * | | |0 = HCLK1 clock Disabled. 730 * | | |1 = HCLK1 clock Enabled. 731 * @var CLK_T::CLKOCTL 732 * Offset: 0x60 Clock Output Control Register 733 * --------------------------------------------------------------------------------------------------- 734 * |Bits |Field |Descriptions 735 * | :----: | :----: | :---- | 736 * |[3:0] |FREQSEL |Clock Output Frequency Selection 737 * | | |The formula of output frequency is 738 * | | |Fout = Fin/2(N+1). 739 * | | |Fin is the input clock frequency. 740 * | | |Fout is the frequency of divider output clock. 741 * | | |N is the 4-bit value of FREQSEL[3:0]. 742 * |[4] |CLKOEN |Clock Output Enable Bit 743 * | | |0 = Clock Output function Disabled. 744 * | | |1 = Clock Output function Enabled. 745 * |[5] |DIV1EN |Clock Output Divide One Enable Bit 746 * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. 747 * | | |1 = Clock Output will output clock with source frequency. 748 * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit 749 * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. 750 * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. 751 * @var CLK_T::CLKDCTL 752 * Offset: 0x70 Clock Fail Detector Control Register 753 * --------------------------------------------------------------------------------------------------- 754 * |Bits |Field |Descriptions 755 * | :----: | :----: | :---- | 756 * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit 757 * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. 758 * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. 759 * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit 760 * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. 761 * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. 762 * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit 763 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. 764 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. 765 * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit 766 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. 767 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. 768 * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit 769 * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled. 770 * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled. 771 * | | |Note: HIRC must be enabled and stabled before enabling HXT clock frequency monitor. 772 * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit 773 * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled. 774 * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled. 775 * @var CLK_T::CLKDSTS 776 * Offset: 0x74 Clock Fail Detector Status Register 777 * --------------------------------------------------------------------------------------------------- 778 * |Bits |Field |Descriptions 779 * | :----: | :----: | :---- | 780 * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect) 781 * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock is normal. 782 * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock stops. 783 * | | |Note 1: Write 1 to clear the bit to 0. 784 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 785 * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect) 786 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. 787 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. 788 * | | |Note 1: Write 1 to clear the bit to 0. 789 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 790 * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag (Write Protect) 791 * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency is normal. 792 * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. 793 * | | |Note 1: Write 1 to clear the bit to 0. 794 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 795 * @var CLK_T::CDUPB 796 * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register 797 * --------------------------------------------------------------------------------------------------- 798 * |Bits |Field |Descriptions 799 * | :----: | :----: | :---- | 800 * |[10:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value 801 * | | |The bits define the maximum value of frequency range detector window. 802 * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag HXTFQIF(CLK_CLKDSTS[8]) will set to 1. 803 * @var CLK_T::CDLOWB 804 * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register 805 * --------------------------------------------------------------------------------------------------- 806 * |Bits |Field |Descriptions 807 * | :----: | :----: | :---- | 808 * |[10:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value 809 * | | |The bits define the minimum value of frequency range detector window. 810 * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag HXTFQIF(CLK_CLKDSTS[8]) will set to 1. 811 * @var CLK_T::STOPREQ 812 * Offset: 0x80 Clock Stop Request Register 813 * --------------------------------------------------------------------------------------------------- 814 * |Bits |Field |Descriptions 815 * | :----: | :----: | :---- | 816 * |[0] |CANFD0REQ |CANFD0 Clock Stop Request 817 * | | |Set this bit and check the CANFD0ACK(CLK_STOPACK[0]) =1, then CANFD0 engine clock stopped. 818 * | | |Set this bit = 0 when CANFD0 clock is not stopped by this bit (default). 819 * |[1] |CANFD1REQ |CANFD1 Clock Stop Request 820 * | | |Set this bit and check the CANFD1ACK(CLK_STOPACK[1]) =1, then CANFD1 engine clock stopped. 821 * | | |Set this bit = 0 when CANFD1 clock is not stopped by this bit (default). 822 * @var CLK_T::STOPACK 823 * Offset: 0x84 Clock Stop Acknowledge Register 824 * --------------------------------------------------------------------------------------------------- 825 * |Bits |Field |Descriptions 826 * | :----: | :----: | :---- | 827 * |[0] |CANFD0ACK |CANFD0 Clock Stop Acknowledge 828 * | | |When this bit =1, CANFD0 engine clock stopped by setting CANFD0REQ(CLK_STOPREQ[0]). 829 * |[1] |CANFD1ACK |CANFD1 Clock Stop Acknowledge 830 * | | |When this bit =1, CANFD1 engine clock stopped by setting CANFD1REQ(CLK_STOPREQ[1]). 831 * @var CLK_T::PMUCTL 832 * Offset: 0x90 Power Manager Control Register 833 * --------------------------------------------------------------------------------------------------- 834 * |Bits |Field |Descriptions 835 * | :----: | :----: | :---- | 836 * |[3:0] |PDMSEL |Power-down Mode Selection (Write Protect) 837 * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. 838 * | | |0000 = Normal Power-down mode 0 is selected (NPD0). 839 * | | |0001 = Normal Power-down mode 1 is selected (NPD1). 840 * | | |0010 = Normal Power-down mode 2 is selected (NPD2). 841 * | | |0011 = Normal Power-down mode 3 is selected (NPD3). 842 * | | |0100 = Normal Power-down mode 4 is selected (NPD4). 843 * | | |0101 = Normal Power-down mode 5 is selected (NPD5). 844 * | | |1000 = Standby Power-down mode 0 is selected (SPD0). 845 * | | |1001 = Standby Power-down mode 1 is selected (SPD1). 846 * | | |1010 = Standby Power-down mode 2 is selected (SPD2). 847 * | | |1100 = Deep Power-down mode 0 is selected (DPD0). 848 * | | |1101 = Deep Power-down mode 1 is selected (DPD1). 849 * | | |Other = Reserved. 850 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 851 * |[10:8] |SRETSEL |SRAM Retention Range Select Bit (Write Protect) 852 * | | |Select SRAM retention range when chip enters NPD3/NPD4/NPD5/SPD0~2 mode. 853 * | | |000 = No SRAM retention. 854 * | | |001 = 8K SRAM retention when chip enters NPD3/NPD4/NPD5/SPD0~2 mode. 855 * | | |010 = 24K SRAM retention when chip enters NPD3/NPD4/NPD5/SPD0~2 mode. 856 * | | |011 = 40K SRAM retention when chip enters NPD3/NPD4/NPD5/SPD0~2 mode. 857 * | | |100 = 72K SRAM retention when chip enters NPD3/NPD4/NPD5/SPD0~2 mode. 858 * | | |101 = 104K SRAM retention when chip enters NPD3/NPD4/NPD5/SPD0~2 mode. 859 * | | |110 = 168K SRAM retention when chip enters NPD3/NPD4/NPD5/SPD0~2 mode. 860 * | | |Others = Reserved. 861 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 862 * | | |Note 2: Users should make sure program stack is within SRAM retention range before chip enters NPD3/NPD4/NPD5/SPD0~2 mode. 863 * |[16] |LSRETSEL |LPSRAM Retention Range Select Bit (Write Protect) 864 * | | |Select LPSRAM retention range when chip enters NPD3/NPD4/NPD5/SPD0~2/DPD0~1 mode. 865 * | | |0 = LPSRAM shut down. 866 * | | |1 = 8K LPSRAM retention (0x2800_0000 - 0x2800_1FFF) when chip enters NPD3/NPD4/NPD5/SPD0~2 mode. 867 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 868 * | | |Note 2: This bit should be set 1 if LPSRAM is active in NPD3/NPD4/NPD5 mode. 869 * |[20] |CARETDIS |Cache RAM Retention Disable Bit (Write Protect) 870 * | | |0 = Cache RAM retention when chip enters NPD3/NPD4/NPD5 mode. 871 * | | |1 = Cache RAM shut down when chip enters NPD3/NPD4/NPD5 mode. 872 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 873 * @var CLK_T::PMUSTS 874 * Offset: 0x94 Power Manager Status Register 875 * --------------------------------------------------------------------------------------------------- 876 * |Bits |Field |Descriptions 877 * | :----: | :----: | :---- | 878 * |[0] |WKPIN0 |Pin0 Wake-up Flag (Read Only) 879 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0). 880 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD0~1 mode. 881 * |[1] |TMRWK |Timer Wake-up Flag (Read Only) 882 * | | |This flag indicates that wake-up of chip from NPD0~5 or Deep Power-down mode (DPD0~1) or Standby Power-down (SPD0~2) mode was requested by wakeup timer time-out. 883 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD0~5/SPD0~2/DPD0~1 mode. 884 * |[2] |RTCWK |RTC Wake-up Flag (Read Only) 885 * | | |This flag indicates that wakeup of device from NPD3/NPD4/NPD5 or Deep Power-down mode (DPD0~1) or Standby Power-down (SPD0~2) mode was requested with a RTC alarm, tick time or tamper happened. 886 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD3/NPD4/NPD5/ SPD0~2/DPD0~1 mode. 887 * |[3] |WKPIN1 |Pin1 Wake-up Flag (Read Only) 888 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.0). 889 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD0/DPD1 mode. 890 * |[4] |WKPIN2 |Pin2 Wake-up Flag (Read Only) 891 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.2). 892 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD0/DPD1 mode. 893 * |[5] |WKPIN3 |Pin3 Wake-up Flag (Read Only) 894 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.12). 895 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD0/DPD1 mode. 896 * |[6] |WKPIN4 |Pin4 Wake-up Flag (Read Only) 897 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PF.6). 898 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD0/DPD1 mode. 899 * |[7] |WKPIN5 |Pin5 Wake-up Flag( Read Only) 900 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PA.12). 901 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD0/DPD1 mode. 902 * |[8] |GPAWK0 |GPA Wake-up 0 Flag (Read Only) 903 * | | |This flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode (SPD0~2) was requested by a transition of selected one GPA group pins. 904 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD0~5/SPD0~2 mode. 905 * |[9] |GPBWK0 |GPB Wake-up 0 Flag (Read Only) 906 * | | |This flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode (SPD0~2) was requested by a transition of selected one GPB group pins. 907 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD0~5/SPD0~2 mode. 908 * |[10] |GPCWK0 |GPC Wake-up 0 Flag (Read Only) 909 * | | |This flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode (SPD0~2) was requested by a transition of selected one GPC group pins. 910 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD0~5/SPD0~2 mode. 911 * |[11] |GPDWK0 |GPD Wake-up 0 Flag (Read Only) 912 * | | |This flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode (SPD0~2) was requested by a transition of selected one GPD group pins. 913 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD0~5/SPD0~2 mode. 914 * |[12] |LVRWK |LVR Wake-up Flag (Read Only) 915 * | | |This flag indicates that wakeup of device from NPD3/NPD4/NPD5 or Standby Power-down mode (SPD0~2) was requested with a LVR happened. 916 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD3/NPD4/NPD5/SPD0~2 mode. 917 * |[13] |BODWK |BOD Wake-up Flag (Read Only) 918 * | | |This flag indicates that wakeup of device from NPD3/NPD4/NPD5 or Standby Power-down mode (SPD0~2) was requested with a BOD happened. 919 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD3/NPD4/NPD5/SPD0~2 mode. 920 * |[15] |RSTWK |RST pin Wake-up Flag (Read Only) 921 * | | |This flag indicates that wakeup of device from NPD3/NPD4/NPD5 or Deep Power-down mode (DPD0~1) or Standby Power-down mode (SPD0~2) was requested with a RST pin trigger happened. 922 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD3/NPD4/NPD5/SPD0~2/DPD0~1 mode. 923 * |[16] |ACMPWK0 |ACMP0 Wake-up Flag (Read Only) 924 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD0~2) was requested with a ACMP0 transition. 925 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD0~2 mode. 926 * |[17] |ACMPWK1 |ACMP1 Wake-up Flag (Read Only) 927 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD0~2) was requested with a ACMP1 transition. 928 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD0~2 mode. 929 * |[18] |ACMPWK2 |ACMP2 Wake-up Flag (Read Only) 930 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD0~2) was requested with a ACMP2 transition. 931 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD0~2 mode. 932 * |[24] |GPAWK1 |GPA Wake-up 1 Flag (Read Only) 933 * | | |This flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode was requested by a transition of selected one GPA group pins. 934 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD0~5/SPD0~2 mode. 935 * |[25] |GPBWK1 |GPB Wake-up 1 Flag (Read Only) 936 * | | |This flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode was requested by a transition of selected one GPB group pins. 937 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD0~5/SPD0~2 mode. 938 * |[26] |GPCWK1 |GPC Wake-up 1 Flag (Read Only) 939 * | | |This flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode was requested by a transition of selected one GPC group pins. 940 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD0~5/SPD0~2 mode. 941 * |[27] |GPDWK1 |GPD Wake-up 1 Flag (Read Only) 942 * | | |This flag indicates that wake-up of chip from NPD0~5 or Standby Power-down mode was requested by a transition of selected one GPD group pins. 943 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering NPD0~5/ SPD0~2 mode. 944 * |[31] |CLRWK |Clear Wake-up Flag 945 * | | |0 = Not cleared. 946 * | | |1 = Clear all wake-up flags. 947 * | | |Note 1: This bit is auto cleared by hardware. 948 * | | |Note 2: If DISAUTOC (CLK_PMUCLK[31])=0, all wake-up flags are auto cleared when chip enters NPD3/NPD4/NPD5/SPD0~2/DPD0~1 Power-down mode. 949 * @var CLK_T::PMUWKCTL 950 * Offset: 0x98 Power Manager Wake-up Control Register 951 * --------------------------------------------------------------------------------------------------- 952 * |Bits |Field |Descriptions 953 * | :----: | :----: | :---- | 954 * |[0] |WKTMREN |Wake-up Timer Enable Bit (Write Protect) 955 * | | |0 = Wake-up timer Disabled. 956 * | | |1 = Wake-up timer Enabled. 957 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 958 * |[1] |WKTMRMOD |Wake-up Timer Mode (Write Protect) 959 * | | |0 = Wake-up timer started when entering any of Power-down mode (except CPU idle mode). 960 * | | |1 = Wake-up timer started immedially when WKTMREN (CLK_PMUWKCTL[0]) =1. 961 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 962 * |[6] |ACMPWKEN |ACMP Standby Power-down Mode Wake-up Enable Bit (Write Protect) 963 * | | |0 = ACMP wake-up disable at Standby Power-down mode. 964 * | | |1 = ACMP wake-up enabled at Standby Power-down mode. 965 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 966 * | | |Note: Set FILTSEL(ACMP_CTLx[15:13]) for comparator output filter count selection, the filter clock is LIRC in ACMP SPD/USPD mode wakeup function. 967 * |[7] |RTCWKEN |RTC Wake-up Enable Bit (Write Protect) 968 * | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode. 969 * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. 970 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 971 * |[11:8] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) 972 * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode. 973 * | | |0000 = Time-out interval is 512 LIRC clocks (16ms). 974 * | | |0001 = Time-out interval is 1024 LIRC clocks (32ms). 975 * | | |0010 = Time-out interval is 2048 LIRC clocks (64ms). 976 * | | |0011 = Time-out interval is 4096 LIRC clocks (128ms). 977 * | | |0100 = Time-out interval is 8192 LIRC clocks (256ms). 978 * | | |0101 = Time-out interval is 16384 LIRC clocks (512ms). 979 * | | |0110 = Time-out interval is 32768 LIRC clocks (1024ms). 980 * | | |0111 = Time-out interval is 65536 LIRC clocks (2048ms). 981 * | | |1000 = Time-out interval is 131072 LIRC clocks (4096ms). 982 * | | |1001 = Time-out interval is 262144 LIRC clocks (8192ms). 983 * | | |1010 = Time-out interval is 524288 LIRC clocks (16384ms). 984 * | | |1011 = Time-out interval is 1048576 LIRC clocks (32768ms). 985 * | | |1100 = Time-out interval is 2097152 LIRC clocks (65536ms). 986 * | | |1101 = Time-out interval is 4194304 LIRC clocks (131072ms). 987 * | | |Others = Time-out interval is 512 LIRC clocks (16ms). 988 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 989 * |[17:16] |WKPINEN0 |Wake-up Pin0 Enable Bit (Write Protect) 990 * | | |This is control register for GPC.0 to wake-up pin. 991 * | | |00 = Wake-up pin disable at Deep Power-down mode. 992 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 993 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 994 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 995 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 996 * |[19:18] |WKPINEN1 |Wake-up Pin1 Enable Bit (Write Protect) 997 * | | |This is control register for GPB.0 to wake-up pin. 998 * | | |00 = Wake-up pin disable at Deep Power-down mode. 999 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1000 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1001 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1002 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1003 * |[21:20] |WKPINEN2 |Wake-up Pin2 Enable Bit (Write Protect) 1004 * | | |This is control register for GPB.2 to wake-up pin. 1005 * | | |00 = Wake-up pin disable at Deep Power-down mode. 1006 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1007 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1008 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1009 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1010 * |[23:22] |WKPINEN3 |Wake-up Pin3 Enable Bit (Write Protect) 1011 * | | |This is control register for GPB.12 to wake-up pin. 1012 * | | |00 = Wake-up pin disable at Deep Power-down mode. 1013 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1014 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1015 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1016 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1017 * |[25:24] |WKPINEN4 |Wake-up Pin4 Enable Bit (Write Protect) 1018 * | | |This is control register for GPF.6 to wake-up pin. 1019 * | | |00 = Wake-up pin disable at Deep Power-down mode. 1020 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1021 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1022 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1023 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1024 * | | |Note: Setting IOCTLSEL(RTC_LXTCTL[8]) to avoid GPF6 unexpected falling edge. 1025 * |[27:26] |WKPINEN5 |Wake-up Pin5 Enable Bit (Write Protect) 1026 * | | |This is control register for GPA.12 to wake-up pin. 1027 * | | |00 = Wake-up pin disable at Deep Power-down mode. 1028 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1029 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1030 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1031 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1032 * |[31] |DISAUTOC |Disable Auto Clear Wakeup flag (Write Protect) 1033 * | | |0 = When CPU enter NPD3/NPD4/NPD5/SPD0~2/DPD0~1, all of wake-up flags in CLK_PMUSTS are auto cleared. 1034 * | | |1 = Disable auto clear function. 1035 * | | |Note 1:This bit is write protected. Refer to the SYS_REGLCTL register. 1036 * | | |Note 2:Wakeup from NPD3/NPD4/NPD5, this bits keep original setting. 1037 * | | |Note 3:Wakeup from SPD0~2/DPD0~1, this bits reseted. 1038 * | | |Note 4 : During hardware do auto clear wakeup flag (1 HCLK cycle period), those wakeup function not work. 1039 * @var CLK_T::PWDBCTL 1040 * Offset: 0x9C GPIO Pin WKIO De-bounce Control Register 1041 * --------------------------------------------------------------------------------------------------- 1042 * |Bits |Field |Descriptions 1043 * | :----: | :----: | :---- | 1044 * |[3:0] |SWKDBCLKSEL|WKIO De-bounce Sampling Cycle Selection 1045 * | | |0000 = Sample wake-up input once per 1 clocks. 1046 * | | |0001 = Sample wake-up input once per 2 clocks. 1047 * | | |0010 = Sample wake-up input once per 4 clocks. 1048 * | | |0011 = Sample wake-up input once per 8 clocks. 1049 * | | |0100 = Sample wake-up input once per 16 clocks. 1050 * | | |0101 = Sample wake-up input once per 32 clocks. 1051 * | | |0110 = Sample wake-up input once per 64 clocks. 1052 * | | |0111 = Sample wake-up input once per 128 clocks. 1053 * | | |1000 = Sample wake-up input once per 256 clocks. 1054 * | | |1001 = Sample wake-up input once per 2*256 clocks. 1055 * | | |1010 = Sample wake-up input once per 4*256 clocks. 1056 * | | |1011 = Sample wake-up input once per 8*256 clocks. 1057 * | | |1100 = Sample wake-up input once per 16*256 clocks. 1058 * | | |1101 = Sample wake-up input once per 32*256 clocks. 1059 * | | |1110 = Sample wake-up input once per 64*256 clocks. 1060 * | | |1111 = Sample wake-up input once per 128*256 clocks.. 1061 * | | |Note: De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC). 1062 * @var CLK_T::PAPWCTL 1063 * Offset: 0xA0 GPA Pin WKIO Control Register 1064 * --------------------------------------------------------------------------------------------------- 1065 * |Bits |Field |Descriptions 1066 * | :----: | :----: | :---- | 1067 * |[0] |WKEN0 |GPA Pin 0 Wake-up-I/O Enable Bit 1068 * | | |0 = GPA group pin 0 Wake-up-I/O function Disabled. 1069 * | | |1 = GPA group pin 0 Wakeup-I/O function Enabled. 1070 * |[1] |PRWKEN0 |GPA Pin 0 Rising Edge Detect Enable Bit 1071 * | | |0 = GPA group pin 0 rising edge detect function Disabled. 1072 * | | |1 = GPA group pin 0 rising edge detect function Enabled. 1073 * |[2] |PFWKEN0 |GPA Pin 0 Falling Edge Detect Enable Bit 1074 * | | |0 = GPA group pin 0 falling edge detect function Disabled. 1075 * | | |1 = GPA group pin 0 falling edge detect function Enabled. 1076 * |[7:4] |WKPSEL0 |GPA Pin 0 Wakeup-I/O Pin Select 1077 * | | |0000 = GPA.0 as Wake-up-I/O function select. 1078 * | | |0001 = GPA.1 as Wakeup-I/O function select. 1079 * | | |0010 = GPA.2 as Wakeup-I/O function select. 1080 * | | |0011 = GPA.3 as Wakeup-I/O function select. 1081 * | | |0100 = GPA.4 as Wakeup-I/O function select. 1082 * | | |0101 = GPA.5 as Wakeup-I/O function select. 1083 * | | |0110 = GPA.6 as Wakeup-I/O function select. 1084 * | | |0111 = GPA.7 as Wakeup-I/O function select. 1085 * | | |1000 = GPA.8 as Wakeup-I/O function select. 1086 * | | |1001 = GPA.9 as Wakeup-I/O function select. 1087 * | | |1010 = GPA.10 as Wakeup-I/O function select. 1088 * | | |1011 = GPA.11 as Wakeup-I/O function select. 1089 * | | |1100 = GPA.12 as Wakeup-I/O function select. 1090 * | | |1101 = GPA.13 as Wakeup-I/O function select. 1091 * | | |1110 = GPA.14 as Wakeup-I/O function select. 1092 * | | |1111 = GPA.15 as Wakeup-I/O function select. 1093 * |[8] |DBEN0 |GPA Pin 0 Input Signal De-bounce Enable Bit 1094 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O 1095 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 1096 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator. 1097 * | | |0 = GPA group pin 0 Wake-up-I/O pin De-bounce function Disabled. 1098 * | | |1 = GPA group pin 0 Wakeup-I/O pin De-bounce function Enabled. 1099 * | | |The de-bounce function is valid only for edgetriggered. 1100 * |[10] |TRIGM0 |GPA Pin 0 Wake-up Pin Trigger Mode Select 1101 * | | |0 = GPA group pin 0 wake-up chip Enabled, trigger ip Enabled. 1102 * | | |1 = GPA group pin 0 wake-up chip Disabled, trigger ip Enabled. 1103 * |[11] |NMR0 |GPA Pin 0 Function Enable at Normal Run Mode Select 1104 * | | |0 = GPA group pin 0 wake-up function enable when chip enters power down. 1105 * | | |1 = GPA group pin 0 wake-up function enable when chip is normal run. 1106 * | | |Note: Enable this bit and the I/O wake-up function is enabled immediately. 1107 * |[16] |WKEN1 |GPA Pin 1 Wake-up Enable Bit 1108 * | | |0 = GPA group pin 1 wake-up function Disabled. 1109 * | | |1 = GPA group pin 1 wake-up function Enabled. 1110 * |[17] |PRWKEN1 |GPA Pin 1 Rising Edge Detect Enable Bit 1111 * | | |0 = GPA group pin 1 rising edge detect function Disabled. 1112 * | | |1 = GPA group pin 1 rising edge detect function Enabled. 1113 * |[18] |PFWKEN1 |GPA Pin 1 Falling Edge Detect Enable Bit 1114 * | | |0 = GPA group pin 1 falling edge detect function Disabled. 1115 * | | |1 = GPA group pin 1 falling edge detect function Enabled. 1116 * |[23:20] |WKPSEL1 |GPA Pin 1 Wakeup-I/O Pin Select 1117 * | | |0000 = GPA.0 as Wakeup-I/O function select. 1118 * | | |0001 = GPA.1 as Wakeup-I/O function select. 1119 * | | |0010 = GPA.2 as Wakeup-I/O function select. 1120 * | | |0011 = GPA.3 as Wakeup-I/O function select. 1121 * | | |0100 = GPA.4 as Wakeup-I/O function select. 1122 * | | |0101 = GPA.5 as Wakeup-I/O function select. 1123 * | | |0110 = GPA.6 as Wakeup-I/O function select. 1124 * | | |0111 = GPA.7 as Wakeup-I/O function select. 1125 * | | |1000 = GPA.8 as Wakeup-I/O function select. 1126 * | | |1001 = GPA.9 as Wakeup-I/O function select. 1127 * | | |1010 = GPA.10 as Wakeup-I/O function select. 1128 * | | |1011 = GPA.11 as Wakeup-I/O function select. 1129 * | | |1100 = GPA.12 as Wakeup-I/O function select. 1130 * | | |1101 = GPA.13 as Wakeup-I/O function select. 1131 * | | |1110 = GPA.14 as Wakeup-I/O function select. 1132 * | | |1111 = GPA.15 as Wakeup-I/O function select. 1133 * |[24] |DBEN1 |GPA Pin 1 Input Signal De-bounce Enable Bit 1134 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O 1135 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 1136 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator. 1137 * | | |0 = GPA group pin 1 Wakeup-I/O pin De-bounce function Disabled. 1138 * | | |1 = GPA group pin 1 Wakeup-I/O pin De-bounce function Enabled. 1139 * | | |The de-bounce function is valid only for edgetriggered. 1140 * |[26] |TRIGM1 |GPA Pin 1 Wake-up Pin Trigger Mode Select 1141 * | | |0 = GPA group pin 1 wake-up chip Enabled, trigger ip Enabled. 1142 * | | |1 = GPA group pin 1 wake-up chip Disabled, trigger ip Enabled. 1143 * |[27] |NMR1 |GPA Pin 1 Function Enable at Normal Run Mode Select 1144 * | | |0 = GPA group pin 1 wake-up function enable when chip enters power down. 1145 * | | |1 = GPA group pin 1 wake-up function enable when chip is normal run. 1146 * | | |Note: Enable this bit and the WKIO function is enabled immediately. 1147 * @var CLK_T::PBPWCTL 1148 * Offset: 0xA4 GPB Pin WKIO Control Register 1149 * --------------------------------------------------------------------------------------------------- 1150 * |Bits |Field |Descriptions 1151 * | :----: | :----: | :---- | 1152 * |[0] |WKEN0 |GPB Pin 0 Wakeup-I/O Enable Bit 1153 * | | |0 = GPB group pin 0 Wakeup-I/O function Disabled. 1154 * | | |1 = GPB group pin 0 Wakeup-I/O function Enabled. 1155 * |[1] |PRWKEN0 |GPB Pin 0 Rising Edge Detect Enable Bit 1156 * | | |0 = GPB group pin 0 rising edge detect function Disabled. 1157 * | | |1 = GPB group pin 0 rising edge detect function Enabled. 1158 * |[2] |PFWKEN0 |GPB Pin 0 Falling Edge Detect Enable Bit 1159 * | | |0 = GPB group pin 0 falling edge detect function Disabled. 1160 * | | |1 = GPB group pin 0 falling edge detect function Enabled. 1161 * |[7:4] |WKPSEL0 |GPB Pin 0 Wakeup-I/O Pin Select 1162 * | | |0000 = GPB.0 as Wakeup-I/O function select. 1163 * | | |0001 = GPB.1 as Wakeup-I/O function select. 1164 * | | |0010 = GPB.2 as Wakeup-I/O function select. 1165 * | | |0011 = GPB.3 as Wakeup-I/O function select. 1166 * | | |0100 = GPB.4 as Wakeup-I/O function select. 1167 * | | |0101 = GPB.5 as Wakeup-I/O function select. 1168 * | | |0110 = GPB.6 as Wakeup-I/O function select. 1169 * | | |0111 = GPB.7 as Wakeup-I/O function select. 1170 * | | |1000 = GPB.8 as Wakeup-I/O function select. 1171 * | | |1001 = GPB.9 as Wakeup-I/O function select. 1172 * | | |1010 = GPB.10 as Wakeup-I/O function select. 1173 * | | |1011 = GPB.11 as Wakeup-I/O function select. 1174 * | | |1100 = GPB.12 as Wakeup-I/O function select. 1175 * | | |1101 = GPB.13 as Wakeup-I/O function select. 1176 * | | |1110 = GPB.14 as Wakeup-I/O function select. 1177 * | | |1111 = GPB.15 as Wakeup-I/O function select. 1178 * |[8] |DBEN0 |GPB Pin 0 Input Signal De-bounce Enable Bit 1179 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O 1180 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 1181 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator. 1182 * | | |0 = GPB group pin 0 Wakeup-I/O pin De-bounce function Disabled. 1183 * | | |1 = GPB group pin 0 Wakeup-I/O pin De-bounce function Enabled. 1184 * | | |The de-bounce function is valid only for edgetriggered. 1185 * |[10] |TRIGM0 |GPB Pin 0 Wake-up Pin Trigger Mode Select 1186 * | | |0 = GPB group pin 0 wake-up chip Enabled, trigger ip Enabled. 1187 * | | |1 = GPB group pin 0 wake-up chip Disabled, trigger ip Enabled. 1188 * |[11] |NMR0 |GPB Pin 0 Function Enable at Normal Run Mode Select 1189 * | | |0 = GPB group pin 0 wake-up function enable when chip enters power down. 1190 * | | |1 = GPB group pin 0 wake-up function enable when chip is normal run. 1191 * | | |Note: Enable this bit and the I/O wake-up function is enabled immediately. 1192 * |[16] |WKEN1 |GPB Pin 1 Wake-up Enable Bit 1193 * | | |0 = GPB group pin 1 wake-up function Disabled. 1194 * | | |1 = GPB group pin 1 wake-up function Enabled. 1195 * |[17] |PRWKEN1 |GPB Pin 1 Rising Edge Detect Enable Bit 1196 * | | |0 = GPB group pin 1 rising edge detect function Disabled. 1197 * | | |1 = GPB group pin 1 rising edge detect function Enabled. 1198 * |[18] |PFWKEN1 |GPB Pin 1 Falling Edge Detect Enable Bit 1199 * | | |0 = GPB group pin 1 falling edge detect function Disabled. 1200 * | | |1 = GPB group pin 1 falling edge detect function Enabled. 1201 * |[23:20] |WKPSEL1 |GPB Pin 1 Wakeup-I/O Pin Select 1202 * | | |0000 = GPB.0 as Wakeup-I/O function select. 1203 * | | |0001 = GPB.1 as Wakeup-I/O function select. 1204 * | | |0010 = GPB.2 as Wakeup-I/O function select. 1205 * | | |0011 = GPB.3 as Wakeup-I/O function select. 1206 * | | |0100 = GPB.4 as Wakeup-I/O function select. 1207 * | | |0101 = GPB.5 as Wakeup-I/O function select. 1208 * | | |0110 = GPB.6 as Wakeup-I/O function select. 1209 * | | |0111 = GPB.7 as Wakeup-I/O function select. 1210 * | | |1000 = GPB.8 as Wakeup-I/O function select. 1211 * | | |1001 = GPB.9 as Wakeup-I/O function select. 1212 * | | |1010 = GPB.10 as Wakeup-I/O function select. 1213 * | | |1011 = GPB.11 as Wakeup-I/O function select. 1214 * | | |1100 = GPB.12 as Wakeup-I/O function select. 1215 * | | |1101 = GPB.13 as Wakeup-I/O function select. 1216 * | | |1110 = GPB.14 as Wakeup-I/O function select. 1217 * | | |1111 = GPB.15 as Wakeup-I/O function select. 1218 * |[24] |DBEN1 |GPB Pin 1 Input Signal De-bounce Enable Bit 1219 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O 1220 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 1221 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator. 1222 * | | |0 = GPB group pin 1 Wakeup-I/O pin De-bounce function Disabled. 1223 * | | |1 = GPB group pin 1 Wakeup-I/O pin De-bounce function Enabled. 1224 * | | |The de-bounce function is valid only for edgetriggered. 1225 * |[26] |TRIGM1 |GPB Pin 1 Wake-up Pin Trigger Mode Select 1226 * | | |0 = GPB group pin 1 wake-up chip Enabled, trigger ip Enabled. 1227 * | | |1 = GPB group pin 1 wake-up chip Disabled, trigger ip Enabled. 1228 * |[27] |NMR1 |GPB Pin 1 Function Enable at Normal Run Mode Select 1229 * | | |0 = GPB group pin 1 wake-up function enable when chip enters power down. 1230 * | | |1 = GPB group pin 1 wake-up function enable when chip is normal run. 1231 * | | |Note: Enable this bit and the WKIO function is enabled immediately. 1232 * @var CLK_T::PCPWCTL 1233 * Offset: 0xA8 GPC Pin WKIO Control Register 1234 * --------------------------------------------------------------------------------------------------- 1235 * |Bits |Field |Descriptions 1236 * | :----: | :----: | :---- | 1237 * |[0] |WKEN0 |GPC Pin 0 Wakeup-I/O Enable Bit 1238 * | | |0 = GPC group pin 0 Wakeup-I/O function Disabled. 1239 * | | |1 = GPC group pin 0 Wakeup-I/O function Enabled. 1240 * |[1] |PRWKEN0 |GPC Pin 0 Rising Edge Detect Enable Bit 1241 * | | |0 = GPC group pin 0 rising edge detect function Disabled. 1242 * | | |1 = GPC group pin 0 rising edge detect function Enabled. 1243 * |[2] |PFWKEN0 |GPC Pin 0 Falling Edge Detect Enable Bit 1244 * | | |0 = GPC group pin 0 falling edge detect function Disabled. 1245 * | | |1 = GPC group pin 0 falling edge detect function Enabled. 1246 * |[7:4] |WKPSEL0 |GPC Pin 0 Wakeup-I/O Pin Select 1247 * | | |0000 = GPC.0 as Wakeup-I/O function select. 1248 * | | |0001 = GPC.1 as Wakeup-I/O function select. 1249 * | | |0010 = GPC.2 as Wakeup-I/O function select. 1250 * | | |0011 = GPC.3 as Wakeup-I/O function select. 1251 * | | |0100 = GPC.4 as Wakeup-I/O function select. 1252 * | | |0101 = GPC.5 as Wakeup-I/O function select. 1253 * | | |0110 = GPC.6 as Wakeup-I/O function select. 1254 * | | |0111 = GPC.7 as Wakeup-I/O function select. 1255 * | | |1000 = GPC.8 as Wakeup-I/O function select. 1256 * | | |1001 = GPC.9 as Wakeup-I/O function select. 1257 * | | |1010 = GPC.10 as Wakeup-I/O function select. 1258 * | | |1011 = GPC.11 as Wakeup-I/O function select. 1259 * | | |1100 = GPC.12 as Wakeup-I/O function select. 1260 * | | |1101 = GPC.13 as Wakeup-I/O function select. 1261 * | | |1110 = GPC.14 as Wakeup-I/O function select. 1262 * | | |1111 = GPC.15 as Wakeup-I/O function select. 1263 * |[8] |DBEN0 |GPC Pin 0 Input Signal De-bounce Enable Bit 1264 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O 1265 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 1266 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator. 1267 * | | |0 = GPC group pin 0 Wakeup-I/O pin De-bounce function Disabled. 1268 * | | |1 = GPC group pin 0 Wakeup-I/O pin De-bounce function Enabled. 1269 * | | |The de-bounce function is valid only for edgetriggered. 1270 * |[10] |TRIGM0 |GPC Pin 0 Wake-up Pin Trigger Mode Select 1271 * | | |0 = GPC group pin 0 wake-up chip Enabled, trigger ip Enabled. 1272 * | | |1 = GPC group pin 0 wake-up chip Disabled, trigger ip Enabled. 1273 * |[11] |NMR0 |GPC Pin 0 Function Enable at Normal Run Mode Select 1274 * | | |0 = GPC group pin 0 wake-up function enabled when chip enters power down. 1275 * | | |1 = GPC group pin 0 wake-up function enabled when chip is normal run. 1276 * | | |Note: Enable this bit and the I/O wake-up function is enabled immediately. 1277 * |[16] |WKEN1 |GPC Pin 1 Wake-up Enable Bit 1278 * | | |0 = GPC group pin 1 wake-up function Disabled. 1279 * | | |1 = GPC group pin 1 wake-up function Enabled. 1280 * |[17] |PRWKEN1 |GPC Pin 1 Rising Edge Detect Enable Bit 1281 * | | |0 = GPC group pin 1 rising edge detect function Disabled. 1282 * | | |1 = GPC group pin 1 rising edge detect function Enabled. 1283 * |[18] |PFWKEN1 |GPC Pin 1 Falling Edge Detect Enable Bit 1284 * | | |0 = GPC group pin 1 falling edge detect function Disabled. 1285 * | | |1 = GPC group pin 1 falling edge detect function Enabled. 1286 * |[23:20] |WKPSEL1 |GPC Pin 1 Wakeup-I/O Pin Select 1287 * | | |0000 = GPC.0 as Wakeup-I/O function select. 1288 * | | |0001 = GPC.1 as Wakeup-I/O function select. 1289 * | | |0010 = GPC.2 as Wakeup-I/O function select. 1290 * | | |0011 = GPC.3 as Wakeup-I/O function select. 1291 * | | |0100 = GPC.4 as Wakeup-I/O function select. 1292 * | | |0101 = GPC.5 as Wakeup-I/O function select. 1293 * | | |0110 = GPC.6 as Wakeup-I/O function select. 1294 * | | |0111 = GPC.7 as Wakeup-I/O function select. 1295 * | | |1000 = GPC.8 as Wakeup-I/O function select. 1296 * | | |1001 = GPC.9 as Wakeup-I/O function select. 1297 * | | |1010 = GPC.10 as Wakeup-I/O function select. 1298 * | | |1011 = GPC.11 as Wakeup-I/O function select. 1299 * | | |1100 = GPC.12 as Wakeup-I/O function select. 1300 * | | |1101 = GPC.13 as Wakeup-I/O function select. 1301 * | | |1110 = GPC.14 as Wakeup-I/O function select. 1302 * | | |1111 = GPC.15 as Wakeup-I/O function select. 1303 * |[24] |DBEN1 |GPC Pin 1 Input Signal De-bounce Enable Bit 1304 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O 1305 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 1306 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator. 1307 * | | |0 = GPC group pin 1 Wakeup-I/O pin De-bounce function Disabled. 1308 * | | |1 = GPC group pin 1 Wakeup-I/O pin De-bounce function Enabled. 1309 * | | |The de-bounce function is valid only for edgetriggered. 1310 * |[26] |TRIGM1 |GPC Pin 1 Wake-up Pin Trigger Mode Select 1311 * | | |0 = GPC group pin 1 wake-up chip Enabled, trigger ip Enabled. 1312 * | | |1 = GPC group pin 1 wake-up chip Disabled, trigger ip Enabled. 1313 * |[27] |NMR1 |GPC Pin 1 Function Enable at Normal Run Mode Select 1314 * | | |0 = GPC group pin 1 wake-up function enabled when chip enters power down. 1315 * | | |1 = GPC group pin 1 wake-up function enabled when chip is normal run. 1316 * | | |Note: Enable this bit and the WKIO function is enabled immediately. 1317 * @var CLK_T::PDPWCTL 1318 * Offset: 0xAC GPD Pin WKIO Control Register 1319 * --------------------------------------------------------------------------------------------------- 1320 * |Bits |Field |Descriptions 1321 * | :----: | :----: | :---- | 1322 * |[0] |WKEN0 |GPD Pin 0 Wakeup-I/O Enable Bit 1323 * | | |0 = GPD group pin 0 Wakeup-I/O function Disabled. 1324 * | | |1 = GPD group pin 0 Wakeup-I/O function Enabled. 1325 * |[1] |PRWKEN0 |GPD Pin 0 Rising Edge Detect Enable Bit 1326 * | | |0 = GPD group pin 0 rising edge detect function Disabled. 1327 * | | |1 = GPD group pin 0 rising edge detect function Enabled. 1328 * |[2] |PFWKEN0 |GPD Pin 0 Falling Edge Detect Enable Bit 1329 * | | |0 = GPD group pin 0 falling edge detect function Disabled. 1330 * | | |1 = GPD group pin 0 falling edge detect function Enabled. 1331 * |[7:4] |WKPSEL0 |GPD Pin 0 Wakeup-I/O Pin Select 1332 * | | |0000 = GPD.0 as Wakeup-I/O function select. 1333 * | | |0001 = GPD.1 as Wakeup-I/O function select. 1334 * | | |0010 = GPD.2 as Wakeup-I/O function select. 1335 * | | |0011 = GPD.3 as Wakeup-I/O function select. 1336 * | | |0100 = GPD.4 as Wakeup-I/O function select. 1337 * | | |0101 = GPD.5 as Wakeup-I/O function select. 1338 * | | |0110 = GPD.6 as Wakeup-I/O function select. 1339 * | | |0111 = GPD.7 as Wakeup-I/O function select. 1340 * | | |1000 = GPD.8 as Wakeup-I/O function select. 1341 * | | |1001 = GPD.9 as Wakeup-I/O function select. 1342 * | | |1010 = GPD.10 as Wakeup-I/O function select. 1343 * | | |1011 = GPD.11 as Wakeup-I/O function select. 1344 * | | |1100 = GPD.12 as Wakeup-I/O function select. 1345 * | | |1101 = GPD.13 as Wakeup-I/O function select. 1346 * | | |1110 = GPD.14 as Wakeup-I/O function select. 1347 * | | |1111 = GPD.15 as Wakeup-I/O function select. 1348 * |[8] |DBEN0 |GPD Pin 0 Input Signal De-bounce Enable Bit 1349 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O 1350 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 1351 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator. 1352 * | | |0 = GPD group pin 0 Wakeup-I/O pin De-bounce function Disabled. 1353 * | | |1 = GPD group pin 0 Wakeup-I/O pin De-bounce function Enabled. 1354 * | | |The de-bounce function is valid only for edgetriggered. 1355 * |[10] |TRIGM0 |GPD Pin 0 Wake-up Pin Trigger Mode Select 1356 * | | |0 = GPD group pin 0 wake-up chip Enabled, trigger ip Enabled. 1357 * | | |1 = GPD group pin 0 wake-up chip Disabled, trigger ip Enabled. 1358 * |[11] |NMR0 |GPD Pin 0 Function Enable at Normal Run Mode Select 1359 * | | |0 = GPD group pin 0 wake-up function enable when chip enters power down. 1360 * | | |1 = GPD group pin 0 wake-up function enable when chip is normal run. 1361 * | | |Note: Enable this bit and the I/O wake-up function is enabled immediately. 1362 * |[16] |WKEN1 |GPD Pin 1 Wake-up Enable Bit 1363 * | | |0 = GPD group pin 1 wake-up function Disabled. 1364 * | | |1 = GPD group pin 1 wake-up function Enabled. 1365 * |[17] |PRWKEN1 |GPD Pin 1 Rising Edge Detect Enable Bit 1366 * | | |0 = GPD group pin 1 rising edge detect function Disabled. 1367 * | | |1 = GPD group pin 1 rising edge detect function Enabled. 1368 * |[18] |PFWKEN1 |GPD Pin 1 Falling Edge Detect Enable Bit 1369 * | | |0 = GPD group pin 1 falling edge detect function Disabled. 1370 * | | |1 = GPD group pin 1 falling edge detect function Enabled. 1371 * |[23:20] |WKPSEL1 |GPD Pin 1 Wakeup-I/O Pin Select 1372 * | | |0000 = GPD.0 as Wakeup-I/O function select. 1373 * | | |0001 = GPD.1 as Wakeup-I/O function select. 1374 * | | |0010 = GPD.2 as Wakeup-I/O function select. 1375 * | | |0011 = GPD.3 as Wakeup-I/O function select. 1376 * | | |0100 = GPD.4 as Wakeup-I/O function select. 1377 * | | |0101 = GPD.5 as Wakeup-I/O function select. 1378 * | | |0110 = GPD.6 as Wakeup-I/O function select. 1379 * | | |0111 = GPD.7 as Wakeup-I/O function select. 1380 * | | |1000 = GPD.8 as Wakeup-I/O function select. 1381 * | | |1001 = GPD.9 as Wakeup-I/O function select. 1382 * | | |1010 = GPD.10 as Wakeup-I/O function select. 1383 * | | |1011 = GPD.11 as Wakeup-I/O function select. 1384 * | | |1100 = GPD.12 as Wakeup-I/O function select. 1385 * | | |1101 = GPD.13 as Wakeup-I/O function select. 1386 * | | |1110 = GPD.14 as Wakeup-I/O function select. 1387 * | | |1111 = GPD.15 as Wakeup-I/O function select. 1388 * |[24] |DBEN1 |GPD Pin 1 Input Signal De-bounce Enable Bit 1389 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O 1390 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 1391 * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator. 1392 * | | |0 = GPD group pin 1 Wakeup-I/O pin De-bounce function Disabled. 1393 * | | |1 = GPD group pin 1 Wakeup-I/O pin De-bounce function Enabled. 1394 * | | |The de-bounce function is valid only for edgetriggered. 1395 * |[26] |TRIGM1 |GPD Pin 1 Wake-up Pin Trigger Mode Select 1396 * | | |0 = GPD group pin 1 wake-up chip Enabled, trigger ip Enabled. 1397 * | | |1 = GPD group pin 1 wake-up chip Disabled, trigger ip Enabled. 1398 * |[27] |NMR1 |GPD Pin 1 Function Enable at Normal Run Mode Select 1399 * | | |0 = GPD group pin 1 wake-up function enable when chip enters power down. 1400 * | | |1 = GPD group pin 1 wake-up function enable when chip is normal run. 1401 * | | |Note: Enable this bit and the WKIO function is enabled immediately. 1402 * @var CLK_T::IOPDCTL 1403 * Offset: 0xB0 GPIO Power-down Control Register 1404 * --------------------------------------------------------------------------------------------------- 1405 * |Bits |Field |Descriptions 1406 * | :----: | :----: | :---- | 1407 * |[0] |IOHR |GPIO Hold Release 1408 * | | |When GPIO enters deep power-down mode or standby power-down mode, all I/O status are hold to keep normal operating status 1409 * | | |After chip was waked up from deep power-down mode or standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. 1410 * | | |Note: This bit is auto cleared by hardware. 1411 * |[8] |DPDHOLDEN |Deep-Power-Down Mode GPIO Hold Enable Bit 1412 * | | |0= When GPIO enters deep power-down mode, all I/O status are tri-state. 1413 * | | |1= When GPIO enters deep power-down mode, all I/O status are hold to keep normal operating status 1414 * | | |After chip was waked up from deep power-down mode, the I/O are still keep hold status until user set CLK_IOPDCTL[0] to release I/O hold status. 1415 * @var CLK_T::PMUINTC 1416 * Offset: 0xC0 Power Manager Interrupt Control Register 1417 * --------------------------------------------------------------------------------------------------- 1418 * |Bits |Field |Descriptions 1419 * | :----: | :----: | :---- | 1420 * |[0] |WKTMRIE |Wakeup-Timer Interrupt Enable Bit 1421 * | | |0 = Wakeup-Timer interrupt function Disabled. 1422 * | | |1 = Wakeup-Timer interrupt function Enabled. 1423 * |[8] |WKIOA0IE |Wakeup-I/O GPA group Pin 0 Interrupt Enable Bit 1424 * | | |0 = Wakeup-I/O interrupt function Disabled. 1425 * | | |1 = Wakeup-I/O interrupt function Enabled. 1426 * |[9] |WKIOB0IE |Wakeup-I/O GPB group Pin 0 Interrupt Enable Bit 1427 * | | |0 = Wakeup-I/O interrupt function Disabled. 1428 * | | |1 = Wakeup-I/O interrupt function Enabled. 1429 * |[10] |WKIOC0IE |Wakeup-I/O GPC group Pin 0 Interrupt Enable Bit 1430 * | | |0 = Wakeup-I/O interrupt function Disabled. 1431 * | | |1 = Wakeup-I/O interrupt function Enabled. 1432 * |[11] |WKIOD0IE |Wakeup-I/O GPD group Pin 0 Interrupt Enable Bit 1433 * | | |0 = Wakeup-I/O interrupt function Disabled. 1434 * | | |1 = Wakeup-I/O interrupt function Enabled. 1435 * |[12] |WKIOA1IE |Wakeup-I/O GPA group Pin 1 Interrupt Enable Bit 1436 * | | |0 = Wakeup-I/O interrupt function Disabled. 1437 * | | |1 = Wakeup-I/O interrupt function Enabled. 1438 * |[13] |WKIOB1IE |Wakeup-I/O GPB group Pin 1 Interrupt Enable Bit 1439 * | | |0 = Wakeup-I/O interrupt function Disabled. 1440 * | | |1 = Wakeup-I/O interrupt function Enabled. 1441 * |[14] |WKIOC1IE |Wakeup-I/O GPC group Pin 1 Interrupt Enable Bit 1442 * | | |0 = Wakeup-I/O interrupt function Disabled. 1443 * | | |1 = Wakeup-I/O interrupt function Enabled. 1444 * |[15] |WKIOD1IE |Wakeup-I/O GPD group Pin 1 Interrupt Enable Bit 1445 * | | |0 = Wakeup-I/O interrupt function Disabled. 1446 * | | |1 = Wakeup-I/O interrupt function Enabled. 1447 * @var CLK_T::PMUINTS 1448 * Offset: 0xC4 Power Manager Interrupt Status Register 1449 * --------------------------------------------------------------------------------------------------- 1450 * |Bits |Field |Descriptions 1451 * | :----: | :----: | :---- | 1452 * |[0] |WKTMRIF |Wakeup-Timer Interrupt Flag 1453 * | | |This flag indicates that Wakeup-Timer interrupt happened. 1454 * | | |Flag is set by hardware while Wakeup-Timer event happen when WKTMRIE(CLK_PMUINTC[0])=1. 1455 * | | |Note: Software can clear this bit by writing 1 to it. 1456 * |[8] |WKIOA0IF |Wakeup-I/O GPA group Pin 0 Interrupt Flag 1457 * | | |This flag indicates that Wakeup-I/O interrupt happened. 1458 * | | |Flag is set by hardware while Wakeup-I/O event happen when WKIOPA0IE(CLK_PMUINTC[8])=1. 1459 * | | |Note: Software can clear this bit by writing 1 to it. 1460 * |[9] |WKIOB0IF |Wakeup-I/O GPB group Pin 0 Interrupt Flag 1461 * | | |This flag indicates that Wakeup-I/O interrupt happened. 1462 * | | |Flag is set by hardware while Wakeup-I/O event happen when WKIOPB0IE(CLK_PMUINTC[9])=1. 1463 * | | |Note: Software can clear this bit by writing 1 to it. 1464 * |[10] |WKIOC0IF |Wakeup-I/O GPC group Pin 0 Interrupt Flag 1465 * | | |This flag indicates that Wakeup-I/O interrupt happened. 1466 * | | |Flag is set by hardware while Wakeup-I/O event happen when WKIOPC0IE(CLK_PMUINTC[10])=1. 1467 * | | |Note: Software can clear this bit by writing 1 to it. 1468 * |[11] |WKIOD0IF |Wakeup-I/O GPD group Pin 0 Interrupt Flag 1469 * | | |This flag indicates that Wakeup-I/O interrupt happened. 1470 * | | |Flag is set by hardware while Wakeup-I/O event happen when WKIOPD0IE (CLK_PMUINTC[11])=1. 1471 * | | |Note: Software can clear this bit by writing 1 to it. 1472 * |[12] |WKIOA1IF |Wakeup-I/O GPA group Pin 1 Interrupt Flag 1473 * | | |This flag indicates that Wakeup-I/O interrupt happened. 1474 * | | |Flag is set by hardware while Wakeup-I/O event happen when WKIOPA1IE(CLK_PMUINTC[12])=1. 1475 * | | |Note: Software can clear this bit by writing 1 to it. 1476 * |[13] |WKIOB1IF |Wakeup-I/O GPB group Pin 1 Interrupt Flag 1477 * | | |This flag indicates that Wakeup-I/O interrupt happened. 1478 * | | |Flag is set by hardware while Wakeup-I/O event happen when WKIOPB1IE(CLK_PMUINTC[13])=1. 1479 * | | |Note: Software can clear this bit by writing 1 to it. 1480 * |[14] |WKIOC1IF |Wakeup-I/O GPC group Pin 1 Interrupt Flag 1481 * | | |This flag indicates that Wakeup-I/O interrupt happened. 1482 * | | |Flag is set by hardware while Wakeup-I/O event happen when WKIOPC1IE(CLK_PMUINTC[14])=1. 1483 * | | |Note: Software can clear this bit by writing 1 to it. 1484 * |[15] |WKIOD1IF |Wakeup-I/O GPD group Pin 1 Interrupt Flag 1485 * | | |This flag indicates that Wakeup-I/O interrupt happened. 1486 * | | |Flag is set by hardware while Wakeup-I/O event happen when WKIOPD1IE(CLK_PMUINTC[15])=1. 1487 * | | |Note: Software can clear this bit by writing 1 to it. 1488 */ 1489 __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ 1490 __IO uint32_t AHBCLK0; /*!< [0x0004] AHB Devices Clock Enable Control Register 0 */ 1491 __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ 1492 __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */ 1493 __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ 1494 __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ 1495 __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ 1496 __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */ 1497 __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ 1498 __I uint32_t RESERVE0[3]; 1499 __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ 1500 __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ 1501 __IO uint32_t APBCLK2; /*!< [0x0038] APB Devices Clock Enable Control Register 2 */ 1502 __IO uint32_t CLKDIV5; /*!< [0x003c] Clock Divider Number Register 5 */ 1503 __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ 1504 __IO uint32_t PLLCTL2; /*!< [0x0044] PLL Control Register 2 */ 1505 __IO uint32_t CLKSEL4; /*!< [0x0048] Clock Source Select Control Register 4 */ 1506 __I uint32_t RESERVE1[1]; 1507 __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ 1508 __I uint32_t RESERVE2[1]; 1509 __IO uint32_t AHBCLK1; /*!< [0x0058] AHB Devices Clock Enable Control Register 1 */ 1510 __I uint32_t RESERVE3[1]; 1511 __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ 1512 __I uint32_t RESERVE4[3]; 1513 __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ 1514 __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ 1515 __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */ 1516 __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */ 1517 __IO uint32_t STOPREQ; /*!< [0x0080] Clock Stop Request Register */ 1518 __I uint32_t STOPACK; /*!< [0x0084] Clock Stop Acknowledge Register */ 1519 __I uint32_t RESERVE5[2]; 1520 __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ 1521 __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ 1522 __IO uint32_t PMUWKCTL; /*!< [0x0098] Power Manager Wake-up Control Register */ 1523 __IO uint32_t PWDBCTL; /*!< [0x009c] GPIO Pin WKIO De-bounce Control Register */ 1524 __IO uint32_t PAPWCTL; /*!< [0x00a0] GPA Pin WKIO Control Register */ 1525 __IO uint32_t PBPWCTL; /*!< [0x00a4] GPB Pin WKIO Control Register */ 1526 __IO uint32_t PCPWCTL; /*!< [0x00a8] GPC Pin WKIO Control Register */ 1527 __IO uint32_t PDPWCTL; /*!< [0x00ac] GPD Pin WKIO Control Register */ 1528 __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Power-down Control Register */ 1529 __I uint32_t RESERVE6[3]; 1530 __IO uint32_t PMUINTC; /*!< [0x00c0] Power Manager Interrupt Control Register */ 1531 __IO uint32_t PMUINTS; /*!< [0x00c4] Power Manager Interrupt Status Register */ 1532 1533 } CLK_T; 1534 1535 /** 1536 @addtogroup CLK_CONST CLK Bit Field Definition 1537 Constant Definitions for CLK Controller 1538 @{ */ 1539 1540 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ 1541 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ 1542 1543 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ 1544 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ 1545 1546 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ 1547 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ 1548 1549 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ 1550 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ 1551 1552 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ 1553 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ 1554 1555 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ 1556 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ 1557 1558 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ 1559 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ 1560 1561 #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ 1562 #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ 1563 1564 #define CLK_PWRCTL_HIRC48MSTBS_Pos (14) /*!< CLK_T::PWRCTL: HIRC48MSTBS Position */ 1565 #define CLK_PWRCTL_HIRC48MSTBS_Msk (0x3ul << CLK_PWRCTL_HIRC48MSTBS_Pos) /*!< CLK_T::PWRCTL: HIRC48MSTBS Mask */ 1566 1567 #define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */ 1568 #define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */ 1569 1570 #define CLK_PWRCTL_HIRC48MEN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48MEN Position */ 1571 #define CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos) /*!< CLK_T::PWRCTL: HIRC48MEN Mask */ 1572 1573 #define CLK_PWRCTL_HXTGAIN_Pos (20) /*!< CLK_T::PWRCTL: HXTGAIN Position */ 1574 #define CLK_PWRCTL_HXTGAIN_Msk (0x7ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ 1575 1576 #define CLK_PWRCTL_MIRCSTBS_Pos (24) /*!< CLK_T::PWRCTL: MIRCSTBS Position */ 1577 #define CLK_PWRCTL_MIRCSTBS_Msk (0x3ul << CLK_PWRCTL_MIRCSTBS_Pos) /*!< CLK_T::PWRCTL: MIRCSTBS Mask */ 1578 1579 #define CLK_PWRCTL_MIRCEN_Pos (26) /*!< CLK_T::PWRCTL: MIRCEN Position */ 1580 #define CLK_PWRCTL_MIRCEN_Msk (0x1ul << CLK_PWRCTL_MIRCEN_Pos) /*!< CLK_T::PWRCTL: MIRCEN Mask */ 1581 1582 #define CLK_PWRCTL_MIRCFSEL_Pos (28) /*!< CLK_T::PWRCTL: MIRCFSEL Position */ 1583 #define CLK_PWRCTL_MIRCFSEL_Msk (0x7ul << CLK_PWRCTL_MIRCFSEL_Pos) /*!< CLK_T::PWRCTL: MIRCFSEL Mask */ 1584 1585 #define CLK_PWRCTL_HXTMD_Pos (31) /*!< CLK_T::PWRCTL: HXTMD Position */ 1586 #define CLK_PWRCTL_HXTMD_Msk (0x1ul << CLK_PWRCTL_HXTMD_Pos) /*!< CLK_T::PWRCTL: HXTMD Mask */ 1587 1588 #define CLK_AHBCLK0_PDMA0CKEN_Pos (1) /*!< CLK_T::AHBCLK0: PDMA0CKEN Position */ 1589 #define CLK_AHBCLK0_PDMA0CKEN_Msk (0x1ul << CLK_AHBCLK0_PDMA0CKEN_Pos) /*!< CLK_T::AHBCLK0: PDMA0CKEN Mask */ 1590 1591 #define CLK_AHBCLK0_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK0: ISPCKEN Position */ 1592 #define CLK_AHBCLK0_ISPCKEN_Msk (0x1ul << CLK_AHBCLK0_ISPCKEN_Pos) /*!< CLK_T::AHBCLK0: ISPCKEN Mask */ 1593 1594 #define CLK_AHBCLK0_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK0: EBICKEN Position */ 1595 #define CLK_AHBCLK0_EBICKEN_Msk (0x1ul << CLK_AHBCLK0_EBICKEN_Pos) /*!< CLK_T::AHBCLK0: EBICKEN Mask */ 1596 1597 #define CLK_AHBCLK0_STCKEN_Pos (4) /*!< CLK_T::AHBCLK0: STCKEN Position */ 1598 #define CLK_AHBCLK0_STCKEN_Msk (0x1ul << CLK_AHBCLK0_STCKEN_Pos) /*!< CLK_T::AHBCLK0: STCKEN Mask */ 1599 1600 #define CLK_AHBCLK0_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK0: CRCCKEN Position */ 1601 #define CLK_AHBCLK0_CRCCKEN_Msk (0x1ul << CLK_AHBCLK0_CRCCKEN_Pos) /*!< CLK_T::AHBCLK0: CRCCKEN Mask */ 1602 1603 #define CLK_AHBCLK0_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK0: CRPTCKEN Position */ 1604 #define CLK_AHBCLK0_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK0_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK0: CRPTCKEN Mask */ 1605 1606 #define CLK_AHBCLK0_KSCKEN_Pos (13) /*!< CLK_T::AHBCLK0: KSCKEN Position */ 1607 #define CLK_AHBCLK0_KSCKEN_Msk (0x1ul << CLK_AHBCLK0_KSCKEN_Pos) /*!< CLK_T::AHBCLK0: KSCKEN Mask */ 1608 1609 #define CLK_AHBCLK0_RMCIDLE_Pos (15) /*!< CLK_T::AHBCLK0: RMCIDLE Position */ 1610 #define CLK_AHBCLK0_RMCIDLE_Msk (0x1ul << CLK_AHBCLK0_RMCIDLE_Pos) /*!< CLK_T::AHBCLK0: RMCIDLE Mask */ 1611 1612 #define CLK_AHBCLK0_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK0: USBHCKEN Position */ 1613 #define CLK_AHBCLK0_USBHCKEN_Msk (0x1ul << CLK_AHBCLK0_USBHCKEN_Pos) /*!< CLK_T::AHBCLK0: USBHCKEN Mask */ 1614 1615 #define CLK_AHBCLK0_RMCFDIS_Pos (23) /*!< CLK_T::AHBCLK0: RMCFDIS Position */ 1616 #define CLK_AHBCLK0_RMCFDIS_Msk (0x1ul << CLK_AHBCLK0_RMCFDIS_Pos) /*!< CLK_T::AHBCLK0: RMCFDIS Mask */ 1617 1618 #define CLK_AHBCLK0_GPACKEN_Pos (24) /*!< CLK_T::AHBCLK0: GPACKEN Position */ 1619 #define CLK_AHBCLK0_GPACKEN_Msk (0x1ul << CLK_AHBCLK0_GPACKEN_Pos) /*!< CLK_T::AHBCLK0: GPACKEN Mask */ 1620 1621 #define CLK_AHBCLK0_GPBCKEN_Pos (25) /*!< CLK_T::AHBCLK0: GPBCKEN Position */ 1622 #define CLK_AHBCLK0_GPBCKEN_Msk (0x1ul << CLK_AHBCLK0_GPBCKEN_Pos) /*!< CLK_T::AHBCLK0: GPBCKEN Mask */ 1623 1624 #define CLK_AHBCLK0_GPCCKEN_Pos (26) /*!< CLK_T::AHBCLK0: GPCCKEN Position */ 1625 #define CLK_AHBCLK0_GPCCKEN_Msk (0x1ul << CLK_AHBCLK0_GPCCKEN_Pos) /*!< CLK_T::AHBCLK0: GPCCKEN Mask */ 1626 1627 #define CLK_AHBCLK0_GPDCKEN_Pos (27) /*!< CLK_T::AHBCLK0: GPDCKEN Position */ 1628 #define CLK_AHBCLK0_GPDCKEN_Msk (0x1ul << CLK_AHBCLK0_GPDCKEN_Pos) /*!< CLK_T::AHBCLK0: GPDCKEN Mask */ 1629 1630 #define CLK_AHBCLK0_GPECKEN_Pos (28) /*!< CLK_T::AHBCLK0: GPECKEN Position */ 1631 #define CLK_AHBCLK0_GPECKEN_Msk (0x1ul << CLK_AHBCLK0_GPECKEN_Pos) /*!< CLK_T::AHBCLK0: GPECKEN Mask */ 1632 1633 #define CLK_AHBCLK0_GPFCKEN_Pos (29) /*!< CLK_T::AHBCLK0: GPFCKEN Position */ 1634 #define CLK_AHBCLK0_GPFCKEN_Msk (0x1ul << CLK_AHBCLK0_GPFCKEN_Pos) /*!< CLK_T::AHBCLK0: GPFCKEN Mask */ 1635 1636 #define CLK_AHBCLK0_GPGCKEN_Pos (30) /*!< CLK_T::AHBCLK0: GPGCKEN Position */ 1637 #define CLK_AHBCLK0_GPGCKEN_Msk (0x1ul << CLK_AHBCLK0_GPGCKEN_Pos) /*!< CLK_T::AHBCLK0: GPGCKEN Mask */ 1638 1639 #define CLK_AHBCLK0_GPHCKEN_Pos (31) /*!< CLK_T::AHBCLK0: GPHCKEN Position */ 1640 #define CLK_AHBCLK0_GPHCKEN_Msk (0x1ul << CLK_AHBCLK0_GPHCKEN_Pos) /*!< CLK_T::AHBCLK0: GPHCKEN Mask */ 1641 1642 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ 1643 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ 1644 1645 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ 1646 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ 1647 1648 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ 1649 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ 1650 1651 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ 1652 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ 1653 1654 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ 1655 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ 1656 1657 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ 1658 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ 1659 1660 #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ 1661 #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ 1662 1663 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ 1664 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ 1665 1666 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ 1667 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ 1668 1669 #define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ 1670 #define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ 1671 1672 #define CLK_APBCLK0_I2C3CKEN_Pos (11) /*!< CLK_T::APBCLK0: I2C3CKEN Position */ 1673 #define CLK_APBCLK0_I2C3CKEN_Msk (0x1ul << CLK_APBCLK0_I2C3CKEN_Pos) /*!< CLK_T::APBCLK0: I2C3CKEN Mask */ 1674 1675 #define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ 1676 #define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ 1677 1678 #define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ 1679 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ 1680 1681 #define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ 1682 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ 1683 1684 #define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ 1685 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ 1686 1687 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ 1688 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ 1689 1690 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ 1691 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ 1692 1693 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ 1694 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ 1695 1696 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ 1697 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ 1698 1699 #define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ 1700 #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ 1701 1702 #define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ 1703 #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ 1704 1705 #define CLK_APBCLK0_UART6CKEN_Pos (22) /*!< CLK_T::APBCLK0: UART6CKEN Position */ 1706 #define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos) /*!< CLK_T::APBCLK0: UART6CKEN Mask */ 1707 1708 #define CLK_APBCLK0_UART7CKEN_Pos (23) /*!< CLK_T::APBCLK0: UART7CKEN Position */ 1709 #define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos) /*!< CLK_T::APBCLK0: UART7CKEN Mask */ 1710 1711 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ 1712 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ 1713 1714 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ 1715 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ 1716 1717 #define CLK_APBCLK0_EADC0CKEN_Pos (28) /*!< CLK_T::APBCLK0: EADC0CKEN Position */ 1718 #define CLK_APBCLK0_EADC0CKEN_Msk (0x1ul << CLK_APBCLK0_EADC0CKEN_Pos) /*!< CLK_T::APBCLK0: EADC0CKEN Mask */ 1719 1720 #define CLK_APBCLK0_TRNGCKEN_Pos (31) /*!< CLK_T::APBCLK0: TRNGCKEN Position */ 1721 #define CLK_APBCLK0_TRNGCKEN_Msk (0x1ul << CLK_APBCLK0_TRNGCKEN_Pos) /*!< CLK_T::APBCLK0: TRNGCKEN Mask */ 1722 1723 #define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ 1724 #define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ 1725 1726 #define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ 1727 #define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ 1728 1729 #define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ 1730 #define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ 1731 1732 #define CLK_APBCLK1_WWDTCKEN_Pos (11) /*!< CLK_T::APBCLK1: WWDTCKEN Position */ 1733 #define CLK_APBCLK1_WWDTCKEN_Msk (0x1ul << CLK_APBCLK1_WWDTCKEN_Pos) /*!< CLK_T::APBCLK1: WWDTCKEN Mask */ 1734 1735 #define CLK_APBCLK1_DACEN_Pos (12) /*!< CLK_T::APBCLK1: DACEN Position */ 1736 #define CLK_APBCLK1_DACEN_Msk (0x1ul << CLK_APBCLK1_DACEN_Pos) /*!< CLK_T::APBCLK1: DACEN Mask */ 1737 1738 #define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ 1739 #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ 1740 1741 #define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ 1742 #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ 1743 1744 #define CLK_APBCLK1_EQEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: EQEI0CKEN Position */ 1745 #define CLK_APBCLK1_EQEI0CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI0CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI0CKEN Mask */ 1746 1747 #define CLK_APBCLK1_EQEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: EQEI1CKEN Position */ 1748 #define CLK_APBCLK1_EQEI1CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI1CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI1CKEN Mask */ 1749 1750 #define CLK_APBCLK1_TKCKEN_Pos (25) /*!< CLK_T::APBCLK1: TKCKEN Position */ 1751 #define CLK_APBCLK1_TKCKEN_Msk (0x1ul << CLK_APBCLK1_TKCKEN_Pos) /*!< CLK_T::APBCLK1: TKCKEN Mask */ 1752 1753 #define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ 1754 #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ 1755 1756 #define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ 1757 #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ 1758 1759 #define CLK_CLKSEL0_HCLK0SEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLK0SEL Position */ 1760 #define CLK_CLKSEL0_HCLK0SEL_Msk (0x7ul << CLK_CLKSEL0_HCLK0SEL_Pos) /*!< CLK_T::CLKSEL0: HCLK0SEL Mask */ 1761 1762 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ 1763 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ 1764 1765 #define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBSEL Position */ 1766 #define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: USBSEL Mask */ 1767 1768 #define CLK_CLKSEL0_EADC0SEL_Pos (10) /*!< CLK_T::CLKSEL0: EADC0SEL Position */ 1769 #define CLK_CLKSEL0_EADC0SEL_Msk (0x3ul << CLK_CLKSEL0_EADC0SEL_Pos) /*!< CLK_T::CLKSEL0: EADC0SEL Mask */ 1770 1771 #define CLK_CLKSEL0_HCLK1SEL_Pos (12) /*!< CLK_T::CLKSEL0: HCLK1SEL Position */ 1772 #define CLK_CLKSEL0_HCLK1SEL_Msk (0x7ul << CLK_CLKSEL0_HCLK1SEL_Pos) /*!< CLK_T::CLKSEL0: HCLK1SEL Mask */ 1773 1774 #define CLK_CLKSEL0_CANFD0SEL_Pos (24) /*!< CLK_T::CLKSEL0: CANFD0SEL Position */ 1775 #define CLK_CLKSEL0_CANFD0SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD0SEL Mask */ 1776 1777 #define CLK_CLKSEL0_CANFD1SEL_Pos (26) /*!< CLK_T::CLKSEL0: CANFD1SEL Position */ 1778 #define CLK_CLKSEL0_CANFD1SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD1SEL Mask */ 1779 1780 #define CLK_CLKSEL1_CLKOSEL_Pos (4) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ 1781 #define CLK_CLKSEL1_CLKOSEL_Msk (0xful << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ 1782 1783 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ 1784 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ 1785 1786 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ 1787 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ 1788 1789 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ 1790 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ 1791 1792 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ 1793 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ 1794 1795 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ 1796 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ 1797 1798 #define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ 1799 #define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ 1800 1801 #define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ 1802 #define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ 1803 1804 #define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ 1805 #define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ 1806 1807 #define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ 1808 #define CLK_CLKSEL2_SPI0SEL_Msk (0x7ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ 1809 1810 #define CLK_CLKSEL2_TKSEL_Pos (7) /*!< CLK_T::CLKSEL2: TKSEL Position */ 1811 #define CLK_CLKSEL2_TKSEL_Msk (0x1ul << CLK_CLKSEL2_TKSEL_Pos) /*!< CLK_T::CLKSEL2: TKSEL Mask */ 1812 1813 #define CLK_CLKSEL2_SPI1SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ 1814 #define CLK_CLKSEL2_SPI1SEL_Msk (0x7ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ 1815 1816 #define CLK_CLKSEL3_PWM0SEL_Pos (6) /*!< CLK_T::CLKSEL3: PWM0SEL Position */ 1817 #define CLK_CLKSEL3_PWM0SEL_Msk (0x1ul << CLK_CLKSEL3_PWM0SEL_Pos) /*!< CLK_T::CLKSEL3: PWM0SEL Mask */ 1818 1819 #define CLK_CLKSEL3_PWM1SEL_Pos (7) /*!< CLK_T::CLKSEL3: PWM1SEL Position */ 1820 #define CLK_CLKSEL3_PWM1SEL_Msk (0x1ul << CLK_CLKSEL3_PWM1SEL_Pos) /*!< CLK_T::CLKSEL3: PWM1SEL Mask */ 1821 1822 #define CLK_CLKSEL3_SPI2SEL_Pos (8) /*!< CLK_T::CLKSEL3: SPI2SEL Position */ 1823 #define CLK_CLKSEL3_SPI2SEL_Msk (0x7ul << CLK_CLKSEL3_SPI2SEL_Pos) /*!< CLK_T::CLKSEL3: SPI2SEL Mask */ 1824 1825 #define CLK_CLKSEL3_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL3: SPI3SEL Position */ 1826 #define CLK_CLKSEL3_SPI3SEL_Msk (0x7ul << CLK_CLKSEL3_SPI3SEL_Pos) /*!< CLK_T::CLKSEL3: SPI3SEL Mask */ 1827 1828 #define CLK_CLKDIV0_HCLK0DIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLK0DIV Position */ 1829 #define CLK_CLKDIV0_HCLK0DIV_Msk (0xful << CLK_CLKDIV0_HCLK0DIV_Pos) /*!< CLK_T::CLKDIV0: HCLK0DIV Mask */ 1830 1831 #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ 1832 #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ 1833 1834 #define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ 1835 #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ 1836 1837 #define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ 1838 #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ 1839 1840 #define CLK_CLKDIV0_EADC0DIV_Pos (16) /*!< CLK_T::CLKDIV0: EADC0DIV Position */ 1841 #define CLK_CLKDIV0_EADC0DIV_Msk (0xfful << CLK_CLKDIV0_EADC0DIV_Pos) /*!< CLK_T::CLKDIV0: EADC0DIV Mask */ 1842 1843 #define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ 1844 #define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ 1845 1846 #define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ 1847 #define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ 1848 1849 #define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ 1850 #define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ 1851 1852 #define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ 1853 #define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ 1854 1855 #define CLK_CLKDIV4_UART6DIV_Pos (16) /*!< CLK_T::CLKDIV4: UART6DIV Position */ 1856 #define CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLK_T::CLKDIV4: UART6DIV Mask */ 1857 1858 #define CLK_CLKDIV4_UART7DIV_Pos (20) /*!< CLK_T::CLKDIV4: UART7DIV Position */ 1859 #define CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLK_T::CLKDIV4: UART7DIV Mask */ 1860 1861 #define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ 1862 #define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ 1863 1864 #define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ 1865 #define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ 1866 1867 #define CLK_APBCLK2_ACMP2CKEN_Pos (7) /*!< CLK_T::APBCLK2: ACMP2CKEN Position */ 1868 #define CLK_APBCLK2_ACMP2CKEN_Msk (0x1ul << CLK_APBCLK2_ACMP2CKEN_Pos) /*!< CLK_T::APBCLK2: ACMP2CKEN Mask */ 1869 1870 #define CLK_APBCLK2_PWM0CKEN_Pos (8) /*!< CLK_T::APBCLK2: PWM0CKEN Position */ 1871 #define CLK_APBCLK2_PWM0CKEN_Msk (0x1ul << CLK_APBCLK2_PWM0CKEN_Pos) /*!< CLK_T::APBCLK2: PWM0CKEN Mask */ 1872 1873 #define CLK_APBCLK2_PWM1CKEN_Pos (9) /*!< CLK_T::APBCLK2: PWM1CKEN Position */ 1874 #define CLK_APBCLK2_PWM1CKEN_Msk (0x1ul << CLK_APBCLK2_PWM1CKEN_Pos) /*!< CLK_T::APBCLK2: PWM1CKEN Mask */ 1875 1876 #define CLK_APBCLK2_UTCPD0CKEN_Pos (15) /*!< CLK_T::APBCLK2: UTCPD0CKEN Position */ 1877 #define CLK_APBCLK2_UTCPD0CKEN_Msk (0x1ul << CLK_APBCLK2_UTCPD0CKEN_Pos) /*!< CLK_T::APBCLK2: UTCPD0CKEN Mask */ 1878 1879 #define CLK_CLKDIV5_CANFD0DIV_Pos (0) /*!< CLK_T::CLKDIV5: CANFD0DIV Position */ 1880 #define CLK_CLKDIV5_CANFD0DIV_Msk (0xful << CLK_CLKDIV5_CANFD0DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD0DIV Mask */ 1881 1882 #define CLK_CLKDIV5_CANFD1DIV_Pos (4) /*!< CLK_T::CLKDIV5: CANFD1DIV Position */ 1883 #define CLK_CLKDIV5_CANFD1DIV_Msk (0xful << CLK_CLKDIV5_CANFD1DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD1DIV Mask */ 1884 1885 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ 1886 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ 1887 1888 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ 1889 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ 1890 1891 #define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ 1892 #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ 1893 1894 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ 1895 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ 1896 1897 #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ 1898 #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ 1899 1900 #define CLK_PLLCTL2_FBDIV_Pos (0) /*!< CLK_T::PLLCTL2: FBDIV Position */ 1901 #define CLK_PLLCTL2_FBDIV_Msk (0x1fful << CLK_PLLCTL2_FBDIV_Pos) /*!< CLK_T::PLLCTL2: FBDIV Mask */ 1902 1903 #define CLK_PLLCTL2_INDIV_Pos (9) /*!< CLK_T::PLLCTL2: INDIV Position */ 1904 #define CLK_PLLCTL2_INDIV_Msk (0x1ful << CLK_PLLCTL2_INDIV_Pos) /*!< CLK_T::PLLCTL2: INDIV Mask */ 1905 1906 #define CLK_PLLCTL2_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL2: OUTDIV Position */ 1907 #define CLK_PLLCTL2_OUTDIV_Msk (0x3ul << CLK_PLLCTL2_OUTDIV_Pos) /*!< CLK_T::PLLCTL2: OUTDIV Mask */ 1908 1909 #define CLK_PLLCTL2_FRDIV_Pos (16) /*!< CLK_T::PLLCTL2: FRDIV Position */ 1910 #define CLK_PLLCTL2_FRDIV_Msk (0xffful << CLK_PLLCTL2_FRDIV_Pos) /*!< CLK_T::PLLCTL2: FRDIV Mask */ 1911 1912 #define CLK_CLKSEL4_UART0SEL_Pos (0) /*!< CLK_T::CLKSEL4: UART0SEL Position */ 1913 #define CLK_CLKSEL4_UART0SEL_Msk (0x7ul << CLK_CLKSEL4_UART0SEL_Pos) /*!< CLK_T::CLKSEL4: UART0SEL Mask */ 1914 1915 #define CLK_CLKSEL4_UART1SEL_Pos (4) /*!< CLK_T::CLKSEL4: UART1SEL Position */ 1916 #define CLK_CLKSEL4_UART1SEL_Msk (0x7ul << CLK_CLKSEL4_UART1SEL_Pos) /*!< CLK_T::CLKSEL4: UART1SEL Mask */ 1917 1918 #define CLK_CLKSEL4_UART2SEL_Pos (8) /*!< CLK_T::CLKSEL4: UART2SEL Position */ 1919 #define CLK_CLKSEL4_UART2SEL_Msk (0x7ul << CLK_CLKSEL4_UART2SEL_Pos) /*!< CLK_T::CLKSEL4: UART2SEL Mask */ 1920 1921 #define CLK_CLKSEL4_UART3SEL_Pos (12) /*!< CLK_T::CLKSEL4: UART3SEL Position */ 1922 #define CLK_CLKSEL4_UART3SEL_Msk (0x7ul << CLK_CLKSEL4_UART3SEL_Pos) /*!< CLK_T::CLKSEL4: UART3SEL Mask */ 1923 1924 #define CLK_CLKSEL4_UART4SEL_Pos (16) /*!< CLK_T::CLKSEL4: UART4SEL Position */ 1925 #define CLK_CLKSEL4_UART4SEL_Msk (0x7ul << CLK_CLKSEL4_UART4SEL_Pos) /*!< CLK_T::CLKSEL4: UART4SEL Mask */ 1926 1927 #define CLK_CLKSEL4_UART5SEL_Pos (20) /*!< CLK_T::CLKSEL4: UART5SEL Position */ 1928 #define CLK_CLKSEL4_UART5SEL_Msk (0x7ul << CLK_CLKSEL4_UART5SEL_Pos) /*!< CLK_T::CLKSEL4: UART5SEL Mask */ 1929 1930 #define CLK_CLKSEL4_UART6SEL_Pos (24) /*!< CLK_T::CLKSEL4: UART6SEL Position */ 1931 #define CLK_CLKSEL4_UART6SEL_Msk (0x7ul << CLK_CLKSEL4_UART6SEL_Pos) /*!< CLK_T::CLKSEL4: UART6SEL Mask */ 1932 1933 #define CLK_CLKSEL4_UART7SEL_Pos (28) /*!< CLK_T::CLKSEL4: UART7SEL Position */ 1934 #define CLK_CLKSEL4_UART7SEL_Msk (0x7ul << CLK_CLKSEL4_UART7SEL_Pos) /*!< CLK_T::CLKSEL4: UART7SEL Mask */ 1935 1936 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ 1937 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ 1938 1939 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ 1940 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ 1941 1942 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ 1943 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ 1944 1945 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ 1946 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ 1947 1948 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ 1949 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ 1950 1951 #define CLK_STATUS_MIRCSTB_Pos (5) /*!< CLK_T::STATUS: MIRCSTB Position */ 1952 #define CLK_STATUS_MIRCSTB_Msk (0x1ul << CLK_STATUS_MIRCSTB_Pos) /*!< CLK_T::STATUS: MIRCSTB Mask */ 1953 1954 #define CLK_STATUS_HIRC48MSTB_Pos (6) /*!< CLK_T::STATUS: HIRC48MSTB Position */ 1955 #define CLK_STATUS_HIRC48MSTB_Msk (0x1ul << CLK_STATUS_HIRC48MSTB_Pos) /*!< CLK_T::STATUS: HIRC48MSTB Mask */ 1956 1957 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ 1958 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ 1959 1960 #define CLK_AHBCLK1_CANRAM0EN_Pos (16) /*!< CLK_T::AHBCLK1: CANRAM0EN Position */ 1961 #define CLK_AHBCLK1_CANRAM0EN_Msk (0x1ul << CLK_AHBCLK1_CANRAM0EN_Pos) /*!< CLK_T::AHBCLK1: CANRAM0EN Mask */ 1962 1963 #define CLK_AHBCLK1_CANRAM1EN_Pos (17) /*!< CLK_T::AHBCLK1: CANRAM1EN Position */ 1964 #define CLK_AHBCLK1_CANRAM1EN_Msk (0x1ul << CLK_AHBCLK1_CANRAM1EN_Pos) /*!< CLK_T::AHBCLK1: CANRAM1EN Mask */ 1965 1966 #define CLK_AHBCLK1_CANFD0CKEN_Pos (20) /*!< CLK_T::AHBCLK1: CANFD0CKEN Position */ 1967 #define CLK_AHBCLK1_CANFD0CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD0CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD0CKEN Mask */ 1968 1969 #define CLK_AHBCLK1_CANFD1CKEN_Pos (21) /*!< CLK_T::AHBCLK1: CANFD1CKEN Position */ 1970 #define CLK_AHBCLK1_CANFD1CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD1CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD1CKEN Mask */ 1971 1972 #define CLK_AHBCLK1_HCLK1EN_Pos (28) /*!< CLK_T::AHBCLK1: HCLK1EN Position */ 1973 #define CLK_AHBCLK1_HCLK1EN_Msk (0x1ul << CLK_AHBCLK1_HCLK1EN_Pos) /*!< CLK_T::AHBCLK1: HCLK1EN Mask */ 1974 1975 #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ 1976 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ 1977 1978 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ 1979 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ 1980 1981 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ 1982 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ 1983 1984 #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ 1985 #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ 1986 1987 #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ 1988 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ 1989 1990 #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ 1991 #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ 1992 1993 #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ 1994 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ 1995 1996 #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ 1997 #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ 1998 1999 #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ 2000 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ 2001 2002 #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ 2003 #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ 2004 2005 #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ 2006 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ 2007 2008 #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ 2009 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ 2010 2011 #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ 2012 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ 2013 2014 #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ 2015 #define CLK_CDUPB_UPERBD_Msk (0x7fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ 2016 2017 #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ 2018 #define CLK_CDLOWB_LOWERBD_Msk (0x7fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ 2019 2020 #define CLK_STOPREQ_CANFD0REQ_Pos (0) /*!< CLK_T::STOPREQ: CANFD0REQ Position */ 2021 #define CLK_STOPREQ_CANFD0REQ_Msk (0x1ul << CLK_STOPREQ_CANFD0REQ_Pos) /*!< CLK_T::STOPREQ: CANFD0REQ Mask */ 2022 2023 #define CLK_STOPREQ_CANFD1REQ_Pos (1) /*!< CLK_T::STOPREQ: CANFD1REQ Position */ 2024 #define CLK_STOPREQ_CANFD1REQ_Msk (0x1ul << CLK_STOPREQ_CANFD1REQ_Pos) /*!< CLK_T::STOPREQ: CANFD1REQ Mask */ 2025 2026 #define CLK_STOPACK_CANFD0ACK_Pos (0) /*!< CLK_T::STOPACK: CANFD0ACK Position */ 2027 #define CLK_STOPACK_CANFD0ACK_Msk (0x1ul << CLK_STOPACK_CANFD0ACK_Pos) /*!< CLK_T::STOPACK: CANFD0ACK Mask */ 2028 2029 #define CLK_STOPACK_CANFD1ACK_Pos (1) /*!< CLK_T::STOPACK: CANFD1ACK Position */ 2030 #define CLK_STOPACK_CANFD1ACK_Msk (0x1ul << CLK_STOPACK_CANFD1ACK_Pos) /*!< CLK_T::STOPACK: CANFD1ACK Mask */ 2031 2032 #define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ 2033 #define CLK_PMUCTL_PDMSEL_Msk (0xful << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ 2034 2035 #define CLK_PMUCTL_SRETSEL_Pos (8) /*!< CLK_T::PMUCTL: SRETSEL Position */ 2036 #define CLK_PMUCTL_SRETSEL_Msk (0x7ul << CLK_PMUCTL_SRETSEL_Pos) /*!< CLK_T::PMUCTL: SRETSEL Mask */ 2037 2038 #define CLK_PMUCTL_LSRETSEL_Pos (16) /*!< CLK_T::PMUCTL: LSRETSEL Position */ 2039 #define CLK_PMUCTL_LSRETSEL_Msk (0x1ul << CLK_PMUCTL_LSRETSEL_Pos) /*!< CLK_T::PMUCTL: LSRETSEL Mask */ 2040 2041 #define CLK_PMUCTL_CARETDIS_Pos (20) /*!< CLK_T::PMUCTL: CARETDIS Position */ 2042 #define CLK_PMUCTL_CARETDIS_Msk (0x1ul << CLK_PMUCTL_CARETDIS_Pos) /*!< CLK_T::PMUCTL: CARETDIS Mask */ 2043 2044 #define CLK_PMUSTS_WKPIN0_Pos (0) /*!< CLK_T::PMUSTS: WKPIN0 Position */ 2045 #define CLK_PMUSTS_WKPIN0_Msk (0x1ul << CLK_PMUSTS_WKPIN0_Pos) /*!< CLK_T::PMUSTS: WKPIN0 Mask */ 2046 2047 #define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ 2048 #define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ 2049 2050 #define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ 2051 #define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ 2052 2053 #define CLK_PMUSTS_WKPIN1_Pos (3) /*!< CLK_T::PMUSTS: WKPIN1 Position */ 2054 #define CLK_PMUSTS_WKPIN1_Msk (0x1ul << CLK_PMUSTS_WKPIN1_Pos) /*!< CLK_T::PMUSTS: WKPIN1 Mask */ 2055 2056 #define CLK_PMUSTS_WKPIN2_Pos (4) /*!< CLK_T::PMUSTS: WKPIN2 Position */ 2057 #define CLK_PMUSTS_WKPIN2_Msk (0x1ul << CLK_PMUSTS_WKPIN2_Pos) /*!< CLK_T::PMUSTS: WKPIN2 Mask */ 2058 2059 #define CLK_PMUSTS_WKPIN3_Pos (5) /*!< CLK_T::PMUSTS: WKPIN3 Position */ 2060 #define CLK_PMUSTS_WKPIN3_Msk (0x1ul << CLK_PMUSTS_WKPIN3_Pos) /*!< CLK_T::PMUSTS: WKPIN3 Mask */ 2061 2062 #define CLK_PMUSTS_WKPIN4_Pos (6) /*!< CLK_T::PMUSTS: WKPIN4 Position */ 2063 #define CLK_PMUSTS_WKPIN4_Msk (0x1ul << CLK_PMUSTS_WKPIN4_Pos) /*!< CLK_T::PMUSTS: WKPIN4 Mask */ 2064 2065 #define CLK_PMUSTS_WKPIN5_Pos (7) /*!< CLK_T::PMUSTS: WKPIN5 Position */ 2066 #define CLK_PMUSTS_WKPIN5_Msk (0x1ul << CLK_PMUSTS_WKPIN5_Pos) /*!< CLK_T::PMUSTS: WKPIN5 Mask */ 2067 2068 #define CLK_PMUSTS_GPAWK0_Pos (8) /*!< CLK_T::PMUSTS: GPAWK0 Position */ 2069 #define CLK_PMUSTS_GPAWK0_Msk (0x1ul << CLK_PMUSTS_GPAWK0_Pos) /*!< CLK_T::PMUSTS: GPAWK0 Mask */ 2070 2071 #define CLK_PMUSTS_GPBWK0_Pos (9) /*!< CLK_T::PMUSTS: GPBWK0 Position */ 2072 #define CLK_PMUSTS_GPBWK0_Msk (0x1ul << CLK_PMUSTS_GPBWK0_Pos) /*!< CLK_T::PMUSTS: GPBWK0 Mask */ 2073 2074 #define CLK_PMUSTS_GPCWK0_Pos (10) /*!< CLK_T::PMUSTS: GPCWK0 Position */ 2075 #define CLK_PMUSTS_GPCWK0_Msk (0x1ul << CLK_PMUSTS_GPCWK0_Pos) /*!< CLK_T::PMUSTS: GPCWK0 Mask */ 2076 2077 #define CLK_PMUSTS_GPDWK0_Pos (11) /*!< CLK_T::PMUSTS: GPDWK0 Position */ 2078 #define CLK_PMUSTS_GPDWK0_Msk (0x1ul << CLK_PMUSTS_GPDWK0_Pos) /*!< CLK_T::PMUSTS: GPDWK0 Mask */ 2079 2080 #define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ 2081 #define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ 2082 2083 #define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ 2084 #define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ 2085 2086 #define CLK_PMUSTS_RSTWK_Pos (15) /*!< CLK_T::PMUSTS: RSTWK Position */ 2087 #define CLK_PMUSTS_RSTWK_Msk (0x1ul << CLK_PMUSTS_RSTWK_Pos) /*!< CLK_T::PMUSTS: RSTWK Mask */ 2088 2089 #define CLK_PMUSTS_ACMPWK0_Pos (16) /*!< CLK_T::PMUSTS: ACMPWK0 Position */ 2090 #define CLK_PMUSTS_ACMPWK0_Msk (0x1ul << CLK_PMUSTS_ACMPWK0_Pos) /*!< CLK_T::PMUSTS: ACMPWK0 Mask */ 2091 2092 #define CLK_PMUSTS_ACMPWK1_Pos (17) /*!< CLK_T::PMUSTS: ACMPWK1 Position */ 2093 #define CLK_PMUSTS_ACMPWK1_Msk (0x1ul << CLK_PMUSTS_ACMPWK1_Pos) /*!< CLK_T::PMUSTS: ACMPWK1 Mask */ 2094 2095 #define CLK_PMUSTS_ACMPWK2_Pos (18) /*!< CLK_T::PMUSTS: ACMPWK2 Position */ 2096 #define CLK_PMUSTS_ACMPWK2_Msk (0x1ul << CLK_PMUSTS_ACMPWK2_Pos) /*!< CLK_T::PMUSTS: ACMPWK2 Mask */ 2097 2098 #define CLK_PMUSTS_GPAWK1_Pos (24) /*!< CLK_T::PMUSTS: GPAWK1 Position */ 2099 #define CLK_PMUSTS_GPAWK1_Msk (0x1ul << CLK_PMUSTS_GPAWK1_Pos) /*!< CLK_T::PMUSTS: GPAWK1 Mask */ 2100 2101 #define CLK_PMUSTS_GPBWK1_Pos (25) /*!< CLK_T::PMUSTS: GPBWK1 Position */ 2102 #define CLK_PMUSTS_GPBWK1_Msk (0x1ul << CLK_PMUSTS_GPBWK1_Pos) /*!< CLK_T::PMUSTS: GPBWK1 Mask */ 2103 2104 #define CLK_PMUSTS_GPCWK1_Pos (26) /*!< CLK_T::PMUSTS: GPCWK1 Position */ 2105 #define CLK_PMUSTS_GPCWK1_Msk (0x1ul << CLK_PMUSTS_GPCWK1_Pos) /*!< CLK_T::PMUSTS: GPCWK1 Mask */ 2106 2107 #define CLK_PMUSTS_GPDWK1_Pos (27) /*!< CLK_T::PMUSTS: GPDWK1 Position */ 2108 #define CLK_PMUSTS_GPDWK1_Msk (0x1ul << CLK_PMUSTS_GPDWK1_Pos) /*!< CLK_T::PMUSTS: GPDWK1 Mask */ 2109 2110 #define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ 2111 #define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ 2112 2113 #define CLK_PMUWKCTL_WKTMREN_Pos (0) /*!< CLK_T::PMUWKCTL: WKTMREN Position */ 2114 #define CLK_PMUWKCTL_WKTMREN_Msk (0x1ul << CLK_PMUWKCTL_WKTMREN_Pos) /*!< CLK_T::PMUWKCTL: WKTMREN Mask */ 2115 2116 #define CLK_PMUWKCTL_WKTMRMOD_Pos (1) /*!< CLK_T::PMUWKCTL: WKTMRMOD Position */ 2117 #define CLK_PMUWKCTL_WKTMRMOD_Msk (0x1ul << CLK_PMUWKCTL_WKTMRMOD_Pos) /*!< CLK_T::PMUWKCTL: WKTMRMOD Mask */ 2118 2119 #define CLK_PMUWKCTL_ACMPWKEN_Pos (6) /*!< CLK_T::PMUWKCTL: ACMPWKEN Position */ 2120 #define CLK_PMUWKCTL_ACMPWKEN_Msk (0x1ul << CLK_PMUWKCTL_ACMPWKEN_Pos) /*!< CLK_T::PMUWKCTL: ACMPWKEN Mask */ 2121 2122 #define CLK_PMUWKCTL_RTCWKEN_Pos (7) /*!< CLK_T::PMUWKCTL: RTCWKEN Position */ 2123 #define CLK_PMUWKCTL_RTCWKEN_Msk (0x1ul << CLK_PMUWKCTL_RTCWKEN_Pos) /*!< CLK_T::PMUWKCTL: RTCWKEN Mask */ 2124 2125 #define CLK_PMUWKCTL_WKTMRIS_Pos (8) /*!< CLK_T::PMUWKCTL: WKTMRIS Position */ 2126 #define CLK_PMUWKCTL_WKTMRIS_Msk (0xful << CLK_PMUWKCTL_WKTMRIS_Pos) /*!< CLK_T::PMUWKCTL: WKTMRIS Mask */ 2127 2128 #define CLK_PMUWKCTL_WKPINEN0_Pos (16) /*!< CLK_T::PMUWKCTL: WKPINEN0 Position */ 2129 #define CLK_PMUWKCTL_WKPINEN0_Msk (0x3ul << CLK_PMUWKCTL_WKPINEN0_Pos) /*!< CLK_T::PMUWKCTL: WKPINEN0 Mask */ 2130 2131 #define CLK_PMUWKCTL_WKPINEN1_Pos (18) /*!< CLK_T::PMUWKCTL: WKPINEN1 Position */ 2132 #define CLK_PMUWKCTL_WKPINEN1_Msk (0x3ul << CLK_PMUWKCTL_WKPINEN1_Pos) /*!< CLK_T::PMUWKCTL: WKPINEN1 Mask */ 2133 2134 #define CLK_PMUWKCTL_WKPINEN2_Pos (20) /*!< CLK_T::PMUWKCTL: WKPINEN2 Position */ 2135 #define CLK_PMUWKCTL_WKPINEN2_Msk (0x3ul << CLK_PMUWKCTL_WKPINEN2_Pos) /*!< CLK_T::PMUWKCTL: WKPINEN2 Mask */ 2136 2137 #define CLK_PMUWKCTL_WKPINEN3_Pos (22) /*!< CLK_T::PMUWKCTL: WKPINEN3 Position */ 2138 #define CLK_PMUWKCTL_WKPINEN3_Msk (0x3ul << CLK_PMUWKCTL_WKPINEN3_Pos) /*!< CLK_T::PMUWKCTL: WKPINEN3 Mask */ 2139 2140 #define CLK_PMUWKCTL_WKPINEN4_Pos (24) /*!< CLK_T::PMUWKCTL: WKPINEN4 Position */ 2141 #define CLK_PMUWKCTL_WKPINEN4_Msk (0x3ul << CLK_PMUWKCTL_WKPINEN4_Pos) /*!< CLK_T::PMUWKCTL: WKPINEN4 Mask */ 2142 2143 #define CLK_PMUWKCTL_WKPINEN5_Pos (26) /*!< CLK_T::PMUWKCTL: WKPINEN5 Position */ 2144 #define CLK_PMUWKCTL_WKPINEN5_Msk (0x3ul << CLK_PMUWKCTL_WKPINEN5_Pos) /*!< CLK_T::PMUWKCTL: WKPINEN5 Mask */ 2145 2146 #define CLK_PMUWKCTL_DISAUTOC_Pos (31) /*!< CLK_T::PMUWKCTL: DISAUTOC Position */ 2147 #define CLK_PMUWKCTL_DISAUTOC_Msk (0x1ul << CLK_PMUWKCTL_DISAUTOC_Pos) /*!< CLK_T::PMUWKCTL: DISAUTOC Mask */ 2148 2149 #define CLK_PWDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::PWDBCTL: SWKDBCLKSEL Position */ 2150 #define CLK_PWDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_PWDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::PWDBCTL: SWKDBCLKSEL Mask */ 2151 2152 #define CLK_PAPWCTL_WKEN0_Pos (0) /*!< CLK_T::PAPWCTL: WKEN0 Position */ 2153 #define CLK_PAPWCTL_WKEN0_Msk (0x1ul << CLK_PAPWCTL_WKEN0_Pos) /*!< CLK_T::PAPWCTL: WKEN0 Mask */ 2154 2155 #define CLK_PAPWCTL_PRWKEN0_Pos (1) /*!< CLK_T::PAPWCTL: PRWKEN0 Position */ 2156 #define CLK_PAPWCTL_PRWKEN0_Msk (0x1ul << CLK_PAPWCTL_PRWKEN0_Pos) /*!< CLK_T::PAPWCTL: PRWKEN0 Mask */ 2157 2158 #define CLK_PAPWCTL_PFWKEN0_Pos (2) /*!< CLK_T::PAPWCTL: PFWKEN0 Position */ 2159 #define CLK_PAPWCTL_PFWKEN0_Msk (0x1ul << CLK_PAPWCTL_PFWKEN0_Pos) /*!< CLK_T::PAPWCTL: PFWKEN0 Mask */ 2160 2161 #define CLK_PAPWCTL_WKPSEL0_Pos (4) /*!< CLK_T::PAPWCTL: WKPSEL0 Position */ 2162 #define CLK_PAPWCTL_WKPSEL0_Msk (0xful << CLK_PAPWCTL_WKPSEL0_Pos) /*!< CLK_T::PAPWCTL: WKPSEL0 Mask */ 2163 2164 #define CLK_PAPWCTL_DBEN0_Pos (8) /*!< CLK_T::PAPWCTL: DBEN0 Position */ 2165 #define CLK_PAPWCTL_DBEN0_Msk (0x1ul << CLK_PAPWCTL_DBEN0_Pos) /*!< CLK_T::PAPWCTL: DBEN0 Mask */ 2166 2167 #define CLK_PAPWCTL_TRIGM0_Pos (10) /*!< CLK_T::PAPWCTL: TRIGM0 Position */ 2168 #define CLK_PAPWCTL_TRIGM0_Msk (0x1ul << CLK_PAPWCTL_TRIGM0_Pos) /*!< CLK_T::PAPWCTL: TRIGM0 Mask */ 2169 2170 #define CLK_PAPWCTL_NMR0_Pos (11) /*!< CLK_T::PAPWCTL: NMR0 Position */ 2171 #define CLK_PAPWCTL_NMR0_Msk (0x1ul << CLK_PAPWCTL_NMR0_Pos) /*!< CLK_T::PAPWCTL: NMR0 Mask */ 2172 2173 #define CLK_PAPWCTL_WKEN1_Pos (16) /*!< CLK_T::PAPWCTL: WKEN1 Position */ 2174 #define CLK_PAPWCTL_WKEN1_Msk (0x1ul << CLK_PAPWCTL_WKEN1_Pos) /*!< CLK_T::PAPWCTL: WKEN1 Mask */ 2175 2176 #define CLK_PAPWCTL_PRWKEN1_Pos (17) /*!< CLK_T::PAPWCTL: PRWKEN1 Position */ 2177 #define CLK_PAPWCTL_PRWKEN1_Msk (0x1ul << CLK_PAPWCTL_PRWKEN1_Pos) /*!< CLK_T::PAPWCTL: PRWKEN1 Mask */ 2178 2179 #define CLK_PAPWCTL_PFWKEN1_Pos (18) /*!< CLK_T::PAPWCTL: PFWKEN1 Position */ 2180 #define CLK_PAPWCTL_PFWKEN1_Msk (0x1ul << CLK_PAPWCTL_PFWKEN1_Pos) /*!< CLK_T::PAPWCTL: PFWKEN1 Mask */ 2181 2182 #define CLK_PAPWCTL_WKPSEL1_Pos (20) /*!< CLK_T::PAPWCTL: WKPSEL1 Position */ 2183 #define CLK_PAPWCTL_WKPSEL1_Msk (0xful << CLK_PAPWCTL_WKPSEL1_Pos) /*!< CLK_T::PAPWCTL: WKPSEL1 Mask */ 2184 2185 #define CLK_PAPWCTL_DBEN1_Pos (24) /*!< CLK_T::PAPWCTL: DBEN1 Position */ 2186 #define CLK_PAPWCTL_DBEN1_Msk (0x1ul << CLK_PAPWCTL_DBEN1_Pos) /*!< CLK_T::PAPWCTL: DBEN1 Mask */ 2187 2188 #define CLK_PAPWCTL_TRIGM1_Pos (26) /*!< CLK_T::PAPWCTL: TRIGM1 Position */ 2189 #define CLK_PAPWCTL_TRIGM1_Msk (0x1ul << CLK_PAPWCTL_TRIGM1_Pos) /*!< CLK_T::PAPWCTL: TRIGM1 Mask */ 2190 2191 #define CLK_PAPWCTL_NMR1_Pos (27) /*!< CLK_T::PAPWCTL: NMR1 Position */ 2192 #define CLK_PAPWCTL_NMR1_Msk (0x1ul << CLK_PAPWCTL_NMR1_Pos) /*!< CLK_T::PAPWCTL: NMR1 Mask */ 2193 2194 #define CLK_PBPWCTL_WKEN0_Pos (0) /*!< CLK_T::PBPWCTL: WKEN0 Position */ 2195 #define CLK_PBPWCTL_WKEN0_Msk (0x1ul << CLK_PBPWCTL_WKEN0_Pos) /*!< CLK_T::PBPWCTL: WKEN0 Mask */ 2196 2197 #define CLK_PBPWCTL_PRWKEN0_Pos (1) /*!< CLK_T::PBPWCTL: PRWKEN0 Position */ 2198 #define CLK_PBPWCTL_PRWKEN0_Msk (0x1ul << CLK_PBPWCTL_PRWKEN0_Pos) /*!< CLK_T::PBPWCTL: PRWKEN0 Mask */ 2199 2200 #define CLK_PBPWCTL_PFWKEN0_Pos (2) /*!< CLK_T::PBPWCTL: PFWKEN0 Position */ 2201 #define CLK_PBPWCTL_PFWKEN0_Msk (0x1ul << CLK_PBPWCTL_PFWKEN0_Pos) /*!< CLK_T::PBPWCTL: PFWKEN0 Mask */ 2202 2203 #define CLK_PBPWCTL_WKPSEL0_Pos (4) /*!< CLK_T::PBPWCTL: WKPSEL0 Position */ 2204 #define CLK_PBPWCTL_WKPSEL0_Msk (0xful << CLK_PBPWCTL_WKPSEL0_Pos) /*!< CLK_T::PBPWCTL: WKPSEL0 Mask */ 2205 2206 #define CLK_PBPWCTL_DBEN0_Pos (8) /*!< CLK_T::PBPWCTL: DBEN0 Position */ 2207 #define CLK_PBPWCTL_DBEN0_Msk (0x1ul << CLK_PBPWCTL_DBEN0_Pos) /*!< CLK_T::PBPWCTL: DBEN0 Mask */ 2208 2209 #define CLK_PBPWCTL_TRIGM0_Pos (10) /*!< CLK_T::PBPWCTL: TRIGM0 Position */ 2210 #define CLK_PBPWCTL_TRIGM0_Msk (0x1ul << CLK_PBPWCTL_TRIGM0_Pos) /*!< CLK_T::PBPWCTL: TRIGM0 Mask */ 2211 2212 #define CLK_PBPWCTL_NMR0_Pos (11) /*!< CLK_T::PBPWCTL: NMR0 Position */ 2213 #define CLK_PBPWCTL_NMR0_Msk (0x1ul << CLK_PBPWCTL_NMR0_Pos) /*!< CLK_T::PBPWCTL: NMR0 Mask */ 2214 2215 #define CLK_PBPWCTL_WKEN1_Pos (16) /*!< CLK_T::PBPWCTL: WKEN1 Position */ 2216 #define CLK_PBPWCTL_WKEN1_Msk (0x1ul << CLK_PBPWCTL_WKEN1_Pos) /*!< CLK_T::PBPWCTL: WKEN1 Mask */ 2217 2218 #define CLK_PBPWCTL_PRWKEN1_Pos (17) /*!< CLK_T::PBPWCTL: PRWKEN1 Position */ 2219 #define CLK_PBPWCTL_PRWKEN1_Msk (0x1ul << CLK_PBPWCTL_PRWKEN1_Pos) /*!< CLK_T::PBPWCTL: PRWKEN1 Mask */ 2220 2221 #define CLK_PBPWCTL_PFWKEN1_Pos (18) /*!< CLK_T::PBPWCTL: PFWKEN1 Position */ 2222 #define CLK_PBPWCTL_PFWKEN1_Msk (0x1ul << CLK_PBPWCTL_PFWKEN1_Pos) /*!< CLK_T::PBPWCTL: PFWKEN1 Mask */ 2223 2224 #define CLK_PBPWCTL_WKPSEL1_Pos (20) /*!< CLK_T::PBPWCTL: WKPSEL1 Position */ 2225 #define CLK_PBPWCTL_WKPSEL1_Msk (0xful << CLK_PBPWCTL_WKPSEL1_Pos) /*!< CLK_T::PBPWCTL: WKPSEL1 Mask */ 2226 2227 #define CLK_PBPWCTL_DBEN1_Pos (24) /*!< CLK_T::PBPWCTL: DBEN1 Position */ 2228 #define CLK_PBPWCTL_DBEN1_Msk (0x1ul << CLK_PBPWCTL_DBEN1_Pos) /*!< CLK_T::PBPWCTL: DBEN1 Mask */ 2229 2230 #define CLK_PBPWCTL_TRIGM1_Pos (26) /*!< CLK_T::PBPWCTL: TRIGM1 Position */ 2231 #define CLK_PBPWCTL_TRIGM1_Msk (0x1ul << CLK_PBPWCTL_TRIGM1_Pos) /*!< CLK_T::PBPWCTL: TRIGM1 Mask */ 2232 2233 #define CLK_PBPWCTL_NMR1_Pos (27) /*!< CLK_T::PBPWCTL: NMR1 Position */ 2234 #define CLK_PBPWCTL_NMR1_Msk (0x1ul << CLK_PBPWCTL_NMR1_Pos) /*!< CLK_T::PBPWCTL: NMR1 Mask */ 2235 2236 #define CLK_PCPWCTL_WKEN0_Pos (0) /*!< CLK_T::PCPWCTL: WKEN0 Position */ 2237 #define CLK_PCPWCTL_WKEN0_Msk (0x1ul << CLK_PCPWCTL_WKEN0_Pos) /*!< CLK_T::PCPWCTL: WKEN0 Mask */ 2238 2239 #define CLK_PCPWCTL_PRWKEN0_Pos (1) /*!< CLK_T::PCPWCTL: PRWKEN0 Position */ 2240 #define CLK_PCPWCTL_PRWKEN0_Msk (0x1ul << CLK_PCPWCTL_PRWKEN0_Pos) /*!< CLK_T::PCPWCTL: PRWKEN0 Mask */ 2241 2242 #define CLK_PCPWCTL_PFWKEN0_Pos (2) /*!< CLK_T::PCPWCTL: PFWKEN0 Position */ 2243 #define CLK_PCPWCTL_PFWKEN0_Msk (0x1ul << CLK_PCPWCTL_PFWKEN0_Pos) /*!< CLK_T::PCPWCTL: PFWKEN0 Mask */ 2244 2245 #define CLK_PCPWCTL_WKPSEL0_Pos (4) /*!< CLK_T::PCPWCTL: WKPSEL0 Position */ 2246 #define CLK_PCPWCTL_WKPSEL0_Msk (0xful << CLK_PCPWCTL_WKPSEL0_Pos) /*!< CLK_T::PCPWCTL: WKPSEL0 Mask */ 2247 2248 #define CLK_PCPWCTL_DBEN0_Pos (8) /*!< CLK_T::PCPWCTL: DBEN0 Position */ 2249 #define CLK_PCPWCTL_DBEN0_Msk (0x1ul << CLK_PCPWCTL_DBEN0_Pos) /*!< CLK_T::PCPWCTL: DBEN0 Mask */ 2250 2251 #define CLK_PCPWCTL_TRIGM0_Pos (10) /*!< CLK_T::PCPWCTL: TRIGM0 Position */ 2252 #define CLK_PCPWCTL_TRIGM0_Msk (0x1ul << CLK_PCPWCTL_TRIGM0_Pos) /*!< CLK_T::PCPWCTL: TRIGM0 Mask */ 2253 2254 #define CLK_PCPWCTL_NMR0_Pos (11) /*!< CLK_T::PCPWCTL: NMR0 Position */ 2255 #define CLK_PCPWCTL_NMR0_Msk (0x1ul << CLK_PCPWCTL_NMR0_Pos) /*!< CLK_T::PCPWCTL: NMR0 Mask */ 2256 2257 #define CLK_PCPWCTL_WKEN1_Pos (16) /*!< CLK_T::PCPWCTL: WKEN1 Position */ 2258 #define CLK_PCPWCTL_WKEN1_Msk (0x1ul << CLK_PCPWCTL_WKEN1_Pos) /*!< CLK_T::PCPWCTL: WKEN1 Mask */ 2259 2260 #define CLK_PCPWCTL_PRWKEN1_Pos (17) /*!< CLK_T::PCPWCTL: PRWKEN1 Position */ 2261 #define CLK_PCPWCTL_PRWKEN1_Msk (0x1ul << CLK_PCPWCTL_PRWKEN1_Pos) /*!< CLK_T::PCPWCTL: PRWKEN1 Mask */ 2262 2263 #define CLK_PCPWCTL_PFWKEN1_Pos (18) /*!< CLK_T::PCPWCTL: PFWKEN1 Position */ 2264 #define CLK_PCPWCTL_PFWKEN1_Msk (0x1ul << CLK_PCPWCTL_PFWKEN1_Pos) /*!< CLK_T::PCPWCTL: PFWKEN1 Mask */ 2265 2266 #define CLK_PCPWCTL_WKPSEL1_Pos (20) /*!< CLK_T::PCPWCTL: WKPSEL1 Position */ 2267 #define CLK_PCPWCTL_WKPSEL1_Msk (0xful << CLK_PCPWCTL_WKPSEL1_Pos) /*!< CLK_T::PCPWCTL: WKPSEL1 Mask */ 2268 2269 #define CLK_PCPWCTL_DBEN1_Pos (24) /*!< CLK_T::PCPWCTL: DBEN1 Position */ 2270 #define CLK_PCPWCTL_DBEN1_Msk (0x1ul << CLK_PCPWCTL_DBEN1_Pos) /*!< CLK_T::PCPWCTL: DBEN1 Mask */ 2271 2272 #define CLK_PCPWCTL_TRIGM1_Pos (26) /*!< CLK_T::PCPWCTL: TRIGM1 Position */ 2273 #define CLK_PCPWCTL_TRIGM1_Msk (0x1ul << CLK_PCPWCTL_TRIGM1_Pos) /*!< CLK_T::PCPWCTL: TRIGM1 Mask */ 2274 2275 #define CLK_PCPWCTL_NMR1_Pos (27) /*!< CLK_T::PCPWCTL: NMR1 Position */ 2276 #define CLK_PCPWCTL_NMR1_Msk (0x1ul << CLK_PCPWCTL_NMR1_Pos) /*!< CLK_T::PCPWCTL: NMR1 Mask */ 2277 2278 #define CLK_PDPWCTL_WKEN0_Pos (0) /*!< CLK_T::PDPWCTL: WKEN0 Position */ 2279 #define CLK_PDPWCTL_WKEN0_Msk (0x1ul << CLK_PDPWCTL_WKEN0_Pos) /*!< CLK_T::PDPWCTL: WKEN0 Mask */ 2280 2281 #define CLK_PDPWCTL_PRWKEN0_Pos (1) /*!< CLK_T::PDPWCTL: PRWKEN0 Position */ 2282 #define CLK_PDPWCTL_PRWKEN0_Msk (0x1ul << CLK_PDPWCTL_PRWKEN0_Pos) /*!< CLK_T::PDPWCTL: PRWKEN0 Mask */ 2283 2284 #define CLK_PDPWCTL_PFWKEN0_Pos (2) /*!< CLK_T::PDPWCTL: PFWKEN0 Position */ 2285 #define CLK_PDPWCTL_PFWKEN0_Msk (0x1ul << CLK_PDPWCTL_PFWKEN0_Pos) /*!< CLK_T::PDPWCTL: PFWKEN0 Mask */ 2286 2287 #define CLK_PDPWCTL_WKPSEL0_Pos (4) /*!< CLK_T::PDPWCTL: WKPSEL0 Position */ 2288 #define CLK_PDPWCTL_WKPSEL0_Msk (0xful << CLK_PDPWCTL_WKPSEL0_Pos) /*!< CLK_T::PDPWCTL: WKPSEL0 Mask */ 2289 2290 #define CLK_PDPWCTL_DBEN0_Pos (8) /*!< CLK_T::PDPWCTL: DBEN0 Position */ 2291 #define CLK_PDPWCTL_DBEN0_Msk (0x1ul << CLK_PDPWCTL_DBEN0_Pos) /*!< CLK_T::PDPWCTL: DBEN0 Mask */ 2292 2293 #define CLK_PDPWCTL_TRIGM0_Pos (10) /*!< CLK_T::PDPWCTL: TRIGM0 Position */ 2294 #define CLK_PDPWCTL_TRIGM0_Msk (0x1ul << CLK_PDPWCTL_TRIGM0_Pos) /*!< CLK_T::PDPWCTL: TRIGM0 Mask */ 2295 2296 #define CLK_PDPWCTL_NMR0_Pos (11) /*!< CLK_T::PDPWCTL: NMR0 Position */ 2297 #define CLK_PDPWCTL_NMR0_Msk (0x1ul << CLK_PDPWCTL_NMR0_Pos) /*!< CLK_T::PDPWCTL: NMR0 Mask */ 2298 2299 #define CLK_PDPWCTL_WKEN1_Pos (16) /*!< CLK_T::PDPWCTL: WKEN1 Position */ 2300 #define CLK_PDPWCTL_WKEN1_Msk (0x1ul << CLK_PDPWCTL_WKEN1_Pos) /*!< CLK_T::PDPWCTL: WKEN1 Mask */ 2301 2302 #define CLK_PDPWCTL_PRWKEN1_Pos (17) /*!< CLK_T::PDPWCTL: PRWKEN1 Position */ 2303 #define CLK_PDPWCTL_PRWKEN1_Msk (0x1ul << CLK_PDPWCTL_PRWKEN1_Pos) /*!< CLK_T::PDPWCTL: PRWKEN1 Mask */ 2304 2305 #define CLK_PDPWCTL_PFWKEN1_Pos (18) /*!< CLK_T::PDPWCTL: PFWKEN1 Position */ 2306 #define CLK_PDPWCTL_PFWKEN1_Msk (0x1ul << CLK_PDPWCTL_PFWKEN1_Pos) /*!< CLK_T::PDPWCTL: PFWKEN1 Mask */ 2307 2308 #define CLK_PDPWCTL_WKPSEL1_Pos (20) /*!< CLK_T::PDPWCTL: WKPSEL1 Position */ 2309 #define CLK_PDPWCTL_WKPSEL1_Msk (0xful << CLK_PDPWCTL_WKPSEL1_Pos) /*!< CLK_T::PDPWCTL: WKPSEL1 Mask */ 2310 2311 #define CLK_PDPWCTL_DBEN1_Pos (24) /*!< CLK_T::PDPWCTL: DBEN1 Position */ 2312 #define CLK_PDPWCTL_DBEN1_Msk (0x1ul << CLK_PDPWCTL_DBEN1_Pos) /*!< CLK_T::PDPWCTL: DBEN1 Mask */ 2313 2314 #define CLK_PDPWCTL_TRIGM1_Pos (26) /*!< CLK_T::PDPWCTL: TRIGM1 Position */ 2315 #define CLK_PDPWCTL_TRIGM1_Msk (0x1ul << CLK_PDPWCTL_TRIGM1_Pos) /*!< CLK_T::PDPWCTL: TRIGM1 Mask */ 2316 2317 #define CLK_PDPWCTL_NMR1_Pos (27) /*!< CLK_T::PDPWCTL: NMR1 Position */ 2318 #define CLK_PDPWCTL_NMR1_Msk (0x1ul << CLK_PDPWCTL_NMR1_Pos) /*!< CLK_T::PDPWCTL: NMR1 Mask */ 2319 2320 #define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ 2321 #define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ 2322 2323 #define CLK_IOPDCTL_DPDHOLDEN_Pos (8) /*!< CLK_T::IOPDCTL: DPDHOLDEN Position */ 2324 #define CLK_IOPDCTL_DPDHOLDEN_Msk (0x1ul << CLK_IOPDCTL_DPDHOLDEN_Pos) /*!< CLK_T::IOPDCTL: DPDHOLDEN Mask */ 2325 2326 #define CLK_PMUINTC_WKTMRIE_Pos (0) /*!< CLK_T::PMUINTC: WKTMRIE Position */ 2327 #define CLK_PMUINTC_WKTMRIE_Msk (0x1ul << CLK_PMUINTC_WKTMRIE_Pos) /*!< CLK_T::PMUINTC: WKTMRIE Mask */ 2328 2329 #define CLK_PMUINTC_WKIOA0IE_Pos (8) /*!< CLK_T::PMUINTC: WKIOA0IE Position */ 2330 #define CLK_PMUINTC_WKIOA0IE_Msk (0x1ul << CLK_PMUINTC_WKIOA0IE_Pos) /*!< CLK_T::PMUINTC: WKIOA0IE Mask */ 2331 2332 #define CLK_PMUINTC_WKIOB0IE_Pos (9) /*!< CLK_T::PMUINTC: WKIOB0IE Position */ 2333 #define CLK_PMUINTC_WKIOB0IE_Msk (0x1ul << CLK_PMUINTC_WKIOB0IE_Pos) /*!< CLK_T::PMUINTC: WKIOB0IE Mask */ 2334 2335 #define CLK_PMUINTC_WKIOC0IE_Pos (10) /*!< CLK_T::PMUINTC: WKIOC0IE Position */ 2336 #define CLK_PMUINTC_WKIOC0IE_Msk (0x1ul << CLK_PMUINTC_WKIOC0IE_Pos) /*!< CLK_T::PMUINTC: WKIOC0IE Mask */ 2337 2338 #define CLK_PMUINTC_WKIOD0IE_Pos (11) /*!< CLK_T::PMUINTC: WKIOD0IE Position */ 2339 #define CLK_PMUINTC_WKIOD0IE_Msk (0x1ul << CLK_PMUINTC_WKIOD0IE_Pos) /*!< CLK_T::PMUINTC: WKIOD0IE Mask */ 2340 2341 #define CLK_PMUINTC_WKIOA1IE_Pos (12) /*!< CLK_T::PMUINTC: WKIOA1IE Position */ 2342 #define CLK_PMUINTC_WKIOA1IE_Msk (0x1ul << CLK_PMUINTC_WKIOA1IE_Pos) /*!< CLK_T::PMUINTC: WKIOA1IE Mask */ 2343 2344 #define CLK_PMUINTC_WKIOB1IE_Pos (13) /*!< CLK_T::PMUINTC: WKIOB1IE Position */ 2345 #define CLK_PMUINTC_WKIOB1IE_Msk (0x1ul << CLK_PMUINTC_WKIOB1IE_Pos) /*!< CLK_T::PMUINTC: WKIOB1IE Mask */ 2346 2347 #define CLK_PMUINTC_WKIOC1IE_Pos (14) /*!< CLK_T::PMUINTC: WKIOC1IE Position */ 2348 #define CLK_PMUINTC_WKIOC1IE_Msk (0x1ul << CLK_PMUINTC_WKIOC1IE_Pos) /*!< CLK_T::PMUINTC: WKIOC1IE Mask */ 2349 2350 #define CLK_PMUINTC_WKIOD1IE_Pos (15) /*!< CLK_T::PMUINTC: WKIOD1IE Position */ 2351 #define CLK_PMUINTC_WKIOD1IE_Msk (0x1ul << CLK_PMUINTC_WKIOD1IE_Pos) /*!< CLK_T::PMUINTC: WKIOD1IE Mask */ 2352 2353 #define CLK_PMUINTS_WKTMRIF_Pos (0) /*!< CLK_T::PMUINTS: WKTMRIF Position */ 2354 #define CLK_PMUINTS_WKTMRIF_Msk (0x1ul << CLK_PMUINTS_WKTMRIF_Pos) /*!< CLK_T::PMUINTS: WKTMRIF Mask */ 2355 2356 #define CLK_PMUINTS_WKIOA0IF_Pos (8) /*!< CLK_T::PMUINTS: WKIOA0IF Position */ 2357 #define CLK_PMUINTS_WKIOA0IF_Msk (0x1ul << CLK_PMUINTS_WKIOA0IF_Pos) /*!< CLK_T::PMUINTS: WKIOA0IF Mask */ 2358 2359 #define CLK_PMUINTS_WKIOB0IF_Pos (9) /*!< CLK_T::PMUINTS: WKIOB0IF Position */ 2360 #define CLK_PMUINTS_WKIOB0IF_Msk (0x1ul << CLK_PMUINTS_WKIOB0IF_Pos) /*!< CLK_T::PMUINTS: WKIOB0IF Mask */ 2361 2362 #define CLK_PMUINTS_WKIOC0IF_Pos (10) /*!< CLK_T::PMUINTS: WKIOC0IF Position */ 2363 #define CLK_PMUINTS_WKIOC0IF_Msk (0x1ul << CLK_PMUINTS_WKIOC0IF_Pos) /*!< CLK_T::PMUINTS: WKIOC0IF Mask */ 2364 2365 #define CLK_PMUINTS_WKIOD0IF_Pos (11) /*!< CLK_T::PMUINTS: WKIOD0IF Position */ 2366 #define CLK_PMUINTS_WKIOD0IF_Msk (0x1ul << CLK_PMUINTS_WKIOD0IF_Pos) /*!< CLK_T::PMUINTS: WKIOD0IF Mask */ 2367 2368 #define CLK_PMUINTS_WKIOA1IF_Pos (12) /*!< CLK_T::PMUINTS: WKIOA1IF Position */ 2369 #define CLK_PMUINTS_WKIOA1IF_Msk (0x1ul << CLK_PMUINTS_WKIOA1IF_Pos) /*!< CLK_T::PMUINTS: WKIOA1IF Mask */ 2370 2371 #define CLK_PMUINTS_WKIOB1IF_Pos (13) /*!< CLK_T::PMUINTS: WKIOB1IF Position */ 2372 #define CLK_PMUINTS_WKIOB1IF_Msk (0x1ul << CLK_PMUINTS_WKIOB1IF_Pos) /*!< CLK_T::PMUINTS: WKIOB1IF Mask */ 2373 2374 #define CLK_PMUINTS_WKIOC1IF_Pos (14) /*!< CLK_T::PMUINTS: WKIOC1IF Position */ 2375 #define CLK_PMUINTS_WKIOC1IF_Msk (0x1ul << CLK_PMUINTS_WKIOC1IF_Pos) /*!< CLK_T::PMUINTS: WKIOC1IF Mask */ 2376 2377 #define CLK_PMUINTS_WKIOD1IF_Pos (15) /*!< CLK_T::PMUINTS: WKIOD1IF Position */ 2378 #define CLK_PMUINTS_WKIOD1IF_Msk (0x1ul << CLK_PMUINTS_WKIOD1IF_Pos) /*!< CLK_T::PMUINTS: WKIOD1IF Mask */ 2379 2380 /**@}*/ /* CLK_CONST */ 2381 /**@}*/ /* end of CLK register group */ 2382 /**@}*/ /* end of REGISTER group */ 2383 2384 #if defined ( __CC_ARM ) 2385 #pragma no_anon_unions 2386 #endif 2387 2388 #endif /* __CLK_REG_H__ */ 2389
