1 /**************************************************************************//** 2 * @file uuart_reg.h 3 * @version V1.00 4 * @brief UUART register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __UUART_REG_H__ 10 #define __UUART_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup UUART UART Mode of USCI Controller(UUART) 23 Memory Mapped Structure for UUART Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var UUART_T::CTL 32 * Offset: 0x00 USCI Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[2:0] |FUNMODE |Function Mode 37 * | | |This bit field selects the protocol for this USCI controller 38 * | | |Selecting a protocol that is not available or a reserved combination disables the USCI 39 * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol 40 * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. 41 * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. 42 * | | |001 = The SPI protocol is selected. 43 * | | |010 = The UART protocol is selected. 44 * | | |100 = The I2C protocol is selected. 45 * | | |Note: Other bit combinations are reserved. 46 * @var UUART_T::INTEN 47 * Offset: 0x04 USCI Interrupt Enable Register 48 * --------------------------------------------------------------------------------------------------- 49 * |Bits |Field |Descriptions 50 * | :----: | :----: | :---- | 51 * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit 52 * | | |This bit enables the interrupt generation in case of a transmit start event. 53 * | | |0 = The transmit start interrupt is disabled. 54 * | | |1 = The transmit start interrupt is enabled. 55 * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit 56 * | | |This bit enables the interrupt generation in case of a transmit finish event. 57 * | | |0 = The transmit finish interrupt is disabled. 58 * | | |1 = The transmit finish interrupt is enabled. 59 * |[3] |RXSTIEN |Receive Start Interrupt Enable BIt 60 * | | |This bit enables the interrupt generation in case of a receive start event. 61 * | | |0 = The receive start interrupt is disabled. 62 * | | |1 = The receive start interrupt is enabled. 63 * |[4] |RXENDIEN |Receive End Interrupt Enable Bit 64 * | | |This bit enables the interrupt generation in case of a receive finish event. 65 * | | |0 = The receive end interrupt is disabled. 66 * | | |1 = The receive end interrupt is enabled. 67 * @var UUART_T::BRGEN 68 * Offset: 0x08 USCI Baud Rate Generator Register 69 * --------------------------------------------------------------------------------------------------- 70 * |Bits |Field |Descriptions 71 * | :----: | :----: | :---- | 72 * |[0] |RCLKSEL |Reference Clock Source Selection 73 * | | |This bit selects the source signal of reference clock (fREF_CLK). 74 * | | |0 = Peripheral device clock fPCLK. 75 * | | |1 = Reserved. 76 * |[1] |PTCLKSEL |Protocol Clock Source Selection 77 * | | |This bit selects the source signal of protocol clock (fPROT_CLK). 78 * | | |0 = Reference clock fREF_CLK. 79 * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). 80 * |[3:2] |SPCLKSEL |Sample Clock Source Selection 81 * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 82 * | | |00 = fSAMP_CLK = fDIV_CLK. 83 * | | |01 = fSAMP_CLK = fPROT_CLK. 84 * | | |10 = fSAMP_CLK = fSCLK. 85 * | | |11 = fSAMP_CLK = fREF_CLK. 86 * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit 87 * | | |This bit enables the 10-bit timing measurement counter. 88 * | | |0 = Timing measurement counter is Disabled. 89 * | | |1 = Timing measurement counter is Enabled. 90 * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection 91 * | | |0 = Timing measurement counter with fPROT_CLK. 92 * | | |1 = Timing measurement counter with fDIV_CLK. 93 * |[9:8] |PDSCNT |Pre-divider for Sample Counter 94 * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK 95 * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). 96 * |[14:10] |DSCNT |Denominator for Sample Counter 97 * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. 98 * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). 99 * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value 100 * |[25:16] |CLKDIV |Clock Divider 101 * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and 102 * | | |the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). 103 * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 104 * | | |when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled 105 * | | |The revised value is the average bit time between bit 5 and bit 6 106 * | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate. 107 * @var UUART_T::DATIN0 108 * Offset: 0x10 USCI Input Data Signal Configuration Register 0 109 * --------------------------------------------------------------------------------------------------- 110 * |Bits |Field |Descriptions 111 * | :----: | :----: | :---- | 112 * |[0] |SYNCSEL |Input Signal Synchronization Selection 113 * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or 114 * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 115 * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. 116 * | | |1 = The synchronized signal can be taken as input for the data shift unit. 117 * |[2] |ININV |Input Signal Inverse Selection 118 * | | |This bit defines the inverter enable of the input asynchronous signal. 119 * | | |0 = The un-synchronized input signal will not be inverted. 120 * | | |1 = The un-synchronized input signal will be inverted. 121 * |[4:3] |EDGEDET |Input Signal Edge Detection Mode 122 * | | |This bit field selects which edge actives the trigger event of input data signal. 123 * | | |00 = The trigger event activation is disabled. 124 * | | |01 = A rising edge activates the trigger event of input data signal. 125 * | | |10 = A falling edge activates the trigger event of input data signal. 126 * | | |11 = Both edges activate the trigger event of input data signal. 127 * | | |Note: In UART function mode, it is suggested to set this bit field as 10. 128 * @var UUART_T::CTLIN0 129 * Offset: 0x20 USCI Input Control Signal Configuration Register 0 130 * --------------------------------------------------------------------------------------------------- 131 * |Bits |Field |Descriptions 132 * | :----: | :----: | :---- | 133 * |[0] |SYNCSEL |Input Synchronization Signal Selection 134 * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or 135 * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 136 * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. 137 * | | |1 = The synchronized signal can be taken as input for the data shift unit. 138 * |[2] |ININV |Input Signal Inverse Selection 139 * | | |This bit defines the inverter enable of the input asynchronous signal. 140 * | | |0 = The un-synchronized input signal will not be inverted. 141 * | | |1 = The un-synchronized input signal will be inverted. 142 * @var UUART_T::CLKIN 143 * Offset: 0x28 USCI Input Clock Signal Configuration Register 144 * --------------------------------------------------------------------------------------------------- 145 * |Bits |Field |Descriptions 146 * | :----: | :----: | :---- | 147 * |[0] |SYNCSEL |Input Synchronization Signal Selection 148 * | | |This bit selects if the un-synchronized input signal or 149 * | | |the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 150 * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. 151 * | | |1 = The synchronized signal can be taken as input for the data shift unit. 152 * @var UUART_T::LINECTL 153 * Offset: 0x2C USCI Line Control Register 154 * --------------------------------------------------------------------------------------------------- 155 * |Bits |Field |Descriptions 156 * | :----: | :----: | :---- | 157 * |[0] |LSB |LSB First Transmission Selection 158 * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. 159 * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. 160 * |[5] |DATOINV |Data Output Inverse Selection 161 * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 162 * | | |0 = The value of USCIx_DAT1 is equal to the data shift register. 163 * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register. 164 * |[7] |CTLOINV |Control Signal Output Inverse Selection 165 * | | |This bit defines the relation between the internal control signal and the output control signal. 166 * | | |0 = No effect. 167 * | | |1 = The control signal will be inverted before its output. 168 * | | |Note: In UART protocol, the control signal means nRTS signal. 169 * |[11:8] |DWIDTH |Word Length of Transmission 170 * | | |This bit field defines the data word length (amount of bits) for reception and transmission 171 * | | |The data word is always right-aligned in the data buffer 172 * | | |USCI support word length from 4 to 16 bits. 173 * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. 174 * | | |0x1: Reserved. 175 * | | |0x2: Reserved. 176 * | | |0x3: Reserved. 177 * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. 178 * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. 179 * | | |.. 180 * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. 181 * | | |Note: In UART protocol, the length can be configured as 6~13 bits. 182 * @var UUART_T::TXDAT 183 * Offset: 0x30 USCI Transmit Data Register 184 * --------------------------------------------------------------------------------------------------- 185 * |Bits |Field |Descriptions 186 * | :----: | :----: | :---- | 187 * |[15:0] |TXDAT |Transmit Data 188 * | | |Software can use this bit field to write 16-bit transmit data for transmission. 189 * @var UUART_T::RXDAT 190 * Offset: 0x34 USCI Receive Data Register 191 * --------------------------------------------------------------------------------------------------- 192 * |Bits |Field |Descriptions 193 * | :----: | :----: | :---- | 194 * |[15:0] |RXDAT |Received Data 195 * | | |This bit field monitors the received data which stored in receive data buffer. 196 * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]). 197 * @var UUART_T::BUFCTL 198 * Offset: 0x38 USCI Transmit/Receive Buffer Control Register 199 * --------------------------------------------------------------------------------------------------- 200 * |Bits |Field |Descriptions 201 * | :----: | :----: | :---- | 202 * |[7] |TXCLR |Clear Transmit Buffer 203 * | | |0 = No effect. 204 * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value) 205 * | | |Should only be used while the buffer is not taking part in data traffic. 206 * | | |Note: It is cleared automatically after one PCLK cycle. 207 * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control 208 * | | |0 = Receive overrun interrupt Disabled. 209 * | | |1 = Receive overrun interrupt Enabled. 210 * |[15] |RXCLR |Clear Receive Buffer 211 * | | |0 = No effect. 212 * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value) 213 * | | |Should only be used while the buffer is not taking part in data traffic. 214 * | | |Note: It is cleared automatically after one PCLK cycle. 215 * |[16] |TXRST |Transmit Reset 216 * | | |0 = No effect. 217 * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. 218 * | | |Note: It is cleared automatically after one PCLK cycle. 219 * |[17] |RXRST |Receive Reset 220 * | | |0 = No effect. 221 * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. 222 * | | |Note 1: It is cleared automatically after one PCLK cycle. 223 * | | |Note 2: It is suggest to check the RXBUSY (USCI_PROTSTS[10]) before this bit will be set to 1. 224 * @var UUART_T::BUFSTS 225 * Offset: 0x3C USCI Transmit/Receive Buffer Status Register 226 * --------------------------------------------------------------------------------------------------- 227 * |Bits |Field |Descriptions 228 * | :----: | :----: | :---- | 229 * |[0] |RXEMPTY |Receive Buffer Empty Indicator 230 * | | |0 = Receive buffer is not empty. 231 * | | |1 = Receive buffer is empty. 232 * |[1] |RXFULL |Receive Buffer Full Indicator 233 * | | |0 = Receive buffer is not full. 234 * | | |1 = Receive buffer is full. 235 * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status 236 * | | |This bit indicates that a receive buffer overrun error event has been detected 237 * | | |If RXOVIEN (USCI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated 238 * | | |It is cleared by software writes 1 to this bit. 239 * | | |0 = A receive buffer overrun error event has not been detected. 240 * | | |1 = A receive buffer overrun error event has been detected. 241 * |[8] |TXEMPTY |Transmit Buffer Empty Indicator 242 * | | |0 = Transmit buffer is not empty. 243 * | | |1 = Transmit buffer is empty. 244 * |[9] |TXFULL |Transmit Buffer Full Indicator 245 * | | |0 = Transmit buffer is not full. 246 * | | |1 = Transmit buffer is full. 247 * @var UUART_T::PDMACTL 248 * Offset: 0x40 USCI PDMA Control Register 249 * --------------------------------------------------------------------------------------------------- 250 * |Bits |Field |Descriptions 251 * | :----: | :----: | :---- | 252 * |[0] |PDMARST |PDMA Reset 253 * | | |0 = No effect. 254 * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. 255 * |[1] |TXPDMAEN |PDMA Transmit Channel Available 256 * | | |0 = Transmit PDMA function Disabled. 257 * | | |1 = Transmit PDMA function Enabled. 258 * |[2] |RXPDMAEN |PDMA Receive Channel Available 259 * | | |0 = Receive PDMA function Disabled. 260 * | | |1 = Receive PDMA function Enabled. 261 * |[3] |PDMAEN |PDMA Mode Enable Bit 262 * | | |0 = PDMA function Disabled. 263 * | | |1 = PDMA function Enabled. 264 * @var UUART_T::WKCTL 265 * Offset: 0x54 USCI Wake-up Control Register 266 * --------------------------------------------------------------------------------------------------- 267 * |Bits |Field |Descriptions 268 * | :----: | :----: | :---- | 269 * |[0] |WKEN |Wake-up Enable Bit 270 * | | |0 = Wake-up function Disabled. 271 * | | |1 = Wake-up function Enabled. 272 * |[2] |PDBOPT |Power Down Blocking Option 273 * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. 274 * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. 275 * @var UUART_T::WKSTS 276 * Offset: 0x58 USCI Wake-up Status Register 277 * --------------------------------------------------------------------------------------------------- 278 * |Bits |Field |Descriptions 279 * | :----: | :----: | :---- | 280 * |[0] |WKF |Wake-up Flag 281 * | | |When chip is woken up from Power-down mode, this bit is set to 1 282 * | | |Software can write 1 to clear this bit. 283 * @var UUART_T::PROTCTL 284 * Offset: 0x5C USCI Protocol Control Register 285 * --------------------------------------------------------------------------------------------------- 286 * |Bits |Field |Descriptions 287 * | :----: | :----: | :---- | 288 * |[0] |STOPB |Stop Bits 289 * | | |This bit defines the number of stop bits in an UART frame. 290 * | | |0 = The number of stop bits is 1. 291 * | | |1 = The number of stop bits is 2. 292 * |[1] |PARITYEN |Parity Enable Bit 293 * | | |This bit defines the parity bit is enabled in an UART frame. 294 * | | |0 = The parity bit Disabled. 295 * | | |1 = The parity bit Enabled. 296 * |[2] |EVENPARITY|Even Parity Enable Bit 297 * | | |0 = Odd number of logic 1's is transmitted and checked in each word. 298 * | | |1 = Even number of logic 1's is transmitted and checked in each word. 299 * | | |Note: This bit has effect only when PARITYEN is set. 300 * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit 301 * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (USCI_BUFSTS[1] = 1'b1)), the UART will de-assert nRTS signal. 302 * | | |0 = nRTS auto-flow control Disabled. 303 * | | |1 = nRTS auto-flow control Enabled. 304 * | | |Note: This bit has effect only when the RTSAUDIREN is not set. 305 * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit 306 * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). 307 * | | |0 = nCTS auto-flow control Disabled. 308 * | | |1 = nCTS auto-flow control Enabled. 309 * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit 310 * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically. 311 * | | |0 = nRTS auto direction control Disabled. 312 * | | |1 = nRTS auto direction control Enabled. 313 * | | |Note 1: This bit is used for nRTS auto direction control for RS485. 314 * | | |Note 2: This bit has effect only when the RTSAUTOEN is not set. 315 * |[6] |ABREN |Auto-baud Rate Detect Enable Bit 316 * | | |0 = Auto-baud rate detect function Disabled. 317 * | | |1 = Auto-baud rate detect function Enabled. 318 * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit 319 * | | |The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (USCI_PROTIEN [1]) is enabled). 320 * |[9] |DATWKEN |Data Wake-up Mode Enable Bit 321 * | | |0 = Data wake-up mode Disabled. 322 * | | |1 = Data wake-up mode Enabled. 323 * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit 324 * | | |0 = nCTS wake-up mode Disabled. 325 * | | |1 = nCTS wake-up mode Enabled. 326 * |[14:11] |WAKECNT |Wake-up Counter 327 * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. 328 * |[24:16] |BRDETITV |Baud Rate Detection Interval 329 * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) does the slave calculates the baud rate in one bits 330 * | | |The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55) 331 * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (USCI_PROTCTL[9]) is set. 332 * | | |Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 333 * |[26] |STICKEN |Stick Parity Enable Bit 334 * | | |0 = Stick parity Disabled. 335 * | | |1 = Stick parity Enabled. 336 * | | |Note: Refer to RS-485 Support section for detail information. 337 * |[29] |BCEN |Transmit Break Control Enable Bit 338 * | | |0 = Transmit Break Control Disabled. 339 * | | |1 = Transmit Break Control Enabled. 340 * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0) 341 * | | |This bit acts only on TX line and has no effect on the transmitter logic. 342 * |[31] |PROTEN |UART Protocol Enable Bit 343 * | | |0 = UART Protocol Disabled. 344 * | | |1 = UART Protocol Enabled. 345 * @var UUART_T::PROTIEN 346 * Offset: 0x60 USCI Protocol Interrupt Enable Register 347 * --------------------------------------------------------------------------------------------------- 348 * |Bits |Field |Descriptions 349 * | :----: | :----: | :---- | 350 * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit 351 * | | |0 = Auto-baud rate interrupt Disabled. 352 * | | |1 = Auto-baud rate interrupt Enabled. 353 * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit 354 * | | |0 = Receive line status interrupt Disabled. 355 * | | |1 = Receive line status interrupt Enabled. 356 * | | |Note: USCI_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 357 * @var UUART_T::PROTSTS 358 * Offset: 0x64 USCI Protocol Status Register 359 * --------------------------------------------------------------------------------------------------- 360 * |Bits |Field |Descriptions 361 * | :----: | :----: | :---- | 362 * |[1] |TXSTIF |Transmit Start Interrupt Flag 363 * | | |0 = A transmit start interrupt status has not occurred. 364 * | | |1 = A transmit start interrupt status has occurred. 365 * | | |Note 1: It is cleared by software writing one into this bit. 366 * | | |Note 2: Used for user to load next transmit data when there is no data in transmit buffer. 367 * |[2] |TXENDIF |Transmit End Interrupt Flag 368 * | | |0 = A transmit end interrupt status has not occurred. 369 * | | |1 = A transmit end interrupt status has occurred. 370 * | | |Note: It is cleared by software writing one into this bit. 371 * |[3] |RXSTIF |Receive Start Interrupt Flag 372 * | | |0 = A receive start interrupt status has not occurred. 373 * | | |1 = A receive start interrupt status has occurred. 374 * | | |Note: It is cleared by software writing one into this bit. 375 * |[4] |RXENDIF |Receive End Interrupt Flag 376 * | | |0 = A receive finish interrupt status has not occurred. 377 * | | |1 = A receive finish interrupt status has occurred. 378 * | | |Note: It is cleared by software writing one into this bit. 379 * |[5] |PARITYERR |Parity Error Flag 380 * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. 381 * | | |0 = No parity error is generated. 382 * | | |1 = Parity error is generated. 383 * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 384 * |[6] |FRMERR |Framing Error Flag 385 * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' 386 * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0). 387 * | | |0 = No framing error is generated. 388 * | | |1 = Framing error is generated. 389 * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 390 * |[7] |BREAK |Break Flag 391 * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' 392 * | | |(logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). 393 * | | |0 = No Break is generated. 394 * | | |1 = Break is generated in the receiver bus. 395 * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 396 * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag 397 * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data 398 * | | |If the ABRIEN (USCI_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated 399 * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. 400 * | | |0 = Auto-baud rate detect function is not done. 401 * | | |1 = One Bit auto-baud rate detect function is done. 402 * | | |Note: This bit can be cleared by writing '1' to it. 403 * |[10] |RXBUSY |RX Bus Status Flag (Read Only) 404 * | | |This bit indicates the busy status of the receiver. 405 * | | |0 = The receiver is Idle. 406 * | | |1 = The receiver is BUSY. 407 * |[11] |ABERRSTS |Auto-baud Rate Error Status 408 * | | |This bit is set when auto-baud rate detection counter overrun 409 * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (USCI_BRGEN[25:16]) value and 410 * | | |enable ABREN (USCI_PROTCTL[6]) to detect the correct baud rate again. 411 * | | |0 = Auto-baud rate detect counter is not overrun. 412 * | | |1 = Auto-baud rate detect counter is overrun. 413 * | | |Note 1: This bit is set at the same time of ABRDETIF. 414 * | | |Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. 415 * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only) 416 * | | |This bit used to indicate the current status of the internal synchronized nCTS signal. 417 * | | |0 = The internal synchronized nCTS is low. 418 * | | |1 = The internal synchronized nCTS is high. 419 * |[17] |CTSLV |nCTS Pin Status (Read Only) 420 * | | |This bit used to monitor the current status of nCTS pin input. 421 * | | |0 = nCTS pin input is low level voltage logic state. 422 * | | |1 = nCTS pin input is high level voltage logic state. 423 */ 424 __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ 425 __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ 426 __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ 427 /// @cond HIDDEN_SYMBOLS 428 __I uint32_t RESERVE0[1]; 429 /// @endcond //HIDDEN_SYMBOLS 430 __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ 431 /// @cond HIDDEN_SYMBOLS 432 __I uint32_t RESERVE1[3]; 433 /// @endcond //HIDDEN_SYMBOLS 434 __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ 435 /// @cond HIDDEN_SYMBOLS 436 __I uint32_t RESERVE2[1]; 437 /// @endcond //HIDDEN_SYMBOLS 438 __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ 439 __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ 440 __IO uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ 441 __IO uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ 442 __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ 443 __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ 444 __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ 445 /// @cond HIDDEN_SYMBOLS 446 __I uint32_t RESERVE3[4]; 447 /// @endcond //HIDDEN_SYMBOLS 448 __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ 449 __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ 450 __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ 451 __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ 452 __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ 453 454 } UUART_T; 455 456 /** 457 @addtogroup UUART_CONST UUART Bit Field Definition 458 Constant Definitions for UUART Controller 459 @{ */ 460 461 #define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */ 462 #define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */ 463 464 #define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */ 465 #define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */ 466 467 #define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */ 468 #define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */ 469 470 #define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */ 471 #define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */ 472 473 #define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */ 474 #define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */ 475 476 #define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */ 477 #define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */ 478 479 #define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */ 480 #define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */ 481 482 #define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */ 483 #define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */ 484 485 #define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */ 486 #define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */ 487 488 #define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */ 489 #define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */ 490 491 #define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */ 492 #define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */ 493 494 #define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */ 495 #define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */ 496 497 #define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */ 498 #define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */ 499 500 #define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */ 501 #define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */ 502 503 #define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */ 504 #define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */ 505 506 #define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */ 507 #define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */ 508 509 #define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */ 510 #define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */ 511 512 #define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */ 513 #define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */ 514 515 #define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */ 516 #define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */ 517 518 #define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */ 519 #define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */ 520 521 #define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */ 522 #define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */ 523 524 #define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */ 525 #define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */ 526 527 #define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */ 528 #define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */ 529 530 #define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */ 531 #define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */ 532 533 #define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */ 534 #define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */ 535 536 #define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */ 537 #define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */ 538 539 #define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */ 540 #define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */ 541 542 #define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */ 543 #define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */ 544 545 #define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */ 546 #define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */ 547 548 #define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */ 549 #define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */ 550 551 #define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */ 552 #define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */ 553 554 #define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */ 555 #define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */ 556 557 #define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */ 558 #define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */ 559 560 #define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */ 561 #define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */ 562 563 #define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */ 564 #define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */ 565 566 #define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */ 567 #define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */ 568 569 #define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */ 570 #define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */ 571 572 #define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */ 573 #define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */ 574 575 #define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */ 576 #define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */ 577 578 #define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */ 579 #define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */ 580 581 #define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */ 582 #define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */ 583 584 #define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */ 585 #define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */ 586 587 #define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */ 588 #define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */ 589 590 #define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */ 591 #define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */ 592 593 #define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */ 594 #define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */ 595 596 #define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */ 597 #define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */ 598 599 #define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */ 600 #define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */ 601 602 #define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */ 603 #define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */ 604 605 #define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */ 606 #define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */ 607 608 #define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */ 609 #define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */ 610 611 #define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */ 612 #define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */ 613 614 #define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */ 615 #define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */ 616 617 #define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */ 618 #define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */ 619 620 #define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */ 621 #define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */ 622 623 #define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */ 624 #define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */ 625 626 #define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */ 627 #define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */ 628 629 #define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */ 630 #define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */ 631 632 #define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */ 633 #define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */ 634 635 #define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */ 636 #define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */ 637 638 #define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */ 639 #define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */ 640 641 #define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */ 642 #define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */ 643 644 #define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */ 645 #define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */ 646 647 #define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */ 648 #define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */ 649 650 #define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */ 651 #define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */ 652 653 #define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */ 654 #define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */ 655 656 #define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */ 657 #define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */ 658 659 #define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */ 660 #define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */ 661 662 #define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */ 663 #define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */ 664 665 #define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */ 666 #define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */ 667 668 #define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */ 669 #define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */ 670 671 /**@}*/ /* UUART_CONST */ 672 /**@}*/ /* end of UUART register group */ 673 /**@}*/ /* end of REGISTER group */ 674 675 #if defined ( __CC_ARM ) 676 #pragma no_anon_unions 677 #endif 678 679 #endif /* __UUART_REG_H__ */ 680
