1 /**************************************************************************//** 2 * @file spi_reg.h 3 * @version V1.00 4 * @brief SPI register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SPI_REG_H__ 10 #define __SPI_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup SPI Serial Peripheral Interface Controller(SPI) 23 Memory Mapped Structure for SPI Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var SPI_T::CTL 32 * Offset: 0x00 SPI Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |SPIEN |SPI Transfer Control Enable Bit 37 * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 38 * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. 39 * | | |0 = Transfer control Disabled. 40 * | | |1 = Transfer control Enabled. 41 * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 42 * |[1] |RXNEG |Receive on Negative Edge 43 * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. 44 * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. 45 * |[2] |TXNEG |Transmit on Negative Edge 46 * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. 47 * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. 48 * |[3] |CLKPOL |Clock Polarity 49 * | | |0 = SPI bus clock is idle low. 50 * | | |1 = SPI bus clock is idle high. 51 * |[7:4] |SUSPITV |Suspend Interval (Master Only) 52 * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer 53 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word 54 * | | |The default value is 0x3 55 * | | |The period of the suspend interval is obtained according to the following equation. 56 * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle 57 * | | |Example: 58 * | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle. 59 * | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle. 60 * | | |..... 61 * | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle. 62 * | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle. 63 * |[12:8] |DWIDTH |Data Width 64 * | | |This field specifies how many bits can be transmitted / received in one transaction 65 * | | |The minimum bit length is 8 bits and can up to 32 bits. 66 * | | |DWIDTH = 0x08 .... 8 bits. 67 * | | |DWIDTH = 0x09 .... 9 bits. 68 * | | |..... 69 * | | |DWIDTH = 0x1F .... 31 bits. 70 * | | |DWIDTH = 0x00 .... 32 bits. 71 * | | |Note: For SPI1~SPI4, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode 72 * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI1~SPI4. 73 * |[13] |LSB |Send LSB First 74 * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. 75 * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). 76 * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit 77 * | | |This bit is used to select full-duplex or half-duplex for SPI transfer 78 * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 79 * | | |0 = SPI operates in full-duplex transfer. 80 * | | |1 = SPI operates in half-duplex transfer. 81 * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) 82 * | | |This bit field is only available in Master mode 83 * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 84 * | | |0 = Receive-only mode Disabled. 85 * | | |1 = Receive-only mode Enabled. 86 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit 87 * | | |0 = SPI unit transfer interrupt Disabled. 88 * | | |1 = SPI unit transfer interrupt Enabled. 89 * |[18] |SLAVE |Slave Mode Control 90 * | | |0 = Master mode. 91 * | | |1 = Slave mode. 92 * |[19] |REORDER |Byte Reorder Function Enable Bit 93 * | | |0 = Byte Reorder function Disabled. 94 * | | |1 = Byte Reorder function Enabled 95 * | | |A byte suspend interval will be inserted among each byte 96 * | | |The period of the byte suspend interval depends on the setting of SUSPITV. 97 * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 98 * |[20] |DATDIR |Data Port Direction Control 99 * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 100 * | | |0 = SPI data is input direction. 101 * | | |1 = SPI data is output direction. 102 * @var SPI_T::CLKDIV 103 * Offset: 0x04 SPI Clock Divider Register 104 * --------------------------------------------------------------------------------------------------- 105 * |Bits |Field |Descriptions 106 * | :----: | :----: | :---- | 107 * |[8:0] |DIVIDER |Clock Divider 108 * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master 109 * | | |The frequency is obtained according to the following equation. 110 * | | |where 111 * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. 112 * | | |Note: Not supported in I2S mode. 113 * @var SPI_T::SSCTL 114 * Offset: 0x08 SPI Slave Select Control Register 115 * --------------------------------------------------------------------------------------------------- 116 * |Bits |Field |Descriptions 117 * | :----: | :----: | :---- | 118 * |[0] |SS |Slave Selection Control (Master Only) 119 * | | |If AUTOSS bit is cleared to 0, 120 * | | |0 = set the SPIx_SS line to inactive state. 121 * | | |1 = set the SPIx_SS line to active state. 122 * | | |If the AUTOSS bit is set to 1, 123 * | | |0 = Keep the SPIx_SS line at inactive state. 124 * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time 125 * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]). 126 * |[2] |SSACTPOL |Slave Selection Active Polarity 127 * | | |This bit defines the active polarity of slave selection signal (SPIx_SS). 128 * | | |0 = The slave selection signal SPIx_SS is active low. 129 * | | |1 = The slave selection signal SPIx_SS is active high. 130 * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) 131 * | | |0 = Automatic slave selection function Disabled 132 * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]). 133 * | | |1 = Automatic slave selection function Enabled. 134 * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit 135 * | | |0 = Slave mode bit count error interrupt Disabled. 136 * | | |1 = Slave mode bit count error interrupt Enabled. 137 * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit 138 * | | |0 = Slave mode TX under run interrupt Disabled. 139 * | | |1 = Slave mode TX under run interrupt Enabled. 140 * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit 141 * | | |0 = Slave select active interrupt Disabled. 142 * | | |1 = Slave select active interrupt Enabled. 143 * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit 144 * | | |0 = Slave select inactive interrupt Disabled. 145 * | | |1 = Slave select inactive interrupt Enabled. 146 * @var SPI_T::PDMACTL 147 * Offset: 0x0C SPI PDMA Control Register 148 * --------------------------------------------------------------------------------------------------- 149 * |Bits |Field |Descriptions 150 * | :----: | :----: | :---- | 151 * |[0] |TXPDMAEN |Transmit PDMA Enable Bit 152 * | | |0 = Transmit PDMA function Disabled. 153 * | | |1 = Transmit PDMA function Enabled. 154 * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function 155 * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. 156 * |[1] |RXPDMAEN |Receive PDMA Enable Bit 157 * | | |0 = Receive PDMA function Disabled. 158 * | | |1 = Receive PDMA function Enabled. 159 * |[2] |PDMARST |PDMA Reset 160 * | | |0 = No effect. 161 * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. 162 * @var SPI_T::FIFOCTL 163 * Offset: 0x10 SPI FIFO Control Register 164 * --------------------------------------------------------------------------------------------------- 165 * |Bits |Field |Descriptions 166 * | :----: | :----: | :---- | 167 * |[0] |RXRST |Receive Reset 168 * | | |0 = No effect. 169 * | | |1 = Reset receive FIFO pointer and receive circuit 170 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 171 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 172 * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. 173 * |[1] |TXRST |Transmit Reset 174 * | | |0 = No effect. 175 * | | |1 = Reset transmit FIFO pointer and transmit circuit 176 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 177 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 178 * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. 179 * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 180 * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit 181 * | | |0 = RX FIFO threshold interrupt Disabled. 182 * | | |1 = RX FIFO threshold interrupt Enabled. 183 * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit 184 * | | |0 = TX FIFO threshold interrupt Disabled. 185 * | | |1 = TX FIFO threshold interrupt Enabled. 186 * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit 187 * | | |0 = Receive time-out interrupt Disabled. 188 * | | |1 = Receive time-out interrupt Enabled. 189 * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit 190 * | | |0 = Receive FIFO overrun interrupt Disabled. 191 * | | |1 = Receive FIFO overrun interrupt Enabled. 192 * |[6] |TXUFPOL |TX Underflow Data Polarity 193 * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. 194 * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. 195 * | | |Note: 196 * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. 197 * | | |2. This bit should be set as 0 in I2S mode. 198 * | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward 199 * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 200 * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit 201 * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1 202 * | | |This bit is used to enable the TX underflow interrupt. 203 * | | |0 = Slave TX underflow interrupt Disabled. 204 * | | |1 = Slave TX underflow interrupt Enabled. 205 * |[8] |RXFBCLR |Receive FIFO Buffer Clear 206 * | | |0 = No effect. 207 * | | |1 = Clear receive FIFO pointer 208 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 209 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 210 * | | |Note: The RX shift register will not be cleared. 211 * |[9] |TXFBCLR |Transmit FIFO Buffer Clear 212 * | | |0 = No effect. 213 * | | |1 = Clear transmit FIFO pointer 214 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 215 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 216 * | | |Note: The TX shift register will not be cleared. 217 * |[26:24] |RXTH |Receive FIFO Threshold 218 * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 219 * | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 220 * |[30:28] |TXTH |Transmit FIFO Threshold 221 * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 222 * | | |For SPI1~SPI4, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length 223 * @var SPI_T::STATUS 224 * Offset: 0x14 SPI Status Register 225 * --------------------------------------------------------------------------------------------------- 226 * |Bits |Field |Descriptions 227 * | :----: | :----: | :---- | 228 * |[0] |BUSY |Busy Status (Read Only) 229 * | | |0 = SPI controller is in idle state. 230 * | | |1 = SPI controller is in busy state. 231 * | | |The following listing are the bus busy conditions: 232 * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0. 233 * | | |b 234 * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. 235 * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1. 236 * | | |d 237 * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active. 238 * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. 239 * |[1] |UNITIF |Unit Transfer Interrupt Flag 240 * | | |0 = No transaction has been finished since this bit was cleared to 0. 241 * | | |1 = SPI controller has finished one unit transfer. 242 * | | |Note: This bit will be cleared by writing 1 to it. 243 * |[2] |SSACTIF |Slave Select Active Interrupt Flag 244 * | | |0 = Slave select active interrupt was cleared or not occurred. 245 * | | |1 = Slave select active interrupt event occurred. 246 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 247 * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag 248 * | | |0 = Slave select inactive interrupt was cleared or not occurred. 249 * | | |1 = Slave select inactive interrupt event occurred. 250 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 251 * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) 252 * | | |0 = The slave select line status is 0. 253 * | | |1 = The slave select line status is 1. 254 * | | |Note: This bit is only available in Slave mode 255 * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 256 * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag 257 * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. 258 * | | |0 = No Slave mode bit count error event. 259 * | | |1 = Slave mode bit count error event occurs. 260 * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state 261 * | | |This bit will be cleared by writing 1 to it. 262 * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag 263 * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. 264 * | | |0 = No Slave TX under run event. 265 * | | |1 = Slave TX under run event occurs. 266 * | | |Note: This bit will be cleared by writing 1 to it. 267 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) 268 * | | |0 = Receive FIFO buffer is not empty. 269 * | | |1 = Receive FIFO buffer is empty. 270 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) 271 * | | |0 = Receive FIFO buffer is not full. 272 * | | |1 = Receive FIFO buffer is full. 273 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) 274 * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. 275 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. 276 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag 277 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 278 * | | |0 = No FIFO is overrun. 279 * | | |1 = Receive FIFO is overrun. 280 * | | |Note: This bit will be cleared by writing 1 to it. 281 * |[12] |RXTOIF |Receive Time-out Interrupt Flag 282 * | | |0 = No receive FIFO time-out event. 283 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode 284 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. 285 * | | |Note: This bit will be cleared by writing 1 to it. 286 * |[15] |SPIENSTS |SPI Enable Status (Read Only) 287 * | | |0 = The SPI controller is disabled. 288 * | | |1 = The SPI controller is enabled. 289 * | | |Note: The SPI peripheral clock is asynchronous with the system clock 290 * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 291 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) 292 * | | |0 = Transmit FIFO buffer is not empty. 293 * | | |1 = Transmit FIFO buffer is empty. 294 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) 295 * | | |0 = Transmit FIFO buffer is not full. 296 * | | |1 = Transmit FIFO buffer is full. 297 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) 298 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. 299 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. 300 * |[19] |TXUFIF |TX Underflow Interrupt Flag 301 * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. 302 * | | |0 = No effect. 303 * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. 304 * | | |Note 1: This bit will be cleared by writing 1 to it. 305 * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 306 * |[23] |TXRXRST |TX or RX Reset Status (Read Only) 307 * | | |0 = The reset function of TXRST or RXRST is done. 308 * | | |1 = Doing the reset function of TXRST or RXRST. 309 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles 310 * | | |User can check the status of this bit to monitor the reset function is doing or done. 311 * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) 312 * | | |This bit field indicates the valid data count of receive FIFO buffer. 313 * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) 314 * | | |This bit field indicates the valid data count of transmit FIFO buffer. 315 * @var SPI_T::TX 316 * Offset: 0x20 SPI Data Transmit Register 317 * --------------------------------------------------------------------------------------------------- 318 * |Bits |Field |Descriptions 319 * | :----: | :----: | :---- | 320 * |[31:0] |TX |Data Transmit Register 321 * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers 322 * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. 323 * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted 324 * | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer. 325 * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0] 326 * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section 327 * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 328 * @var SPI_T::RX 329 * Offset: 0x30 SPI Data Receive Register 330 * --------------------------------------------------------------------------------------------------- 331 * |Bits |Field |Descriptions 332 * | :----: | :----: | :---- | 333 * |[31:0] |RX |Data Receive Register 334 * | | |There are 4-level FIFO buffers in this controller 335 * | | |The data receive register holds the data received from SPI data input pin 336 * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register 337 * | | |This is a read only register. 338 * @var SPI_T::I2SCTL 339 * Offset: 0x60 I2S Control Register 340 * --------------------------------------------------------------------------------------------------- 341 * |Bits |Field |Descriptions 342 * | :----: | :----: | :---- | 343 * |[0] |I2SEN |I2S Controller Enable Bit 344 * | | |0 = Disabled I2S mode. 345 * | | |1 = Enabled I2S mode. 346 * | | |Note: 347 * | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode. 348 * | | |2 349 * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 350 * |[1] |TXEN |Transmit Enable Bit 351 * | | |0 = Data transmit Disabled. 352 * | | |1 = Data transmit Enabled. 353 * |[2] |RXEN |Receive Enable Bit 354 * | | |0 = Data receive Disabled. 355 * | | |1 = Data receive Enabled. 356 * |[3] |MUTE |Transmit Mute Enable Bit 357 * | | |0 = Transmit data is shifted from buffer. 358 * | | |1 = Transmit channel zero. 359 * |[5:4] |WDWIDTH |Word Width 360 * | | |00 = data size is 8-bit. 361 * | | |01 = data size is 16-bit. 362 * | | |10 = data size is 24-bit. 363 * | | |11 = data size is 32-bit. 364 * |[6] |MONO |Monaural Data 365 * | | |0 = Data is stereo format. 366 * | | |1 = Data is monaural format. 367 * |[7] |ORDER |Stereo Data Order in FIFO 368 * | | |0 = Left channel data at high byte. 369 * | | |1 = Left channel data at low byte. 370 * |[8] |SLAVE |Slave Mode 371 * | | |I2S can operate as master or slave 372 * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M480 series to audio CODEC chip 373 * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 374 * | | |0 = Master mode. 375 * | | |1 = Slave mode. 376 * |[15] |MCLKEN |Master Clock Enable Bit 377 * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 378 * | | |0 = Master clock Disabled. 379 * | | |1 = Master clock Enabled. 380 * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit 381 * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1 382 * | | |This function is only available in transmit operation. 383 * | | |0 = Right channel zero cross detection Disabled. 384 * | | |1 = Right channel zero cross detection Enabled. 385 * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit 386 * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1 387 * | | |This function is only available in transmit operation. 388 * | | |0 = Left channel zero cross detection Disabled. 389 * | | |1 = Left channel zero cross detection Enabled. 390 * |[23] |RXLCH |Receive Left Channel Enable Bit 391 * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. 392 * | | |0 = Receive right channel data in Mono mode. 393 * | | |1 = Receive left channel data in Mono mode. 394 * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit 395 * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 396 * | | |0 = Interrupt Disabled. 397 * | | |1 = Interrupt Enabled. 398 * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit 399 * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 400 * | | |0 = Interrupt Disabled. 401 * | | |1 = Interrupt Enabled. 402 * |[29:28] |FORMAT |Data Format Selection 403 * | | |00 = I2S data format. 404 * | | |01 = MSB justified data format. 405 * | | |10 = PCM mode A. 406 * | | |11 = PCM mode B. 407 * @var SPI_T::I2SCLK 408 * Offset: 0x64 I2S Clock Divider Control Register 409 * --------------------------------------------------------------------------------------------------- 410 * |Bits |Field |Descriptions 411 * | :----: | :----: | :---- | 412 * |[6:0] |MCLKDIV |Master Clock Divider 413 * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices 414 * | | |The frequency of master clock, fMCLK, is determined by the following expressions: 415 * | | |If MCLKDIV >= 1,. 416 * | | |If MCLKDIV = 0,. 417 * | | |where 418 * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2 419 * | | |In general, the master clock rate is 256 times sampling clock rate. 420 * |[17:8] |BCLKDIV |Bit Clock Divider 421 * | | |The I2S controller will generate bit clock in Master mode 422 * | | |The clock frequency of bit clock , fBCLK, is determined by the following expression: 423 * | | |where 424 * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. 425 * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . 426 * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. 427 * @var SPI_T::I2SSTS 428 * Offset: 0x68 I2S Status Register 429 * --------------------------------------------------------------------------------------------------- 430 * |Bits |Field |Descriptions 431 * | :----: | :----: | :---- | 432 * |[4] |RIGHT |Right Channel (Read Only) 433 * | | |This bit indicates the current transmit data is belong to which channel. 434 * | | |0 = Left channel. 435 * | | |1 = Right channel. 436 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) 437 * | | |0 = Receive FIFO buffer is not empty. 438 * | | |1 = Receive FIFO buffer is empty. 439 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) 440 * | | |0 = Receive FIFO buffer is not full. 441 * | | |1 = Receive FIFO buffer is full. 442 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) 443 * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. 444 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. 445 * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. 446 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag 447 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 448 * | | |Note: This bit will be cleared by writing 1 to it. 449 * |[12] |RXTOIF |Receive Time-out Interrupt Flag 450 * | | |0 = No receive FIFO time-out event. 451 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode 452 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. 453 * | | |Note: This bit will be cleared by writing 1 to it. 454 * |[15] |I2SENSTS |I2S Enable Status (Read Only) 455 * | | |0 = The SPI/I2S control logic is disabled. 456 * | | |1 = The SPI/I2S control logic is enabled. 457 * | | |Note: The SPI peripheral clock is asynchronous with the system clock 458 * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 459 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) 460 * | | |0 = Transmit FIFO buffer is not empty. 461 * | | |1 = Transmit FIFO buffer is empty. 462 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) 463 * | | |0 = Transmit FIFO buffer is not full. 464 * | | |1 = Transmit FIFO buffer is full. 465 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) 466 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. 467 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. 468 * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. 469 * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag 470 * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. 471 * | | |Note: This bit will be cleared by writing 1 to it. 472 * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag 473 * | | |0 = No zero cross event occurred on right channel. 474 * | | |1 = Zero cross event occurred on right channel. 475 * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag 476 * | | |0 = No zero cross event occurred on left channel. 477 * | | |1 = Zero cross event occurred on left channel. 478 * |[23] |TXRXRST |TX or RX Reset Status (Read Only) 479 * | | |0 = The reset function of TXRST or RXRST is done. 480 * | | |1 = Doing the reset function of TXRST or RXRST. 481 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles 482 * | | |User can check the status of this bit to monitor the reset function is doing or done. 483 * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) 484 * | | |This bit field indicates the valid data count of receive FIFO buffer. 485 * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) 486 * | | |This bit field indicates the valid data count of transmit FIFO buffer. 487 */ 488 __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ 489 __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ 490 __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ 491 __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ 492 __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ 493 __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ 494 /// @cond HIDDEN_SYMBOLS 495 __I uint32_t RESERVE0[2]; 496 /// @endcond //HIDDEN_SYMBOLS 497 __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ 498 /// @cond HIDDEN_SYMBOLS 499 __I uint32_t RESERVE1[3]; 500 /// @endcond //HIDDEN_SYMBOLS 501 __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ 502 /// @cond HIDDEN_SYMBOLS 503 __I uint32_t RESERVE2[11]; 504 /// @endcond //HIDDEN_SYMBOLS 505 __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ 506 __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ 507 __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ 508 509 } SPI_T; 510 511 /** 512 @addtogroup SPI_CONST SPI Bit Field Definition 513 Constant Definitions for SPI Controller 514 @{ */ 515 516 #define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ 517 #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ 518 519 #define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ 520 #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ 521 522 #define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ 523 #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ 524 525 #define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ 526 #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ 527 528 #define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ 529 #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ 530 531 #define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ 532 #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ 533 534 #define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ 535 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ 536 537 #define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ 538 #define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ 539 540 #define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ 541 #define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ 542 543 #define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ 544 #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ 545 546 #define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ 547 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ 548 549 #define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ 550 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ 551 552 #define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ 553 #define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ 554 555 #define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ 556 #define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ 557 558 #define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ 559 #define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ 560 561 #define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ 562 #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ 563 564 #define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ 565 #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ 566 567 #define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ 568 #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ 569 570 #define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ 571 #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ 572 573 #define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ 574 #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ 575 576 #define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ 577 #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ 578 579 #define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */ 580 #define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */ 581 582 #define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ 583 #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ 584 585 #define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ 586 #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ 587 588 #define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ 589 #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ 590 591 #define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ 592 #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ 593 594 #define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ 595 #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ 596 597 #define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ 598 #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ 599 600 #define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ 601 #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ 602 603 #define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ 604 #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ 605 606 #define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ 607 #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ 608 609 #define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ 610 #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ 611 612 #define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ 613 #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ 614 615 #define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ 616 #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ 617 618 #define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ 619 #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ 620 621 #define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ 622 #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ 623 624 #define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ 625 #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ 626 627 #define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ 628 #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ 629 630 #define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ 631 #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ 632 633 #define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ 634 #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ 635 636 #define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ 637 #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ 638 639 #define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ 640 #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ 641 642 #define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ 643 #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ 644 645 #define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ 646 #define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ 647 648 #define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ 649 #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ 650 651 #define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ 652 #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ 653 654 #define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ 655 #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ 656 657 #define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ 658 #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ 659 660 #define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ 661 #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ 662 663 #define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ 664 #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ 665 666 #define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ 667 #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ 668 669 #define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ 670 #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ 671 672 #define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ 673 #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ 674 675 #define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ 676 #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ 677 678 #define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ 679 #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ 680 681 #define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ 682 #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ 683 684 #define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ 685 #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ 686 687 #define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ 688 #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ 689 690 #define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ 691 #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ 692 693 #define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ 694 #define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ 695 696 #define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ 697 #define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ 698 699 #define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ 700 #define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ 701 702 #define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ 703 #define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ 704 705 #define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ 706 #define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ 707 708 #define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ 709 #define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ 710 711 #define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ 712 #define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ 713 714 #define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ 715 #define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ 716 717 #define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ 718 #define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ 719 720 #define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ 721 #define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ 722 723 #define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ 724 #define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ 725 726 #define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ 727 #define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ 728 729 #define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ 730 #define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ 731 732 #define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ 733 #define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ 734 735 #define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ 736 #define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ 737 738 #define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ 739 #define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ 740 741 #define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ 742 #define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ 743 744 #define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ 745 #define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ 746 747 #define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ 748 #define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ 749 750 #define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ 751 #define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ 752 753 #define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ 754 #define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ 755 756 #define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ 757 #define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ 758 759 #define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ 760 #define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ 761 762 #define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ 763 #define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ 764 765 #define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ 766 #define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ 767 768 #define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ 769 #define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ 770 771 #define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ 772 #define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ 773 774 #define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ 775 #define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ 776 777 #define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ 778 #define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ 779 780 #define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ 781 #define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ 782 783 #define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ 784 #define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ 785 786 #define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ 787 #define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ 788 789 #define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ 790 #define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ 791 792 /**@}*/ /* SPI_CONST */ 793 /**@}*/ /* end of SPI register group */ 794 /**@}*/ /* end of REGISTER group */ 795 796 #if defined ( __CC_ARM ) 797 #pragma no_anon_unions 798 #endif 799 800 #endif /* __SPI_REG_H__ */ 801
