1 /****************************************************************************//**
2 * @file i2s.h
3 * @version V0.10
4 * @brief M480 I2S driver header file
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __I2S_H__
10 #define __I2S_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17 /** @addtogroup Standard_Driver Standard Driver
18 @{
19 */
20
21 /** @addtogroup I2S_Driver I2S Driver
22 @{
23 */
24
25 /** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants
26 @{
27 */
28 #define I2S_DATABIT_8 (0U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
29 #define I2S_DATABIT_16 (1U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
30 #define I2S_DATABIT_24 (2U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
31 #define I2S_DATABIT_32 (3U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
32
33 /* Audio Format */
34 #define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */
35 #define I2S_DISABLE_MONO (0U) /*!< Stereo channel \hideinitializer */
36
37 /* I2S Data Format */
38 #define I2S_FORMAT_I2S (0U << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */
39 #define I2S_FORMAT_I2S_MSB (1U << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */
40 #define I2S_FORMAT_I2S_LSB (2U << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */
41 #define I2S_FORMAT_PCM (4U << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */
42 #define I2S_FORMAT_PCM_MSB (5U << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */
43 #define I2S_FORMAT_PCM_LSB (6U << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */
44
45 /* I2S Data Format */
46 #define I2S_ORDER_AT_MSB (0U) /*!< Channel data is at MSB \hideinitializer */
47 #define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */
48
49 /* I2S TDM Channel Number */
50 #define I2S_TDM_2CH 0U /*!< Use TDM 2 channel \hideinitializer */
51 #define I2S_TDM_4CH 1U /*!< Use TDM 4 channel \hideinitializer */
52 #define I2S_TDM_6CH 2U /*!< Use TDM 6 channel \hideinitializer */
53 #define I2S_TDM_8CH 3U /*!< Use TDM 8 channel \hideinitializer */
54
55 /* I2S TDM Channel Width */
56 #define I2S_TDM_WIDTH_8BIT 0U /*!< TDM channel witch is 8-bit \hideinitializer */
57 #define I2S_TDM_WIDTH_16BIT 1U /*!< TDM channel witch is 16-bit \hideinitializer */
58 #define I2S_TDM_WIDTH_24BIT 2U /*!< TDM channel witch is 24-bit \hideinitializer */
59 #define I2S_TDM_WIDTH_32BIT 3U /*!< TDM channel witch is 32-bit \hideinitializer */
60
61 /* I2S TDM Sync Width */
62 #define I2S_TDM_SYNC_ONE_BCLK 0U /*!< TDM sync widht is one BLCK period \hideinitializer */
63 #define I2S_TDM_SYNC_ONE_CHANNEL 1U /*!< TDM sync widht is one channel period \hideinitializer */
64
65 /* I2S Operation mode */
66 #define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */
67 #define I2S_MODE_MASTER (0u) /*!< As master mode \hideinitializer */
68
69 /* I2S FIFO Threshold */
70 #define I2S_FIFO_TX_LEVEL_WORD_0 (0U) /*!< TX threshold is 0 word \hideinitializer */
71 #define I2S_FIFO_TX_LEVEL_WORD_1 (1U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
72 #define I2S_FIFO_TX_LEVEL_WORD_2 (2U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
73 #define I2S_FIFO_TX_LEVEL_WORD_3 (3U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
74 #define I2S_FIFO_TX_LEVEL_WORD_4 (4U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */
75 #define I2S_FIFO_TX_LEVEL_WORD_5 (5U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */
76 #define I2S_FIFO_TX_LEVEL_WORD_6 (6U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */
77 #define I2S_FIFO_TX_LEVEL_WORD_7 (7U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */
78 #define I2S_FIFO_TX_LEVEL_WORD_8 (8U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */
79 #define I2S_FIFO_TX_LEVEL_WORD_9 (9U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */
80 #define I2S_FIFO_TX_LEVEL_WORD_10 (10U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */
81 #define I2S_FIFO_TX_LEVEL_WORD_11 (11U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */
82 #define I2S_FIFO_TX_LEVEL_WORD_12 (12U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */
83 #define I2S_FIFO_TX_LEVEL_WORD_13 (13U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */
84 #define I2S_FIFO_TX_LEVEL_WORD_14 (14U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */
85 #define I2S_FIFO_TX_LEVEL_WORD_15 (15U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */
86
87 #define I2S_FIFO_RX_LEVEL_WORD_1 (0U) /*!< RX threshold is 1 word \hideinitializer */
88 #define I2S_FIFO_RX_LEVEL_WORD_2 (1U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
89 #define I2S_FIFO_RX_LEVEL_WORD_3 (2U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
90 #define I2S_FIFO_RX_LEVEL_WORD_4 (3U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
91 #define I2S_FIFO_RX_LEVEL_WORD_5 (4U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */
92 #define I2S_FIFO_RX_LEVEL_WORD_6 (5U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */
93 #define I2S_FIFO_RX_LEVEL_WORD_7 (6U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */
94 #define I2S_FIFO_RX_LEVEL_WORD_8 (7U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */
95 #define I2S_FIFO_RX_LEVEL_WORD_9 (8U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */
96 #define I2S_FIFO_RX_LEVEL_WORD_10 (9U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */
97 #define I2S_FIFO_RX_LEVEL_WORD_11 (10U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */
98 #define I2S_FIFO_RX_LEVEL_WORD_12 (11U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */
99 #define I2S_FIFO_RX_LEVEL_WORD_13 (12U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */
100 #define I2S_FIFO_RX_LEVEL_WORD_14 (13U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */
101 #define I2S_FIFO_RX_LEVEL_WORD_15 (14U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */
102 #define I2S_FIFO_RX_LEVEL_WORD_16 (15U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */
103
104 /* I2S Record Channel */
105 #define I2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */
106 #define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
107
108 /* I2S Channel */
109 #define I2S_RIGHT (0U) /*!< Select right channel \hideinitializer */
110 #define I2S_LEFT (1U) /*!< Select left channel \hideinitializer */
111
112 /*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */
113
114 /** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions
115 @{
116 */
117 /*---------------------------------------------------------------------------------------------------------*/
118 /* inline functions */
119 /*---------------------------------------------------------------------------------------------------------*/
120 /**
121 * @brief Enable zero cross detect function.
122 * @param[in] i2s is the base address of I2S module.
123 * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
124 * @return none
125 * \hideinitializer
126 */
I2S_ENABLE_TX_ZCD(I2S_T * i2s,uint32_t u32ChMask)127 __STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
128 {
129 if((u32ChMask > 0U) && (u32ChMask < 9U))
130 {
131 i2s->CTL1 |= ((uint32_t)1U << (u32ChMask-1U));
132 }
133 }
134
135 /**
136 * @brief Disable zero cross detect function.
137 * @param[in] i2s is the base address of I2S module.
138 * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
139 * @return none
140 * \hideinitializer
141 */
I2S_DISABLE_TX_ZCD(I2S_T * i2s,uint32_t u32ChMask)142 __STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
143 {
144 if((u32ChMask > 0U) && (u32ChMask < 9U))
145 {
146 i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask-1U));
147 }
148 }
149
150 /**
151 * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
152 * @param[in] i2s is the base address of I2S module.
153 * @return none
154 * \hideinitializer
155 */
156 #define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )
157
158 /**
159 * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
160 * @param[in] i2s is the base address of I2S module.
161 * @return none
162 * \hideinitializer
163 */
164 #define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )
165
166 /**
167 * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
168 * @param[in] i2s is the base address of I2S module.
169 * @return none
170 * \hideinitializer
171 */
172 #define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )
173
174 /**
175 * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
176 * @param[in] i2s is the base address of I2S module.
177 * @return none
178 * \hideinitializer
179 */
180 #define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )
181
182 /**
183 * @brief Enable I2S Tx function .
184 * @param[in] i2s is the base address of I2S module.
185 * @return none
186 * \hideinitializer
187 */
188 #define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )
189
190 /**
191 * @brief Disable I2S Tx function .
192 * @param[in] i2s is the base address of I2S module.
193 * @return none
194 * \hideinitializer
195 */
196 #define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )
197
198 /**
199 * @brief Enable I2S Rx function .
200 * @param[in] i2s is the base address of I2S module.
201 * @return none
202 * \hideinitializer
203 */
204 #define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )
205
206 /**
207 * @brief Disable I2S Rx function .
208 * @param[in] i2s is the base address of I2S module.
209 * @return none
210 * \hideinitializer
211 */
212 #define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )
213
214 /**
215 * @brief Enable Tx Mute function .
216 * @param[in] i2s is the base address of I2S module.
217 * @return none
218 * \hideinitializer
219 */
220 #define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )
221
222 /**
223 * @brief Disable Tx Mute function .
224 * @param[in] i2s is the base address of I2S module.
225 * @return none
226 * \hideinitializer
227 */
228 #define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )
229
230 /**
231 * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
232 * @param[in] i2s is the base address of I2S module.
233 * @return none
234 * \hideinitializer
235 */
236 #define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )
237
238 /**
239 * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
240 * @param[in] i2s is the base address of I2S module.
241 * @return none
242 * \hideinitializer
243 */
244 #define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )
245
246 /**
247 * @brief This function sets the recording source channel when mono mode is used.
248 * @param[in] i2s is the base address of I2S module.
249 * @param[in] u32Ch left or right channel. Valid values are:
250 * - \ref I2S_MONO_LEFT
251 * - \ref I2S_MONO_RIGHT
252 * @return none
253 * \hideinitializer
254 */
I2S_SET_MONO_RX_CHANNEL(I2S_T * i2s,uint32_t u32Ch)255 __STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
256 {
257 u32Ch == I2S_MONO_LEFT ?
258 (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :
259 (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);
260 }
261
262 /**
263 * @brief Write data to I2S Tx FIFO.
264 * @param[in] i2s is the base address of I2S module.
265 * @param[in] u32Data: The data written to FIFO.
266 * @return none
267 * \hideinitializer
268 */
269 #define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) )
270
271 /**
272 * @brief Read Rx FIFO.
273 * @param[in] i2s is the base address of I2S module.
274 * @return Data in Rx FIFO.
275 * \hideinitializer
276 */
277 #define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
278
279 /**
280 * @brief This function gets the interrupt flag according to the mask parameter.
281 * @param[in] i2s is the base address of I2S module.
282 * @param[in] u32Mask is the mask for the all interrupt flags.
283 * @return The masked bit value of interrupt flag.
284 * \hideinitializer
285 */
286 #define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )
287
288 /**
289 * @brief This function clears the interrupt flag according to the mask parameter.
290 * @param[in] i2s is the base address of I2S module.
291 * @param[in] u32Mask is the mask for the all interrupt flags.
292 * @return none
293 * \hideinitializer
294 */
295 #define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )
296
297 /**
298 * @brief This function gets the zero crossing interrupt flag according to the mask parameter.
299 * @param[in] i2s is the base address of I2S module.
300 * @param[in] u32Mask is the mask for the all interrupt flags.
301 * @return The masked bit value of interrupt flag.
302 * \hideinitializer
303 */
304 #define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )
305
306 /**
307 * @brief This function clears the zero crossing interrupt flag according to the mask parameter.
308 * @param[in] i2s is the base address of I2S module.
309 * @param[in] u32Mask is the mask for the all interrupt flags.
310 * @return none
311 * \hideinitializer
312 */
313 #define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )
314
315 /**
316 * @brief Get transmit FIFO level
317 * @param[in] i2s is the base address of I2S module.
318 * @return FIFO level
319 * \hideinitializer
320 */
321 #define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )
322
323 /**
324 * @brief Get receive FIFO level
325 * @param[in] i2s is the base address of I2S module.
326 * @return FIFO level
327 * \hideinitializer
328 */
329 #define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )
330
331 void I2S_Close(I2S_T *i2s);
332 void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
333 void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
334 uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
335 void I2S_DisableMCLK(I2S_T *i2s);
336 void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
337 void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);
338 uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat);
339
340 /*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
341
342
343 /*@}*/ /* end of group I2S_Driver */
344
345 /*@}*/ /* end of group Standard_Driver */
346 #ifdef __cplusplus
347 }
348 #endif
349
350 #endif
351
352 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
353
354
