1 /**************************************************************************//** 2 * @file fmc_reg.h 3 * @version V1.00 4 * @brief FMC register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __FMC_REG_H__ 10 #define __FMC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup FMC Flash Memory Controller(FMC) 23 Memory Mapped Structure for FMC Controller 24 @{ */ 25 26 typedef struct 27 { 28 /** 29 * @var FMC_T::ISPCTL 30 * Offset: 0x00 ISP Control Register 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[0] |ISPEN |ISP Enable Bit (Write Protect) 35 * | | |ISP function enable bit. Set this bit to enable ISP function. 36 * | | |0 = ISP function Disabled. 37 * | | |1 = ISP function Enabled. 38 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 39 * |[1] |BS |Boot Select (Write Protect) 40 * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively 41 * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from 42 * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 43 * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. 44 * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. 45 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 46 * |[2] |SPUEN |SPROM Update Enable Bit (Write Protect) 47 * | | |0 = SPROM cannot be updated. 48 * | | |1 = SPROM can be updated. 49 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 50 * |[3] |APUEN |APROM Update Enable Bit (Write Protect) 51 * | | |0 = APROM cannot be updated when the chip runs in APROM. 52 * | | |1 = APROM can be updated when the chip runs in APROM. 53 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 54 * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) 55 * | | |0 = CONFIG cannot be updated. 56 * | | |1 = CONFIG can be updated. 57 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 58 * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) 59 * | | |LDROM update enable bit. 60 * | | |0 = LDROM cannot be updated. 61 * | | |1 = LDROM can be updated. 62 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 63 * |[6] |ISPFF |ISP Fail Flag (Write Protect) 64 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 65 * | | |This bit needs to be cleared by writing 1 to it. 66 * | | |(1) APROM writes to itself if APUEN is set to 0. 67 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 68 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 69 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 70 * | | |(5) SPROM is programmed at SPROM secured mode. 71 * | | |(6) Page Erase command at LOCK mode with ICE connection 72 * | | |(7) Erase or Program command at brown-out detected 73 * | | |(8) Destination address is illegal, such as over an available range. 74 * | | |(9) Invalid ISP commands 75 * | | |(10) Vector address is mapping to SPROM region 76 * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 77 * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 78 * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 79 * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. 80 * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1 81 * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A 82 * | | |(17) Read any content of boot loader with ICE connection 83 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 84 * |[16] |BL |Boot Loader Booting (Write Protect) 85 * | | |This bit is initiated with the inversed value of MBS (CONFIG0[5]) 86 * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded 87 * | | |This bit is used to check chip boot from Boot Loader or not 88 * | | |User should keep original value of this bit when updating FMC_ISPCTL register. 89 * | | |0 = Booting from APROM or LDROM. 90 * | | |1 = Booting from Boot Loader. 91 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 92 * @var FMC_T::ISPADDR 93 * Offset: 0x04 ISP Address Register 94 * --------------------------------------------------------------------------------------------------- 95 * |Bits |Field |Descriptions 96 * | :----: | :----: | :---- | 97 * |[31:0] |ISPADDR |ISP Address 98 * | | |The NuMicro M480 series is equipped with embedded flash 99 * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation 100 * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. 101 * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation. 102 * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) 103 * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). 104 * @var FMC_T::ISPDAT 105 * Offset: 0x08 ISP Data Register 106 * --------------------------------------------------------------------------------------------------- 107 * |Bits |Field |Descriptions 108 * | :----: | :----: | :---- | 109 * |[31:0] |ISPDAT |ISP Data 110 * | | |Write data to this register before ISP program operation. 111 * | | |Read data from this register after ISP read operation. 112 * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff 113 * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment 114 * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result 115 * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect 116 * @var FMC_T::ISPCMD 117 * Offset: 0x0C ISP Command Register 118 * --------------------------------------------------------------------------------------------------- 119 * |Bits |Field |Descriptions 120 * | :----: | :----: | :---- | 121 * |[6:0] |CMD |ISP Command 122 * | | |ISP command table is shown below: 123 * | | |0x00= FLASH Read. 124 * | | |0x04= Read Unique ID. 125 * | | |0x08= Read Flash All-One Result. 126 * | | |0x0B= Read Company ID. 127 * | | |0x0C= Read Device ID. 128 * | | |0x0D= Read Checksum. 129 * | | |0x21= FLASH 32-bit Program. 130 * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. 131 * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. 132 * | | |0x25= FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1.. 133 * | | |0x27= FLASH Multi-Word Program. 134 * | | |0x28= Run Flash All-One Verification. 135 * | | |0x2D= Run Checksum Calculation. 136 * | | |0x2E= Vector Remap. 137 * | | |0x40= FLASH 64-bit Read. 138 * | | |0x61= FLASH 64-bit Program. 139 * | | |The other commands are invalid. 140 * @var FMC_T::ISPTRG 141 * Offset: 0x10 ISP Trigger Control Register 142 * --------------------------------------------------------------------------------------------------- 143 * |Bits |Field |Descriptions 144 * | :----: | :----: | :---- | 145 * |[0] |ISPGO |ISP Start Trigger (Write Protect) 146 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 147 * | | |0 = ISP operation is finished. 148 * | | |1 = ISP is progressed. 149 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 150 * @var FMC_T::DFBA 151 * Offset: 0x14 Data Flash Base Address 152 * --------------------------------------------------------------------------------------------------- 153 * |Bits |Field |Descriptions 154 * | :----: | :----: | :---- | 155 * |[31:0] |DFBA |Data Flash Base Address 156 * | | |This register indicates Data Flash start address. It is a read only register. 157 * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 158 * | | |This register is valid when DFEN (CONFIG0[0]) =0 . 159 * @var FMC_T::ISPSTS 160 * Offset: 0x40 ISP Status Register 161 * --------------------------------------------------------------------------------------------------- 162 * |Bits |Field |Descriptions 163 * | :----: | :----: | :---- | 164 * |[0] |ISPBUSY |ISP Busy Flag (Read Only) 165 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 166 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 167 * | | |0 = ISP operation is finished. 168 * | | |1 = ISP is progressed. 169 * |[2:1] |CBS |Boot Selection of CONFIG (Read Only) 170 * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 171 * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. 172 * | | |00 = LDROM with IAP mode. 173 * | | |01 = LDROM without IAP mode. 174 * | | |10 = APROM with IAP mode. 175 * | | |11 = APROM without IAP mode. 176 * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) 177 * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 178 * | | |0 = Booting from Boot Loader. 179 * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) 180 * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only) 181 * | | |This bit is set if flash access cycle auto-tuning function is disabled 182 * | | |The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. 183 * | | |0 = Flash access cycle auto-tuning is enabled. 184 * | | |1 = Flash access cycle auto-tuning is disabled. 185 * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) 186 * | | |This bit is set if data is mismatched at ISP programming verification 187 * | | |This bit is clear by performing ISP flash erase or ISP read CID operation 188 * | | |0 = Flash Program is success. 189 * | | |1 = Flash Program is fail. Program data is different with data in the flash memory 190 * |[6] |ISPFF |ISP Fail Flag (Write Protect) 191 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] 192 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 193 * | | |(1) APROM writes to itself if APUEN is set to 0. 194 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 195 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 196 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 197 * | | |(5) SPROM is programmed at SPROM secured mode. 198 * | | |(6) Page Erase command at LOCK mode with ICE connection 199 * | | |(7) Erase or Program command at brown-out detected 200 * | | |(8) Destination address is illegal, such as over an available range. 201 * | | |(9) Invalid ISP commands 202 * | | |(10) Vector address is mapping to SPROM region. 203 * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 204 * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 205 * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 206 * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. 207 * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. 208 * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A 209 * | | |(17) Read any content of boot loader with ICE connection 210 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 211 * |[7] |ALLONE |Flash All-one Verification Flag 212 * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1 213 * | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. 214 * | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete. 215 * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) 216 * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF} 217 * |[31] |SCODE |Security Code Active Flag 218 * | | |This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation. 219 * | | |0 = Secured code is inactive. 220 * | | |1 = Secured code is active. 221 * @var FMC_T::CYCCTL 222 * Offset: 0x4C Flash Access Cycle Control Register 223 * --------------------------------------------------------------------------------------------------- 224 * |Bits |Field |Descriptions 225 * | :----: | :----: | :---- | 226 * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) 227 * | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;. 228 * | | |The HCLK working frequency range range is<27MHz 229 * | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;. 230 * | | | The optimized HCLK working frequency range is 27~54 MHz 231 * | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;. 232 * | | |The optimized HCLK working frequency range is 54~81MHz 233 * | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;. 234 * | | | The optimized HCLK working frequency range is81~108MHz 235 * | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;. 236 * | | |The optimized HCLK working frequency range is 108~135MHz 237 * | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;. 238 * | | | The optimized HCLK working frequency range is 135~162MHz 239 * | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;. 240 * | | | The optimized HCLK working frequency range is 162~192MHz 241 * | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;. 242 * | | |The optimized HCLK working frequency range is >192MHz 243 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 244 * @var FMC_T::KPKEY0 245 * Offset: 0x50 KPROM KEY0 Data Register 246 * --------------------------------------------------------------------------------------------------- 247 * |Bits |Field |Descriptions 248 * | :----: | :----: | :---- | 249 * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only) 250 * | | |Write KPKEY0 data to this register before KEY Comparison operation. 251 * @var FMC_T::KPKEY1 252 * Offset: 0x54 KPROM KEY1 Data Register 253 * --------------------------------------------------------------------------------------------------- 254 * |Bits |Field |Descriptions 255 * | :----: | :----: | :---- | 256 * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only) 257 * | | |Write KPKEY1 data to this register before KEY Comparison operation. 258 * @var FMC_T::KPKEY2 259 * Offset: 0x58 KPROM KEY2 Data Register 260 * --------------------------------------------------------------------------------------------------- 261 * |Bits |Field |Descriptions 262 * | :----: | :----: | :---- | 263 * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only) 264 * | | |Write KPKEY2 data to this register before KEY Comparison operation. 265 * @var FMC_T::KPKEYTRG 266 * Offset: 0x5C KPROM KEY Comparison Trigger Control Register 267 * --------------------------------------------------------------------------------------------------- 268 * |Bits |Field |Descriptions 269 * | :----: | :----: | :---- | 270 * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection) 271 * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished 272 * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0. 273 * | | |0 = KEY comparison operation is finished. 274 * | | |1 = KEY comparison is progressed. 275 * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 276 * |[1] |TCEN |Timeout Counting Enable (Write Protection) 277 * | | |0 = Timeout counting is disabled. 278 * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish. 279 * | | |10 minutes is at least for timeout, and average is about 20 minutes. 280 * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 281 * @var FMC_T::KPKEYSTS 282 * Offset: 0x60 KPROM KEY Comparison Status Register 283 * --------------------------------------------------------------------------------------------------- 284 * |Bits |Field |Descriptions 285 * | :----: | :----: | :---- | 286 * |[0] |KEYBUSY |KEY Comparison Busy (Read Only) 287 * | | |0 = KEY comparison is finished. 288 * | | |1 = KEY comparison is busy. 289 * |[1] |KEYLOCK |KEY LOCK Flag 290 * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection 291 * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0 292 * | | |This bit also can be set to 1 while 293 * | | | - CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or 294 * | | | - KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or 295 * | | | - KEYENROM is programmed a non-0xFF value or 296 * | | | - Timeout event or 297 * | | | - FORBID(FMC_KPKEYSTS[3]) is 1 298 * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection. 299 * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection. 300 * | | |SPROM write protect is depended on SPFLAG. 301 * | | |CONFIG write protect is depended on CFGFLAG 302 * |[2] |KEYMATCH |KEY Match Flag (Read Only) 303 * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched 304 * | | |This bit is also cleared to 0 while 305 * | | | - CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or 306 * | | | - Timeout event or 307 * | | | - KPROM is erased or 308 * | | | - KEYENROM is programmed to a non-0xFF value. 309 * | | | - Chip is in power down mode. 310 * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. 311 * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting. 312 * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only) 313 * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]). 314 * | | |0 = KEY comparison is not forbidden. 315 * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger. 316 * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only) 317 * | | |This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset 318 * | | |This bit is cleared to 0 by hardware while KPROM is erased 319 * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. 320 * | | |0 = Security Key protection is disabled. 321 * | | |1 = Security Key protection is enabled. 322 * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only) 323 * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset 324 * | | |This bit is cleared to 0 by hardware while KPROM is erased 325 * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. 326 * | | |0 = CONFIG write-protection is disabled. 327 * | | |1 = CONFIG write-protection is enabled. 328 * |[6] |SPFLAG |SPROM Write-protection Enabled Flag (Read Only) 329 * | | |This bit is set while the KEYENROM [1] is 0 at power-on or reset 330 * | | |This bit is cleared to 0 by hardware while KPROM is erased 331 * | | |This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0. 332 * | | |0 = SPROM write-protection is disabled. 333 * | | |1 = SPROM write-protection is enabled. 334 * @var FMC_T::KPKEYCNT 335 * Offset: 0x64 KPROM KEY-Unmatched Counting Register 336 * --------------------------------------------------------------------------------------------------- 337 * |Bits |Field |Descriptions 338 * | :----: | :----: | :---- | 339 * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only) 340 * | | |KPKECNT is increased when entry keys is wrong in Security Key protection 341 * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on. 342 * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only) 343 * | | |KPKEMAX is the maximum error key entry number at each power-on 344 * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated 345 * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting 346 * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX. 347 * @var FMC_T::KPCNT 348 * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register 349 * --------------------------------------------------------------------------------------------------- 350 * |Bits |Field |Descriptions 351 * | :----: | :----: | :---- | 352 * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only) 353 * | | |KPCNT is the power-on counting for error key entry in Security Key protection 354 * | | |KPCNT is cleared to 0 if key comparison is matched. 355 * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only) 356 * | | |KPMAX is the power-on maximum number for error key entry 357 * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated 358 * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting 359 * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX 360 * @var FMC_T::MPDAT0 361 * Offset: 0x80 ISP Data0 Register 362 * --------------------------------------------------------------------------------------------------- 363 * |Bits |Field |Descriptions 364 * | :----: | :----: | :---- | 365 * |[31:0] |ISPDAT0 |ISP Data 0 366 * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data 367 * @var FMC_T::MPDAT1 368 * Offset: 0x84 ISP Data1 Register 369 * --------------------------------------------------------------------------------------------------- 370 * |Bits |Field |Descriptions 371 * | :----: | :----: | :---- | 372 * |[31:0] |ISPDAT1 |ISP Data 1 373 * | | |This register is the second 32-bit data for 64-bit/multi-word programming. 374 * @var FMC_T::MPDAT2 375 * Offset: 0x88 ISP Data2 Register 376 * --------------------------------------------------------------------------------------------------- 377 * |Bits |Field |Descriptions 378 * | :----: | :----: | :---- | 379 * |[31:0] |ISPDAT2 |ISP Data 2 380 * | | |This register is the third 32-bit data for multi-word programming. 381 * @var FMC_T::MPDAT3 382 * Offset: 0x8C ISP Data3 Register 383 * --------------------------------------------------------------------------------------------------- 384 * |Bits |Field |Descriptions 385 * | :----: | :----: | :---- | 386 * |[31:0] |ISPDAT3 |ISP Data 3 387 * | | |This register is the fourth 32-bit data for multi-word programming. 388 * @var FMC_T::MPSTS 389 * Offset: 0xC0 ISP Multi-Program Status Register 390 * --------------------------------------------------------------------------------------------------- 391 * |Bits |Field |Descriptions 392 * | :----: | :----: | :---- | 393 * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) 394 * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. 395 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 396 * | | |0 = ISP Multi-Word program operation is finished. 397 * | | |1 = ISP Multi-Word program operation is progressed. 398 * |[1] |PPGO |ISP Multi-program Status (Read Only) 399 * | | |0 = ISP multi-word program operation is not active. 400 * | | |1 = ISP multi-word program operation is in progress. 401 * |[2] |ISPFF |ISP Fail Flag (Read Only) 402 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] 403 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 404 * | | |(1) APROM writes to itself if APUEN is set to 0. 405 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 406 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 407 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 408 * | | |(5) SPROM is programmed at SPROM secured mode. 409 * | | |(6) Page Erase command at LOCK mode with ICE connection 410 * | | |(7) Erase or Program command at brown-out detected 411 * | | |(8) Destination address is illegal, such as over an available range. 412 * | | |(9) Invalid ISP commands 413 * | | |(10) Vector address is mapping to SPROM region. 414 * |[4] |D0 |ISP DATA 0 Flag (Read Only) 415 * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. 416 * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. 417 * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. 418 * |[5] |D1 |ISP DATA 1 Flag (Read Only) 419 * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. 420 * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. 421 * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. 422 * |[6] |D2 |ISP DATA 2 Flag (Read Only) 423 * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. 424 * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. 425 * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. 426 * |[7] |D3 |ISP DATA 3 Flag (Read Only) 427 * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. 428 * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. 429 * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. 430 * @var FMC_T::MPADDR 431 * Offset: 0xC4 ISP Multi-Program Address Register 432 * --------------------------------------------------------------------------------------------------- 433 * |Bits |Field |Descriptions 434 * | :----: | :----: | :---- | 435 * |[31:0] |MPADDR |ISP Multi-word Program Address 436 * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. 437 * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. 438 */ 439 __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ 440 __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ 441 __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ 442 __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ 443 __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ 444 __I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */ 445 /// @cond HIDDEN_SYMBOLS 446 __I uint32_t RESERVE0[10]; 447 /// @endcond //HIDDEN_SYMBOLS 448 __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ 449 /// @cond HIDDEN_SYMBOLS 450 __I uint32_t RESERVE1[2]; 451 /// @endcond //HIDDEN_SYMBOLS 452 __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ 453 __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */ 454 __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */ 455 __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */ 456 __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */ 457 __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */ 458 __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */ 459 __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */ 460 /// @cond HIDDEN_SYMBOLS 461 __I uint32_t RESERVE2[5]; 462 /// @endcond //HIDDEN_SYMBOLS 463 __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ 464 __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ 465 __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ 466 __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ 467 /// @cond HIDDEN_SYMBOLS 468 __I uint32_t RESERVE3[12]; 469 /// @endcond //HIDDEN_SYMBOLS 470 __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ 471 __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ 472 /// @cond HIDDEN_SYMBOLS 473 __I uint32_t RESERVE4[2]; 474 /// @endcond //HIDDEN_SYMBOLS 475 __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */ 476 __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */ 477 __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */ 478 __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */ 479 __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */ 480 481 } FMC_T; 482 483 /** 484 @addtogroup FMC_CONST FMC Bit Field Definition 485 Constant Definitions for FMC Controller 486 @{ */ 487 488 #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ 489 #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ 490 491 #define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ 492 #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ 493 494 #define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */ 495 #define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */ 496 497 #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ 498 #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ 499 500 #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ 501 #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ 502 503 #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ 504 #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ 505 506 #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ 507 #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ 508 509 #define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */ 510 #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */ 511 512 #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ 513 #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ 514 515 #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ 516 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ 517 518 #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ 519 #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ 520 521 #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ 522 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ 523 524 #define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */ 525 #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */ 526 527 #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ 528 #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ 529 530 #define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */ 531 #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ 532 533 #define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ 534 #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ 535 536 #define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */ 537 #define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */ 538 539 #define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ 540 #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ 541 542 #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ 543 #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ 544 545 #define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ 546 #define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ 547 548 #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ 549 #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ 550 551 #define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */ 552 #define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */ 553 554 #define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ 555 #define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ 556 557 #define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */ 558 #define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */ 559 560 #define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */ 561 #define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */ 562 563 #define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */ 564 #define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */ 565 566 #define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */ 567 #define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */ 568 569 #define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */ 570 #define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */ 571 572 #define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */ 573 #define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */ 574 575 #define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */ 576 #define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */ 577 578 #define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */ 579 #define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */ 580 581 #define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */ 582 #define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */ 583 584 #define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */ 585 #define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */ 586 587 #define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */ 588 #define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */ 589 590 #define FMC_KPKEYSTS_SPFLAG_Pos (6) /*!< FMC_T::KPKEYSTS: SPFLAG Position */ 591 #define FMC_KPKEYSTS_SPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SPFLAG Mask */ 592 593 #define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */ 594 #define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */ 595 596 #define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */ 597 #define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */ 598 599 #define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */ 600 #define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */ 601 602 #define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */ 603 #define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */ 604 605 #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ 606 #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ 607 608 #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ 609 #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ 610 611 #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ 612 #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ 613 614 #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ 615 #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ 616 617 #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ 618 #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ 619 620 #define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ 621 #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ 622 623 #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ 624 #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ 625 626 #define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ 627 #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ 628 629 #define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ 630 #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ 631 632 #define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ 633 #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ 634 635 #define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ 636 #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ 637 638 #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ 639 #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ 640 641 #define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */ 642 #define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */ 643 644 #define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */ 645 #define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */ 646 647 #define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */ 648 #define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */ 649 650 #define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */ 651 #define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */ 652 653 #define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */ 654 #define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */ 655 656 #define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */ 657 #define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOM20STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */ 658 659 #define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */ 660 #define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */ 661 662 #define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */ 663 #define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */ 664 665 #define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */ 666 #define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */ 667 668 #define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */ 669 #define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */ 670 671 #define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */ 672 #define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */ 673 674 #define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */ 675 #define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */ 676 677 #define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */ 678 #define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */ 679 680 /**@}*/ /* FMC_CONST */ 681 /**@}*/ /* end of FMC register group */ 682 /**@}*/ /* end of REGISTER group */ 683 684 #if defined ( __CC_ARM ) 685 #pragma no_anon_unions 686 #endif 687 688 #endif /* __FMC_REG_H__ */ 689
