1 /**************************************************************************//** 2 * @file emac_reg.h 3 * @version V1.00 4 * @brief EMAC register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EMAC_REG_H__ 10 #define __EMAC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup EMAC Ethernet MAC Controller(EMAC) 23 Memory Mapped Structure for EMAC Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 /** 30 * @var EMAC_T::CAMCTL 31 * Offset: 0x00 CAM Comparison Control Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |AUP |Accept Unicast Packet 36 * | | |The AUP controls the unicast packet reception 37 * | | |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address. 38 * | | |0 = EMAC receives packet depends on the CAM comparison result. 39 * | | |1 = EMAC receives all unicast packets. 40 * |[1] |AMP |Accept Multicast Packet 41 * | | |The AMP controls the multicast packet reception 42 * | | |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address. 43 * | | |0 = EMAC receives packet depends on the CAM comparison result. 44 * | | |1 = EMAC receives all multicast packets. 45 * |[2] |ABP |Accept Broadcast Packet 46 * | | |The ABP controls the broadcast packet reception 47 * | | |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address. 48 * | | |0 = EMAC receives packet depends on the CAM comparison result. 49 * | | |1 = EMAC receives all broadcast packets. 50 * |[3] |COMPEN |Complement CAM Comparison Enable Bit 51 * | | |The COMPEN controls the complement of the CAM comparison result 52 * | | |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address 53 * | | |configured in CAM entry will be dropped 54 * | | |And the incoming packet with destination MAC address does not configured in any CAM entry will be received. 55 * | | |0 = Complement CAM comparison result Disabled. 56 * | | |1 = Complement CAM comparison result Enabled. 57 * |[4] |CMPEN |CAM Compare Enable Bit 58 * | | |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition 59 * | | |If software wants to receive a packet with specific destination MAC address, configures the MAC address 60 * | | |into CAM 12~0, then enables that CAM entry and set CMPEN to 1. 61 * | | |0 = CAM comparison function for destination MAC address recognition Disabled. 62 * | | |1 = CAM comparison function for destination MAC address recognition Enabled. 63 * @var EMAC_T::CAMEN 64 * Offset: 0x04 CAM Enable Register 65 * --------------------------------------------------------------------------------------------------- 66 * |Bits |Field |Descriptions 67 * | :----: | :----: | :---- | 68 * |[0] |CAMxEN |CAM Entry X Enable Bit 69 * | | |The CAMxEN controls the validation of CAM entry x. 70 * | | |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission 71 * | | |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM 72 * | | |entries all must be enabled first. 73 * | | |0 = CAM entry x Disabled. 74 * | | |1 = CAM entry x Enabled. 75 * @var EMAC_T::CAM0M 76 * Offset: 0x08 CAM0 Most Significant Word Register 77 * --------------------------------------------------------------------------------------------------- 78 * |Bits |Field |Descriptions 79 * | :----: | :----: | :---- | 80 * |[7:0] |MACADDR2 |MAC Address Byte 2 81 * |[15:8] |MACADDR3 |MAC Address Byte 3 82 * |[23:16] |MACADDR4 |MAC Address Byte 4 83 * |[31:24] |MACADDR5 |MAC Address Byte 5 84 * | | |The CAMxM keeps the bit 47~16 of MAC address 85 * | | |The x can be the 0~14 86 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 87 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 88 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 89 * @var EMAC_T::CAM0L 90 * Offset: 0x0C CAM0 Least Significant Word Register 91 * --------------------------------------------------------------------------------------------------- 92 * |Bits |Field |Descriptions 93 * | :----: | :----: | :---- | 94 * |[23:16] |MACADDR0 |MAC Address Byte 0 95 * |[31:24] |MACADDR1 |MAC Address Byte 1 96 * | | |The CAMxL keeps the bit 15~0 of MAC address 97 * | | |The x can be the 0~14 98 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 99 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 100 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 101 * @var EMAC_T::CAM1M 102 * Offset: 0x10 CAM1 Most Significant Word Register 103 * --------------------------------------------------------------------------------------------------- 104 * |Bits |Field |Descriptions 105 * | :----: | :----: | :---- | 106 * |[7:0] |MACADDR2 |MAC Address Byte 2 107 * |[15:8] |MACADDR3 |MAC Address Byte 3 108 * |[23:16] |MACADDR4 |MAC Address Byte 4 109 * |[31:24] |MACADDR5 |MAC Address Byte 5 110 * | | |The CAMxM keeps the bit 47~16 of MAC address 111 * | | |The x can be the 0~14 112 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 113 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 114 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 115 * @var EMAC_T::CAM1L 116 * Offset: 0x14 CAM1 Least Significant Word Register 117 * --------------------------------------------------------------------------------------------------- 118 * |Bits |Field |Descriptions 119 * | :----: | :----: | :---- | 120 * |[23:16] |MACADDR0 |MAC Address Byte 0 121 * |[31:24] |MACADDR1 |MAC Address Byte 1 122 * | | |The CAMxL keeps the bit 15~0 of MAC address 123 * | | |The x can be the 0~14 124 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 125 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 126 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 127 * @var EMAC_T::CAM2M 128 * Offset: 0x18 CAM2 Most Significant Word Register 129 * --------------------------------------------------------------------------------------------------- 130 * |Bits |Field |Descriptions 131 * | :----: | :----: | :---- | 132 * |[7:0] |MACADDR2 |MAC Address Byte 2 133 * |[15:8] |MACADDR3 |MAC Address Byte 3 134 * |[23:16] |MACADDR4 |MAC Address Byte 4 135 * |[31:24] |MACADDR5 |MAC Address Byte 5 136 * | | |The CAMxM keeps the bit 47~16 of MAC address 137 * | | |The x can be the 0~14 138 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 139 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 140 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 141 * @var EMAC_T::CAM2L 142 * Offset: 0x1C CAM2 Least Significant Word Register 143 * --------------------------------------------------------------------------------------------------- 144 * |Bits |Field |Descriptions 145 * | :----: | :----: | :---- | 146 * |[23:16] |MACADDR0 |MAC Address Byte 0 147 * |[31:24] |MACADDR1 |MAC Address Byte 1 148 * | | |The CAMxL keeps the bit 15~0 of MAC address 149 * | | |The x can be the 0~14 150 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 151 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 152 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 153 * @var EMAC_T::CAM3M 154 * Offset: 0x20 CAM3 Most Significant Word Register 155 * --------------------------------------------------------------------------------------------------- 156 * |Bits |Field |Descriptions 157 * | :----: | :----: | :---- | 158 * |[7:0] |MACADDR2 |MAC Address Byte 2 159 * |[15:8] |MACADDR3 |MAC Address Byte 3 160 * |[23:16] |MACADDR4 |MAC Address Byte 4 161 * |[31:24] |MACADDR5 |MAC Address Byte 5 162 * | | |The CAMxM keeps the bit 47~16 of MAC address 163 * | | |The x can be the 0~14 164 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 165 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 166 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 167 * @var EMAC_T::CAM3L 168 * Offset: 0x24 CAM3 Least Significant Word Register 169 * --------------------------------------------------------------------------------------------------- 170 * |Bits |Field |Descriptions 171 * | :----: | :----: | :---- | 172 * |[23:16] |MACADDR0 |MAC Address Byte 0 173 * |[31:24] |MACADDR1 |MAC Address Byte 1 174 * | | |The CAMxL keeps the bit 15~0 of MAC address 175 * | | |The x can be the 0~14 176 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 177 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 178 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 179 * @var EMAC_T::CAM4M 180 * Offset: 0x28 CAM4 Most Significant Word Register 181 * --------------------------------------------------------------------------------------------------- 182 * |Bits |Field |Descriptions 183 * | :----: | :----: | :---- | 184 * |[7:0] |MACADDR2 |MAC Address Byte 2 185 * |[15:8] |MACADDR3 |MAC Address Byte 3 186 * |[23:16] |MACADDR4 |MAC Address Byte 4 187 * |[31:24] |MACADDR5 |MAC Address Byte 5 188 * | | |The CAMxM keeps the bit 47~16 of MAC address 189 * | | |The x can be the 0~14 190 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 191 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 192 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 193 * @var EMAC_T::CAM4L 194 * Offset: 0x2C CAM4 Least Significant Word Register 195 * --------------------------------------------------------------------------------------------------- 196 * |Bits |Field |Descriptions 197 * | :----: | :----: | :---- | 198 * |[23:16] |MACADDR0 |MAC Address Byte 0 199 * |[31:24] |MACADDR1 |MAC Address Byte 1 200 * | | |The CAMxL keeps the bit 15~0 of MAC address 201 * | | |The x can be the 0~14 202 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 203 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 204 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 205 * @var EMAC_T::CAM5M 206 * Offset: 0x30 CAM5 Most Significant Word Register 207 * --------------------------------------------------------------------------------------------------- 208 * |Bits |Field |Descriptions 209 * | :----: | :----: | :---- | 210 * |[7:0] |MACADDR2 |MAC Address Byte 2 211 * |[15:8] |MACADDR3 |MAC Address Byte 3 212 * |[23:16] |MACADDR4 |MAC Address Byte 4 213 * |[31:24] |MACADDR5 |MAC Address Byte 5 214 * | | |The CAMxM keeps the bit 47~16 of MAC address 215 * | | |The x can be the 0~14 216 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 217 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 218 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 219 * @var EMAC_T::CAM5L 220 * Offset: 0x34 CAM5 Least Significant Word Register 221 * --------------------------------------------------------------------------------------------------- 222 * |Bits |Field |Descriptions 223 * | :----: | :----: | :---- | 224 * |[23:16] |MACADDR0 |MAC Address Byte 0 225 * |[31:24] |MACADDR1 |MAC Address Byte 1 226 * | | |The CAMxL keeps the bit 15~0 of MAC address 227 * | | |The x can be the 0~14 228 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 229 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 230 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 231 * @var EMAC_T::CAM6M 232 * Offset: 0x38 CAM6 Most Significant Word Register 233 * --------------------------------------------------------------------------------------------------- 234 * |Bits |Field |Descriptions 235 * | :----: | :----: | :---- | 236 * |[7:0] |MACADDR2 |MAC Address Byte 2 237 * |[15:8] |MACADDR3 |MAC Address Byte 3 238 * |[23:16] |MACADDR4 |MAC Address Byte 4 239 * |[31:24] |MACADDR5 |MAC Address Byte 5 240 * | | |The CAMxM keeps the bit 47~16 of MAC address 241 * | | |The x can be the 0~14 242 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 243 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 244 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 245 * @var EMAC_T::CAM6L 246 * Offset: 0x3C CAM6 Least Significant Word Register 247 * --------------------------------------------------------------------------------------------------- 248 * |Bits |Field |Descriptions 249 * | :----: | :----: | :---- | 250 * |[23:16] |MACADDR0 |MAC Address Byte 0 251 * |[31:24] |MACADDR1 |MAC Address Byte 1 252 * | | |The CAMxL keeps the bit 15~0 of MAC address 253 * | | |The x can be the 0~14 254 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 255 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 256 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 257 * @var EMAC_T::CAM7M 258 * Offset: 0x40 CAM7 Most Significant Word Register 259 * --------------------------------------------------------------------------------------------------- 260 * |Bits |Field |Descriptions 261 * | :----: | :----: | :---- | 262 * |[7:0] |MACADDR2 |MAC Address Byte 2 263 * |[15:8] |MACADDR3 |MAC Address Byte 3 264 * |[23:16] |MACADDR4 |MAC Address Byte 4 265 * |[31:24] |MACADDR5 |MAC Address Byte 5 266 * | | |The CAMxM keeps the bit 47~16 of MAC address 267 * | | |The x can be the 0~14 268 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 269 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 270 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 271 * @var EMAC_T::CAM7L 272 * Offset: 0x44 CAM7 Least Significant Word Register 273 * --------------------------------------------------------------------------------------------------- 274 * |Bits |Field |Descriptions 275 * | :----: | :----: | :---- | 276 * |[23:16] |MACADDR0 |MAC Address Byte 0 277 * |[31:24] |MACADDR1 |MAC Address Byte 1 278 * | | |The CAMxL keeps the bit 15~0 of MAC address 279 * | | |The x can be the 0~14 280 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 281 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 282 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 283 * @var EMAC_T::CAM8M 284 * Offset: 0x48 CAM8 Most Significant Word Register 285 * --------------------------------------------------------------------------------------------------- 286 * |Bits |Field |Descriptions 287 * | :----: | :----: | :---- | 288 * |[7:0] |MACADDR2 |MAC Address Byte 2 289 * |[15:8] |MACADDR3 |MAC Address Byte 3 290 * |[23:16] |MACADDR4 |MAC Address Byte 4 291 * |[31:24] |MACADDR5 |MAC Address Byte 5 292 * | | |The CAMxM keeps the bit 47~16 of MAC address 293 * | | |The x can be the 0~14 294 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 295 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 296 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 297 * @var EMAC_T::CAM8L 298 * Offset: 0x4C CAM8 Least Significant Word Register 299 * --------------------------------------------------------------------------------------------------- 300 * |Bits |Field |Descriptions 301 * | :----: | :----: | :---- | 302 * |[23:16] |MACADDR0 |MAC Address Byte 0 303 * |[31:24] |MACADDR1 |MAC Address Byte 1 304 * | | |The CAMxL keeps the bit 15~0 of MAC address 305 * | | |The x can be the 0~14 306 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 307 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 308 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 309 * @var EMAC_T::CAM9M 310 * Offset: 0x50 CAM9 Most Significant Word Register 311 * --------------------------------------------------------------------------------------------------- 312 * |Bits |Field |Descriptions 313 * | :----: | :----: | :---- | 314 * |[7:0] |MACADDR2 |MAC Address Byte 2 315 * |[15:8] |MACADDR3 |MAC Address Byte 3 316 * |[23:16] |MACADDR4 |MAC Address Byte 4 317 * |[31:24] |MACADDR5 |MAC Address Byte 5 318 * | | |The CAMxM keeps the bit 47~16 of MAC address 319 * | | |The x can be the 0~14 320 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 321 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 322 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 323 * @var EMAC_T::CAM9L 324 * Offset: 0x54 CAM9 Least Significant Word Register 325 * --------------------------------------------------------------------------------------------------- 326 * |Bits |Field |Descriptions 327 * | :----: | :----: | :---- | 328 * |[23:16] |MACADDR0 |MAC Address Byte 0 329 * |[31:24] |MACADDR1 |MAC Address Byte 1 330 * | | |The CAMxL keeps the bit 15~0 of MAC address 331 * | | |The x can be the 0~14 332 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 333 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 334 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 335 * @var EMAC_T::CAM10M 336 * Offset: 0x58 CAM10 Most Significant Word Register 337 * --------------------------------------------------------------------------------------------------- 338 * |Bits |Field |Descriptions 339 * | :----: | :----: | :---- | 340 * |[7:0] |MACADDR2 |MAC Address Byte 2 341 * |[15:8] |MACADDR3 |MAC Address Byte 3 342 * |[23:16] |MACADDR4 |MAC Address Byte 4 343 * |[31:24] |MACADDR5 |MAC Address Byte 5 344 * | | |The CAMxM keeps the bit 47~16 of MAC address 345 * | | |The x can be the 0~14 346 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 347 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 348 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 349 * @var EMAC_T::CAM10L 350 * Offset: 0x5C CAM10 Least Significant Word Register 351 * --------------------------------------------------------------------------------------------------- 352 * |Bits |Field |Descriptions 353 * | :----: | :----: | :---- | 354 * |[23:16] |MACADDR0 |MAC Address Byte 0 355 * |[31:24] |MACADDR1 |MAC Address Byte 1 356 * | | |The CAMxL keeps the bit 15~0 of MAC address 357 * | | |The x can be the 0~14 358 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 359 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 360 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 361 * @var EMAC_T::CAM11M 362 * Offset: 0x60 CAM11 Most Significant Word Register 363 * --------------------------------------------------------------------------------------------------- 364 * |Bits |Field |Descriptions 365 * | :----: | :----: | :---- | 366 * |[7:0] |MACADDR2 |MAC Address Byte 2 367 * |[15:8] |MACADDR3 |MAC Address Byte 3 368 * |[23:16] |MACADDR4 |MAC Address Byte 4 369 * |[31:24] |MACADDR5 |MAC Address Byte 5 370 * | | |The CAMxM keeps the bit 47~16 of MAC address 371 * | | |The x can be the 0~14 372 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 373 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 374 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 375 * @var EMAC_T::CAM11L 376 * Offset: 0x64 CAM11 Least Significant Word Register 377 * --------------------------------------------------------------------------------------------------- 378 * |Bits |Field |Descriptions 379 * | :----: | :----: | :---- | 380 * |[23:16] |MACADDR0 |MAC Address Byte 0 381 * |[31:24] |MACADDR1 |MAC Address Byte 1 382 * | | |The CAMxL keeps the bit 15~0 of MAC address 383 * | | |The x can be the 0~14 384 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 385 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 386 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 387 * @var EMAC_T::CAM12M 388 * Offset: 0x68 CAM12 Most Significant Word Register 389 * --------------------------------------------------------------------------------------------------- 390 * |Bits |Field |Descriptions 391 * | :----: | :----: | :---- | 392 * |[7:0] |MACADDR2 |MAC Address Byte 2 393 * |[15:8] |MACADDR3 |MAC Address Byte 3 394 * |[23:16] |MACADDR4 |MAC Address Byte 4 395 * |[31:24] |MACADDR5 |MAC Address Byte 5 396 * | | |The CAMxM keeps the bit 47~16 of MAC address 397 * | | |The x can be the 0~14 398 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 399 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 400 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 401 * @var EMAC_T::CAM12L 402 * Offset: 0x6C CAM12 Least Significant Word Register 403 * --------------------------------------------------------------------------------------------------- 404 * |Bits |Field |Descriptions 405 * | :----: | :----: | :---- | 406 * |[23:16] |MACADDR0 |MAC Address Byte 0 407 * |[31:24] |MACADDR1 |MAC Address Byte 1 408 * | | |The CAMxL keeps the bit 15~0 of MAC address 409 * | | |The x can be the 0~14 410 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 411 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 412 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 413 * @var EMAC_T::CAM13M 414 * Offset: 0x70 CAM13 Most Significant Word Register 415 * --------------------------------------------------------------------------------------------------- 416 * |Bits |Field |Descriptions 417 * | :----: | :----: | :---- | 418 * |[7:0] |MACADDR2 |MAC Address Byte 2 419 * |[15:8] |MACADDR3 |MAC Address Byte 3 420 * |[23:16] |MACADDR4 |MAC Address Byte 4 421 * |[31:24] |MACADDR5 |MAC Address Byte 5 422 * | | |The CAMxM keeps the bit 47~16 of MAC address 423 * | | |The x can be the 0~14 424 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 425 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 426 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 427 * @var EMAC_T::CAM13L 428 * Offset: 0x74 CAM13 Least Significant Word Register 429 * --------------------------------------------------------------------------------------------------- 430 * |Bits |Field |Descriptions 431 * | :----: | :----: | :---- | 432 * |[23:16] |MACADDR0 |MAC Address Byte 0 433 * |[31:24] |MACADDR1 |MAC Address Byte 1 434 * | | |The CAMxL keeps the bit 15~0 of MAC address 435 * | | |The x can be the 0~14 436 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 437 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 438 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 439 * @var EMAC_T::CAM14M 440 * Offset: 0x78 CAM14 Most Significant Word Register 441 * --------------------------------------------------------------------------------------------------- 442 * |Bits |Field |Descriptions 443 * | :----: | :----: | :---- | 444 * |[7:0] |MACADDR2 |MAC Address Byte 2 445 * |[15:8] |MACADDR3 |MAC Address Byte 3 446 * |[23:16] |MACADDR4 |MAC Address Byte 4 447 * |[31:24] |MACADDR5 |MAC Address Byte 5 448 * | | |The CAMxM keeps the bit 47~16 of MAC address 449 * | | |The x can be the 0~14 450 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 451 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 452 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 453 * @var EMAC_T::CAM14L 454 * Offset: 0x7C CAM14 Least Significant Word Register 455 * --------------------------------------------------------------------------------------------------- 456 * |Bits |Field |Descriptions 457 * | :----: | :----: | :---- | 458 * |[23:16] |MACADDR0 |MAC Address Byte 0 459 * |[31:24] |MACADDR1 |MAC Address Byte 1 460 * | | |The CAMxL keeps the bit 15~0 of MAC address 461 * | | |The x can be the 0~14 462 * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. 463 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 464 * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. 465 * @var EMAC_T::CAM15MSB 466 * Offset: 0x80 CAM15 Most Significant Word Register 467 * --------------------------------------------------------------------------------------------------- 468 * |Bits |Field |Descriptions 469 * | :----: | :----: | :---- | 470 * |[15:0] |OPCODE |OP Code Field of PAUSE Control Frame 471 * | | |In the PAUSE control frame, an op code field defined and is 0x0001. 472 * |[31:16] |LENGTH |LENGTH Field of PAUSE Control Frame 473 * | | |In the PAUSE control frame, a LENGTH field defined and is 0x8808. 474 * @var EMAC_T::CAM15LSB 475 * Offset: 0x84 CAM15 Least Significant Word Register 476 * --------------------------------------------------------------------------------------------------- 477 * |Bits |Field |Descriptions 478 * | :----: | :----: | :---- | 479 * |[31:24] |OPERAND |Pause Parameter 480 * | | |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination 481 * | | |Ethernet MAC Controller paused 482 * | | |The unit of the OPERAND is a slot time, the 512-bit time. 483 * @var EMAC_T::TXDSA 484 * Offset: 0x88 Transmit Descriptor Link List Start Address Register 485 * --------------------------------------------------------------------------------------------------- 486 * |Bits |Field |Descriptions 487 * | :----: | :----: | :---- | 488 * |[31:0] |TXDSA |Transmit Descriptor Link-list Start Address 489 * | | |The TXDSA keeps the start address of transmit descriptor link-list 490 * | | |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the 491 * | | |current transmit descriptor start address register (EMAC_CTXDSA) 492 * | | |The TXDSA does not be updated by EMAC 493 * | | |During the operation, EMAC will ignore the bits [1:0] of TXDSA 494 * | | |This means that TX descriptors must locate at word boundary memory address. 495 * @var EMAC_T::RXDSA 496 * Offset: 0x8C Receive Descriptor Link List Start Address Register 497 * --------------------------------------------------------------------------------------------------- 498 * |Bits |Field |Descriptions 499 * | :----: | :----: | :---- | 500 * |[31:0] |RXDSA |Receive Descriptor Link-list Start Address 501 * | | |The RXDSA keeps the start address of receive descriptor link-list 502 * | | |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current 503 * | | |receive descriptor start address register (EMAC_CRXDSA) 504 * | | |The RXDSA does not be updated by EMAC 505 * | | |During the operation, EMAC will ignore the bits [1:0] of RXDSA 506 * | | |This means that RX descriptors must locate at word boundary memory address. 507 * @var EMAC_T::CTL 508 * Offset: 0x90 MAC Control Register 509 * --------------------------------------------------------------------------------------------------- 510 * |Bits |Field |Descriptions 511 * | :----: | :----: | :---- | 512 * |[0] |RXON |Frame Reception ON 513 * | | |The RXON controls the normal packet reception of EMAC 514 * | | |If the RXON is set to high, the EMAC starts the packet reception process, including the RX 515 * | | |descriptor fetching, packet reception and RX descriptor modification. 516 * | | |It is necessary to finish EMAC initial sequence before enable RXON 517 * | | |Otherwise, the EMAC operation is undefined. 518 * | | |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet 519 * | | |reception process after the current packet reception finished. 520 * | | |0 = Packet reception process stopped. 521 * | | |1 = Packet reception process started. 522 * |[1] |ALP |Accept Long Packet 523 * | | |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception 524 * | | |If the ALP is set to high, the EMAC will accept the long packet. 525 * | | |Otherwise, the long packet will be dropped. 526 * | | |0 = Ethernet MAC controller dropped the long packet. 527 * | | |1 = Ethernet MAC controller received the long packet. 528 * |[2] |ARP |Accept Runt Packet 529 * | | |The ARP controls the runt packet, which length is less than 64 bytes, reception 530 * | | |If the ARP is set to high, the EMAC will accept the runt packet. 531 * | | |Otherwise, the runt packet will be dropped. 532 * | | |0 = Ethernet MAC controller dropped the runt packet. 533 * | | |1 = Ethernet MAC controller received the runt packet. 534 * |[3] |ACP |Accept Control Packet 535 * | | |The ACP controls the control frame reception 536 * | | |If the ACP is set to high, the EMAC will accept the control frame 537 * | | |Otherwise, the control frame will be dropped 538 * | | |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode. 539 * | | |0 = Ethernet MAC controller dropped the control frame. 540 * | | |1 = Ethernet MAC controller received the control frame. 541 * |[4] |AEP |Accept CRC Error Packet 542 * | | |The AEP controls the EMAC accepts or drops the CRC error packet 543 * | | |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet. 544 * | | |0 = Ethernet MAC controller dropped the CRC error packet. 545 * | | |1 = Ethernet MAC controller received the CRC error packet. 546 * |[5] |STRIPCRC |Strip CRC Checksum 547 * | | |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum 548 * | | |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet. 549 * | | |0 = The 4 bytes CRC checksum is included in packet length calculation. 550 * | | |1 = The 4 bytes CRC checksum is excluded in packet length calculation. 551 * |[6] |WOLEN |Wake on LAN Enable Bit 552 * | | |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet 553 * | | |is Magic Packet and wakeup system from Power-down mode. 554 * | | |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller 555 * | | |would generate a wakeup event to wake system up from Power-down mode. 556 * | | |0 = Wake-up by Magic Packet function Disabled. 557 * | | |1 = Wake-up by Magic Packet function Enabled. 558 * |[8] |TXON |Frame Transmission ON 559 * | | |The TXON controls the normal packet transmission of EMAC 560 * | | |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX 561 * | | |descriptor fetching, packet transmission and TX descriptor modification. 562 * | | |It is must to finish EMAC initial sequence before enable TXON 563 * | | |Otherwise, the EMAC operation is undefined. 564 * | | |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet 565 * | | |transmission process after the current packet transmission finished. 566 * | | |0 = Packet transmission process stopped. 567 * | | |1 = Packet transmission process started. 568 * |[9] |NODEF |No Deferral 569 * | | |The NODEF controls the enable of deferral exceed counter 570 * | | |If NODEF is set to high, the deferral exceed counter is disabled 571 * | | |The NODEF is only useful while EMAC is operating on half duplex mode. 572 * | | |0 = The deferral exceed counter Enabled. 573 * | | |1 = The deferral exceed counter Disabled. 574 * |[16] |SDPZ |Send PAUSE Frame 575 * | | |The SDPZ controls the PAUSE control frame transmission. 576 * | | |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured 577 * | | |first and the corresponding CAM enable bit of CAMEN register also must be set. 578 * | | |Then, set SDPZ to 1 enables the PAUSE control frame transmission. 579 * | | |The SDPZ is a self-clear bit 580 * | | |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically. 581 * | | |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode. 582 * | | |0 = PAUSE control frame transmission completed. 583 * | | |1 = PAUSE control frame transmission Enabled. 584 * |[17] |SQECHKEN |SQE Checking Enable Bit 585 * | | |The SQECHKEN controls the enable of SQE checking 586 * | | |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode 587 * | | |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps 588 * | | |or full duplex mode. 589 * | | |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode. 590 * | | |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode. 591 * |[18] |FUDUP |Full Duplex Mode Selection 592 * | | |The FUDUP controls that if EMAC is operating on full or half duplex mode. 593 * | | |0 = EMAC operates in half duplex mode. 594 * | | |1 = EMAC operates in full duplex mode. 595 * |[19] |RMIIRXCTL |RMII RX Control 596 * | | |The RMIIRXCTL control the receive data sample in RMII mode 597 * | | |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high. 598 * | | |0 = RMII RX control disabled. 599 * | | |1 = RMII RX control enabled. 600 * |[20] |OPMODE |Operation Mode Selection 601 * | | |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode 602 * | | |The RST (EMAC_CTL[24]) would not affect OPMODE value. 603 * | | |0 = EMAC operates in 10Mbps mode. 604 * | | |1 = EMAC operates in 100Mbps mode. 605 * |[22] |RMIIEN |RMII Mode Enable Bit 606 * | | |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII 607 * | | |interface or RMII interface 608 * | | |The RST (EMAC_CTL[24]) would not affect RMIIEN value. 609 * | | |0 = Ethernet MAC controller RMII mode Disabled. 610 * | | |1 = Ethernet MAC controller RMII mode Enabled. 611 * | | |NOTE: This field must keep 1. 612 * |[24] |RST |Software Reset 613 * | | |The RST implements a reset function to make the EMAC return default state 614 * | | |The RST is a self-clear bit 615 * | | |This means after the software reset finished, the RST will be cleared automatically 616 * | | |Enable RST can also reset all control and status registers, exclusive of the control bits 617 * | | |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]). 618 * | | |The EMAC re-initial is necessary after the software reset completed. 619 * | | |0 = Software reset completed. 620 * | | |1 = Software reset Enabled. 621 * @var EMAC_T::MIIMDAT 622 * Offset: 0x94 MII Management Data Register 623 * --------------------------------------------------------------------------------------------------- 624 * |Bits |Field |Descriptions 625 * | :----: | :----: | :---- | 626 * |[15:0] |DATA |MII Management Data 627 * | | |The DATA is the 16 bits data that will be written into the registers of external PHY for MII 628 * | | |Management write command or the data from the registers of external PHY for MII Management read command. 629 * @var EMAC_T::MIIMCTL 630 * Offset: 0x98 MII Management Control and Address Register 631 * --------------------------------------------------------------------------------------------------- 632 * |Bits |Field |Descriptions 633 * | :----: | :----: | :---- | 634 * |[4:0] |PHYREG |PHY Register Address 635 * | | |The PHYREG keeps the address to indicate which register of external PHY is the target of the 636 * | | |MII management command. 637 * |[12:8] |PHYADDR |PHY Address 638 * | | |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command. 639 * |[16] |WRITE |Write Command 640 * | | |The Write defines the MII management command is a read or write. 641 * | | |0 = MII management command is a read command. 642 * | | |1 = MII management command is a write command. 643 * |[17] |BUSY |Busy Bit 644 * | | |The BUSY controls the enable of the MII management frame generation 645 * | | |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates 646 * | | |the MII management frame to external PHY through MII Management I/F 647 * | | |The BUSY is a self-clear bit 648 * | | |This means the BUSY will be cleared automatically after the MII management command finished. 649 * | | |0 = MII management command generation finished. 650 * | | |1 = MII management command generation Enabled. 651 * |[18] |PREAMSP |Preamble Suppress 652 * | | |The PREAMSP controls the preamble field generation of MII management frame 653 * | | |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped. 654 * | | |0 = Preamble field generation of MII management frame not skipped. 655 * | | |1 = Preamble field generation of MII management frame skipped. 656 * |[19] |MDCON |MDC Clock ON 657 * | | |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on. 658 * | | |0 = MDC clock off. 659 * | | |1 = MDC clock on. 660 * @var EMAC_T::FIFOCTL 661 * Offset: 0x9C FIFO Threshold Control Register 662 * --------------------------------------------------------------------------------------------------- 663 * |Bits |Field |Descriptions 664 * | :----: | :----: | :---- | 665 * |[1:0] |RXFIFOTH |RXFIFO Low Threshold 666 * | | |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO 667 * | | |and system memory 668 * | | |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold 669 * | | |The low threshold is the half of high threshold always 670 * | | |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to 671 * | | |transfer frame data from RXFIFO to system memory 672 * | | |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame 673 * | | |data to system memory. 674 * | | |00 = Depend on the burst length setting 675 * | | |If the burst length is 8 words, high threshold is 8 words, too. 676 * | | |01 = RXFIFO high threshold is 64B and low threshold is 32B. 677 * | | |10 = RXFIFO high threshold is 128B and low threshold is 64B. 678 * | | |11 = RXFIFO high threshold is 192B and low threshold is 96B. 679 * |[9:8] |TXFIFOTH |TXFIFO Low Threshold 680 * | | |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system 681 * | | |memory and TXFIFO 682 * | | |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold 683 * | | |The high threshold is the twice of low threshold always 684 * | | |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops 685 * | | |generate request to transfer frame data from system memory to TXFIFO 686 * | | |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data 687 * | | |from system memory to TXFIFO. 688 * | | |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network 689 * | | |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold 690 * | | |during the transmission of the frame 691 * | | |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame 692 * | | |out after the frame data are all inside the TXFIFO. 693 * | | |00 = Undefined. 694 * | | |01 = TXFIFO low threshold is 64B and high threshold is 128B. 695 * | | |10 = TXFIFO low threshold is 80B and high threshold is 160B. 696 * | | |11 = TXFIFO low threshold is 96B and high threshold is 192B. 697 * |[21:20] |BURSTLEN |DMA Burst Length 698 * | | |This defines the burst length of AHB bus cycle while EMAC accesses system memory. 699 * | | |00 = 4 words. 700 * | | |01 = 8 words. 701 * | | |10 = 16 words. 702 * | | |11 = 16 words. 703 * @var EMAC_T::TXST 704 * Offset: 0xA0 Transmit Start Demand Register 705 * --------------------------------------------------------------------------------------------------- 706 * |Bits |Field |Descriptions 707 * | :----: | :----: | :---- | 708 * |[31:0] |TXST |Transmit Start Demand 709 * | | |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, 710 * | | |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted 711 * | | |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write 712 * | | |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission. 713 * | | |The EMAC_TXST is a write only register and read from this register is undefined. 714 * | | |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state. 715 * @var EMAC_T::RXST 716 * Offset: 0xA4 Receive Start Demand Register 717 * --------------------------------------------------------------------------------------------------- 718 * |Bits |Field |Descriptions 719 * | :----: | :----: | :---- | 720 * |[31:0] |RXST |Receive Start Demand 721 * | | |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, 722 * | | |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted 723 * | | |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write 724 * | | |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception. 725 * | | |The EMAC_RXST is a write only register and read from this register is undefined. 726 * | | |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state. 727 * @var EMAC_T::MRFL 728 * Offset: 0xA8 Maximum Receive Frame Control Register 729 * --------------------------------------------------------------------------------------------------- 730 * |Bits |Field |Descriptions 731 * | :----: | :----: | :---- | 732 * |[15:0] |MRFL |Maximum Receive Frame Length 733 * | | |The MRFL defines the maximum frame length for received frame 734 * | | |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) 735 * | | |is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered. 736 * | | |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to 737 * | | |receive a frame which length is greater than 1518 bytes. 738 * @var EMAC_T::INTEN 739 * Offset: 0xAC MAC Interrupt Enable Register 740 * --------------------------------------------------------------------------------------------------- 741 * |Bits |Field |Descriptions 742 * | :----: | :----: | :---- | 743 * |[0] |RXIEN |Receive Interrupt Enable Bit 744 * | | |The RXIEN controls the RX interrupt generation. 745 * | | |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU 746 * | | |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] 747 * | | |is set and the corresponding bit of EMAC_INTEN is enabled 748 * | | |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled 749 * | | |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit. 750 * | | |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled. 751 * | | |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled. 752 * |[1] |CRCEIEN |CRC Error Interrupt Enable Bit 753 * | | |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation 754 * | | |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the 755 * | | |EMAC generates the RX interrupt to CPU 756 * | | |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 757 * | | |CRCEIF (EMAC_INTSTS[1]) is set. 758 * | | |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled. 759 * | | |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled. 760 * |[2] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Bit 761 * | | |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation 762 * | | |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the 763 * | | |EMAC generates the RX interrupt to CPU 764 * | | |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 765 * | | |RXOVIF (EMAC_INTSTS[2]) is set. 766 * | | |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled. 767 * | | |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled. 768 * |[3] |LPIEN |Long Packet Interrupt Enable Bit 769 * | | |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation 770 * | | |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC 771 * | | |generates the RX interrupt to CPU 772 * | | |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF 773 * | | |(EMAC_INTSTS[3]) is set. 774 * | | |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled. 775 * | | |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled. 776 * |[4] |RXGDIEN |Receive Good Interrupt Enable Bit 777 * | | |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation 778 * | | |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the 779 * | | |EMAC generates the RX interrupt to CPU 780 * | | |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 781 * | | |RXGDIF (EMAC_INTSTS[4]) is set. 782 * | | |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled. 783 * | | |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled. 784 * |[5] |ALIEIEN |Alignment Error Interrupt Enable Bit 785 * | | |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation 786 * | | |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the 787 * | | |EMAC generates the RX interrupt to CPU 788 * | | |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 789 * | | |ALIEIF (EMAC_INTSTS[5]) is set. 790 * | | |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled. 791 * | | |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled. 792 * |[6] |RPIEN |Runt Packet Interrupt Enable Bit 793 * | | |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation 794 * | | |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC 795 * | | |generates the RX interrupt to CPU 796 * | | |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 797 * | | |RPIF (EMAC_INTSTS[6]) is set. 798 * | | |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled. 799 * | | |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled. 800 * |[7] |MPCOVIEN |Miss Packet Counter Overrun Interrupt Enable Bit 801 * | | |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation 802 * | | |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, 803 * | | |the EMAC generates the RX interrupt to CPU 804 * | | |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 805 * | | |MPCOVIF (EMAC_INTSTS[7]) is set. 806 * | | |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled. 807 * | | |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled. 808 * |[8] |MFLEIEN |Maximum Frame Length Exceed Interrupt Enable Bit 809 * | | |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation 810 * | | |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the 811 * | | |EMAC generates the RX interrupt to CPU 812 * | | |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 813 * | | |MFLEIF (EMAC_INTSTS[8]) is set. 814 * | | |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled. 815 * | | |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled. 816 * |[9] |DENIEN |DMA Early Notification Interrupt Enable Bit 817 * | | |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation 818 * | | |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the 819 * | | |EMAC generates the RX interrupt to CPU 820 * | | |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 821 * | | |DENIF (EMAC_INTSTS[9]) is set. 822 * | | |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled. 823 * | | |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled. 824 * |[10] |RDUIEN |Receive Descriptor Unavailable Interrupt Enable Bit 825 * | | |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation 826 * | | |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the 827 * | | |EMAC generates the RX interrupt to CPU 828 * | | |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 829 * | | |RDUIF (EMAC_MIOSTA[10]) register is set. 830 * | | |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled. 831 * | | |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled. 832 * |[11] |RXBEIEN |Receive Bus Error Interrupt Enable Bit 833 * | | |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation 834 * | | |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the 835 * | | |EMAC generates the RX interrupt to CPU 836 * | | |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 837 * | | |RXBEIF (EMAC_INTSTS[11]) is set. 838 * | | |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled. 839 * | | |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled. 840 * |[14] |CFRIEN |Control Frame Receive Interrupt Enable Bit 841 * | | |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation 842 * | | |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the 843 * | | |EMAC generates the RX interrupt to CPU 844 * | | |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 845 * | | |CFRIF (EMAC_INTSTS[14]) register is set. 846 * | | |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled. 847 * | | |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled. 848 * |[15] |WOLIEN |Wake on LAN Interrupt Enable Bit 849 * | | |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation 850 * | | |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, 851 * | | |the EMAC generates the RX interrupt to CPU 852 * | | |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the 853 * | | |WOLIF (EMAC_INTSTS[15]) is set. 854 * | | |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled. 855 * | | |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled. 856 * |[16] |TXIEN |Transmit Interrupt Enable Bit 857 * | | |The TXIEN controls the TX interrupt generation. 858 * | | |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU 859 * | | |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of 860 * | | |EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled 861 * | | |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled 862 * | | |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit. 863 * | | |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled. 864 * | | |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled. 865 * |[17] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Bit 866 * | | |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation 867 * | | |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled, 868 * | | |the EMAC generates the TX interrupt to CPU 869 * | | |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even 870 * | | |the TXUDIF (EMAC_INTSTS[17]) is set. 871 * | | |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled. 872 * | | |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled. 873 * |[18] |TXCPIEN |Transmit Completion Interrupt Enable Bit 874 * | | |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation 875 * | | |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled, 876 * | | |the EMAC generates the TX interrupt to CPU 877 * | | |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the 878 * | | |TXCPIF (EMAC_INTSTS[18]) is set. 879 * | | |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled. 880 * | | |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled. 881 * |[19] |EXDEFIEN |Defer Exceed Interrupt Enable Bit 882 * | | |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation 883 * | | |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled, 884 * | | |the EMAC generates the TX interrupt to CPU 885 * | | |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the 886 * | | |EXDEFIF (EMAC_INTSTS[19]) is set. 887 * | | |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled. 888 * | | |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled. 889 * |[20] |NCSIEN |No Carrier Sense Interrupt Enable Bit 890 * | | |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation 891 * | | |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the 892 * | | |EMAC generates the TX interrupt to CPU 893 * | | |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the 894 * | | |NCSIF (EMAC_INTSTS[20]) is set. 895 * | | |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled. 896 * | | |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled. 897 * |[21] |TXABTIEN |Transmit Abort Interrupt Enable Bit 898 * | | |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation 899 * | | |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled, 900 * | | |the EMAC generates the TX interrupt to CPU 901 * | | |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the 902 * | | |TXABTIF (EMAC_INTSTS[21]) is set. 903 * | | |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled. 904 * | | |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled. 905 * |[22] |LCIEN |Late Collision Interrupt Enable Bit 906 * | | |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation 907 * | | |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the 908 * | | |EMAC generates the TX interrupt to CPU 909 * | | |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the 910 * | | |LCIF (EMAC_INTSTS[22]) is set. 911 * | | |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled. 912 * | | |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled. 913 * |[23] |TDUIEN |Transmit Descriptor Unavailable Interrupt Enable Bit 914 * | | |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation 915 * | | |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the 916 * | | |EMAC generates the TX interrupt to CPU 917 * | | |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the 918 * | | |TDUIF (EMAC_INTSTS[23]) is set. 919 * | | |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled. 920 * | | |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled. 921 * |[24] |TXBEIEN |Transmit Bus Error Interrupt Enable Bit 922 * | | |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation 923 * | | |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the 924 * | | |EMAC generates the TX interrupt to CPU 925 * | | |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the 926 * | | |TXBEIF (EMAC_INTSTS[24]) is set. 927 * | | |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled. 928 * | | |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled. 929 * |[28] |TSALMIEN |Time Stamp Alarm Interrupt Enable Bit 930 * | | |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation 931 * | | |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the 932 * | | |EMAC generates the TX interrupt to CPU 933 * | | |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the 934 * | | |TXTSALMIF (EMAC_INTEN[28]) is set. 935 * | | |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled. 936 * | | |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled. 937 * @var EMAC_T::INTSTS 938 * Offset: 0xB0 MAC Interrupt Status Register 939 * --------------------------------------------------------------------------------------------------- 940 * |Bits |Field |Descriptions 941 * | :----: | :----: | :---- | 942 * |[0] |RXIF |Receive Interrupt 943 * | | |The RXIF indicates the RX interrupt status. 944 * | | |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates 945 * | | |the EMAC generates RX interrupt to CPU 946 * | | |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated. 947 * | | |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1] 948 * | | |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in 949 * | | |EMAC_INTEN[15:1] is also enabled, the RXIF will be high. 950 * | | |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too. 951 * | | |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled. 952 * | | |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in 953 * | | |EMAC_INTEN[15:1] is enabled, too. 954 * |[1] |CRCEIF |CRC Error Interrupt 955 * | | |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped 956 * | | |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and 957 * | | |CRCEIF will not be set. 958 * | | |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high 959 * | | |Write 1 to this bit clears the CRCEIF status. 960 * | | |0 = The frame does not incur CRC error. 961 * | | |1 = The frame incurred CRC error. 962 * |[2] |RXOVIF |Receive FIFO Overflow Interrupt 963 * | | |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception 964 * | | |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer 965 * | | |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control, 966 * | | |the RXFIFOTH of FFTCR register, to higher level. 967 * | | |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high 968 * | | |Write 1 to this bit clears the RXOVIF status. 969 * | | |0 = No RXFIFO overflow occurred during packet reception. 970 * | | |1 = RXFIFO overflow occurred during packet reception. 971 * |[3] |LPIF |Long Packet Interrupt Flag 972 * | | |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the 973 * | | |incoming packet is dropped 974 * | | |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set. 975 * | | |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high 976 * | | |Write 1 to this bit clears the LPIF status. 977 * | | |0 = The incoming frame is not a long frame or S/W wants to receive a long frame. 978 * | | |1 = The incoming frame is a long frame and dropped. 979 * |[4] |RXGDIF |Receive Good Interrupt 980 * | | |The RXGDIF high indicates the frame reception has completed. 981 * | | |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high 982 * | | |Write 1 to this bit clears the RXGDIF status. 983 * | | |0 = The frame reception has not complete yet. 984 * | | |1 = The frame reception has completed. 985 * |[5] |ALIEIF |Alignment Error Interrupt 986 * | | |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte 987 * | | |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high 988 * | | |Write 1 to this bit clears the ALIEIF status. 989 * | | |0 = The frame length is a multiple of byte. 990 * | | |1 = The frame length is not a multiple of byte. 991 * |[6] |RPIF |Runt Packet Interrupt 992 * | | |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped 993 * | | |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set. 994 * | | |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high 995 * | | |Write 1 to this bit clears the RPIF status. 996 * | | |0 = The incoming frame is not a short frame or S/W wants to receive a short frame. 997 * | | |1 = The incoming frame is a short frame and dropped. 998 * |[7] |MPCOVIF |Missed Packet Counter Overrun Interrupt Flag 999 * | | |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow 1000 * | | |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high 1001 * | | |Write 1 to this bit clears the MPCOVIF status. 1002 * | | |0 = The MPCNT has not rolled over yet. 1003 * | | |1 = The MPCNT has rolled over yet. 1004 * |[8] |MFLEIF |Maximum Frame Length Exceed Interrupt Flag 1005 * | | |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation 1006 * | | |configured in DMARFC register and the incoming packet is dropped 1007 * | | |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high 1008 * | | |Write 1 to this bit clears the MFLEIF status. 1009 * | | |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC. 1010 * | | |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC. 1011 * |[9] |DENIF |DMA Early Notification Interrupt 1012 * | | |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet. 1013 * | | |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high 1014 * | | |Write 1 to this bit clears the DENIF status. 1015 * | | |0 = The LENGTH field of incoming packet has not received yet. 1016 * | | |1 = The LENGTH field of incoming packet has received. 1017 * |[10] |RDUIF |Receive Descriptor Unavailable Interrupt 1018 * | | |The RDUIF high indicates that there is no available RX descriptor for packet reception and 1019 * | | |RXDMA will stay at Halt state 1020 * | | |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to 1021 * | | |make RXDMA leave Halt state while new RX descriptor is available. 1022 * | | |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high 1023 * | | |Write 1 to this bit clears the RDUIF status. 1024 * | | |0 = RX descriptor is available. 1025 * | | |1 = RX descriptor is unavailable. 1026 * |[11] |RXBEIF |Receive Bus Error Interrupt 1027 * | | |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access 1028 * | | |system memory through RXDMA during packet reception process 1029 * | | |Reset EMAC is recommended while RXBEIF status is high. 1030 * | | |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high 1031 * | | |Write 1 to this bit clears the RXBEIF status. 1032 * | | |0 = No ERROR response is received. 1033 * | | |1 = ERROR response is received. 1034 * |[14] |CFRIF |Control Frame Receive Interrupt 1035 * | | |The CFRIF high indicates EMAC receives a flow control frame 1036 * | | |The CFRIF only available while EMAC is operating on full duplex mode. 1037 * | | |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high 1038 * | | |Write 1 to this bit clears the CFRIF status. 1039 * | | |0 = The EMAC does not receive the flow control frame. 1040 * | | |1 = The EMAC receives a flow control frame. 1041 * |[15] |WOLIF |Wake on LAN Interrupt Flag 1042 * | | |The WOLIF high indicates EMAC receives a Magic Packet 1043 * | | |The CFRIF only available while system is in power down mode and WOLEN is set high. 1044 * | | |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high 1045 * | | |Write 1 to this bit clears the WOLIF status. 1046 * | | |0 = The EMAC does not receive the Magic Packet. 1047 * | | |1 = The EMAC receives a Magic Packet. 1048 * |[16] |TXIF |Transmit Interrupt 1049 * | | |The TXIF indicates the TX interrupt status. 1050 * | | |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates 1051 * | | |the EMAC generates TX interrupt to CPU 1052 * | | |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated. 1053 * | | |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17] 1054 * | | |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit 1055 * | | |in EMAC_INTEN[28:17] is also enabled, the TXIF will be high 1056 * | | |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too. 1057 * | | |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled. 1058 * | | |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit 1059 * | | |in EMAC_INTEN[28:17] is enabled, too. 1060 * |[17] |TXUDIF |Transmit FIFO Underflow Interrupt 1061 * | | |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission 1062 * | | |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically 1063 * | | |without S/W intervention 1064 * | | |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, 1065 * | | |the TXFIFOTH of FFTCR register, to higher level. 1066 * | | |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high 1067 * | | |Write 1 to this bit clears the TXUDIF status. 1068 * | | |0 = No TXFIFO underflow occurred during packet transmission. 1069 * | | |1 = TXFIFO underflow occurred during packet transmission. 1070 * |[18] |TXCPIF |Transmit Completion Interrupt 1071 * | | |The TXCPIF indicates the packet transmission has completed correctly. 1072 * | | |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high 1073 * | | |Write 1 to this bit clears the TXCPIF status. 1074 * | | |0 = The packet transmission not completed. 1075 * | | |1 = The packet transmission has completed. 1076 * |[19] |EXDEFIF |Defer Exceed Interrupt 1077 * | | |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms 1078 * | | |on 100Mbps mode, or 3.2768ms on 10Mbps mode. 1079 * | | |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC 1080 * | | |is operating on half-duplex mode. 1081 * | | |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high 1082 * | | |Write 1 to this bit clears the EXDEFIF status. 1083 * | | |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). 1084 * | | |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). 1085 * |[20] |NCSIF |No Carrier Sense Interrupt 1086 * | | |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during 1087 * | | |the packet transmission 1088 * | | |The NCSIF is only available while EMAC is operating on half-duplex mode 1089 * | | |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high. 1090 * | | |Write 1 to this bit clears the NCSIF status. 1091 * | | |0 = CRS signal actives correctly. 1092 * | | |1 = CRS signal does not active at the start of or during the packet transmission. 1093 * |[21] |TXABTIF |Transmit Abort Interrupt 1094 * | | |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission, 1095 * | | |and then the transmission process for this packet is aborted 1096 * | | |The transmission abort is only available while EMAC is operating on half-duplex mode. 1097 * | | |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high 1098 * | | |Write 1 to this bit clears the TXABTIF status. 1099 * | | |0 = Packet does not incur 16 consecutive collisions during transmission. 1100 * | | |1 = Packet incurred 16 consecutive collisions during transmission. 1101 * |[22] |LCIF |Late Collision Interrupt 1102 * | | |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window 1103 * | | |This means after the 64 bytes of a frame has been transmitted out to the network, the collision 1104 * | | |still occurred. 1105 * | | |The late collision check will only be done while EMAC is operating on half-duplex mode 1106 * | | |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high. 1107 * | | |Write 1 to this bit clears the LCIF status. 1108 * | | |0 = No collision occurred in the outside of 64 bytes collision window. 1109 * | | |1 = Collision occurred in the outside of 64 bytes collision window. 1110 * |[23] |TDUIF |Transmit Descriptor Unavailable Interrupt 1111 * | | |The TDUIF high indicates that there is no available TX descriptor for packet transmission and 1112 * | | |TXDMA will stay at Halt state. 1113 * | | |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make 1114 * | | |TXDMA leave Halt state while new TX descriptor is available. 1115 * | | |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high. 1116 * | | |Write 1 to this bit clears the TDUIF status. 1117 * | | |0 = TX descriptor is available. 1118 * | | |1 = TX descriptor is unavailable. 1119 * |[24] |TXBEIF |Transmit Bus Error Interrupt 1120 * | | |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system 1121 * | | |memory through TXDMA during packet transmission process 1122 * | | |Reset EMAC is recommended while TXBEIF status is high. 1123 * | | |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high. 1124 * | | |Write 1 to this bit clears the TXBEIF status. 1125 * | | |0 = No ERROR response is received. 1126 * | | |1 = ERROR response is received. 1127 * |[28] |TSALMIF |Time Stamp Alarm Interrupt 1128 * | | |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and 1129 * | | |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR. 1130 * | | |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high. 1131 * | | |Write 1 to this bit clears the TSALMIF status. 1132 * | | |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC. 1133 * | | |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC. 1134 * @var EMAC_T::GENSTS 1135 * Offset: 0xB4 MAC General Status Register 1136 * --------------------------------------------------------------------------------------------------- 1137 * |Bits |Field |Descriptions 1138 * | :----: | :----: | :---- | 1139 * |[0] |CFR |Control Frame Received 1140 * | | |The CFRIF high indicates EMAC receives a flow control frame 1141 * | | |The CFRIF only available while EMAC is operating on full duplex mode. 1142 * | | |0 = The EMAC does not receive the flow control frame. 1143 * | | |1 = The EMAC receives a flow control frame. 1144 * |[1] |RXHALT |Receive Halted 1145 * | | |The RXHALT high indicates the next normal packet reception process will be halted because 1146 * | | |the bit RXON of MCMDR is disabled be S/W. 1147 * | | |0 = Next normal packet reception process will go on. 1148 * | | |1 = Next normal packet reception process will be halted. 1149 * |[2] |RXFFULL |RXFIFO Full 1150 * | | |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO 1151 * | | |and the following incoming packet will be dropped. 1152 * | | |0 = The RXFIFO is not full. 1153 * | | |1 = The RXFIFO is full and the following incoming packet will be dropped. 1154 * |[7:4] |COLCNT |Collision Count 1155 * | | |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission 1156 * | | |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be 1157 * | | |0 and bit TXABTIF will be set to 1. 1158 * |[8] |DEF |Deferred Transmission 1159 * | | |The DEF high indicates the packet transmission has deferred once 1160 * | | |The DEF is only available while EMAC is operating on half-duplex mode. 1161 * | | |0 = Packet transmission does not defer. 1162 * | | |1 = Packet transmission has deferred once. 1163 * |[9] |TXPAUSED |Transmission Paused 1164 * | | |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally 1165 * | | |because EMAC received a PAUSE control frame. 1166 * | | |0 = Next normal packet transmission process will go on. 1167 * | | |1 = Next normal packet transmission process will be paused. 1168 * |[10] |SQE |Signal Quality Error 1169 * | | |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode 1170 * | | |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC 1171 * | | |is operating on 10Mbps half-duplex mode. 1172 * | | |0 = No SQE error found at end of packet transmission. 1173 * | | |1 = SQE error found at end of packet transmission. 1174 * |[11] |TXHALT |Transmission Halted 1175 * | | |The TXHALT high indicates the next normal packet transmission process will be halted because 1176 * | | |the bit TXON (EMAC_CTL[8]) is disabled be S/W. 1177 * | | |0 = Next normal packet transmission process will go on. 1178 * | | |1 = Next normal packet transmission process will be halted. 1179 * |[12] |RPSTS |Remote Pause Status 1180 * | | |The RPSTS indicates that remote pause counter down counting actives. 1181 * | | |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause 1182 * | | |counter down counting 1183 * | | |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet 1184 * | | |transmission until the down counting done. 1185 * | | |0 = Remote pause counter down counting done. 1186 * | | |1 = Remote pause counter down counting actives. 1187 * @var EMAC_T::MPCNT 1188 * Offset: 0xB8 Missed Packet Count Register 1189 * --------------------------------------------------------------------------------------------------- 1190 * |Bits |Field |Descriptions 1191 * | :----: | :----: | :---- | 1192 * |[15:0] |MPCNT |Miss Packet Count 1193 * | | |The MPCNT indicates the number of packets that were dropped due to various types of receive errors 1194 * | | |The following type of receiving error makes missed packet counter increase: 1195 * | | |1. Incoming packet is incurred RXFIFO overflow. 1196 * | | |2. Incoming packet is dropped due to RXON is disabled. 1197 * | | |3. Incoming packet is incurred CRC error. 1198 * @var EMAC_T::RPCNT 1199 * Offset: 0xBC MAC Receive Pause Count Register 1200 * --------------------------------------------------------------------------------------------------- 1201 * |Bits |Field |Descriptions 1202 * | :----: | :----: | :---- | 1203 * |[15:0] |RPCNT |MAC Receive Pause Count 1204 * | | |The RPCNT keeps the OPERAND field of the PAUSE control frame 1205 * | | |It indicates how many slot time (512 bit time) the TX of EMAC will be paused. 1206 * @var EMAC_T::FRSTS 1207 * Offset: 0xC8 DMA Receive Frame Status Register 1208 * --------------------------------------------------------------------------------------------------- 1209 * |Bits |Field |Descriptions 1210 * | :----: | :----: | :---- | 1211 * |[15:0] |RXFLT |Receive Frame LENGTH 1212 * | | |The RXFLT keeps the LENGTH field of each incoming Ethernet packet 1213 * | | |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has 1214 * | | |received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt. 1215 * | | |And, the content of LENGTH field will be stored in RXFLT. 1216 * @var EMAC_T::CTXDSA 1217 * Offset: 0xCC Current Transmit Descriptor Start Address Register 1218 * --------------------------------------------------------------------------------------------------- 1219 * |Bits |Field |Descriptions 1220 * | :----: | :----: | :---- | 1221 * |[31:0] |CTXDSA |Current Transmit Descriptor Start Address 1222 * | | |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently 1223 * | | |The CTXDSA is read only and write to this register has no effect. 1224 * @var EMAC_T::CTXBSA 1225 * Offset: 0xD0 Current Transmit Buffer Start Address Register 1226 * --------------------------------------------------------------------------------------------------- 1227 * |Bits |Field |Descriptions 1228 * | :----: | :----: | :---- | 1229 * |[31:0] |CTXBSA |Current Transmit Buffer Start Address 1230 * | | |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently 1231 * | | |The CTXBSA is read only and write to this register has no effect. 1232 * @var EMAC_T::CRXDSA 1233 * Offset: 0xD4 Current Receive Descriptor Start Address Register 1234 * --------------------------------------------------------------------------------------------------- 1235 * |Bits |Field |Descriptions 1236 * | :----: | :----: | :---- | 1237 * |[31:0] |CRXDSA |Current Receive Descriptor Start Address 1238 * | | |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently 1239 * | | |The CRXDSA is read only and write to this register has no effect. 1240 * @var EMAC_T::CRXBSA 1241 * Offset: 0xD8 Current Receive Buffer Start Address Register 1242 * --------------------------------------------------------------------------------------------------- 1243 * |Bits |Field |Descriptions 1244 * | :----: | :----: | :---- | 1245 * |[31:0] |CRXBSA |Current Receive Buffer Start Address 1246 * | | |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently 1247 * | | |The CRXBSA is read only and write to this register has no effect. 1248 * @var EMAC_T::TSCTL 1249 * Offset: 0x100 Time Stamp Control Register 1250 * --------------------------------------------------------------------------------------------------- 1251 * |Bits |Field |Descriptions 1252 * | :----: | :----: | :---- | 1253 * |[0] |TSEN |Time Stamp Function Enable Bit 1254 * | | |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not. 1255 * | | |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low 1256 * | | |to disable IEEE 1588 PTP time stamp function. 1257 * | | |0 = I EEE 1588 PTP time stamp function Disabled. 1258 * | | |1 = IEEE 1588 PTP time stamp function Enabled. 1259 * |[1] |TSIEN |Time Stamp Counter Initialization Enable Bit 1260 * | | |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC 1261 * | | |and EMAC_UPDSUBSEC to PTP time stamp counter. 1262 * | | |After the load operation finished, Ethernet MAC controller clear this bit to low automatically. 1263 * | | |0 = Time stamp counter initialization done. 1264 * | | |1 = Time stamp counter initialization Enabled. 1265 * |[2] |TSMODE |Time Stamp Fine Update Enable Bit 1266 * | | |This bit chooses the time stamp counter update mode. 1267 * | | |0 = Time stamp counter is in coarse update mode. 1268 * | | |1 = Time stamp counter is in fine update mode. 1269 * |[3] |TSUPDATE |Time Stamp Counter Time Update Enable Bit 1270 * | | |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and 1271 * | | |EMAC_UPDSUBSEC to PTP time stamp counter. 1272 * | | |After the add operation finished, Ethernet MAC controller clear this bit to low automatically. 1273 * | | |0 = No action. 1274 * | | |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC. 1275 * |[5] |TSALMEN |Time Stamp Alarm Enable Bit 1276 * | | |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when 1277 * | | |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. 1278 * | | |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. 1279 * | | |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. 1280 * @var EMAC_T::TSSEC 1281 * Offset: 0x110 Time Stamp Counter Second Register 1282 * --------------------------------------------------------------------------------------------------- 1283 * |Bits |Field |Descriptions 1284 * | :----: | :----: | :---- | 1285 * |[31:0] |SEC |Time Stamp Counter Second 1286 * | | |This register reflects the bit [63:32] value of 64-bit reference timing counter 1287 * | | |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. 1288 * @var EMAC_T::TSSUBSEC 1289 * Offset: 0x114 Time Stamp Counter Sub Second Register 1290 * --------------------------------------------------------------------------------------------------- 1291 * |Bits |Field |Descriptions 1292 * | :----: | :----: | :---- | 1293 * |[31:0] |SUBSEC |Time Stamp Counter Sub-second 1294 * | | |This register reflects the bit [31:0] value of 64-bit reference timing counter 1295 * | | |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. 1296 * @var EMAC_T::TSINC 1297 * Offset: 0x118 Time Stamp Increment Register 1298 * --------------------------------------------------------------------------------------------------- 1299 * |Bits |Field |Descriptions 1300 * | :----: | :----: | :---- | 1301 * |[7:0] |CNTINC |Time Stamp Counter Increment 1302 * | | |Time stamp counter increment value. 1303 * | | |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every 1304 * | | |time when it wants to increase the EMAC_TSSUBSEC value. 1305 * @var EMAC_T::TSADDEND 1306 * Offset: 0x11C Time Stamp Addend Register 1307 * --------------------------------------------------------------------------------------------------- 1308 * |Bits |Field |Descriptions 1309 * | :----: | :----: | :---- | 1310 * |[31:0] |ADDEND |Time Stamp Counter Addend 1311 * | | |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC. 1312 * | | |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator 1313 * | | |with this 32-bit value in each HCLK 1314 * | | |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit 1315 * | | |value kept in register EMAC_TSINC. 1316 * @var EMAC_T::UPDSEC 1317 * Offset: 0x120 Time Stamp Update Second Register 1318 * --------------------------------------------------------------------------------------------------- 1319 * |Bits |Field |Descriptions 1320 * | :----: | :----: | :---- | 1321 * |[31:0] |SEC |Time Stamp Counter Second Update 1322 * | | |When TSIEN (EMAC_TSCTL[1]) is high 1323 * | | |EMAC loads this 32-bit value to EMAC_TSSEC directly 1324 * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value. 1325 * @var EMAC_T::UPDSUBSEC 1326 * Offset: 0x124 Time Stamp Update Sub Second Register 1327 * --------------------------------------------------------------------------------------------------- 1328 * |Bits |Field |Descriptions 1329 * | :----: | :----: | :---- | 1330 * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Update 1331 * | | |When TSIEN (EMAC_TSCTL[1]) is high 1332 * | | |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly 1333 * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value. 1334 * @var EMAC_T::ALMSEC 1335 * Offset: 0x128 Time Stamp Alarm Second Register 1336 * --------------------------------------------------------------------------------------------------- 1337 * |Bits |Field |Descriptions 1338 * | :----: | :----: | :---- | 1339 * |[31:0] |SEC |Time Stamp Counter Second Alarm 1340 * | | |Time stamp counter second part alarm value. 1341 * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high 1342 * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to 1343 * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. 1344 * @var EMAC_T::ALMSUBSEC 1345 * Offset: 0x12C Time Stamp Alarm Sub Second Register 1346 * --------------------------------------------------------------------------------------------------- 1347 * |Bits |Field |Descriptions 1348 * | :----: | :----: | :---- | 1349 * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Alarm 1350 * | | |Time stamp counter sub-second part alarm value. 1351 * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high 1352 * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to 1353 * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. 1354 */ 1355 __IO uint32_t CAMCTL; /*!< [0x0000] CAM Comparison Control Register */ 1356 __IO uint32_t CAMEN; /*!< [0x0004] CAM Enable Register */ 1357 __IO uint32_t CAM0M; /*!< [0x0008] CAM0 Most Significant Word Register */ 1358 __IO uint32_t CAM0L; /*!< [0x000c] CAM0 Least Significant Word Register */ 1359 __IO uint32_t CAM1M; /*!< [0x0010] CAM1 Most Significant Word Register */ 1360 __IO uint32_t CAM1L; /*!< [0x0014] CAM1 Least Significant Word Register */ 1361 __IO uint32_t CAM2M; /*!< [0x0018] CAM2 Most Significant Word Register */ 1362 __IO uint32_t CAM2L; /*!< [0x001c] CAM2 Least Significant Word Register */ 1363 __IO uint32_t CAM3M; /*!< [0x0020] CAM3 Most Significant Word Register */ 1364 __IO uint32_t CAM3L; /*!< [0x0024] CAM3 Least Significant Word Register */ 1365 __IO uint32_t CAM4M; /*!< [0x0028] CAM4 Most Significant Word Register */ 1366 __IO uint32_t CAM4L; /*!< [0x002c] CAM4 Least Significant Word Register */ 1367 __IO uint32_t CAM5M; /*!< [0x0030] CAM5 Most Significant Word Register */ 1368 __IO uint32_t CAM5L; /*!< [0x0034] CAM5 Least Significant Word Register */ 1369 __IO uint32_t CAM6M; /*!< [0x0038] CAM6 Most Significant Word Register */ 1370 __IO uint32_t CAM6L; /*!< [0x003c] CAM6 Least Significant Word Register */ 1371 __IO uint32_t CAM7M; /*!< [0x0040] CAM7 Most Significant Word Register */ 1372 __IO uint32_t CAM7L; /*!< [0x0044] CAM7 Least Significant Word Register */ 1373 __IO uint32_t CAM8M; /*!< [0x0048] CAM8 Most Significant Word Register */ 1374 __IO uint32_t CAM8L; /*!< [0x004c] CAM8 Least Significant Word Register */ 1375 __IO uint32_t CAM9M; /*!< [0x0050] CAM9 Most Significant Word Register */ 1376 __IO uint32_t CAM9L; /*!< [0x0054] CAM9 Least Significant Word Register */ 1377 __IO uint32_t CAM10M; /*!< [0x0058] CAM10 Most Significant Word Register */ 1378 __IO uint32_t CAM10L; /*!< [0x005c] CAM10 Least Significant Word Register */ 1379 __IO uint32_t CAM11M; /*!< [0x0060] CAM11 Most Significant Word Register */ 1380 __IO uint32_t CAM11L; /*!< [0x0064] CAM11 Least Significant Word Register */ 1381 __IO uint32_t CAM12M; /*!< [0x0068] CAM12 Most Significant Word Register */ 1382 __IO uint32_t CAM12L; /*!< [0x006c] CAM12 Least Significant Word Register */ 1383 __IO uint32_t CAM13M; /*!< [0x0070] CAM13 Most Significant Word Register */ 1384 __IO uint32_t CAM13L; /*!< [0x0074] CAM13 Least Significant Word Register */ 1385 __IO uint32_t CAM14M; /*!< [0x0078] CAM14 Most Significant Word Register */ 1386 __IO uint32_t CAM14L; /*!< [0x007c] CAM14 Least Significant Word Register */ 1387 __IO uint32_t CAM15MSB; /*!< [0x0080] CAM15 Most Significant Word Register */ 1388 __IO uint32_t CAM15LSB; /*!< [0x0084] CAM15 Least Significant Word Register */ 1389 __IO uint32_t TXDSA; /*!< [0x0088] Transmit Descriptor Link List Start Address Register */ 1390 __IO uint32_t RXDSA; /*!< [0x008c] Receive Descriptor Link List Start Address Register */ 1391 __IO uint32_t CTL; /*!< [0x0090] MAC Control Register */ 1392 __IO uint32_t MIIMDAT; /*!< [0x0094] MII Management Data Register */ 1393 __IO uint32_t MIIMCTL; /*!< [0x0098] MII Management Control and Address Register */ 1394 __IO uint32_t FIFOCTL; /*!< [0x009c] FIFO Threshold Control Register */ 1395 __O uint32_t TXST; /*!< [0x00a0] Transmit Start Demand Register */ 1396 __O uint32_t RXST; /*!< [0x00a4] Receive Start Demand Register */ 1397 __IO uint32_t MRFL; /*!< [0x00a8] Maximum Receive Frame Control Register */ 1398 __IO uint32_t INTEN; /*!< [0x00ac] MAC Interrupt Enable Register */ 1399 __IO uint32_t INTSTS; /*!< [0x00b0] MAC Interrupt Status Register */ 1400 __IO uint32_t GENSTS; /*!< [0x00b4] MAC General Status Register */ 1401 __IO uint32_t MPCNT; /*!< [0x00b8] Missed Packet Count Register */ 1402 __I uint32_t RPCNT; /*!< [0x00bc] MAC Receive Pause Count Register */ 1403 /** @cond HIDDEN_SYMBOLS */ 1404 __I uint32_t RESERVE0[2]; 1405 /** @endcond */ 1406 __IO uint32_t FRSTS; /*!< [0x00c8] DMA Receive Frame Status Register */ 1407 __I uint32_t CTXDSA; /*!< [0x00cc] Current Transmit Descriptor Start Address Register */ 1408 __I uint32_t CTXBSA; /*!< [0x00d0] Current Transmit Buffer Start Address Register */ 1409 __I uint32_t CRXDSA; /*!< [0x00d4] Current Receive Descriptor Start Address Register */ 1410 __I uint32_t CRXBSA; /*!< [0x00d8] Current Receive Buffer Start Address Register */ 1411 /** @cond HIDDEN_SYMBOLS */ 1412 __I uint32_t RESERVE1[9]; 1413 /** @endcond */ 1414 __IO uint32_t TSCTL; /*!< [0x0100] Time Stamp Control Register */ 1415 /** @cond HIDDEN_SYMBOLS */ 1416 __I uint32_t RESERVE2[3]; 1417 /** @endcond */ 1418 __I uint32_t TSSEC; /*!< [0x0110] Time Stamp Counter Second Register */ 1419 __I uint32_t TSSUBSEC; /*!< [0x0114] Time Stamp Counter Sub Second Register */ 1420 __IO uint32_t TSINC; /*!< [0x0118] Time Stamp Increment Register */ 1421 __IO uint32_t TSADDEND; /*!< [0x011c] Time Stamp Addend Register */ 1422 __IO uint32_t UPDSEC; /*!< [0x0120] Time Stamp Update Second Register */ 1423 __IO uint32_t UPDSUBSEC; /*!< [0x0124] Time Stamp Update Sub Second Register */ 1424 __IO uint32_t ALMSEC; /*!< [0x0128] Time Stamp Alarm Second Register */ 1425 __IO uint32_t ALMSUBSEC; /*!< [0x012c] Time Stamp Alarm Sub Second Register */ 1426 1427 } EMAC_T; 1428 1429 /** 1430 @addtogroup EMAC_CONST EMAC Bit Field Definition 1431 Constant Definitions for EMAC Controller 1432 @{ */ 1433 1434 #define EMAC_CAMCTL_AUP_Pos (0) /*!< EMAC_T::CAMCTL: AUP Position */ 1435 #define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /*!< EMAC_T::CAMCTL: AUP Mask */ 1436 1437 #define EMAC_CAMCTL_AMP_Pos (1) /*!< EMAC_T::CAMCTL: AMP Position */ 1438 #define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /*!< EMAC_T::CAMCTL: AMP Mask */ 1439 1440 #define EMAC_CAMCTL_ABP_Pos (2) /*!< EMAC_T::CAMCTL: ABP Position */ 1441 #define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /*!< EMAC_T::CAMCTL: ABP Mask */ 1442 1443 #define EMAC_CAMCTL_COMPEN_Pos (3) /*!< EMAC_T::CAMCTL: COMPEN Position */ 1444 #define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /*!< EMAC_T::CAMCTL: COMPEN Mask */ 1445 1446 #define EMAC_CAMCTL_CMPEN_Pos (4) /*!< EMAC_T::CAMCTL: CMPEN Position */ 1447 #define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /*!< EMAC_T::CAMCTL: CMPEN Mask */ 1448 1449 #define EMAC_CAMEN_CAMxEN_Pos (0) /*!< EMAC_T::CAMEN: CAMxEN Position */ 1450 #define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /*!< EMAC_T::CAMEN: CAMxEN Mask */ 1451 1452 #define EMAC_CAM0M_MACADDR2_Pos (0) /*!< EMAC_T::CAM0M: MACADDR2 Position */ 1453 #define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /*!< EMAC_T::CAM0M: MACADDR2 Mask */ 1454 1455 #define EMAC_CAM0M_MACADDR3_Pos (8) /*!< EMAC_T::CAM0M: MACADDR3 Position */ 1456 #define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /*!< EMAC_T::CAM0M: MACADDR3 Mask */ 1457 1458 #define EMAC_CAM0M_MACADDR4_Pos (16) /*!< EMAC_T::CAM0M: MACADDR4 Position */ 1459 #define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /*!< EMAC_T::CAM0M: MACADDR4 Mask */ 1460 1461 #define EMAC_CAM0M_MACADDR5_Pos (24) /*!< EMAC_T::CAM0M: MACADDR5 Position */ 1462 #define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /*!< EMAC_T::CAM0M: MACADDR5 Mask */ 1463 1464 #define EMAC_CAM0L_MACADDR0_Pos (16) /*!< EMAC_T::CAM0L: MACADDR0 Position */ 1465 #define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /*!< EMAC_T::CAM0L: MACADDR0 Mask */ 1466 1467 #define EMAC_CAM0L_MACADDR1_Pos (24) /*!< EMAC_T::CAM0L: MACADDR1 Position */ 1468 #define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /*!< EMAC_T::CAM0L: MACADDR1 Mask */ 1469 1470 #define EMAC_CAM1M_MACADDR2_Pos (0) /*!< EMAC_T::CAM1M: MACADDR2 Position */ 1471 #define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /*!< EMAC_T::CAM1M: MACADDR2 Mask */ 1472 1473 #define EMAC_CAM1M_MACADDR3_Pos (8) /*!< EMAC_T::CAM1M: MACADDR3 Position */ 1474 #define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /*!< EMAC_T::CAM1M: MACADDR3 Mask */ 1475 1476 #define EMAC_CAM1M_MACADDR4_Pos (16) /*!< EMAC_T::CAM1M: MACADDR4 Position */ 1477 #define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /*!< EMAC_T::CAM1M: MACADDR4 Mask */ 1478 1479 #define EMAC_CAM1M_MACADDR5_Pos (24) /*!< EMAC_T::CAM1M: MACADDR5 Position */ 1480 #define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /*!< EMAC_T::CAM1M: MACADDR5 Mask */ 1481 1482 #define EMAC_CAM1L_MACADDR0_Pos (16) /*!< EMAC_T::CAM1L: MACADDR0 Position */ 1483 #define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /*!< EMAC_T::CAM1L: MACADDR0 Mask */ 1484 1485 #define EMAC_CAM1L_MACADDR1_Pos (24) /*!< EMAC_T::CAM1L: MACADDR1 Position */ 1486 #define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /*!< EMAC_T::CAM1L: MACADDR1 Mask */ 1487 1488 #define EMAC_CAM2M_MACADDR2_Pos (0) /*!< EMAC_T::CAM2M: MACADDR2 Position */ 1489 #define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /*!< EMAC_T::CAM2M: MACADDR2 Mask */ 1490 1491 #define EMAC_CAM2M_MACADDR3_Pos (8) /*!< EMAC_T::CAM2M: MACADDR3 Position */ 1492 #define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /*!< EMAC_T::CAM2M: MACADDR3 Mask */ 1493 1494 #define EMAC_CAM2M_MACADDR4_Pos (16) /*!< EMAC_T::CAM2M: MACADDR4 Position */ 1495 #define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /*!< EMAC_T::CAM2M: MACADDR4 Mask */ 1496 1497 #define EMAC_CAM2M_MACADDR5_Pos (24) /*!< EMAC_T::CAM2M: MACADDR5 Position */ 1498 #define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /*!< EMAC_T::CAM2M: MACADDR5 Mask */ 1499 1500 #define EMAC_CAM2L_MACADDR0_Pos (16) /*!< EMAC_T::CAM2L: MACADDR0 Position */ 1501 #define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /*!< EMAC_T::CAM2L: MACADDR0 Mask */ 1502 1503 #define EMAC_CAM2L_MACADDR1_Pos (24) /*!< EMAC_T::CAM2L: MACADDR1 Position */ 1504 #define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /*!< EMAC_T::CAM2L: MACADDR1 Mask */ 1505 1506 #define EMAC_CAM3M_MACADDR2_Pos (0) /*!< EMAC_T::CAM3M: MACADDR2 Position */ 1507 #define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /*!< EMAC_T::CAM3M: MACADDR2 Mask */ 1508 1509 #define EMAC_CAM3M_MACADDR3_Pos (8) /*!< EMAC_T::CAM3M: MACADDR3 Position */ 1510 #define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /*!< EMAC_T::CAM3M: MACADDR3 Mask */ 1511 1512 #define EMAC_CAM3M_MACADDR4_Pos (16) /*!< EMAC_T::CAM3M: MACADDR4 Position */ 1513 #define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /*!< EMAC_T::CAM3M: MACADDR4 Mask */ 1514 1515 #define EMAC_CAM3M_MACADDR5_Pos (24) /*!< EMAC_T::CAM3M: MACADDR5 Position */ 1516 #define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /*!< EMAC_T::CAM3M: MACADDR5 Mask */ 1517 1518 #define EMAC_CAM3L_MACADDR0_Pos (16) /*!< EMAC_T::CAM3L: MACADDR0 Position */ 1519 #define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /*!< EMAC_T::CAM3L: MACADDR0 Mask */ 1520 1521 #define EMAC_CAM3L_MACADDR1_Pos (24) /*!< EMAC_T::CAM3L: MACADDR1 Position */ 1522 #define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /*!< EMAC_T::CAM3L: MACADDR1 Mask */ 1523 1524 #define EMAC_CAM4M_MACADDR2_Pos (0) /*!< EMAC_T::CAM4M: MACADDR2 Position */ 1525 #define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /*!< EMAC_T::CAM4M: MACADDR2 Mask */ 1526 1527 #define EMAC_CAM4M_MACADDR3_Pos (8) /*!< EMAC_T::CAM4M: MACADDR3 Position */ 1528 #define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /*!< EMAC_T::CAM4M: MACADDR3 Mask */ 1529 1530 #define EMAC_CAM4M_MACADDR4_Pos (16) /*!< EMAC_T::CAM4M: MACADDR4 Position */ 1531 #define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /*!< EMAC_T::CAM4M: MACADDR4 Mask */ 1532 1533 #define EMAC_CAM4M_MACADDR5_Pos (24) /*!< EMAC_T::CAM4M: MACADDR5 Position */ 1534 #define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /*!< EMAC_T::CAM4M: MACADDR5 Mask */ 1535 1536 #define EMAC_CAM4L_MACADDR0_Pos (16) /*!< EMAC_T::CAM4L: MACADDR0 Position */ 1537 #define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /*!< EMAC_T::CAM4L: MACADDR0 Mask */ 1538 1539 #define EMAC_CAM4L_MACADDR1_Pos (24) /*!< EMAC_T::CAM4L: MACADDR1 Position */ 1540 #define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /*!< EMAC_T::CAM4L: MACADDR1 Mask */ 1541 1542 #define EMAC_CAM5M_MACADDR2_Pos (0) /*!< EMAC_T::CAM5M: MACADDR2 Position */ 1543 #define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /*!< EMAC_T::CAM5M: MACADDR2 Mask */ 1544 1545 #define EMAC_CAM5M_MACADDR3_Pos (8) /*!< EMAC_T::CAM5M: MACADDR3 Position */ 1546 #define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /*!< EMAC_T::CAM5M: MACADDR3 Mask */ 1547 1548 #define EMAC_CAM5M_MACADDR4_Pos (16) /*!< EMAC_T::CAM5M: MACADDR4 Position */ 1549 #define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /*!< EMAC_T::CAM5M: MACADDR4 Mask */ 1550 1551 #define EMAC_CAM5M_MACADDR5_Pos (24) /*!< EMAC_T::CAM5M: MACADDR5 Position */ 1552 #define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /*!< EMAC_T::CAM5M: MACADDR5 Mask */ 1553 1554 #define EMAC_CAM5L_MACADDR0_Pos (16) /*!< EMAC_T::CAM5L: MACADDR0 Position */ 1555 #define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /*!< EMAC_T::CAM5L: MACADDR0 Mask */ 1556 1557 #define EMAC_CAM5L_MACADDR1_Pos (24) /*!< EMAC_T::CAM5L: MACADDR1 Position */ 1558 #define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /*!< EMAC_T::CAM5L: MACADDR1 Mask */ 1559 1560 #define EMAC_CAM6M_MACADDR2_Pos (0) /*!< EMAC_T::CAM6M: MACADDR2 Position */ 1561 #define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /*!< EMAC_T::CAM6M: MACADDR2 Mask */ 1562 1563 #define EMAC_CAM6M_MACADDR3_Pos (8) /*!< EMAC_T::CAM6M: MACADDR3 Position */ 1564 #define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /*!< EMAC_T::CAM6M: MACADDR3 Mask */ 1565 1566 #define EMAC_CAM6M_MACADDR4_Pos (16) /*!< EMAC_T::CAM6M: MACADDR4 Position */ 1567 #define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /*!< EMAC_T::CAM6M: MACADDR4 Mask */ 1568 1569 #define EMAC_CAM6M_MACADDR5_Pos (24) /*!< EMAC_T::CAM6M: MACADDR5 Position */ 1570 #define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /*!< EMAC_T::CAM6M: MACADDR5 Mask */ 1571 1572 #define EMAC_CAM6L_MACADDR0_Pos (16) /*!< EMAC_T::CAM6L: MACADDR0 Position */ 1573 #define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /*!< EMAC_T::CAM6L: MACADDR0 Mask */ 1574 1575 #define EMAC_CAM6L_MACADDR1_Pos (24) /*!< EMAC_T::CAM6L: MACADDR1 Position */ 1576 #define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /*!< EMAC_T::CAM6L: MACADDR1 Mask */ 1577 1578 #define EMAC_CAM7M_MACADDR2_Pos (0) /*!< EMAC_T::CAM7M: MACADDR2 Position */ 1579 #define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /*!< EMAC_T::CAM7M: MACADDR2 Mask */ 1580 1581 #define EMAC_CAM7M_MACADDR3_Pos (8) /*!< EMAC_T::CAM7M: MACADDR3 Position */ 1582 #define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /*!< EMAC_T::CAM7M: MACADDR3 Mask */ 1583 1584 #define EMAC_CAM7M_MACADDR4_Pos (16) /*!< EMAC_T::CAM7M: MACADDR4 Position */ 1585 #define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /*!< EMAC_T::CAM7M: MACADDR4 Mask */ 1586 1587 #define EMAC_CAM7M_MACADDR5_Pos (24) /*!< EMAC_T::CAM7M: MACADDR5 Position */ 1588 #define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /*!< EMAC_T::CAM7M: MACADDR5 Mask */ 1589 1590 #define EMAC_CAM7L_MACADDR0_Pos (16) /*!< EMAC_T::CAM7L: MACADDR0 Position */ 1591 #define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /*!< EMAC_T::CAM7L: MACADDR0 Mask */ 1592 1593 #define EMAC_CAM7L_MACADDR1_Pos (24) /*!< EMAC_T::CAM7L: MACADDR1 Position */ 1594 #define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /*!< EMAC_T::CAM7L: MACADDR1 Mask */ 1595 1596 #define EMAC_CAM8M_MACADDR2_Pos (0) /*!< EMAC_T::CAM8M: MACADDR2 Position */ 1597 #define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /*!< EMAC_T::CAM8M: MACADDR2 Mask */ 1598 1599 #define EMAC_CAM8M_MACADDR3_Pos (8) /*!< EMAC_T::CAM8M: MACADDR3 Position */ 1600 #define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /*!< EMAC_T::CAM8M: MACADDR3 Mask */ 1601 1602 #define EMAC_CAM8M_MACADDR4_Pos (16) /*!< EMAC_T::CAM8M: MACADDR4 Position */ 1603 #define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /*!< EMAC_T::CAM8M: MACADDR4 Mask */ 1604 1605 #define EMAC_CAM8M_MACADDR5_Pos (24) /*!< EMAC_T::CAM8M: MACADDR5 Position */ 1606 #define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /*!< EMAC_T::CAM8M: MACADDR5 Mask */ 1607 1608 #define EMAC_CAM8L_MACADDR0_Pos (16) /*!< EMAC_T::CAM8L: MACADDR0 Position */ 1609 #define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /*!< EMAC_T::CAM8L: MACADDR0 Mask */ 1610 1611 #define EMAC_CAM8L_MACADDR1_Pos (24) /*!< EMAC_T::CAM8L: MACADDR1 Position */ 1612 #define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /*!< EMAC_T::CAM8L: MACADDR1 Mask */ 1613 1614 #define EMAC_CAM9M_MACADDR2_Pos (0) /*!< EMAC_T::CAM9M: MACADDR2 Position */ 1615 #define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /*!< EMAC_T::CAM9M: MACADDR2 Mask */ 1616 1617 #define EMAC_CAM9M_MACADDR3_Pos (8) /*!< EMAC_T::CAM9M: MACADDR3 Position */ 1618 #define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /*!< EMAC_T::CAM9M: MACADDR3 Mask */ 1619 1620 #define EMAC_CAM9M_MACADDR4_Pos (16) /*!< EMAC_T::CAM9M: MACADDR4 Position */ 1621 #define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /*!< EMAC_T::CAM9M: MACADDR4 Mask */ 1622 1623 #define EMAC_CAM9M_MACADDR5_Pos (24) /*!< EMAC_T::CAM9M: MACADDR5 Position */ 1624 #define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /*!< EMAC_T::CAM9M: MACADDR5 Mask */ 1625 1626 #define EMAC_CAM9L_MACADDR0_Pos (16) /*!< EMAC_T::CAM9L: MACADDR0 Position */ 1627 #define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /*!< EMAC_T::CAM9L: MACADDR0 Mask */ 1628 1629 #define EMAC_CAM9L_MACADDR1_Pos (24) /*!< EMAC_T::CAM9L: MACADDR1 Position */ 1630 #define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /*!< EMAC_T::CAM9L: MACADDR1 Mask */ 1631 1632 #define EMAC_CAM10M_MACADDR2_Pos (0) /*!< EMAC_T::CAM10M: MACADDR2 Position */ 1633 #define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /*!< EMAC_T::CAM10M: MACADDR2 Mask */ 1634 1635 #define EMAC_CAM10M_MACADDR3_Pos (8) /*!< EMAC_T::CAM10M: MACADDR3 Position */ 1636 #define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /*!< EMAC_T::CAM10M: MACADDR3 Mask */ 1637 1638 #define EMAC_CAM10M_MACADDR4_Pos (16) /*!< EMAC_T::CAM10M: MACADDR4 Position */ 1639 #define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /*!< EMAC_T::CAM10M: MACADDR4 Mask */ 1640 1641 #define EMAC_CAM10M_MACADDR5_Pos (24) /*!< EMAC_T::CAM10M: MACADDR5 Position */ 1642 #define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /*!< EMAC_T::CAM10M: MACADDR5 Mask */ 1643 1644 #define EMAC_CAM10L_MACADDR0_Pos (16) /*!< EMAC_T::CAM10L: MACADDR0 Position */ 1645 #define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /*!< EMAC_T::CAM10L: MACADDR0 Mask */ 1646 1647 #define EMAC_CAM10L_MACADDR1_Pos (24) /*!< EMAC_T::CAM10L: MACADDR1 Position */ 1648 #define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /*!< EMAC_T::CAM10L: MACADDR1 Mask */ 1649 1650 #define EMAC_CAM11M_MACADDR2_Pos (0) /*!< EMAC_T::CAM11M: MACADDR2 Position */ 1651 #define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /*!< EMAC_T::CAM11M: MACADDR2 Mask */ 1652 1653 #define EMAC_CAM11M_MACADDR3_Pos (8) /*!< EMAC_T::CAM11M: MACADDR3 Position */ 1654 #define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /*!< EMAC_T::CAM11M: MACADDR3 Mask */ 1655 1656 #define EMAC_CAM11M_MACADDR4_Pos (16) /*!< EMAC_T::CAM11M: MACADDR4 Position */ 1657 #define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /*!< EMAC_T::CAM11M: MACADDR4 Mask */ 1658 1659 #define EMAC_CAM11M_MACADDR5_Pos (24) /*!< EMAC_T::CAM11M: MACADDR5 Position */ 1660 #define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /*!< EMAC_T::CAM11M: MACADDR5 Mask */ 1661 1662 #define EMAC_CAM11L_MACADDR0_Pos (16) /*!< EMAC_T::CAM11L: MACADDR0 Position */ 1663 #define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /*!< EMAC_T::CAM11L: MACADDR0 Mask */ 1664 1665 #define EMAC_CAM11L_MACADDR1_Pos (24) /*!< EMAC_T::CAM11L: MACADDR1 Position */ 1666 #define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /*!< EMAC_T::CAM11L: MACADDR1 Mask */ 1667 1668 #define EMAC_CAM12M_MACADDR2_Pos (0) /*!< EMAC_T::CAM12M: MACADDR2 Position */ 1669 #define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /*!< EMAC_T::CAM12M: MACADDR2 Mask */ 1670 1671 #define EMAC_CAM12M_MACADDR3_Pos (8) /*!< EMAC_T::CAM12M: MACADDR3 Position */ 1672 #define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /*!< EMAC_T::CAM12M: MACADDR3 Mask */ 1673 1674 #define EMAC_CAM12M_MACADDR4_Pos (16) /*!< EMAC_T::CAM12M: MACADDR4 Position */ 1675 #define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /*!< EMAC_T::CAM12M: MACADDR4 Mask */ 1676 1677 #define EMAC_CAM12M_MACADDR5_Pos (24) /*!< EMAC_T::CAM12M: MACADDR5 Position */ 1678 #define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /*!< EMAC_T::CAM12M: MACADDR5 Mask */ 1679 1680 #define EMAC_CAM12L_MACADDR0_Pos (16) /*!< EMAC_T::CAM12L: MACADDR0 Position */ 1681 #define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /*!< EMAC_T::CAM12L: MACADDR0 Mask */ 1682 1683 #define EMAC_CAM12L_MACADDR1_Pos (24) /*!< EMAC_T::CAM12L: MACADDR1 Position */ 1684 #define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /*!< EMAC_T::CAM12L: MACADDR1 Mask */ 1685 1686 #define EMAC_CAM13M_MACADDR2_Pos (0) /*!< EMAC_T::CAM13M: MACADDR2 Position */ 1687 #define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /*!< EMAC_T::CAM13M: MACADDR2 Mask */ 1688 1689 #define EMAC_CAM13M_MACADDR3_Pos (8) /*!< EMAC_T::CAM13M: MACADDR3 Position */ 1690 #define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /*!< EMAC_T::CAM13M: MACADDR3 Mask */ 1691 1692 #define EMAC_CAM13M_MACADDR4_Pos (16) /*!< EMAC_T::CAM13M: MACADDR4 Position */ 1693 #define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /*!< EMAC_T::CAM13M: MACADDR4 Mask */ 1694 1695 #define EMAC_CAM13M_MACADDR5_Pos (24) /*!< EMAC_T::CAM13M: MACADDR5 Position */ 1696 #define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /*!< EMAC_T::CAM13M: MACADDR5 Mask */ 1697 1698 #define EMAC_CAM13L_MACADDR0_Pos (16) /*!< EMAC_T::CAM13L: MACADDR0 Position */ 1699 #define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /*!< EMAC_T::CAM13L: MACADDR0 Mask */ 1700 1701 #define EMAC_CAM13L_MACADDR1_Pos (24) /*!< EMAC_T::CAM13L: MACADDR1 Position */ 1702 #define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /*!< EMAC_T::CAM13L: MACADDR1 Mask */ 1703 1704 #define EMAC_CAM14M_MACADDR2_Pos (0) /*!< EMAC_T::CAM14M: MACADDR2 Position */ 1705 #define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /*!< EMAC_T::CAM14M: MACADDR2 Mask */ 1706 1707 #define EMAC_CAM14M_MACADDR3_Pos (8) /*!< EMAC_T::CAM14M: MACADDR3 Position */ 1708 #define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /*!< EMAC_T::CAM14M: MACADDR3 Mask */ 1709 1710 #define EMAC_CAM14M_MACADDR4_Pos (16) /*!< EMAC_T::CAM14M: MACADDR4 Position */ 1711 #define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /*!< EMAC_T::CAM14M: MACADDR4 Mask */ 1712 1713 #define EMAC_CAM14M_MACADDR5_Pos (24) /*!< EMAC_T::CAM14M: MACADDR5 Position */ 1714 #define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /*!< EMAC_T::CAM14M: MACADDR5 Mask */ 1715 1716 #define EMAC_CAM14L_MACADDR0_Pos (16) /*!< EMAC_T::CAM14L: MACADDR0 Position */ 1717 #define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /*!< EMAC_T::CAM14L: MACADDR0 Mask */ 1718 1719 #define EMAC_CAM14L_MACADDR1_Pos (24) /*!< EMAC_T::CAM14L: MACADDR1 Position */ 1720 #define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /*!< EMAC_T::CAM14L: MACADDR1 Mask */ 1721 1722 #define EMAC_CAM15MSB_OPCODE_Pos (0) /*!< EMAC_T::CAM15MSB: OPCODE Position */ 1723 #define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /*!< EMAC_T::CAM15MSB: OPCODE Mask */ 1724 1725 #define EMAC_CAM15MSB_LENGTH_Pos (16) /*!< EMAC_T::CAM15MSB: LENGTH Position */ 1726 #define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /*!< EMAC_T::CAM15MSB: LENGTH Mask */ 1727 1728 #define EMAC_CAM15LSB_OPERAND_Pos (24) /*!< EMAC_T::CAM15LSB: OPERAND Position */ 1729 #define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /*!< EMAC_T::CAM15LSB: OPERAND Mask */ 1730 1731 #define EMAC_TXDSA_TXDSA_Pos (0) /*!< EMAC_T::TXDSA: TXDSA Position */ 1732 #define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /*!< EMAC_T::TXDSA: TXDSA Mask */ 1733 1734 #define EMAC_RXDSA_RXDSA_Pos (0) /*!< EMAC_T::RXDSA: RXDSA Position */ 1735 #define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /*!< EMAC_T::RXDSA: RXDSA Mask */ 1736 1737 #define EMAC_CTL_RXON_Pos (0) /*!< EMAC_T::CTL: RXON Position */ 1738 #define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /*!< EMAC_T::CTL: RXON Mask */ 1739 1740 #define EMAC_CTL_ALP_Pos (1) /*!< EMAC_T::CTL: ALP Position */ 1741 #define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /*!< EMAC_T::CTL: ALP Mask */ 1742 1743 #define EMAC_CTL_ARP_Pos (2) /*!< EMAC_T::CTL: ARP Position */ 1744 #define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /*!< EMAC_T::CTL: ARP Mask */ 1745 1746 #define EMAC_CTL_ACP_Pos (3) /*!< EMAC_T::CTL: ACP Position */ 1747 #define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /*!< EMAC_T::CTL: ACP Mask */ 1748 1749 #define EMAC_CTL_AEP_Pos (4) /*!< EMAC_T::CTL: AEP Position */ 1750 #define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /*!< EMAC_T::CTL: AEP Mask */ 1751 1752 #define EMAC_CTL_STRIPCRC_Pos (5) /*!< EMAC_T::CTL: STRIPCRC Position */ 1753 #define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /*!< EMAC_T::CTL: STRIPCRC Mask */ 1754 1755 #define EMAC_CTL_WOLEN_Pos (6) /*!< EMAC_T::CTL: WOLEN Position */ 1756 #define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /*!< EMAC_T::CTL: WOLEN Mask */ 1757 1758 #define EMAC_CTL_TXON_Pos (8) /*!< EMAC_T::CTL: TXON Position */ 1759 #define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /*!< EMAC_T::CTL: TXON Mask */ 1760 1761 #define EMAC_CTL_NODEF_Pos (9) /*!< EMAC_T::CTL: NODEF Position */ 1762 #define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /*!< EMAC_T::CTL: NODEF Mask */ 1763 1764 #define EMAC_CTL_SDPZ_Pos (16) /*!< EMAC_T::CTL: SDPZ Position */ 1765 #define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /*!< EMAC_T::CTL: SDPZ Mask */ 1766 1767 #define EMAC_CTL_SQECHKEN_Pos (17) /*!< EMAC_T::CTL: SQECHKEN Position */ 1768 #define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /*!< EMAC_T::CTL: SQECHKEN Mask */ 1769 1770 #define EMAC_CTL_FUDUP_Pos (18) /*!< EMAC_T::CTL: FUDUP Position */ 1771 #define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /*!< EMAC_T::CTL: FUDUP Mask */ 1772 1773 #define EMAC_CTL_RMIIRXCTL_Pos (19) /*!< EMAC_T::CTL: RMIIRXCTL Position */ 1774 #define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /*!< EMAC_T::CTL: RMIIRXCTL Mask */ 1775 1776 #define EMAC_CTL_OPMODE_Pos (20) /*!< EMAC_T::CTL: OPMODE Position */ 1777 #define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /*!< EMAC_T::CTL: OPMODE Mask */ 1778 1779 #define EMAC_CTL_RMIIEN_Pos (22) /*!< EMAC_T::CTL: RMIIEN Position */ 1780 #define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /*!< EMAC_T::CTL: RMIIEN Mask */ 1781 1782 #define EMAC_CTL_RST_Pos (24) /*!< EMAC_T::CTL: RST Position */ 1783 #define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /*!< EMAC_T::CTL: RST Mask */ 1784 1785 #define EMAC_MIIMDAT_DATA_Pos (0) /*!< EMAC_T::MIIMDAT: DATA Position */ 1786 #define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /*!< EMAC_T::MIIMDAT: DATA Mask */ 1787 1788 #define EMAC_MIIMCTL_PHYREG_Pos (0) /*!< EMAC_T::MIIMCTL: PHYREG Position */ 1789 #define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /*!< EMAC_T::MIIMCTL: PHYREG Mask */ 1790 1791 #define EMAC_MIIMCTL_PHYADDR_Pos (8) /*!< EMAC_T::MIIMCTL: PHYADDR Position */ 1792 #define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /*!< EMAC_T::MIIMCTL: PHYADDR Mask */ 1793 1794 #define EMAC_MIIMCTL_WRITE_Pos (16) /*!< EMAC_T::MIIMCTL: WRITE Position */ 1795 #define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /*!< EMAC_T::MIIMCTL: WRITE Mask */ 1796 1797 #define EMAC_MIIMCTL_BUSY_Pos (17) /*!< EMAC_T::MIIMCTL: BUSY Position */ 1798 #define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /*!< EMAC_T::MIIMCTL: BUSY Mask */ 1799 1800 #define EMAC_MIIMCTL_PREAMSP_Pos (18) /*!< EMAC_T::MIIMCTL: PREAMSP Position */ 1801 #define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /*!< EMAC_T::MIIMCTL: PREAMSP Mask */ 1802 1803 #define EMAC_MIIMCTL_MDCON_Pos (19) /*!< EMAC_T::MIIMCTL: MDCON Position */ 1804 #define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /*!< EMAC_T::MIIMCTL: MDCON Mask */ 1805 1806 #define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /*!< EMAC_T::FIFOCTL: RXFIFOTH Position */ 1807 #define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: RXFIFOTH Mask */ 1808 1809 #define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /*!< EMAC_T::FIFOCTL: TXFIFOTH Position */ 1810 #define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: TXFIFOTH Mask */ 1811 1812 #define EMAC_FIFOCTL_BURSTLEN_Pos (20) /*!< EMAC_T::FIFOCTL: BURSTLEN Position */ 1813 #define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /*!< EMAC_T::FIFOCTL: BURSTLEN Mask */ 1814 1815 #define EMAC_TXST_TXST_Pos (0) /*!< EMAC_T::TXST: TXST Position */ 1816 #define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /*!< EMAC_T::TXST: TXST Mask */ 1817 1818 #define EMAC_RXST_RXST_Pos (0) /*!< EMAC_T::RXST: RXST Position */ 1819 #define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /*!< EMAC_T::RXST: RXST Mask */ 1820 1821 #define EMAC_MRFL_MRFL_Pos (0) /*!< EMAC_T::MRFL: MRFL Position */ 1822 #define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /*!< EMAC_T::MRFL: MRFL Mask */ 1823 1824 #define EMAC_INTEN_RXIEN_Pos (0) /*!< EMAC_T::INTEN: RXIEN Position */ 1825 #define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /*!< EMAC_T::INTEN: RXIEN Mask */ 1826 1827 #define EMAC_INTEN_CRCEIEN_Pos (1) /*!< EMAC_T::INTEN: CRCEIEN Position */ 1828 #define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /*!< EMAC_T::INTEN: CRCEIEN Mask */ 1829 1830 #define EMAC_INTEN_RXOVIEN_Pos (2) /*!< EMAC_T::INTEN: RXOVIEN Position */ 1831 #define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /*!< EMAC_T::INTEN: RXOVIEN Mask */ 1832 1833 #define EMAC_INTEN_LPIEN_Pos (3) /*!< EMAC_T::INTEN: LPIEN Position */ 1834 #define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /*!< EMAC_T::INTEN: LPIEN Mask */ 1835 1836 #define EMAC_INTEN_RXGDIEN_Pos (4) /*!< EMAC_T::INTEN: RXGDIEN Position */ 1837 #define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /*!< EMAC_T::INTEN: RXGDIEN Mask */ 1838 1839 #define EMAC_INTEN_ALIEIEN_Pos (5) /*!< EMAC_T::INTEN: ALIEIEN Position */ 1840 #define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /*!< EMAC_T::INTEN: ALIEIEN Mask */ 1841 1842 #define EMAC_INTEN_RPIEN_Pos (6) /*!< EMAC_T::INTEN: RPIEN Position */ 1843 #define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /*!< EMAC_T::INTEN: RPIEN Mask */ 1844 1845 #define EMAC_INTEN_MPCOVIEN_Pos (7) /*!< EMAC_T::INTEN: MPCOVIEN Position */ 1846 #define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /*!< EMAC_T::INTEN: MPCOVIEN Mask */ 1847 1848 #define EMAC_INTEN_MFLEIEN_Pos (8) /*!< EMAC_T::INTEN: MFLEIEN Position */ 1849 #define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /*!< EMAC_T::INTEN: MFLEIEN Mask */ 1850 1851 #define EMAC_INTEN_DENIEN_Pos (9) /*!< EMAC_T::INTEN: DENIEN Position */ 1852 #define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /*!< EMAC_T::INTEN: DENIEN Mask */ 1853 1854 #define EMAC_INTEN_RDUIEN_Pos (10) /*!< EMAC_T::INTEN: RDUIEN Position */ 1855 #define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /*!< EMAC_T::INTEN: RDUIEN Mask */ 1856 1857 #define EMAC_INTEN_RXBEIEN_Pos (11) /*!< EMAC_T::INTEN: RXBEIEN Position */ 1858 #define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /*!< EMAC_T::INTEN: RXBEIEN Mask */ 1859 1860 #define EMAC_INTEN_CFRIEN_Pos (14) /*!< EMAC_T::INTEN: CFRIEN Position */ 1861 #define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /*!< EMAC_T::INTEN: CFRIEN Mask */ 1862 1863 #define EMAC_INTEN_WOLIEN_Pos (15) /*!< EMAC_T::INTEN: WOLIEN Position */ 1864 #define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /*!< EMAC_T::INTEN: WOLIEN Mask */ 1865 1866 #define EMAC_INTEN_TXIEN_Pos (16) /*!< EMAC_T::INTEN: TXIEN Position */ 1867 #define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /*!< EMAC_T::INTEN: TXIEN Mask */ 1868 1869 #define EMAC_INTEN_TXUDIEN_Pos (17) /*!< EMAC_T::INTEN: TXUDIEN Position */ 1870 #define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /*!< EMAC_T::INTEN: TXUDIEN Mask */ 1871 1872 #define EMAC_INTEN_TXCPIEN_Pos (18) /*!< EMAC_T::INTEN: TXCPIEN Position */ 1873 #define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /*!< EMAC_T::INTEN: TXCPIEN Mask */ 1874 1875 #define EMAC_INTEN_EXDEFIEN_Pos (19) /*!< EMAC_T::INTEN: EXDEFIEN Position */ 1876 #define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /*!< EMAC_T::INTEN: EXDEFIEN Mask */ 1877 1878 #define EMAC_INTEN_NCSIEN_Pos (20) /*!< EMAC_T::INTEN: NCSIEN Position */ 1879 #define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /*!< EMAC_T::INTEN: NCSIEN Mask */ 1880 1881 #define EMAC_INTEN_TXABTIEN_Pos (21) /*!< EMAC_T::INTEN: TXABTIEN Position */ 1882 #define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /*!< EMAC_T::INTEN: TXABTIEN Mask */ 1883 1884 #define EMAC_INTEN_LCIEN_Pos (22) /*!< EMAC_T::INTEN: LCIEN Position */ 1885 #define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /*!< EMAC_T::INTEN: LCIEN Mask */ 1886 1887 #define EMAC_INTEN_TDUIEN_Pos (23) /*!< EMAC_T::INTEN: TDUIEN Position */ 1888 #define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /*!< EMAC_T::INTEN: TDUIEN Mask */ 1889 1890 #define EMAC_INTEN_TXBEIEN_Pos (24) /*!< EMAC_T::INTEN: TXBEIEN Position */ 1891 #define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /*!< EMAC_T::INTEN: TXBEIEN Mask */ 1892 1893 #define EMAC_INTEN_TSALMIEN_Pos (28) /*!< EMAC_T::INTEN: TSALMIEN Position */ 1894 #define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /*!< EMAC_T::INTEN: TSALMIEN Mask */ 1895 1896 #define EMAC_INTSTS_RXIF_Pos (0) /*!< EMAC_T::INTSTS: RXIF Position */ 1897 #define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /*!< EMAC_T::INTSTS: RXIF Mask */ 1898 1899 #define EMAC_INTSTS_CRCEIF_Pos (1) /*!< EMAC_T::INTSTS: CRCEIF Position */ 1900 #define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /*!< EMAC_T::INTSTS: CRCEIF Mask */ 1901 1902 #define EMAC_INTSTS_RXOVIF_Pos (2) /*!< EMAC_T::INTSTS: RXOVIF Position */ 1903 #define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /*!< EMAC_T::INTSTS: RXOVIF Mask */ 1904 1905 #define EMAC_INTSTS_LPIF_Pos (3) /*!< EMAC_T::INTSTS: LPIF Position */ 1906 #define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /*!< EMAC_T::INTSTS: LPIF Mask */ 1907 1908 #define EMAC_INTSTS_RXGDIF_Pos (4) /*!< EMAC_T::INTSTS: RXGDIF Position */ 1909 #define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /*!< EMAC_T::INTSTS: RXGDIF Mask */ 1910 1911 #define EMAC_INTSTS_ALIEIF_Pos (5) /*!< EMAC_T::INTSTS: ALIEIF Position */ 1912 #define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /*!< EMAC_T::INTSTS: ALIEIF Mask */ 1913 1914 #define EMAC_INTSTS_RPIF_Pos (6) /*!< EMAC_T::INTSTS: RPIF Position */ 1915 #define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /*!< EMAC_T::INTSTS: RPIF Mask */ 1916 1917 #define EMAC_INTSTS_MPCOVIF_Pos (7) /*!< EMAC_T::INTSTS: MPCOVIF Position */ 1918 #define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /*!< EMAC_T::INTSTS: MPCOVIF Mask */ 1919 1920 #define EMAC_INTSTS_MFLEIF_Pos (8) /*!< EMAC_T::INTSTS: MFLEIF Position */ 1921 #define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /*!< EMAC_T::INTSTS: MFLEIF Mask */ 1922 1923 #define EMAC_INTSTS_DENIF_Pos (9) /*!< EMAC_T::INTSTS: DENIF Position */ 1924 #define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /*!< EMAC_T::INTSTS: DENIF Mask */ 1925 1926 #define EMAC_INTSTS_RDUIF_Pos (10) /*!< EMAC_T::INTSTS: RDUIF Position */ 1927 #define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /*!< EMAC_T::INTSTS: RDUIF Mask */ 1928 1929 #define EMAC_INTSTS_RXBEIF_Pos (11) /*!< EMAC_T::INTSTS: RXBEIF Position */ 1930 #define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /*!< EMAC_T::INTSTS: RXBEIF Mask */ 1931 1932 #define EMAC_INTSTS_CFRIF_Pos (14) /*!< EMAC_T::INTSTS: CFRIF Position */ 1933 #define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /*!< EMAC_T::INTSTS: CFRIF Mask */ 1934 1935 #define EMAC_INTSTS_WOLIF_Pos (15) /*!< EMAC_T::INTSTS: WOLIF Position */ 1936 #define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /*!< EMAC_T::INTSTS: WOLIF Mask */ 1937 1938 #define EMAC_INTSTS_TXIF_Pos (16) /*!< EMAC_T::INTSTS: TXIF Position */ 1939 #define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /*!< EMAC_T::INTSTS: TXIF Mask */ 1940 1941 #define EMAC_INTSTS_TXUDIF_Pos (17) /*!< EMAC_T::INTSTS: TXUDIF Position */ 1942 #define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /*!< EMAC_T::INTSTS: TXUDIF Mask */ 1943 1944 #define EMAC_INTSTS_TXCPIF_Pos (18) /*!< EMAC_T::INTSTS: TXCPIF Position */ 1945 #define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /*!< EMAC_T::INTSTS: TXCPIF Mask */ 1946 1947 #define EMAC_INTSTS_EXDEFIF_Pos (19) /*!< EMAC_T::INTSTS: EXDEFIF Position */ 1948 #define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /*!< EMAC_T::INTSTS: EXDEFIF Mask */ 1949 1950 #define EMAC_INTSTS_NCSIF_Pos (20) /*!< EMAC_T::INTSTS: NCSIF Position */ 1951 #define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /*!< EMAC_T::INTSTS: NCSIF Mask */ 1952 1953 #define EMAC_INTSTS_TXABTIF_Pos (21) /*!< EMAC_T::INTSTS: TXABTIF Position */ 1954 #define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /*!< EMAC_T::INTSTS: TXABTIF Mask */ 1955 1956 #define EMAC_INTSTS_LCIF_Pos (22) /*!< EMAC_T::INTSTS: LCIF Position */ 1957 #define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /*!< EMAC_T::INTSTS: LCIF Mask */ 1958 1959 #define EMAC_INTSTS_TDUIF_Pos (23) /*!< EMAC_T::INTSTS: TDUIF Position */ 1960 #define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /*!< EMAC_T::INTSTS: TDUIF Mask */ 1961 1962 #define EMAC_INTSTS_TXBEIF_Pos (24) /*!< EMAC_T::INTSTS: TXBEIF Position */ 1963 #define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /*!< EMAC_T::INTSTS: TXBEIF Mask */ 1964 1965 #define EMAC_INTSTS_TSALMIF_Pos (28) /*!< EMAC_T::INTSTS: TSALMIF Position */ 1966 #define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /*!< EMAC_T::INTSTS: TSALMIF Mask */ 1967 1968 #define EMAC_GENSTS_CFR_Pos (0) /*!< EMAC_T::GENSTS: CFR Position */ 1969 #define EMAC_GENSTS_CFR_Msk (0x1ul << EMAC_GENSTS_CFR_Pos) /*!< EMAC_T::GENSTS: CFR Mask */ 1970 1971 #define EMAC_GENSTS_RXHALT_Pos (1) /*!< EMAC_T::GENSTS: RXHALT Position */ 1972 #define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /*!< EMAC_T::GENSTS: RXHALT Mask */ 1973 1974 #define EMAC_GENSTS_RXFFULL_Pos (2) /*!< EMAC_T::GENSTS: RXFFULL Position */ 1975 #define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /*!< EMAC_T::GENSTS: RXFFULL Mask */ 1976 1977 #define EMAC_GENSTS_COLCNT_Pos (4) /*!< EMAC_T::GENSTS: COLCNT Position */ 1978 #define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /*!< EMAC_T::GENSTS: COLCNT Mask */ 1979 1980 #define EMAC_GENSTS_DEF_Pos (8) /*!< EMAC_T::GENSTS: DEF Position */ 1981 #define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /*!< EMAC_T::GENSTS: DEF Mask */ 1982 1983 #define EMAC_GENSTS_TXPAUSED_Pos (9) /*!< EMAC_T::GENSTS: TXPAUSED Position */ 1984 #define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /*!< EMAC_T::GENSTS: TXPAUSED Mask */ 1985 1986 #define EMAC_GENSTS_SQE_Pos (10) /*!< EMAC_T::GENSTS: SQE Position */ 1987 #define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /*!< EMAC_T::GENSTS: SQE Mask */ 1988 1989 #define EMAC_GENSTS_TXHALT_Pos (11) /*!< EMAC_T::GENSTS: TXHALT Position */ 1990 #define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /*!< EMAC_T::GENSTS: TXHALT Mask */ 1991 1992 #define EMAC_GENSTS_RPSTS_Pos (12) /*!< EMAC_T::GENSTS: RPSTS Position */ 1993 #define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /*!< EMAC_T::GENSTS: RPSTS Mask */ 1994 1995 #define EMAC_MPCNT_MPCNT_Pos (0) /*!< EMAC_T::MPCNT: MPCNT Position */ 1996 #define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /*!< EMAC_T::MPCNT: MPCNT Mask */ 1997 1998 #define EMAC_RPCNT_RPCNT_Pos (0) /*!< EMAC_T::RPCNT: RPCNT Position */ 1999 #define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /*!< EMAC_T::RPCNT: RPCNT Mask */ 2000 2001 #define EMAC_FRSTS_RXFLT_Pos (0) /*!< EMAC_T::FRSTS: RXFLT Position */ 2002 #define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /*!< EMAC_T::FRSTS: RXFLT Mask */ 2003 2004 #define EMAC_CTXDSA_CTXDSA_Pos (0) /*!< EMAC_T::CTXDSA: CTXDSA Position */ 2005 #define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /*!< EMAC_T::CTXDSA: CTXDSA Mask */ 2006 2007 #define EMAC_CTXBSA_CTXBSA_Pos (0) /*!< EMAC_T::CTXBSA: CTXBSA Position */ 2008 #define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /*!< EMAC_T::CTXBSA: CTXBSA Mask */ 2009 2010 #define EMAC_CRXDSA_CRXDSA_Pos (0) /*!< EMAC_T::CRXDSA: CRXDSA Position */ 2011 #define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /*!< EMAC_T::CRXDSA: CRXDSA Mask */ 2012 2013 #define EMAC_CRXBSA_CRXBSA_Pos (0) /*!< EMAC_T::CRXBSA: CRXBSA Position */ 2014 #define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /*!< EMAC_T::CRXBSA: CRXBSA Mask */ 2015 2016 #define EMAC_TSCTL_TSEN_Pos (0) /*!< EMAC_T::TSCTL: TSEN Position */ 2017 #define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /*!< EMAC_T::TSCTL: TSEN Mask */ 2018 2019 #define EMAC_TSCTL_TSIEN_Pos (1) /*!< EMAC_T::TSCTL: TSIEN Position */ 2020 #define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /*!< EMAC_T::TSCTL: TSIEN Mask */ 2021 2022 #define EMAC_TSCTL_TSMODE_Pos (2) /*!< EMAC_T::TSCTL: TSMODE Position */ 2023 #define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /*!< EMAC_T::TSCTL: TSMODE Mask */ 2024 2025 #define EMAC_TSCTL_TSUPDATE_Pos (3) /*!< EMAC_T::TSCTL: TSUPDATE Position */ 2026 #define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /*!< EMAC_T::TSCTL: TSUPDATE Mask */ 2027 2028 #define EMAC_TSCTL_TSALMEN_Pos (5) /*!< EMAC_T::TSCTL: TSALMEN Position */ 2029 #define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /*!< EMAC_T::TSCTL: TSALMEN Mask */ 2030 2031 #define EMAC_TSSEC_SEC_Pos (0) /*!< EMAC_T::TSSEC: SEC Position */ 2032 #define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /*!< EMAC_T::TSSEC: SEC Mask */ 2033 2034 #define EMAC_TSSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::TSSUBSEC: SUBSEC Position */ 2035 #define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /*!< EMAC_T::TSSUBSEC: SUBSEC Mask */ 2036 2037 #define EMAC_TSINC_CNTINC_Pos (0) /*!< EMAC_T::TSINC: CNTINC Position */ 2038 #define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /*!< EMAC_T::TSINC: CNTINC Mask */ 2039 2040 #define EMAC_TSADDEND_ADDEND_Pos (0) /*!< EMAC_T::TSADDEND: ADDEND Position */ 2041 #define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /*!< EMAC_T::TSADDEND: ADDEND Mask */ 2042 2043 #define EMAC_UPDSEC_SEC_Pos (0) /*!< EMAC_T::UPDSEC: SEC Position */ 2044 #define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /*!< EMAC_T::UPDSEC: SEC Mask */ 2045 2046 #define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::UPDSUBSEC: SUBSEC Position */ 2047 #define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /*!< EMAC_T::UPDSUBSEC: SUBSEC Mask */ 2048 2049 #define EMAC_ALMSEC_SEC_Pos (0) /*!< EMAC_T::ALMSEC: SEC Position */ 2050 #define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /*!< EMAC_T::ALMSEC: SEC Mask */ 2051 2052 #define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::ALMSUBSEC: SUBSEC Position */ 2053 #define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /*!< EMAC_T::ALMSUBSEC: SUBSEC Mask */ 2054 2055 /**@}*/ /* EMAC_CONST */ 2056 /**@}*/ /* end of EMAC register group */ 2057 /**@}*/ /* end of REGISTER group */ 2058 2059 #if defined ( __CC_ARM ) 2060 #pragma no_anon_unions 2061 #endif 2062 2063 #endif /* __EMAC_REG_H__ */ 2064
