1 /**************************************************************************//** 2 * @file ebi_reg.h 3 * @version V1.00 4 * @brief EBI register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EBI_REG_H__ 10 #define __EBI_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup EBI External Bus Interface Controller(EBI) 23 Memory Mapped Structure for EBI Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var EBI_T::CTL0 32 * Offset: 0x00 External Bus Interface Bank0 Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |EN |EBI Enable Bit 37 * | | |This bit is the functional enable bit for EBI. 38 * | | |0 = EBI function Disabled. 39 * | | |1 = EBI function Enabled. 40 * |[1] |DW16 |EBI Data Width 16-bit Select 41 * | | |This bit defines if the EBI data width is 8-bit or 16-bit. 42 * | | |0 = EBI data width is 8-bit. 43 * | | |1 = EBI data width is 16-bit. 44 * |[2] |CSPOLINV |Chip Select Pin Polar Inverse 45 * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). 46 * | | |0 = Chip select pin (EBI_nCS) is active low. 47 * | | |1 = Chip select pin (EBI_nCS) is active high. 48 * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit 49 * | | |0 = Address/Data Bus Separating Mode Disabled. 50 * | | |1 = Address/Data Bus Separating Mode Enabled. 51 * |[4] |CACCESS |Continuous Data Access Mode 52 * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. 53 * | | |0 = Continuous data access mode Disabled. 54 * | | |1 = Continuous data access mode Enabled. 55 * |[10:8] |MCLKDIV |External Output Clock Divider 56 * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: 57 * | | |000 = HCLK/1. 58 * | | |001 = HCLK/2. 59 * | | |010 = HCLK/4. 60 * | | |011 = HCLK/8. 61 * | | |100 = HCLK/16. 62 * | | |101 = HCLK/32. 63 * | | |110 = HCLK/64. 64 * | | |111 = HCLK/128. 65 * |[18:16] |TALE |Extend Time of ALE 66 * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. 67 * | | |tALE = (TALE+1)*EBI_MCLK. 68 * | | |Note: This field only available in EBI_CTL0 register 69 * |[24] |WBUFEN |EBI Write Buffer Enable Bit 70 * | | |0 = EBI write buffer Disabled. 71 * | | |1 = EBI write buffer Enabled. 72 * | | |Note: This bit only available in EBI_CTL0 register 73 * @var EBI_T::TCTL0 74 * Offset: 0x04 External Bus Interface Bank0 Timing Control Register 75 * --------------------------------------------------------------------------------------------------- 76 * |Bits |Field |Descriptions 77 * | :----: | :----: | :---- | 78 * |[7:3] |TACC |EBI Data Access Time 79 * | | |TACC define data access time (tACC). 80 * | | |tACC = (TACC +1) * EBI_MCLK. 81 * |[10:8] |TAHD |EBI Data Access Hold Time 82 * | | |TAHD define data access hold time (tAHD). 83 * | | |tAHD = (TAHD +1) * EBI_MCLK. 84 * |[15:12] |W2X |Idle Cycle After Write 85 * | | |This field defines the number of W2X idle cycle. 86 * | | |W2X idle cycle = (W2X * EBI_MCLK). 87 * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. 88 * |[22] |RAHDOFF |Access Hold Time Disable Control When Read 89 * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. 90 * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. 91 * |[23] |WAHDOFF |Access Hold Time Disable Control When Write 92 * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. 93 * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. 94 * |[27:24] |R2R |Idle Cycle Between Read-to-read 95 * | | |This field defines the number of R2R idle cycle. 96 * | | |R2R idle cycle = (R2R * EBI_MCLK). 97 * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. 98 * @var EBI_T::CTL1 99 * Offset: 0x10 External Bus Interface Bank1 Control Register 100 * --------------------------------------------------------------------------------------------------- 101 * |Bits |Field |Descriptions 102 * | :----: | :----: | :---- | 103 * |[0] |EN |EBI Enable Bit 104 * | | |This bit is the functional enable bit for EBI. 105 * | | |0 = EBI function Disabled. 106 * | | |1 = EBI function Enabled. 107 * |[1] |DW16 |EBI Data Width 16-bit Select 108 * | | |This bit defines if the EBI data width is 8-bit or 16-bit. 109 * | | |0 = EBI data width is 8-bit. 110 * | | |1 = EBI data width is 16-bit. 111 * |[2] |CSPOLINV |Chip Select Pin Polar Inverse 112 * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). 113 * | | |0 = Chip select pin (EBI_nCS) is active low. 114 * | | |1 = Chip select pin (EBI_nCS) is active high. 115 * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit 116 * | | |0 = Address/Data Bus Separating Mode Disabled. 117 * | | |1 = Address/Data Bus Separating Mode Enabled. 118 * |[4] |CACCESS |Continuous Data Access Mode 119 * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. 120 * | | |0 = Continuous data access mode Disabled. 121 * | | |1 = Continuous data access mode Enabled. 122 * |[10:8] |MCLKDIV |External Output Clock Divider 123 * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: 124 * | | |000 = HCLK/1. 125 * | | |001 = HCLK/2. 126 * | | |010 = HCLK/4. 127 * | | |011 = HCLK/8. 128 * | | |100 = HCLK/16. 129 * | | |101 = HCLK/32. 130 * | | |110 = HCLK/64. 131 * | | |111 = HCLK/128. 132 * |[18:16] |TALE |Extend Time of ALE 133 * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. 134 * | | |tALE = (TALE+1)*EBI_MCLK. 135 * | | |Note: This field only available in EBI_CTL0 register 136 * |[24] |WBUFEN |EBI Write Buffer Enable Bit 137 * | | |0 = EBI write buffer Disabled. 138 * | | |1 = EBI write buffer Enabled. 139 * | | |Note: This bit only available in EBI_CTL0 register 140 * @var EBI_T::TCTL1 141 * Offset: 0x14 External Bus Interface Bank1 Timing Control Register 142 * --------------------------------------------------------------------------------------------------- 143 * |Bits |Field |Descriptions 144 * | :----: | :----: | :---- | 145 * |[7:3] |TACC |EBI Data Access Time 146 * | | |TACC define data access time (tACC). 147 * | | |tACC = (TACC +1) * EBI_MCLK. 148 * |[10:8] |TAHD |EBI Data Access Hold Time 149 * | | |TAHD define data access hold time (tAHD). 150 * | | |tAHD = (TAHD +1) * EBI_MCLK. 151 * |[15:12] |W2X |Idle Cycle After Write 152 * | | |This field defines the number of W2X idle cycle. 153 * | | |W2X idle cycle = (W2X * EBI_MCLK). 154 * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. 155 * |[22] |RAHDOFF |Access Hold Time Disable Control When Read 156 * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. 157 * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. 158 * |[23] |WAHDOFF |Access Hold Time Disable Control When Write 159 * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. 160 * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. 161 * |[27:24] |R2R |Idle Cycle Between Read-to-read 162 * | | |This field defines the number of R2R idle cycle. 163 * | | |R2R idle cycle = (R2R * EBI_MCLK). 164 * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. 165 * @var EBI_T::CTL2 166 * Offset: 0x20 External Bus Interface Bank2 Control Register 167 * --------------------------------------------------------------------------------------------------- 168 * |Bits |Field |Descriptions 169 * | :----: | :----: | :---- | 170 * |[0] |EN |EBI Enable Bit 171 * | | |This bit is the functional enable bit for EBI. 172 * | | |0 = EBI function Disabled. 173 * | | |1 = EBI function Enabled. 174 * |[1] |DW16 |EBI Data Width 16-bit Select 175 * | | |This bit defines if the EBI data width is 8-bit or 16-bit. 176 * | | |0 = EBI data width is 8-bit. 177 * | | |1 = EBI data width is 16-bit. 178 * |[2] |CSPOLINV |Chip Select Pin Polar Inverse 179 * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). 180 * | | |0 = Chip select pin (EBI_nCS) is active low. 181 * | | |1 = Chip select pin (EBI_nCS) is active high. 182 * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit 183 * | | |0 = Address/Data Bus Separating Mode Disabled. 184 * | | |1 = Address/Data Bus Separating Mode Enabled. 185 * |[4] |CACCESS |Continuous Data Access Mode 186 * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. 187 * | | |0 = Continuous data access mode Disabled. 188 * | | |1 = Continuous data access mode Enabled. 189 * |[10:8] |MCLKDIV |External Output Clock Divider 190 * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: 191 * | | |000 = HCLK/1. 192 * | | |001 = HCLK/2. 193 * | | |010 = HCLK/4. 194 * | | |011 = HCLK/8. 195 * | | |100 = HCLK/16. 196 * | | |101 = HCLK/32. 197 * | | |110 = HCLK/64. 198 * | | |111 = HCLK/128. 199 * |[18:16] |TALE |Extend Time of ALE 200 * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. 201 * | | |tALE = (TALE+1)*EBI_MCLK. 202 * | | |Note: This field only available in EBI_CTL0 register 203 * |[24] |WBUFEN |EBI Write Buffer Enable Bit 204 * | | |0 = EBI write buffer Disabled. 205 * | | |1 = EBI write buffer Enabled. 206 * | | |Note: This bit only available in EBI_CTL0 register 207 * @var EBI_T::TCTL2 208 * Offset: 0x24 External Bus Interface Bank2 Timing Control Register 209 * --------------------------------------------------------------------------------------------------- 210 * |Bits |Field |Descriptions 211 * | :----: | :----: | :---- | 212 * |[7:3] |TACC |EBI Data Access Time 213 * | | |TACC define data access time (tACC). 214 * | | |tACC = (TACC +1) * EBI_MCLK. 215 * |[10:8] |TAHD |EBI Data Access Hold Time 216 * | | |TAHD define data access hold time (tAHD). 217 * | | |tAHD = (TAHD +1) * EBI_MCLK. 218 * |[15:12] |W2X |Idle Cycle After Write 219 * | | |This field defines the number of W2X idle cycle. 220 * | | |W2X idle cycle = (W2X * EBI_MCLK). 221 * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. 222 * |[22] |RAHDOFF |Access Hold Time Disable Control When Read 223 * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. 224 * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. 225 * |[23] |WAHDOFF |Access Hold Time Disable Control When Write 226 * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. 227 * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. 228 * |[27:24] |R2R |Idle Cycle Between Read-to-read 229 * | | |This field defines the number of R2R idle cycle. 230 * | | |R2R idle cycle = (R2R * EBI_MCLK). 231 * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. 232 */ 233 __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ 234 __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ 235 /// @cond HIDDEN_SYMBOLS 236 __I uint32_t RESERVE0[2]; 237 /// @endcond //HIDDEN_SYMBOLS 238 __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ 239 __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ 240 /// @cond HIDDEN_SYMBOLS 241 __I uint32_t RESERVE1[2]; 242 /// @endcond //HIDDEN_SYMBOLS 243 __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ 244 __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ 245 246 } EBI_T; 247 248 /** 249 @addtogroup EBI_CONST EBI Bit Field Definition 250 Constant Definitions for EBI Controller 251 @{ */ 252 253 #define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */ 254 #define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */ 255 256 #define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */ 257 #define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */ 258 259 #define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */ 260 #define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */ 261 262 #define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */ 263 #define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */ 264 265 #define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */ 266 #define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */ 267 268 #define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */ 269 #define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */ 270 271 #define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */ 272 #define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */ 273 274 #define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */ 275 #define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */ 276 277 #define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */ 278 #define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */ 279 280 #define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */ 281 #define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */ 282 283 #define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */ 284 #define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */ 285 286 #define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */ 287 #define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */ 288 289 #define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */ 290 #define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */ 291 292 #define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */ 293 #define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */ 294 295 #define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */ 296 #define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */ 297 298 #define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */ 299 #define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */ 300 301 #define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */ 302 #define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */ 303 304 #define EBI_CTL0_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */ 305 #define EBI_CTL0_ADSEPEN_Msk (0x1ul << EBI_CTL0_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */ 306 307 #define EBI_CTL0_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */ 308 #define EBI_CTL0_CACCESS_Msk (0x1ul << EBI_CTL0_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */ 309 310 #define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */ 311 #define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */ 312 313 #define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */ 314 #define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */ 315 316 #define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */ 317 #define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */ 318 319 #define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */ 320 #define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */ 321 322 #define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */ 323 #define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */ 324 325 #define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */ 326 #define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */ 327 328 #define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */ 329 #define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */ 330 331 #define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */ 332 #define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */ 333 334 #define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */ 335 #define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */ 336 337 #define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */ 338 #define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */ 339 340 #define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */ 341 #define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */ 342 343 #define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */ 344 #define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */ 345 346 #define EBI_CTL1_ADSEPEN_Pos (3) /*!< EBI_T::CTL1: ADSEPEN Position */ 347 #define EBI_CTL1_ADSEPEN_Msk (0x1ul << EBI_CTL1_ADSEPEN_Pos) /*!< EBI_T::CTL1: ADSEPEN Mask */ 348 349 #define EBI_CTL1_CACCESS_Pos (4) /*!< EBI_T::CTL1: CACCESS Position */ 350 #define EBI_CTL1_CACCESS_Msk (0x1ul << EBI_CTL1_CACCESS_Pos) /*!< EBI_T::CTL1: CACCESS Mask */ 351 352 #define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */ 353 #define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */ 354 355 #define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */ 356 #define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */ 357 358 #define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */ 359 #define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */ 360 361 #define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */ 362 #define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */ 363 364 #define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */ 365 #define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */ 366 367 #define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */ 368 #define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */ 369 370 #define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */ 371 #define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */ 372 373 #define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */ 374 #define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */ 375 376 #define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */ 377 #define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */ 378 379 #define EBI_CTL2_EN_Pos (0) /*!< EBI_T::CTL2: EN Position */ 380 #define EBI_CTL2_EN_Msk (0x1ul << EBI_CTL2_EN_Pos) /*!< EBI_T::CTL2: EN Mask */ 381 382 #define EBI_CTL2_DW16_Pos (1) /*!< EBI_T::CTL2: DW16 Position */ 383 #define EBI_CTL2_DW16_Msk (0x1ul << EBI_CTL2_DW16_Pos) /*!< EBI_T::CTL2: DW16 Mask */ 384 385 #define EBI_CTL2_CSPOLINV_Pos (2) /*!< EBI_T::CTL2: CSPOLINV Position */ 386 #define EBI_CTL2_CSPOLINV_Msk (0x1ul << EBI_CTL2_CSPOLINV_Pos) /*!< EBI_T::CTL2: CSPOLINV Mask */ 387 388 #define EBI_CTL2_ADSEPEN_Pos (3) /*!< EBI_T::CTL2: ADSEPEN Position */ 389 #define EBI_CTL2_ADSEPEN_Msk (0x1ul << EBI_CTL2_ADSEPEN_Pos) /*!< EBI_T::CTL2: ADSEPEN Mask */ 390 391 #define EBI_CTL2_CACCESS_Pos (4) /*!< EBI_T::CTL2: CACCESS Position */ 392 #define EBI_CTL2_CACCESS_Msk (0x1ul << EBI_CTL2_CACCESS_Pos) /*!< EBI_T::CTL2: CACCESS Mask */ 393 394 #define EBI_CTL2_MCLKDIV_Pos (8) /*!< EBI_T::CTL2: MCLKDIV Position */ 395 #define EBI_CTL2_MCLKDIV_Msk (0x7ul << EBI_CTL2_MCLKDIV_Pos) /*!< EBI_T::CTL2: MCLKDIV Mask */ 396 397 #define EBI_CTL2_TALE_Pos (16) /*!< EBI_T::CTL2: TALE Position */ 398 #define EBI_CTL2_TALE_Msk (0x7ul << EBI_CTL2_TALE_Pos) /*!< EBI_T::CTL2: TALE Mask */ 399 400 #define EBI_CTL2_WBUFEN_Pos (24) /*!< EBI_T::CTL2: WBUFEN Position */ 401 #define EBI_CTL2_WBUFEN_Msk (0x1ul << EBI_CTL2_WBUFEN_Pos) /*!< EBI_T::CTL2: WBUFEN Mask */ 402 403 #define EBI_TCTL2_TACC_Pos (3) /*!< EBI_T::TCTL2: TACC Position */ 404 #define EBI_TCTL2_TACC_Msk (0x1ful << EBI_TCTL2_TACC_Pos) /*!< EBI_T::TCTL2: TACC Mask */ 405 406 #define EBI_TCTL2_TAHD_Pos (8) /*!< EBI_T::TCTL2: TAHD Position */ 407 #define EBI_TCTL2_TAHD_Msk (0x7ul << EBI_TCTL2_TAHD_Pos) /*!< EBI_T::TCTL2: TAHD Mask */ 408 409 #define EBI_TCTL2_W2X_Pos (12) /*!< EBI_T::TCTL2: W2X Position */ 410 #define EBI_TCTL2_W2X_Msk (0xful << EBI_TCTL2_W2X_Pos) /*!< EBI_T::TCTL2: W2X Mask */ 411 412 #define EBI_TCTL2_RAHDOFF_Pos (22) /*!< EBI_T::TCTL2: RAHDOFF Position */ 413 #define EBI_TCTL2_RAHDOFF_Msk (0x1ul << EBI_TCTL2_RAHDOFF_Pos) /*!< EBI_T::TCTL2: RAHDOFF Mask */ 414 415 #define EBI_TCTL2_WAHDOFF_Pos (23) /*!< EBI_T::TCTL2: WAHDOFF Position */ 416 #define EBI_TCTL2_WAHDOFF_Msk (0x1ul << EBI_TCTL2_WAHDOFF_Pos) /*!< EBI_T::TCTL2: WAHDOFF Mask */ 417 418 #define EBI_TCTL2_R2R_Pos (24) /*!< EBI_T::TCTL2: R2R Position */ 419 #define EBI_TCTL2_R2R_Msk (0xful << EBI_TCTL2_R2R_Pos) /*!< EBI_T::TCTL2: R2R Mask */ 420 421 /**@}*/ /* EBI_CONST */ 422 /**@}*/ /* end of EBI register group */ 423 /**@}*/ /* end of REGISTER group */ 424 425 #if defined ( __CC_ARM ) 426 #pragma no_anon_unions 427 #endif 428 429 #endif /* __EBI_REG_H__ */ 430
