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Searched refs:CTL (Results 1 – 25 of 61) sorted by relevance

123

/hal_nuvoton-3.4.0/m48x/StdDriver/inc/
Dacmp.h89 #define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Ms…
99 #define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_…
114 #define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)…
123 #define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV)
133 #define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk)
147 #define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(…
158 #define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)
168 #define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)
178 #define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)
188 #define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)
[all …]
Dqei.h65 #define QEI_DISABLE_CNT_CMP(qei) ((qei)->CTL &= (~QEI_CTL_CMPEN_Msk))
74 #define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk)
83 #define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk))
92 #define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk)
101 #define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk))
110 #define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk)
123 #define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))
136 #define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType))
149 #define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))
162 #define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType))
[all …]
Dwdt.h71 #define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)…
83 #define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Ms…
95 #define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk…
108 #define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL)
121 #define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL)
134 #define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL)
167 WDT->CTL = 0UL; in WDT_Close()
182 WDT->CTL |= WDT_CTL_INTEN_Msk; in WDT_EnableInt()
198 WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); in WDT_DisableInt()
Dqspi.h199 #define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk)
208 #define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk)
219 #define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPIT…
228 #define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk)
237 #define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk)
247 #define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) |…
266 #define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk)
275 #define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk)
283 #define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
291 #define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QS…
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Ddac.h77 #define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
86 #define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
96 #define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
105 #define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
115 #define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
125 #define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
134 #define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
143 #define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
152 #define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
161 #define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
[all …]
Dsc.h185 #define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1…
199 while((sc)->CTL & SC_CTL_SYNC_Msk) in SC_SetTxRetry()
204 (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk); in SC_SetTxRetry()
208 while((sc)->CTL & SC_CTL_SYNC_Msk) in SC_SetTxRetry()
212 (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk; in SC_SetTxRetry()
224 while((sc)->CTL & SC_CTL_SYNC_Msk) in SC_SetRxRetry()
229 (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk); in SC_SetRxRetry()
233 while((sc)->CTL & SC_CTL_SYNC_Msk) in SC_SetRxRetry()
237 (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk; in SC_SetRxRetry()
Dtimer.h93 #define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_…
106 #define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0)
121 #define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLP…
136 #define TIMER_SET_OPMODE(timer, u32OpMode) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_OPMODE_Msk)…
174 timer->CTL |= TIMER_CTL_CNTEN_Msk; in TIMER_Start()
188 timer->CTL &= ~TIMER_CTL_CNTEN_Msk; in TIMER_Stop()
204 timer->CTL |= TIMER_CTL_WKEN_Msk; in TIMER_EnableWakeup()
218 timer->CTL &= ~TIMER_CTL_WKEN_Msk; in TIMER_DisableWakeup()
316 timer->CTL |= TIMER_CTL_INTEN_Msk; in TIMER_EnableInt()
330 timer->CTL &= ~TIMER_CTL_INTEN_Msk; in TIMER_DisableInt()
Dopa.h53 #define OPA_POWER_ON(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum))))
63 #define OPA_POWER_DOWN(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum))))
73 #define OPA_ENABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum…
83 #define OPA_DISABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaN…
93 #define OPA_ENABLE_INT(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum))))
103 #define OPA_DISABLE_INT(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum))))
Demac.h57 #define EMAC_ENABLE_TX() (EMAC->CTL |= EMAC_CTL_TXON_Msk)
66 #define EMAC_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0)
74 #define EMAC_DISABLE_TX() (EMAC->CTL &= ~EMAC_CTL_TXON_Msk)
83 #define EMAC_DISABLE_RX() (EMAC->CTL &= ~EMAC_CTL_RXON_Msk)
91 #define EMAC_ENABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL |= EMAC_CTL_WOLEN_Msk)
99 #define EMAC_DISABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk)
Dotg.h61 #define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
70 #define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
116 #define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
125 #define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
Dhsotg.h61 #define HSOTG_ENABLE() (HSOTG->CTL |= HSOTG_CTL_OTGEN_Msk)
70 #define HSOTG_DISABLE() (HSOTG->CTL &= ~HSOTG_CTL_OTGEN_Msk)
116 #define HSOTG_ENABLE_WAKEUP() (HSOTG->CTL |= HSOTG_CTL_WKEN_Msk)
125 #define HSOTG_DISABLE_WAKEUP() (HSOTG->CTL &= ~HSOTG_CTL_WKEN_Msk)
Dspi.h248 #define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
257 #define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
268 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk…
277 #define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
286 #define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
296 #define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u…
315 #define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
324 #define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
Deadc.h103 #define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk)
114 #define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
123 #define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
199 #define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
210 #define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
246 #define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Form…
/hal_nuvoton-3.4.0/m48x/StdDriver/src/
Dtrng.c38 TRNG->CTL |= TRNG_CTL_TRNGEN_Msk; in TRNG_Open()
43 while ((TRNG->CTL & TRNG_CTL_READY_Msk) == 0); in TRNG_Open()
60 u32Reg = TRNG->CTL; in TRNG_GenWord()
64 TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; in TRNG_GenWord()
69 if (TRNG->CTL & TRNG_CTL_DVIF_Msk) in TRNG_GenWord()
95 u32Reg = TRNG->CTL; in TRNG_GenBignum()
99 TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; in TRNG_GenBignum()
104 if (TRNG->CTL & TRNG_CTL_DVIF_Msk) in TRNG_GenBignum()
130 u32Reg = TRNG->CTL; in TRNG_GenBignumHex()
134 TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; in TRNG_GenBignumHex()
[all …]
Dccap.c61 CCAP->CTL = (CCAP->CTL & ~(0x00000040UL)) | u32OutFormet; in CCAP_Open()
101 CCAP->CTL |= CCAP_CTL_UPDATE_Msk; in CCAP_SetPacketBuf()
111 CCAP->CTL &= ~CCAP_CTL_CCAPEN; in CCAP_Close()
167 CCAP->CTL = (CCAP->CTL & ~CCAP_CTL_MY8_MY4) | CCAP_CTL_MONO_Msk |u32Interface; in CCAP_EnableMono()
178 CCAP->CTL |= CCAP_CTL_MONO_Msk; in CCAP_DisableMono()
191 CCAP->CTL |= CCAP_CTL_Luma_Y_One_Msk; in CCAP_EnableLumaYOne()
203 CCAP->CTL &= ~CCAP_CTL_Luma_Y_One_Msk; in CCAP_DisableLumaYOne()
213 CCAP->CTL |= CCAP_CTL_CCAPEN; in CCAP_Start()
229 CCAP->CTL &= ~CCAP_CTL_CCAPEN; in CCAP_Stop()
232 CCAP->CTL |= CCAP_CTL_SHUTTER_Msk; in CCAP_Stop()
Dsdh.c55 sdh->CTL |= SDH_CTL_CLK8OEN_Msk; in SDH_CheckRB()
56 while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) in SDH_CheckRB()
82 buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)|(SDH_CTL_COEN_Msk); in SDH_SDCommand()
83 sdh->CTL = buf; in SDH_SDCommand()
85 while ((sdh->CTL & SDH_CTL_COEN_Msk) == SDH_CTL_COEN_Msk) in SDH_SDCommand()
111 …buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk); in SDH_SDCmdAndRsp()
112 sdh->CTL = buf; in SDH_SDCmdAndRsp()
116 while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) in SDH_SDCmdAndRsp()
120 sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */ in SDH_SDCmdAndRsp()
131 while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) in SDH_SDCmdAndRsp()
[all …]
Dpdma.c46 pdma->DSCT[i].CTL = 0UL; in PDMA_Open()
85 pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); in PDMA_SetTransferCnt()
86 pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos)); in PDMA_SetTransferCnt()
104 pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; in PDMA_SetStride()
124 pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; in PDMA_SetRepeat()
151 pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); in PDMA_SetTransferAddr()
152 pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); in PDMA_SetTransferAddr()
294 … pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; in PDMA_SetTransferMode()
299 pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; in PDMA_SetTransferMode()
327 pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); in PDMA_SetBurstType()
[all …]
Dsc.c41 uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos); in SC_IsCardInserted()
94 while(sc->CTL & SC_CTL_SYNC_Msk) in SC_Close()
98 sc->CTL = 0UL; in SC_Close()
140 while(sc->CTL & SC_CTL_SYNC_Msk) in SC_Open()
144 sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg; in SC_Open()
172 while(sc->CTL & SC_CTL_SYNC_Msk) in SC_ResetReader()
176 sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | in SC_ResetReader()
182 while(sc->CTL & SC_CTL_SYNC_Msk) in SC_ResetReader()
187 sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk; in SC_ResetReader()
227 sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos); in SC_SetBlockGuardTime()
[all …]
Dqei.c33 qei->CTL = (uint32_t)0; in QEI_Close()
107 …qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk |… in QEI_Open()
122 qei->CTL |= QEI_CTL_QEIEN_Msk; in QEI_Start()
134 qei->CTL &= (~QEI_CTL_QEIEN_Msk); in QEI_Stop()
Dtimer.c59 timer->CTL = u32Mode | u32Prescale; in TIMER_Open()
76 timer->CTL = 0UL; in TIMER_Close()
99 timer->CTL = 0UL; in TIMER_Delay()
140 timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; in TIMER_Delay()
149 while(timer->CTL & TIMER_CTL_ACTSTS_Msk) in TIMER_Delay()
211 timer->CTL |= TIMER_CTL_EXTCNTEN_Msk; in TIMER_EnableEventCounter()
225 timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk; in TIMER_DisableEventCounter()
305 timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk; in TIMER_EnableFreqCounter()
316 timer->CTL &= ~TIMER_CTL_INTRGEN_Msk; in TIMER_DisableFreqCounter()
Demac.c214 EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; in EMAC_PhyInit()
215 EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; in EMAC_PhyInit()
248 EMAC->CTL |= EMAC_CTL_OPMODE_Msk; in EMAC_PhyInit()
249 EMAC->CTL |= EMAC_CTL_FUDUP_Msk; in EMAC_PhyInit()
253 EMAC->CTL |= EMAC_CTL_OPMODE_Msk; in EMAC_PhyInit()
254 EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; in EMAC_PhyInit()
258 EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; in EMAC_PhyInit()
259 EMAC->CTL |= EMAC_CTL_FUDUP_Msk; in EMAC_PhyInit()
263 EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk; in EMAC_PhyInit()
264 EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk; in EMAC_PhyInit()
[all …]
Dacmp.c48 …acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u3… in ACMP_Open()
63 acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk); in ACMP_Close()
Ddac.c50 dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk); in DAC_Open()
51 dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk); in DAC_Open()
63 dac->CTL &= (~DAC_CTL_DACEN_Msk); in DAC_Close()
Dcrc.c50 CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk; in CRC_Open()
53 CRC->CTL |= CRC_CTL_CHKSINIT_Msk; in CRC_Open()
69 switch(CRC->CTL & CRC_CTL_CRCMODE_Msk) in CRC_GetChecksum()
Deadc.c36 eadc->CTL &= (~EADC_CTL_DIFFEN_Msk); in EADC_Open()
38 eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk); in EADC_Open()
50 eadc->CTL &= ~EADC_CTL_ADCEN_Msk; in EADC_Close()

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