1 /**************************************************************************//** 2 * @file spim.h 3 * @version V1.00 4 * @brief M480 series SPIM driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SPIM_H__ 10 #define __SPIM_H__ 11 12 /*---------------------------------------------------------------------------------------------------------*/ 13 /* Include related headers */ 14 /*---------------------------------------------------------------------------------------------------------*/ 15 16 #ifdef __cplusplus 17 extern "C" 18 { 19 #endif 20 21 22 /** @addtogroup Standard_Driver Standard Driver 23 @{ 24 */ 25 26 /** @addtogroup SPIM_Driver SPIM Driver 27 @{ 28 */ 29 30 31 /** @addtogroup SPIM_EXPORTED_CONSTANTS SPIM Exported Constants 32 @{ 33 */ 34 35 #define SPIM_DMM_MAP_ADDR 0x8000000UL /*!< DMM mode memory map base address \hideinitializer */ 36 #define SPIM_DMM_SIZE 0x2000000UL /*!< DMM mode memory mapping size \hideinitializer */ 37 #define SPIM_CCM_ADDR 0x20020000UL /*!< CCM mode memory map base address \hideinitializer */ 38 #define SPIM_CCM_SIZE 0x8000UL /*!< CCM mode memory size \hideinitializer */ 39 40 /*---------------------------------------------------------------------------------------------------------*/ 41 /* SPIM_CTL0 constant definitions */ 42 /*---------------------------------------------------------------------------------------------------------*/ 43 #define SPIM_CTL0_RW_IN(x) ((x) ? 0UL : (0x1UL << SPIM_CTL0_QDIODIR_Pos)) /*!< SPIM_CTL0: SPI Interface Direction Select \hideinitializer */ 44 #define SPIM_CTL0_BITMODE_SING (0UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: One bit mode (SPI Interface including DO, DI, HOLD, WP) \hideinitializer */ 45 #define SPIM_CTL0_BITMODE_DUAL (1UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Two bits mode (SPI Interface including D0, D1, HOLD, WP) \hideinitializer */ 46 #define SPIM_CTL0_BITMODE_QUAD (2UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Four bits mode (SPI Interface including D0, D1, D2, D3) \hideinitializer */ 47 #define SPIM_CTL0_OPMODE_IO (0UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: I/O Mode \hideinitializer */ 48 #define SPIM_CTL0_OPMODE_PAGEWRITE (1UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Write Mode \hideinitializer */ 49 #define SPIM_CTL0_OPMODE_PAGEREAD (2UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Read Mode \hideinitializer */ 50 #define SPIM_CTL0_OPMODE_DIRECTMAP (3UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Direct Map Mode \hideinitializer */ 51 52 #define CMD_NORMAL_PAGE_PROGRAM (0x02UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ 53 #define CMD_NORMAL_PAGE_PROGRAM_4B (0x12UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ 54 #define CMD_QUAD_PAGE_PROGRAM_WINBOND (0x32UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for Winbond) (Page Write Mode Use) \hideinitializer */ 55 #define CMD_QUAD_PAGE_PROGRAM_MXIC (0x38UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for MXIC) (Page Write Mode Use) \hideinitializer */ 56 #define CMD_QUAD_PAGE_PROGRAM_EON (0x40UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page Program (for EON) (Page Write Mode Use) \hideinitializer */ 57 58 #define CMD_DMA_NORMAL_READ (0x03UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Read Data (Page Read Mode Use) \hideinitializer */ 59 #define CMD_DMA_FAST_READ (0x0BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read (Page Read Mode Use) \hideinitializer */ 60 #define CMD_DMA_NORMAL_DUAL_READ (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ 61 #define CMD_DMA_FAST_READ_DUAL_OUTPUT (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ 62 #define CMD_DMA_FAST_READ_QUAD_OUTPUT (0x6BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ 63 #define CMD_DMA_FAST_DUAL_READ (0xBBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ 64 #define CMD_DMA_NORMAL_QUAD_READ (0xE7UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ 65 #define CMD_DMA_FAST_QUAD_READ (0xEBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ 66 67 /** @cond HIDDEN_SYMBOLS */ 68 69 typedef enum 70 { 71 MFGID_UNKNOW = 0x00U, 72 MFGID_SPANSION = 0x01U, 73 MFGID_EON = 0x1CU, 74 MFGID_ISSI = 0x7FU, 75 MFGID_MXIC = 0xC2U, 76 MFGID_WINBOND = 0xEFU 77 } 78 E_MFGID; 79 80 /* Flash opcodes. */ 81 #define OPCODE_WREN 0x06U /* Write enable */ 82 #define OPCODE_RDSR 0x05U /* Read status register #1*/ 83 #define OPCODE_WRSR 0x01U /* Write status register #1 */ 84 #define OPCODE_RDSR2 0x35U /* Read status register #2*/ 85 #define OPCODE_WRSR2 0x31U /* Write status register #2 */ 86 #define OPCODE_RDSR3 0x15U /* Read status register #3*/ 87 #define OPCODE_WRSR3 0x11U /* Write status register #3 */ 88 #define OPCODE_PP 0x02U /* Page program (up to 256 bytes) */ 89 #define OPCODE_SE_4K 0x20U /* Erase 4KB sector */ 90 #define OPCODE_BE_32K 0x52U /* Erase 32KB block */ 91 #define OPCODE_CHIP_ERASE 0xc7U /* Erase whole flash chip */ 92 #define OPCODE_BE_64K 0xd8U /* Erase 64KB block */ 93 #define OPCODE_READ_ID 0x90U /* Read ID */ 94 #define OPCODE_RDID 0x9fU /* Read JEDEC ID */ 95 #define OPCODE_BRRD 0x16U /* SPANSION flash - Bank Register Read command */ 96 #define OPCODE_BRWR 0x17U /* SPANSION flash - Bank Register write command */ 97 #define OPCODE_NORM_READ 0x03U /* Read data bytes */ 98 #define OPCODE_FAST_READ 0x0bU /* Read data bytes */ 99 #define OPCODE_FAST_DUAL_READ 0x3bU /* Read data bytes */ 100 #define OPCODE_FAST_QUAD_READ 0x6bU /* Read data bytes */ 101 102 /* Used for SST flashes only. */ 103 #define OPCODE_BP 0x02U /* Byte program */ 104 #define OPCODE_WRDI 0x04U /* Write disable */ 105 #define OPCODE_AAI_WP 0xadU /* Auto u32Address increment word program */ 106 107 /* Used for Macronix flashes only. */ 108 #define OPCODE_EN4B 0xb7U /* Enter 4-byte mode */ 109 #define OPCODE_EX4B 0xe9U /* Exit 4-byte mode */ 110 111 #define OPCODE_RDSCUR 0x2bU 112 #define OPCODE_WRSCUR 0x2fU 113 114 #define OPCODE_RSTEN 0x66U 115 #define OPCODE_RST 0x99U 116 117 #define OPCODE_ENQPI 0x38U 118 #define OPCODE_EXQPI 0xFFU 119 120 /* Status Register bits. */ 121 #define SR_WIP 0x1U /* Write in progress */ 122 #define SR_WEL 0x2U /* Write enable latch */ 123 #define SR_QE 0x40U /* Quad Enable for MXIC */ 124 /* Status Register #2 bits. */ 125 #define SR2_QE 0x2U /* Quad Enable for Winbond */ 126 /* meaning of other SR_* bits may differ between vendors */ 127 #define SR_BP0 0x4U /* Block protect 0 */ 128 #define SR_BP1 0x8U /* Block protect 1 */ 129 #define SR_BP2 0x10U /* Block protect 2 */ 130 #define SR_SRWD 0x80U /* SR write protect */ 131 #define SR3_ADR 0x01U /* 4-byte u32Address mode */ 132 133 #define SCUR_4BYTE 0x04U /* 4-byte u32Address mode */ 134 135 /** @endcond HIDDEN_SYMBOLS */ 136 137 /*@}*/ /* end of group SPIM_EXPORTED_CONSTANTS */ 138 139 140 /** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions 141 @{ 142 */ 143 144 145 /*---------------------------------------------------------------------------------------------------------*/ 146 /* Define Macros and functions */ 147 /*---------------------------------------------------------------------------------------------------------*/ 148 149 /** 150 * @details Enable cipher. 151 * \hideinitializer 152 */ 153 #define SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk) 154 155 /** 156 * @details Disable cipher. 157 * \hideinitializer 158 */ 159 #define SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk) 160 161 /** 162 * @details Enable cipher balance 163 * \hideinitializer 164 */ 165 #define SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk) 166 167 /** 168 * @details Disable cipher balance 169 * \hideinitializer 170 */ 171 #define SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk) 172 173 /** 174 * @details Set 4-byte address to be enabled/disabled. 175 * \hideinitializer 176 */ 177 #define SPIM_SET_4BYTE_ADDR_EN(x) \ 178 do { \ 179 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \ 180 } while (0) 181 182 /** 183 * @details Enable SPIM interrupt 184 * \hideinitializer 185 */ 186 #define SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk) 187 188 /** 189 * @details Disable SPIM interrupt 190 * \hideinitializer 191 */ 192 #define SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk) 193 194 /** 195 * @details Is interrupt flag on. 196 * \hideinitializer 197 */ 198 #define SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL) 199 200 /** 201 * @details Clear interrupt flag. 202 * \hideinitializer 203 */ 204 #define SPIM_CLR_INT() \ 205 do { \ 206 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos); \ 207 } while (0) 208 209 /** 210 * @details Set transmit/receive bit length 211 * \hideinitializer 212 */ 213 #define SPIM_SET_DATA_WIDTH(x) \ 214 do { \ 215 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos); \ 216 } while (0) 217 218 /** 219 * @details Get data transmit/receive bit length setting 220 * \hideinitializer 221 */ 222 #define SPIM_GET_DATA_WIDTH() \ 223 (((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U) 224 225 /** 226 * @details Set data transmit/receive burst number 227 * \hideinitializer 228 */ 229 #define SPIM_SET_DATA_NUM(x) \ 230 do { \ 231 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos); \ 232 } while (0) 233 234 /** 235 * @details Get data transmit/receive burst number 236 * \hideinitializer 237 */ 238 #define SPIM_GET_DATA_NUM() \ 239 (((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U) 240 241 /** 242 * @details Enable Single Input mode. 243 * \hideinitializer 244 */ 245 #define SPIM_ENABLE_SING_INPUT_MODE() \ 246 do { \ 247 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1)); \ 248 } while (0) 249 250 /** 251 * @details Enable Single Output mode. 252 * \hideinitializer 253 */ 254 #define SPIM_ENABLE_SING_OUTPUT_MODE() \ 255 do { \ 256 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0)); \ 257 } while (0) 258 259 /** 260 * @details Enable Dual Input mode. 261 * \hideinitializer 262 */ 263 #define SPIM_ENABLE_DUAL_INPUT_MODE() \ 264 do { \ 265 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U)); \ 266 } while (0) 267 268 /** 269 * @details Enable Dual Output mode. 270 * \hideinitializer 271 */ 272 #define SPIM_ENABLE_DUAL_OUTPUT_MODE() \ 273 do { \ 274 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U)); \ 275 } while (0) 276 277 /** 278 * @details Enable Quad Input mode. 279 * \hideinitializer 280 */ 281 #define SPIM_ENABLE_QUAD_INPUT_MODE() \ 282 do { \ 283 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U)); \ 284 } while (0) 285 286 /** 287 * @details Enable Quad Output mode. 288 * \hideinitializer 289 */ 290 #define SPIM_ENABLE_QUAD_OUTPUT_MODE() \ 291 do { \ 292 SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U)); \ 293 } while (0) 294 295 /** 296 * @details Set suspend interval which ranges between 0 and 15. 297 * \hideinitializer 298 */ 299 #define SPIM_SET_SUSP_INTVL(x) \ 300 do { \ 301 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos); \ 302 } while (0) 303 304 /** 305 * @details Get suspend interval setting 306 * \hideinitializer 307 */ 308 #define SPIM_GET_SUSP_INTVL() \ 309 ((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos) 310 311 /** 312 * @details Set operation mode. 313 * \hideinitializer 314 */ 315 #define SPIM_SET_OPMODE(x) \ 316 do { \ 317 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \ 318 } while (0) 319 320 /** 321 * @details Get operation mode. 322 * \hideinitializer 323 */ 324 #define SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk) 325 326 /** 327 * @details Set SPIM mode. 328 * \hideinitializer 329 */ 330 #define SPIM_SET_SPIM_MODE(x) \ 331 do { \ 332 SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x); \ 333 } while (0) 334 335 /** 336 * @details Get SPIM mode. 337 * \hideinitializer 338 */ 339 #define SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk) 340 341 /** 342 * @details Start operation. 343 * \hideinitializer 344 */ 345 #define SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk) 346 347 /** 348 * @details Is engine busy. 349 * \hideinitializer 350 */ 351 #define SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) 352 353 /** 354 * @details Wait for free. 355 * \hideinitializer 356 */ 357 #define SPIM_WAIT_FREE() \ 358 do { \ 359 while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) { } \ 360 } while (0) 361 362 /** 363 * @details Enable cache. 364 * \hideinitializer 365 */ 366 #define SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk) 367 368 /** 369 * @details Disable cache. 370 * \hideinitializer 371 */ 372 #define SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk) 373 374 /** 375 * @details Is cache enabled. 376 * \hideinitializer 377 */ 378 #define SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1) 379 380 /** 381 * @details Enable CCM 382 * \hideinitializer 383 */ 384 #define SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk) 385 386 /** 387 * @details Disable CCM. 388 * \hideinitializer 389 */ 390 #define SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk) 391 392 /** 393 * @details Is CCM enabled. 394 * \hideinitializer 395 */ 396 #define SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos) 397 398 /** 399 * @details Invalidate cache. 400 * \hideinitializer 401 */ 402 #define SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk) 403 404 /** 405 * @details Set SS(Select Active) to active level. 406 * \hideinitializer 407 */ 408 #define SPIM_SET_SS_EN(x) \ 409 do { \ 410 (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \ 411 } while (0) 412 413 /** 414 * @details Is SS(Select Active) in active level. 415 * \hideinitializer 416 */ 417 #define SPIM_GET_SS_EN() \ 418 (!(SPIM->CTL1 & SPIM_CTL1_SS_Msk)) 419 420 /** 421 * @details Set active level of slave select to be high/low. 422 * \hideinitializer 423 */ 424 #define SPIM_SET_SS_ACTLVL(x) \ 425 do { \ 426 (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos)); \ 427 } while (0) 428 429 /** 430 * @details Set idle time interval 431 * \hideinitializer 432 */ 433 #define SPIM_SET_IDL_INTVL(x) \ 434 do { \ 435 SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos); \ 436 } while (0) 437 438 /** 439 * @details Get idle time interval setting 440 * \hideinitializer 441 */ 442 #define SPIM_GET_IDL_INTVL() \ 443 ((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos) 444 445 /** 446 * @details Set SPIM clock divider 447 * \hideinitializer 448 */ 449 #define SPIM_SET_CLOCK_DIVIDER(x) \ 450 do { \ 451 SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos); \ 452 } while (0) 453 454 /** 455 * @details Get SPIM current clock divider setting 456 * \hideinitializer 457 */ 458 #define SPIM_GET_CLOCK_DIVIDER() \ 459 ((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos) 460 461 /** 462 * @details Set SPI flash deselect time interval of DMA write mode 463 * \hideinitializer 464 */ 465 #define SPIM_SET_RXCLKDLY_DWDELSEL(x) \ 466 do { \ 467 (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) | ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \ 468 } while (0) 469 470 /** 471 * @details Get SPI flash deselect time interval of DMA write mode 472 * \hideinitializer 473 */ 474 #define SPIM_GET_RXCLKDLY_DWDELSEL() \ 475 ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos) 476 477 /** 478 * @details Set sampling clock delay selection for received data 479 * \hideinitializer 480 */ 481 #define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \ 482 do { \ 483 (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) | ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \ 484 } while (0) 485 486 /** 487 * @details Get sampling clock delay selection for received data 488 * \hideinitializer 489 */ 490 #define SPIM_GET_RXCLKDLY_RDDLYSEL() \ 491 ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos) 492 493 /** 494 * @details Set sampling clock edge selection for received data 495 * \hideinitializer 496 */ 497 #define SPIM_SET_RXCLKDLY_RDEDGE() \ 498 (SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \ 499 500 /** 501 * @details Get sampling clock edge selection for received data 502 * \hideinitializer 503 */ 504 #define SPIM_CLR_RXCLKDLY_RDEDGE() \ 505 (SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk) 506 507 /** 508 * @details Set mode bits data for continuous read mode 509 * \hideinitializer 510 */ 511 #define SPIM_SET_DMMCTL_CRMDAT(x) \ 512 do { \ 513 (SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) | ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \ 514 } while (0) 515 516 /** 517 * @details Get mode bits data for continuous read mode 518 * \hideinitializer 519 */ 520 #define SPIM_GET_DMMCTL_CRMDAT() \ 521 ((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos) 522 523 /** 524 * @details Set DMM mode SPI flash deselect time 525 * \hideinitializer 526 */ 527 #define SPIM_DMM_SET_DESELTIM(x) \ 528 do { \ 529 SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos); \ 530 } while (0) 531 532 /** 533 * @details Get current DMM mode SPI flash deselect time setting 534 * \hideinitializer 535 */ 536 #define SPIM_DMM_GET_DESELTIM() \ 537 ((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos) 538 539 /** 540 * @details Enable DMM mode burst wrap mode 541 * \hideinitializer 542 */ 543 #define SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk) 544 545 /** 546 * @details Disable DMM mode burst wrap mode 547 * \hideinitializer 548 */ 549 #define SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk) 550 551 /** 552 * @details Enable DMM mode continuous read mode 553 * \hideinitializer 554 */ 555 #define SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk) 556 557 /** 558 * @details Disable DMM mode continuous read mode 559 * \hideinitializer 560 */ 561 #define SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk) 562 563 /** 564 * @details Set DMM mode SPI flash active SCLK time 565 * \hideinitializer 566 */ 567 #define SPIM_DMM_SET_ACTSCLKT(x) \ 568 do { \ 569 SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk; \ 570 } while (0) 571 572 /** 573 * @details Set SPI flash active SCLK time as SPIM default 574 * \hideinitializer 575 */ 576 #define SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk) 577 578 /** 579 * @details Set dummy cycle number (Only for DMM mode and DMA mode) 580 * \hideinitializer 581 */ 582 #define SPIM_SET_DCNUM(x) \ 583 do { \ 584 SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk; \ 585 } while (0) 586 587 /** 588 * @details Set dummy cycle number (Only for DMM mode and DMA mode) as SPIM default 589 * \hideinitializer 590 */ 591 #define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk) 592 593 594 595 /*---------------------------------------------------------------------------------------------------------*/ 596 /* Define Function Prototypes */ 597 /*---------------------------------------------------------------------------------------------------------*/ 598 599 600 int SPIM_InitFlash(int clrWP); 601 uint32_t SPIM_GetSClkFreq(void); 602 void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit); 603 int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit); 604 int SPIM_Is4ByteModeEnable(uint32_t u32NBit); 605 606 void SPIM_ChipErase(uint32_t u32NBit, int isSync); 607 void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync); 608 609 void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat); 610 void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy); 611 612 void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd); 613 void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync); 614 615 void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl); 616 void SPIM_ExitDirectMapMode(void); 617 618 void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit); 619 620 void SPIM_WinbondUnlock(uint32_t u32NBit); 621 622 /*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */ 623 624 /*@}*/ /* end of group SPIM_Driver */ 625 626 /*@}*/ /* end of group Standard_Driver */ 627 628 #ifdef __cplusplus 629 } 630 #endif 631 632 #endif /* __SPIM_H__ */ 633 634 /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ 635
