1 /**************************************************************************//** 2 * @file clk_reg.h 3 * @version V1.00 4 * @brief CLK register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CLK_REG_H__ 10 #define __CLK_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup CLK System Clock Controller(CLK) 23 Memory Mapped Structure for CLK Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var CLK_T::PWRCTL 32 * Offset: 0x00 System Power-down Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |HXTEN |HXT Enable Bit (Write Protect) 37 * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26] 38 * | | |When the default clock source is from HXT, this bit is set to 1 automatically. 39 * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. 40 * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. 41 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 42 * |[1] |LXTEN |LXT Enable Bit (Write Protect) 43 * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled. 44 * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled. 45 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 46 * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) 47 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. 48 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. 49 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 50 * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) 51 * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. 52 * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. 53 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 54 * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect) 55 * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. 56 * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC). 57 * | | |0 = Clock cycles delay Disabled. 58 * | | |1 = Clock cycles delay Enabled. 59 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 60 * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) 61 * | | |0 = Power-down mode wake-up interrupt Disabled. 62 * | | |1 = Power-down mode wake-up interrupt Enabled. 63 * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high. 64 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 65 * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status 66 * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. 67 * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. 68 * | | |Note1: Write 1 to clear the bit to 0. 69 * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 70 * |[7] |PDEN |System Power-down Enable (Write Protect) 71 * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. 72 * | | |When chip wakes up from Power-down mode, this bit is auto cleared 73 * | | |Users need to set this bit again for next Power-down. 74 * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. 75 * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection 76 * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. 77 * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI. 78 * | | |1 = Chip enters Power-down mode after CPU sleep command WFI. 79 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 80 * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) 81 * | | |This is a protected register. Please refer to open lock sequence to program it. 82 * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally 83 * | | |If gain control is enabled, crystal will consume more power than gain control off. 84 * | | |00 = HXT frequency is lower than from 8 MHz. 85 * | | |01 = HXT frequency is from 8 MHz to 12 MHz. 86 * | | |10 = HXT frequency is from 12 MHz to 16 MHz. 87 * | | |11 = HXT frequency is higher than 16 MHz. 88 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 89 * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) 90 * | | |This is a protected register. Please refer to open lock sequence to program it. 91 * | | |0 = Select INV type. 92 * | | |1 = Select GM type. 93 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 94 * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect) 95 * | | |This is a protected register. Please refer to open lock sequence to program it. 96 * | | |0 = HXT Crystal TURBO mode disabled. 97 * | | |1 = HXT Crystal TURBO mode enabled. 98 * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect) 99 * | | |00 = HIRC stable count is 64 clocks. 100 * | | |01 = HIRC stable count is 24 clocks. 101 * | | |others = Reserved. 102 * |[18] |HIRCEN |HIRC48M Enable Bit (Write Protect) 103 * | | |0 = 48 MHz internal high speed RC oscillator (HIRC) Disabled. 104 * | | |1 = 48 MHz internal high speed RC oscillator (HIRC) Enabled. 105 * @var CLK_T::AHBCLK 106 * Offset: 0x04 AHB Devices Clock Enable Control Register 107 * --------------------------------------------------------------------------------------------------- 108 * |Bits |Field |Descriptions 109 * | :----: | :----: | :---- | 110 * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit 111 * | | |0 = PDMA peripheral clock Disabled. 112 * | | |1 = PDMA peripheral clock Enabled. 113 * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit 114 * | | |0 = Flash ISP peripheral clock Disabled. 115 * | | |1 = Flash ISP peripheral clock Enabled. 116 * |[3] |EBICKEN |EBI Controller Clock Enable Bit 117 * | | |0 = EBI peripheral clock Disabled. 118 * | | |1 = EBI peripheral clock Enabled. 119 * |[5] |EMACCKEN |Ethernet Controller Clock Enable Bit 120 * | | |0 = Ethernet Controller engine clock Disabled. 121 * | | |1 = Ethernet Controller engine clock Enabled. 122 * |[6] |SDH0CKEN |SD0 Controller Clock Enable Bit 123 * | | |0 = SD0 engine clock Disabled. 124 * | | |1 = SD0 engine clock Enabled. 125 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit 126 * | | |0 = CRC peripheral clock Disabled. 127 * | | |1 = CRC peripheral clock Enabled. 128 * |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit 129 * | | |0 = HSUSB device controller's clock Disabled. 130 * | | |1 = HSUSB device controller's clock Enabled. 131 * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit 132 * | | |0 = Cryptographic Accelerator clock Disabled. 133 * | | |1 = Cryptographic Accelerator clock Enabled. 134 * |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit 135 * | | |0 = SPIM controller clock Disabled. 136 * | | |1 = SPIM controller clock Enabled. 137 * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode 138 * | | |0 = FMC clock Disabled when chip is under IDLE mode. 139 * | | |1 = FMC clock Enabled when chip is under IDLE mode. 140 * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit 141 * | | |0 = USB HOST peripheral clock Disabled. 142 * | | |1 = USB HOST peripheral clock Enabled. 143 * |[17] |SDH1CKEN |SD1 Controller Clock Enable Bit 144 * | | |0 = SD1 engine clock Disabled. 145 * | | |1 = SD1 engine clock Enabled. 146 * @var CLK_T::APBCLK0 147 * Offset: 0x08 APB Devices Clock Enable Control Register 0 148 * --------------------------------------------------------------------------------------------------- 149 * |Bits |Field |Descriptions 150 * | :----: | :----: | :---- | 151 * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) 152 * | | |0 = Watchdog timer clock Disabled. 153 * | | |1 = Watchdog timer clock Enabled. 154 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 155 * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit 156 * | | |This bit is used to control the RTC APB clock only 157 * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]) 158 * | | |It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC). 159 * | | |0 = RTC clock Disabled. 160 * | | |1 = RTC clock Enabled. 161 * |[2] |TMR0CKEN |Timer0 Clock Enable Bit 162 * | | |0 = Timer0 clock Disabled. 163 * | | |1 = Timer0 clock Enabled. 164 * |[3] |TMR1CKEN |Timer1 Clock Enable Bit 165 * | | |0 = Timer1 clock Disabled. 166 * | | |1 = Timer1 clock Enabled. 167 * |[4] |TMR2CKEN |Timer2 Clock Enable Bit 168 * | | |0 = Timer2 clock Disabled. 169 * | | |1 = Timer2 clock Enabled. 170 * |[5] |TMR3CKEN |Timer3 Clock Enable Bit 171 * | | |0 = Timer3 clock Disabled. 172 * | | |1 = Timer3 clock Enabled. 173 * |[6] |CLKOCKEN |CLKO Clock Enable Bit 174 * | | |0 = CLKO clock Disabled. 175 * | | |1 = CLKO clock Enabled. 176 * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit 177 * | | |0 = Analog comparator 0/1 clock Disabled. 178 * | | |1 = Analog comparator 0/1 clock Enabled. 179 * |[8] |I2C0CKEN |I2C0 Clock Enable Bit 180 * | | |0 = I2C0 clock Disabled. 181 * | | |1 = I2C0 clock Enabled. 182 * |[9] |I2C1CKEN |I2C1 Clock Enable Bit 183 * | | |0 = I2C1 clock Disabled. 184 * | | |1 = I2C1 clock Enabled. 185 * |[10] |I2C2CKEN |I2C2 Clock Enable Bit 186 * | | |0 = I2C2 clock Disabled. 187 * | | |1 = I2C2 clock Enabled. 188 * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit 189 * | | |0 = QSPI0 clock Disabled. 190 * | | |1 = QSPI0 clock Enabled. 191 * |[13] |SPI0CKEN |SPI0 Clock Enable Bit 192 * | | |0 = SPI0 clock Disabled. 193 * | | |1 = SPI0 clock Enabled. 194 * |[14] |SPI1CKEN |SPI1 Clock Enable Bit 195 * | | |0 = SPI1 clock Disabled. 196 * | | |1 = SPI1 clock Enabled. 197 * |[15] |SPI2CKEN |SPI2 Clock Enable Bit 198 * | | |0 = SPI2 clock Disabled. 199 * | | |1 = SPI2 clock Enabled. 200 * |[16] |UART0CKEN |UART0 Clock Enable Bit 201 * | | |0 = UART0 clock Disabled. 202 * | | |1 = UART0 clock Enabled. 203 * |[17] |UART1CKEN |UART1 Clock Enable Bit 204 * | | |0 = UART1 clock Disabled. 205 * | | |1 = UART1 clock Enabled. 206 * |[18] |UART2CKEN |UART2 Clock Enable Bit 207 * | | |0 = UART2 clock Disabled. 208 * | | |1 = UART2 clock Enabled. 209 * |[19] |UART3CKEN |UART3 Clock Enable Bit 210 * | | |0 = UART3 clock Disabled. 211 * | | |1 = UART3 clock Enabled. 212 * |[20] |UART4CKEN |UART4 Clock Enable Bit 213 * | | |0 = UART4 clock Disabled. 214 * | | |1 = UART4 clock Enabled. 215 * |[21] |UART5CKEN |UART5 Clock Enable Bit 216 * | | |0 = UART5 clock Disabled. 217 * | | |1 = UART5 clock Enabled. 218 * |[24] |CAN0CKEN |CAN0 Clock Enable Bit 219 * | | |0 = CAN0 clock Disabled. 220 * | | |1 = CAN0 clock Enabled. 221 * |[25] |CAN1CKEN |CAN1 Clock Enable Bit 222 * | | |0 = CAN1 clock Disabled. 223 * | | |1 = CAN1 clock Enabled. 224 * |[26] |OTGCKEN |USB OTG Clock Enable Bit 225 * | | |0 = USB OTG clock Disabled. 226 * | | |1 = USB OTG clock Enabled. 227 * |[27] |USBDCKEN |USB Device Clock Enable Bit 228 * | | |0 = USB Device clock Disabled. 229 * | | |1 = USB Device clock Enabled. 230 * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit 231 * | | |0 = EADC clock Disabled. 232 * | | |1 = EADC clock Enabled. 233 * |[29] |I2S0CKEN |I2S0 Clock Enable Bit 234 * | | |0 = I2S0 Clock Disabled. 235 * | | |1 = I2S0 Clock Enabled. 236 * |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit 237 * | | |0 = HSUSB OTG clock Disabled. 238 * | | |1 = HSUSB OTG clock Enabled. 239 * @var CLK_T::APBCLK1 240 * Offset: 0x0C APB Devices Clock Enable Control Register 1 241 * --------------------------------------------------------------------------------------------------- 242 * |Bits |Field |Descriptions 243 * | :----: | :----: | :---- | 244 * |[0] |SC0CKEN |SC0 Clock Enable Bit 245 * | | |0 = SC0 clock Disabled. 246 * | | |1 = SC0 clock Enabled. 247 * |[1] |SC1CKEN |SC1 Clock Enable Bit 248 * | | |0 = SC1 clock Disabled. 249 * | | |1 = SC1 clock Enabled. 250 * |[2] |SC2CKEN |SC2 Clock Enable Bit 251 * | | |0 = SC2 clock Disabled. 252 * | | |1 = SC2 clock Enabled. 253 * |[6] |SPI3CKEN |SPI3 Clock Enable Bit 254 * | | |0 = SPI3 clock Disabled. 255 * | | |1 = SPI3 clock Enabled. 256 * |[8] |USCI0CKEN |USCI0 Clock Enable Bit 257 * | | |0 = USCI0 clock Disabled. 258 * | | |1 = USCI0 clock Enabled. 259 * |[9] |USCI1CKEN |USCI1 Clock Enable Bit 260 * | | |0 = USCI1 clock Disabled. 261 * | | |1 = USCI1 clock Enabled. 262 * |[12] |DACCKEN |DAC Clock Enable Bit 263 * | | |0 = DAC clock Disabled. 264 * | | |1 = DAC clock Enabled. 265 * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit 266 * | | |0 = EPWM0 clock Disabled. 267 * | | |1 = EPWM0 clock Enabled. 268 * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit 269 * | | |0 = EPWM1 clock Disabled. 270 * | | |1 = EPWM1 clock Enabled. 271 * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit 272 * | | |0 = BPWM0 clock Disabled. 273 * | | |1 = BPWM0 clock Enabled. 274 * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit 275 * | | |0 = BPWM1 clock Disabled. 276 * | | |1 = BPWM1 clock Enabled. 277 * |[22] |QEI0CKEN |QEI0 Clock Enable Bit 278 * | | |0 = QEI0 clock Disabled. 279 * | | |1 = QEI0 clock Enabled. 280 * |[23] |QEI1CKEN |QEI1 Clock Enable Bit 281 * | | |0 = QEI1 clock Disabled. 282 * | | |1 = QEI1 clock Enabled. 283 * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit 284 * | | |0 = ECAP0 clock Disabled. 285 * | | |1 = ECAP0 clock Enabled. 286 * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit 287 * | | |0 = ECAP1 clock Disabled. 288 * | | |1 = ECAP1 clock Enabled. 289 * |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Bit 290 * | | |0 = OPA clock Disabled. 291 * | | |1 = OPA clock Enabled. 292 * @var CLK_T::CLKSEL0 293 * Offset: 0x10 Clock Source Select Control Register 0 294 * --------------------------------------------------------------------------------------------------- 295 * |Bits |Field |Descriptions 296 * | :----: | :----: | :---- | 297 * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) 298 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. 299 * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset 300 * | | |Therefore the default value is either 000b or 111b. 301 * | | |000 = Clock source from HXT. 302 * | | |001 = Clock source from LXT. 303 * | | |010 = Clock source from PLL. 304 * | | |011 = Clock source from LIRC. 305 * | | |111 = Clock source from HIRC. 306 * | | |Other = Reserved. 307 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 308 * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect) 309 * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. 310 * | | |000 = Clock source from HXT. 311 * | | |001 = Clock source from LXT. 312 * | | |010 = Clock source from HXT/2. 313 * | | |011 = Clock source from HCLK/2. 314 * | | |111 = Clock source from HIRC/2. 315 * | | |Note: if SysTick clock source is not from HCLK (i.e 316 * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2. 317 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 318 * |[8] |USBSEL |USB Clock Source Selection (Write Protect) 319 * | | |0 = Clock source from RC48M. 320 * | | |1 = Clock source from PLL. 321 * |[21:20] |SDH0SEL |SD0 Engine Clock Source Selection (Write Protect) 322 * | | |00 = Clock source from HXT clock. 323 * | | |01 = Clock source from PLL clock. 324 * | | |10 = Clock source from HCLK. 325 * | | |11 = Clock source from HIRC clock. 326 * |[23:22] |SDH1SEL |SD1 Engine Clock Source Selection (Write Protect) 327 * | | |00 = Clock source from HXT clock. 328 * | | |01 = Clock source from PLL clock. 329 * | | |10 = Clock source from HCLK. 330 * | | |11 = Clock source from HIRC clock. 331 * @var CLK_T::CLKSEL1 332 * Offset: 0x14 Clock Source Select Control Register 1 333 * --------------------------------------------------------------------------------------------------- 334 * |Bits |Field |Descriptions 335 * | :----: | :----: | :---- | 336 * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) 337 * | | |00 = Reserved. 338 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 339 * | | |10 = Clock source from HCLK/2048. 340 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 341 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 342 * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection 343 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 344 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 345 * | | |010 = Clock source from PCLK0. 346 * | | |011 = Clock source from external clock TM0 pin. 347 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 348 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 349 * | | |Others = Reserved. 350 * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection 351 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 352 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 353 * | | |010 = Clock source from PCLK0. 354 * | | |011 = Clock source from external clock TM1 pin. 355 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 356 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 357 * | | |Others = Reserved. 358 * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection 359 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 360 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 361 * | | |010 = Clock source from PCLK1. 362 * | | |011 = Clock source from external clock TM2 pin. 363 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 364 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 365 * | | |Others = Reserved. 366 * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection 367 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 368 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 369 * | | |010 = Clock source from PCLK1. 370 * | | |011 = Clock source from external clock TM3 pin. 371 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 372 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 373 * | | |Others = Reserved. 374 * |[25:24] |UART0SEL |UART0 Clock Source Selection 375 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 376 * | | |01 = Clock source from PLL. 377 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 378 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 379 * |[27:26] |UART1SEL |UART1 Clock Source Selection 380 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 381 * | | |01 = Clock source from PLL. 382 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 383 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 384 * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection 385 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 386 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 387 * | | |10 = Clock source from HCLK. 388 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 389 * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection 390 * | | |10 = Clock source from HCLK/2048. 391 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 392 * | | |Others = Reserved. 393 * @var CLK_T::CLKSEL2 394 * Offset: 0x18 Clock Source Select Control Register 2 395 * --------------------------------------------------------------------------------------------------- 396 * |Bits |Field |Descriptions 397 * | :----: | :----: | :---- | 398 * |[0] |EPWM0SEL |EPWM0 Clock Source Selection 399 * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. 400 * | | |0 = Clock source from PLL. 401 * | | |1 = Clock source from PCLK0. 402 * |[1] |EPWM1SEL |EPWM1 Clock Source Selection 403 * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. 404 * | | |0 = Clock source from PLL. 405 * | | |1 = Clock source from PCLK1. 406 * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection 407 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 408 * | | |01 = Clock source from PLL. 409 * | | |10 = Clock source from PCLK0. 410 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 411 * |[5:4] |SPI0SEL |SPI0 Clock Source Selection 412 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 413 * | | |01 = Clock source from PLL. 414 * | | |10 = Clock source from PCLK1. 415 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 416 * |[7:6] |SPI1SEL |SPI1 Clock Source Selection 417 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 418 * | | |01 = Clock source from PLL. 419 * | | |10 = Clock source from PCLK0. 420 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 421 * |[8] |BPWM0SEL |BPWM0 Clock Source Selection 422 * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. 423 * | | |0 = Clock source from PLL. 424 * | | |1 = Clock source from PCLK0. 425 * |[9] |BPWM1SEL |BPWM1 Clock Source Selection 426 * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. 427 * | | |0 = Clock source from PLL. 428 * | | |1 = Clock source from PCLK1. 429 * |[11:10] |SPI2SEL |SPI2 Clock Source Selection 430 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 431 * | | |01 = Clock source from PLL. 432 * | | |10 = Clock source from PCLK1. 433 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 434 * |[13:12] |SPI3SEL |SPI3 Clock Source Selection 435 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 436 * | | |01 = Clock source from PLL. 437 * | | |10 = Clock source from PCLK0. 438 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 439 * @var CLK_T::CLKSEL3 440 * Offset: 0x1C Clock Source Select Control Register 3 441 * --------------------------------------------------------------------------------------------------- 442 * |Bits |Field |Descriptions 443 * | :----: | :----: | :---- | 444 * |[1:0] |SC0SEL |SC0 Clock Source Selection 445 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 446 * | | |01 = Clock source from PLL. 447 * | | |10 = Clock source from PCLK0. 448 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 449 * |[3:2] |SC1SEL |SC0 Clock Source Selection 450 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 451 * | | |01 = Clock source from PLL. 452 * | | |10 = Clock source from PCLK1. 453 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 454 * |[5:4] |SC2SEL |SC2 Clock Source Selection 455 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 456 * | | |01 = Clock source from PLL. 457 * | | |10 = Clock source from PCLK0. 458 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 459 * |[8] |RTCSEL |RTC Clock Source Selection 460 * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 461 * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 462 * |[17:16] |I2S0SEL |I2S0 Clock Source Selection 463 * | | |00 = Clock source from HXT clock. 464 * | | |01 = Clock source from PLL clock. 465 * | | |10 = Clock source from PCLK. 466 * | | |11 = Clock source from HIRC clock. 467 * |[25:24] |UART2SEL |UART2 Clock Source Selection 468 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 469 * | | |01 = Clock source from PLL. 470 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 471 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 472 * |[27:26] |UART3SEL |UART3 Clock Source Selection 473 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 474 * | | |01 = Clock source from PLL. 475 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 476 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 477 * |[29:28] |UART4SEL |UART4 Clock Source Selection 478 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 479 * | | |01 = Clock source from PLL. 480 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 481 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 482 * |[31:30] |UART5SEL |UART5 Clock Source Selection 483 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 484 * | | |01 = Clock source from PLL. 485 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 486 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 487 * @var CLK_T::CLKDIV0 488 * Offset: 0x20 Clock Divider Number Register 0 489 * --------------------------------------------------------------------------------------------------- 490 * |Bits |Field |Descriptions 491 * | :----: | :----: | :---- | 492 * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source 493 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). 494 * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock 495 * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1). 496 * |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source 497 * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). 498 * |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source 499 * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). 500 * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source 501 * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). 502 * |[31:24] |SDH0DIV |SD0 Clock Divide Number From SD0 Clock Source 503 * | | |SD0 clock frequency = (SD0 clock source frequency) / (SDH0DIV + 1). 504 * @var CLK_T::CLKDIV1 505 * Offset: 0x24 Clock Divider Number Register 1 506 * --------------------------------------------------------------------------------------------------- 507 * |Bits |Field |Descriptions 508 * | :----: | :----: | :---- | 509 * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source 510 * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1). 511 * |[15:8] |SC1DIV |SC1 Clock Divide Number From SC1 Clock Source 512 * | | |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1). 513 * |[23:16] |SC2DIV |SC2 Clock Divide Number From SC2 Clock Source 514 * | | |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1). 515 * @var CLK_T::CLKDIV3 516 * Offset: 0x2C Clock Divider Number Register 3 517 * --------------------------------------------------------------------------------------------------- 518 * |Bits |Field |Descriptions 519 * | :----: | :----: | :---- | 520 * |[23:16] |EMACDIV |Ethernet Clock Divide Number Form HCLK 521 * | | |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1). 522 * |[31:24] |SDH1DIV |SD1 Clock Divide Number From SD1 Clock Source 523 * | | |SD1 clock frequency = (SD1 clock source frequency) / (SDH1DIV + 1). 524 * @var CLK_T::CLKDIV4 525 * Offset: 0x30 Clock Divider Number Register 4 526 * --------------------------------------------------------------------------------------------------- 527 * |Bits |Field |Descriptions 528 * | :----: | :----: | :---- | 529 * |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source 530 * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). 531 * |[7:4] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source 532 * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). 533 * |[11:8] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source 534 * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). 535 * |[15:12] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source 536 * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). 537 * @var CLK_T::PCLKDIV 538 * Offset: 0x34 APB Clock Divider Register 539 * --------------------------------------------------------------------------------------------------- 540 * |Bits |Field |Descriptions 541 * | :----: | :----: | :---- | 542 * |[2:0] |APB0DIV |APB0 Clock Divider 543 * | | |APB0 clock can be divided from HCLK 544 * | | |000: PCLK0 = HCLK. 545 * | | |001: PCLK0 = 1/2 HCLK. 546 * | | |010: PCLK0 = 1/4 HCLK. 547 * | | |011: PCLK0 = 1/8 HCLK. 548 * | | |100: PCLK0 = 1/16 HCLK. 549 * | | |Others: Reserved. 550 * |[6:4] |APB1DIV |APB1 Clock Divider 551 * | | |APB1 clock can be divided from HCLK 552 * | | |000: PCLK1 = HCLK. 553 * | | |001: PCLK1 = 1/2 HCLK. 554 * | | |010: PCLK1 = 1/4 HCLK. 555 * | | |011: PCLK1 = 1/8 HCLK. 556 * | | |100: PCLK1 = 1/16 HCLK. 557 * | | |Others: Reserved. 558 * @var CLK_T::PLLCTL 559 * Offset: 0x40 PLL Control Register 560 * --------------------------------------------------------------------------------------------------- 561 * |Bits |Field |Descriptions 562 * | :----: | :----: | :---- | 563 * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) 564 * | | |Refer to the formulas below the table. 565 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 566 * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) 567 * | | |Refer to the formulas below the table. 568 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 569 * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) 570 * | | |Refer to the formulas below the table. 571 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 572 * |[16] |PD |Power-down Mode (Write Protect) 573 * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. 574 * | | |0 = PLL is in normal mode. 575 * | | |1 = PLL is in Power-down mode (default). 576 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 577 * |[17] |BP |PLL Bypass Control (Write Protect) 578 * | | |0 = PLL is in normal mode (default). 579 * | | |1 = PLL clock output is same as PLL input clock FIN. 580 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 581 * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect) 582 * | | |0 = PLL FOUT Enabled. 583 * | | |1 = PLL FOUT is fixed low. 584 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 585 * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) 586 * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). 587 * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). 588 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 589 * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) 590 * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz). 591 * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz). 592 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 593 * @var CLK_T::STATUS 594 * Offset: 0x50 Clock Status Monitor Register 595 * --------------------------------------------------------------------------------------------------- 596 * |Bits |Field |Descriptions 597 * | :----: | :----: | :---- | 598 * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) 599 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. 600 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. 601 * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) 602 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. 603 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. 604 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) 605 * | | |0 = Internal PLL clock is not stable or disabled. 606 * | | |1 = Internal PLL clock is stable and enabled. 607 * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) 608 * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. 609 * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. 610 * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) 611 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. 612 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. 613 * | | |Note: This bit is read only. 614 * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) 615 * | | |This bit is updated when software switches system clock source 616 * | | |If switch target clock is stable, this bit will be set to 0 617 * | | |If switch target clock is not stable, this bit will be set to 1. 618 * | | |0 = Clock switching success. 619 * | | |1 = Clock switching failure. 620 * | | |Note: Write 1 to clear the bit to 0. 621 * @var CLK_T::CLKOCTL 622 * Offset: 0x60 Clock Output Control Register 623 * --------------------------------------------------------------------------------------------------- 624 * |Bits |Field |Descriptions 625 * | :----: | :----: | :---- | 626 * |[3:0] |FREQSEL |Clock Output Frequency Selection 627 * | | |The formula of output frequency is 628 * | | |Fout = Fin/2(N+1). 629 * | | |Fin is the input clock frequency. 630 * | | |Fout is the frequency of divider output clock. 631 * | | |N is the 4-bit value of FREQSEL[3:0]. 632 * |[4] |CLKOEN |Clock Output Enable Bit 633 * | | |0 = Clock Output function Disabled. 634 * | | |1 = Clock Output function Enabled. 635 * |[5] |DIV1EN |Clock Output Divide One Enable Bit 636 * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. 637 * | | |1 = Clock Output will output clock with source frequency. 638 * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit 639 * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. 640 * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. 641 * @var CLK_T::CLKDCTL 642 * Offset: 0x70 Clock Fail Detector Control Register 643 * --------------------------------------------------------------------------------------------------- 644 * |Bits |Field |Descriptions 645 * | :----: | :----: | :---- | 646 * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit 647 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. 648 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. 649 * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit 650 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. 651 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. 652 * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit 653 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. 654 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. 655 * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit 656 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. 657 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. 658 * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit 659 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled. 660 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled. 661 * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit 662 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled. 663 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled. 664 * @var CLK_T::CLKDSTS 665 * Offset: 0x74 Clock Fail Detector Status Register 666 * --------------------------------------------------------------------------------------------------- 667 * |Bits |Field |Descriptions 668 * | :----: | :----: | :---- | 669 * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag 670 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. 671 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. 672 * | | |Note: Write 1 to clear the bit to 0. 673 * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag 674 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. 675 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. 676 * | | |Note: Write 1 to clear the bit to 0. 677 * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag 678 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal. 679 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. 680 * | | |Note: Write 1 to clear the bit to 0. 681 * @var CLK_T::CDUPB 682 * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register 683 * --------------------------------------------------------------------------------------------------- 684 * |Bits |Field |Descriptions 685 * | :----: | :----: | :---- | 686 * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value 687 * | | |The bits define the maximum value of frequency range detector window. 688 * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. 689 * @var CLK_T::CDLOWB 690 * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register 691 * --------------------------------------------------------------------------------------------------- 692 * |Bits |Field |Descriptions 693 * | :----: | :----: | :---- | 694 * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value 695 * | | |The bits define the minimum value of frequency range detector window. 696 * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. 697 * @var CLK_T::PMUCTL 698 * Offset: 0x90 Power Manager Control Register 699 * --------------------------------------------------------------------------------------------------- 700 * |Bits |Field |Descriptions 701 * | :----: | :----: | :---- | 702 * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) 703 * | | |This is a protected register. Please refer to open lock sequence to program it. 704 * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. 705 * | | |000 = Power-down mode is selected. (PD) 706 * | | |001 = Low leakage Power-down mode is selected (LLPD). 707 * | | |010 =Fast wake-up Power-down mode is selected (FWPD). 708 * | | |011 = Reserved. 709 * | | |100 = Standby Power-down mode 0 is selected (SPD0) (SRAM retention). 710 * | | |101 = Standby Power-down mode 1 is selected (SPD1). 711 * | | |110 = Deep Power-down mode is selected (DPD). 712 * | | |111 = Reserved. 713 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 714 * |[3] |DPDHOLDEN |Deep-Power-Down Mode GPIO Hold Enable 715 * | | |0 = When GPIO enters deep power-down mode, all I/O status are tri-state. 716 * | | |1 = When GPIO enters deep power-down mode, all I/O status are hold to keep normal operating status. 717 * | | | After chip was waked up from deep power-down mode, the I/O are still keep hold status until user set CLK_IOPDCTL[0] 718 * | | | to release I/O hold status. 719 * |[8] |WKTMREN |Wake-up Timer Enable (Write Protect) 720 * | | |This is a protected register. Please refer to open lock sequence to program it. 721 * | | |0 = Wake-up timer disable at DPD/SPD mode. 722 * | | |1 = Wake-up timer enabled at DPD/SPD mode. 723 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 724 * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) 725 * | | |This is a protected register. Please refer to open lock sequence to program it. 726 * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode. 727 * | | |000 = Time-out interval is 128 OSC10K clocks (12.8 ms). 728 * | | |001 = Time-out interval is 256 OSC10K clocks (25.6 ms). 729 * | | |010 = Time-out interval is 512 OSC10K clocks (51.2 ms). 730 * | | |011 = Time-out interval is 1024 OSC10K clocks (102.4ms). 731 * | | |100 = Time-out interval is 4096 OSC10K clocks (409.6ms). 732 * | | |101 = Time-out interval is 8192 OSC10K clocks (819.2ms). 733 * | | |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms). 734 * | | |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms). 735 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 736 * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect) 737 * | | |This is a protected register. Please refer to open lock sequence to program it. 738 * | | |00 = Wake-up pin disable at Deep Power-down mode. 739 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 740 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 741 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 742 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 743 * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) 744 * | | |This is a protected register. Please refer to open lock sequence to program it. 745 * | | |0 = ACMP wake-up disable at Standby Power-down mode. 746 * | | |1 = ACMP wake-up enabled at Standby Power-down mode. 747 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 748 * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) 749 * | | |This is a protected register. Please refer to open lock sequence to program it. 750 * | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode. 751 * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. 752 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 753 * @var CLK_T::PMUSTS 754 * Offset: 0x94 Power Manager Status Register 755 * --------------------------------------------------------------------------------------------------- 756 * |Bits |Field |Descriptions 757 * | :----: | :----: | :---- | 758 * |[0] |PINWK |Pin Wake-up Flag (Read Only) 759 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0) 760 * | | |This flag is cleared when DPD mode is entered. 761 * |[1] |TMRWK |Timer Wake-up Flag (Read Only) 762 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out 763 * | | |This flag is cleared when DPD or SPD mode is entered. 764 * |[2] |RTCWK |RTC Wake-up Flag (Read Only) 765 * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened 766 * | | |This flag is cleared when DPD or SPD mode is entered. 767 * |[8] |GPAWK |GPA Wake-up Flag (Read Only) 768 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins 769 * | | |This flag is cleared when SPD mode is entered. 770 * |[9] |GPBWK |GPB Wake-up Flag (Read Only) 771 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins 772 * | | |This flag is cleared when SPD mode is entered. 773 * |[10] |GPCWK |GPC Wake-up Flag (Read Only) 774 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins 775 * | | |This flag is cleared when SPD mode is entered. 776 * |[11] |GPDWK |GPD Wake-up Flag (Read Only) 777 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins 778 * | | |This flag is cleared when SPD mode is entered. 779 * |[12] |LVRWK |LVR Wake-up Flag (Read Only) 780 * | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened 781 * | | |This flag is cleared when SPD mode is entered. 782 * |[13] |BODWK |BOD Wake-up Flag (Read Only) 783 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened 784 * | | |This flag is cleared when SPD mode is entered. 785 * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) 786 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition 787 * | | |This flag is cleared when SPD mode is entered. 788 * |[31] |CLRWK |Clear Wake-up Flag 789 * | | |0 = No clear. 790 * | | |1 = Clear all wake-up flag. 791 * @var CLK_T::LDOCTL 792 * Offset: 0x98 LDO Control Register 793 * --------------------------------------------------------------------------------------------------- 794 * |Bits |Field |Descriptions 795 * | :----: | :----: | :---- | 796 * |[18] |PDBIASEN |Power-down Bias Enable Bit 797 * | | |0 = Reserved. 798 * | | |1 = Power-down bias enabled. 799 * | | |Note: This bit should set to 1 before chip enter power-down mode. 800 * @var CLK_T::SWKDBCTL 801 * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register 802 * --------------------------------------------------------------------------------------------------- 803 * |Bits |Field |Descriptions 804 * | :----: | :----: | :---- | 805 * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection 806 * | | |0000 = Sample wake-up input once per 1 clocks. 807 * | | |0001 = Sample wake-up input once per 2 clocks. 808 * | | |0010 = Sample wake-up input once per 4 clocks. 809 * | | |0011 = Sample wake-up input once per 8 clocks. 810 * | | |0100 = Sample wake-up input once per 16 clocks. 811 * | | |0101 = Sample wake-up input once per 32 clocks. 812 * | | |0110 = Sample wake-up input once per 64 clocks. 813 * | | |0111 = Sample wake-up input once per 128 clocks. 814 * | | |1000 = Sample wake-up input once per 256 clocks. 815 * | | |1001 = Sample wake-up input once per 2*256 clocks. 816 * | | |1010 = Sample wake-up input once per 4*256 clocks. 817 * | | |1011 = Sample wake-up input once per 8*256 clocks. 818 * | | |1100 = Sample wake-up input once per 16*256 clocks. 819 * | | |1101 = Sample wake-up input once per 32*256 clocks. 820 * | | |1110 = Sample wake-up input once per 64*256 clocks. 821 * | | |1111 = Sample wake-up input once per 128*256 clocks. 822 * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). 823 * @var CLK_T::PASWKCTL 824 * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register 825 * --------------------------------------------------------------------------------------------------- 826 * |Bits |Field |Descriptions 827 * | :----: | :----: | :---- | 828 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 829 * | | |0 = GPA group pin wake-up function disabled. 830 * | | |1 = GPA group pin wake-up function enabled. 831 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 832 * | | |0 = GPA group pin rising edge wake-up function disabled. 833 * | | |1 = GPA group pin rising edge wake-up function enabled. 834 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 835 * | | |0 = GPA group pin falling edge wake-up function disabled. 836 * | | |1 = GPA group pin falling edge wake-up function enabled. 837 * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select 838 * | | |0000 = GPA.0 wake-up function enabled. 839 * | | |0001 = GPA.1 wake-up function enabled. 840 * | | |0010 = GPA.2 wake-up function enabled. 841 * | | |0011 = GPA.3 wake-up function enabled. 842 * | | |0100 = GPA.4 wake-up function enabled. 843 * | | |0101 = GPA.5 wake-up function enabled. 844 * | | |0110 = GPA.6 wake-up function enabled. 845 * | | |0111 = GPA.7 wake-up function enabled. 846 * | | |1000 = GPA.8 wake-up function enabled. 847 * | | |1001 = GPA.9 wake-up function enabled. 848 * | | |1010 = GPA.10 wake-up function enabled. 849 * | | |1011 = GPA.11 wake-up function enabled. 850 * | | |1100 = GPA.12 wake-up function enabled. 851 * | | |1101 = GPA.13 wake-up function enabled. 852 * | | |1110 = GPA.14 wake-up function enabled. 853 * | | |1111 = GPA.15 wake-up function enabled. 854 * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit 855 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO 856 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 857 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. 858 * | | |0 = Standby power-down wake-up pin De-bounce function disable. 859 * | | |1 = Standby power-down wake-up pin De-bounce function enable. 860 * | | |The de-bounce function is valid only for edge triggered. 861 * @var CLK_T::PBSWKCTL 862 * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register 863 * --------------------------------------------------------------------------------------------------- 864 * |Bits |Field |Descriptions 865 * | :----: | :----: | :---- | 866 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 867 * | | |0 = GPB group pin wake-up function disabled. 868 * | | |1 = GPB group pin wake-up function enabled. 869 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 870 * | | |0 = GPB group pin rising edge wake-up function disabled. 871 * | | |1 = GPB group pin rising edge wake-up function enabled. 872 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 873 * | | |0 = GPB group pin falling edge wake-up function disabled. 874 * | | |1 = GPB group pin falling edge wake-up function enabled. 875 * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select 876 * | | |0000 = GPB.0 wake-up function enabled. 877 * | | |0001 = GPB.1 wake-up function enabled. 878 * | | |0010 = GPB.2 wake-up function enabled. 879 * | | |0011 = GPB.3 wake-up function enabled. 880 * | | |0100 = GPB.4 wake-up function enabled. 881 * | | |0101 = GPB.5 wake-up function enabled. 882 * | | |0110 = GPB.6 wake-up function enabled. 883 * | | |0111 = GPB.7 wake-up function enabled. 884 * | | |1000 = GPB.8 wake-up function enabled. 885 * | | |1001 = GPB.9 wake-up function enabled. 886 * | | |1010 = GPB.10 wake-up function enabled. 887 * | | |1011 = GPB.11 wake-up function enabled. 888 * | | |1100 = GPB.12 wake-up function enabled. 889 * | | |1101 = GPB.13 wake-up function enabled. 890 * | | |1110 = GPB.14 wake-up function enabled. 891 * | | |1111 = GPB.15 wake-up function enabled. 892 * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit 893 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO 894 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 895 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. 896 * | | |0 = Standby power-down wake-up pin De-bounce function disable. 897 * | | |1 = Standby power-down wake-up pin De-bounce function enable. 898 * | | |The de-bounce function is valid only for edge triggered. 899 * @var CLK_T::PCSWKCTL 900 * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register 901 * --------------------------------------------------------------------------------------------------- 902 * |Bits |Field |Descriptions 903 * | :----: | :----: | :---- | 904 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 905 * | | |0 = GPC group pin wake-up function disabled. 906 * | | |1 = GPC group pin wake-up function enabled. 907 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 908 * | | |0 = GPC group pin rising edge wake-up function disabled. 909 * | | |1 = GPC group pin rising edge wake-up function enabled. 910 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 911 * | | |0 = GPC group pin falling edge wake-up function disabled. 912 * | | |1 = GPC group pin falling edge wake-up function enabled. 913 * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select 914 * | | |0000 = GPC.0 wake-up function enabled. 915 * | | |0001 = GPC.1 wake-up function enabled. 916 * | | |0010 = GPC.2 wake-up function enabled. 917 * | | |0011 = GPC.3 wake-up function enabled. 918 * | | |0100 = GPC.4 wake-up function enabled. 919 * | | |0101 = GPC.5 wake-up function enabled. 920 * | | |0110 = GPC.6 wake-up function enabled. 921 * | | |0111 = GPC.7 wake-up function enabled. 922 * | | |1000 = GPC.8 wake-up function enabled. 923 * | | |1001 = GPC.9 wake-up function enabled. 924 * | | |1010 = GPC.10 wake-up function enabled. 925 * | | |1011 = GPC.11 wake-up function enabled. 926 * | | |1100 = GPC.12 wake-up function enabled. 927 * | | |1101 = GPC.13 wake-up function enabled. 928 * | | |1110 = GPC.14 wake-up function enabled. 929 * | | |1111 = GPC.15 wake-up function enabled. 930 * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit 931 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO 932 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 933 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. 934 * | | |0 = Standby power-down wake-up pin De-bounce function disable. 935 * | | |1 = Standby power-down wake-up pin De-bounce function enable. 936 * | | |The de-bounce function is valid only for edge triggered. 937 * @var CLK_T::PDSWKCTL 938 * Offset: 0xAC GPD Standby Power-down Wake-up Control Register 939 * --------------------------------------------------------------------------------------------------- 940 * |Bits |Field |Descriptions 941 * | :----: | :----: | :---- | 942 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 943 * | | |0 = GPD group pin wake-up function disabled. 944 * | | |1 = GPD group pin wake-up function enabled. 945 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 946 * | | |0 = GPD group pin rising edge wake-up function disabled. 947 * | | |1 = GPD group pin rising edge wake-up function enabled. 948 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 949 * | | |0 = GPD group pin falling edge wake-up function disabled. 950 * | | |1 = GPD group pin falling edge wake-up function enabled. 951 * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select 952 * | | |0000 = GPD.0 wake-up function enabled. 953 * | | |0001 = GPD.1 wake-up function enabled. 954 * | | |0010 = GPD.2 wake-up function enabled. 955 * | | |0011 = GPD.3 wake-up function enabled. 956 * | | |0100 = GPD.4 wake-up function enabled. 957 * | | |0101 = GPD.5 wake-up function enabled. 958 * | | |0110 = GPD.6 wake-up function enabled. 959 * | | |0111 = GPD.7 wake-up function enabled. 960 * | | |1000 = GPD.8 wake-up function enabled. 961 * | | |1001 = GPD.9 wake-up function enabled. 962 * | | |1010 = GPD.10 wake-up function enabled. 963 * | | |1011 = GPD.11 wake-up function enabled. 964 * | | |1100 = GPD.12 wake-up function enabled. 965 * | | |1101 = GPD.13 wake-up function enabled. 966 * | | |1110 = GPD.14 wake-up function enabled. 967 * | | |1111 = GPD.15 wake-up function enabled. 968 * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit 969 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO 970 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 971 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. 972 * | | |0 = Standby power-down wake-up pin De-bounce function disable. 973 * | | |1 = Standby power-down wake-up pin De-bounce function enable. 974 * | | |The de-bounce function is valid only for edge triggered. 975 * @var CLK_T::IOPDCTL 976 * Offset: 0xB0 GPIO Standby Power-down Control Register 977 * --------------------------------------------------------------------------------------------------- 978 * |Bits |Field |Descriptions 979 * | :----: | :----: | :---- | 980 * |[0] |IOHR |GPIO Hold Release 981 * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status 982 * | | |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. 983 * | | |This bit is auto cleared by hardware. 984 */ 985 __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ 986 __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ 987 __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ 988 __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */ 989 __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ 990 __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ 991 __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ 992 __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */ 993 __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ 994 __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ 995 __IO uint32_t CLKDIV2; /*!< [0x0028] Clock Divider Number Register 2 */ 996 __IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */ 997 __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ 998 __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ 999 /** @cond HIDDEN_SYMBOLS */ 1000 __I uint32_t RESERVE1[2]; 1001 /** @endcond */ 1002 __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ 1003 /** @cond HIDDEN_SYMBOLS */ 1004 __I uint32_t RESERVE2[3]; 1005 /** @endcond */ 1006 __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ 1007 /** @cond HIDDEN_SYMBOLS */ 1008 __I uint32_t RESERVE3[3]; 1009 /** @endcond */ 1010 __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ 1011 /** @cond HIDDEN_SYMBOLS */ 1012 __I uint32_t RESERVE4[3]; 1013 /** @endcond */ 1014 __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ 1015 __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ 1016 __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */ 1017 __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */ 1018 /** @cond HIDDEN_SYMBOLS */ 1019 __I uint32_t RESERVE5[4]; 1020 /** @endcond */ 1021 __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ 1022 __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ 1023 __IO uint32_t LDOCTL; /*!< [0x0098] LDO Control Register */ 1024 __IO uint32_t SWKDBCTL; /*!< [0x009c] Standby Power-down Wake-up De-bounce Control Register */ 1025 __IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */ 1026 __IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */ 1027 __IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */ 1028 __IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */ 1029 __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */ 1030 1031 } CLK_T; 1032 1033 /** 1034 @addtogroup CLK_CONST CLK Bit Field Definition 1035 Constant Definitions for CLK Controller 1036 @{ */ 1037 1038 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ 1039 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ 1040 1041 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ 1042 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ 1043 1044 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ 1045 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ 1046 1047 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ 1048 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ 1049 1050 #define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */ 1051 #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */ 1052 1053 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ 1054 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ 1055 1056 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ 1057 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ 1058 1059 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ 1060 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ 1061 1062 #define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ 1063 #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ 1064 1065 #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ 1066 #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ 1067 1068 #define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */ 1069 #define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */ 1070 1071 #define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */ 1072 #define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */ 1073 1074 #define CLK_PWRCTL_HIRC48MEN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48MEN Position */ 1075 #define CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos) /*!< CLK_T::PWRCTL: HIRC48MEN Mask */ 1076 1077 #define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */ 1078 #define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */ 1079 1080 #define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ 1081 #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ 1082 1083 #define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ 1084 #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ 1085 1086 #define CLK_AHBCLK_EMACCKEN_Pos (5) /*!< CLK_T::AHBCLK: EMACCKEN Position */ 1087 #define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /*!< CLK_T::AHBCLK: EMACCKEN Mask */ 1088 1089 #define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */ 1090 #define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */ 1091 1092 #define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ 1093 #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ 1094 1095 #define CLK_AHBCLK_CCAPCKEN_Pos (8) /*!< CLK_T::AHBCLK: CCAPCKEN Position */ 1096 #define CLK_AHBCLK_CCAPCKEN_Msk (0x1ul << CLK_AHBCLK_CCAPCKEN_Pos) /*!< CLK_T::AHBCLK: CCAPCKEN Mask */ 1097 1098 #define CLK_AHBCLK_SENCKEN_Pos (9) /*!< CLK_T::AHBCLK: SENCKEN Position */ 1099 #define CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos) /*!< CLK_T::AHBCLK: SENCKEN Mask */ 1100 1101 #define CLK_AHBCLK_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK: HSUSBDCKEN Position */ 1102 #define CLK_AHBCLK_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK: HSUSBDCKEN Mask */ 1103 1104 #define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ 1105 #define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ 1106 1107 #define CLK_AHBCLK_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK: SPIMCKEN Position */ 1108 #define CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK: SPIMCKEN Mask */ 1109 1110 #define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ 1111 #define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ 1112 1113 #define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */ 1114 #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */ 1115 1116 #define CLK_AHBCLK_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK: SDH1CKEN Position */ 1117 #define CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK: SDH1CKEN Mask */ 1118 1119 #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ 1120 #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ 1121 1122 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ 1123 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ 1124 1125 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ 1126 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ 1127 1128 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ 1129 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ 1130 1131 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ 1132 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ 1133 1134 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ 1135 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ 1136 1137 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ 1138 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ 1139 1140 #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ 1141 #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ 1142 1143 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ 1144 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ 1145 1146 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ 1147 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ 1148 1149 #define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ 1150 #define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ 1151 1152 #define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ 1153 #define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ 1154 1155 #define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ 1156 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ 1157 1158 #define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ 1159 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ 1160 1161 #define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ 1162 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ 1163 1164 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ 1165 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ 1166 1167 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ 1168 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ 1169 1170 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ 1171 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ 1172 1173 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ 1174 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ 1175 1176 #define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ 1177 #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ 1178 1179 #define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ 1180 #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ 1181 1182 #define CLK_APBCLK0_UART6CKEN_Pos (22) /*!< CLK_T::APBCLK0: UART6CKEN Position */ 1183 #define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos) /*!< CLK_T::APBCLK0: UART6CKEN Mask */ 1184 1185 #define CLK_APBCLK0_UART7CKEN_Pos (23) /*!< CLK_T::APBCLK0: UART7CKEN Position */ 1186 #define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos) /*!< CLK_T::APBCLK0: UART7CKEN Mask */ 1187 1188 #define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ 1189 #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ 1190 1191 #define CLK_APBCLK0_CAN1CKEN_Pos (25) /*!< CLK_T::APBCLK0: CAN1CKEN Position */ 1192 #define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /*!< CLK_T::APBCLK0: CAN1CKEN Mask */ 1193 1194 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ 1195 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ 1196 1197 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ 1198 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ 1199 1200 #define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ 1201 #define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ 1202 1203 #define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ 1204 #define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ 1205 1206 #define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */ 1207 #define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */ 1208 1209 #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ 1210 #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ 1211 1212 #define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ 1213 #define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ 1214 1215 #define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ 1216 #define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ 1217 1218 #define CLK_APBCLK1_QSPI1CKEN_Pos (4) /*!< CLK_T::APBCLK1: QSPI1CKEN Position */ 1219 #define CLK_APBCLK1_QSPI1CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos) /*!< CLK_T::APBCLK1: QSPI1CKEN Mask */ 1220 1221 #define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ 1222 #define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ 1223 1224 #define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ 1225 #define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ 1226 1227 #define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ 1228 #define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ 1229 1230 #define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ 1231 #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ 1232 1233 #define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ 1234 #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ 1235 1236 #define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ 1237 #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ 1238 1239 #define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ 1240 #define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ 1241 1242 #define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ 1243 #define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ 1244 1245 #define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */ 1246 #define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */ 1247 1248 #define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */ 1249 #define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */ 1250 1251 #define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */ 1252 #define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */ 1253 1254 #define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ 1255 #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ 1256 1257 #define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ 1258 #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ 1259 1260 #define CLK_APBCLK1_CAN2CKEN_Pos (28) /*!< CLK_T::APBCLK1: CAN2CKEN Position */ 1261 #define CLK_APBCLK1_CAN2CKEN_Msk (0x1ul << CLK_APBCLK1_CAN2CKEN_Pos) /*!< CLK_T::APBCLK1: CAN2CKEN Mask */ 1262 1263 #define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK_T::APBCLK1: OPACKEN Position */ 1264 #define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK_T::APBCLK1: OPACKEN Mask */ 1265 1266 #define CLK_APBCLK1_EADC1CKEN_Pos (31) /*!< CLK_T::APBCLK1: EADC1CKEN Position */ 1267 #define CLK_APBCLK1_EADC1CKEN_Msk (0x1ul << CLK_APBCLK1_EADC1CKEN_Pos) /*!< CLK_T::APBCLK1: EADC1CKEN Mask */ 1268 1269 #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ 1270 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ 1271 1272 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ 1273 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ 1274 1275 #define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */ 1276 #define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */ 1277 1278 #define CLK_CLKSEL0_CCAPSEL_Pos (16) /*!< CLK_T::CLKSEL0: CCAPSEL Position */ 1279 #define CLK_CLKSEL0_CCAPSEL_Msk (0x3ul << CLK_CLKSEL0_CCAPSEL_Pos) /*!< CLK_T::CLKSEL0: CCAPSEL Mask */ 1280 1281 #define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ 1282 #define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ 1283 1284 #define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */ 1285 #define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */ 1286 1287 #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ 1288 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ 1289 1290 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ 1291 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ 1292 1293 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ 1294 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ 1295 1296 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ 1297 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ 1298 1299 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ 1300 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ 1301 1302 #define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ 1303 #define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ 1304 1305 #define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */ 1306 #define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ 1307 1308 #define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ 1309 #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ 1310 1311 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ 1312 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ 1313 1314 #define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ 1315 #define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ 1316 1317 #define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ 1318 #define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ 1319 1320 #define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ 1321 #define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ 1322 1323 #define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ 1324 #define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ 1325 1326 #define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ 1327 #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ 1328 1329 #define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ 1330 #define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ 1331 1332 #define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ 1333 #define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ 1334 1335 #define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */ 1336 #define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */ 1337 1338 #define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ 1339 #define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ 1340 1341 #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ 1342 #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ 1343 1344 #define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ 1345 #define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ 1346 1347 #define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ 1348 #define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ 1349 1350 #define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */ 1351 #define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */ 1352 1353 #define CLK_CLKSEL3_QSPI1SEL_Pos (12) /*!< CLK_T::CLKSEL3: QSPI1SEL Position */ 1354 #define CLK_CLKSEL3_QSPI1SEL_Msk (0x3ul << CLK_CLKSEL3_QSPI1SEL_Pos) /*!< CLK_T::CLKSEL3: QSPI1SEL Mask */ 1355 1356 #define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ 1357 #define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ 1358 1359 #define CLK_CLKSEL3_UART6SEL_Pos (20) /*!< CLK_T::CLKSEL3: UART6SEL Position */ 1360 #define CLK_CLKSEL3_UART6SEL_Msk (0x3ul << CLK_CLKSEL3_UART6SEL_Pos) /*!< CLK_T::CLKSEL3: UART6SEL Mask */ 1361 1362 #define CLK_CLKSEL3_UART7SEL_Pos (22) /*!< CLK_T::CLKSEL3: UART7SEL Position */ 1363 #define CLK_CLKSEL3_UART7SEL_Msk (0x3ul << CLK_CLKSEL3_UART7SEL_Pos) /*!< CLK_T::CLKSEL3: UART7SEL Mask */ 1364 1365 #define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ 1366 #define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ 1367 1368 #define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */ 1369 #define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */ 1370 1371 #define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */ 1372 #define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ 1373 1374 #define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */ 1375 #define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ 1376 1377 #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ 1378 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ 1379 1380 #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ 1381 #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ 1382 1383 #define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ 1384 #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ 1385 1386 #define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ 1387 #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ 1388 1389 #define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ 1390 #define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ 1391 1392 #define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ 1393 #define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ 1394 1395 #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ 1396 #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ 1397 1398 #define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ 1399 #define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ 1400 1401 #define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ 1402 #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ 1403 1404 #define CLK_CLKDIV2_I2SDIV_Pos (0) /*!< CLK_T::CLKDIV2: I2SDIV Position */ 1405 #define CLK_CLKDIV2_I2SDIV_Msk (0xful << CLK_CLKDIV2_I2SDIV_Pos) /*!< CLK_T::CLKDIV2: I2SDIV Mask */ 1406 1407 #define CLK_CLKDIV2_EADC1DIV_Pos (24) /*!< CLK_T::CLKDIV2: EADC1DIV Position */ 1408 #define CLK_CLKDIV2_EADC1DIV_Msk (0xfful << CLK_CLKDIV2_EADC1DIV_Pos) /*!< CLK_T::CLKDIV2: EADC1DIV Mask */ 1409 1410 #define CLK_CLKDIV3_CCAPDIV_Pos (0) /*!< CLK_T::CLKDIV3: CCAPDIV Position */ 1411 #define CLK_CLKDIV3_CCAPDIV_Msk (0xfful << CLK_CLKDIV3_CCAPDIV_Pos) /*!< CLK_T::CLKDIV3: CCAPDIV Mask */ 1412 1413 #define CLK_CLKDIV3_VSENSEDIV_Pos (8) /*!< CLK_T::CLKDIV3: VSENSEDIV Position */ 1414 #define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLK_T::CLKDIV3: VSENSEDIV Mask */ 1415 1416 #define CLK_CLKDIV3_EMACDIV_Pos (16) /*!< CLK_T::CLKDIV3: EMACDIV Position */ 1417 #define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLK_T::CLKDIV3: EMACDIV Mask */ 1418 1419 #define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */ 1420 #define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */ 1421 1422 #define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ 1423 #define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ 1424 1425 #define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ 1426 #define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ 1427 1428 #define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ 1429 #define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ 1430 1431 #define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ 1432 #define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ 1433 1434 #define CLK_CLKDIV4_UART6DIV_Pos (16) /*!< CLK_T::CLKDIV4: UART6DIV Position */ 1435 #define CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLK_T::CLKDIV4: UART6DIV Mask */ 1436 1437 #define CLK_CLKDIV4_UART7DIV_Pos (20) /*!< CLK_T::CLKDIV4: UART7DIV Position */ 1438 #define CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLK_T::CLKDIV4: UART7DIV Mask */ 1439 1440 #define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ 1441 #define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ 1442 1443 #define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ 1444 #define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ 1445 1446 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ 1447 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ 1448 1449 #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ 1450 #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ 1451 1452 #define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ 1453 #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ 1454 1455 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ 1456 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ 1457 1458 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ 1459 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ 1460 1461 #define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ 1462 #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ 1463 1464 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ 1465 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ 1466 1467 #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ 1468 #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ 1469 1470 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ 1471 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ 1472 1473 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ 1474 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ 1475 1476 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ 1477 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ 1478 1479 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ 1480 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ 1481 1482 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ 1483 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ 1484 1485 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ 1486 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ 1487 1488 #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ 1489 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ 1490 1491 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ 1492 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ 1493 1494 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ 1495 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ 1496 1497 #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ 1498 #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ 1499 1500 #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ 1501 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ 1502 1503 #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ 1504 #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ 1505 1506 #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ 1507 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ 1508 1509 #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ 1510 #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ 1511 1512 #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ 1513 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ 1514 1515 #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ 1516 #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ 1517 1518 #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ 1519 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ 1520 1521 #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ 1522 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ 1523 1524 #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ 1525 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ 1526 1527 #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ 1528 #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ 1529 1530 #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ 1531 #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ 1532 1533 #define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ 1534 #define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ 1535 1536 #define CLK_PMUCTL_DPDHOLDEN_Pos (3) /*!< CLK_T::PMUCTL: DPDHOLDEN Position */ 1537 #define CLK_PMUCTL_DPDHOLDEN_Msk (0x1ul << CLK_PMUCTL_DPDHOLDEN_Pos) /*!< CLK_T::PMUCTL: DPDHOLDEN Mask */ 1538 1539 #define CLK_PMUCTL_SRETSEL_Pos (4) /*!< CLK_T::PMUCTL: SRETSEL Position */ 1540 #define CLK_PMUCTL_SRETSEL_Msk (0x7ul << CLK_PMUCTL_SRETSEL_Pos) /*!< CLK_T::PMUCTL: SRETSEL Mask */ 1541 1542 #define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ 1543 #define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ 1544 1545 #define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ 1546 #define CLK_PMUCTL_WKTMRIS_Msk (0xful << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ 1547 1548 #define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */ 1549 #define CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */ 1550 1551 #define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ 1552 #define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ 1553 1554 #define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ 1555 #define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ 1556 1557 #define CLK_PMUCTL_WKPINEN1_Pos (24) /*!< CLK_T::PMUCTL: WKPINEN1 Position */ 1558 #define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) /*!< CLK_T::PMUCTL: WKPINEN1 Mask */ 1559 1560 #define CLK_PMUCTL_WKPINEN2_Pos (26) /*!< CLK_T::PMUCTL: WKPINEN2 Position */ 1561 #define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) /*!< CLK_T::PMUCTL: WKPINEN2 Mask */ 1562 1563 #define CLK_PMUCTL_WKPINEN3_Pos (28) /*!< CLK_T::PMUCTL: WKPINEN3 Position */ 1564 #define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) /*!< CLK_T::PMUCTL: WKPINEN3 Mask */ 1565 1566 #define CLK_PMUCTL_WKPINEN4_Pos (30) /*!< CLK_T::PMUCTL: WKPINEN4 Position */ 1567 #define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) /*!< CLK_T::PMUCTL: WKPINEN4 Mask */ 1568 1569 #define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */ 1570 #define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */ 1571 1572 #define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ 1573 #define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ 1574 1575 #define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ 1576 #define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ 1577 1578 #define CLK_PMUSTS_PINWK1_Pos (3) /*!< CLK_T::PMUSTS: PINWK1 Position */ 1579 #define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) /*!< CLK_T::PMUSTS: PINWK1 Mask */ 1580 1581 #define CLK_PMUSTS_PINWK2_Pos (4) /*!< CLK_T::PMUSTS: PINWK2 Position */ 1582 #define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) /*!< CLK_T::PMUSTS: PINWK2 Mask */ 1583 1584 #define CLK_PMUSTS_PINWK3_Pos (5) /*!< CLK_T::PMUSTS: PINWK3 Position */ 1585 #define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) /*!< CLK_T::PMUSTS: PINWK3 Mask */ 1586 1587 #define CLK_PMUSTS_PINWK4_Pos (6) /*!< CLK_T::PMUSTS: PINWK4 Position */ 1588 #define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) /*!< CLK_T::PMUSTS: PINWK4 Mask */ 1589 1590 #define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ 1591 #define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ 1592 1593 #define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ 1594 #define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ 1595 1596 #define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ 1597 #define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ 1598 1599 #define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ 1600 #define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ 1601 1602 #define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ 1603 #define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ 1604 1605 #define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ 1606 #define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ 1607 1608 #define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */ 1609 #define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */ 1610 1611 #define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ 1612 #define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ 1613 1614 #define CLK_LDOCTL_PDBIASEN_Pos (18) /*!< CLK_T::LDOCTL: PDBIASEN Position */ 1615 #define CLK_LDOCTL_PDBIASEN_Msk (0x1ul << CLK_LDOCTL_PDBIASEN_Pos) /*!< CLK_T::LDOCTL: PDBIASEN Mask */ 1616 1617 #define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ 1618 #define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ 1619 1620 #define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ 1621 #define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ 1622 1623 #define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ 1624 #define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ 1625 1626 #define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ 1627 #define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ 1628 1629 #define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ 1630 #define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ 1631 1632 #define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ 1633 #define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ 1634 1635 #define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ 1636 #define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ 1637 1638 #define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ 1639 #define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ 1640 1641 #define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ 1642 #define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ 1643 1644 #define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ 1645 #define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ 1646 1647 #define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ 1648 #define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ 1649 1650 #define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ 1651 #define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ 1652 1653 #define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ 1654 #define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ 1655 1656 #define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ 1657 #define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ 1658 1659 #define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ 1660 #define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ 1661 1662 #define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ 1663 #define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ 1664 1665 #define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ 1666 #define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ 1667 1668 #define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ 1669 #define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ 1670 1671 #define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ 1672 #define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ 1673 1674 #define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ 1675 #define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ 1676 1677 #define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ 1678 #define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ 1679 1680 #define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ 1681 #define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ 1682 1683 /**@}*/ /* CLK_CONST */ 1684 /**@}*/ /* end of CLK register group */ 1685 /**@}*/ /* end of REGISTER group */ 1686 1687 #if defined ( __CC_ARM ) 1688 #pragma no_anon_unions 1689 #endif 1690 1691 #endif /* __CLK_REG_H__ */ 1692
