1 /**************************************************************************//** 2 * @file wdt_reg.h 3 * @version V1.00 4 * @brief WDT register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __WDT_REG_H__ 10 #define __WDT_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup WDT Watch Dog Timer Controller(WDT) 23 Memory Mapped Structure for WDT Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var WDT_T::CTL 32 * Offset: 0x00 WDT Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |RSTCNT |Reset WDT Up Counter (Write Protect) 37 * | | |0 = No effect. 38 * | | |1 = Reset the internal 18-bit WDT up counter value. 39 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 40 * | | |Note2: This bit will be automatically cleared by hardware. 41 * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect) 42 * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. 43 * | | |0 = WDT time-out reset function Disabled. 44 * | | |1 = WDT time-out reset function Enabled. 45 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 46 * |[2] |RSTF |WDT Time-out Reset Flag 47 * | | |This bit indicates the system has been reset by WDT time-out reset or not. 48 * | | |0 = WDT time-out reset did not occur. 49 * | | |1 = WDT time-out reset occurred. 50 * | | |Note: This bit is cleared by writing 1 to it. 51 * |[3] |IF |WDT Time-out Interrupt Flag 52 * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval 53 * | | |0 = WDT time-out interrupt did not occur. 54 * | | |1 = WDT time-out interrupt occurred. 55 * | | |Note: This bit is cleared by writing 1 to it. 56 * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) 57 * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. 58 * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. 59 * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. 60 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 61 * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT. 62 * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect) 63 * | | |This bit indicates the interrupt wake-up flag status of WDT 64 * | | |0 = WDT does not cause chip wake-up. 65 * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. 66 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 67 * | | |Note2: This bit is cleared by writing 1 to it. 68 * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) 69 * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. 70 * | | |0 = WDT time-out interrupt Disabled. 71 * | | |1 = WDT time-out interrupt Enabled. 72 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 73 * |[7] |WDTEN |WDT Enable Control (Write Protect) 74 * | | |0 = WDT Disabled (This action will reset the internal up counter value). 75 * | | |1 = WDT Enabled. 76 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 77 * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0. 78 * |[10:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) 79 * | | |These three bits select the time-out interval period for the WDT. 80 * | | |000 = 24 * WDT_CLK. 81 * | | |001 = 26 * WDT_CLK. 82 * | | |010 = 28 * WDT_CLK. 83 * | | |011 = 210 * WDT_CLK. 84 * | | |100 = 212 * WDT_CLK. 85 * | | |101 = 214 * WDT_CLK. 86 * | | |110 = 216 * WDT_CLK. 87 * | | |111 = 218 * WDT_CLK. 88 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 89 * |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only) 90 * | | |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. 91 * | | |0 = Set WDTEN bit is completed. 92 * | | |1 = Set WDTEN bit is synchronizing and not become active yet.. 93 * | | |Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active. 94 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) 95 * | | |0 = ICE debug mode acknowledgement affects WDT counting. 96 * | | |WDT up counter will be held while CPU is held by ICE. 97 * | | |1 = ICE debug mode acknowledgement Disabled. 98 * | | |WDT up counter will keep going no matter CPU is held by ICE or not. 99 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 100 * @var WDT_T::ALTCTL 101 * Offset: 0x04 WDT Alternative Control Register 102 * --------------------------------------------------------------------------------------------------- 103 * |Bits |Field |Descriptions 104 * | :----: | :----: | :---- | 105 * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect) 106 * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened 107 * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. 108 * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. 109 * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. 110 * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. 111 * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. 112 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 113 * | | |Note2: This register will be reset to 0 if WDT time-out reset happened. 114 * @var WDT_T::RSTCNT 115 * Offset: 0x08 WDT Reset Counter Register 116 * --------------------------------------------------------------------------------------------------- 117 * |Bits |Field |Descriptions 118 * | :----: | :----: | :---- | 119 * |[31:0] |RSTCNT |WDT Reset Counter Register 120 * | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0. 121 * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. 122 * | | |Note: RSTCNT (WDT_CTL[0]) bit is a write protected bit 123 * | | |RSTCNT (WDT_RSTCNT[31:0]) bits are not write protected. 124 */ 125 __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ 126 __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ 127 __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ 128 129 } WDT_T; 130 131 /** 132 @addtogroup WDT_CONST WDT Bit Field Definition 133 Constant Definitions for WDT Controller 134 @{ */ 135 136 #define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */ 137 #define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */ 138 139 #define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ 140 #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ 141 142 #define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ 143 #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ 144 145 #define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ 146 #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ 147 148 #define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ 149 #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ 150 151 #define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ 152 #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ 153 154 #define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ 155 #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ 156 157 #define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ 158 #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ 159 160 #define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ 161 #define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ 162 163 #define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ 164 #define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ 165 166 #define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ 167 #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ 168 169 #define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ 170 #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ 171 172 #define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ 173 #define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ 174 175 /**@}*/ /* WDT_CONST */ 176 /**@}*/ /* end of WDT register group */ 177 /**@}*/ /* end of REGISTER group */ 178 179 #if defined ( __CC_ARM ) 180 #pragma no_anon_unions 181 #endif 182 183 #endif /* __WDT_REG_H__ */ 184
