1 /**************************************************************************//** 2 * @file usbd_reg.h 3 * @version V1.00 4 * @brief USBD register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __USBD_REG_H__ 10 #define __USBD_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup USBD USB Device Controller(USBD) 23 Memory Mapped Structure for USBD Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 /** 30 * @var USBD_EP_T::BUFSEG 31 * Offset: 0x000 Endpoint n Buffer Segmentation Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[8:3] |BUFSEG |Endpoint Buffer Segmentation 36 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is 37 * | | |USBD_SRAM address + { BUFSEG, 3'b000} 38 * | | |Where the USBD_SRAM address = USBD_BA+0x100h. 39 * | | |Refer to the section 7.29.5.7 for the endpoint SRAM structure and its description. 40 * @var USBD_EP_T::MXPLD 41 * Offset: 0x004 Endpoint n Maximal Payload Register 42 * --------------------------------------------------------------------------------------------------- 43 * |Bits |Field |Descriptions 44 * | :----: | :----: | :---- | 45 * |[8:0] |MXPLD |Maximal Payload 46 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) 47 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. 48 * | | |(1) When the register is written by CPU, 49 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. 50 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. 51 * | | |(2) When the register is read by CPU, 52 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host 53 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. 54 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 55 * @var USBD_EP_T::CFG 56 * Offset: 0x008 Endpoint n Configuration Register 57 * --------------------------------------------------------------------------------------------------- 58 * |Bits |Field |Descriptions 59 * | :----: | :----: | :---- | 60 * |[3:0] |EPNUM |Endpoint Number 61 * | | |These bits are used to define the endpoint number of the current endpoint 62 * |[4] |ISOCH |Isochronous Endpoint 63 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. 64 * | | |0 = No Isochronous endpoint. 65 * | | |1 = Isochronous endpoint. 66 * |[6:5] |STATE |Endpoint STATE 67 * | | |00 = Endpoint is Disabled. 68 * | | |01 = Out endpoint. 69 * | | |10 = IN endpoint. 70 * | | |11 = Undefined. 71 * |[7] |DSQSYNC |Data Sequence Synchronization 72 * | | |0 = DATA0 PID. 73 * | | |1 = DATA1 PID. 74 * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction 75 * | | |hardware will toggle automatically in IN token base on the bit. 76 * |[9] |CSTALL |Clear STALL Response 77 * | | |0 = Disable the device to clear the STALL handshake in setup stage. 78 * | | |1 = Clear the device to response STALL handshake in setup stage. 79 * @var USBD_EP_T::CFGP 80 * Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register 81 * --------------------------------------------------------------------------------------------------- 82 * |Bits |Field |Descriptions 83 * | :----: | :----: | :---- | 84 * |[0] |CLRRDY |Clear Ready 85 * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data 86 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0. 87 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. 88 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. 89 * | | |This bit is write 1 only and is always 0 when it is read back. 90 * |[1] |SSTALL |Set STALL 91 * | | |0 = Disable the device to response STALL. 92 * | | |1 = Set the device to respond STALL automatically. 93 */ 94 __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint n Buffer Segmentation Register */ 95 __IO uint32_t MXPLD; /*!< [0x0004] Endpoint n Maximal Payload Register */ 96 __IO uint32_t CFG; /*!< [0x0008] Endpoint n Configuration Register */ 97 __IO uint32_t CFGP; /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register */ 98 99 } USBD_EP_T; 100 101 typedef struct 102 { 103 104 105 /** 106 * @var USBD_T::INTEN 107 * Offset: 0x00 USB Device Interrupt Enable Register 108 * --------------------------------------------------------------------------------------------------- 109 * |Bits |Field |Descriptions 110 * | :----: | :----: | :---- | 111 * |[0] |BUSIEN |Bus Event Interrupt Enable Bit 112 * | | |0 = BUS event interrupt Disabled. 113 * | | |1 = BUS event interrupt Enabled. 114 * |[1] |USBIEN |USB Event Interrupt Enable Bit 115 * | | |0 = USB event interrupt Disabled. 116 * | | |1 = USB event interrupt Enabled. 117 * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit 118 * | | |0 = VBUS detection Interrupt Disabled. 119 * | | |1 = VBUS detection Interrupt Enabled. 120 * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit 121 * | | |0 = No-event-wake-up Interrupt Disabled. 122 * | | |1 = No-event-wake-up Interrupt Enabled. 123 * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit 124 * | | |0 = SOF Interrupt Disabled. 125 * | | |1 = SOF Interrupt Enabled. 126 * |[8] |WKEN |Wake-up Function Enable Bit 127 * | | |0 = USB wake-up function Disabled. 128 * | | |1 = USB wake-up function Enabled. 129 * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token 130 * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted. 131 * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token. 132 * @var USBD_T::INTSTS 133 * Offset: 0x04 USB Device Interrupt Event Status Register 134 * --------------------------------------------------------------------------------------------------- 135 * |Bits |Field |Descriptions 136 * | :----: | :----: | :---- | 137 * |[0] |BUSIF |BUS Interrupt Status 138 * | | |The BUS event means that there is one of the suspense or the resume function in the bus. 139 * | | |0 = No BUS event occurred. 140 * | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0]. 141 * |[1] |USBIF |USB Event Interrupt Status 142 * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. 143 * | | |0 = No USB event occurred. 144 * | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]). 145 * |[2] |VBDETIF |VBUS Detection Interrupt Status 146 * | | |0 = There is not attached/detached event in the USB. 147 * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2]. 148 * |[3] |NEVWKIF |No-event-wake-up Interrupt Status 149 * | | |0 = NEVWK event does not occur. 150 * | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3]. 151 * |[4] |SOFIF |Start of Frame Interrupt Status 152 * | | |0 = SOF event does not occur. 153 * | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4]. 154 * |[16] |EPEVT0 |Endpoint 0's USB Event Status 155 * | | |0 = No event occurred in endpoint 0. 156 * | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1]. 157 * |[17] |EPEVT1 |Endpoint 1's USB Event Status 158 * | | |0 = No event occurred in endpoint 1. 159 * | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1]. 160 * |[18] |EPEVT2 |Endpoint 2's USB Event Status 161 * | | |0 = No event occurred in endpoint 2. 162 * | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1]. 163 * |[19] |EPEVT3 |Endpoint 3's USB Event Status 164 * | | |0 = No event occurred in endpoint 3. 165 * | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1]. 166 * |[20] |EPEVT4 |Endpoint 4's USB Event Status 167 * | | |0 = No event occurred in endpoint 4. 168 * | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1]. 169 * |[21] |EPEVT5 |Endpoint 5's USB Event Status 170 * | | |0 = No event occurred in endpoint 5. 171 * | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1]. 172 * |[22] |EPEVT6 |Endpoint 6's USB Event Status 173 * | | |0 = No event occurred in endpoint 6. 174 * | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1]. 175 * |[23] |EPEVT7 |Endpoint 7's USB Event Status 176 * | | |0 = No event occurred in endpoint 7. 177 * | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1]. 178 * |[24] |EPEVT8 |Endpoint 8's USB Event Status 179 * | | |0 = No event occurred in endpoint 8. 180 * | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1]. 181 * |[25] |EPEVT9 |Endpoint 9's USB Event Status 182 * | | |0 = No event occurred in endpoint 9. 183 * | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1]. 184 * |[26] |EPEVT10 |Endpoint 10's USB Event Status 185 * | | |0 = No event occurred in endpoint 10. 186 * | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1]. 187 * |[27] |EPEVT11 |Endpoint 11's USB Event Status 188 * | | |0 = No event occurred in endpoint 11. 189 * | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1]. 190 * |[31] |SETUP |Setup Event Status 191 * | | |0 = No Setup event. 192 * | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31]. 193 * @var USBD_T::FADDR 194 * Offset: 0x08 USB Device Function Address Register 195 * --------------------------------------------------------------------------------------------------- 196 * |Bits |Field |Descriptions 197 * | :----: | :----: | :---- | 198 * |[6:0] |FADDR |USB Device Function Address 199 * @var USBD_T::EPSTS 200 * Offset: 0x0C USB Device Endpoint Status Register 201 * --------------------------------------------------------------------------------------------------- 202 * |Bits |Field |Descriptions 203 * | :----: | :----: | :---- | 204 * |[7] |OV |Overrun 205 * | | |It indicates that the received data is over the maximum payload number or not. 206 * | | |0 = No overrun. 207 * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes. 208 * @var USBD_T::ATTR 209 * Offset: 0x10 USB Device Bus Status and Attribution Register 210 * --------------------------------------------------------------------------------------------------- 211 * |Bits |Field |Descriptions 212 * | :----: | :----: | :---- | 213 * |[0] |USBRST |USB Reset Status 214 * | | |0 = Bus no reset. 215 * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us. 216 * | | |Note: This bit is read only. 217 * |[1] |SUSPEND |Suspend Status 218 * | | |0 = Bus no suspend. 219 * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping. 220 * | | |Note: This bit is read only. 221 * |[2] |RESUME |Resume Status 222 * | | |0 = No bus resume. 223 * | | |1 = Resume from suspend. 224 * | | |Note: This bit is read only. 225 * |[3] |TOUT |Time-out Status 226 * | | |0 = No time-out. 227 * | | |1 = No Bus response more than 18 bits time. 228 * | | |Note: This bit is read only. 229 * |[4] |PHYEN |PHY Transceiver Function Enable Bit 230 * | | |0 = PHY transceiver function Disabled. 231 * | | |1 = PHY transceiver function Enabled. 232 * |[5] |RWAKEUP |Remote Wake-up 233 * | | |0 = Release the USB bus from K state. 234 * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up. 235 * |[7] |USBEN |USB Controller Enable Bit 236 * | | |0 = USB Controller Disabled. 237 * | | |1 = USB Controller Enabled. 238 * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit 239 * | | |0 = Pull-up resistor in USB_D+ bus Disabled. 240 * | | |1 = Pull-up resistor in USB_D+ bus Active. 241 * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection 242 * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. 243 * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. 244 * |[11] |LPMACK |LPM Token Acknowledge Enable Bit 245 * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively. 246 * | | |0= the valid LPM Token will be NYET. 247 * | | |1= the valid LPM Token will be ACK. 248 * |[12] |L1SUSPEND |LPM L1 Suspend 249 * | | |0 = Bus no L1 state suspend. 250 * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. 251 * | | |Note: This bit is read only. 252 * |[13] |L1RESUME |LPM L1 Resume 253 * | | |0 = Bus no LPM L1 state resume. 254 * | | |1 = LPM L1 state Resume from LPM L1 state suspend. 255 * | | |Note: This bit is read only. 256 * @var USBD_T::VBUSDET 257 * Offset: 0x14 USB Device VBUS Detection Register 258 * --------------------------------------------------------------------------------------------------- 259 * |Bits |Field |Descriptions 260 * | :----: | :----: | :---- | 261 * |[0] |VBUSDET |Device VBUS Detection 262 * | | |0 = Controller is not attached to the USB host. 263 * | | |1 = Controller is attached to the USB host. 264 * @var USBD_T::STBUFSEG 265 * Offset: 0x18 SETUP Token Buffer Segmentation Register 266 * --------------------------------------------------------------------------------------------------- 267 * |Bits |Field |Descriptions 268 * | :----: | :----: | :---- | 269 * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation 270 * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is 271 * | | |USBD_SRAM address + {STBUFSEG, 3'b000} 272 * | | |Where the USBD_SRAM address = USBD_BA+0x100h. 273 * | | |Note: It is used for SETUP token only. 274 * @var USBD_T::EPSTS0 275 * Offset: 0x20 USB Device Endpoint Status Register 0 276 * --------------------------------------------------------------------------------------------------- 277 * |Bits |Field |Descriptions 278 * | :----: | :----: | :---- | 279 * |[03:00] |EPSTS0 |Endpoint 0 Status 280 * | | |These bits are used to indicate the current status of this endpoint 281 * | | |0000 = In ACK. 282 * | | |0001 = In NAK. 283 * | | |0010 = Out Packet Data0 ACK. 284 * | | |0011 = Setup ACK. 285 * | | |0110 = Out Packet Data1 ACK. 286 * | | |0111 = Isochronous transfer end. 287 * |[07:04] |EPSTS1 |Endpoint 1 Status 288 * | | |These bits are used to indicate the current status of this endpoint 289 * | | |0000 = In ACK. 290 * | | |0001 = In NAK. 291 * | | |0010 = Out Packet Data0 ACK. 292 * | | |0011 = Setup ACK. 293 * | | |0110 = Out Packet Data1 ACK. 294 * | | |0111 = Isochronous transfer end. 295 * |[11:08] |EPSTS2 |Endpoint 2 Status 296 * | | |These bits are used to indicate the current status of this endpoint 297 * | | |0000 = In ACK. 298 * | | |0001 = In NAK. 299 * | | |0010 = Out Packet Data0 ACK. 300 * | | |0011 = Setup ACK. 301 * | | |0110 = Out Packet Data1 ACK. 302 * | | |0111 = Isochronous transfer end. 303 * |[15:12] |EPSTS3 |Endpoint 3 Status 304 * | | |These bits are used to indicate the current status of this endpoint 305 * | | |0000 = In ACK. 306 * | | |0001 = In NAK. 307 * | | |0010 = Out Packet Data0 ACK. 308 * | | |0011 = Setup ACK. 309 * | | |0110 = Out Packet Data1 ACK. 310 * | | |0111 = Isochronous transfer end. 311 * |[19:16] |EPSTS4 |Endpoint 4 Status 312 * | | |These bits are used to indicate the current status of this endpoint 313 * | | |0000 = In ACK. 314 * | | |0001 = In NAK. 315 * | | |0010 = Out Packet Data0 ACK. 316 * | | |0011 = Setup ACK. 317 * | | |0110 = Out Packet Data1 ACK. 318 * | | |0111 = Isochronous transfer end. 319 * |[23:20] |EPSTS5 |Endpoint 5 Status 320 * | | |These bits are used to indicate the current status of this endpoint 321 * | | |0000 = In ACK. 322 * | | |0001 = In NAK. 323 * | | |0010 = Out Packet Data0 ACK. 324 * | | |0011 = Setup ACK. 325 * | | |0110 = Out Packet Data1 ACK. 326 * | | |0111 = Isochronous transfer end. 327 * |[27:24] |EPSTS6 |Endpoint 6 Status 328 * | | |These bits are used to indicate the current status of this endpoint 329 * | | |0000 = In ACK. 330 * | | |0001 = In NAK. 331 * | | |0010 = Out Packet Data0 ACK. 332 * | | |0011 = Setup ACK. 333 * | | |0110 = Out Packet Data1 ACK. 334 * | | |0111 = Isochronous transfer end. 335 * |[31:28] |EPSTS7 |Endpoint 7 Status 336 * | | |These bits are used to indicate the current status of this endpoint 337 * | | |0000 = In ACK. 338 * | | |0001 = In NAK. 339 * | | |0010 = Out Packet Data0 ACK. 340 * | | |0011 = Setup ACK. 341 * | | |0110 = Out Packet Data1 ACK. 342 * | | |0111 = Isochronous transfer end. 343 * @var USBD_T::EPSTS1 344 * Offset: 0x24 USB Device Endpoint Status Register 1 345 * --------------------------------------------------------------------------------------------------- 346 * |Bits |Field |Descriptions 347 * | :----: | :----: | :---- | 348 * |[3:0] |EPSTS8 |Endpoint 8 Status 349 * | | |These bits are used to indicate the current status of this endpoint 350 * | | |0000 = In ACK. 351 * | | |0001 = In NAK. 352 * | | |0010 = Out Packet Data0 ACK. 353 * | | |0011 = Setup ACK. 354 * | | |0110 = Out Packet Data1 ACK. 355 * | | |0111 = Isochronous transfer end. 356 * |[7:4] |EPSTS9 |Endpoint 9 Status 357 * | | |These bits are used to indicate the current status of this endpoint 358 * | | |0000 = In ACK. 359 * | | |0001 = In NAK. 360 * | | |0010 = Out Packet Data0 ACK. 361 * | | |0011 = Setup ACK. 362 * | | |0110 = Out Packet Data1 ACK. 363 * | | |0111 = Isochronous transfer end. 364 * |[11:8] |EPSTS10 |Endpoint 10 Status 365 * | | |These bits are used to indicate the current status of this endpoint 366 * | | |0000 = In ACK. 367 * | | |0001 = In NAK. 368 * | | |0010 = Out Packet Data0 ACK. 369 * | | |0011 = Setup ACK. 370 * | | |0110 = Out Packet Data1 ACK. 371 * | | |0111 = Isochronous transfer end. 372 * |[15:12] |EPSTS11 |Endpoint 11 Status 373 * | | |These bits are used to indicate the current status of this endpoint 374 * | | |0000 = In ACK. 375 * | | |0001 = In NAK. 376 * | | |0010 = Out Packet Data0 ACK. 377 * | | |0011 = Setup ACK. 378 * | | |0110 = Out Packet Data1 ACK. 379 * | | |0111 = Isochronous transfer end. 380 * @var USBD_T::LPMATTR 381 * Offset: 0x88 USB LPM Attribution Register 382 * --------------------------------------------------------------------------------------------------- 383 * |Bits |Field |Descriptions 384 * | :----: | :----: | :---- | 385 * |[3:0] |LPMLINKSTS|LPM Link State 386 * | | |These bits contain the bLinkState received with last ACK LPM Token 387 * |[7:4] |LPMBESL |LPM Best Effort Service Latency 388 * | | |These bits contain the BESL value received with last ACK LPM Token 389 * |[8] |LPMRWAKUP |LPM Remote Wakeup 390 * | | |This bit contains the bRemoteWake value received with last ACK LPM Token 391 * @var USBD_T::FN 392 * Offset: 0x8C USB Frame number Register 393 * --------------------------------------------------------------------------------------------------- 394 * |Bits |Field |Descriptions 395 * | :----: | :----: | :---- | 396 * |[10:0] |FN |Frame Number 397 * | | |These bits contain the 11-bits frame number in the last received SOF packet. 398 * @var USBD_T::SE0 399 * Offset: 0x90 USB Device Drive SE0 Control Register 400 * --------------------------------------------------------------------------------------------------- 401 * |Bits |Field |Descriptions 402 * | :----: | :----: | :---- | 403 * |[0] |SE0 |Drive Single Ended Zero in USB Bus 404 * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. 405 * | | |0 = Normal operation. 406 * | | |1 = Force USB PHY transceiver to drive SE0. 407 */ 408 409 __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */ 410 __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */ 411 __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */ 412 __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */ 413 __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */ 414 __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */ 415 __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */ 416 /// @cond HIDDEN_SYMBOLS 417 __I uint32_t RESERVE0[1]; 418 /// @endcond //HIDDEN_SYMBOLS 419 __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */ 420 __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */ 421 /// @cond HIDDEN_SYMBOLS 422 __I uint32_t RESERVE1[24]; 423 /// @endcond //HIDDEN_SYMBOLS 424 __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */ 425 __I uint32_t FN; /*!< [0x008c] USB Frame number Register */ 426 __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */ 427 /// @cond HIDDEN_SYMBOLS 428 __I uint32_t RESERVE2[283]; 429 /// @endcond //HIDDEN_SYMBOLS 430 USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */ 431 432 } USBD_T; 433 434 435 /** 436 @addtogroup USBD_CONST USBD Bit Field Definition 437 Constant Definitions for USBD Controller 438 @{ */ 439 440 #define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */ 441 #define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */ 442 443 #define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */ 444 #define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */ 445 446 #define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */ 447 #define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */ 448 449 #define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */ 450 #define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */ 451 452 #define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */ 453 #define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */ 454 455 #define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */ 456 #define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */ 457 458 #define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */ 459 #define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */ 460 461 #define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */ 462 #define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */ 463 464 #define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */ 465 #define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */ 466 467 #define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */ 468 #define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */ 469 470 #define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */ 471 #define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */ 472 473 #define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */ 474 #define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */ 475 476 #define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */ 477 #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */ 478 479 #define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */ 480 #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */ 481 482 #define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */ 483 #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */ 484 485 #define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */ 486 #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */ 487 488 #define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */ 489 #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */ 490 491 #define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */ 492 #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */ 493 494 #define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */ 495 #define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */ 496 497 #define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */ 498 #define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */ 499 500 #define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */ 501 #define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */ 502 503 #define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */ 504 #define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */ 505 506 #define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */ 507 #define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */ 508 509 #define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */ 510 #define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */ 511 512 #define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */ 513 #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ 514 515 #define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */ 516 #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ 517 518 #define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */ 519 #define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */ 520 521 #define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */ 522 #define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ 523 524 #define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */ 525 #define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ 526 527 #define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */ 528 #define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ 529 530 #define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */ 531 #define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */ 532 533 #define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */ 534 #define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */ 535 536 #define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */ 537 #define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ 538 539 #define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */ 540 #define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */ 541 542 #define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */ 543 #define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */ 544 545 #define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */ 546 #define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ 547 548 #define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */ 549 #define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */ 550 551 #define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */ 552 #define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */ 553 554 #define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */ 555 #define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */ 556 557 #define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */ 558 #define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */ 559 560 #define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */ 561 #define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ 562 563 #define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */ 564 #define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */ 565 566 #define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */ 567 #define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */ 568 569 #define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */ 570 #define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */ 571 572 #define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */ 573 #define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */ 574 575 #define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */ 576 #define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */ 577 578 #define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */ 579 #define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */ 580 581 #define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */ 582 #define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */ 583 584 #define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */ 585 #define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */ 586 587 #define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */ 588 #define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */ 589 590 #define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */ 591 #define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */ 592 593 #define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */ 594 #define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */ 595 596 #define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */ 597 #define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */ 598 599 #define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */ 600 #define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */ 601 602 #define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */ 603 #define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */ 604 605 #define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */ 606 #define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */ 607 608 #define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */ 609 #define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */ 610 611 #define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */ 612 #define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */ 613 614 #define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ 615 #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ 616 617 #define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */ 618 #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ 619 620 #define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */ 621 #define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */ 622 623 #define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */ 624 #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ 625 626 #define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */ 627 #define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ 628 629 #define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */ 630 #define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */ 631 632 #define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */ 633 #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ 634 635 #define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */ 636 #define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ 637 638 #define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */ 639 #define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ 640 641 /**@}*/ /* USBD_CONST */ 642 /**@}*/ /* end of USBD register group */ 643 /**@}*/ /* end of REGISTER group */ 644 645 #if defined ( __CC_ARM ) 646 #pragma no_anon_unions 647 #endif 648 649 #endif /* __USBD_REG_H__ */ 650
