1 /*
2 * Copyright (c) 2021 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRFY_QDEC_H__
35 #define NRFY_QDEC_H__
36
37 #include <nrfx.h>
38 #include <hal/nrf_qdec.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 NRFY_STATIC_INLINE void __nrfy_internal_qdec_event_enabled_clear(NRF_QDEC_Type * p_reg,
45 uint32_t mask,
46 nrf_qdec_event_t event);
47
48 NRFY_STATIC_INLINE bool __nrfy_internal_qdec_event_handle(NRF_QDEC_Type * p_reg,
49 uint32_t mask,
50 nrf_qdec_event_t event,
51 uint32_t * p_evt_mask);
52
53 NRFY_STATIC_INLINE uint32_t __nrfy_internal_qdec_events_process(NRF_QDEC_Type * p_reg,
54 uint32_t mask);
55
56 /**
57 * @defgroup nrfy_qdec QDEC HALY
58 * @{
59 * @ingroup nrf_qdec
60 * @brief Hardware access layer with cache and barrier support for managing the QDEC peripheral.
61 */
62
63 /** @brief Configuration structure for QDEC pins. */
64 typedef struct
65 {
66 uint32_t a_pin; /**< Pin number for A input. */
67 uint32_t b_pin; /**< Pin number for B input. */
68 uint32_t led_pin; /**< Pin number for LED output. */
69 } nrfy_qdec_pins_t;
70
71 /** @brief QDEC configuration structure. */
72 typedef struct
73 {
74 nrf_qdec_reportper_t reportper; /**< Report period in samples. */
75 nrf_qdec_sampleper_t sampleper; /**< Sampling period in microseconds. */
76 nrfy_qdec_pins_t pins; /**< Pin configuration structure. */
77 uint32_t ledpre; /**< Time (in microseconds) how long LED is switched on before sampling. */
78 nrf_qdec_ledpol_t ledpol; /**< Active LED polarity. */
79 bool dbfen; /**< State of debouncing filter. */
80 bool skip_psel_cfg; /**< Skip pin selection configuration.
81 When set to true, the driver does not modify
82 pin select registers in the peripheral.
83 Those registers are supposed to be set up
84 externally before the driver is initialized.
85 @note When both GPIO configuration and pin
86 selection are to be skipped, the structure
87 fields that specify pins can be omitted,
88 as they are ignored anyway. */
89 } nrfy_qdec_config_t;
90
91 /**
92 * @brief Function for configuring the QDEC.
93 *
94 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
95 * @param[in] p_config Pointer to the peripheral configuration structure.
96 */
nrfy_qdec_periph_configure(NRF_QDEC_Type * p_reg,nrfy_qdec_config_t const * p_config)97 NRFY_STATIC_INLINE void nrfy_qdec_periph_configure(NRF_QDEC_Type * p_reg,
98 nrfy_qdec_config_t const * p_config)
99 {
100 nrf_qdec_sampleper_set(p_reg, p_config->sampleper);
101 nrf_qdec_reportper_set(p_reg, p_config->reportper);
102
103 if (p_config->pins.led_pin != NRF_QDEC_PIN_NOT_CONNECTED)
104 {
105 nrf_qdec_ledpre_set(p_reg, p_config->ledpre);
106 nrf_qdec_ledpol_set(p_reg, p_config->ledpol);
107 }
108 else
109 {
110 nrf_qdec_ledpre_set(p_reg, NRF_QDEC_LEDPRE_DEFAULT);
111 }
112
113 if (!p_config->skip_psel_cfg)
114 {
115 nrf_qdec_pins_set(p_reg,
116 p_config->pins.a_pin,
117 p_config->pins.b_pin,
118 p_config->pins.led_pin);
119 }
120
121 if (p_config->dbfen)
122 {
123 nrf_qdec_dbfen_enable(p_reg);
124 }
125 else
126 {
127 nrf_qdec_dbfen_disable(p_reg);
128 }
129
130 nrf_barrier_w();
131 }
132
133 /**
134 * @brief Function for initializing the specified QDEC interrupts.
135 *
136 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
137 * @param[in] mask Mask of interrupts to be initialized.
138 * @param[in] irq_priority Interrupt priority.
139 * @param[in] enable True if the interrupts are to be enabled, false otherwise.
140 */
nrfy_qdec_int_init(NRF_QDEC_Type * p_reg,uint32_t mask,uint8_t irq_priority,bool enable)141 NRFY_STATIC_INLINE void nrfy_qdec_int_init(NRF_QDEC_Type * p_reg,
142 uint32_t mask,
143 uint8_t irq_priority,
144 bool enable)
145 {
146 __nrfy_internal_qdec_event_enabled_clear(p_reg, mask, NRF_QDEC_EVENT_SAMPLERDY);
147 __nrfy_internal_qdec_event_enabled_clear(p_reg, mask, NRF_QDEC_EVENT_REPORTRDY);
148 __nrfy_internal_qdec_event_enabled_clear(p_reg, mask, NRF_QDEC_EVENT_ACCOF);
149 #if NRF_QDEC_HAS_EVENT_DBLRDY
150 __nrfy_internal_qdec_event_enabled_clear(p_reg, mask, NRF_QDEC_EVENT_DBLRDY);
151 #endif
152 #if NRF_QDEC_HAS_EVENT_STOPPED
153 __nrfy_internal_qdec_event_enabled_clear(p_reg, mask, NRF_QDEC_EVENT_STOPPED);
154 #endif
155
156 nrf_barrier_w();
157
158 NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_reg), irq_priority);
159 NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_reg));
160
161 if (enable)
162 {
163 nrf_qdec_int_enable(p_reg, mask);
164 }
165
166 nrf_barrier_w();
167 }
168
169 /**
170 * @brief Function for uninitializing the QDEC interrupts.
171 *
172 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
173 */
nrfy_qdec_int_uninit(NRF_QDEC_Type * p_reg)174 NRFY_STATIC_INLINE void nrfy_qdec_int_uninit(NRF_QDEC_Type * p_reg)
175 {
176 NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_reg));
177 nrf_barrier_w();
178 }
179
180 /**
181 * @brief Function for processing the specified QDEC events.
182 *
183 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
184 * @param[in] mask Mask of events to be processed, created by @ref NRFY_EVENT_TO_INT_BITMASK().
185 *
186 * @return Mask of events that were generated and processed.
187 * To be checked against the result of @ref NRFY_EVENT_TO_INT_BITMASK().
188 */
nrfy_qdec_events_process(NRF_QDEC_Type * p_reg,uint32_t mask)189 NRFY_STATIC_INLINE uint32_t nrfy_qdec_events_process(NRF_QDEC_Type * p_reg,
190 uint32_t mask)
191 {
192 uint32_t evt_mask = __nrfy_internal_qdec_events_process(p_reg, mask);
193 nrf_barrier_w();
194 return evt_mask;
195 }
196
197 /**
198 * @brief Function for reading QDEC accumulators.
199 *
200 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
201 * @param[in] p_acc Pointer to store the accumulated transitions
202 * @param[in] p_accdbl Pointer to store the accumulated double transitions.
203 */
nrfy_qdec_accumulators_read(NRF_QDEC_Type const * p_reg,int32_t * p_acc,uint32_t * p_accdbl)204 NRFY_STATIC_INLINE void nrfy_qdec_accumulators_read(NRF_QDEC_Type const * p_reg,
205 int32_t * p_acc,
206 uint32_t * p_accdbl)
207 {
208 nrf_barrier_r();
209 *p_acc = nrf_qdec_accread_get(p_reg);
210 *p_accdbl = nrf_qdec_accdblread_get(p_reg);
211 nrf_barrier_r();
212 }
213
214 /**
215 * @brief Function for reading QDEC pins.
216 *
217 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
218 * @param[in] p_pins Pointer to the QDEC pin configurartion structure.
219 */
nrfy_qdec_pins_get(NRF_QDEC_Type const * p_reg,nrfy_qdec_pins_t * p_pins)220 NRFY_STATIC_INLINE void nrfy_qdec_pins_get(NRF_QDEC_Type const * p_reg,
221 nrfy_qdec_pins_t * p_pins)
222 {
223 nrf_barrier_rw();
224 p_pins->a_pin = nrf_qdec_phase_a_pin_get(p_reg);
225 p_pins->b_pin = nrf_qdec_phase_b_pin_get(p_reg);
226 p_pins->led_pin = nrf_qdec_led_pin_get(p_reg);
227 nrf_barrier_r();
228 }
229
230 /**
231 * @brief Function for setting QDEC pins.
232 *
233 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
234 * @param[in] p_pins Pointer to the QDEC pin configurartion structure.
235 */
nrfy_qdec_pins_set(NRF_QDEC_Type * p_reg,nrfy_qdec_pins_t const * p_pins)236 NRFY_STATIC_INLINE void nrfy_qdec_pins_set(NRF_QDEC_Type * p_reg,
237 nrfy_qdec_pins_t const * p_pins)
238 {
239 nrf_qdec_pins_set(p_reg, p_pins->a_pin, p_pins->b_pin, p_pins->led_pin);
240 nrf_barrier_w();
241 }
242
243 /** @refhal{nrf_qdec_enable} */
nrfy_qdec_enable(NRF_QDEC_Type * p_reg)244 NRFY_STATIC_INLINE void nrfy_qdec_enable(NRF_QDEC_Type * p_reg)
245 {
246 nrf_qdec_enable(p_reg);
247 nrf_barrier_w();
248 }
249
250 /** @refhal{nrf_qdec_disable} */
nrfy_qdec_disable(NRF_QDEC_Type * p_reg)251 NRFY_STATIC_INLINE void nrfy_qdec_disable(NRF_QDEC_Type * p_reg)
252 {
253 nrf_qdec_disable(p_reg);
254 nrf_barrier_w();
255 }
256
257 /** @refhal{nrf_qdec_enable_get} */
nrfy_qdec_enable_get(NRF_QDEC_Type const * p_reg)258 NRFY_STATIC_INLINE uint32_t nrfy_qdec_enable_get(NRF_QDEC_Type const * p_reg)
259 {
260 nrf_barrier_rw();
261 uint32_t ret = nrf_qdec_enable_get(p_reg);
262 nrf_barrier_r();
263 return ret;
264 }
265
266 /** @refhal{nrf_qdec_int_enable} */
nrfy_qdec_int_enable(NRF_QDEC_Type * p_reg,uint32_t mask)267 NRFY_STATIC_INLINE void nrfy_qdec_int_enable(NRF_QDEC_Type * p_reg, uint32_t mask)
268 {
269 nrf_qdec_int_enable(p_reg, mask);
270 nrf_barrier_w();
271 }
272
273 /** @refhal{nrf_qdec_int_disable} */
nrfy_qdec_int_disable(NRF_QDEC_Type * p_reg,uint32_t mask)274 NRFY_STATIC_INLINE void nrfy_qdec_int_disable(NRF_QDEC_Type * p_reg, uint32_t mask)
275 {
276 nrf_qdec_int_disable(p_reg, mask);
277 nrf_barrier_w();
278 }
279
280 /** @refhal{nrf_qdec_int_enable_check} */
nrfy_qdec_int_enable_check(NRF_QDEC_Type const * p_reg,uint32_t mask)281 NRFY_STATIC_INLINE uint32_t nrfy_qdec_int_enable_check(NRF_QDEC_Type const * p_reg, uint32_t mask)
282 {
283 nrf_barrier_rw();
284 uint32_t ret = nrf_qdec_int_enable_check(p_reg, mask);
285 nrf_barrier_r();
286 return ret;
287 }
288
289 /** @refhal{nrf_qdec_dbfen_enable} */
nrfy_qdec_dbfen_enable(NRF_QDEC_Type * p_reg)290 NRFY_STATIC_INLINE void nrfy_qdec_dbfen_enable(NRF_QDEC_Type * p_reg)
291 {
292 nrf_qdec_dbfen_enable(p_reg);
293 nrf_barrier_w();
294 }
295
296 /** @refhal{nrf_qdec_dbfen_disable} */
nrfy_qdec_dbfen_disable(NRF_QDEC_Type * p_reg)297 NRFY_STATIC_INLINE void nrfy_qdec_dbfen_disable(NRF_QDEC_Type * p_reg)
298 {
299 nrf_qdec_dbfen_disable(p_reg);
300 nrf_barrier_w();
301 }
302
303 /** @refhal{nrf_qdec_dbfen_get} */
nrfy_qdec_dbfen_get(NRF_QDEC_Type const * p_reg)304 NRFY_STATIC_INLINE uint32_t nrfy_qdec_dbfen_get(NRF_QDEC_Type const * p_reg)
305 {
306 nrf_barrier_rw();
307 uint32_t ret = nrf_qdec_dbfen_get(p_reg);
308 nrf_barrier_r();
309 return ret;
310 }
311
312 /** @refhal{nrf_qdec_phase_a_pin_get} */
nrfy_qdec_a_pin_get(NRF_QDEC_Type const * p_reg)313 NRFY_STATIC_INLINE uint32_t nrfy_qdec_a_pin_get(NRF_QDEC_Type const * p_reg)
314 {
315 nrf_barrier_rw();
316 uint32_t ret = nrf_qdec_phase_a_pin_get(p_reg);
317 nrf_barrier_r();
318 return ret;
319 }
320
321 /** @refhal{nrf_qdec_phase_b_pin_get} */
nrfy_qdec_b_pin_get(NRF_QDEC_Type const * p_reg)322 NRFY_STATIC_INLINE uint32_t nrfy_qdec_b_pin_get(NRF_QDEC_Type const * p_reg)
323 {
324 nrf_barrier_rw();
325 uint32_t ret = nrf_qdec_phase_b_pin_get(p_reg);
326 nrf_barrier_r();
327 return ret;
328 }
329
330 /** @refhal{nrf_qdec_led_pin_get} */
nrfy_qdec_led_pin_get(NRF_QDEC_Type const * p_reg)331 NRFY_STATIC_INLINE uint32_t nrfy_qdec_led_pin_get(NRF_QDEC_Type const * p_reg)
332 {
333 nrf_barrier_rw();
334 uint32_t ret = nrf_qdec_led_pin_get(p_reg);
335 nrf_barrier_r();
336 return ret;
337 }
338
339 /** @refhal{nrf_qdec_task_trigger} */
nrfy_qdec_task_trigger(NRF_QDEC_Type * p_reg,nrf_qdec_task_t task)340 NRFY_STATIC_INLINE void nrfy_qdec_task_trigger(NRF_QDEC_Type * p_reg, nrf_qdec_task_t task)
341 {
342 nrf_qdec_task_trigger(p_reg, task);
343 nrf_barrier_w();
344 }
345
346 /** @refhal{nrf_qdec_task_address_get} */
nrfy_qdec_task_address_get(NRF_QDEC_Type const * p_reg,nrf_qdec_task_t task)347 NRFY_STATIC_INLINE uint32_t nrfy_qdec_task_address_get(NRF_QDEC_Type const * p_reg,
348 nrf_qdec_task_t task)
349 {
350 return nrf_qdec_task_address_get(p_reg, task);
351 }
352
353 /** @refhal{nrf_qdec_event_clear} */
nrfy_qdec_event_clear(NRF_QDEC_Type * p_reg,nrf_qdec_event_t event)354 NRFY_STATIC_INLINE void nrfy_qdec_event_clear(NRF_QDEC_Type * p_reg, nrf_qdec_event_t event)
355 {
356 nrf_qdec_event_clear(p_reg, event);
357 nrf_barrier_w();
358 }
359
360 /** @refhal{nrf_qdec_event_check} */
nrfy_qdec_event_check(NRF_QDEC_Type const * p_reg,nrf_qdec_event_t event)361 NRFY_STATIC_INLINE bool nrfy_qdec_event_check(NRF_QDEC_Type const * p_reg, nrf_qdec_event_t event)
362 {
363 nrf_barrier_rw();
364 bool ret = nrf_qdec_event_check(p_reg, event);
365 nrf_barrier_r();
366 return ret;
367 }
368
369 /** @refhal{nrf_qdec_event_address_get} */
nrfy_qdec_event_address_get(NRF_QDEC_Type const * p_reg,nrf_qdec_event_t event)370 NRFY_STATIC_INLINE uint32_t nrfy_qdec_event_address_get(NRF_QDEC_Type const * p_reg,
371 nrf_qdec_event_t event)
372 {
373 return nrf_qdec_event_address_get(p_reg, event);
374 }
375
376 /** @refhal{nrf_qdec_shorts_enable} */
nrfy_qdec_shorts_enable(NRF_QDEC_Type * p_reg,uint32_t mask)377 NRFY_STATIC_INLINE void nrfy_qdec_shorts_enable(NRF_QDEC_Type * p_reg, uint32_t mask)
378 {
379 nrf_qdec_shorts_enable(p_reg, mask);
380 nrf_barrier_w();
381 }
382
383 /** @refhal{nrf_qdec_shorts_disable} */
nrfy_qdec_shorts_disable(NRF_QDEC_Type * p_reg,uint32_t mask)384 NRFY_STATIC_INLINE void nrfy_qdec_shorts_disable(NRF_QDEC_Type * p_reg, uint32_t mask)
385 {
386 nrf_qdec_shorts_disable(p_reg, mask);
387 nrf_barrier_w();
388 }
389
390 /** @refhal{nrf_qdec_sampleper_to_value} */
nrfy_qdec_sampleper_to_value(nrf_qdec_sampleper_t sampleper)391 NRFY_STATIC_INLINE uint32_t nrfy_qdec_sampleper_to_value(nrf_qdec_sampleper_t sampleper)
392 {
393 return nrf_qdec_sampleper_to_value(sampleper);
394 }
395
396 /** @refhal{nrf_qdec_sampleper_set} */
nrfy_qdec_sampleper_set(NRF_QDEC_Type * p_reg,nrf_qdec_sampleper_t sampleper)397 NRFY_STATIC_INLINE void nrfy_qdec_sampleper_set(NRF_QDEC_Type * p_reg,
398 nrf_qdec_sampleper_t sampleper)
399 {
400 nrf_qdec_sampleper_set(p_reg, sampleper);
401 nrf_barrier_w();
402 }
403
404 /** @refhal{nrf_qdec_sampleper_get} */
nrfy_qdec_sampleper_get(NRF_QDEC_Type const * p_reg)405 NRFY_STATIC_INLINE nrf_qdec_sampleper_t nrfy_qdec_sampleper_get(NRF_QDEC_Type const * p_reg)
406 {
407 nrf_barrier_rw();
408 nrf_qdec_sampleper_t ret = nrf_qdec_sampleper_get(p_reg);
409 nrf_barrier_r();
410 return ret;
411 }
412
413 /** @refhal{nrf_qdec_sample_get} */
nrfy_qdec_sample_get(NRF_QDEC_Type const * p_reg)414 NRFY_STATIC_INLINE int32_t nrfy_qdec_sample_get(NRF_QDEC_Type const * p_reg)
415 {
416 nrf_barrier_rw();
417 int32_t ret = nrf_qdec_sample_get(p_reg);
418 nrf_barrier_r();
419 return ret;
420 }
421
422 /** @refhal{nrf_qdec_acc_get} */
nrfy_qdec_acc_get(NRF_QDEC_Type const * p_reg)423 NRFY_STATIC_INLINE int32_t nrfy_qdec_acc_get(NRF_QDEC_Type const * p_reg)
424 {
425 nrf_barrier_r();
426 int32_t ret = nrf_qdec_acc_get(p_reg);
427 nrf_barrier_r();
428 return ret;
429 }
430
431 /** @refhal{nrf_qdec_accread_get} */
nrfy_qdec_accread_get(NRF_QDEC_Type const * p_reg)432 NRFY_STATIC_INLINE int32_t nrfy_qdec_accread_get(NRF_QDEC_Type const * p_reg)
433 {
434 nrf_barrier_r();
435 int32_t ret = nrf_qdec_accread_get(p_reg);
436 nrf_barrier_r();
437 return ret;
438 }
439
440 /** @refhal{nrf_qdec_accdbl_get} */
nrfy_qdec_accdbl_get(NRF_QDEC_Type const * p_reg)441 NRFY_STATIC_INLINE uint32_t nrfy_qdec_accdbl_get(NRF_QDEC_Type const * p_reg)
442 {
443 nrf_barrier_r();
444 uint32_t ret = nrf_qdec_accdbl_get(p_reg);
445 nrf_barrier_r();
446 return ret;
447 }
448
449 /** @refhal{nrf_qdec_accdblread_get} */
nrfy_qdec_accdblread_get(NRF_QDEC_Type const * p_reg)450 NRFY_STATIC_INLINE uint32_t nrfy_qdec_accdblread_get(NRF_QDEC_Type const * p_reg)
451 {
452 nrf_barrier_r();
453 uint32_t ret = nrf_qdec_accdblread_get(p_reg);
454 nrf_barrier_r();
455 return ret;
456 }
457
458 /** @refhal{nrf_qdec_ledpre_set} */
nrfy_qdec_ledpre_set(NRF_QDEC_Type * p_reg,uint32_t time_us)459 NRFY_STATIC_INLINE void nrfy_qdec_ledpre_set(NRF_QDEC_Type * p_reg, uint32_t time_us)
460 {
461 nrf_qdec_ledpre_set(p_reg, time_us);
462 nrf_barrier_w();
463 }
464
465 /** @refhal{nrf_qdec_ledpre_get} */
nrfy_qdec_ledpre_get(NRF_QDEC_Type const * p_reg)466 NRFY_STATIC_INLINE uint32_t nrfy_qdec_ledpre_get(NRF_QDEC_Type const * p_reg)
467 {
468 nrf_barrier_rw();
469 uint32_t ret = nrf_qdec_ledpre_get(p_reg);
470 nrf_barrier_r();
471 return ret;
472 }
473
474 /** @refhal{nrf_qdec_ledpol_set} */
nrfy_qdec_ledpol_set(NRF_QDEC_Type * p_reg,nrf_qdec_ledpol_t pol)475 NRFY_STATIC_INLINE void nrfy_qdec_ledpol_set(NRF_QDEC_Type * p_reg, nrf_qdec_ledpol_t pol)
476 {
477 nrf_qdec_ledpol_set(p_reg, pol);
478 nrf_barrier_w();
479 }
480
481 /** @refhal{nrf_qdec_ledpol_get} */
nrfy_qdec_ledpol_get(NRF_QDEC_Type const * p_reg)482 NRFY_STATIC_INLINE uint32_t nrfy_qdec_ledpol_get(NRF_QDEC_Type const * p_reg)
483 {
484 nrf_barrier_rw();
485 uint32_t ret = nrf_qdec_ledpol_get(p_reg);
486 nrf_barrier_r();
487
488 return ret;
489 }
490
491 /** @refhal{nrf_qdec_reportper_set} */
nrfy_qdec_reportper_set(NRF_QDEC_Type * p_reg,nrf_qdec_reportper_t reportper)492 NRFY_STATIC_INLINE void nrfy_qdec_reportper_set(NRF_QDEC_Type * p_reg,
493 nrf_qdec_reportper_t reportper)
494 {
495 nrf_qdec_reportper_set(p_reg, reportper);
496 nrf_barrier_w();
497 }
498
499 /** @refhal{nrf_qdec_reportper_get} */
nrfy_qdec_reportper_get(NRF_QDEC_Type const * p_reg)500 NRFY_STATIC_INLINE nrf_qdec_reportper_t nrfy_qdec_reportper_get(NRF_QDEC_Type const * p_reg)
501 {
502 nrf_barrier_rw();
503 nrf_qdec_reportper_t ret = nrf_qdec_reportper_get(p_reg);
504 nrf_barrier_r();
505 return ret;
506 }
507
508 /** @refhal{nrf_qdec_reportper_to_value} */
nrfy_qdec_reportper_to_value(nrf_qdec_reportper_t reportper)509 NRFY_STATIC_INLINE uint32_t nrfy_qdec_reportper_to_value(nrf_qdec_reportper_t reportper)
510 {
511 return nrf_qdec_reportper_to_value(reportper);
512 }
513
514 /** @} */
515
__nrfy_internal_qdec_event_enabled_clear(NRF_QDEC_Type * p_reg,uint32_t mask,nrf_qdec_event_t event)516 NRFY_STATIC_INLINE void __nrfy_internal_qdec_event_enabled_clear(NRF_QDEC_Type * p_reg,
517 uint32_t mask,
518 nrf_qdec_event_t event)
519 {
520 if (mask & NRFY_EVENT_TO_INT_BITMASK(event))
521 {
522 nrf_qdec_event_clear(p_reg, event);
523 }
524 }
525
__nrfy_internal_qdec_event_handle(NRF_QDEC_Type * p_reg,uint32_t mask,nrf_qdec_event_t event,uint32_t * p_evt_mask)526 NRFY_STATIC_INLINE bool __nrfy_internal_qdec_event_handle(NRF_QDEC_Type * p_reg,
527 uint32_t mask,
528 nrf_qdec_event_t event,
529 uint32_t * p_evt_mask)
530 {
531 if ((mask & NRFY_EVENT_TO_INT_BITMASK(event)) && nrf_qdec_event_check(p_reg, event))
532 {
533 nrf_qdec_event_clear(p_reg, event);
534 if (p_evt_mask)
535 {
536 *p_evt_mask |= NRFY_EVENT_TO_INT_BITMASK(event);
537 }
538 return true;
539 }
540 return false;
541 }
542
__nrfy_internal_qdec_events_process(NRF_QDEC_Type * p_reg,uint32_t mask)543 NRFY_STATIC_INLINE uint32_t __nrfy_internal_qdec_events_process(NRF_QDEC_Type * p_reg,
544 uint32_t mask)
545 {
546 uint32_t event_mask = 0;
547
548 nrf_barrier_r();
549 (void)__nrfy_internal_qdec_event_handle(p_reg,
550 mask,
551 NRF_QDEC_EVENT_SAMPLERDY,
552 &event_mask);
553 (void)__nrfy_internal_qdec_event_handle(p_reg,
554 mask,
555 NRF_QDEC_EVENT_REPORTRDY,
556 &event_mask);
557 (void)__nrfy_internal_qdec_event_handle(p_reg,
558 mask,
559 NRF_QDEC_EVENT_ACCOF,
560 &event_mask);
561 #if NRF_QDEC_HAS_EVENT_DBLRDY
562 (void)__nrfy_internal_qdec_event_handle(p_reg,
563 mask,
564 NRF_QDEC_EVENT_DBLRDY,
565 &event_mask);
566 #endif
567 #if NRF_QDEC_HAS_EVENT_STOPPED
568 (void)__nrfy_internal_qdec_event_handle(p_reg,
569 mask,
570 NRF_QDEC_EVENT_STOPPED,
571 &event_mask);
572 #endif
573 return event_mask;
574 }
575
576 #ifdef __cplusplus
577 }
578 #endif
579
580 #endif // NRFY_QDEC_H__
581
