1 /*
2 * Copyright (c) 2023 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRFY_NFCT_H__
35 #define NRFY_NFCT_H__
36
37 #include <nrfx.h>
38 #include <hal/nrf_nfct.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 NRFY_STATIC_INLINE void __nrfy_internal_nfct_event_enabled_clear(NRF_NFCT_Type * p_reg,
45 uint32_t mask,
46 nrf_nfct_event_t event);
47
48 NRFY_STATIC_INLINE bool __nrfy_internal_nfct_event_handle(NRF_NFCT_Type * p_reg,
49 uint32_t mask,
50 nrf_nfct_event_t event,
51 uint32_t * p_evt_mask);
52
53 NRFY_STATIC_INLINE uint32_t __nrfy_internal_nfct_events_process(NRF_NFCT_Type * p_reg,
54 uint32_t mask);
55
56 /**
57 * @defgroup nrfy_nfct NFCT HALY
58 * @{
59 * @ingroup nrf_nfct
60 * @brief Hardware access layer with cache and barrier support for managing the NFCT peripheral.
61 */
62
63 #if NRF_NFCT_HAS_MODULATION_PSEL_REG || defined(__NRFX_DOXYGEN__)
64 /** @refhal{NRF_NFCT_HAS_MODULATION_PSEL_REG} */
65 #define NRFY_NFCT_HAS_MODULATION_PSEL_REG 1
66 #else
67 #define NRFY_NFCT_HAS_MODULATION_PSEL_REG 0
68 #endif
69
70 #if NRF_NFCT_HAS_MODULATION_CTRL_REG || defined(__NRFX_DOXYGEN__)
71 /** @refhal{NRF_NFCT_HAS_MODULATION_CTRL_REG} */
72 #define NRFY_NFCT_HAS_MODULATION_CTRL_REG 1
73 #else
74 #define NRFY_NFCT_HAS_MODULATION_CTRL_REG 0
75 #endif
76
77 #if NRF_NFCT_HAS_TAG_STATE_REG || defined(__NRFX_DOXYGEN__)
78 /** @refhal{NRF_NFCT_HAS_TAG_STATE_REG} */
79 #define NRFY_NFCT_HAS_TAG_STATE_REG 1
80 #else
81 #define NRFY_NFCT_HAS_TAG_STATE_REG 0
82 #endif
83
84 #if NRF_NFCT_HAS_SLEEP_STATE_REG || defined(__NRFX_DOXYGEN__)
85 /** @refhal{NRF_NFCT_HAS_SLEEP_STATE_REG} */
86 #define NRFY_NFCT_HAS_SLEEP_STATE_REG 1
87 #else
88 #define NRFY_NFCT_HAS_SLEEP_STATE_REG 0
89 #endif
90
91 #if NRF_NFCT_HAS_AUTOCOLRES_CONFIG_REG || defined(__NRFX_DOXYGEN__)
92 /** @refhal{NRF_NFCT_HAS_AUTOCOLRES_CONFIG_REG} */
93 #define NRFY_NFCT_HAS_AUTOCOLRES_CONFIG_REG 1
94 #else
95 #define NRFY_NFCT_HAS_AUTOCOLRES_CONFIG_REG 0
96 #endif
97
98 #if NRF_NFCT_HAS_PAD_CONFIG_REG || defined(__NRFX_DOXYGEN__)
99 /** @refhal{NRF_NFCT_HAS_PAD_CONFIG_REG} */
100 #define NRFY_NFCT_HAS_PAD_CONFIG_REG 1
101 #else
102 #define NRFY_NFCT_HAS_PAD_CONFIG_REG 0
103 #endif
104
105 #if NRF_NFCT_HAS_BIAS_CONFIG_TRIM_REG || defined(__NRFX_DOXYGEN__)
106 /** @refhal{NRF_NFCT_HAS_BIAS_CONFIG_TRIM_REG} */
107 #define NRFY_NFCT_HAS_BIAS_CONFIG_TRIM_REG 1
108 #else
109 #define NRFY_NFCT_HAS_BIAS_CONFIG_TRIM_REG 0
110 #endif
111
112 /** @brief NFCT parameters storage structure. */
113 typedef struct
114 {
115 uint32_t fdmax; ///< Frame delay max value.
116 uint32_t fdmin; ///< Frame delay min value.
117 uint32_t int_enabled; ///< Interrupts status.
118 uint8_t nfcid1[NRF_NFCT_SENSRES_NFCID1_SIZE_TRIPLE]; ///< NFCID1 value.
119 nrf_nfct_sensres_nfcid1_size_t nfcid1_size; ///< NFCID1 size.
120 nrf_nfct_selres_protocol_t protocol; ///< NFC protocol type.
121 } nrfy_nfct_parameters_t;
122
123 /**
124 * @brief Function for initializing the specified NFCT interrupts.
125 *
126 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
127 * @param[in] mask Mask of interrupts to be initialized.
128 * @param[in] irq_priority Interrupts priority.
129 * @param[in] enable True if interrupts associated with the event mask are to be enabled,
130 * false otherwise.
131 */
nrfy_nfct_int_init(NRF_NFCT_Type * p_reg,uint32_t mask,uint8_t irq_priority,bool enable)132 NRFY_STATIC_INLINE void nrfy_nfct_int_init(NRF_NFCT_Type * p_reg,
133 uint32_t mask,
134 uint8_t irq_priority,
135 bool enable)
136 {
137 IRQn_Type nfct_irq = nrfx_get_irq_number(p_reg);
138
139 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_READY);
140 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_FIELDDETECTED);
141 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_FIELDLOST);
142 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_TXFRAMESTART);
143 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_TXFRAMEEND);
144 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_RXFRAMESTART);
145 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_RXFRAMEEND);
146 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_ERROR);
147 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_RXERROR);
148 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_ENDRX);
149 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_ENDTX);
150 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_AUTOCOLRESSTARTED);
151 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_COLLISION);
152 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_SELECTED);
153 __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_STARTED);
154 nrf_barrier_w();
155
156 NRFY_IRQ_PENDING_CLEAR(nfct_irq);
157 nrf_barrier_w();
158
159 NRFY_IRQ_PRIORITY_SET(nfct_irq, irq_priority);
160 NRFY_IRQ_ENABLE(nfct_irq);
161
162 if (enable)
163 {
164 nrf_nfct_int_enable(p_reg, mask);
165 }
166
167 nrf_barrier_w();
168 }
169
170 /**
171 * @brief Function for un-initializing the NFCT interrupts.
172 *
173 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
174 */
nrfy_nfct_int_uninit(NRF_NFCT_Type * p_reg)175 NRFY_STATIC_INLINE void nrfy_nfct_int_uninit(NRF_NFCT_Type * p_reg)
176 {
177 IRQn_Type nfct_irq = nrfx_get_irq_number(p_reg);
178
179 NRFY_IRQ_DISABLE(nfct_irq);
180 nrf_barrier_w();
181 NRFY_IRQ_PENDING_CLEAR(nfct_irq);
182 nrf_barrier_w();
183 }
184
185 /**
186 * @brief Function for processing the specified NFCT events.
187 *
188 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
189 * @param[in] mask Mask of the events to be processed, created by the
190 * @ref NRFY_EVENT_TO_INT_BITMASK().
191 *
192 * @return Mask of the events that were generated and processed.
193 * To be checked against the result of the @ref NRFY_EVENT_TO_INT_BITMASK().
194 */
nrfy_nfct_events_process(NRF_NFCT_Type * p_reg,uint32_t mask)195 NRFY_STATIC_INLINE uint32_t nrfy_nfct_events_process(NRF_NFCT_Type * p_reg, uint32_t mask)
196 {
197 uint32_t evt_mask = __nrfy_internal_nfct_events_process(p_reg, mask);
198 nrf_barrier_w();
199 return evt_mask;
200 }
201
202 /**
203 * @brief Function for saving NFCT parameters before peripheral reset.
204 *
205 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
206 * @param[in] p_params Pointer to the structure where the parameters will be saved.
207 */
nrfy_nfct_parameters_save(NRF_NFCT_Type const * p_reg,nrfy_nfct_parameters_t * p_params)208 NRFY_STATIC_INLINE void nrfy_nfct_parameters_save(NRF_NFCT_Type const * p_reg,
209 nrfy_nfct_parameters_t * p_params)
210 {
211 nrf_barrier_rw();
212 p_params->fdmax = nrf_nfct_frame_delay_max_get(p_reg);
213 p_params->fdmin = nrf_nfct_frame_delay_min_get(p_reg);
214 p_params->nfcid1_size = nrf_nfct_nfcid1_get(p_reg, p_params->nfcid1);
215 p_params->protocol = nrf_nfct_selres_protocol_get(p_reg);
216 p_params->int_enabled = nrf_nfct_int_enable_get(p_reg);
217 nrf_barrier_r();
218 }
219
220 /**
221 * @brief Function for restoring NFCT parameters after peripheral reset. The parameters are
222 * written back to the peripheral registers.
223 *
224 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
225 * @param[in] p_params Pointer to the structure holding peripheral parameters to be restored.
226 */
nrfy_nfct_parameters_restore(NRF_NFCT_Type * p_reg,nrfy_nfct_parameters_t const * p_params)227 NRFY_STATIC_INLINE void nrfy_nfct_parameters_restore(NRF_NFCT_Type * p_reg,
228 nrfy_nfct_parameters_t const * p_params)
229 {
230 nrf_nfct_frame_delay_max_set(p_reg, p_params->fdmax);
231 nrf_nfct_frame_delay_min_set(p_reg, (uint16_t)p_params->fdmin);
232 nrf_nfct_nfcid1_set(p_reg, p_params->nfcid1, p_params->nfcid1_size);
233 nrf_nfct_selres_protocol_set(p_reg, p_params->protocol);
234
235 nrf_barrier_w();
236 }
237
238 /**
239 * @brief Function for setting the the NFCT RX/TX buffer (address and maximum length).
240 *
241 * @note Buffer for the NFC RX/TX data is used by EasyDMA and must be located in RAM.
242 *
243 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
244 * @param[in] p_rxtx_buf Pointer to the receive or transmit buffer.
245 * @param[in] max_txrx_len Maximum receive or transmit length in bytes
246 * (size of the RAM buffer for EasyDMA).
247 * @param[in] rx True if buffer is set for the frame reception, false if buffer is set for
248 * the frame transmission.
249 */
nrfy_nfct_rxtx_buffer_set(NRF_NFCT_Type * p_reg,uint8_t * p_rxtx_buf,uint16_t max_txrx_len,bool rx)250 NRFY_STATIC_INLINE void nrfy_nfct_rxtx_buffer_set(NRF_NFCT_Type * p_reg,
251 uint8_t * p_rxtx_buf,
252 uint16_t max_txrx_len,
253 bool rx)
254 {
255 if (p_rxtx_buf && !rx)
256 {
257 NRFY_CACHE_WB(p_rxtx_buf, max_txrx_len);
258 }
259
260 nrf_nfct_rxtx_buffer_set(p_reg, p_rxtx_buf, max_txrx_len);
261 nrf_barrier_w();
262 }
263
264 /** @refhal{nrf_nfct_task_trigger} */
nrfy_nfct_task_trigger(NRF_NFCT_Type * p_reg,nrf_nfct_task_t task)265 NRFY_STATIC_INLINE void nrfy_nfct_task_trigger(NRF_NFCT_Type * p_reg, nrf_nfct_task_t task)
266 {
267 nrf_nfct_task_trigger(p_reg, task);
268 nrf_barrier_w();
269 }
270
271 /** @refhal{nrf_nfct_task_address_get} */
nrfy_nfct_task_address_get(NRF_NFCT_Type const * p_reg,nrf_nfct_task_t task)272 NRFY_STATIC_INLINE uint32_t nrfy_nfct_task_address_get(NRF_NFCT_Type const * p_reg,
273 nrf_nfct_task_t task)
274 {
275 return nrf_nfct_task_address_get(p_reg, task);
276 }
277
278 /** @refhal{nrf_nfct_event_clear} */
nrfy_nfct_event_clear(NRF_NFCT_Type * p_reg,nrf_nfct_event_t event)279 NRFY_STATIC_INLINE void nrfy_nfct_event_clear(NRF_NFCT_Type * p_reg, nrf_nfct_event_t event)
280 {
281 nrf_nfct_event_clear(p_reg, event);
282 nrf_barrier_w();
283 }
284
285 /** @refhal{nrf_nfct_event_check} */
nrfy_nfct_event_check(NRF_NFCT_Type const * p_reg,nrf_nfct_event_t event)286 NRFY_STATIC_INLINE bool nrfy_nfct_event_check(NRF_NFCT_Type const * p_reg, nrf_nfct_event_t event)
287 {
288 nrf_barrier_rw();
289 bool check = nrf_nfct_event_check(p_reg, event);
290 nrf_barrier_r();
291 return check;
292 }
293
294 /** @refhal{nrf_nfct_shorts_enable} */
nrfy_nfct_shorts_enable(NRF_NFCT_Type * p_reg,uint32_t short_mask)295 NRFY_STATIC_INLINE void nrfy_nfct_shorts_enable(NRF_NFCT_Type * p_reg, uint32_t short_mask)
296 {
297 nrf_nfct_shorts_enable(p_reg, short_mask);
298 nrf_barrier_w();
299 }
300
301 /** @refhal{nrf_nfct_shorts_disable} */
nrfy_nfct_shorts_disable(NRF_NFCT_Type * p_reg,uint32_t short_mask)302 NRFY_STATIC_INLINE void nrfy_nfct_shorts_disable(NRF_NFCT_Type * p_reg, uint32_t short_mask)
303 {
304 nrf_nfct_shorts_disable(p_reg, short_mask);
305 nrf_barrier_w();
306 }
307
308 /** @refhal{nrf_nfct_shorts_get} */
nrfy_nfct_shorts_get(NRF_NFCT_Type const * p_reg)309 NRFY_STATIC_INLINE uint32_t nrfy_nfct_shorts_get(NRF_NFCT_Type const * p_reg)
310 {
311 nrf_barrier_rw();
312 uint32_t shorts = nrf_nfct_shorts_get(p_reg);
313 nrf_barrier_r();
314 return shorts;
315 }
316
317 /** @refhal{nrf_nfct_shorts_set} */
nrfy_nfct_shorts_set(NRF_NFCT_Type * p_reg,uint32_t short_mask)318 NRFY_STATIC_INLINE void nrfy_nfct_shorts_set(NRF_NFCT_Type * p_reg, uint32_t short_mask)
319 {
320 nrf_nfct_shorts_set(p_reg, short_mask);
321 nrf_barrier_w();
322 }
323
324 /** @refhal{nrf_nfct_int_enable} */
nrfy_nfct_int_enable(NRF_NFCT_Type * p_reg,uint32_t mask)325 NRFY_STATIC_INLINE void nrfy_nfct_int_enable(NRF_NFCT_Type * p_reg, uint32_t mask)
326 {
327 nrf_nfct_int_enable(p_reg, mask);
328 nrf_barrier_w();
329 }
330
331 /** @refhal{nrf_nfct_int_enable_check} */
nrfy_nfct_int_enable_check(NRF_NFCT_Type const * p_reg,uint32_t mask)332 NRFY_STATIC_INLINE uint32_t nrfy_nfct_int_enable_check(NRF_NFCT_Type const * p_reg, uint32_t mask)
333 {
334 nrf_barrier_rw();
335 uint32_t check = nrf_nfct_int_enable_check(p_reg, mask);
336 nrf_barrier_r();
337 return check;
338 }
339
340 /** @refhal{nrf_nfct_int_enable_get} */
nrfy_nfct_int_enable_get(NRF_NFCT_Type const * p_reg)341 NRFY_STATIC_INLINE uint32_t nrfy_nfct_int_enable_get(NRF_NFCT_Type const * p_reg)
342 {
343 nrf_barrier_rw();
344 uint32_t check = nrf_nfct_int_enable_get(p_reg);
345 nrf_barrier_w();
346 return check;
347 }
348
349 /** @refhal{nrf_nfct_int_disable} */
nrfy_nfct_int_disable(NRF_NFCT_Type * p_reg,uint32_t mask)350 NRFY_STATIC_INLINE void nrfy_nfct_int_disable(NRF_NFCT_Type * p_reg, uint32_t mask)
351 {
352 nrf_nfct_int_disable(p_reg, mask);
353 nrf_barrier_w();
354 }
355
356 #if NRFY_NFCT_HAS_MODULATION_PSEL_REG
357 /** @refhal{nrf_nfct_mod_ctrl_pin_set} */
nrfy_nfct_mod_ctrl_pin_set(NRF_NFCT_Type * p_reg,uint32_t mod_ctrl_pin)358 NRFY_STATIC_INLINE void nrfy_nfct_mod_ctrl_pin_set(NRF_NFCT_Type * p_reg, uint32_t mod_ctrl_pin)
359 {
360 nrf_nfct_mod_ctrl_pin_set(p_reg, mod_ctrl_pin);
361 nrf_barrier_w();
362 }
363
364 /** @refhal{nrf_nfct_mod_ctrl_pin_get} */
nrfy_nfct_mod_ctrl_pin_get(NRF_NFCT_Type const * p_reg)365 NRFY_STATIC_INLINE uint32_t nrfy_nfct_mod_ctrl_pin_get(NRF_NFCT_Type const * p_reg)
366 {
367 nrf_barrier_rw();
368 uint32_t pins = nrf_nfct_mod_ctrl_pin_get(p_reg);
369 nrf_barrier_r();
370 return pins;
371 }
372 #endif // NRFY_NFCT_HAS_MODULATION_PSEL_REG
373
374 /** @refhal{nrf_nfct_modulation_output_set} */
375 #if NRFY_NFCT_HAS_MODULATION_CTRL_REG
nrfy_nfct_modulation_output_set(NRF_NFCT_Type * p_reg,nrf_nfct_modulation_ctrl_t mod_ctrl)376 NRFY_STATIC_INLINE void nrfy_nfct_modulation_output_set(NRF_NFCT_Type * p_reg,
377 nrf_nfct_modulation_ctrl_t mod_ctrl)
378 {
379 nrf_nfct_modulation_output_set(p_reg, mod_ctrl);
380 nrf_barrier_w();
381 }
382
383 /** @refhal{nrf_nfct_modulation_output_get} */
384 NRFY_STATIC_INLINE
nrfy_nfct_modulation_output_get(NRF_NFCT_Type const * p_reg)385 nrf_nfct_modulation_ctrl_t nrfy_nfct_modulation_output_get(NRF_NFCT_Type const * p_reg)
386 {
387 nrf_barrier_rw();
388 nrf_nfct_modulation_ctrl_t modulation_ctrl = nrf_nfct_modulation_output_get(p_reg);
389 nrf_barrier_r();
390 return modulation_ctrl;
391 }
392 #endif // NRFY_NFCT_HAS_MODULATION_CTRL_REG
393
394 /** @refhal{nrf_nfct_error_status_get} */
nrfy_nfct_error_status_get(NRF_NFCT_Type const * p_reg)395 NRFY_STATIC_INLINE uint32_t nrfy_nfct_error_status_get(NRF_NFCT_Type const * p_reg)
396 {
397 nrf_barrier_rw();
398 uint32_t error_status = nrf_nfct_error_status_get(p_reg);
399 nrf_barrier_r();
400 return error_status;
401 }
402
403 /** @refhal{nrf_nfct_error_status_clear} */
nrfy_nfct_error_status_clear(NRF_NFCT_Type * p_reg,uint32_t error_flag)404 NRFY_STATIC_INLINE void nrfy_nfct_error_status_clear(NRF_NFCT_Type * p_reg, uint32_t error_flag)
405 {
406 nrf_nfct_error_status_clear(p_reg, error_flag);
407 nrf_barrier_w();
408 }
409
410 /** @refhal{nrf_nfct_rx_frame_status_get} */
nrfy_nfct_rx_frame_status_get(NRF_NFCT_Type const * p_reg)411 NRFY_STATIC_INLINE uint32_t nrfy_nfct_rx_frame_status_get(NRF_NFCT_Type const * p_reg)
412 {
413 nrf_barrier_rw();
414 uint32_t frame_status = nrf_nfct_rx_frame_status_get(p_reg);
415 nrf_barrier_r();
416 return frame_status;
417 }
418
419 /** @refhal{nrf_nfct_rx_frame_status_clear} */
nrfy_nfct_rx_frame_status_clear(NRF_NFCT_Type * p_reg,uint32_t framestatus_flags)420 NRFY_STATIC_INLINE void nrfy_nfct_rx_frame_status_clear(NRF_NFCT_Type * p_reg,
421 uint32_t framestatus_flags)
422 {
423 nrf_nfct_rx_frame_status_clear(p_reg, framestatus_flags);
424 nrf_barrier_w();
425 }
426
427 #if NRFY_NFCT_HAS_TAG_STATE_REG
428 /** @refhal{nrf_nfct_tag_state_get} */
nrfy_nfct_tag_state_get(NRF_NFCT_Type const * p_reg)429 NRFY_STATIC_INLINE nrf_nfct_tag_state_t nrfy_nfct_tag_state_get(NRF_NFCT_Type const * p_reg)
430 {
431 nrf_barrier_r();
432 nrf_nfct_tag_state_t tag_state = nrf_nfct_tag_state_get(p_reg);
433 nrf_barrier_r();
434 return tag_state;
435 }
436 #endif // NRFY_NFCT_HAS_TAG_STATE_REG
437
438 #if NRFY_NFCT_HAS_SLEEP_STATE_REG
439 /** @refhal{nrf_nfct_sleep_state_get} */
nrfy_nfct_sleep_state_get(NRF_NFCT_Type const * p_reg)440 NRFY_STATIC_INLINE nrf_nfct_sleep_state_t nrfy_nfct_sleep_state_get(NRF_NFCT_Type const * p_reg)
441 {
442 nrf_barrier_r();
443 nrf_nfct_sleep_state_t sleep_state = nrf_nfct_sleep_state_get(p_reg);
444 nrf_barrier_r();
445 return sleep_state;
446 }
447 #endif // NRFY_NFCT_HAS_SLEEP_STATE_REG
448
449 /** @refhal{nrf_nfct_field_status_get} */
nrfy_nfct_field_status_get(NRF_NFCT_Type const * p_reg)450 NRFY_STATIC_INLINE uint8_t nrfy_nfct_field_status_get(NRF_NFCT_Type const * p_reg)
451 {
452 nrf_barrier_r();
453 uint8_t status = nrf_nfct_field_status_get(p_reg);
454 nrf_barrier_r();
455 return status;
456 }
457
458 /** @refhal{nrf_nfct_frame_delay_min_get} */
nrfy_nfct_frame_delay_min_get(NRF_NFCT_Type const * p_reg)459 NRFY_STATIC_INLINE uint16_t nrfy_nfct_frame_delay_min_get(NRF_NFCT_Type const * p_reg)
460 {
461 nrf_barrier_rw();
462 uint16_t frame_delay_min = nrf_nfct_frame_delay_min_get(p_reg);
463 nrf_barrier_r();
464 return frame_delay_min;
465 }
466
467 /** @refhal{nrf_nfct_frame_delay_min_set} */
nrfy_nfct_frame_delay_min_set(NRF_NFCT_Type * p_reg,uint16_t frame_delay_min)468 NRFY_STATIC_INLINE void nrfy_nfct_frame_delay_min_set(NRF_NFCT_Type * p_reg,
469 uint16_t frame_delay_min)
470 {
471 nrf_nfct_frame_delay_min_set(p_reg, frame_delay_min);
472 nrf_barrier_w();
473 }
474
475 /** @refhal{nrf_nfct_frame_delay_max_get} */
nrfy_nfct_frame_delay_max_get(NRF_NFCT_Type const * p_reg)476 NRFY_STATIC_INLINE uint32_t nrfy_nfct_frame_delay_max_get(NRF_NFCT_Type const * p_reg)
477 {
478 nrf_barrier_rw();
479 uint32_t frame_delay_max = nrf_nfct_frame_delay_max_get(p_reg);
480 nrf_barrier_r();
481 return frame_delay_max;
482 }
483
484 /** @refhal{nrf_nfct_frame_delay_max_set} */
nrfy_nfct_frame_delay_max_set(NRF_NFCT_Type * p_reg,uint32_t frame_delay_max)485 NRFY_STATIC_INLINE void nrfy_nfct_frame_delay_max_set(NRF_NFCT_Type * p_reg,
486 uint32_t frame_delay_max)
487 {
488 nrf_nfct_frame_delay_max_set(p_reg, frame_delay_max);
489 nrf_barrier_w();
490 }
491
492 /** @refhal{nrf_nfct_frame_delay_mode_get} */
493 NRFY_STATIC_INLINE
nrfy_nfct_frame_delay_mode_get(NRF_NFCT_Type const * p_reg)494 nrf_nfct_frame_delay_mode_t nrfy_nfct_frame_delay_mode_get(NRF_NFCT_Type const * p_reg)
495 {
496 nrf_barrier_rw();
497 nrf_nfct_frame_delay_mode_t frame_delay_mode = nrf_nfct_frame_delay_mode_get(p_reg);
498 nrf_barrier_r();
499 return frame_delay_mode;
500 }
501
502 /** @refhal{nrf_nfct_frame_delay_mode_set} */
nrfy_nfct_frame_delay_mode_set(NRF_NFCT_Type * p_reg,nrf_nfct_frame_delay_mode_t frame_delay_mode)503 NRFY_STATIC_INLINE void nrfy_nfct_frame_delay_mode_set(NRF_NFCT_Type * p_reg,
504 nrf_nfct_frame_delay_mode_t frame_delay_mode)
505 {
506 nrf_nfct_frame_delay_mode_set(p_reg, frame_delay_mode);
507 nrf_barrier_w();
508 }
509
510 /** @refhal{nrf_nfct_rxtx_buffer_get} */
nrfy_nfct_rxtx_buffer_get(NRF_NFCT_Type const * p_reg)511 NRFY_STATIC_INLINE uint8_t * nrfy_nfct_rxtx_buffer_get(NRF_NFCT_Type const * p_reg)
512 {
513 nrf_barrier_rw();
514 uint8_t *buffer = nrf_nfct_rxtx_buffer_get(p_reg);
515 nrf_barrier_r();
516 return buffer;
517 }
518
519 /** @refhal{nrf_nfct_max_rxtx_length_get} */
nrfy_nfct_max_rxtx_length_get(NRF_NFCT_Type const * p_reg)520 NRFY_STATIC_INLINE uint16_t nrfy_nfct_max_rxtx_length_get(NRF_NFCT_Type const * p_reg)
521 {
522 nrf_barrier_rw();
523 uint16_t max_length = nrf_nfct_max_rxtx_length_get(p_reg);
524 nrf_barrier_r();
525 return max_length;
526 }
527
528 /** @refhal{nrf_nfct_tx_frame_config_get} */
nrfy_nfct_tx_frame_config_get(NRF_NFCT_Type const * p_reg)529 NRFY_STATIC_INLINE uint8_t nrfy_nfct_tx_frame_config_get(NRF_NFCT_Type const * p_reg)
530 {
531 nrf_barrier_rw();
532 uint8_t frame_config = nrf_nfct_tx_frame_config_get(p_reg);
533 nrf_barrier_r();
534 return frame_config;
535 }
536
537 /** @refhal{nrf_nfct_tx_frame_config_set} */
nrfy_nfct_tx_frame_config_set(NRF_NFCT_Type * p_reg,uint8_t flags)538 NRFY_STATIC_INLINE void nrfy_nfct_tx_frame_config_set(NRF_NFCT_Type * p_reg, uint8_t flags)
539 {
540 nrf_nfct_rx_frame_config_set(p_reg, flags);
541 nrf_barrier_w();
542 }
543
544 /** @refhal{nrf_nfct_tx_bits_get} */
nrfy_nfct_tx_bits_get(NRF_NFCT_Type const * p_reg)545 NRFY_STATIC_INLINE uint16_t nrfy_nfct_tx_bits_get(NRF_NFCT_Type const * p_reg)
546 {
547 nrf_barrier_rw();
548 uint16_t bits = nrf_nfct_tx_bits_get(p_reg);
549 nrf_barrier_r();
550 return bits;
551 }
552
553 /** @refhal{nrf_nfct_tx_bits_set} */
nrfy_nfct_tx_bits_set(NRF_NFCT_Type * p_reg,uint16_t tx_bits)554 NRFY_STATIC_INLINE void nrfy_nfct_tx_bits_set(NRF_NFCT_Type * p_reg, uint16_t tx_bits)
555 {
556 nrf_nfct_tx_bits_set(p_reg, tx_bits);
557 nrf_barrier_w();
558 }
559
560 /** @refhal{nrf_nfct_rx_frame_config_get} */
nrfy_nfct_rx_frame_config_get(NRF_NFCT_Type const * p_reg)561 NRFY_STATIC_INLINE uint8_t nrfy_nfct_rx_frame_config_get(NRF_NFCT_Type const * p_reg)
562 {
563 nrf_barrier_rw();
564 uint8_t frame_config = nrf_nfct_rx_frame_config_get(p_reg);
565 nrf_barrier_r();
566 return frame_config;
567 }
568
569 /** @refhal{nrf_nfct_rx_frame_config_set} */
nrfy_nfct_rx_frame_config_set(NRF_NFCT_Type * p_reg,uint8_t flags)570 NRFY_STATIC_INLINE void nrfy_nfct_rx_frame_config_set(NRF_NFCT_Type * p_reg, uint8_t flags)
571 {
572 nrf_nfct_rx_frame_config_set(p_reg, flags);
573 nrf_barrier_w();
574 }
575
576 /** @refhal{nrf_nfct_rx_bits_get} */
nrfy_nfct_rx_bits_get(NRF_NFCT_Type const * p_reg,bool crc_excluded)577 NRFY_STATIC_INLINE uint16_t nrfy_nfct_rx_bits_get(NRF_NFCT_Type const * p_reg, bool crc_excluded)
578 {
579 nrf_barrier_r();
580 uint16_t rx_bits = nrf_nfct_rx_bits_get(p_reg, crc_excluded);
581 nrf_barrier_r();
582 return rx_bits;
583 }
584
585 /** @refhal{nrf_nfct_nfcid1_get} */
586 NRFY_STATIC_INLINE
nrfy_nfct_nfcid1_get(NRF_NFCT_Type const * p_reg,uint8_t * p_nfcid1_buf)587 nrf_nfct_sensres_nfcid1_size_t nrfy_nfct_nfcid1_get(NRF_NFCT_Type const * p_reg,
588 uint8_t * p_nfcid1_buf)
589 {
590 nrf_barrier_rw();
591 nrf_nfct_sensres_nfcid1_size_t nfcid1_size = nrf_nfct_nfcid1_get(p_reg, p_nfcid1_buf);
592 nrf_barrier_rw();
593 return nfcid1_size;
594 }
595
596 /** @refhal{nrf_nfct_nfcid1_set} */
nrfy_nfct_nfcid1_set(NRF_NFCT_Type * p_reg,uint8_t const * p_nfcid1_buf,nrf_nfct_sensres_nfcid1_size_t nfcid1_size)597 NRFY_STATIC_INLINE void nrfy_nfct_nfcid1_set(NRF_NFCT_Type * p_reg,
598 uint8_t const * p_nfcid1_buf,
599 nrf_nfct_sensres_nfcid1_size_t nfcid1_size)
600 {
601 nrf_nfct_nfcid1_set(p_reg, p_nfcid1_buf, nfcid1_size);
602 nrf_barrier_w();
603 }
604
605 #if NRFY_NFCT_HAS_AUTOCOLRES_CONFIG_REG
606 /** @refhal{nrf_nfct_autocolres_is_enabled} */
nrfy_nfct_autocolres_is_enabled(NRF_NFCT_Type const * p_reg)607 NRFY_STATIC_INLINE bool nrfy_nfct_autocolres_is_enabled(NRF_NFCT_Type const * p_reg)
608 {
609 nrf_barrier_rw();
610 bool enabled = nrf_nfct_autocolres_is_enabled(p_reg);
611 nrf_barrier_r();
612 return enabled;
613 }
614
615 /** @refhal{nrf_nfct_autocolres_enable} */
nrfy_nfct_autocolres_enable(NRF_NFCT_Type * p_reg)616 NRFY_STATIC_INLINE void nrfy_nfct_autocolres_enable(NRF_NFCT_Type * p_reg)
617 {
618 nrf_nfct_autocolres_enable(p_reg);
619 nrf_barrier_w();
620 }
621
622 /** @refhal{nrf_nfct_autocolres_disable} */
nrfy_nfct_autocolres_disable(NRF_NFCT_Type * p_reg)623 NRFY_STATIC_INLINE void nrfy_nfct_autocolres_disable(NRF_NFCT_Type * p_reg)
624 {
625 nrf_nfct_autocolres_disable(p_reg);
626 nrf_barrier_w();
627 }
628 #endif // NRFY_NFCT_HAS_AUTOCOLRES_CONFIG_REG
629
630 /** @refhal{nrf_nfct_sensres_nfcid1_size_get} */
631 NRFY_STATIC_INLINE
nrfy_nfct_sensres_nfcid1_size_get(NRF_NFCT_Type const * p_reg)632 nrf_nfct_sensres_nfcid1_size_t nrfy_nfct_sensres_nfcid1_size_get(NRF_NFCT_Type const * p_reg)
633 {
634 nrf_barrier_rw();
635 nrf_nfct_sensres_nfcid1_size_t nfcid1_size = nrf_nfct_sensres_nfcid1_size_get(p_reg);
636 nrf_barrier_r();
637 return nfcid1_size;
638 }
639
640 /** @refhal{nrf_nfct_sensres_nfcid1_size_set} */
641 NRFY_STATIC_INLINE
nrfy_nfct_sensres_nfcid1_size_set(NRF_NFCT_Type * p_reg,nrf_nfct_sensres_nfcid1_size_t nfcid1_size)642 void nrfy_nfct_sensres_nfcid1_size_set(NRF_NFCT_Type * p_reg,
643 nrf_nfct_sensres_nfcid1_size_t nfcid1_size)
644 {
645 nrf_nfct_sensres_nfcid1_size_set(p_reg, nfcid1_size);
646 nrf_barrier_w();
647 }
648
649 /** @refhal{nrf_nfct_sensres_bit_frame_sdd_get} */
650 NRFY_STATIC_INLINE
nrfy_nfct_sensres_bit_frame_sdd_get(NRF_NFCT_Type const * p_reg)651 nrf_nfct_sensres_bit_frame_sdd_t nrfy_nfct_sensres_bit_frame_sdd_get(NRF_NFCT_Type const * p_reg)
652 {
653 nrf_barrier_rw();
654 nrf_nfct_sensres_bit_frame_sdd_t frame_sdd = nrf_nfct_sensres_bit_frame_sdd_get(p_reg);
655 nrf_barrier_r();
656 return frame_sdd;
657 }
658
659 /** @refhal{nrf_nfct_sensres_bit_frame_sdd_set} */
660 NRFY_STATIC_INLINE
nrfy_nfct_sensres_bit_frame_sdd_set(NRF_NFCT_Type * p_reg,nrf_nfct_sensres_bit_frame_sdd_t bit_frame_sdd)661 void nrfy_nfct_sensres_bit_frame_sdd_set(NRF_NFCT_Type * p_reg,
662 nrf_nfct_sensres_bit_frame_sdd_t bit_frame_sdd)
663 {
664 nrf_nfct_sensres_bit_frame_sdd_set(p_reg, bit_frame_sdd);
665 nrf_barrier_w();
666 }
667
668 /** @refhal{nrf_nfct_sensres_platform_config_get} */
669 NRFY_STATIC_INLINE nrf_nfct_sensres_platform_config_t
nrfy_nfct_sensres_platform_config_get(NRF_NFCT_Type const * p_reg)670 nrfy_nfct_sensres_platform_config_get(NRF_NFCT_Type const * p_reg)
671 {
672 nrf_barrier_rw();
673 nrf_nfct_sensres_platform_config_t config = nrf_nfct_sensres_platform_config_get(p_reg);
674 nrf_barrier_r();
675 return config;
676 }
677
678 /** @refhal{nrf_nfct_sensres_platform_config_set} */
679 NRFY_STATIC_INLINE
nrfy_nfct_sensres_platform_config_set(NRF_NFCT_Type * p_reg,nrf_nfct_sensres_platform_config_t platform_config)680 void nrfy_nfct_sensres_platform_config_set(NRF_NFCT_Type * p_reg,
681 nrf_nfct_sensres_platform_config_t platform_config)
682 {
683 nrf_nfct_sensres_platform_config_set(p_reg, platform_config);
684 nrf_barrier_w();
685 }
686
687 /** @refhal{nrf_nfct_selres_cascade_check} */
nrfy_nfct_selres_cascade_check(NRF_NFCT_Type const * p_reg)688 NRFY_STATIC_INLINE bool nrfy_nfct_selres_cascade_check(NRF_NFCT_Type const * p_reg)
689 {
690 nrf_barrier_rw();
691 bool check = nrf_nfct_selres_cascade_check(p_reg);
692 nrf_barrier_r();
693 return check;
694 }
695
696 /** @refhal{nrf_nfct_selres_protocol_get} */
697 NRFY_STATIC_INLINE
nrfy_nfct_selres_protocol_get(NRF_NFCT_Type const * p_reg)698 nrf_nfct_selres_protocol_t nrfy_nfct_selres_protocol_get(NRF_NFCT_Type const * p_reg)
699 {
700 nrf_barrier_rw();
701 nrf_nfct_selres_protocol_t protocol = nrf_nfct_selres_protocol_get(p_reg);
702 nrf_barrier_r();
703 return protocol;
704 }
705
706 /** @refhal{nrf_nfct_selres_protocol_set} */
nrfy_nfct_selres_protocol_set(NRF_NFCT_Type * p_reg,nrf_nfct_selres_protocol_t sel_res_protocol)707 NRFY_STATIC_INLINE void nrfy_nfct_selres_protocol_set(NRF_NFCT_Type * p_reg,
708 nrf_nfct_selres_protocol_t sel_res_protocol)
709 {
710 nrf_nfct_selres_protocol_set(p_reg, sel_res_protocol);
711 nrf_barrier_w();
712 }
713
714 /** @refhal{nrf_nfct_selres_get} */
nrfy_nfct_selres_get(NRF_NFCT_Type const * p_reg)715 NRFY_STATIC_INLINE uint32_t nrfy_nfct_selres_get(NRF_NFCT_Type const * p_reg)
716 {
717 nrf_barrier_rw();
718 uint32_t selres = nrf_nfct_selres_get(p_reg);
719 nrf_barrier_r();
720 return selres;
721 }
722
723 /** @refhal{nrf_nfct_selres_set} */
nrfy_nfct_selres_set(NRF_NFCT_Type * p_reg,uint32_t selres)724 NRFY_STATIC_INLINE void nrfy_nfct_selres_set(NRF_NFCT_Type * p_reg, uint32_t selres)
725 {
726 nrf_nfct_selres_set(p_reg, selres);
727 nrf_barrier_w();
728 }
729
730 #if NRFY_NFCT_HAS_PAD_CONFIG_REG
731 /** @refhal{nrf_nfct_pad_config_enable_check} */
nrfy_nfct_pad_config_enable_check(NRF_NFCT_Type const * p_reg)732 NRFY_STATIC_INLINE bool nrfy_nfct_pad_config_enable_check(NRF_NFCT_Type const * p_reg)
733 {
734 nrf_barrier_rw();
735 bool enabled = nrf_nfct_pad_config_enable_check(p_reg);
736 nrf_barrier_w();
737 return enabled;
738 }
739
740 /** @refhal{nrf_nfct_pad_config_enable_set} */
nrfy_nfct_pad_config_enable_set(NRF_NFCT_Type * p_reg,bool enable)741 NRFY_STATIC_INLINE void nrfy_nfct_pad_config_enable_set(NRF_NFCT_Type * p_reg, bool enable)
742 {
743 nrf_nfct_pad_config_enable_set(p_reg, enable);
744 nrf_barrier_w();
745 }
746 #endif // NRFY_NFCT_HAS_PAD_CONFIG_REG
747
748 #if NRFY_NFCT_HAS_BIAS_CONFIG_TRIM_REG
749 /** @refhal{nrf_nfct_bias_config_get} */
nrfy_nfct_bias_config_get(NRF_NFCT_Type const * p_reg,nrf_nfct_bias_config_t * p_bias_config)750 NRFY_STATIC_INLINE void nrfy_nfct_bias_config_get(NRF_NFCT_Type const * p_reg,
751 nrf_nfct_bias_config_t * p_bias_config)
752 {
753 nrf_barrier_rw();
754 nrf_nfct_bias_config_get(p_reg, p_bias_config);
755 nrf_barrier_r();
756 }
757
758 /** @refhal{nrf_nfct_bias_config_set} */
nrfy_nfct_bias_config_set(NRF_NFCT_Type * p_reg,nrf_nfct_bias_config_t const * p_bias_config)759 NRFY_STATIC_INLINE void nrfy_nfct_bias_config_set(NRF_NFCT_Type * p_reg,
760 nrf_nfct_bias_config_t const * p_bias_config)
761 {
762 nrf_nfct_bias_config_set(p_reg, p_bias_config);
763 nrf_barrier_w();
764 }
765 #endif // NRFY_NFCT_HAS_BIAS_CONFIG_TRIM_REG
766
767 /** @} */
768
__nrfy_internal_nfct_event_enabled_clear(NRF_NFCT_Type * p_reg,uint32_t mask,nrf_nfct_event_t event)769 NRFY_STATIC_INLINE void __nrfy_internal_nfct_event_enabled_clear(NRF_NFCT_Type * p_reg,
770 uint32_t mask,
771 nrf_nfct_event_t event)
772 {
773 if (mask & NRFY_EVENT_TO_INT_BITMASK(event))
774 {
775 nrf_nfct_event_clear(p_reg, event);
776 }
777 }
778
__nrfy_internal_nfct_event_handle(NRF_NFCT_Type * p_reg,uint32_t mask,nrf_nfct_event_t event,uint32_t * p_evt_mask)779 NRFY_STATIC_INLINE bool __nrfy_internal_nfct_event_handle(NRF_NFCT_Type * p_reg,
780 uint32_t mask,
781 nrf_nfct_event_t event,
782 uint32_t * p_evt_mask)
783 {
784 if ((mask & NRFY_EVENT_TO_INT_BITMASK(event)) && nrf_nfct_event_check(p_reg, event))
785 {
786 nrf_nfct_event_clear(p_reg, event);
787 if (p_evt_mask)
788 {
789 *p_evt_mask |= NRFY_EVENT_TO_INT_BITMASK(event);
790 }
791 return true;
792 }
793
794 return false;
795 }
796
__nrfy_internal_nfct_events_process(NRF_NFCT_Type * p_reg,uint32_t mask)797 NRFY_STATIC_INLINE uint32_t __nrfy_internal_nfct_events_process(NRF_NFCT_Type * p_reg, uint32_t mask)
798 {
799 uint32_t evt_mask = 0;
800
801 nrf_barrier_r();
802 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_READY, &evt_mask);
803 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_FIELDDETECTED, &evt_mask);
804 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_FIELDLOST, &evt_mask);
805 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_TXFRAMESTART, &evt_mask);
806 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_TXFRAMEEND, &evt_mask);
807 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_RXFRAMESTART, &evt_mask);
808 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_RXFRAMEEND, &evt_mask);
809 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_ERROR, &evt_mask);
810 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_RXERROR, &evt_mask);
811 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_ENDRX, &evt_mask);
812 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_ENDTX, &evt_mask);
813 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_AUTOCOLRESSTARTED, &evt_mask);
814 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_COLLISION, &evt_mask);
815 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_SELECTED, &evt_mask);
816 __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_STARTED, &evt_mask);
817
818 if (evt_mask & NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_RXFRAMEEND))
819 {
820 uint8_t *buffer = nrf_nfct_rxtx_buffer_get(p_reg);
821 uint16_t bytes = (nrf_nfct_rx_bits_get(p_reg, true) >> 3U);
822
823 nrf_barrier_rw();
824 NRFY_CACHE_INV(buffer, bytes);
825 }
826
827 nrf_barrier_w();
828
829 return evt_mask;
830 }
831
832 #ifdef __cplusplus
833 }
834 #endif
835
836 #endif // NRFY_NFCT_H__
837
