1 /*
2 * Copyright (c) 2023 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_RRAMC_H__
35 #define NRF_RRAMC_H__
36
37 #include <nrfx.h>
38 #include <nrf_bitmask.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /**
45 * @defgroup nrf_rramc_hal RRAMC HAL
46 * @{
47 * @ingroup nrf_rramc
48 * @brief Hardware access layer for managing the the Resistive Random Access Memory Controller (RRAMC) peripheral.
49 */
50
51 /** @brief Maximum size of a write-buffer in number of 128-bit words. */
52 #define NRF_RRAMC_CONFIG_WRITE_BUFF_SIZE_MAX RRAMC_CONFIG_WRITEBUFSIZE_Max
53
54 /** @brief Maximum preload timeout value for waiting for a next write. */
55 #define NRF_RRAMC_READYNEXTTIMEOUT_MAX RRAMC_READYNEXTTIMEOUT_VALUE_Max
56
57 /** @brief RRAMC region permissions bitmask. */
58 #define NRF_RRAMC_REGION_CONFIG_PERM_MASK (RRAMC_REGION_CONFIG_READ_Msk | \
59 RRAMC_REGION_CONFIG_WRITE_Msk | \
60 RRAMC_REGION_CONFIG_EXECUTE_Msk | \
61 RRAMC_REGION_CONFIG_SECURE_Msk)
62
63 /** @brief RRAMC tasks. */
64 typedef enum
65 {
66 NRF_RRAMC_TASK_WAKEUP = offsetof(NRF_RRAMC_Type, TASKS_WAKEUP), ///< Wakeup the RRAM from low power mode.
67 NRF_RRAMC_TASK_COMMIT_WRITEBUF = offsetof(NRF_RRAMC_Type, TASKS_COMMITWRITEBUF), ///< Commit the data stored in internal write-buffer to RRAM.
68 } nrf_rramc_task_t;
69
70 /** @brief RRAMC events. */
71 typedef enum
72 {
73 NRF_RRAMC_EVENT_WOKENUP = offsetof(NRF_RRAMC_Type, EVENTS_WOKENUP), ///< The RRAM is woken up from low power mode.
74 NRF_RRAMC_EVENT_READY = offsetof(NRF_RRAMC_Type, EVENTS_READY), ///< RRAMC is ready.
75 NRF_RRAMC_EVENT_READY_NEXT = offsetof(NRF_RRAMC_Type, EVENTS_READYNEXT), ///< Ready to accept a new write operation.
76 NRF_RRAMC_EVENT_ERROR_ACCESS = offsetof(NRF_RRAMC_Type, EVENTS_ACCESSERROR), ///< RRAM access error.
77 } nrf_rramc_event_t;
78
79 /** @brief RRAMC interrupts. */
80 typedef enum
81 {
82 NRF_RRAMC_INT_WOKENUP_MASK = RRAMC_INTENSET_WOKENUP_Msk, ///< Interrupt on WOKENUP event.
83 NRF_RRAMC_INT_READY_MASK = RRAMC_INTENSET_READY_Msk, ///< Interrupt on READY event.
84 NRF_RRAMC_INT_READY_NEXT_MASK = RRAMC_INTENSET_READYNEXT_Msk, ///< Interrupt on READYNEXT event.
85 NRF_RRAMC_INT_ERROR_ACCESS_MASK = RRAMC_INTENSET_ACCESSERROR_Msk, ///< Interrupt on ACCESSERROR event.
86 NRF_RRAMC_ALL_INTS_MASK = NRF_RRAMC_INT_WOKENUP_MASK
87 | NRF_RRAMC_INT_READY_MASK
88 | NRF_RRAMC_INT_READY_NEXT_MASK
89 | NRF_RRAMC_INT_ERROR_ACCESS_MASK ///< All RRAMC interrupts.
90 } nrf_rramc_int_mask_t;
91
92 /** @brief RRAMC configuration structure. */
93 typedef struct
94 {
95 bool mode_write; ///< True if write mode is to be enabled, false otherwise.
96 uint8_t write_buff_size; ///< Write-buffer size in case set to 0 buffering is disabled.
97 } nrf_rramc_config_t;
98
99 /** @brief Preload timeout value for waiting for a next write. */
100 typedef struct
101 {
102 uint16_t value; ///< Preload value expressed in clock cycles.
103 bool enable; ///< True if write to the RRAM is to be triggered on the next timeout, false otherwise.
104 } nrf_rramc_ready_next_timeout_t;
105
106 /** @brief Power configuration. */
107 typedef struct
108 {
109 uint16_t access_timeout; ///< Access timeout used for going into standby power mode or remain active on wake up, expressed in clock cycles.
110 bool abort_on_pof; ///< True if the current RRAM write operation is to be aborted on the power failure, false otherwise.
111 } nrf_rramc_power_t;
112
113 /**
114 * @brief RRAMC region permissions mask.
115 *
116 * @note When bit is set, the selected action is allowed.
117 */
118 typedef enum
119 {
120 NRF_RRAMC_REGION_PERM_READ_MASK = RRAMC_REGION_CONFIG_READ_Msk, ///< Read access.
121 NRF_RRAMC_REGION_PERM_WRITE_MASK = RRAMC_REGION_CONFIG_WRITE_Msk, ///< Write access.
122 NRF_RRAMC_REGION_PERM_EXECUTE_MASK = RRAMC_REGION_CONFIG_EXECUTE_Msk, ///< Software execute.
123 NRF_RRAMC_REGION_PERM_SECURE_MASK = RRAMC_REGION_CONFIG_SECURE_Msk, ///< Secure-only access.
124 } nrf_rramc_region_perm_mask_t;
125
126 /** @brief RRAMC region configuration. */
127 typedef struct
128 {
129 uint32_t address; ///< Start address of the region.
130 uint32_t permissions; ///< Permissions created using @ref nrf_rramc_region_perm_mask_t.
131 bool writeonce; ///< True if writes to the region are to be applied only when the current data is 0xFFFFFFFF.
132 bool lock; ///< True if memory belonging to given region is to be read-only.
133 uint16_t size_kb; ///< Region size in kBs. */
134 } nrf_rramc_region_config_t;
135
136 /**
137 * @brief Function for activating the specified RRAMC task.
138 *
139 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
140 * @param[in] task Task to be activated.
141 */
142 NRF_STATIC_INLINE void nrf_rramc_task_trigger(NRF_RRAMC_Type * p_reg, nrf_rramc_task_t task);
143
144 /**
145 * @brief Function for getting the address of the specified RRAMC task register.
146 *
147 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
148 * @param[in] task RRAMC task.
149 *
150 * @return Address of the specified task register.
151 */
152 NRF_STATIC_INLINE uint32_t nrf_rramc_task_address_get(NRF_RRAMC_Type const * p_reg,
153 nrf_rramc_task_t task);
154
155 /**
156 * @brief Function for clearing the specified RRAMC event.
157 *
158 * @param[in] p_reg Pointer to the peripheral register structure.
159 * @param[in] event Event to clear.
160 */
161 NRF_STATIC_INLINE void nrf_rramc_event_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_event_t event);
162
163 /**
164 * @brief Function for retrieving the state of the RRAMC event.
165 *
166 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
167 * @param[in] event Event to be checked.
168 *
169 * @retval true The event has been generated.
170 * @retval false The event has not been generated.
171 */
172 NRF_STATIC_INLINE bool nrf_rramc_event_check(NRF_RRAMC_Type const * p_reg, nrf_rramc_event_t event);
173
174 /**
175 * @brief Function for getting the address of the specified RRAMC event register.
176 *
177 * @param[in] p_reg Pointer to the peripheral register structure.
178 * @param[in] event Requested event.
179 *
180 * @return Address of the specified event register.
181 */
182 NRF_STATIC_INLINE uint32_t nrf_rramc_event_address_get(NRF_RRAMC_Type const * p_reg,
183 nrf_rramc_event_t event);
184
185 /**
186 * @brief Function for enabling the specified interrupts.
187 *
188 * @param[in] p_reg Pointer to the peripheral register structure.
189 * @param[in] mask Mask of interrupts to be enabled.
190 * Use @ref nrf_rramc_int_mask_t values for bit masking.
191 */
192 NRF_STATIC_INLINE void nrf_rramc_int_enable(NRF_RRAMC_Type * p_reg, uint32_t mask);
193
194 /**
195 * @brief Function for disabling the specified interrupts.
196 *
197 * @param[in] p_reg Pointer to the peripheral register structure.
198 * @param[in] mask Mask of interrupts to be disabled.
199 * Use @ref nrf_rramc_int_mask_t values for bit masking.
200 */
201 NRF_STATIC_INLINE void nrf_rramc_int_disable(NRF_RRAMC_Type * p_reg, uint32_t mask);
202
203 /**
204 * @brief Function for checking if the specified interrupts are enabled.
205 *
206 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
207 * @param[in] mask Mask of interrupts to be checked.
208 * Use @ref nrf_rramc_int_mask_t values for bit masking.
209 *
210 * @return Mask of enabled interrupts.
211 */
212 NRF_STATIC_INLINE uint32_t nrf_rramc_int_enable_check(NRF_RRAMC_Type const * p_reg, uint32_t mask);
213
214 /**
215 * @brief Function for getting the state of pending interrupts.
216 *
217 * @note States of pending interrupt are saved as a bitmask.
218 * One set at particular position means that interrupt for event is pending.
219 *
220 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
221 *
222 * @return Bitmask with information about pending interrupts.
223 * Use @ref nrf_rramc_int_mask_t values for bit masking.
224 */
225 NRF_STATIC_INLINE uint32_t nrf_rramc_int_pending_get(NRF_RRAMC_Type const * p_reg);
226
227 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
228 /**
229 * @brief Function for setting the subscribe configuration for a wakeup
230 * RRAMC task.
231 *
232 * @note Not every task has its corresponding subscribe register.
233 * Refer to the Product Specification for more information.
234 *
235 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
236 * @param[in] task Task for which to set the configuration.
237 * @param[in] channel Channel through which to subscribe events.
238 */
239 NRF_STATIC_INLINE void nrf_rramc_subscribe_set(NRF_RRAMC_Type * p_reg,
240 nrf_rramc_task_t task,
241 uint8_t channel);
242
243 /**
244 * @brief Function for clearing the subscribe configuration for a wakeup
245 * RRAMC task.
246 *
247 * @note Not every task has its corresponding subscribe register.
248 * Refer to the Product Specification for more information.
249 *
250 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
251 * @param[in] task Task for which to clear the configuration.
252 */
253 NRF_STATIC_INLINE void nrf_rramc_subscribe_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_task_t task);
254
255 /**
256 * @brief Function for setting the publish configuration for a wokenup
257 * RRAMC event.
258 *
259 * @note Not every event has its corresponding publish register.
260 * Refer to the Product Specification for more information.
261 *
262 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
263 * @param[in] event Event for which to set the configuration.
264 * @param[in] channel Channel through which to publish the event.
265 */
266 NRF_STATIC_INLINE void nrf_rramc_publish_set(NRF_RRAMC_Type * p_reg,
267 nrf_rramc_event_t event,
268 uint8_t channel);
269
270 /**
271 * @brief Function for clearing the publish configuration for a wokenup
272 * RRAMC event.
273 *
274 * @note Not every event has its corresponding publish register.
275 * Refer to the Product Specification for more information.
276 *
277 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
278 * @param[in] event Event for which to clear the configuration.
279 */
280 NRF_STATIC_INLINE void nrf_rramc_publish_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_event_t event);
281
282 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
283
284 /**
285 * @brief Function for checking current RRAMC operation status.
286 *
287 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
288 *
289 * @retval true Current operation is completed, and RRAMC is ready.
290 * @retval false RRAMC is busy.
291 */
292 NRF_STATIC_INLINE bool nrf_rramc_ready_check(NRF_RRAMC_Type const * p_reg);
293
294 /**
295 * @brief Function for checking whether RRAMC is ready to accept a new write operation.
296 *
297 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
298 *
299 * @retval true RRAMC is ready to accept a new write operation.
300 * @retval false RRAMC cannot accept any write operation now.
301 */
302 NRF_STATIC_INLINE bool nrf_rramc_write_ready_check(NRF_RRAMC_Type const * p_reg);
303
304 /**
305 * @brief Fuction for checking the address of the first access error.
306 *
307 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
308 *
309 * @return Access error address.
310 */
311 NRF_STATIC_INLINE uint32_t nrf_rramc_error_access_addr_get(NRF_RRAMC_Type const * p_reg);
312
313 /**
314 * @brief Function for checking whether the internal write-buffer has been committed to RRAM and is now empty.
315 *
316 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
317 *
318 * @retval true The internal write-buffer is empty and has no content that needs to be commited.
319 * @retval false The internal write-buffer has data that needs to be committed.
320 */
321 NRF_STATIC_INLINE bool nrf_rramc_empty_buffer_check(NRF_RRAMC_Type const * p_reg);
322
323 /**
324 * @brief Function for getting the RRAMC peripheral configuration.
325 *
326 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
327 * @param[out] p_config Pointer to the structure to be filled with RRAMC configuration data.
328 */
329 NRF_STATIC_INLINE void nrf_rramc_config_get(NRF_RRAMC_Type const * p_reg,
330 nrf_rramc_config_t * p_config);
331
332 /**
333 * @brief Function for setting the RRAMC peripheral configuration.
334 *
335 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
336 * @param[in] p_config Pointer to the structure with configuration to be set.
337 */
338 NRF_STATIC_INLINE void nrf_rramc_config_set(NRF_RRAMC_Type * p_reg,
339 nrf_rramc_config_t const * p_config);
340
341 /**
342 * @brief Function for getting preload timeout value for waiting for a next write.
343 *
344 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
345 * @param[out] p_config Pointer to the structure to be filled with information about
346 * preload timeout value.
347 */
348 NRF_STATIC_INLINE void nrf_rramc_ready_next_timeout_get(NRF_RRAMC_Type const * p_reg,
349 nrf_rramc_ready_next_timeout_t * p_config);
350
351 /**
352 * @brief Function for setting preload timeout value for waiting for a next write.
353 *
354 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
355 * @param[in] p_config Pointer to the structure filled with information about$ preload
356 * timeout value.
357 */
358 NRF_STATIC_INLINE
359 void nrf_rramc_ready_next_timeout_set(NRF_RRAMC_Type * p_reg,
360 nrf_rramc_ready_next_timeout_t const * p_config);
361
362 /**
363 * @brief Function for getting the RRAMC power configuration.
364 *
365 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
366 * @param[out] p_config Pointer to the structure to be filled with information about
367 * power configuration.
368 */
369 NRF_STATIC_INLINE void nrf_rramc_power_config_get(NRF_RRAMC_Type const * p_reg,
370 nrf_rramc_power_t * p_config);
371
372 /**
373 * @brief Function for setting the RRAMC power configuration.
374 *
375 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
376 * @param[in] p_config Pointer to the structure filled with information about power configuration.
377 */
378 NRF_STATIC_INLINE void nrf_rramc_power_config_set(NRF_RRAMC_Type * p_reg,
379 nrf_rramc_power_t const * p_config);
380
381 /**
382 * @brief Function for checking if the erasing operation of the whole RRAM main block has been started.
383 *
384 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
385 *
386 * @retval true Erase of chip started.
387 * @retval false No operation.
388 */
389 NRF_STATIC_INLINE bool nrf_rramc_erase_all_check(NRF_RRAMC_Type const * p_reg);
390
391 /**
392 * @brief Function for erasing whole RRAM main block, that includes the SICR and the UICR.
393 *
394 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
395 */
396 NRF_STATIC_INLINE void nrf_rramc_erase_all_set(NRF_RRAMC_Type * p_reg);
397
398 /**
399 * @brief Function for setting the configuration of the specified RRAMC region.
400 *
401 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
402 * @param[in] region Region number.
403 * @param[in] p_config Pointer to the configuration structure.
404 */
405 NRF_STATIC_INLINE void nrf_rramc_region_config_set(NRF_RRAMC_Type * p_reg,
406 uint8_t region,
407 nrf_rramc_region_config_t const * p_config);
408
409 /**
410 * @brief Function for getting the configuration of the specified RRAMC region.
411 *
412 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
413 * @param[in] region Region number.
414 * @param[in] p_config Pointer to the structure to be filled with RRAMC region settings.
415 */
416 NRF_STATIC_INLINE void nrf_rramc_region_config_get(NRF_RRAMC_Type const * p_reg,
417 uint8_t region,
418 nrf_rramc_region_config_t * p_config);
419
420 /**
421 * @brief Function for getting the raw configuration of the specified RRAMC region.
422 *
423 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
424 * @param[in] region Region number.
425 *
426 * @return Raw configuration.
427 */
428 NRF_STATIC_INLINE uint32_t nrf_rramc_region_config_raw_get(NRF_RRAMC_Type const * p_reg,
429 uint8_t region);
430
431 /**
432 * @brief Function for writing a byte to RRAM memory.
433 *
434 * @note If write buffer is enabled, new data might not be immediately committed
435 * to the target memory.
436 *
437 * @warning Before calling this function, the caller must ensure that write mode
438 * is enabled using @ref nrf_rramc_config_set.
439 *
440 * @param[in] address Address of the byte to write.
441 * @param[in] value Value to write.
442 */
443 NRF_STATIC_INLINE void nrf_rramc_byte_write(uint32_t address, uint8_t value);
444
445 /**
446 * @brief Function for writing a halfword to RRAM memory.
447 *
448 * @note If write buffer is enabled, new data might not be immediately committed
449 * to the target memory.
450 *
451 * @warning Before calling this function, the caller must ensure that write mode
452 * is enabled using @ref nrf_rramc_config_set.
453 *
454 * @param[in] address Address of the halfword to write.
455 * @param[in] value Value to write.
456 */
457 NRF_STATIC_INLINE void nrf_rramc_halfword_write(uint32_t address, uint16_t value);
458
459 /**
460 * @brief Function for writing a word to RRAM memory.
461 *
462 * @note If write buffer is enabled, new data might not be immediately committed
463 * to the target memory.
464 *
465 * @warning Before calling this function, the caller must ensure that write mode
466 * is enabled using @ref nrf_rramc_config_set.
467 *
468 * @param[in] address Address of the word to write.
469 * @param[in] value Value to write.
470 */
471 NRF_STATIC_INLINE void nrf_rramc_word_write(uint32_t address, uint32_t value);
472
473 /**
474 * @brief Function for writing a given number of bytes from a specified buffer
475 * into RRAM memory.
476 *
477 * @note If write buffer is enabled, new data might not be immediately committed
478 * to the target memory.
479 *
480 * @warning Before calling this function, the caller must ensure that write mode
481 * is enabled using @ref nrf_rramc_config_set.
482 *
483 * @param[in] address Destination address in RRAM.
484 * @param[in] src Pointer to the buffer from where data will be copied.
485 * @param[in] num_bytes Number of bytes to write.
486 *
487 */
488 NRF_STATIC_INLINE void nrf_rramc_buffer_write(uint32_t address, void * src, uint32_t num_bytes);
489
490 /**
491 * @brief Function for reading a byte from the RRAM memory.
492 *
493 * @param[in] address Address of the byte to read.
494 *
495 * @return Value read from RRAM memory.
496 */
497 NRF_STATIC_INLINE uint8_t nrf_rramc_byte_read(uint32_t address);
498
499 /**
500 * @brief Function for reading a halfword from the RRAM memory.
501 *
502 * @param[in] address Address of the halfword to read.
503 *
504 * @return Value read from RRAM memory.
505 */
506 NRF_STATIC_INLINE uint16_t nrf_rramc_halfword_read(uint32_t address);
507
508 /**
509 * @brief Function for reading a word from the RRAM memory.
510 *
511 * @param[in] address Address of the word to read.
512 *
513 * @return Value read from RRAM memory.
514 */
515 NRF_STATIC_INLINE uint32_t nrf_rramc_word_read(uint32_t address);
516
517 /**
518 * @brief Function for reading a given number of bytes from RRAM memory
519 * into a specified buffer.
520 *
521 * @param[in] dst Pointer to the buffer to store the data.
522 * @param[in] address Address of the first byte to read.
523 * @param[in] num_bytes Number of bytes to read.
524 *
525 */
526 NRF_STATIC_INLINE void nrf_rramc_buffer_read(void * dst, uint32_t address, uint32_t num_bytes);
527
528 #ifndef NRF_DECLARE_ONLY
529
nrf_rramc_task_trigger(NRF_RRAMC_Type * p_reg,nrf_rramc_task_t task)530 NRF_STATIC_INLINE void nrf_rramc_task_trigger(NRF_RRAMC_Type * p_reg, nrf_rramc_task_t task)
531 {
532 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
533 }
534
nrf_rramc_task_address_get(NRF_RRAMC_Type const * p_reg,nrf_rramc_task_t task)535 NRF_STATIC_INLINE uint32_t nrf_rramc_task_address_get(NRF_RRAMC_Type const * p_reg,
536 nrf_rramc_task_t task)
537 {
538 return ((uint32_t)p_reg + (uint32_t)task);
539 }
540
nrf_rramc_event_clear(NRF_RRAMC_Type * p_reg,nrf_rramc_event_t event)541 NRF_STATIC_INLINE void nrf_rramc_event_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_event_t event)
542 {
543 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
544 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
545 }
546
nrf_rramc_event_check(NRF_RRAMC_Type const * p_reg,nrf_rramc_event_t event)547 NRF_STATIC_INLINE bool nrf_rramc_event_check(NRF_RRAMC_Type const * p_reg, nrf_rramc_event_t event)
548 {
549 return nrf_event_check(p_reg, event);
550 }
551
nrf_rramc_event_address_get(NRF_RRAMC_Type const * p_reg,nrf_rramc_event_t event)552 NRF_STATIC_INLINE uint32_t nrf_rramc_event_address_get(NRF_RRAMC_Type const * p_reg,
553 nrf_rramc_event_t event)
554 {
555 return ((uint32_t)p_reg + (uint32_t)event);
556 }
557
nrf_rramc_int_enable(NRF_RRAMC_Type * p_reg,uint32_t mask)558 NRF_STATIC_INLINE void nrf_rramc_int_enable(NRF_RRAMC_Type * p_reg, uint32_t mask)
559 {
560 p_reg->INTENSET = mask;
561 }
562
nrf_rramc_int_disable(NRF_RRAMC_Type * p_reg,uint32_t mask)563 NRF_STATIC_INLINE void nrf_rramc_int_disable(NRF_RRAMC_Type * p_reg, uint32_t mask)
564 {
565 p_reg->INTENCLR = mask;
566 }
567
nrf_rramc_int_enable_check(NRF_RRAMC_Type const * p_reg,uint32_t mask)568 NRF_STATIC_INLINE uint32_t nrf_rramc_int_enable_check(NRF_RRAMC_Type const * p_reg,
569 uint32_t mask)
570 {
571 return p_reg->INTENSET & mask;
572 }
573
nrf_rramc_int_pending_get(NRF_RRAMC_Type const * p_reg)574 NRF_STATIC_INLINE uint32_t nrf_rramc_int_pending_get(NRF_RRAMC_Type const * p_reg)
575 {
576 return p_reg->INTPEND;
577 }
578
579 #if defined(DPPI_PRESENT)
nrf_rramc_subscribe_set(NRF_RRAMC_Type * p_reg,nrf_rramc_task_t task,uint8_t channel)580 NRF_STATIC_INLINE void nrf_rramc_subscribe_set(NRF_RRAMC_Type * p_reg,
581 nrf_rramc_task_t task,
582 uint8_t channel)
583 {
584 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
585 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
586 }
587
nrf_rramc_subscribe_clear(NRF_RRAMC_Type * p_reg,nrf_rramc_task_t task)588 NRF_STATIC_INLINE void nrf_rramc_subscribe_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_task_t task)
589 {
590 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
591 }
592
nrf_rramc_publish_set(NRF_RRAMC_Type * p_reg,nrf_rramc_event_t event,uint8_t channel)593 NRF_STATIC_INLINE void nrf_rramc_publish_set(NRF_RRAMC_Type * p_reg,
594 nrf_rramc_event_t event,
595 uint8_t channel)
596 {
597 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
598 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
599 }
600
nrf_rramc_publish_clear(NRF_RRAMC_Type * p_reg,nrf_rramc_event_t event)601 NRF_STATIC_INLINE void nrf_rramc_publish_clear(NRF_RRAMC_Type * p_reg, nrf_rramc_event_t event)
602 {
603 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
604 }
605 #endif // defined(DPPI_PRESENT)
606
nrf_rramc_ready_check(NRF_RRAMC_Type const * p_reg)607 NRF_STATIC_INLINE bool nrf_rramc_ready_check(NRF_RRAMC_Type const * p_reg)
608 {
609 return ((p_reg->READY & RRAMC_READY_READY_Msk) >>
610 RRAMC_READY_READY_Pos) ==
611 RRAMC_READY_READY_Ready;
612 }
613
nrf_rramc_write_ready_check(NRF_RRAMC_Type const * p_reg)614 NRF_STATIC_INLINE bool nrf_rramc_write_ready_check(NRF_RRAMC_Type const * p_reg)
615 {
616 return ((p_reg->READYNEXT & RRAMC_READYNEXT_READYNEXT_Msk) >>
617 RRAMC_READYNEXT_READYNEXT_Pos) ==
618 RRAMC_READYNEXT_READYNEXT_Ready;
619 }
620
nrf_rramc_error_access_addr_get(NRF_RRAMC_Type const * p_reg)621 NRF_STATIC_INLINE uint32_t nrf_rramc_error_access_addr_get(NRF_RRAMC_Type const * p_reg)
622 {
623 return (uint32_t)p_reg->ACCESSERRORADDR;
624 }
625
nrf_rramc_empty_buffer_check(NRF_RRAMC_Type const * p_reg)626 NRF_STATIC_INLINE bool nrf_rramc_empty_buffer_check(NRF_RRAMC_Type const * p_reg)
627 {
628 return ((p_reg->BUFSTATUS.WRITEBUFEMPTY & RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Msk) >>
629 RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Pos) ==
630 RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Empty;
631 }
632
nrf_rramc_config_get(NRF_RRAMC_Type const * p_reg,nrf_rramc_config_t * p_config)633 NRF_STATIC_INLINE void nrf_rramc_config_get(NRF_RRAMC_Type const * p_reg,
634 nrf_rramc_config_t * p_config)
635 {
636 p_config->mode_write = (bool)((p_reg->CONFIG & RRAMC_CONFIG_WEN_Msk) >>
637 RRAMC_CONFIG_WEN_Pos);
638 p_config->write_buff_size = (uint32_t)((p_reg->CONFIG & RRAMC_CONFIG_WRITEBUFSIZE_Msk) >>
639 RRAMC_CONFIG_WRITEBUFSIZE_Pos);
640 }
641
nrf_rramc_config_set(NRF_RRAMC_Type * p_reg,nrf_rramc_config_t const * p_config)642 NRF_STATIC_INLINE void nrf_rramc_config_set(NRF_RRAMC_Type * p_reg,
643 nrf_rramc_config_t const * p_config)
644 {
645 NRFX_ASSERT(p_config->write_buff_size <= NRF_RRAMC_CONFIG_WRITE_BUFF_SIZE_MAX);
646
647 p_reg->CONFIG = ((uint32_t)p_config->mode_write << RRAMC_CONFIG_WEN_Pos) |
648 ((uint32_t)p_config->write_buff_size << RRAMC_CONFIG_WRITEBUFSIZE_Pos);
649 }
650
nrf_rramc_ready_next_timeout_get(NRF_RRAMC_Type const * p_reg,nrf_rramc_ready_next_timeout_t * p_config)651 NRF_STATIC_INLINE void nrf_rramc_ready_next_timeout_get(NRF_RRAMC_Type const * p_reg,
652 nrf_rramc_ready_next_timeout_t * p_config)
653 {
654 p_config->value = (uint16_t)((p_reg->READYNEXTTIMEOUT & RRAMC_READYNEXTTIMEOUT_VALUE_Msk) >>
655 RRAMC_READYNEXTTIMEOUT_VALUE_Pos);
656 p_config->enable = ((p_reg->READYNEXTTIMEOUT & RRAMC_READYNEXTTIMEOUT_EN_Msk)
657 >> RRAMC_READYNEXTTIMEOUT_EN_Pos) == RRAMC_READYNEXTTIMEOUT_EN_Enable;
658 }
659
660 NRF_STATIC_INLINE void
nrf_rramc_ready_next_timeout_set(NRF_RRAMC_Type * p_reg,nrf_rramc_ready_next_timeout_t const * p_config)661 nrf_rramc_ready_next_timeout_set(NRF_RRAMC_Type * p_reg,
662 nrf_rramc_ready_next_timeout_t const * p_config)
663 {
664 NRFX_ASSERT(p_config->value <= NRF_RRAMC_READYNEXTTIMEOUT_MAX);
665
666 p_reg->READYNEXTTIMEOUT = ((uint32_t)p_config->value << RRAMC_READYNEXTTIMEOUT_VALUE_Pos) |
667 ((p_config->enable ? RRAMC_READYNEXTTIMEOUT_EN_Enable :
668 RRAMC_READYNEXTTIMEOUT_EN_Disable)
669 << RRAMC_READYNEXTTIMEOUT_EN_Pos);
670 }
671
nrf_rramc_power_config_get(NRF_RRAMC_Type const * p_reg,nrf_rramc_power_t * p_config)672 NRF_STATIC_INLINE void nrf_rramc_power_config_get(NRF_RRAMC_Type const * p_reg,
673 nrf_rramc_power_t * p_config)
674 {
675 p_config->access_timeout = (uint16_t)((p_reg->POWER.CONFIG &
676 RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Msk) >>
677 RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Pos);
678 p_config->abort_on_pof = ((p_reg->POWER.CONFIG &
679 RRAMC_POWER_CONFIG_POF_Msk) >>
680 RRAMC_POWER_CONFIG_POF_Pos) ==
681 RRAMC_POWER_CONFIG_POF_Abort;
682 }
683
nrf_rramc_power_config_set(NRF_RRAMC_Type * p_reg,nrf_rramc_power_t const * p_config)684 NRF_STATIC_INLINE void nrf_rramc_power_config_set(NRF_RRAMC_Type * p_reg,
685 nrf_rramc_power_t const * p_config)
686 {
687 p_reg->POWER.CONFIG =
688 ((uint32_t)p_config->access_timeout << RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Pos) |
689 ((uint32_t)p_config->abort_on_pof << RRAMC_POWER_CONFIG_POF_Pos);
690 }
691
nrf_rramc_erase_all_check(NRF_RRAMC_Type const * p_reg)692 NRF_STATIC_INLINE bool nrf_rramc_erase_all_check(NRF_RRAMC_Type const * p_reg)
693 {
694 return ((p_reg->ERASE.ERASEALL & RRAMC_ERASE_ERASEALL_ERASE_Msk) >>
695 RRAMC_ERASE_ERASEALL_ERASE_Pos) ==
696 RRAMC_ERASE_ERASEALL_ERASE_Erase;
697 }
698
nrf_rramc_erase_all_set(NRF_RRAMC_Type * p_reg)699 NRF_STATIC_INLINE void nrf_rramc_erase_all_set(NRF_RRAMC_Type * p_reg)
700 {
701 p_reg->ERASE.ERASEALL = RRAMC_ERASE_ERASEALL_ERASE_Erase;
702 }
703
nrf_rramc_region_config_set(NRF_RRAMC_Type * p_reg,uint8_t region,nrf_rramc_region_config_t const * p_config)704 NRF_STATIC_INLINE void nrf_rramc_region_config_set(NRF_RRAMC_Type * p_reg,
705 uint8_t region,
706 nrf_rramc_region_config_t const * p_config)
707 {
708 p_reg->REGION[region].ADDRESS = p_config->address;
709 p_reg->REGION[region].CONFIG = (((p_config->permissions
710 & NRF_RRAMC_REGION_CONFIG_PERM_MASK)) |
711 ((p_config->writeonce ? RRAMC_REGION_CONFIG_WRITEONCE_Enabled :
712 RRAMC_REGION_CONFIG_WRITEONCE_Disabled)
713 << RRAMC_REGION_CONFIG_WRITEONCE_Pos) |
714 ((p_config->lock ? RRAMC_REGION_CONFIG_LOCK_Enabled:
715 RRAMC_REGION_CONFIG_LOCK_Disabled)
716 << RRAMC_REGION_CONFIG_LOCK_Pos) |
717 ((p_config->size_kb << RRAMC_REGION_CONFIG_SIZE_Pos)
718 & RRAMC_REGION_CONFIG_SIZE_Msk));
719 }
720
nrf_rramc_region_config_get(NRF_RRAMC_Type const * p_reg,uint8_t region,nrf_rramc_region_config_t * p_config)721 NRF_STATIC_INLINE void nrf_rramc_region_config_get(NRF_RRAMC_Type const * p_reg,
722 uint8_t region,
723 nrf_rramc_region_config_t * p_config)
724 {
725 uint32_t reg = p_reg->REGION[region].CONFIG;
726 p_config->permissions = reg & NRF_RRAMC_REGION_CONFIG_PERM_MASK;
727 p_config->writeonce = ((reg & RRAMC_REGION_CONFIG_WRITEONCE_Msk)
728 >> RRAMC_REGION_CONFIG_WRITE_Pos) ==
729 RRAMC_REGION_CONFIG_WRITEONCE_Enabled;
730 p_config->lock = ((reg & RRAMC_REGION_CONFIG_LOCK_Msk)
731 >> RRAMC_REGION_CONFIG_LOCK_Pos) == RRAMC_REGION_CONFIG_LOCK_Enabled;
732 p_config->size_kb = (reg & RRAMC_REGION_CONFIG_SIZE_Msk) >> RRAMC_REGION_CONFIG_SIZE_Pos;
733 p_config->address = p_reg->REGION[region].ADDRESS;
734 }
735
nrf_rramc_region_config_raw_get(NRF_RRAMC_Type const * p_reg,uint8_t region)736 NRF_STATIC_INLINE uint32_t nrf_rramc_region_config_raw_get(NRF_RRAMC_Type const * p_reg,
737 uint8_t region)
738 {
739 return p_reg->REGION[region].CONFIG;
740 }
741
nrf_rramc_byte_write(uint32_t address,uint8_t value)742 NRF_STATIC_INLINE void nrf_rramc_byte_write(uint32_t address, uint8_t value)
743 {
744 *(volatile uint8_t *)address = value;
745 }
746
nrf_rramc_halfword_write(uint32_t address,uint16_t value)747 NRF_STATIC_INLINE void nrf_rramc_halfword_write(uint32_t address, uint16_t value)
748 {
749 *(volatile uint16_t *)address = value;
750 }
751
nrf_rramc_word_write(uint32_t address,uint32_t value)752 NRF_STATIC_INLINE void nrf_rramc_word_write(uint32_t address, uint32_t value)
753 {
754 *(volatile uint32_t *)address = value;
755 }
756
nrf_rramc_buffer_write(uint32_t address,void * src,uint32_t num_bytes)757 NRF_STATIC_INLINE void nrf_rramc_buffer_write(uint32_t address, void * src, uint32_t num_bytes)
758 {
759 memcpy((void *)address, src, num_bytes);
760 }
761
nrf_rramc_byte_read(uint32_t address)762 NRF_STATIC_INLINE uint8_t nrf_rramc_byte_read(uint32_t address)
763 {
764 return *(volatile uint8_t *)address;
765 }
766
nrf_rramc_halfword_read(uint32_t address)767 NRF_STATIC_INLINE uint16_t nrf_rramc_halfword_read(uint32_t address)
768 {
769 return *(volatile uint16_t *)address;
770 }
771
nrf_rramc_word_read(uint32_t address)772 NRF_STATIC_INLINE uint32_t nrf_rramc_word_read(uint32_t address)
773 {
774 return *(volatile uint32_t *)address;
775 }
776
nrf_rramc_buffer_read(void * dst,uint32_t address,uint32_t num_bytes)777 NRF_STATIC_INLINE void nrf_rramc_buffer_read(void * dst, uint32_t address, uint32_t num_bytes)
778 {
779 memcpy(dst, (void *)address, num_bytes);
780 }
781
782 #endif // NRF_DECLARE_ONLY
783
784 /** @} */
785
786 #ifdef __cplusplus
787 }
788 #endif
789
790 #endif // NRF_RRAM_H__
791
