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Searched refs:channels_mask (Results 1 – 7 of 7) sorted by relevance

/hal_nordic-latest/nrfx/helpers/
Dnrfx_gppi_dppi_ppib_lumos.c85 return nrfx_flag32_alloc(&p_dppic->channels_mask, p_channel); in dppic_channel_alloc()
94 return nrfx_flag32_free(&p_dppic->channels_mask, channel); in dppic_channel_free()
341 nrfx_atomic_t possible_mask = path.src_dppic->channels_mask; in gppi_dppi_connection_setup()
342 possible_mask &= path.dst_dppic->channels_mask; in gppi_dppi_connection_setup()
355 path.src_dppic->channels_mask &= ~NRFX_BIT(common_channel); in gppi_dppi_connection_setup()
356 path.dst_dppic->channels_mask &= ~NRFX_BIT(common_channel); in gppi_dppi_connection_setup()
418 nrfx_atomic_t possible_mask = p_src_dppic->channels_mask; in gppi_dppi_connection_setup()
419 possible_mask &= p_main_dppic->channels_mask; in gppi_dppi_connection_setup()
420 possible_mask &= p_dst_dppic->channels_mask; in gppi_dppi_connection_setup()
435 p_src_dppic->channels_mask &= ~NRFX_BIT(common_channel); in gppi_dppi_connection_setup()
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/hal_nordic-latest/nrfx/samples/src/nrfx_saadc/simple_blocking/
Dmain.c157 uint32_t channels_mask = 0; in main() local
168 channels_mask = nrfx_saadc_channels_configured_get(); in main()
169 status = nrfx_saadc_simple_mode_set(channels_mask, in main()
213 channels_mask = nrfx_saadc_channels_configured_get(); in main()
214 status = nrfx_saadc_simple_mode_set(channels_mask, in main()
/hal_nordic-latest/nrfx/samples/src/nrfx_saadc/simple_non_blocking/
Dmain.c199 uint32_t channels_mask = 0; in main() local
210 channels_mask = nrfx_saadc_channels_configured_get(); in main()
211 status = nrfx_saadc_simple_mode_set(channels_mask, in main()
248 channels_mask = nrfx_saadc_channels_configured_get(); in main()
249 status = nrfx_saadc_simple_mode_set(channels_mask, in main()
/hal_nordic-latest/nrfx/hal/
Dnrf_ipc.h299 uint32_t channels_mask);
326 uint32_t channels_mask);
454 uint32_t channels_mask) in nrf_ipc_send_config_set() argument
456 p_reg->SEND_CNF[index] = channels_mask; in nrf_ipc_send_config_set()
466 uint32_t channels_mask) in nrf_ipc_receive_config_set() argument
468 p_reg->RECEIVE_CNF[index] = channels_mask; in nrf_ipc_receive_config_set()
Dnrf_spu.h386 uint32_t channels_mask,
894 uint32_t channels_mask, in nrf_spu_dppi_config_set() argument
899 p_reg->DPPI[dppi_id].PERM = channels_mask; in nrf_spu_dppi_config_set()
/hal_nordic-latest/nrfx/soc/interconnect/dppic_ppib/
Dnrfx_interconnect_dppic_ppib.h73 nrfx_atomic_t channels_mask; ///< Mask of configurable DPPIC channels. member
Dnrfx_interconnect_dppic_ppib_lumos.h57 .channels_mask = NRFX_BIT_MASK(NRFX_CONCAT(DPPIC, idx, _CH_NUM))