1 /*
2 
3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef __NRF9120_BITS_H
36 #define __NRF9120_BITS_H
37 
38 /*lint ++flb "Enter library region" */
39 
40 /* Peripheral: APPROTECT */
41 /* Description: Access Port Protection 0 */
42 
43 /* Register: APPROTECT_SECUREAPPROTECT_DISABLE */
44 /* Description: Software disable SECUREAPPROTECT mechanism */
45 
46 /* Bits 7..0 : Software disable SECUREAPPROTECT mechanism */
47 #define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */
48 #define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */
49 #define APPROTECT_SECUREAPPROTECT_DISABLE_DISABLE_SwUnprotected (0x5AUL) /*!< Software disable SECUREAPPROTECT mechanism */
50 
51 /* Register: APPROTECT_SECUREAPPROTECT_FORCEPROTECT */
52 /* Description: Software force SECUREAPPROTECT mechanism */
53 
54 /* Bit 9 : Write 0x1 to force enable SECUREAPPROTECT mechanism */
55 #define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (9UL) /*!< Position of FORCEPROTECT field. */
56 #define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0x1UL << APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */
57 #define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x1UL) /*!< Software force enable SECUREAPPROTECT mechanism */
58 
59 /* Register: APPROTECT_APPROTECT_DISABLE */
60 /* Description: Software disable APPROTECT mechanism */
61 
62 /* Bits 7..0 : Software disable APPROTECT mechanism */
63 #define APPROTECT_APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */
64 #define APPROTECT_APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */
65 #define APPROTECT_APPROTECT_DISABLE_DISABLE_SwUnprotected (0x5AUL) /*!< Software disable APPROTECT mechanism */
66 
67 /* Register: APPROTECT_APPROTECT_FORCEPROTECT */
68 /* Description: Software force APPROTECT mechanism */
69 
70 /* Bit 9 : Write 0x1 to force enable APPROTECT mechanism */
71 #define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (9UL) /*!< Position of FORCEPROTECT field. */
72 #define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0x1UL << APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */
73 #define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x1UL) /*!< Software force enable APPROTECT mechanism */
74 
75 
76 /* Peripheral: ATBFUNNEL */
77 /* Description: ATB funnel module 0 */
78 
79 /* Register: ATBFUNNEL_CTRLREG */
80 /* Description: The IDFILTER0 register enables the programming of ID filtering for master port 0. */
81 
82 /* Bits 11..8 : Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you can use this setting to minimize switching.
83           When a source has nothing to transmit, then another source is selected irrespective of the minimum number of transactions.
84           The ATB funnel holds for the minimum hold time and one additional transaction. The actual hold time is the register value plus 1.
85           The maximum value that can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved. */
86 #define ATBFUNNEL_CTRLREG_HT_Pos (8UL) /*!< Position of HT field. */
87 #define ATBFUNNEL_CTRLREG_HT_Msk (0xFUL << ATBFUNNEL_CTRLREG_HT_Pos) /*!< Bit mask of HT field. */
88 
89 /* Bit 7 : Enable slave port 7. */
90 #define ATBFUNNEL_CTRLREG_ENS_7_Pos (7UL) /*!< Position of ENS_7 field. */
91 #define ATBFUNNEL_CTRLREG_ENS_7_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_7_Pos) /*!< Bit mask of ENS_7 field. */
92 #define ATBFUNNEL_CTRLREG_ENS_7_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */
93 #define ATBFUNNEL_CTRLREG_ENS_7_Enabled (0x1UL) /*!< Slave port enabled. */
94 
95 /* Bit 6 : Enable slave port 6. */
96 #define ATBFUNNEL_CTRLREG_ENS_6_Pos (6UL) /*!< Position of ENS_6 field. */
97 #define ATBFUNNEL_CTRLREG_ENS_6_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_6_Pos) /*!< Bit mask of ENS_6 field. */
98 #define ATBFUNNEL_CTRLREG_ENS_6_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */
99 #define ATBFUNNEL_CTRLREG_ENS_6_Enabled (0x1UL) /*!< Slave port enabled. */
100 
101 /* Bit 5 : Enable slave port 5. */
102 #define ATBFUNNEL_CTRLREG_ENS_5_Pos (5UL) /*!< Position of ENS_5 field. */
103 #define ATBFUNNEL_CTRLREG_ENS_5_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_5_Pos) /*!< Bit mask of ENS_5 field. */
104 #define ATBFUNNEL_CTRLREG_ENS_5_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */
105 #define ATBFUNNEL_CTRLREG_ENS_5_Enabled (0x1UL) /*!< Slave port enabled. */
106 
107 /* Bit 4 : Enable slave port 4. */
108 #define ATBFUNNEL_CTRLREG_ENS_4_Pos (4UL) /*!< Position of ENS_4 field. */
109 #define ATBFUNNEL_CTRLREG_ENS_4_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_4_Pos) /*!< Bit mask of ENS_4 field. */
110 #define ATBFUNNEL_CTRLREG_ENS_4_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */
111 #define ATBFUNNEL_CTRLREG_ENS_4_Enabled (0x1UL) /*!< Slave port enabled. */
112 
113 /* Bit 3 : Enable slave port 3. */
114 #define ATBFUNNEL_CTRLREG_ENS_3_Pos (3UL) /*!< Position of ENS_3 field. */
115 #define ATBFUNNEL_CTRLREG_ENS_3_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_3_Pos) /*!< Bit mask of ENS_3 field. */
116 #define ATBFUNNEL_CTRLREG_ENS_3_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */
117 #define ATBFUNNEL_CTRLREG_ENS_3_Enabled (0x1UL) /*!< Slave port enabled. */
118 
119 /* Bit 2 : Enable slave port 2. */
120 #define ATBFUNNEL_CTRLREG_ENS_2_Pos (2UL) /*!< Position of ENS_2 field. */
121 #define ATBFUNNEL_CTRLREG_ENS_2_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_2_Pos) /*!< Bit mask of ENS_2 field. */
122 #define ATBFUNNEL_CTRLREG_ENS_2_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */
123 #define ATBFUNNEL_CTRLREG_ENS_2_Enabled (0x1UL) /*!< Slave port enabled. */
124 
125 /* Bit 1 : Enable slave port 1. */
126 #define ATBFUNNEL_CTRLREG_ENS_1_Pos (1UL) /*!< Position of ENS_1 field. */
127 #define ATBFUNNEL_CTRLREG_ENS_1_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_1_Pos) /*!< Bit mask of ENS_1 field. */
128 #define ATBFUNNEL_CTRLREG_ENS_1_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */
129 #define ATBFUNNEL_CTRLREG_ENS_1_Enabled (0x1UL) /*!< Slave port enabled. */
130 
131 /* Bit 0 : Enable slave port 0. */
132 #define ATBFUNNEL_CTRLREG_ENS_0_Pos (0UL) /*!< Position of ENS_0 field. */
133 #define ATBFUNNEL_CTRLREG_ENS_0_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_0_Pos) /*!< Bit mask of ENS_0 field. */
134 #define ATBFUNNEL_CTRLREG_ENS_0_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */
135 #define ATBFUNNEL_CTRLREG_ENS_0_Enabled (0x1UL) /*!< Slave port enabled. */
136 
137 /* Register: ATBFUNNEL_PRIORITYCTRLREG */
138 /* Description: The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-bit field is a priority for each particular slave interface. */
139 
140 /* Bits 23..21 : Priority value of port number 7. */
141 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Pos (21UL) /*!< Position of PRIPORT7 field. */
142 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Pos) /*!< Bit mask of PRIPORT7 field. */
143 
144 /* Bits 20..18 : Priority value of port number 6. */
145 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Pos (18UL) /*!< Position of PRIPORT6 field. */
146 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Pos) /*!< Bit mask of PRIPORT6 field. */
147 
148 /* Bits 17..15 : Priority value of port number 5. */
149 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Pos (15UL) /*!< Position of PRIPORT5 field. */
150 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Pos) /*!< Bit mask of PRIPORT5 field. */
151 
152 /* Bits 14..12 : Priority value of port number 4. */
153 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Pos (12UL) /*!< Position of PRIPORT4 field. */
154 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Pos) /*!< Bit mask of PRIPORT4 field. */
155 
156 /* Bits 11..9 : Priority value of port number 3. */
157 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Pos (9UL) /*!< Position of PRIPORT3 field. */
158 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Pos) /*!< Bit mask of PRIPORT3 field. */
159 
160 /* Bits 8..6 : Priority value of port number 2. */
161 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Pos (6UL) /*!< Position of PRIPORT2 field. */
162 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Pos) /*!< Bit mask of PRIPORT2 field. */
163 
164 /* Bits 5..3 : Priority value of port number 1. */
165 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Pos (3UL) /*!< Position of PRIPORT1 field. */
166 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Pos) /*!< Bit mask of PRIPORT1 field. */
167 
168 /* Bits 2..0 : Priority value of port number 0. */
169 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Pos (0UL) /*!< Position of PRIPORT0 field. */
170 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Pos) /*!< Bit mask of PRIPORT0 field. */
171 
172 /* Register: ATBFUNNEL_ITATBDATA0 */
173 /* Description: The ITATBDATA0 register performs different functions depending on whether the access is a read or a write. */
174 
175 /* Bit 16 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
176 #define ATBFUNNEL_ITATBDATA0_ATDATA_16_Pos (16UL) /*!< Position of ATDATA_16 field. */
177 #define ATBFUNNEL_ITATBDATA0_ATDATA_16_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_16_Pos) /*!< Bit mask of ATDATA_16 field. */
178 #define ATBFUNNEL_ITATBDATA0_ATDATA_16_Low (0x0UL) /*!< Pin is logic 0. */
179 #define ATBFUNNEL_ITATBDATA0_ATDATA_16_High (0x1UL) /*!< Pin is logic 1. */
180 
181 /* Bit 15 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
182 #define ATBFUNNEL_ITATBDATA0_ATDATA_15_Pos (15UL) /*!< Position of ATDATA_15 field. */
183 #define ATBFUNNEL_ITATBDATA0_ATDATA_15_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_15_Pos) /*!< Bit mask of ATDATA_15 field. */
184 #define ATBFUNNEL_ITATBDATA0_ATDATA_15_Low (0x0UL) /*!< Pin is logic 0. */
185 #define ATBFUNNEL_ITATBDATA0_ATDATA_15_High (0x1UL) /*!< Pin is logic 1. */
186 
187 /* Bit 14 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
188 #define ATBFUNNEL_ITATBDATA0_ATDATA_14_Pos (14UL) /*!< Position of ATDATA_14 field. */
189 #define ATBFUNNEL_ITATBDATA0_ATDATA_14_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_14_Pos) /*!< Bit mask of ATDATA_14 field. */
190 #define ATBFUNNEL_ITATBDATA0_ATDATA_14_Low (0x0UL) /*!< Pin is logic 0. */
191 #define ATBFUNNEL_ITATBDATA0_ATDATA_14_High (0x1UL) /*!< Pin is logic 1. */
192 
193 /* Bit 13 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
194 #define ATBFUNNEL_ITATBDATA0_ATDATA_13_Pos (13UL) /*!< Position of ATDATA_13 field. */
195 #define ATBFUNNEL_ITATBDATA0_ATDATA_13_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_13_Pos) /*!< Bit mask of ATDATA_13 field. */
196 #define ATBFUNNEL_ITATBDATA0_ATDATA_13_Low (0x0UL) /*!< Pin is logic 0. */
197 #define ATBFUNNEL_ITATBDATA0_ATDATA_13_High (0x1UL) /*!< Pin is logic 1. */
198 
199 /* Bit 12 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
200 #define ATBFUNNEL_ITATBDATA0_ATDATA_12_Pos (12UL) /*!< Position of ATDATA_12 field. */
201 #define ATBFUNNEL_ITATBDATA0_ATDATA_12_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_12_Pos) /*!< Bit mask of ATDATA_12 field. */
202 #define ATBFUNNEL_ITATBDATA0_ATDATA_12_Low (0x0UL) /*!< Pin is logic 0. */
203 #define ATBFUNNEL_ITATBDATA0_ATDATA_12_High (0x1UL) /*!< Pin is logic 1. */
204 
205 /* Bit 11 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
206 #define ATBFUNNEL_ITATBDATA0_ATDATA_11_Pos (11UL) /*!< Position of ATDATA_11 field. */
207 #define ATBFUNNEL_ITATBDATA0_ATDATA_11_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_11_Pos) /*!< Bit mask of ATDATA_11 field. */
208 #define ATBFUNNEL_ITATBDATA0_ATDATA_11_Low (0x0UL) /*!< Pin is logic 0. */
209 #define ATBFUNNEL_ITATBDATA0_ATDATA_11_High (0x1UL) /*!< Pin is logic 1. */
210 
211 /* Bit 10 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
212 #define ATBFUNNEL_ITATBDATA0_ATDATA_10_Pos (10UL) /*!< Position of ATDATA_10 field. */
213 #define ATBFUNNEL_ITATBDATA0_ATDATA_10_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_10_Pos) /*!< Bit mask of ATDATA_10 field. */
214 #define ATBFUNNEL_ITATBDATA0_ATDATA_10_Low (0x0UL) /*!< Pin is logic 0. */
215 #define ATBFUNNEL_ITATBDATA0_ATDATA_10_High (0x1UL) /*!< Pin is logic 1. */
216 
217 /* Bit 9 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
218 #define ATBFUNNEL_ITATBDATA0_ATDATA_9_Pos (9UL) /*!< Position of ATDATA_9 field. */
219 #define ATBFUNNEL_ITATBDATA0_ATDATA_9_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_9_Pos) /*!< Bit mask of ATDATA_9 field. */
220 #define ATBFUNNEL_ITATBDATA0_ATDATA_9_Low (0x0UL) /*!< Pin is logic 0. */
221 #define ATBFUNNEL_ITATBDATA0_ATDATA_9_High (0x1UL) /*!< Pin is logic 1. */
222 
223 /* Bit 8 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
224 #define ATBFUNNEL_ITATBDATA0_ATDATA_8_Pos (8UL) /*!< Position of ATDATA_8 field. */
225 #define ATBFUNNEL_ITATBDATA0_ATDATA_8_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_8_Pos) /*!< Bit mask of ATDATA_8 field. */
226 #define ATBFUNNEL_ITATBDATA0_ATDATA_8_Low (0x0UL) /*!< Pin is logic 0. */
227 #define ATBFUNNEL_ITATBDATA0_ATDATA_8_High (0x1UL) /*!< Pin is logic 1. */
228 
229 /* Bit 7 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
230 #define ATBFUNNEL_ITATBDATA0_ATDATA_7_Pos (7UL) /*!< Position of ATDATA_7 field. */
231 #define ATBFUNNEL_ITATBDATA0_ATDATA_7_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_7_Pos) /*!< Bit mask of ATDATA_7 field. */
232 #define ATBFUNNEL_ITATBDATA0_ATDATA_7_Low (0x0UL) /*!< Pin is logic 0. */
233 #define ATBFUNNEL_ITATBDATA0_ATDATA_7_High (0x1UL) /*!< Pin is logic 1. */
234 
235 /* Bit 6 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
236 #define ATBFUNNEL_ITATBDATA0_ATDATA_6_Pos (6UL) /*!< Position of ATDATA_6 field. */
237 #define ATBFUNNEL_ITATBDATA0_ATDATA_6_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_6_Pos) /*!< Bit mask of ATDATA_6 field. */
238 #define ATBFUNNEL_ITATBDATA0_ATDATA_6_Low (0x0UL) /*!< Pin is logic 0. */
239 #define ATBFUNNEL_ITATBDATA0_ATDATA_6_High (0x1UL) /*!< Pin is logic 1. */
240 
241 /* Bit 5 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
242 #define ATBFUNNEL_ITATBDATA0_ATDATA_5_Pos (5UL) /*!< Position of ATDATA_5 field. */
243 #define ATBFUNNEL_ITATBDATA0_ATDATA_5_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_5_Pos) /*!< Bit mask of ATDATA_5 field. */
244 #define ATBFUNNEL_ITATBDATA0_ATDATA_5_Low (0x0UL) /*!< Pin is logic 0. */
245 #define ATBFUNNEL_ITATBDATA0_ATDATA_5_High (0x1UL) /*!< Pin is logic 1. */
246 
247 /* Bit 4 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
248 #define ATBFUNNEL_ITATBDATA0_ATDATA_4_Pos (4UL) /*!< Position of ATDATA_4 field. */
249 #define ATBFUNNEL_ITATBDATA0_ATDATA_4_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_4_Pos) /*!< Bit mask of ATDATA_4 field. */
250 #define ATBFUNNEL_ITATBDATA0_ATDATA_4_Low (0x0UL) /*!< Pin is logic 0. */
251 #define ATBFUNNEL_ITATBDATA0_ATDATA_4_High (0x1UL) /*!< Pin is logic 1. */
252 
253 /* Bit 3 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
254 #define ATBFUNNEL_ITATBDATA0_ATDATA_3_Pos (3UL) /*!< Position of ATDATA_3 field. */
255 #define ATBFUNNEL_ITATBDATA0_ATDATA_3_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_3_Pos) /*!< Bit mask of ATDATA_3 field. */
256 #define ATBFUNNEL_ITATBDATA0_ATDATA_3_Low (0x0UL) /*!< Pin is logic 0. */
257 #define ATBFUNNEL_ITATBDATA0_ATDATA_3_High (0x1UL) /*!< Pin is logic 1. */
258 
259 /* Bit 2 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
260 #define ATBFUNNEL_ITATBDATA0_ATDATA_2_Pos (2UL) /*!< Position of ATDATA_2 field. */
261 #define ATBFUNNEL_ITATBDATA0_ATDATA_2_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_2_Pos) /*!< Bit mask of ATDATA_2 field. */
262 #define ATBFUNNEL_ITATBDATA0_ATDATA_2_Low (0x0UL) /*!< Pin is logic 0. */
263 #define ATBFUNNEL_ITATBDATA0_ATDATA_2_High (0x1UL) /*!< Pin is logic 1. */
264 
265 /* Bit 1 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
266 #define ATBFUNNEL_ITATBDATA0_ATDATA_1_Pos (1UL) /*!< Position of ATDATA_1 field. */
267 #define ATBFUNNEL_ITATBDATA0_ATDATA_1_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_1_Pos) /*!< Bit mask of ATDATA_1 field. */
268 #define ATBFUNNEL_ITATBDATA0_ATDATA_1_Low (0x0UL) /*!< Pin is logic 0. */
269 #define ATBFUNNEL_ITATBDATA0_ATDATA_1_High (0x1UL) /*!< Pin is logic 1. */
270 
271 /* Bit 0 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
272 #define ATBFUNNEL_ITATBDATA0_ATDATA_0_Pos (0UL) /*!< Position of ATDATA_0 field. */
273 #define ATBFUNNEL_ITATBDATA0_ATDATA_0_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_0_Pos) /*!< Bit mask of ATDATA_0 field. */
274 #define ATBFUNNEL_ITATBDATA0_ATDATA_0_Low (0x0UL) /*!< Pin is logic 0. */
275 #define ATBFUNNEL_ITATBDATA0_ATDATA_0_High (0x1UL) /*!< Pin is logic 1. */
276 
277 /* Register: ATBFUNNEL_ITATBCTR2 */
278 /* Description: The ITATBCTR2 register performs different functions depending on whether the access is a read or a write. */
279 
280 /* Bit 1 : A read access returns the value of afvalidm.
281         A write access outputs the data to atreadys[n], where the value of the CTRLREG at 0x000 defines n. */
282 #define ATBFUNNEL_ITATBCTR2_AFVALID_Pos (1UL) /*!< Position of AFVALID field. */
283 #define ATBFUNNEL_ITATBCTR2_AFVALID_Msk (0x1UL << ATBFUNNEL_ITATBCTR2_AFVALID_Pos) /*!< Bit mask of AFVALID field. */
284 #define ATBFUNNEL_ITATBCTR2_AFVALID_Low (0x0UL) /*!< Pin is logic 0. */
285 #define ATBFUNNEL_ITATBCTR2_AFVALID_High (0x1UL) /*!< Pin is logic 1. */
286 
287 /* Bit 0 : A read access returns the value of atreadym.
288         A write access outputs the data to afvalids[n], where the value of the CTRLREG at 0x000 defines n. */
289 #define ATBFUNNEL_ITATBCTR2_ATREADY_Pos (0UL) /*!< Position of ATREADY field. */
290 #define ATBFUNNEL_ITATBCTR2_ATREADY_Msk (0x1UL << ATBFUNNEL_ITATBCTR2_ATREADY_Pos) /*!< Bit mask of ATREADY field. */
291 #define ATBFUNNEL_ITATBCTR2_ATREADY_Low (0x0UL) /*!< Pin is logic 0. */
292 #define ATBFUNNEL_ITATBCTR2_ATREADY_High (0x1UL) /*!< Pin is logic 1. */
293 
294 /* Register: ATBFUNNEL_ITATBCTR1 */
295 /* Description: The ITATBCTR1 register performs different functions depending on whether the access is a read or a write. */
296 
297 /* Bits 6..0 : A read returns the value of the atids[n] signals, where the value of the Control Register at 0x000 defines n.
298 A write outputs the value to the atidm port. */
299 #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Pos (0UL) /*!< Position of ATVALIDM0 field. */
300 #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Msk (0x7FUL << ATBFUNNEL_ITATBCTR1_ATVALIDM0_Pos) /*!< Bit mask of ATVALIDM0 field. */
301 #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Low (0x00UL) /*!< Pin is logic 0. */
302 #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_High (0x01UL) /*!< Pin is logic 1. */
303 
304 /* Register: ATBFUNNEL_ITATBCTR0 */
305 /* Description: The ITATBCTR0 register performs different functions depending on whether the access is a read or a write. */
306 
307 /* Bits 9..8 : A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg at 0x000 defines n.
308 A write outputs the value to atbytesm. */
309 #define ATBFUNNEL_ITATBCTR0_ATBYTES_Pos (8UL) /*!< Position of ATBYTES field. */
310 #define ATBFUNNEL_ITATBCTR0_ATBYTES_Msk (0x3UL << ATBFUNNEL_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field. */
311 #define ATBFUNNEL_ITATBCTR0_ATBYTES_Low (0x0UL) /*!< Pin is logic 0. */
312 #define ATBFUNNEL_ITATBCTR0_ATBYTES_High (0x1UL) /*!< Pin is logic 1. */
313 
314 /* Bit 2 : A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg at 0x000 defines n.
315 A write outputs the value to afreadym. */
316 #define ATBFUNNEL_ITATBCTR0_AFREADY_Pos (2UL) /*!< Position of AFREADY field. */
317 #define ATBFUNNEL_ITATBCTR0_AFREADY_Msk (0x1UL << ATBFUNNEL_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field. */
318 #define ATBFUNNEL_ITATBCTR0_AFREADY_Low (0x0UL) /*!< Pin is logic 0. */
319 #define ATBFUNNEL_ITATBCTR0_AFREADY_High (0x1UL) /*!< Pin is logic 1. */
320 
321 /* Bit 0 : A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at 0x000 defines n.
322 A write outputs the value to atvalidm. */
323 #define ATBFUNNEL_ITATBCTR0_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */
324 #define ATBFUNNEL_ITATBCTR0_ATVALID_Msk (0x1UL << ATBFUNNEL_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field. */
325 #define ATBFUNNEL_ITATBCTR0_ATVALID_Low (0x0UL) /*!< Pin is logic 0. */
326 #define ATBFUNNEL_ITATBCTR0_ATVALID_High (0x1UL) /*!< Pin is logic 1. */
327 
328 /* Register: ATBFUNNEL_ITCTRL */
329 /* Description: The ITCTRL register enables the component to switch from a functional mode, which is the default behavior,
330       to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. */
331 
332 /* Bit 0 : Integration Mode Enable. */
333 #define ATBFUNNEL_ITCTRL_IME_Pos (0UL) /*!< Position of IME field. */
334 #define ATBFUNNEL_ITCTRL_IME_Msk (0x1UL << ATBFUNNEL_ITCTRL_IME_Pos) /*!< Bit mask of IME field. */
335 #define ATBFUNNEL_ITCTRL_IME_Disabled (0x0UL) /*!< Integration mode disabled. */
336 #define ATBFUNNEL_ITCTRL_IME_Enabled (0x1UL) /*!< Integration mode enabled. */
337 
338 /* Register: ATBFUNNEL_CLAIMSET */
339 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality.
340       The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. */
341 
342 /* Bit 3 : Set claim bit 3 and check if bit is implemented or not. */
343 #define ATBFUNNEL_CLAIMSET_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */
344 #define ATBFUNNEL_CLAIMSET_BIT_3_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */
345 #define ATBFUNNEL_CLAIMSET_BIT_3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented. */
346 #define ATBFUNNEL_CLAIMSET_BIT_3_Implemented (0x1UL) /*!< Claim bit 3 is implemented. */
347 #define ATBFUNNEL_CLAIMSET_BIT_3_Set (0x1UL) /*!< Set claim bit 3. */
348 
349 /* Bit 2 : Set claim bit 2 and check if bit is implemented or not. */
350 #define ATBFUNNEL_CLAIMSET_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */
351 #define ATBFUNNEL_CLAIMSET_BIT_2_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */
352 #define ATBFUNNEL_CLAIMSET_BIT_2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented. */
353 #define ATBFUNNEL_CLAIMSET_BIT_2_Implemented (0x1UL) /*!< Claim bit 2 is implemented. */
354 #define ATBFUNNEL_CLAIMSET_BIT_2_Set (0x1UL) /*!< Set claim bit 2. */
355 
356 /* Bit 1 : Set claim bit 1 and check if bit is implemented or not. */
357 #define ATBFUNNEL_CLAIMSET_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */
358 #define ATBFUNNEL_CLAIMSET_BIT_1_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */
359 #define ATBFUNNEL_CLAIMSET_BIT_1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented. */
360 #define ATBFUNNEL_CLAIMSET_BIT_1_Implemented (0x1UL) /*!< Claim bit 1 is implemented. */
361 #define ATBFUNNEL_CLAIMSET_BIT_1_Set (0x1UL) /*!< Set claim bit 1. */
362 
363 /* Bit 0 : Set claim bit 0 and check if bit is implemented or not. */
364 #define ATBFUNNEL_CLAIMSET_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */
365 #define ATBFUNNEL_CLAIMSET_BIT_0_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */
366 #define ATBFUNNEL_CLAIMSET_BIT_0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented. */
367 #define ATBFUNNEL_CLAIMSET_BIT_0_Implemented (0x1UL) /*!< Claim bit 0 is implemented. */
368 #define ATBFUNNEL_CLAIMSET_BIT_0_Set (0x1UL) /*!< Set claim bit 0. */
369 
370 /* Register: ATBFUNNEL_CLAIMCLR */
371 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality.
372       The claim tags have no effect on the operation of the component.
373       The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. */
374 
375 /* Bit 3 : Read or clear claim bit 3. */
376 #define ATBFUNNEL_CLAIMCLR_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */
377 #define ATBFUNNEL_CLAIMCLR_BIT_3_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */
378 #define ATBFUNNEL_CLAIMCLR_BIT_3_Cleared (0x0UL) /*!< Claim bit 3 is not set. */
379 #define ATBFUNNEL_CLAIMCLR_BIT_3_Set (0x1UL) /*!< Claim bit 3 is set. */
380 #define ATBFUNNEL_CLAIMCLR_BIT_3_Clear (0x1UL) /*!< Clear claim bit 3. */
381 
382 /* Bit 2 : Read or clear claim bit 2. */
383 #define ATBFUNNEL_CLAIMCLR_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */
384 #define ATBFUNNEL_CLAIMCLR_BIT_2_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */
385 #define ATBFUNNEL_CLAIMCLR_BIT_2_Cleared (0x0UL) /*!< Claim bit 2 is not set. */
386 #define ATBFUNNEL_CLAIMCLR_BIT_2_Set (0x1UL) /*!< Claim bit 2 is set. */
387 #define ATBFUNNEL_CLAIMCLR_BIT_2_Clear (0x1UL) /*!< Clear claim bit 2. */
388 
389 /* Bit 1 : Read or clear claim bit 1. */
390 #define ATBFUNNEL_CLAIMCLR_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */
391 #define ATBFUNNEL_CLAIMCLR_BIT_1_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */
392 #define ATBFUNNEL_CLAIMCLR_BIT_1_Cleared (0x0UL) /*!< Claim bit 1 is not set. */
393 #define ATBFUNNEL_CLAIMCLR_BIT_1_Set (0x1UL) /*!< Claim bit 1 is set. */
394 #define ATBFUNNEL_CLAIMCLR_BIT_1_Clear (0x1UL) /*!< Clear claim bit 1. */
395 
396 /* Bit 0 : Read or clear claim bit 0. */
397 #define ATBFUNNEL_CLAIMCLR_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */
398 #define ATBFUNNEL_CLAIMCLR_BIT_0_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */
399 #define ATBFUNNEL_CLAIMCLR_BIT_0_Cleared (0x0UL) /*!< Claim bit 0 is not set. */
400 #define ATBFUNNEL_CLAIMCLR_BIT_0_Set (0x1UL) /*!< Claim bit 0 is set. */
401 #define ATBFUNNEL_CLAIMCLR_BIT_0_Clear (0x1UL) /*!< Clear claim bit 0. */
402 
403 /* Register: ATBFUNNEL_LAR */
404 /* Description: This is used to enable write access to device registers. */
405 
406 /* Bits 31..0 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. */
407 #define ATBFUNNEL_LAR_ACCESS_Pos (0UL) /*!< Position of ACCESS field. */
408 #define ATBFUNNEL_LAR_ACCESS_Msk (0xFFFFFFFFUL << ATBFUNNEL_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field. */
409 #define ATBFUNNEL_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface. */
410 
411 /* Register: ATBFUNNEL_LSR */
412 /* Description: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug.
413       Accesses to the extended stimulus port registers are not affected by the lock mechanism.
414       This register must always be present although there might not be any lock access control mechanism.
415       The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register.
416       For most components this covers all registers except for the Lock Access Register. */
417 
418 /* Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */
419 #define ATBFUNNEL_LSR_TYPE_Pos (2UL) /*!< Position of TYPE field. */
420 #define ATBFUNNEL_LSR_TYPE_Msk (0x1UL << ATBFUNNEL_LSR_TYPE_Pos) /*!< Bit mask of TYPE field. */
421 #define ATBFUNNEL_LSR_TYPE_Bits32 (0x0UL) /*!< This component implements a 32-bit Lock Access Register. */
422 #define ATBFUNNEL_LSR_TYPE_Bits8 (0x1UL) /*!< This component implements an 8-bit Lock Access Register. */
423 
424 /* Bit 1 : Returns the current status of the Lock. */
425 #define ATBFUNNEL_LSR_LOCKED_Pos (1UL) /*!< Position of LOCKED field. */
426 #define ATBFUNNEL_LSR_LOCKED_Msk (0x1UL << ATBFUNNEL_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */
427 #define ATBFUNNEL_LSR_LOCKED_UnLocked (0x0UL) /*!< Write access is allowed to this device. */
428 #define ATBFUNNEL_LSR_LOCKED_Locked (0x1UL) /*!< Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. */
429 
430 /* Bit 0 : Indicates that a lock control mechanism exists for this device. */
431 #define ATBFUNNEL_LSR_PRESENT_Pos (0UL) /*!< Position of PRESENT field. */
432 #define ATBFUNNEL_LSR_PRESENT_Msk (0x1UL << ATBFUNNEL_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field. */
433 #define ATBFUNNEL_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access Register are ignored. */
434 #define ATBFUNNEL_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present. */
435 
436 /* Register: ATBFUNNEL_AUTHSTATUS */
437 /* Description: Indicates the current level of tracing permitted by the system */
438 
439 /* Bits 7..6 : Secure Non-Invasive Debug */
440 #define ATBFUNNEL_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */
441 #define ATBFUNNEL_AUTHSTATUS_SNID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */
442 #define ATBFUNNEL_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
443 #define ATBFUNNEL_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */
444 
445 /* Bits 5..4 : Secure Invasive Debug */
446 #define ATBFUNNEL_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */
447 #define ATBFUNNEL_AUTHSTATUS_SID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */
448 #define ATBFUNNEL_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
449 #define ATBFUNNEL_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */
450 
451 /* Bits 3..2 : Non-secure Non-Invasive Debug */
452 #define ATBFUNNEL_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */
453 #define ATBFUNNEL_AUTHSTATUS_NSNID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */
454 #define ATBFUNNEL_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
455 #define ATBFUNNEL_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */
456 
457 /* Bits 1..0 : Non-secure Invasive Debug */
458 #define ATBFUNNEL_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */
459 #define ATBFUNNEL_AUTHSTATUS_NSID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */
460 #define ATBFUNNEL_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
461 #define ATBFUNNEL_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */
462 
463 /* Register: ATBFUNNEL_DEVID */
464 /* Description: Indicates the capabilities of the component. */
465 
466 /* Bits 3..0 : Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. */
467 #define ATBFUNNEL_DEVID_PORTCOUNT_Pos (0UL) /*!< Position of PORTCOUNT field. */
468 #define ATBFUNNEL_DEVID_PORTCOUNT_Msk (0xFUL << ATBFUNNEL_DEVID_PORTCOUNT_Pos) /*!< Bit mask of PORTCOUNT field. */
469 
470 /* Register: ATBFUNNEL_DEVTYPE */
471 /* Description: The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. */
472 
473 /* Bits 7..4 : The sub-type of the component */
474 #define ATBFUNNEL_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */
475 #define ATBFUNNEL_DEVTYPE_SUB_Msk (0xFUL << ATBFUNNEL_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */
476 #define ATBFUNNEL_DEVTYPE_SUB_Replicator (0x1UL) /*!< This component arbitrates ATB inputs mapping to ATB outputs. */
477 
478 /* Bits 3..0 : The main type of the component */
479 #define ATBFUNNEL_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */
480 #define ATBFUNNEL_DEVTYPE_MAJOR_Msk (0xFUL << ATBFUNNEL_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */
481 #define ATBFUNNEL_DEVTYPE_MAJOR_InputOutputDevice (0x2UL) /*!< Indicates that this component has ATB inputs and outputs. */
482 
483 
484 /* Peripheral: ATBREPLICATOR */
485 /* Description: ATB Replicator module */
486 
487 /* Register: ATBREPLICATOR_IDFILTER0 */
488 /* Description: The IDFILTER0 register enables the programming of ID filtering for master port 0. */
489 
490 /* Bit 7 : Enable or disable ID filtering for IDs 0x70_0x7F. */
491 #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Pos (7UL) /*!< Position of ID0_70_7F field. */
492 #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_70_7F_Pos) /*!< Bit mask of ID0_70_7F field. */
493 #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */
494 #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
495 
496 /* Bit 6 : Enable or disable ID filtering for IDs 0x60_0x6F. */
497 #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Pos (6UL) /*!< Position of ID0_60_6F field. */
498 #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_60_6F_Pos) /*!< Bit mask of ID0_60_6F field. */
499 #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */
500 #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
501 
502 /* Bit 5 : Enable or disable ID filtering for IDs 0x50_0x5F. */
503 #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Pos (5UL) /*!< Position of ID0_50_5F field. */
504 #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_50_5F_Pos) /*!< Bit mask of ID0_50_5F field. */
505 #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */
506 #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
507 
508 /* Bit 4 : Enable or disable ID filtering for IDs 0x40_0x4F. */
509 #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Pos (4UL) /*!< Position of ID0_40_4F field. */
510 #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_40_4F_Pos) /*!< Bit mask of ID0_40_4F field. */
511 #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */
512 #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
513 
514 /* Bit 3 : Enable or disable ID filtering for IDs 0x30_0x3F. */
515 #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Pos (3UL) /*!< Position of ID0_30_3F field. */
516 #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_30_3F_Pos) /*!< Bit mask of ID0_30_3F field. */
517 #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */
518 #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
519 
520 /* Bit 2 : Enable or disable ID filtering for IDs 0x20_0x2F. */
521 #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Pos (2UL) /*!< Position of ID0_20_2F field. */
522 #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_20_2F_Pos) /*!< Bit mask of ID0_20_2F field. */
523 #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */
524 #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
525 
526 /* Bit 1 : Enable or disable ID filtering for IDs 0x10_0x1F. */
527 #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Pos (1UL) /*!< Position of ID0_10_1F field. */
528 #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_10_1F_Pos) /*!< Bit mask of ID0_10_1F field. */
529 #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */
530 #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
531 
532 /* Bit 0 : Enable or disable ID filtering for IDs 0x00_0x0F. */
533 #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Pos (0UL) /*!< Position of ID0_00_0F field. */
534 #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_00_0F_Pos) /*!< Bit mask of ID0_00_0F field. */
535 #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */
536 #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
537 
538 /* Register: ATBREPLICATOR_IDFILTER1 */
539 /* Description: The IDFILTER1 register enables the programming of ID filtering for master port 1. */
540 
541 /* Bit 7 : Enable or disable ID filtering for IDs 0x70_0x7F. */
542 #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Pos (7UL) /*!< Position of ID1_70_7F field. */
543 #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_70_7F_Pos) /*!< Bit mask of ID1_70_7F field. */
544 #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */
545 #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
546 
547 /* Bit 6 : Enable or disable ID filtering for IDs 0x60_0x6F. */
548 #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Pos (6UL) /*!< Position of ID1_60_6F field. */
549 #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_60_6F_Pos) /*!< Bit mask of ID1_60_6F field. */
550 #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */
551 #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
552 
553 /* Bit 5 : Enable or disable ID filtering for IDs 0x50_0x5F. */
554 #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Pos (5UL) /*!< Position of ID1_50_5F field. */
555 #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_50_5F_Pos) /*!< Bit mask of ID1_50_5F field. */
556 #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */
557 #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
558 
559 /* Bit 4 : Enable or disable ID filtering for IDs 0x40_0x4F. */
560 #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Pos (4UL) /*!< Position of ID1_40_4F field. */
561 #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_40_4F_Pos) /*!< Bit mask of ID1_40_4F field. */
562 #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */
563 #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
564 
565 /* Bit 3 : Enable or disable ID filtering for IDs 0x30_0x3F. */
566 #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Pos (3UL) /*!< Position of ID1_30_3F field. */
567 #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_30_3F_Pos) /*!< Bit mask of ID1_30_3F field. */
568 #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */
569 #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
570 
571 /* Bit 2 : Enable or disable ID filtering for IDs 0x20_0x2F. */
572 #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Pos (2UL) /*!< Position of ID1_20_2F field. */
573 #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_20_2F_Pos) /*!< Bit mask of ID1_20_2F field. */
574 #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */
575 #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
576 
577 /* Bit 1 : Enable or disable ID filtering for IDs 0x10_0x1F. */
578 #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Pos (1UL) /*!< Position of ID1_10_1F field. */
579 #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_10_1F_Pos) /*!< Bit mask of ID1_10_1F field. */
580 #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */
581 #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
582 
583 /* Bit 0 : Enable or disable ID filtering for IDs 0x00_0x0F. */
584 #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Pos (0UL) /*!< Position of ID1_00_0F field. */
585 #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_00_0F_Pos) /*!< Bit mask of ID1_00_0F field. */
586 #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */
587 #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
588 
589 /* Register: ATBREPLICATOR_ITATBCTR1 */
590 /* Description: The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in integration mode. */
591 
592 /* Bit 3 : Reads the value of the atvalids input. */
593 #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Pos (3UL) /*!< Position of ATVALIDS field. */
594 #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATVALIDS_Pos) /*!< Bit mask of ATVALIDS field. */
595 #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Low (0x0UL) /*!< Pin is logic 0. */
596 #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_High (0x1UL) /*!< Pin is logic 1. */
597 
598 /* Bit 1 : Reads the value of the atreadym1 input. */
599 #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Pos (1UL) /*!< Position of ATREADYM1 field. */
600 #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATREADYM1_Pos) /*!< Bit mask of ATREADYM1 field. */
601 #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Low (0x0UL) /*!< Pin is logic 0. */
602 #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_High (0x1UL) /*!< Pin is logic 1. */
603 
604 /* Bit 0 : Reads the value of the atreadym0 input. */
605 #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Pos (0UL) /*!< Position of ATREADYM0 field. */
606 #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATREADYM0_Pos) /*!< Bit mask of ATREADYM0 field. */
607 #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Low (0x0UL) /*!< Pin is logic 0. */
608 #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_High (0x1UL) /*!< Pin is logic 1. */
609 
610 /* Register: ATBREPLICATOR_ITATBCTR0 */
611 /* Description: The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in integration mode. */
612 
613 /* Bit 3 : Sets the value of the atreadys output. */
614 #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Pos (3UL) /*!< Position of ATREADYS field. */
615 #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATREADYS_Pos) /*!< Bit mask of ATREADYS field. */
616 #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Low (0x0UL) /*!< Pin is logic 0. */
617 #define ATBREPLICATOR_ITATBCTR0_ATREADYS_High (0x1UL) /*!< Pin is logic 1. */
618 
619 /* Bit 2 : Sets the value of the atvalidm1 output. */
620 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Pos (2UL) /*!< Position of ATVALIDM1 field. */
621 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Pos) /*!< Bit mask of ATVALIDM1 field. */
622 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Low (0x0UL) /*!< Pin is logic 0. */
623 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_High (0x1UL) /*!< Pin is logic 1. */
624 
625 /* Bit 0 : Sets the value of the atvalidm0 output. */
626 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Pos (0UL) /*!< Position of ATVALIDM0 field. */
627 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Pos) /*!< Bit mask of ATVALIDM0 field. */
628 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Low (0x0UL) /*!< Pin is logic 0. */
629 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_High (0x1UL) /*!< Pin is logic 1. */
630 
631 /* Register: ATBREPLICATOR_ITCTRL */
632 /* Description: The ITCTRL register enables the component to switch from a functional mode, which is the default behavior,
633       to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. */
634 
635 /* Bit 0 : Integration Mode Enable. */
636 #define ATBREPLICATOR_ITCTRL_IME_Pos (0UL) /*!< Position of IME field. */
637 #define ATBREPLICATOR_ITCTRL_IME_Msk (0x1UL << ATBREPLICATOR_ITCTRL_IME_Pos) /*!< Bit mask of IME field. */
638 #define ATBREPLICATOR_ITCTRL_IME_Disabled (0x0UL) /*!< Integration mode disabled. */
639 #define ATBREPLICATOR_ITCTRL_IME_Enabled (0x1UL) /*!< Integration mode enabled. */
640 
641 /* Register: ATBREPLICATOR_CLAIMSET */
642 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality.
643       The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. */
644 
645 /* Bit 3 : Set claim bit 3 and check if bit is implemented or not. */
646 #define ATBREPLICATOR_CLAIMSET_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */
647 #define ATBREPLICATOR_CLAIMSET_BIT_3_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */
648 #define ATBREPLICATOR_CLAIMSET_BIT_3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented. */
649 #define ATBREPLICATOR_CLAIMSET_BIT_3_Implemented (0x1UL) /*!< Claim bit 3 is implemented. */
650 #define ATBREPLICATOR_CLAIMSET_BIT_3_Set (0x1UL) /*!< Set claim bit 3. */
651 
652 /* Bit 2 : Set claim bit 2 and check if bit is implemented or not. */
653 #define ATBREPLICATOR_CLAIMSET_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */
654 #define ATBREPLICATOR_CLAIMSET_BIT_2_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */
655 #define ATBREPLICATOR_CLAIMSET_BIT_2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented. */
656 #define ATBREPLICATOR_CLAIMSET_BIT_2_Implemented (0x1UL) /*!< Claim bit 2 is implemented. */
657 #define ATBREPLICATOR_CLAIMSET_BIT_2_Set (0x1UL) /*!< Set claim bit 2. */
658 
659 /* Bit 1 : Set claim bit 1 and check if bit is implemented or not. */
660 #define ATBREPLICATOR_CLAIMSET_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */
661 #define ATBREPLICATOR_CLAIMSET_BIT_1_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */
662 #define ATBREPLICATOR_CLAIMSET_BIT_1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented. */
663 #define ATBREPLICATOR_CLAIMSET_BIT_1_Implemented (0x1UL) /*!< Claim bit 1 is implemented. */
664 #define ATBREPLICATOR_CLAIMSET_BIT_1_Set (0x1UL) /*!< Set claim bit 1. */
665 
666 /* Bit 0 : Set claim bit 0 and check if bit is implemented or not. */
667 #define ATBREPLICATOR_CLAIMSET_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */
668 #define ATBREPLICATOR_CLAIMSET_BIT_0_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */
669 #define ATBREPLICATOR_CLAIMSET_BIT_0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented. */
670 #define ATBREPLICATOR_CLAIMSET_BIT_0_Implemented (0x1UL) /*!< Claim bit 0 is implemented. */
671 #define ATBREPLICATOR_CLAIMSET_BIT_0_Set (0x1UL) /*!< Set claim bit 0. */
672 
673 /* Register: ATBREPLICATOR_CLAIMCLR */
674 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality.
675       The claim tags have no effect on the operation of the component.
676       The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. */
677 
678 /* Bit 3 : Read or clear claim bit 3. */
679 #define ATBREPLICATOR_CLAIMCLR_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */
680 #define ATBREPLICATOR_CLAIMCLR_BIT_3_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */
681 #define ATBREPLICATOR_CLAIMCLR_BIT_3_Cleared (0x0UL) /*!< Claim bit 3 is not set. */
682 #define ATBREPLICATOR_CLAIMCLR_BIT_3_Set (0x1UL) /*!< Claim bit 3 is set. */
683 #define ATBREPLICATOR_CLAIMCLR_BIT_3_Clear (0x1UL) /*!< Clear claim bit 3. */
684 
685 /* Bit 2 : Read or clear claim bit 2. */
686 #define ATBREPLICATOR_CLAIMCLR_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */
687 #define ATBREPLICATOR_CLAIMCLR_BIT_2_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */
688 #define ATBREPLICATOR_CLAIMCLR_BIT_2_Cleared (0x0UL) /*!< Claim bit 2 is not set. */
689 #define ATBREPLICATOR_CLAIMCLR_BIT_2_Set (0x1UL) /*!< Claim bit 2 is set. */
690 #define ATBREPLICATOR_CLAIMCLR_BIT_2_Clear (0x1UL) /*!< Clear claim bit 2. */
691 
692 /* Bit 1 : Read or clear claim bit 1. */
693 #define ATBREPLICATOR_CLAIMCLR_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */
694 #define ATBREPLICATOR_CLAIMCLR_BIT_1_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */
695 #define ATBREPLICATOR_CLAIMCLR_BIT_1_Cleared (0x0UL) /*!< Claim bit 1 is not set. */
696 #define ATBREPLICATOR_CLAIMCLR_BIT_1_Set (0x1UL) /*!< Claim bit 1 is set. */
697 #define ATBREPLICATOR_CLAIMCLR_BIT_1_Clear (0x1UL) /*!< Clear claim bit 1. */
698 
699 /* Bit 0 : Read or clear claim bit 0. */
700 #define ATBREPLICATOR_CLAIMCLR_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */
701 #define ATBREPLICATOR_CLAIMCLR_BIT_0_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */
702 #define ATBREPLICATOR_CLAIMCLR_BIT_0_Cleared (0x0UL) /*!< Claim bit 0 is not set. */
703 #define ATBREPLICATOR_CLAIMCLR_BIT_0_Set (0x1UL) /*!< Claim bit 0 is set. */
704 #define ATBREPLICATOR_CLAIMCLR_BIT_0_Clear (0x1UL) /*!< Clear claim bit 0. */
705 
706 /* Register: ATBREPLICATOR_LAR */
707 /* Description: This is used to enable write access to device registers. */
708 
709 /* Bits 31..0 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. */
710 #define ATBREPLICATOR_LAR_ACCESS_Pos (0UL) /*!< Position of ACCESS field. */
711 #define ATBREPLICATOR_LAR_ACCESS_Msk (0xFFFFFFFFUL << ATBREPLICATOR_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field. */
712 #define ATBREPLICATOR_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface. */
713 
714 /* Register: ATBREPLICATOR_LSR */
715 /* Description: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug.
716       Accesses to the extended stimulus port registers are not affected by the lock mechanism.
717       This register must always be present although there might not be any lock access control mechanism.
718       The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register.
719       For most components this covers all registers except for the Lock Access Register. */
720 
721 /* Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */
722 #define ATBREPLICATOR_LSR_TYPE_Pos (2UL) /*!< Position of TYPE field. */
723 #define ATBREPLICATOR_LSR_TYPE_Msk (0x1UL << ATBREPLICATOR_LSR_TYPE_Pos) /*!< Bit mask of TYPE field. */
724 #define ATBREPLICATOR_LSR_TYPE_Bits32 (0x0UL) /*!< This component implements a 32-bit Lock Access Register. */
725 #define ATBREPLICATOR_LSR_TYPE_Bits8 (0x1UL) /*!< This component implements an 8-bit Lock Access Register. */
726 
727 /* Bit 1 : Returns the current status of the Lock. */
728 #define ATBREPLICATOR_LSR_LOCKED_Pos (1UL) /*!< Position of LOCKED field. */
729 #define ATBREPLICATOR_LSR_LOCKED_Msk (0x1UL << ATBREPLICATOR_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */
730 #define ATBREPLICATOR_LSR_LOCKED_UnLocked (0x0UL) /*!< Write access is allowed to this device. */
731 #define ATBREPLICATOR_LSR_LOCKED_Locked (0x1UL) /*!< Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. */
732 
733 /* Bit 0 : Indicates that a lock control mechanism exists for this device. */
734 #define ATBREPLICATOR_LSR_PRESENT_Pos (0UL) /*!< Position of PRESENT field. */
735 #define ATBREPLICATOR_LSR_PRESENT_Msk (0x1UL << ATBREPLICATOR_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field. */
736 #define ATBREPLICATOR_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access Register are ignored. */
737 #define ATBREPLICATOR_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present. */
738 
739 /* Register: ATBREPLICATOR_AUTHSTATUS */
740 /* Description: Indicates the current level of tracing permitted by the system */
741 
742 /* Bits 7..6 : Secure Non-Invasive Debug */
743 #define ATBREPLICATOR_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */
744 #define ATBREPLICATOR_AUTHSTATUS_SNID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */
745 #define ATBREPLICATOR_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
746 #define ATBREPLICATOR_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */
747 
748 /* Bits 5..4 : Secure Invasive Debug */
749 #define ATBREPLICATOR_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */
750 #define ATBREPLICATOR_AUTHSTATUS_SID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */
751 #define ATBREPLICATOR_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
752 #define ATBREPLICATOR_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */
753 
754 /* Bits 3..2 : Non-secure Non-Invasive Debug */
755 #define ATBREPLICATOR_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */
756 #define ATBREPLICATOR_AUTHSTATUS_NSNID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */
757 #define ATBREPLICATOR_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
758 #define ATBREPLICATOR_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */
759 
760 /* Bits 1..0 : Non-secure Invasive Debug */
761 #define ATBREPLICATOR_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */
762 #define ATBREPLICATOR_AUTHSTATUS_NSID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */
763 #define ATBREPLICATOR_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
764 #define ATBREPLICATOR_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */
765 
766 /* Register: ATBREPLICATOR_DEVID */
767 /* Description: Indicates the capabilities of the component. */
768 
769 /* Bits 3..0 : Indicates the number of master ports implemented. */
770 #define ATBREPLICATOR_DEVID_PORTNUM_Pos (0UL) /*!< Position of PORTNUM field. */
771 #define ATBREPLICATOR_DEVID_PORTNUM_Msk (0xFUL << ATBREPLICATOR_DEVID_PORTNUM_Pos) /*!< Bit mask of PORTNUM field. */
772 
773 /* Register: ATBREPLICATOR_DEVTYPE */
774 /* Description: The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. */
775 
776 /* Bits 7..4 : The sub-type of the component */
777 #define ATBREPLICATOR_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */
778 #define ATBREPLICATOR_DEVTYPE_SUB_Msk (0xFUL << ATBREPLICATOR_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */
779 #define ATBREPLICATOR_DEVTYPE_SUB_Replicator (0x2UL) /*!< Indicates that this component replicates trace from a single source to multiple targets. */
780 
781 /* Bits 3..0 : The main type of the component */
782 #define ATBREPLICATOR_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */
783 #define ATBREPLICATOR_DEVTYPE_MAJOR_Msk (0xFUL << ATBREPLICATOR_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */
784 #define ATBREPLICATOR_DEVTYPE_MAJOR_InputOutputDevice (0x2UL) /*!< Indicates that this component has ATB inputs and outputs. */
785 
786 
787 /* Peripheral: CC_AES */
788 /* Description: CRYPTOCELL AES engine */
789 
790 /* Register: CC_AES_AES_KEY_0 */
791 /* Description: Description collection: AES key value to use.
792         The initial AES_KEY_0[0] register holds the least significant bits [31:0] of the key value. */
793 
794 /* Bits 31..0 : AES key value. */
795 #define CC_AES_AES_KEY_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */
796 #define CC_AES_AES_KEY_0_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_KEY_0_VALUE_Pos) /*!< Bit mask of VALUE field. */
797 
798 /* Register: CC_AES_AES_IV_0 */
799 /* Description: Description collection: AES Initialization Vector (IV) to use.
800         The initial AES_IV_0[0] register holds the least significant bits [31:0] of the IV. */
801 
802 /* Bits 31..0 : AES non-tunneling or first tunnel stage IV value. */
803 #define CC_AES_AES_IV_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */
804 #define CC_AES_AES_IV_0_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_IV_0_VALUE_Pos) /*!< Bit mask of VALUE field. */
805 
806 /* Register: CC_AES_AES_CTR */
807 /* Description: Description collection: AES counter (CTR) to use.
808         The initial AES_CTR[0] register holds the least significant bits [31:0] of the CTR. */
809 
810 /* Bits 31..0 : AES CTR value. */
811 #define CC_AES_AES_CTR_VALUE_Pos (0UL) /*!< Position of VALUE field. */
812 #define CC_AES_AES_CTR_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_CTR_VALUE_Pos) /*!< Bit mask of VALUE field. */
813 
814 /* Register: CC_AES_AES_BUSY */
815 /* Description: Status register for AES engine activity. */
816 
817 /* Bit 0 : AES engine status. */
818 #define CC_AES_AES_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
819 #define CC_AES_AES_BUSY_STATUS_Msk (0x1UL << CC_AES_AES_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
820 #define CC_AES_AES_BUSY_STATUS_Idle (0x0UL) /*!< AES engine is idle */
821 #define CC_AES_AES_BUSY_STATUS_Busy (0x1UL) /*!< AES engine is busy */
822 
823 /* Register: CC_AES_AES_SK */
824 /* Description: Writing to this address trigger sampling of the HW key to the AES_KEY_0 register */
825 
826 /* Bit 0 : Sample HW key to AES_KEY_0 registers. */
827 #define CC_AES_AES_SK_AES_SK_Pos (0UL) /*!< Position of AES_SK field. */
828 #define CC_AES_AES_SK_AES_SK_Msk (0x1UL << CC_AES_AES_SK_AES_SK_Pos) /*!< Bit mask of AES_SK field. */
829 
830 /* Register: CC_AES_AES_CMAC_INIT */
831 /* Description: Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations. */
832 
833 /* Bit 0 : Generate K1 and K2 for the AES-CMAC operations. */
834 #define CC_AES_AES_CMAC_INIT_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
835 #define CC_AES_AES_CMAC_INIT_ENABLE_Msk (0x1UL << CC_AES_AES_CMAC_INIT_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
836 #define CC_AES_AES_CMAC_INIT_ENABLE_Enable (0x1UL) /*!< Initialize AES-CMAC operations. */
837 
838 /* Register: CC_AES_AES_REMAINING_BYTES */
839 /* Description: This register should be set with the amount of remaining bytes until the end of the current AES operation. */
840 
841 /* Bits 31..0 : Remaining bytes util the end of the current AES operation. */
842 #define CC_AES_AES_REMAINING_BYTES_VALUE_Pos (0UL) /*!< Position of VALUE field. */
843 #define CC_AES_AES_REMAINING_BYTES_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_REMAINING_BYTES_VALUE_Pos) /*!< Bit mask of VALUE field. */
844 
845 /* Register: CC_AES_AES_CONTROL */
846 /* Description: Control the AES engine behavior. */
847 
848 /* Bit 31 : Using direct access and not the DIN-DOUT DMA interface */
849 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Pos (31UL) /*!< Position of DIRECT_ACCESS field. */
850 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Msk (0x1UL << CC_AES_AES_CONTROL_DIRECT_ACCESS_Pos) /*!< Bit mask of DIRECT_ACCESS field. */
851 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Disable (0x0UL) /*!< Access using the DIN-DOUT DMA interface */
852 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Enable (0x1UL) /*!< Access using direct access */
853 
854 /* Bit 29 : This field determines the value that is written to AES_KEY_0, when AES_SK is kicked. */
855 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Pos (29UL) /*!< Position of AES_XOR_CRYPTOKEY field. */
856 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Msk (0x1UL << CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Pos) /*!< Bit mask of AES_XOR_CRYPTOKEY field. */
857 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Disable (0x0UL) /*!< The value that is written to AES_KEY_0 is the value of the HW cryptokey as is. */
858 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Enable (0x1UL) /*!< The value that is written to AES_KEY_0 is the value of the HW cryptokey XOR with the current value of AES_KEY_0. */
859 
860 /* Bits 13..12 : Set the AES key length. */
861 #define CC_AES_AES_CONTROL_NK_KEY0_Pos (12UL) /*!< Position of NK_KEY0 field. */
862 #define CC_AES_AES_CONTROL_NK_KEY0_Msk (0x3UL << CC_AES_AES_CONTROL_NK_KEY0_Pos) /*!< Bit mask of NK_KEY0 field. */
863 #define CC_AES_AES_CONTROL_NK_KEY0_128Bits (0x0UL) /*!< 128 bits key length */
864 
865 /* Bits 4..2 : Set the AES mode. */
866 #define CC_AES_AES_CONTROL_MODE_KEY0_Pos (2UL) /*!< Position of MODE_KEY0 field. */
867 #define CC_AES_AES_CONTROL_MODE_KEY0_Msk (0x7UL << CC_AES_AES_CONTROL_MODE_KEY0_Pos) /*!< Bit mask of MODE_KEY0 field. */
868 #define CC_AES_AES_CONTROL_MODE_KEY0_ECB (0x0UL) /*!< Electronic codebook mode */
869 #define CC_AES_AES_CONTROL_MODE_KEY0_CBC (0x1UL) /*!< Cipher block chaining mode */
870 #define CC_AES_AES_CONTROL_MODE_KEY0_CTR (0x2UL) /*!< Counter mode */
871 #define CC_AES_AES_CONTROL_MODE_KEY0_CBC_MAC (0x3UL) /*!< Cipher Block Chaining Message Authentication Code */
872 #define CC_AES_AES_CONTROL_MODE_KEY0_CMAC (0x7UL) /*!< Cipher-based Message Authentication Code */
873 
874 /* Bit 0 : Set AES encrypt or decrypt mode in non-tunneling operations. */
875 #define CC_AES_AES_CONTROL_DEC_KEY0_Pos (0UL) /*!< Position of DEC_KEY0 field. */
876 #define CC_AES_AES_CONTROL_DEC_KEY0_Msk (0x1UL << CC_AES_AES_CONTROL_DEC_KEY0_Pos) /*!< Bit mask of DEC_KEY0 field. */
877 #define CC_AES_AES_CONTROL_DEC_KEY0_Encrypt (0x0UL) /*!< Perform AES encryption */
878 #define CC_AES_AES_CONTROL_DEC_KEY0_Decrypt (0x1UL) /*!< Perform AES decryption */
879 
880 /* Register: CC_AES_AES_HW_FLAGS */
881 /* Description: Hardware configuration of the AES engine. Reset value holds the supported features. */
882 
883 /* Bit 12 : If this flag is set, the engine support DFA countermeasures. */
884 #define CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Pos (12UL) /*!< Position of DFA_CNTRMSR_EXIST field. */
885 #define CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Pos) /*!< Bit mask of DFA_CNTRMSR_EXIST field. */
886 
887 /* Bit 11 : If this flag is set, the engine support a second register set for tunneling operations. */
888 #define CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Pos (11UL) /*!< Position of SECOND_REGS_SET_EXIST field. */
889 #define CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Pos) /*!< Bit mask of SECOND_REGS_SET_EXIST field. */
890 
891 /* Bit 10 : If this flag is set, the engine support tunneling operations. */
892 #define CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Pos (10UL) /*!< Position of AES_TUNNEL_EXIST field. */
893 #define CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Pos) /*!< Bit mask of AES_TUNNEL_EXIST field. */
894 
895 /* Bit 9 : If this flag is set, the engine contains the PREV_IV register for faster AES XCBC MAC calculation. */
896 #define CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Pos (9UL) /*!< Position of AES_SUPPORT_PREV_IV field. */
897 #define CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Pos) /*!< Bit mask of AES_SUPPORT_PREV_IV field. */
898 
899 /* Bit 8 : If this flag is set, the engine uses 5 SBOX where each AES round takes 4 cycles. */
900 #define CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Pos (8UL) /*!< Position of USE_5_SBOXES field. */
901 #define CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Msk (0x1UL << CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Pos) /*!< Bit mask of USE_5_SBOXES field. */
902 
903 /* Bit 5 : If this flag is set, the engine uses SBOX tables. */
904 #define CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Pos (5UL) /*!< Position of USE_SBOX_TABLE field. */
905 #define CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Msk (0x1UL << CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Pos) /*!< Bit mask of USE_SBOX_TABLE field. */
906 
907 /* Bit 4 : If this flag is set, the engine only support encrypt operations. */
908 #define CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Pos (4UL) /*!< Position of ONLY_ENCRYPT field. */
909 #define CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Msk (0x1UL << CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Pos) /*!< Bit mask of ONLY_ENCRYPT field. */
910 
911 /* Bit 3 : If this flag is set, the engine support AES CTR mode. */
912 #define CC_AES_AES_HW_FLAGS_CTR_EXIST_Pos (3UL) /*!< Position of CTR_EXIST field. */
913 #define CC_AES_AES_HW_FLAGS_CTR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_CTR_EXIST_Pos) /*!< Bit mask of CTR_EXIST field. */
914 
915 /* Bit 2 : If this flag is set, the engine support DPA countermeasures. */
916 #define CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Pos (2UL) /*!< Position of DPA_CNTRMSR_EXIST field. */
917 #define CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Pos) /*!< Bit mask of DPA_CNTRMSR_EXIST field. */
918 
919 /* Bit 1 : If this flag is set, the engine support AES_LARGE_RKEK. */
920 #define CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Pos (1UL) /*!< Position of AES_LARGE_RKEK field. */
921 #define CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Pos) /*!< Bit mask of AES_LARGE_RKEK field. */
922 
923 /* Bit 0 : If this flag is set, the engine support 192 bits and 256 bits key size. */
924 #define CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Pos (0UL) /*!< Position of SUPPORT_256_192_KEY field. */
925 #define CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Msk (0x1UL << CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Pos) /*!< Bit mask of SUPPORT_256_192_KEY field. */
926 
927 /* Register: CC_AES_AES_CTR_NO_INCREMENT */
928 /* Description: This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks */
929 
930 /* Bit 0 : This field enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks */
931 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
932 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Msk (0x1UL << CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
933 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Disable (0x0UL) /*!< Counter always incremented between blocks */
934 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Enable (0x1UL) /*!< Do not increment counter between blocks */
935 
936 /* Register: CC_AES_AES_SW_RESET */
937 /* Description: Reset the AES engine. */
938 
939 /* Bit 0 : Writing any value to this address resets the AES engine. The reset takes 4 CPU clock cycles to complete. */
940 #define CC_AES_AES_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
941 #define CC_AES_AES_SW_RESET_RESET_Msk (0x1UL << CC_AES_AES_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
942 #define CC_AES_AES_SW_RESET_RESET_Enable (0x1UL) /*!< Reset AES engine. */
943 
944 /* Register: CC_AES_AES_CMAC_SIZE0_KICK */
945 /* Description: Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register. */
946 
947 /* Bit 0 : Force AES CMAC operation with size 0. */
948 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
949 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Msk (0x1UL << CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
950 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Disable (0x0UL) /*!< Normal AES CMAC operation */
951 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Enable (0x1UL) /*!< Force CMAC operation with size 0 */
952 
953 
954 /* Peripheral: CC_AHB */
955 /* Description: CRYPTOCELL AHB interface */
956 
957 /* Register: CC_AHB_AHBM_SINGLES */
958 /* Description: This register forces the AHB transactions from CRYPTOCELL master to be always singles. */
959 
960 /* Bit 0 : Force AHB singles */
961 #define CC_AHB_AHBM_SINGLES_AHB_SINGLES_Pos (0UL) /*!< Position of AHB_SINGLES field. */
962 #define CC_AHB_AHBM_SINGLES_AHB_SINGLES_Msk (0x1UL << CC_AHB_AHBM_SINGLES_AHB_SINGLES_Pos) /*!< Bit mask of AHB_SINGLES field. */
963 
964 /* Register: CC_AHB_AHBM_HPROT */
965 /* Description: This register holds the AHB HPROT value */
966 
967 /* Bits 3..0 : The AHB HPROT value */
968 #define CC_AHB_AHBM_HPROT_AHB_HPROT_Pos (0UL) /*!< Position of AHB_HPROT field. */
969 #define CC_AHB_AHBM_HPROT_AHB_HPROT_Msk (0xFUL << CC_AHB_AHBM_HPROT_AHB_HPROT_Pos) /*!< Bit mask of AHB_HPROT field. */
970 
971 /* Register: CC_AHB_AHBM_HMASTLOCK */
972 /* Description: This register holds AHB HMASTLOCK value */
973 
974 /* Bit 0 : The AHB HMASTLOCK value. */
975 #define CC_AHB_AHBM_HMASTLOCK_AHB_HMASTLOCK_Pos (0UL) /*!< Position of AHB_HMASTLOCK field. */
976 #define CC_AHB_AHBM_HMASTLOCK_AHB_HMASTLOCK_Msk (0x1UL << CC_AHB_AHBM_HMASTLOCK_AHB_HMASTLOCK_Pos) /*!< Bit mask of AHB_HMASTLOCK field. */
977 
978 /* Register: CC_AHB_AHBM_HNONSEC */
979 /* Description: This register holds AHB HNONSEC value */
980 
981 /* Bit 1 : The AHB HNONSEC value for read transaction. */
982 #define CC_AHB_AHBM_HNONSEC_AHB_READ_HNONSEC_Pos (1UL) /*!< Position of AHB_READ_HNONSEC field. */
983 #define CC_AHB_AHBM_HNONSEC_AHB_READ_HNONSEC_Msk (0x1UL << CC_AHB_AHBM_HNONSEC_AHB_READ_HNONSEC_Pos) /*!< Bit mask of AHB_READ_HNONSEC field. */
984 
985 /* Bit 0 : The AHB HNONSEC value for write transaction. */
986 #define CC_AHB_AHBM_HNONSEC_AHB_WRITE_HNONSEC_Pos (0UL) /*!< Position of AHB_WRITE_HNONSEC field. */
987 #define CC_AHB_AHBM_HNONSEC_AHB_WRITE_HNONSEC_Msk (0x1UL << CC_AHB_AHBM_HNONSEC_AHB_WRITE_HNONSEC_Pos) /*!< Bit mask of AHB_WRITE_HNONSEC field. */
988 
989 
990 /* Peripheral: CC_CHACHA */
991 /* Description: CRYPTOCELL CHACHA engine */
992 
993 /* Register: CC_CHACHA_CHACHA_CONTROL */
994 /* Description: Control the CHACHA engine behavior. */
995 
996 /* Bit 10 : Use 96 bits Initialization Vector (IV) */
997 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Pos (10UL) /*!< Position of USE_IV_96BIT field. */
998 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Pos) /*!< Bit mask of USE_IV_96BIT field. */
999 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Disable (0x0UL) /*!< Use default size IV of 64 bit */
1000 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Enable (0x1UL) /*!< The IV is 96 bits */
1001 
1002 /* Bit 9 : Reset block counter for new messages */
1003 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Pos (9UL) /*!< Position of RESET_BLOCK_CNT field. */
1004 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Pos) /*!< Bit mask of RESET_BLOCK_CNT field. */
1005 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Disable (0x0UL) /*!< Use current block counter value */
1006 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Enable (0x1UL) /*!< Reset block counter value to zero */
1007 
1008 /* Bits 5..4 : Set number of permutation rounds, default value is 20. */
1009 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Pos (4UL) /*!< Position of NUM_OF_ROUNDS field. */
1010 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Msk (0x3UL << CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Pos) /*!< Bit mask of NUM_OF_ROUNDS field. */
1011 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Default (0x0UL) /*!< Use 20 rounds of rotation (default) */
1012 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_12Rounds (0x1UL) /*!< Use 12 rounds of rotation */
1013 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_8Rounds (0x2UL) /*!< Use 8 rounds of rotation */
1014 
1015 /* Bit 3 : Key length selection. */
1016 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Pos (3UL) /*!< Position of KEY_LEN field. */
1017 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Pos) /*!< Bit mask of KEY_LEN field. */
1018 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_256Bits (0x0UL) /*!< Use 256 bits key length */
1019 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_128Bits (0x1UL) /*!< Use 128 bits key length */
1020 
1021 /* Bit 2 : Generate the key to use in Poly1305 message authentication code calculation. */
1022 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Pos (2UL) /*!< Position of GEN_KEY_POLY1305 field. */
1023 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Pos) /*!< Bit mask of GEN_KEY_POLY1305 field. */
1024 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Disable (0x0UL) /*!< Do not generate Poly1305 key */
1025 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Enable (0x1UL) /*!< Generate Poly1305 key */
1026 
1027 /* Bit 1 : Perform initialization for a new message */
1028 #define CC_CHACHA_CHACHA_CONTROL_INIT_Pos (1UL) /*!< Position of INIT field. */
1029 #define CC_CHACHA_CHACHA_CONTROL_INIT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_INIT_Pos) /*!< Bit mask of INIT field. */
1030 #define CC_CHACHA_CHACHA_CONTROL_INIT_Disable (0x0UL) /*!< Message already initialized */
1031 #define CC_CHACHA_CHACHA_CONTROL_INIT_Enable (0x1UL) /*!< Initialize new message */
1032 
1033 /* Bit 0 : Run engine in ChaCha or Salsa mode */
1034 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Pos (0UL) /*!< Position of CHACHA_OR_SALSA field. */
1035 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Pos) /*!< Bit mask of CHACHA_OR_SALSA field. */
1036 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_ChaCha (0x0UL) /*!< Run engine in ChaCha mode */
1037 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Salsa (0x1UL) /*!< Run engine in Salsa mode */
1038 
1039 /* Register: CC_CHACHA_CHACHA_VERSION */
1040 /* Description: CHACHA engine HW version */
1041 
1042 /* Bits 31..0 :   */
1043 #define CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Pos (0UL) /*!< Position of CHACHA_VERSION field. */
1044 #define CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Pos) /*!< Bit mask of CHACHA_VERSION field. */
1045 
1046 /* Register: CC_CHACHA_CHACHA_KEY */
1047 /* Description: Description collection: CHACHA key value to use. The initial CHACHA_KEY[0] register holds the least significant bits [31:0] of the key value. */
1048 
1049 /* Bits 31..0 : CHACHA key value. */
1050 #define CC_CHACHA_CHACHA_KEY_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1051 #define CC_CHACHA_CHACHA_KEY_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_KEY_VALUE_Pos) /*!< Bit mask of VALUE field. */
1052 
1053 /* Register: CC_CHACHA_CHACHA_IV */
1054 /* Description: Description collection: CHACHA Initialization Vector (IV) to use. The IV is also known as the nonce. */
1055 
1056 /* Bits 31..0 : CHACHA IV value. */
1057 #define CC_CHACHA_CHACHA_IV_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1058 #define CC_CHACHA_CHACHA_IV_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_IV_VALUE_Pos) /*!< Bit mask of VALUE field. */
1059 
1060 /* Register: CC_CHACHA_CHACHA_BUSY */
1061 /* Description: Status register for CHACHA engine activity. */
1062 
1063 /* Bit 0 : CHACHA engine status. */
1064 #define CC_CHACHA_CHACHA_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1065 #define CC_CHACHA_CHACHA_BUSY_STATUS_Msk (0x1UL << CC_CHACHA_CHACHA_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
1066 #define CC_CHACHA_CHACHA_BUSY_STATUS_Idle (0x0UL) /*!< CHACHA engine is idle */
1067 #define CC_CHACHA_CHACHA_BUSY_STATUS_Busy (0x1UL) /*!< CHACHA engine is busy */
1068 
1069 /* Register: CC_CHACHA_CHACHA_HW_FLAGS */
1070 /* Description: Hardware configuration of the CHACHA engine. Reset value holds the supported features. */
1071 
1072 /* Bit 2 : If this flag is set, the next matrix calculated when the current one is written to data output path. */
1073 #define CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Pos (2UL) /*!< Position of FAST_CHACHA field. */
1074 #define CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Pos) /*!< Bit mask of FAST_CHACHA field. */
1075 
1076 /* Bit 1 : If this flag is set, the engine include Salsa support */
1077 #define CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Pos (1UL) /*!< Position of SALSA_EXISTS field. */
1078 #define CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Pos) /*!< Bit mask of SALSA_EXISTS field. */
1079 
1080 /* Bit 0 : If this flag is set, the engine include ChaCha support */
1081 #define CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Pos (0UL) /*!< Position of CHACHA_EXISTS field. */
1082 #define CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Pos) /*!< Bit mask of CHACHA_EXISTS field. */
1083 
1084 /* Register: CC_CHACHA_CHACHA_BLOCK_CNT_LSB */
1085 /* Description: Store the LSB value of the block counter, in order to support suspend/resume of operation */
1086 
1087 /* Bits 31..0 : This register holds the ChaCha block counter bits [31:0] and must be read and written during respectively suspend and resume operations. */
1088 #define CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1089 #define CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Pos) /*!< Bit mask of VALUE field. */
1090 
1091 /* Register: CC_CHACHA_CHACHA_BLOCK_CNT_MSB */
1092 /* Description: Store the MSB value of the block counter, in order to support suspend/resume of operation */
1093 
1094 /* Bits 31..0 : This register holds the ChaCha block counter bits [63:32] and must be read and written during respectively suspend and resume operations. */
1095 #define CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1096 #define CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Pos) /*!< Bit mask of VALUE field. */
1097 
1098 /* Register: CC_CHACHA_CHACHA_SW_RESET */
1099 /* Description: Reset the CHACHA engine. */
1100 
1101 /* Bit 0 : Writing any value to this address resets the CHACHA engine. The reset takes 4 CPU clock cycles to complete. */
1102 #define CC_CHACHA_CHACHA_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
1103 #define CC_CHACHA_CHACHA_SW_RESET_RESET_Msk (0x1UL << CC_CHACHA_CHACHA_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
1104 #define CC_CHACHA_CHACHA_SW_RESET_RESET_Enable (0x1UL) /*!< Reset CHACHA engine. */
1105 
1106 /* Register: CC_CHACHA_CHACHA_POLY1305_KEY */
1107 /* Description: Description collection: The auto-generated key to use in Poly1305 MAC calculation. The initial CHACHA_POLY1305_KEY[0] register holds the least significant bits [31:0] of the key value. */
1108 
1109 /* Bits 31..0 : Poly1305 key value. */
1110 #define CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1111 #define CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Pos) /*!< Bit mask of VALUE field. */
1112 
1113 /* Register: CC_CHACHA_CHACHA_ENDIANNESS */
1114 /* Description: CHACHA engine data order configuration. */
1115 
1116 /* Bit 4 : Change the byte order of the output data. */
1117 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Pos (4UL) /*!< Position of CHACHA_DOUT_BYTE_ORDER field. */
1118 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Pos) /*!< Bit mask of CHACHA_DOUT_BYTE_ORDER field. */
1119 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Default (0x0UL) /*!< Use default byte order within each output word, where bytes are ordered as follows: B0, B1, B2, B3. */
1120 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Reverse (0x1UL) /*!< Reverse the byte order within each output word, where bytes are re-ordered as follows: B3, B2, B1, B0. */
1121 
1122 /* Bit 3 : Change the word order of the output data. */
1123 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Pos (3UL) /*!< Position of CHACHA_DOUT_WORD_ORDER field. */
1124 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Pos) /*!< Bit mask of CHACHA_DOUT_WORD_ORDER field. */
1125 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Default (0x0UL) /*!< Uses default word order for 128-bits output, where words are ordered as follows: w0, w1, w2, w3. */
1126 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Reverse (0x1UL) /*!< Reverse the word order for 128-bits output, where words are re-ordered as follows: w3, w2, w1, w0. */
1127 
1128 /* Bit 2 : Change the quarter of a matrix order in the engine. */
1129 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Pos (2UL) /*!< Position of CHACHA_CORE_MATRIX_LBE_ORDER field. */
1130 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Pos) /*!< Bit mask of CHACHA_CORE_MATRIX_LBE_ORDER field. */
1131 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Default (0x0UL) /*!< Use default quarter of matrix order, where quarters are ordered as follows: q0, q1, q2, q3. Each quarter represents a 128-bits section of the matrix. */
1132 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Reverse (0x1UL) /*!< Reverse the order of matrix quarters, where quarters are re-ordered as follows: q3, q2, q1, q0. Each quarter represents a 128-bits section of the matrix. */
1133 
1134 /* Bit 1 : Change the byte order of the input data. */
1135 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Pos (1UL) /*!< Position of CHACHA_DIN_BYTE_ORDER field. */
1136 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Pos) /*!< Bit mask of CHACHA_DIN_BYTE_ORDER field. */
1137 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Default (0x0UL) /*!< Use default byte order within each input word, where bytes are ordered as follows: B0, B1, B2, B3. */
1138 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Reverse (0x1UL) /*!< Reverse the byte order within each input word, where bytes are re-ordered as follows: B3, B2, B1, B0. */
1139 
1140 /* Bit 0 : Change the word order of the input data. */
1141 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Pos (0UL) /*!< Position of CHACHA_DIN_WORD_ORDER field. */
1142 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Pos) /*!< Bit mask of CHACHA_DIN_WORD_ORDER field. */
1143 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Default (0x0UL) /*!< Use default word order for 128-bits input, where words are ordered as follows: w0, w1, w2, w3. */
1144 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Reverse (0x1UL) /*!< Reverses the word order for 128-bits input, where words are re-ordered as follows: w3, w2, w1, w0. */
1145 
1146 /* Register: CC_CHACHA_CHACHA_DEBUG */
1147 /* Description: Debug register for the CHACHA engine */
1148 
1149 /* Bits 1..0 : Reflects the debug state of the CHACHA FSM. */
1150 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Pos (0UL) /*!< Position of FSM_STATE field. */
1151 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Msk (0x3UL << CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Pos) /*!< Bit mask of FSM_STATE field. */
1152 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_IDLE_STATE (0x0UL) /*!< CHACHA FSM is in idle state */
1153 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_INIT_STATE (0x1UL) /*!< CHACHA FSM is in init state */
1154 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_ROUNDS_STATE (0x2UL) /*!< CHACHA FSM is in rounds state */
1155 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_FINAL_STATE (0x3UL) /*!< CHACHA FSM is in final state */
1156 
1157 
1158 /* Peripheral: CC_CTL */
1159 /* Description: CRYPTOCELL CTL interface */
1160 
1161 /* Register: CC_CTL_CRYPTO_CTL */
1162 /* Description: Defines the cryptographic flow. */
1163 
1164 /* Bits 4..0 : Configure the cryptographic engine mode. */
1165 #define CC_CTL_CRYPTO_CTL_MODE_Pos (0UL) /*!< Position of MODE field. */
1166 #define CC_CTL_CRYPTO_CTL_MODE_Msk (0x1FUL << CC_CTL_CRYPTO_CTL_MODE_Pos) /*!< Bit mask of MODE field. */
1167 #define CC_CTL_CRYPTO_CTL_MODE_Bypass (0x00UL) /*!< Bypass cryptographic engine */
1168 #define CC_CTL_CRYPTO_CTL_MODE_AESActive (0x01UL) /*!< Use AES engine */
1169 #define CC_CTL_CRYPTO_CTL_MODE_AESToHashActive (0x02UL) /*!< Pipe AES engine output to HASH engine input */
1170 #define CC_CTL_CRYPTO_CTL_MODE_AESAndHashActive (0x03UL) /*!< Process input using both AES and HASH engine in parallell */
1171 #define CC_CTL_CRYPTO_CTL_MODE_HashActive (0x07UL) /*!< Use HASH engine */
1172 #define CC_CTL_CRYPTO_CTL_MODE_AESMACAndBypassActive (0x09UL) /*!< Calculate AES MAC and bypass */
1173 #define CC_CTL_CRYPTO_CTL_MODE_AESToHashAndDOUTActive (0x0AUL) /*!< Pipe AES engine output to HASH engine input. The resulting digest output is piped to DOUT buffer. */
1174 #define CC_CTL_CRYPTO_CTL_MODE_ChaChaActive (0x10UL) /*!< Use CHACHA engine */
1175 
1176 /* Register: CC_CTL_CRYPTO_BUSY */
1177 /* Description: Status register for cryptographic cores engine activity. */
1178 
1179 /* Bit 0 : Cryptographic core engines status. */
1180 #define CC_CTL_CRYPTO_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1181 #define CC_CTL_CRYPTO_BUSY_STATUS_Msk (0x1UL << CC_CTL_CRYPTO_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
1182 #define CC_CTL_CRYPTO_BUSY_STATUS_Idle (0x0UL) /*!< Cryptographic core engines are idle */
1183 #define CC_CTL_CRYPTO_BUSY_STATUS_Busy (0x1UL) /*!< Cryptographic core engines are busy */
1184 
1185 /* Register: CC_CTL_HASH_BUSY */
1186 /* Description: Status register for HASH engine activity. */
1187 
1188 /* Bit 0 : Hash engine status. */
1189 #define CC_CTL_HASH_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1190 #define CC_CTL_HASH_BUSY_STATUS_Msk (0x1UL << CC_CTL_HASH_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
1191 #define CC_CTL_HASH_BUSY_STATUS_Idle (0x0UL) /*!< HASH engine is idle */
1192 #define CC_CTL_HASH_BUSY_STATUS_Busy (0x1UL) /*!< HASH engine is busy */
1193 
1194 /* Register: CC_CTL_CONTEXT_ID */
1195 /* Description: A general-purpose read/write register. */
1196 
1197 /* Bits 7..0 : Context ID */
1198 #define CC_CTL_CONTEXT_ID_CONTEXT_ID_Pos (0UL) /*!< Position of CONTEXT_ID field. */
1199 #define CC_CTL_CONTEXT_ID_CONTEXT_ID_Msk (0xFFUL << CC_CTL_CONTEXT_ID_CONTEXT_ID_Pos) /*!< Bit mask of CONTEXT_ID field. */
1200 
1201 
1202 /* Peripheral: CC_DIN */
1203 /* Description: CRYPTOCELL Data IN interface */
1204 
1205 /* Register: CC_DIN_DIN_BUFFER */
1206 /* Description: Used by CPU to write data directly to the DIN buffer, which is then sent to the cryptographic engines for processing. */
1207 
1208 /* Bits 31..0 : This register is mapped into 8 addresses in order to enable a CPU burst. */
1209 #define CC_DIN_DIN_BUFFER_DATA_Pos (0UL) /*!< Position of DATA field. */
1210 #define CC_DIN_DIN_BUFFER_DATA_Msk (0xFFFFFFFFUL << CC_DIN_DIN_BUFFER_DATA_Pos) /*!< Bit mask of DATA field. */
1211 
1212 /* Register: CC_DIN_DIN_DMA_MEM_BUSY */
1213 /* Description: Status register for DIN DMA engine activity when accessing memory. */
1214 
1215 /* Bit 0 : DIN memory DMA engine status. */
1216 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1217 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Msk (0x1UL << CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
1218 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Idle (0x0UL) /*!< DIN memory DMA engine is idle */
1219 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Busy (0x1UL) /*!< DIN memory DMA engine is busy */
1220 
1221 /* Register: CC_DIN_SRC_MEM_ADDR */
1222 /* Description: Data source address in memory. */
1223 
1224 /* Bits 31..0 : Source address in memory. */
1225 #define CC_DIN_SRC_MEM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
1226 #define CC_DIN_SRC_MEM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DIN_SRC_MEM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
1227 
1228 /* Register: CC_DIN_SRC_MEM_SIZE */
1229 /* Description: The number of bytes to be read from memory. Writing to this register triggers the DMA operation. */
1230 
1231 /* Bit 31 : This field is reserved */
1232 #define CC_DIN_SRC_MEM_SIZE_LAST_Pos (31UL) /*!< Position of LAST field. */
1233 #define CC_DIN_SRC_MEM_SIZE_LAST_Msk (0x1UL << CC_DIN_SRC_MEM_SIZE_LAST_Pos) /*!< Bit mask of LAST field. */
1234 
1235 /* Bit 30 : This field is reserved */
1236 #define CC_DIN_SRC_MEM_SIZE_FIRST_Pos (30UL) /*!< Position of FIRST field. */
1237 #define CC_DIN_SRC_MEM_SIZE_FIRST_Msk (0x1UL << CC_DIN_SRC_MEM_SIZE_FIRST_Pos) /*!< Bit mask of FIRST field. */
1238 
1239 /* Bits 29..0 : Total number of bytes to read from memory. */
1240 #define CC_DIN_SRC_MEM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
1241 #define CC_DIN_SRC_MEM_SIZE_SIZE_Msk (0x3FFFFFFFUL << CC_DIN_SRC_MEM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
1242 
1243 /* Register: CC_DIN_SRC_SRAM_ADDR */
1244 /* Description: Data source address in RNG SRAM. */
1245 
1246 /* Bits 31..0 : Source address in RNG SRAM. */
1247 #define CC_DIN_SRC_SRAM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
1248 #define CC_DIN_SRC_SRAM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DIN_SRC_SRAM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
1249 
1250 /* Register: CC_DIN_SRC_SRAM_SIZE */
1251 /* Description: The number of bytes to be read from RNG SRAM. Writing to this register triggers the DMA operation. */
1252 
1253 /* Bits 31..0 : Total number of bytes to read from RNG SRAM. */
1254 #define CC_DIN_SRC_SRAM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
1255 #define CC_DIN_SRC_SRAM_SIZE_SIZE_Msk (0xFFFFFFFFUL << CC_DIN_SRC_SRAM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
1256 
1257 /* Register: CC_DIN_DIN_DMA_SRAM_BUSY */
1258 /* Description: Status register for DIN DMA engine activity when accessing RNG SRAM. */
1259 
1260 /* Bit 0 : DIN RNG SRAM DMA engine status. */
1261 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1262 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Msk (0x1UL << CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
1263 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Idle (0x0UL) /*!< DIN RNG SRAM DMA engine is idle */
1264 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Busy (0x1UL) /*!< DIN RNG SRAM DMA engine is busy */
1265 
1266 /* Register: CC_DIN_DIN_DMA_SRAM_ENDIANNESS */
1267 /* Description: Configure the endianness of DIN DMA transactions towards RNG SRAM. */
1268 
1269 /* Bit 0 : Endianness of DIN DMA transactions towards RNG SRAM. The default value is little-endian. */
1270 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */
1271 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
1272 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for RNG SRAM DMA transactions */
1273 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for RNG SRAM DMA transactions */
1274 
1275 /* Register: CC_DIN_DIN_SW_RESET */
1276 /* Description: Reset the DIN DMA engine. */
1277 
1278 /* Bit 0 : Writing any value to this address resets the DIN DMA engine. The reset takes 4 CPU clock cycles to complete. */
1279 #define CC_DIN_DIN_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
1280 #define CC_DIN_DIN_SW_RESET_RESET_Msk (0x1UL << CC_DIN_DIN_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
1281 #define CC_DIN_DIN_SW_RESET_RESET_Enable (0x1UL) /*!< Reset DIN DMA engine. */
1282 
1283 /* Register: CC_DIN_DIN_CPU_DATA */
1284 /* Description: Specifies the number of bytes the CPU will write to the DIN_BUFFER, ensuring the cryptographic engine processes the correct amount of data. */
1285 
1286 /* Bits 15..0 : When using CPU direct write to the DIN_BUFFER, the size of input data in bytes should be written to this register. */
1287 #define CC_DIN_DIN_CPU_DATA_SIZE_Pos (0UL) /*!< Position of SIZE field. */
1288 #define CC_DIN_DIN_CPU_DATA_SIZE_Msk (0xFFFFUL << CC_DIN_DIN_CPU_DATA_SIZE_Pos) /*!< Bit mask of SIZE field. */
1289 
1290 /* Register: CC_DIN_DIN_WRITE_ALIGN */
1291 /* Description: Indicates that the next CPU write to the DIN_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). */
1292 
1293 /* Bit 0 : Next CPU write to the DIN_BUFFER is the last word. */
1294 #define CC_DIN_DIN_WRITE_ALIGN_LAST_Pos (0UL) /*!< Position of LAST field. */
1295 #define CC_DIN_DIN_WRITE_ALIGN_LAST_Msk (0x1UL << CC_DIN_DIN_WRITE_ALIGN_LAST_Pos) /*!< Bit mask of LAST field. */
1296 #define CC_DIN_DIN_WRITE_ALIGN_LAST_Confirm (0x1UL) /*!< The next CPU write is the last in the sequence. */
1297 
1298 /* Register: CC_DIN_DIN_FIFO_EMPTY */
1299 /* Description: Register indicating if DIN FIFO is empty and if more data can be accepted. */
1300 
1301 /* Bit 0 : DIN FIFO status */
1302 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1303 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_Msk (0x1UL << CC_DIN_DIN_FIFO_EMPTY_STATUS_Pos) /*!< Bit mask of STATUS field. */
1304 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_NotEmpty (0x0UL) /*!< DIN FIFO is not empty */
1305 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_Empty (0x1UL) /*!< DIN FIFO is empty, and more data can be accepted */
1306 
1307 /* Register: CC_DIN_DIN_FIFO_RESET */
1308 /* Description: Reset the DIN FIFO, effectively clearing the FIFO for new data. */
1309 
1310 /* Bit 0 : Writing any value to this address resets the DIN FIFO. */
1311 #define CC_DIN_DIN_FIFO_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
1312 #define CC_DIN_DIN_FIFO_RESET_RESET_Msk (0x1UL << CC_DIN_DIN_FIFO_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
1313 #define CC_DIN_DIN_FIFO_RESET_RESET_Enable (0x1UL) /*!< Reset DIN FIFO. */
1314 
1315 
1316 /* Peripheral: CC_DOUT */
1317 /* Description: CRYPTOCELL Data OUT interface */
1318 
1319 /* Register: CC_DOUT_DOUT_BUFFER */
1320 /* Description: Cryptographic results directly accessible by the CPU. */
1321 
1322 /* Bits 31..0 : This address can be used by the CPU to read data directly from the DOUT buffer. */
1323 #define CC_DOUT_DOUT_BUFFER_DATA_Pos (0UL) /*!< Position of DATA field. */
1324 #define CC_DOUT_DOUT_BUFFER_DATA_Msk (0xFFFFFFFFUL << CC_DOUT_DOUT_BUFFER_DATA_Pos) /*!< Bit mask of DATA field. */
1325 
1326 /* Register: CC_DOUT_DOUT_DMA_MEM_BUSY */
1327 /* Description: Status register for DOUT DMA engine activity when accessing memory. */
1328 
1329 /* Bit 0 : DOUT memory DMA engine status. */
1330 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1331 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
1332 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Idle (0x0UL) /*!< DOUT memory DMA engine is idle */
1333 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Busy (0x1UL) /*!< DOUT memory DMA engine is busy */
1334 
1335 /* Register: CC_DOUT_DST_MEM_ADDR */
1336 /* Description: Data destination address in memory. */
1337 
1338 /* Bits 31..0 : Destination address in memory. */
1339 #define CC_DOUT_DST_MEM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
1340 #define CC_DOUT_DST_MEM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DOUT_DST_MEM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
1341 
1342 /* Register: CC_DOUT_DST_MEM_SIZE */
1343 /* Description: The number of bytes to be written to memory. */
1344 
1345 /* Bit 31 : This field is reserved */
1346 #define CC_DOUT_DST_MEM_SIZE_LAST_Pos (31UL) /*!< Position of LAST field. */
1347 #define CC_DOUT_DST_MEM_SIZE_LAST_Msk (0x1UL << CC_DOUT_DST_MEM_SIZE_LAST_Pos) /*!< Bit mask of LAST field. */
1348 
1349 /* Bit 30 : This field is reserved */
1350 #define CC_DOUT_DST_MEM_SIZE_FIRST_Pos (30UL) /*!< Position of FIRST field. */
1351 #define CC_DOUT_DST_MEM_SIZE_FIRST_Msk (0x1UL << CC_DOUT_DST_MEM_SIZE_FIRST_Pos) /*!< Bit mask of FIRST field. */
1352 
1353 /* Bits 29..0 : Total number of bytes to write to memory. */
1354 #define CC_DOUT_DST_MEM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
1355 #define CC_DOUT_DST_MEM_SIZE_SIZE_Msk (0x3FFFFFFFUL << CC_DOUT_DST_MEM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
1356 
1357 /* Register: CC_DOUT_DST_SRAM_ADDR */
1358 /* Description: Data destination address in RNG SRAM. */
1359 
1360 /* Bits 31..0 : Destination address in RNG SRAM. */
1361 #define CC_DOUT_DST_SRAM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
1362 #define CC_DOUT_DST_SRAM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DOUT_DST_SRAM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
1363 
1364 /* Register: CC_DOUT_DST_SRAM_SIZE */
1365 /* Description: The number of bytes to be written to RNG SRAM. */
1366 
1367 /* Bits 31..0 : Total number of bytes to write to RNG SRAM. */
1368 #define CC_DOUT_DST_SRAM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
1369 #define CC_DOUT_DST_SRAM_SIZE_SIZE_Msk (0xFFFFFFFFUL << CC_DOUT_DST_SRAM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
1370 
1371 /* Register: CC_DOUT_DOUT_DMA_SRAM_BUSY */
1372 /* Description: Status register for DOUT DMA engine activity when accessing RNG SRAM. */
1373 
1374 /* Bit 0 : DOUT RNG SRAM DMA engine status. */
1375 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1376 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
1377 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Idle (0x0UL) /*!< DOUT RNG SRAM DMA engine is idle */
1378 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Busy (0x1UL) /*!< DOUT RNG SRAM DMA engine is busy */
1379 
1380 /* Register: CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS */
1381 /* Description: Configure the endianness of DOUT DMA transactions towards RNG SRAM. */
1382 
1383 /* Bit 0 : Endianness of DOUT DMA transactions towards RNG SRAM. The default value is little-endian. */
1384 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */
1385 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
1386 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for RNG SRAM DMA transactions */
1387 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for RNG SRAM DMA transactions */
1388 
1389 /* Register: CC_DOUT_DOUT_READ_ALIGN */
1390 /* Description: Indication that the next CPU read from the DOUT_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). */
1391 
1392 /* Bit 0 : Next CPU read from the DOUT_BUFFER is the last word, and the remaining read aligned content can be flushed. */
1393 #define CC_DOUT_DOUT_READ_ALIGN_LAST_Pos (0UL) /*!< Position of LAST field. */
1394 #define CC_DOUT_DOUT_READ_ALIGN_LAST_Msk (0x1UL << CC_DOUT_DOUT_READ_ALIGN_LAST_Pos) /*!< Bit mask of LAST field. */
1395 #define CC_DOUT_DOUT_READ_ALIGN_LAST_Flush (0x1UL) /*!< Flush the remaining read aligned content. */
1396 
1397 /* Register: CC_DOUT_DOUT_FIFO_EMPTY */
1398 /* Description: Register indicating if DOUT FIFO is empty or if more data will come. */
1399 
1400 /* Bit 0 : DOUT FIFO status */
1401 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1402 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Pos) /*!< Bit mask of STATUS field. */
1403 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_NotEmpty (0x0UL) /*!< DOUT FIFO is not empty, and more data will come */
1404 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Empty (0x1UL) /*!< DOUT FIFO is empty */
1405 
1406 /* Register: CC_DOUT_DOUT_SW_RESET */
1407 /* Description: Reset the DOUT DMA engine. */
1408 
1409 /* Bit 0 : Writing any value to this address resets the DOUT DMA engine. The reset takes 4 CPU clock cycles to complete. */
1410 #define CC_DOUT_DOUT_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
1411 #define CC_DOUT_DOUT_SW_RESET_RESET_Msk (0x1UL << CC_DOUT_DOUT_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
1412 #define CC_DOUT_DOUT_SW_RESET_RESET_Enable (0x1UL) /*!< Reset DOUT DMA engine. */
1413 
1414 
1415 /* Peripheral: CC_HASH */
1416 /* Description: CRYPTOCELL HASH engine */
1417 
1418 /* Register: CC_HASH_HASH_H */
1419 /* Description: Description collection: HASH_H value registers. The initial HASH_H[0] register holds the least significant bits [31:0] of the value. */
1420 
1421 /* Bits 31..0 : Write the initial hash value before start of digest operation, and read the final hash value result after
1422           the digest operation has been completed. */
1423 #define CC_HASH_HASH_H_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1424 #define CC_HASH_HASH_H_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_H_VALUE_Pos) /*!< Bit mask of VALUE field. */
1425 
1426 /* Register: CC_HASH_HASH_PAD_AUTO */
1427 /* Description: Configure the HASH engine to automatically pad data at the end of the DMA transfer to complete the digest operation. */
1428 
1429 /* Bit 0 : Enable automatic padding in hardware. */
1430 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Pos (0UL) /*!< Position of HWPAD field. */
1431 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Msk (0x1UL << CC_HASH_HASH_PAD_AUTO_HWPAD_Pos) /*!< Bit mask of HWPAD field. */
1432 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Disable (0x0UL) /*!< Do not enable automatic hardware padding. */
1433 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Enable (0x1UL) /*!< Enable automatic hardware padding. */
1434 
1435 /* Register: CC_HASH_HASH_INIT_STATE */
1436 /* Description: Configure HASH engine initial state registers. */
1437 
1438 /* Bit 0 : Enable loading of data to initial state registers. Digest/IV for HASH/AES_MAC. */
1439 #define CC_HASH_HASH_INIT_STATE_LOAD_Pos (0UL) /*!< Position of LOAD field. */
1440 #define CC_HASH_HASH_INIT_STATE_LOAD_Msk (0x1UL << CC_HASH_HASH_INIT_STATE_LOAD_Pos) /*!< Bit mask of LOAD field. */
1441 #define CC_HASH_HASH_INIT_STATE_LOAD_Disable (0x0UL) /*!< Disable loading of data to initial state registers. */
1442 #define CC_HASH_HASH_INIT_STATE_LOAD_Enable (0x1UL) /*!< Enable loading of data to initial state registers. */
1443 
1444 /* Register: CC_HASH_HASH_VERSION */
1445 /* Description: HASH engine HW version */
1446 
1447 /* Bits 15..12 : Major version number */
1448 #define CC_HASH_HASH_VERSION_MAJOR_VERSION_NUMBER_Pos (12UL) /*!< Position of MAJOR_VERSION_NUMBER field. */
1449 #define CC_HASH_HASH_VERSION_MAJOR_VERSION_NUMBER_Msk (0xFUL << CC_HASH_HASH_VERSION_MAJOR_VERSION_NUMBER_Pos) /*!< Bit mask of MAJOR_VERSION_NUMBER field. */
1450 
1451 /* Bits 11..8 : Minor version number */
1452 #define CC_HASH_HASH_VERSION_MINOR_VERSION_NUMBER_Pos (8UL) /*!< Position of MINOR_VERSION_NUMBER field. */
1453 #define CC_HASH_HASH_VERSION_MINOR_VERSION_NUMBER_Msk (0xFUL << CC_HASH_HASH_VERSION_MINOR_VERSION_NUMBER_Pos) /*!< Bit mask of MINOR_VERSION_NUMBER field. */
1454 
1455 /* Bits 7..0 :   */
1456 #define CC_HASH_HASH_VERSION_PATCH_Pos (0UL) /*!< Position of PATCH field. */
1457 #define CC_HASH_HASH_VERSION_PATCH_Msk (0xFFUL << CC_HASH_HASH_VERSION_PATCH_Pos) /*!< Bit mask of PATCH field. */
1458 
1459 /* Register: CC_HASH_HASH_CONTROL */
1460 /* Description: Control the HASH engine behavior. */
1461 
1462 /* Bits 3..0 : Select HASH mode to execute */
1463 #define CC_HASH_HASH_CONTROL_MODE_Pos (0UL) /*!< Position of MODE field. */
1464 #define CC_HASH_HASH_CONTROL_MODE_Msk (0xFUL << CC_HASH_HASH_CONTROL_MODE_Pos) /*!< Bit mask of MODE field. */
1465 #define CC_HASH_HASH_CONTROL_MODE_SHA1 (0x1UL) /*!< Select SHA1 mode */
1466 #define CC_HASH_HASH_CONTROL_MODE_SHA256 (0x2UL) /*!< Select SHA256 mode */
1467 #define CC_HASH_HASH_CONTROL_MODE_SHA224 (0xAUL) /*!< Select SHA224 mode */
1468 
1469 /* Register: CC_HASH_HASH_PAD */
1470 /* Description: Enable the hardware padding feature of the HASH engine. */
1471 
1472 /* Bit 0 : Configure hardware padding feature. */
1473 #define CC_HASH_HASH_PAD_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1474 #define CC_HASH_HASH_PAD_ENABLE_Msk (0x1UL << CC_HASH_HASH_PAD_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1475 #define CC_HASH_HASH_PAD_ENABLE_Disable (0x0UL) /*!< Disable hardware padding feature. */
1476 #define CC_HASH_HASH_PAD_ENABLE_Enable (0x1UL) /*!< Enable hardware padding feature. */
1477 
1478 /* Register: CC_HASH_HASH_PAD_FORCE */
1479 /* Description: Force the hardware padding operation to trigger if the input data length is zero bytes. */
1480 
1481 /* Bit 2 : Trigger hardware padding operation. */
1482 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Pos (2UL) /*!< Position of ENABLE field. */
1483 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Msk (0x1UL << CC_HASH_HASH_PAD_FORCE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1484 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Disable (0x0UL) /*!< Do not force hardware padding to trigger. */
1485 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Enable (0x1UL) /*!< Force hardware padding to trigger. */
1486 
1487 /* Register: CC_HASH_HASH_CUR_LEN_0 */
1488 /* Description: Bits [31:0] of the number of bytes that have been digested so far. */
1489 
1490 /* Bits 31..0 : Bits [31:0] of current length of digested data in bytes. */
1491 #define CC_HASH_HASH_CUR_LEN_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1492 #define CC_HASH_HASH_CUR_LEN_0_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_CUR_LEN_0_VALUE_Pos) /*!< Bit mask of VALUE field. */
1493 
1494 /* Register: CC_HASH_HASH_CUR_LEN_1 */
1495 /* Description: Bits [63:32] of the number of bytes that have been digested so far. */
1496 
1497 /* Bits 31..0 : Bits [63:32] of current length of digested data in bytes. */
1498 #define CC_HASH_HASH_CUR_LEN_1_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1499 #define CC_HASH_HASH_CUR_LEN_1_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_CUR_LEN_1_VALUE_Pos) /*!< Bit mask of VALUE field. */
1500 
1501 /* Register: CC_HASH_HASH_HW_FLAGS */
1502 /* Description: Hardware configuration of the HASH engine. Reset value holds the supported features. */
1503 
1504 /* Bit 18 : If this flag is set, the engine include HASH to DOUT support. */
1505 #define CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Pos (18UL) /*!< Position of DUMP_HASH_TO_DOUT_EXISTS field. */
1506 #define CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Pos) /*!< Bit mask of DUMP_HASH_TO_DOUT_EXISTS field. */
1507 
1508 /* Bit 17 : If this flag is set, the engine include compare digest logic. */
1509 #define CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Pos (17UL) /*!< Position of HASH_COMPARE_EXISTS field. */
1510 #define CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Pos) /*!< Bit mask of HASH_COMPARE_EXISTS field. */
1511 
1512 /* Bit 16 : If this flag is set, the engine include SHA-256 support. */
1513 #define CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Pos (16UL) /*!< Position of SHA_256_EXISTS field. */
1514 #define CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Pos) /*!< Bit mask of SHA_256_EXISTS field. */
1515 
1516 /* Bit 15 : If this flag is set, the engine include HMAC support. */
1517 #define CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Pos (15UL) /*!< Position of HMAC_EXISTS field. */
1518 #define CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Pos) /*!< Bit mask of HMAC_EXISTS field. */
1519 
1520 /* Bit 14 : If this flag is set, the engine include MD5 support. */
1521 #define CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Pos (14UL) /*!< Position of MD5_EXISTS field. */
1522 #define CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Pos) /*!< Bit mask of MD5_EXISTS field. */
1523 
1524 /* Bit 13 : If this flag is set, the engine include pad block support. */
1525 #define CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Pos (13UL) /*!< Position of PAD_EXISTS field. */
1526 #define CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Pos) /*!< Bit mask of PAD_EXISTS field. */
1527 
1528 /* Bit 12 : If this flag is set, the engine include SHA-512 support. */
1529 #define CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Pos (12UL) /*!< Position of SHA_512_EXISTS field. */
1530 #define CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Pos) /*!< Bit mask of SHA_512_EXISTS field. */
1531 
1532 /* Bits 11..8 : Determine the granularity of word size. */
1533 #define CC_HASH_HASH_HW_FLAGS_DW_Pos (8UL) /*!< Position of DW field. */
1534 #define CC_HASH_HASH_HW_FLAGS_DW_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_DW_Pos) /*!< Bit mask of DW field. */
1535 #define CC_HASH_HASH_HW_FLAGS_DW_32Bits (0x0UL) /*!< 32 bits word data. */
1536 #define CC_HASH_HASH_HW_FLAGS_DW_64Bits (0x1UL) /*!< 64 bits word data. */
1537 
1538 /* Bits 7..4 : Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi. */
1539 #define CC_HASH_HASH_HW_FLAGS_CH_Pos (4UL) /*!< Position of CH field. */
1540 #define CC_HASH_HASH_HW_FLAGS_CH_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_CH_Pos) /*!< Bit mask of CH field. */
1541 #define CC_HASH_HASH_HW_FLAGS_CH_One (0x0UL) /*!< One Hi value is updated at a time. */
1542 #define CC_HASH_HASH_HW_FLAGS_CH_All (0x1UL) /*!< All Hi values are updated at the same time. */
1543 
1544 /* Bits 3..0 : Indicates the number of concurrent words the hash is using to compute signature. */
1545 #define CC_HASH_HASH_HW_FLAGS_CW_Pos (0UL) /*!< Position of CW field. */
1546 #define CC_HASH_HASH_HW_FLAGS_CW_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_CW_Pos) /*!< Bit mask of CW field. */
1547 #define CC_HASH_HASH_HW_FLAGS_CW_One (0x1UL) /*!< One concurrent word used by hash during signature generation */
1548 #define CC_HASH_HASH_HW_FLAGS_CW_Two (0x2UL) /*!< Two concurrent words used by hash during signature generation */
1549 
1550 /* Register: CC_HASH_HASH_SW_RESET */
1551 /* Description: Reset the HASH engine. */
1552 
1553 /* Bit 0 : Writing any value to this address resets the HASH engine. The reset takes 4 CPU clock cycles to complete. */
1554 #define CC_HASH_HASH_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
1555 #define CC_HASH_HASH_SW_RESET_RESET_Msk (0x1UL << CC_HASH_HASH_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
1556 #define CC_HASH_HASH_SW_RESET_RESET_Enable (0x1UL) /*!< Reset HASH engine. */
1557 
1558 /* Register: CC_HASH_HASH_ENDIANNESS */
1559 /* Description: Configure the endianness of HASH data and padding generation. */
1560 
1561 /* Bit 0 : Endianness of HASH data and padding generation. The default value is little-endian. */
1562 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */
1563 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_HASH_HASH_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
1564 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for data and padding */
1565 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for data and padding */
1566 
1567 
1568 /* Peripheral: CC_HOST_RGF */
1569 /* Description: CRYPTOCELL HOST register interface */
1570 
1571 /* Register: CC_HOST_RGF_IRR */
1572 /* Description: Interrupt request register. Each bit of this register holds the interrupt
1573         status of a single interrupt source. If corresponding IMR bit is
1574         unmasked, an interrupt is generated. */
1575 
1576 /* Bit 10 : The RNG interrupt status. */
1577 #define CC_HOST_RGF_IRR_RNG_INT_Pos (10UL) /*!< Position of RNG_INT field. */
1578 #define CC_HOST_RGF_IRR_RNG_INT_Msk (0x1UL << CC_HOST_RGF_IRR_RNG_INT_Pos) /*!< Bit mask of RNG_INT field. */
1579 
1580 /* Bit 9 : The PKA end of operation interrupt status. */
1581 #define CC_HOST_RGF_IRR_PKA_INT_Pos (9UL) /*!< Position of PKA_INT field. */
1582 #define CC_HOST_RGF_IRR_PKA_INT_Msk (0x1UL << CC_HOST_RGF_IRR_PKA_INT_Pos) /*!< Bit mask of PKA_INT field. */
1583 
1584 /* Bit 8 : The AHB error interrupt status. */
1585 #define CC_HOST_RGF_IRR_AHB_ERR_INT_Pos (8UL) /*!< Position of AHB_ERR_INT field. */
1586 #define CC_HOST_RGF_IRR_AHB_ERR_INT_Msk (0x1UL << CC_HOST_RGF_IRR_AHB_ERR_INT_Pos) /*!< Bit mask of AHB_ERR_INT field. */
1587 
1588 /* Bit 7 : The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to memory. */
1589 #define CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Pos (7UL) /*!< Position of DOUT_TO_MEM_INT field. */
1590 #define CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Msk (0x1UL << CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Pos) /*!< Bit mask of DOUT_TO_MEM_INT field. */
1591 
1592 /* Bit 6 : The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from memory to DIN buffer. */
1593 #define CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Pos (6UL) /*!< Position of MEM_TO_DIN_INT field. */
1594 #define CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Msk (0x1UL << CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Pos) /*!< Bit mask of MEM_TO_DIN_INT field. */
1595 
1596 /* Bit 5 : The DOUT to RNG SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to RNG SRAM. */
1597 #define CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Pos (5UL) /*!< Position of DOUT_TO_SRAM_INT field. */
1598 #define CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Msk (0x1UL << CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Pos) /*!< Bit mask of DOUT_TO_SRAM_INT field. */
1599 
1600 /* Bit 4 : The RNG SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from RNG SRAM to DIN buffer. */
1601 #define CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Pos (4UL) /*!< Position of SRAM_TO_DIN_INT field. */
1602 #define CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Msk (0x1UL << CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Pos) /*!< Bit mask of SRAM_TO_DIN_INT field. */
1603 
1604 /* Register: CC_HOST_RGF_IMR */
1605 /* Description: Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. */
1606 
1607 /* Bit 10 : The RNG interrupt mask. */
1608 #define CC_HOST_RGF_IMR_RNG_MASK_Pos (10UL) /*!< Position of RNG_MASK field. */
1609 #define CC_HOST_RGF_IMR_RNG_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_RNG_MASK_Pos) /*!< Bit mask of RNG_MASK field. */
1610 #define CC_HOST_RGF_IMR_RNG_MASK_IRQEnable (0x0UL) /*!< Do not mask RNG interrupt i.e. interrupt is generated */
1611 #define CC_HOST_RGF_IMR_RNG_MASK_IRQDisable (0x1UL) /*!< Mask RNG interrupt i.e. no interrupt is generated */
1612 
1613 /* Bit 9 : The PKA end of operation interrupt mask. */
1614 #define CC_HOST_RGF_IMR_PKA_MASK_Pos (9UL) /*!< Position of PKA_MASK field. */
1615 #define CC_HOST_RGF_IMR_PKA_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_PKA_MASK_Pos) /*!< Bit mask of PKA_MASK field. */
1616 #define CC_HOST_RGF_IMR_PKA_MASK_IRQEnable (0x0UL) /*!< Do not mask PKA end of operation interrupt i.e. interrupt is generated */
1617 #define CC_HOST_RGF_IMR_PKA_MASK_IRQDisable (0x1UL) /*!< Mask PKA end of operation interrupt i.e. no interrupt is generated */
1618 
1619 /* Bit 8 : The AHB error interrupt mask. */
1620 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_Pos (8UL) /*!< Position of AHB_ERR_MASK field. */
1621 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_AHB_ERR_MASK_Pos) /*!< Bit mask of AHB_ERR_MASK field. */
1622 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask AHB error interrupt i.e. interrupt is generated */
1623 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_IRQDisable (0x1UL) /*!< Mask AHB error interrupt i.e. no interrupt is generated */
1624 
1625 /* Bit 7 : The DOUT to memory DMA done interrupt mask. */
1626 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Pos (7UL) /*!< Position of DOUT_TO_MEM_MASK field. */
1627 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Pos) /*!< Bit mask of DOUT_TO_MEM_MASK field. */
1628 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_IRQEnable (0x0UL) /*!< Do not mask DOUT to memory DMA done interrupt i.e. interrupt is generated */
1629 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_IRQDisable (0x1UL) /*!< Mask DOUT to memory DMA done interrupt i.e. no interrupt is generated */
1630 
1631 /* Bit 6 : The memory to DIN DMA done interrupt mask. */
1632 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Pos (6UL) /*!< Position of MEM_TO_DIN_MASK field. */
1633 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Pos) /*!< Bit mask of MEM_TO_DIN_MASK field. */
1634 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_IRQEnable (0x0UL) /*!< Do not mask memory to DIN DMA done interrupt i.e. interrupt is generated */
1635 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_IRQDisable (0x1UL) /*!< Mask memory to DIN DMA done interrupt i.e. no interrupt is generated */
1636 
1637 /* Bit 5 : The DOUT to RNG SRAM DMA done interrupt mask. */
1638 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Pos (5UL) /*!< Position of DOUT_TO_SRAM_MASK field. */
1639 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Pos) /*!< Bit mask of DOUT_TO_SRAM_MASK field. */
1640 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_IRQEnable (0x0UL) /*!< Do not mask DOUT to RNG SRAM DMA done interrupt i.e. interrupt is generated */
1641 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_IRQDisable (0x1UL) /*!< Mask DOUT to RNG SRAM DMA done interrupt i.e. no interrupt is generated */
1642 
1643 /* Bit 4 : The RNG SRAM to DIN DMA done interrupt mask. */
1644 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Pos (4UL) /*!< Position of SRAM_TO_DIN_MASK field. */
1645 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Pos) /*!< Bit mask of SRAM_TO_DIN_MASK field. */
1646 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_IRQEnable (0x0UL) /*!< Do not mask RNG SRAM to DIN DMA done interrupt i.e. interrupt is generated */
1647 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_IRQDisable (0x1UL) /*!< Mask RNG SRAM to DIN DMA done interrupt i.e. no interrupt is generated */
1648 
1649 /* Register: CC_HOST_RGF_ICR */
1650 /* Description: Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR. */
1651 
1652 /* Bit 10 : The RNG interrupt clear. Register RNG_ISR in the RNG engine must be cleared before this interrupt can be cleared. */
1653 #define CC_HOST_RGF_ICR_RNG_CLEAR_Pos (10UL) /*!< Position of RNG_CLEAR field. */
1654 #define CC_HOST_RGF_ICR_RNG_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_RNG_CLEAR_Pos) /*!< Bit mask of RNG_CLEAR field. */
1655 
1656 /* Bit 9 : The PKA end of operation interrupt clear. */
1657 #define CC_HOST_RGF_ICR_PKA_CLEAR_Pos (9UL) /*!< Position of PKA_CLEAR field. */
1658 #define CC_HOST_RGF_ICR_PKA_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_PKA_CLEAR_Pos) /*!< Bit mask of PKA_CLEAR field. */
1659 
1660 /* Bit 8 : The AHB error interrupt clear. */
1661 #define CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Pos (8UL) /*!< Position of AHB_ERR_CLEAR field. */
1662 #define CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Pos) /*!< Bit mask of AHB_ERR_CLEAR field. */
1663 
1664 /* Bit 7 : The DOUT to memory DMA done interrupt clear. */
1665 #define CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Pos (7UL) /*!< Position of DOUT_TO_MEM_CLEAR field. */
1666 #define CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Pos) /*!< Bit mask of DOUT_TO_MEM_CLEAR field. */
1667 
1668 /* Bit 6 : The memory to DIN DMA done interrupt clear. */
1669 #define CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Pos (6UL) /*!< Position of MEM_TO_DIN_CLEAR field. */
1670 #define CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Pos) /*!< Bit mask of MEM_TO_DIN_CLEAR field. */
1671 
1672 /* Bit 5 : The DOUT to RNG SRAM DMA done interrupt clear. */
1673 #define CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Pos (5UL) /*!< Position of DOUT_TO_SRAM_CLEAR field. */
1674 #define CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Pos) /*!< Bit mask of DOUT_TO_SRAM_CLEAR field. */
1675 
1676 /* Bit 4 : The RNG SRAM to DIN DMA done interrupt clear. */
1677 #define CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Pos (4UL) /*!< Position of SRAM_TO_DIN_CLEAR field. */
1678 #define CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Pos) /*!< Bit mask of SRAM_TO_DIN_CLEAR field. */
1679 
1680 /* Register: CC_HOST_RGF_ENDIANNESS */
1681 /* Description: This register defines the endianness of the Host-accessible registers, and can only be written once. */
1682 
1683 /* Bit 15 : DIN read word endianness. */
1684 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Pos (15UL) /*!< Position of DIN_RD_WBG field. */
1685 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Pos) /*!< Bit mask of DIN_RD_WBG field. */
1686 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_LittleEndian (0x0UL) /*!< Configure DIN read word as little-endian */
1687 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_BigEndian (0x1UL) /*!< Configure DIN read word as big-endian */
1688 
1689 /* Bit 11 : DOUT write word endianness. */
1690 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Pos (11UL) /*!< Position of DOUT_WR_WBG field. */
1691 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Pos) /*!< Bit mask of DOUT_WR_WBG field. */
1692 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_LittleEndian (0x0UL) /*!< Configure DOUT write word as little-endian */
1693 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_BigEndian (0x1UL) /*!< Configure DOUT write word as big-endian */
1694 
1695 /* Bit 7 : DIN read endianness. */
1696 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Pos (7UL) /*!< Position of DIN_RD_BG field. */
1697 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Pos) /*!< Bit mask of DIN_RD_BG field. */
1698 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_LittleEndian (0x0UL) /*!< Configure DIN read as little-endian */
1699 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_BigEndian (0x1UL) /*!< Configure DIN read as big-endian */
1700 
1701 /* Bit 3 : DOUT write endianness. */
1702 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Pos (3UL) /*!< Position of DOUT_WR_BG field. */
1703 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Pos) /*!< Bit mask of DOUT_WR_BG field. */
1704 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_LittleEndian (0x0UL) /*!< Configure DOUT write as little-endian */
1705 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_BigEndian (0x1UL) /*!< Configure DOUT write as big-endian */
1706 
1707 /* Register: CC_HOST_RGF_HOST_SIGNATURE */
1708 /* Description: This register holds the CRYPTOCELL subsystem signature. See reset value. */
1709 
1710 /* Bits 31..0 : Fixed-value identification signature used by host driver to verify CRYPTOCELL presence at this address. */
1711 #define CC_HOST_RGF_HOST_SIGNATURE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1712 #define CC_HOST_RGF_HOST_SIGNATURE_VALUE_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_SIGNATURE_VALUE_Pos) /*!< Bit mask of VALUE field. */
1713 
1714 /* Register: CC_HOST_RGF_HOST_BOOT */
1715 /* Description: Hardware configuration of the CRYPTOCELL subsystem. Reset value holds the supported features. */
1716 
1717 /* Bit 30 : If this flag is set, the AES engine is present */
1718 #define CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Pos (30UL) /*!< Position of AES_EXISTS_LOCAL field. */
1719 #define CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_EXISTS_LOCAL field. */
1720 
1721 /* Bit 29 : If this flag is set, the AES engine only support encryption */
1722 #define CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Pos (29UL) /*!< Position of ONLY_ENCRYPT_LOCAL field. */
1723 #define CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Pos) /*!< Bit mask of ONLY_ENCRYPT_LOCAL field. */
1724 
1725 /* Bit 28 : If this flag is set, the AES engine supports 192/256 bits key sizes */
1726 #define CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Pos (28UL) /*!< Position of SUPPORT_256_192_KEY_LOCAL field. */
1727 #define CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Pos) /*!< Bit mask of SUPPORT_256_192_KEY_LOCAL field. */
1728 
1729 /* Bit 27 : If this flag is set, the AES engine supports tunneling operations */
1730 #define CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Pos (27UL) /*!< Position of TUNNELING_ENB_LOCAL field. */
1731 #define CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Pos) /*!< Bit mask of TUNNELING_ENB_LOCAL field. */
1732 
1733 /* Bit 26 : If this flag is set, the AES engine data input support byte size resolution */
1734 #define CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Pos (26UL) /*!< Position of AES_DIN_BYTE_RESOLUTION_LOCAL field. */
1735 #define CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Pos) /*!< Bit mask of AES_DIN_BYTE_RESOLUTION_LOCAL field. */
1736 
1737 /* Bit 25 : If this flag is set, AES CTR mode is supported */
1738 #define CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Pos (25UL) /*!< Position of CTR_EXISTS_LOCAL field. */
1739 #define CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Pos) /*!< Bit mask of CTR_EXISTS_LOCAL field. */
1740 
1741 /* Bit 24 : If this flag is set, AES XEX mode is supported */
1742 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Pos (24UL) /*!< Position of AES_XEX_EXISTS_LOCAL field. */
1743 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_XEX_EXISTS_LOCAL field. */
1744 
1745 /* Bit 23 : If this flag is set, AES XEX mode T-value calculation in HW is supported */
1746 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Pos (23UL) /*!< Position of AES_XEX_HW_T_CALC_LOCAL field. */
1747 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Pos) /*!< Bit mask of AES_XEX_HW_T_CALC_LOCAL field. */
1748 
1749 /* Bit 22 : If this flag is set, AES CCM mode is supported */
1750 #define CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Pos (22UL) /*!< Position of AES_CCM_EXISTS_LOCAL field. */
1751 #define CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_CCM_EXISTS_LOCAL field. */
1752 
1753 /* Bit 21 : If this flag is set, AES CMAC mode is supported */
1754 #define CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Pos (21UL) /*!< Position of AES_CMAC_EXISTS_LOCAL field. */
1755 #define CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_CMAC_EXISTS_LOCAL field. */
1756 
1757 /* Bit 20 : If this flag is set, AES XCBC-MAC mode is supported */
1758 #define CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Pos (20UL) /*!< Position of AES_XCBC_MAC_EXISTS_LOCAL field. */
1759 #define CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_XCBC_MAC_EXISTS_LOCAL field. */
1760 
1761 /* Bit 19 : If this flag is set, the DES engine is present */
1762 #define CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Pos (19UL) /*!< Position of DES_EXISTS_LOCAL field. */
1763 #define CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Pos) /*!< Bit mask of DES_EXISTS_LOCAL field. */
1764 
1765 /* Bit 18 : If this flag is set, the C2 engine is present */
1766 #define CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Pos (18UL) /*!< Position of C2_EXISTS_LOCAL field. */
1767 #define CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Pos) /*!< Bit mask of C2_EXISTS_LOCAL field. */
1768 
1769 /* Bit 17 : If this flag is set, the HASH engine is present */
1770 #define CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Pos (17UL) /*!< Position of HASH_EXISTS_LOCAL field. */
1771 #define CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Pos) /*!< Bit mask of HASH_EXISTS_LOCAL field. */
1772 
1773 /* Bit 16 : If this flag is set, the HASH engine supports MD5 */
1774 #define CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Pos (16UL) /*!< Position of MD5_PRSNT_LOCAL field. */
1775 #define CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Pos) /*!< Bit mask of MD5_PRSNT_LOCAL field. */
1776 
1777 /* Bit 15 : If this flag is set, the HASH engine supports SHA256 */
1778 #define CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Pos (15UL) /*!< Position of SHA_256_PRSNT_LOCAL field. */
1779 #define CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Pos) /*!< Bit mask of SHA_256_PRSNT_LOCAL field. */
1780 
1781 /* Bit 14 : If this flag is set, the HASH engine supports SHA512 */
1782 #define CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Pos (14UL) /*!< Position of SHA_512_PRSNT_LOCAL field. */
1783 #define CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Pos) /*!< Bit mask of SHA_512_PRSNT_LOCAL field. */
1784 
1785 /* Bit 13 : If this flag is set, the RC4 engine is present */
1786 #define CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Pos (13UL) /*!< Position of RC4_EXISTS_LOCAL field. */
1787 #define CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Pos) /*!< Bit mask of RC4_EXISTS_LOCAL field. */
1788 
1789 /* Bit 12 : If this flag is set, the PKA engine is present */
1790 #define CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Pos (12UL) /*!< Position of PKA_EXISTS_LOCAL field. */
1791 #define CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Pos) /*!< Bit mask of PKA_EXISTS_LOCAL field. */
1792 
1793 /* Bit 11 : If this flag is set, the RNG engine is present */
1794 #define CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Pos (11UL) /*!< Position of RNG_EXISTS_LOCAL field. */
1795 #define CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Pos) /*!< Bit mask of RNG_EXISTS_LOCAL field. */
1796 
1797 /* Bit 10 : If this flag is set, PAU is supported */
1798 #define CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Pos (10UL) /*!< Position of PAU_EXISTS_LOCAL field. */
1799 #define CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Pos) /*!< Bit mask of PAU_EXISTS_LOCAL field. */
1800 
1801 /* Bit 9 : If this flag is set, Descriptors are supported */
1802 #define CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Pos (9UL) /*!< Position of DSCRPTR_EXISTS_LOCAL field. */
1803 #define CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Pos) /*!< Bit mask of DSCRPTR_EXISTS_LOCAL field. */
1804 
1805 /* Bits 8..6 : SRAM size */
1806 #define CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Pos (6UL) /*!< Position of SRAM_SIZE_LOCAL field. */
1807 #define CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Msk (0x7UL << CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Pos) /*!< Bit mask of SRAM_SIZE_LOCAL field. */
1808 
1809 /* Bit 5 : If this flag is set, RKEK ECC is supported */
1810 #define CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Pos (5UL) /*!< Position of RKEK_ECC_EXISTS_LOCAL_N field. */
1811 #define CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Pos) /*!< Bit mask of RKEK_ECC_EXISTS_LOCAL_N field. */
1812 
1813 /* Bit 3 : If this flag is set, external secure memory is supported */
1814 #define CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Pos (3UL) /*!< Position of EXT_MEM_SECURED_LOCAL field. */
1815 #define CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Pos) /*!< Bit mask of EXT_MEM_SECURED_LOCAL field. */
1816 
1817 /* Bit 2 : If this flag is set, HASH in fuses is supported */
1818 #define CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Pos (2UL) /*!< Position of HASH_IN_FUSES_LOCAL field. */
1819 #define CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Pos) /*!< Bit mask of HASH_IN_FUSES_LOCAL field. */
1820 
1821 /* Bit 1 : If this flag is set, large RKEK is supported */
1822 #define CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Pos (1UL) /*!< Position of LARGE_RKEK_LOCAL field. */
1823 #define CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Pos) /*!< Bit mask of LARGE_RKEK_LOCAL field. */
1824 
1825 /* Bit 0 : If this flag is set, full power gating is implemented */
1826 #define CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Pos (0UL) /*!< Position of POWER_GATING_EXISTS_LOCAL field. */
1827 #define CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Pos) /*!< Bit mask of POWER_GATING_EXISTS_LOCAL field. */
1828 
1829 /* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */
1830 /* Description: AES hardware key select. */
1831 
1832 /* Bits 1..0 : Select the source of the HW key that is used by the AES engine */
1833 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */
1834 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */
1835 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0x0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */
1836 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (0x1UL) /*!< Use hard-coded RTL key K_PRTL */
1837 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (0x2UL) /*!< Use provided session key */
1838 
1839 /* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */
1840 /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
1841 
1842 /* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
1843 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */
1844 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */
1845 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0x0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */
1846 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (0x1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */
1847 
1848 /* Register: CC_HOST_RGF_HOST_IOT_KDR0 */
1849 /* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */
1850 
1851 /* Bits 31..0 : This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. Write: K_DR bits 31:0. */
1852 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */
1853 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */
1854 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_NotRetained (0x00000000UL) /*!< Read: 128 bits K_DR key value is not yet retained in the CRYPTOCELL AO power domain. */
1855 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Retained (0x00000001UL) /*!< Read: 128 bits K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */
1856 
1857 /* Register: CC_HOST_RGF_HOST_IOT_KDR1 */
1858 /* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
1859 
1860 /* Bits 31..0 : K_DR bits 63:32 */
1861 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */
1862 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */
1863 
1864 /* Register: CC_HOST_RGF_HOST_IOT_KDR2 */
1865 /* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
1866 
1867 /* Bits 31..0 : K_DR bits 95:64 */
1868 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */
1869 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */
1870 
1871 /* Register: CC_HOST_RGF_HOST_IOT_KDR3 */
1872 /* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
1873 
1874 /* Bits 31..0 : K_DR bits 127:96 */
1875 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */
1876 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */
1877 
1878 /* Register: CC_HOST_RGF_HOST_IOT_LCS */
1879 /* Description: Controls life-cycle state (LCS) for CRYPTOCELL subsystem */
1880 
1881 /* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */
1882 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */
1883 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */
1884 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0x0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */
1885 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (0x1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */
1886 
1887 /* Bits 2..0 : Life-cycle state value. This field is write-once per reset. */
1888 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */
1889 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */
1890 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_DebugEnable (0x0UL) /*!< CC310 operates in debug mode */
1891 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (0x2UL) /*!< CC310 operates in secure mode */
1892 
1893 
1894 /* Peripheral: CC_MISC */
1895 /* Description: CRYPTOCELL MISC interface */
1896 
1897 /* Register: CC_MISC_AES_CLK */
1898 /* Description: Clock control for the AES engine. */
1899 
1900 /* Bit 0 : Enables clock for the AES engine. */
1901 #define CC_MISC_AES_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1902 #define CC_MISC_AES_CLK_ENABLE_Msk (0x1UL << CC_MISC_AES_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1903 #define CC_MISC_AES_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the AES engine. */
1904 #define CC_MISC_AES_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the AES engine. */
1905 
1906 /* Register: CC_MISC_HASH_CLK */
1907 /* Description: Clock control for the HASH engine. */
1908 
1909 /* Bit 0 : Enables clock for the HASH engine. */
1910 #define CC_MISC_HASH_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1911 #define CC_MISC_HASH_CLK_ENABLE_Msk (0x1UL << CC_MISC_HASH_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1912 #define CC_MISC_HASH_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the HASH engine. */
1913 #define CC_MISC_HASH_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the HASH engine. */
1914 
1915 /* Register: CC_MISC_PKA_CLK */
1916 /* Description: Clock control for the PKA engine. */
1917 
1918 /* Bit 0 : Enables clock for the PKA engine. */
1919 #define CC_MISC_PKA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1920 #define CC_MISC_PKA_CLK_ENABLE_Msk (0x1UL << CC_MISC_PKA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1921 #define CC_MISC_PKA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the PKA engine. */
1922 #define CC_MISC_PKA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the PKA engine. */
1923 
1924 /* Register: CC_MISC_DMA_CLK */
1925 /* Description: Clock control for the DMA engines. */
1926 
1927 /* Bit 0 : Enables clock for the DMA engines. */
1928 #define CC_MISC_DMA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1929 #define CC_MISC_DMA_CLK_ENABLE_Msk (0x1UL << CC_MISC_DMA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1930 #define CC_MISC_DMA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the DMA engines. */
1931 #define CC_MISC_DMA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the DMA engines. */
1932 
1933 /* Register: CC_MISC_CLK_STATUS */
1934 /* Description: CRYPTOCELL clocks status register. */
1935 
1936 /* Bit 8 : Status of DMA engines clock. */
1937 #define CC_MISC_CLK_STATUS_DMA_CLK_Pos (8UL) /*!< Position of DMA_CLK field. */
1938 #define CC_MISC_CLK_STATUS_DMA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_DMA_CLK_Pos) /*!< Bit mask of DMA_CLK field. */
1939 #define CC_MISC_CLK_STATUS_DMA_CLK_Disabled (0x0UL) /*!< Clocks for DMA engines are disabled */
1940 #define CC_MISC_CLK_STATUS_DMA_CLK_Enabled (0x1UL) /*!< Clocks for DMA engines are enabled */
1941 
1942 /* Bit 7 : Status of CHACHA engine clock. */
1943 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Pos (7UL) /*!< Position of CHACHA_CLK field. */
1944 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_CHACHA_CLK_Pos) /*!< Bit mask of CHACHA_CLK field. */
1945 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Disabled (0x0UL) /*!< Clock for CHACHA engine is disabled */
1946 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Enabled (0x1UL) /*!< Clock for CHACHA engine is enabled */
1947 
1948 /* Bit 3 : Status of PKA engine clock. */
1949 #define CC_MISC_CLK_STATUS_PKA_CLK_Pos (3UL) /*!< Position of PKA_CLK field. */
1950 #define CC_MISC_CLK_STATUS_PKA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_PKA_CLK_Pos) /*!< Bit mask of PKA_CLK field. */
1951 #define CC_MISC_CLK_STATUS_PKA_CLK_Disabled (0x0UL) /*!< Clock for PKA engine is disabled */
1952 #define CC_MISC_CLK_STATUS_PKA_CLK_Enabled (0x1UL) /*!< Clock for PKA engine is enabled */
1953 
1954 /* Bit 2 : Status of HASH engine clock. */
1955 #define CC_MISC_CLK_STATUS_HASH_CLK_Pos (2UL) /*!< Position of HASH_CLK field. */
1956 #define CC_MISC_CLK_STATUS_HASH_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_HASH_CLK_Pos) /*!< Bit mask of HASH_CLK field. */
1957 #define CC_MISC_CLK_STATUS_HASH_CLK_Disabled (0x0UL) /*!< Clock for HASH engine is disabled */
1958 #define CC_MISC_CLK_STATUS_HASH_CLK_Enabled (0x1UL) /*!< Clock for HASH engine is enabled */
1959 
1960 /* Bit 0 : Status of AES engine clock. */
1961 #define CC_MISC_CLK_STATUS_AES_CLK_Pos (0UL) /*!< Position of AES_CLK field. */
1962 #define CC_MISC_CLK_STATUS_AES_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_AES_CLK_Pos) /*!< Bit mask of AES_CLK field. */
1963 #define CC_MISC_CLK_STATUS_AES_CLK_Disabled (0x0UL) /*!< Clock for AES engine is disabled */
1964 #define CC_MISC_CLK_STATUS_AES_CLK_Enabled (0x1UL) /*!< Clock for AES engine is enabled */
1965 
1966 /* Register: CC_MISC_CHACHA_CLK */
1967 /* Description: Clock control for the CHACHA engine. */
1968 
1969 /* Bit 0 : Enables clock for the CHACHA engine. */
1970 #define CC_MISC_CHACHA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1971 #define CC_MISC_CHACHA_CLK_ENABLE_Msk (0x1UL << CC_MISC_CHACHA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1972 #define CC_MISC_CHACHA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the CHACHA engine. */
1973 #define CC_MISC_CHACHA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the CHACHA engine. */
1974 
1975 
1976 /* Peripheral: CC_PKA */
1977 /* Description: CRYPTOCELL PKA engine */
1978 
1979 /* Register: CC_PKA_MEMORY_MAP */
1980 /* Description: Description collection: Register for mapping the virtual register R[n] to a physical address in the PKA SRAM. */
1981 
1982 /* Bits 9..1 : The physical word address used for the virtual register. */
1983 #define CC_PKA_MEMORY_MAP_ADDR_Pos (1UL) /*!< Position of ADDR field. */
1984 #define CC_PKA_MEMORY_MAP_ADDR_Msk (0x1FFUL << CC_PKA_MEMORY_MAP_ADDR_Pos) /*!< Bit mask of ADDR field. */
1985 
1986 /* Register: CC_PKA_OPCODE */
1987 /* Description: Operation code to be executed by the PKA engine. Writing to this register triggers the PKA operation. */
1988 
1989 /* Bits 31..27 : Operation code to be executed by the PKA engine */
1990 #define CC_PKA_OPCODE_OPCODE_Pos (27UL) /*!< Position of OPCODE field. */
1991 #define CC_PKA_OPCODE_OPCODE_Msk (0x1FUL << CC_PKA_OPCODE_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
1992 #define CC_PKA_OPCODE_OPCODE_Terminate (0x00UL) /*!< Terminate operation */
1993 #define CC_PKA_OPCODE_OPCODE_AddInc (0x04UL) /*!< Add or Increment */
1994 #define CC_PKA_OPCODE_OPCODE_SubDecNeg (0x05UL) /*!< Subtract, Decrement, or Negate */
1995 #define CC_PKA_OPCODE_OPCODE_ModAddInc (0x06UL) /*!< Modular Add or Modular Increment */
1996 #define CC_PKA_OPCODE_OPCODE_ModSubDecNeg (0x07UL) /*!< Modular Subtract, Modular Decrement, or Modular Negate */
1997 #define CC_PKA_OPCODE_OPCODE_ANDTST0CLR0 (0x08UL) /*!< Perform AND, test, or clear */
1998 #define CC_PKA_OPCODE_OPCODE_ORCOPYSET0 (0x09UL) /*!< Perform OR, copy, or set bits */
1999 #define CC_PKA_OPCODE_OPCODE_XORFLP0INVCMP (0x0AUL) /*!< Perform XOR, flip bits, invert, or compare */
2000 #define CC_PKA_OPCODE_OPCODE_SHR0 (0x0CUL) /*!< Shift right 0 operation */
2001 #define CC_PKA_OPCODE_OPCODE_SHR1 (0x0DUL) /*!< Shift right 1 operation */
2002 #define CC_PKA_OPCODE_OPCODE_SHL0 (0x0EUL) /*!< Shift left 0 operation */
2003 #define CC_PKA_OPCODE_OPCODE_SHL1 (0x0FUL) /*!< Shift left 1 operation */
2004 #define CC_PKA_OPCODE_OPCODE_MulLow (0x10UL) /*!< Multiply low operation */
2005 #define CC_PKA_OPCODE_OPCODE_ModMul (0x11UL) /*!< Modular multiply operation */
2006 #define CC_PKA_OPCODE_OPCODE_ModMulN (0x12UL) /*!< Modular multiply N operation */
2007 #define CC_PKA_OPCODE_OPCODE_ModExp (0x13UL) /*!< Modular exponentiation operation */
2008 #define CC_PKA_OPCODE_OPCODE_Division (0x14UL) /*!< Division operation */
2009 #define CC_PKA_OPCODE_OPCODE_ModInv (0x15UL) /*!< Modular inversion operation */
2010 #define CC_PKA_OPCODE_OPCODE_ModDiv (0x16UL) /*!< Modular division operation */
2011 #define CC_PKA_OPCODE_OPCODE_MulHigh (0x17UL) /*!< Multiply high operation */
2012 #define CC_PKA_OPCODE_OPCODE_ModMLAC (0x18UL) /*!< Modular multiplication acceleration */
2013 #define CC_PKA_OPCODE_OPCODE_ModMLACNR (0x19UL) /*!< Modular multiplication acceleration where final reduction is omitted */
2014 #define CC_PKA_OPCODE_OPCODE_Reduction (0x1BUL) /*!< Reduction operation */
2015 
2016 /* Bits 26..24 : The length of the operands. This value serves as an PKA length register index. E.g.: if LEN field value is set to 0, PKA_L[0] holds the size of the operands. */
2017 #define CC_PKA_OPCODE_LEN_Pos (24UL) /*!< Position of LEN field. */
2018 #define CC_PKA_OPCODE_LEN_Msk (0x7UL << CC_PKA_OPCODE_LEN_Pos) /*!< Bit mask of LEN field. */
2019 
2020 /* Bit 23 : This field controls the interpretation of REG_A. */
2021 #define CC_PKA_OPCODE_CONST_A_Pos (23UL) /*!< Position of CONST_A field. */
2022 #define CC_PKA_OPCODE_CONST_A_Msk (0x1UL << CC_PKA_OPCODE_CONST_A_Pos) /*!< Bit mask of CONST_A field. */
2023 #define CC_PKA_OPCODE_CONST_A_Register (0x0UL) /*!< REG_A is intepreted as a register index. */
2024 #define CC_PKA_OPCODE_CONST_A_Constant (0x1UL) /*!< REG_A is intepreted as a constant. */
2025 
2026 /* Bits 22..18 : Operand A virtual register index. */
2027 #define CC_PKA_OPCODE_REG_A_Pos (18UL) /*!< Position of REG_A field. */
2028 #define CC_PKA_OPCODE_REG_A_Msk (0x1FUL << CC_PKA_OPCODE_REG_A_Pos) /*!< Bit mask of REG_A field. */
2029 
2030 /* Bit 17 : This field controls the interpretation of REG_B. */
2031 #define CC_PKA_OPCODE_CONST_B_Pos (17UL) /*!< Position of CONST_B field. */
2032 #define CC_PKA_OPCODE_CONST_B_Msk (0x1UL << CC_PKA_OPCODE_CONST_B_Pos) /*!< Bit mask of CONST_B field. */
2033 #define CC_PKA_OPCODE_CONST_B_Register (0x0UL) /*!< REG_B is intepreted as a register index. */
2034 #define CC_PKA_OPCODE_CONST_B_Constant (0x1UL) /*!< REG_B is intepreted as a constant. */
2035 
2036 /* Bits 16..12 : Operand B virtual register index. */
2037 #define CC_PKA_OPCODE_REG_B_Pos (12UL) /*!< Position of REG_B field. */
2038 #define CC_PKA_OPCODE_REG_B_Msk (0x1FUL << CC_PKA_OPCODE_REG_B_Pos) /*!< Bit mask of REG_B field. */
2039 
2040 /* Bit 11 : This field controls the interpretation of REG_R. */
2041 #define CC_PKA_OPCODE_DISCARD_R_Pos (11UL) /*!< Position of DISCARD_R field. */
2042 #define CC_PKA_OPCODE_DISCARD_R_Msk (0x1UL << CC_PKA_OPCODE_DISCARD_R_Pos) /*!< Bit mask of DISCARD_R field. */
2043 #define CC_PKA_OPCODE_DISCARD_R_Register (0x0UL) /*!< REG_R is intepreted as a register index. */
2044 #define CC_PKA_OPCODE_DISCARD_R_Discard (0x1UL) /*!< Result is discarded. */
2045 
2046 /* Bits 10..6 : Result register virtual register index. */
2047 #define CC_PKA_OPCODE_REG_R_Pos (6UL) /*!< Position of REG_R field. */
2048 #define CC_PKA_OPCODE_REG_R_Msk (0x1FUL << CC_PKA_OPCODE_REG_R_Pos) /*!< Bit mask of REG_R field. */
2049 
2050 /* Bits 5..0 : Holds the operation tag or the operand C virtual register index. */
2051 #define CC_PKA_OPCODE_TAG_Pos (0UL) /*!< Position of TAG field. */
2052 #define CC_PKA_OPCODE_TAG_Msk (0x3FUL << CC_PKA_OPCODE_TAG_Pos) /*!< Bit mask of TAG field. */
2053 
2054 /* Register: CC_PKA_N_NP_T0_T1_ADDR */
2055 /* Description: This register defines the N, Np, T0, and T1 virtual register index. */
2056 
2057 /* Bits 19..15 : Temporary register 1 virtual register index. Default is R31. */
2058 #define CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Pos (15UL) /*!< Position of T1_VIRTUAL_ADDR field. */
2059 #define CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Pos) /*!< Bit mask of T1_VIRTUAL_ADDR field. */
2060 
2061 /* Bits 14..10 : Temporary register 0 virtual register index. Default is R30. */
2062 #define CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Pos (10UL) /*!< Position of T0_VIRTUAL_ADDR field. */
2063 #define CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Pos) /*!< Bit mask of T0_VIRTUAL_ADDR field. */
2064 
2065 /* Bits 9..5 : Register Np virtual register index. Default is R1. */
2066 #define CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Pos (5UL) /*!< Position of NP_VIRTUAL_ADDR field. */
2067 #define CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Pos) /*!< Bit mask of NP_VIRTUAL_ADDR field. */
2068 
2069 /* Bits 4..0 : Register N virtual register index. Default is R0. */
2070 #define CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Pos (0UL) /*!< Position of N_VIRTUAL_ADDR field. */
2071 #define CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Pos) /*!< Bit mask of N_VIRTUAL_ADDR field. */
2072 
2073 /* Register: CC_PKA_PKA_STATUS */
2074 /* Description: This register holds the status for the PKA pipeline. */
2075 
2076 /* Bits 20..16 : Opcode of the last operation */
2077 #define CC_PKA_PKA_STATUS_OPCODE_Pos (16UL) /*!< Position of OPCODE field. */
2078 #define CC_PKA_PKA_STATUS_OPCODE_Msk (0x1FUL << CC_PKA_PKA_STATUS_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
2079 
2080 /* Bit 15 : Indicates the modular inverse of zero. */
2081 #define CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Pos (15UL) /*!< Position of MODINV_OF_ZERO field. */
2082 #define CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Pos) /*!< Bit mask of MODINV_OF_ZERO field. */
2083 
2084 /* Bit 14 : Indication if the division is done by zero. */
2085 #define CC_PKA_PKA_STATUS_DIV_BY_ZERO_Pos (14UL) /*!< Position of DIV_BY_ZERO field. */
2086 #define CC_PKA_PKA_STATUS_DIV_BY_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_DIV_BY_ZERO_Pos) /*!< Bit mask of DIV_BY_ZERO field. */
2087 
2088 /* Bit 13 : Modular overflow flag. */
2089 #define CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Pos (13UL) /*!< Position of ALU_MODOVRFLW field. */
2090 #define CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Pos) /*!< Bit mask of ALU_MODOVRFLW field. */
2091 
2092 /* Bit 12 : Indicates if the result of ALU OUT is zero. */
2093 #define CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Pos (12UL) /*!< Position of ALU_OUT_ZERO field. */
2094 #define CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Pos) /*!< Bit mask of ALU_OUT_ZERO field. */
2095 
2096 /* Bit 11 : Indicates the last subtraction operation sign. */
2097 #define CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Pos (11UL) /*!< Position of ALU_SUB_IS_ZERO field. */
2098 #define CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Pos) /*!< Bit mask of ALU_SUB_IS_ZERO field. */
2099 
2100 /* Bit 10 : Holds the carry of the last modular operation. */
2101 #define CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Pos (10UL) /*!< Position of ALU_CARRY_MOD field. */
2102 #define CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Pos) /*!< Bit mask of ALU_CARRY_MOD field. */
2103 
2104 /* Bit 9 : Holds the carry of the last ALU operation. */
2105 #define CC_PKA_PKA_STATUS_ALU_CARRY_Pos (9UL) /*!< Position of ALU_CARRY field. */
2106 #define CC_PKA_PKA_STATUS_ALU_CARRY_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_CARRY_Pos) /*!< Bit mask of ALU_CARRY field. */
2107 
2108 /* Bit 8 : Indicates the MSB sign of the last operation. */
2109 #define CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Pos (8UL) /*!< Position of ALU_SIGN_OUT field. */
2110 #define CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Pos) /*!< Bit mask of ALU_SIGN_OUT field. */
2111 
2112 /* Bits 7..4 : The least significant 4-bits of the operand updated in shift operation. */
2113 #define CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Pos (4UL) /*!< Position of ALU_LSB_4BITS field. */
2114 #define CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Msk (0xFUL << CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Pos) /*!< Bit mask of ALU_LSB_4BITS field. */
2115 
2116 /* Bits 3..0 : The most significant 4-bits of the operand updated in shift operation. */
2117 #define CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Pos (0UL) /*!< Position of ALU_MSB_4BITS field. */
2118 #define CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Msk (0xFUL << CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Pos) /*!< Bit mask of ALU_MSB_4BITS field. */
2119 
2120 /* Register: CC_PKA_PKA_SW_RESET */
2121 /* Description: Reset the PKA engine. */
2122 
2123 /* Bit 0 : Writing any value to this address resets the PKA engine. The reset takes 4 CPU clock cycles to complete. */
2124 #define CC_PKA_PKA_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
2125 #define CC_PKA_PKA_SW_RESET_RESET_Msk (0x1UL << CC_PKA_PKA_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
2126 #define CC_PKA_PKA_SW_RESET_RESET_Enable (0x1UL) /*!< Reset PKA engine. */
2127 
2128 /* Register: CC_PKA_PKA_L */
2129 /* Description: Description collection: This register holds the operands bit size. */
2130 
2131 /* Bits 12..0 : Operand bit size. */
2132 #define CC_PKA_PKA_L_OpSize_Pos (0UL) /*!< Position of OpSize field. */
2133 #define CC_PKA_PKA_L_OpSize_Msk (0x1FFFUL << CC_PKA_PKA_L_OpSize_Pos) /*!< Bit mask of OpSize field. */
2134 
2135 /* Register: CC_PKA_PKA_PIPE */
2136 /* Description: Status register indicating if the PKA pipeline is ready to receive a new OPCODE. */
2137 
2138 /* Bit 0 : PKA pipeline status. */
2139 #define CC_PKA_PKA_PIPE_STATUS_Pos (0UL) /*!< Position of STATUS field. */
2140 #define CC_PKA_PKA_PIPE_STATUS_Msk (0x1UL << CC_PKA_PKA_PIPE_STATUS_Pos) /*!< Bit mask of STATUS field. */
2141 #define CC_PKA_PKA_PIPE_STATUS_NotReady (0x0UL) /*!< PKA pipeline is not ready for a new OPCODE */
2142 #define CC_PKA_PKA_PIPE_STATUS_Ready (0x1UL) /*!< PKA pipeline is ready for a new OPCODE */
2143 
2144 /* Register: CC_PKA_PKA_DONE */
2145 /* Description: Status register indicating if the PKA operation has been completed. */
2146 
2147 /* Bit 0 : PKA operation status. */
2148 #define CC_PKA_PKA_DONE_STATUS_Pos (0UL) /*!< Position of STATUS field. */
2149 #define CC_PKA_PKA_DONE_STATUS_Msk (0x1UL << CC_PKA_PKA_DONE_STATUS_Pos) /*!< Bit mask of STATUS field. */
2150 #define CC_PKA_PKA_DONE_STATUS_Processing (0x0UL) /*!< PKA operation is processing */
2151 #define CC_PKA_PKA_DONE_STATUS_Completed (0x1UL) /*!< PKA operation is completed and pipeline is empty */
2152 
2153 /* Register: CC_PKA_PKA_VERSION */
2154 /* Description: PKA engine HW version. Reset value holds the version. */
2155 
2156 /* Bits 31..0 :   */
2157 #define CC_PKA_PKA_VERSION_PKA_VERSION_Pos (0UL) /*!< Position of PKA_VERSION field. */
2158 #define CC_PKA_PKA_VERSION_PKA_VERSION_Msk (0xFFFFFFFFUL << CC_PKA_PKA_VERSION_PKA_VERSION_Pos) /*!< Bit mask of PKA_VERSION field. */
2159 
2160 /* Register: CC_PKA_PKA_SRAM_WADDR */
2161 /* Description: Start address in PKA SRAM for subsequent write transactions. */
2162 
2163 /* Bits 31..0 : PKA SRAM start address for write transaction */
2164 #define CC_PKA_PKA_SRAM_WADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
2165 #define CC_PKA_PKA_SRAM_WADDR_ADDR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
2166 
2167 /* Register: CC_PKA_PKA_SRAM_WDATA */
2168 /* Description: Write data to PKA SRAM. Writing to this register triggers a DMA transaction writing data into PKA SRAM. The DMA address offset is automatically incremented during write. */
2169 
2170 /* Bits 31..0 : Data to write to PKA SRAM. */
2171 #define CC_PKA_PKA_SRAM_WDATA_DATA_Pos (0UL) /*!< Position of DATA field. */
2172 #define CC_PKA_PKA_SRAM_WDATA_DATA_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WDATA_DATA_Pos) /*!< Bit mask of DATA field. */
2173 
2174 /* Register: CC_PKA_PKA_SRAM_RDATA */
2175 /* Description: Read data from PKA SRAM. Reading from this register triggers a DMA transaction read data from PKA SRAM. The DMA address offset is automatically incremented during read. */
2176 
2177 /* Bits 31..0 : Data to read from PKA SRAM */
2178 #define CC_PKA_PKA_SRAM_RDATA_DATA_Pos (0UL) /*!< Position of DATA field. */
2179 #define CC_PKA_PKA_SRAM_RDATA_DATA_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_RDATA_DATA_Pos) /*!< Bit mask of DATA field. */
2180 
2181 /* Register: CC_PKA_PKA_SRAM_WCLEAR */
2182 /* Description: Register for clearing PKA SRAM write buffer. */
2183 
2184 /* Bits 31..0 : Clear the PKA SRAM write buffer. */
2185 #define CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */
2186 #define CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Pos) /*!< Bit mask of CLEAR field. */
2187 
2188 /* Register: CC_PKA_PKA_SRAM_RADDR */
2189 /* Description: Start address in PKA SRAM for subsequent read transactions. */
2190 
2191 /* Bits 31..0 : PKA SRAM start address for read transaction */
2192 #define CC_PKA_PKA_SRAM_RADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
2193 #define CC_PKA_PKA_SRAM_RADDR_ADDR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_RADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
2194 
2195 
2196 /* Peripheral: CC_RNG */
2197 /* Description: CRYPTOCELL RNG engine */
2198 
2199 /* Register: CC_RNG_RNG_IMR */
2200 /* Description: Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. */
2201 
2202 /* Bit 5 : See RNG_ISR for explanation on this interrupt. */
2203 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_Pos (5UL) /*!< Position of DMA_DONE_MASK field. */
2204 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_DMA_DONE_MASK_Pos) /*!< Bit mask of DMA_DONE_MASK field. */
2205 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_IRQEnable (0x0UL) /*!< Do not mask the RNG DMA completion interrupt i.e. interrupt is generated */
2206 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_IRQDisable (0x1UL) /*!< Mask the RNG DMA completion interrupt i.e. no interrupt is generated */
2207 
2208 /* Bit 4 : See RNG_ISR for explanation on this interrupt. */
2209 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_Pos (4UL) /*!< Position of WATCHDOG_MASK field. */
2210 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_WATCHDOG_MASK_Pos) /*!< Bit mask of WATCHDOG_MASK field. */
2211 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_IRQEnable (0x0UL) /*!< Do not mask the watchdog interrupt i.e. interrupt is generated */
2212 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_IRQDisable (0x1UL) /*!< Mask the watchdog interrupt i.e. no interrupt is generated */
2213 
2214 /* Bit 3 : See RNG_ISR for explanation on this interrupt. */
2215 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_Pos (3UL) /*!< Position of VNC_ERR_MASK field. */
2216 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_VNC_ERR_MASK_Pos) /*!< Bit mask of VNC_ERR_MASK field. */
2217 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask the von Neumann corrector error interrupt i.e. interrupt is generated */
2218 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_IRQDisable (0x1UL) /*!< Mask the von Neumann corrector error interrupt i.e. no interrupt is generated */
2219 
2220 /* Bit 2 : See RNG_ISR for explanation on this interrupt. */
2221 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Pos (2UL) /*!< Position of CRNGT_ERR_MASK field. */
2222 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Pos) /*!< Bit mask of CRNGT_ERR_MASK field. */
2223 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask the CRNGT error interrupt i.e. interrupt is generated */
2224 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_IRQDisable (0x1UL) /*!< Mask the CRNGT error interrupt i.e. no interrupt is generated */
2225 
2226 /* Bit 1 : See RNG_ISR for explanation on this interrupt. */
2227 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Pos (1UL) /*!< Position of AUTOCORR_ERR_MASK field. */
2228 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Pos) /*!< Bit mask of AUTOCORR_ERR_MASK field. */
2229 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask autocorrelation interrupt i.e. interrupt is generated */
2230 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_IRQDisable (0x1UL) /*!< Mask autocorrelation interrupt i.e. no interrupt is generated */
2231 
2232 /* Bit 0 : See RNG_ISR for explanation on this interrupt. */
2233 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_Pos (0UL) /*!< Position of EHR_VALID_MASK field. */
2234 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_EHR_VALID_MASK_Pos) /*!< Bit mask of EHR_VALID_MASK field. */
2235 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_IRQEnable (0x0UL) /*!< Do not mask EHR interrupt i.e. interrupt is generated */
2236 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_IRQDisable (0x1UL) /*!< Mask EHR interrupt i.e. no interrupt is generated */
2237 
2238 /* Register: CC_RNG_RNG_ISR */
2239 /* Description: Interrupt status register. Each bit of this register holds the interrupt
2240         status of a single interrupt source. If corresponding RNG_IMR bit is
2241         unmasked, an interrupt is generated. */
2242 
2243 /* Bit 5 : RNG DMA to SRAM is completed. */
2244 #define CC_RNG_RNG_ISR_DMA_DONE_INT_Pos (5UL) /*!< Position of DMA_DONE_INT field. */
2245 #define CC_RNG_RNG_ISR_DMA_DONE_INT_Msk (0x1UL << CC_RNG_RNG_ISR_DMA_DONE_INT_Pos) /*!< Bit mask of DMA_DONE_INT field. */
2246 
2247 /* Bit 4 : Maximum number of CPU clock cycles per sample have been exceeded. See RNG_WATCHDOG_VAL for more information. */
2248 #define CC_RNG_RNG_ISR_WATCHDOG_INT_Pos (4UL) /*!< Position of WATCHDOG_INT field. */
2249 #define CC_RNG_RNG_ISR_WATCHDOG_INT_Msk (0x1UL << CC_RNG_RNG_ISR_WATCHDOG_INT_Pos) /*!< Bit mask of WATCHDOG_INT field. */
2250 
2251 /* Bit 3 : von Neumann corrector error. Failure occurs if 32 consecutive collected bits are identical, ZERO, or ONE. */
2252 #define CC_RNG_RNG_ISR_VNC_ERR_INT_Pos (3UL) /*!< Position of VNC_ERR_INT field. */
2253 #define CC_RNG_RNG_ISR_VNC_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_VNC_ERR_INT_Pos) /*!< Bit mask of VNC_ERR_INT field. */
2254 
2255 /* Bit 2 : Continuous random number generator test error. Failure occurs when two consecutive blocks of 16 collected bits are equal. */
2256 #define CC_RNG_RNG_ISR_CRNGT_ERR_INT_Pos (2UL) /*!< Position of CRNGT_ERR_INT field. */
2257 #define CC_RNG_RNG_ISR_CRNGT_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_CRNGT_ERR_INT_Pos) /*!< Bit mask of CRNGT_ERR_INT field. */
2258 
2259 /* Bit 1 : Autocorrelation error. Failure occurs when autocorrelation test has failed four times in a row. Once set, the TRNG ceases to function until next reset. */
2260 #define CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Pos (1UL) /*!< Position of AUTOCORR_ERR_INT field. */
2261 #define CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Pos) /*!< Bit mask of AUTOCORR_ERR_INT field. */
2262 
2263 /* Bit 0 : 192-bits have been collected and are ready to be read. */
2264 #define CC_RNG_RNG_ISR_EHR_VALID_INT_Pos (0UL) /*!< Position of EHR_VALID_INT field. */
2265 #define CC_RNG_RNG_ISR_EHR_VALID_INT_Msk (0x1UL << CC_RNG_RNG_ISR_EHR_VALID_INT_Pos) /*!< Bit mask of EHR_VALID_INT field. */
2266 
2267 /* Register: CC_RNG_RNG_ICR */
2268 /* Description: Interrupt clear register. Writing a 1 bit into a field in this register
2269         will clear the corresponding bit in RNG_ISR. */
2270 
2271 /* Bit 5 : Writing value '1' clears corresponding bit in RNG_ISR */
2272 #define CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Pos (5UL) /*!< Position of DMA_DONE_CLEAR field. */
2273 #define CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Pos) /*!< Bit mask of DMA_DONE_CLEAR field. */
2274 
2275 /* Bit 4 : Writing value '1' clears corresponding bit in RNG_ISR */
2276 #define CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Pos (4UL) /*!< Position of WATCHDOG_CLEAR field. */
2277 #define CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Pos) /*!< Bit mask of WATCHDOG_CLEAR field. */
2278 
2279 /* Bit 3 : Writing value '1' clears corresponding bit in RNG_ISR */
2280 #define CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Pos (3UL) /*!< Position of VNC_ERR_CLEAR field. */
2281 #define CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Pos) /*!< Bit mask of VNC_ERR_CLEAR field. */
2282 
2283 /* Bit 2 : Writing value '1' clears corresponding bit in RNG_ISR */
2284 #define CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Pos (2UL) /*!< Position of CRNGT_ERR_CLEAR field. */
2285 #define CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Pos) /*!< Bit mask of CRNGT_ERR_CLEAR field. */
2286 
2287 /* Bit 1 : Cannot be cleared by software! Only RNG reset clears this bit. */
2288 #define CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Pos (1UL) /*!< Position of AUTOCORR_ERR_CLEAR field. */
2289 #define CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Pos) /*!< Bit mask of AUTOCORR_ERR_CLEAR field. */
2290 
2291 /* Bit 0 : Writing value '1' clears corresponding bit in RNG_ISR */
2292 #define CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Pos (0UL) /*!< Position of EHR_VALID_CLEAR field. */
2293 #define CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Pos) /*!< Bit mask of EHR_VALID_CLEAR field. */
2294 
2295 /* Register: CC_RNG_TRNG_CONFIG */
2296 /* Description: TRNG ring oscillator length configuration */
2297 
2298 /* Bits 1..0 : Set the length of the oscillator ring (= the number of inverters) out of four possible configurations. */
2299 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_Pos (0UL) /*!< Position of ROSC_LEN field. */
2300 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_Msk (0x3UL << CC_RNG_TRNG_CONFIG_ROSC_LEN_Pos) /*!< Bit mask of ROSC_LEN field. */
2301 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC1 (0x0UL) /*!< Use shortest ROSC1 ring oscillator configuration. */
2302 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC2 (0x1UL) /*!< Use ROSC2 ring oscillator configuration. */
2303 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC3 (0x2UL) /*!< Use ROSC3 ring oscillator configuration. */
2304 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC4 (0x3UL) /*!< Use longest ROSC4 ring oscillator configuration. */
2305 
2306 /* Register: CC_RNG_TRNG_VALID */
2307 /* Description: This register indicates if TRNG entropy collection is valid. */
2308 
2309 /* Bit 0 : A value of 1 indicates that collection of bits in the TRNG is completed, and data can be read from EHR_DATA registers. */
2310 #define CC_RNG_TRNG_VALID_EHR_DATA_Pos (0UL) /*!< Position of EHR_DATA field. */
2311 #define CC_RNG_TRNG_VALID_EHR_DATA_Msk (0x1UL << CC_RNG_TRNG_VALID_EHR_DATA_Pos) /*!< Bit mask of EHR_DATA field. */
2312 #define CC_RNG_TRNG_VALID_EHR_DATA_NotValid (0x0UL) /*!< Collection of bits not valid. */
2313 #define CC_RNG_TRNG_VALID_EHR_DATA_Valid (0x1UL) /*!< Collection of bits valid. */
2314 
2315 /* Register: CC_RNG_EHR_DATA */
2316 /* Description: Description collection: The entropy holding registers (EHR) hold 192-bits random data collected by the TRNG. The initial EHR_DATA[0] register holds the least significant bits [31:0] of the random data value. */
2317 
2318 /* Bits 31..0 : Random data value. */
2319 #define CC_RNG_EHR_DATA_VALUE_Pos (0UL) /*!< Position of VALUE field. */
2320 #define CC_RNG_EHR_DATA_VALUE_Msk (0xFFFFFFFFUL << CC_RNG_EHR_DATA_VALUE_Pos) /*!< Bit mask of VALUE field. */
2321 
2322 /* Register: CC_RNG_NOISE_SOURCE */
2323 /* Description: This register controls the ring oscillator circuit used as a noise source. */
2324 
2325 /* Bit 0 : Enable or disable the noise source. */
2326 #define CC_RNG_NOISE_SOURCE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2327 #define CC_RNG_NOISE_SOURCE_ENABLE_Msk (0x1UL << CC_RNG_NOISE_SOURCE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2328 #define CC_RNG_NOISE_SOURCE_ENABLE_Disabled (0x0UL) /*!< Noise source is disabled */
2329 #define CC_RNG_NOISE_SOURCE_ENABLE_Enabled (0x1UL) /*!< Noise source is enabled */
2330 
2331 /* Register: CC_RNG_SAMPLE_CNT */
2332 /* Description: Sample count defining the number of CPU clock cycles between two consecutive noise source samples. */
2333 
2334 /* Bits 31..0 : Number of CPU clock cycles between two consecutive noise source samples. */
2335 #define CC_RNG_SAMPLE_CNT_VALUE_Pos (0UL) /*!< Position of VALUE field. */
2336 #define CC_RNG_SAMPLE_CNT_VALUE_Msk (0xFFFFFFFFUL << CC_RNG_SAMPLE_CNT_VALUE_Pos) /*!< Bit mask of VALUE field. */
2337 
2338 /* Register: CC_RNG_AUTOCORR_STATISTIC */
2339 /* Description: Statistics counter for autocorrelation test activations. Statistics collection is stopped if one of the counters reach its limit of all ones. */
2340 
2341 /* Bits 21..14 : Count each time an autocorrelation test fails. Any write to the field resets the counter. */
2342 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Pos (14UL) /*!< Position of AUTOCORR_FAILS field. */
2343 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Msk (0xFFUL << CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Pos) /*!< Bit mask of AUTOCORR_FAILS field. */
2344 
2345 /* Bits 13..0 : Count each time an autocorrelation test starts. Any write to the field resets the counter. */
2346 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Pos (0UL) /*!< Position of AUTOCORR_TRYS field. */
2347 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Msk (0x3FFFUL << CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Pos) /*!< Bit mask of AUTOCORR_TRYS field. */
2348 
2349 /* Register: CC_RNG_TRNG_DEBUG */
2350 /* Description: Debug register for the TRNG. This register is used to bypass TRNG tests in hardware. */
2351 
2352 /* Bit 3 : Bypass the autocorrelation test. */
2353 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Pos (3UL) /*!< Position of AUTOCORR_BYPASS field. */
2354 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Pos) /*!< Bit mask of AUTOCORR_BYPASS field. */
2355 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Disabled (0x0UL) /*!< Autocorrelation test is active */
2356 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Enabled (0x1UL) /*!< Bypass the autocorrelation test */
2357 
2358 /* Bit 2 : Bypass the Continuous Random Number Generator Test (CRNGT). */
2359 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Pos (2UL) /*!< Position of CRNGT_BYPASS field. */
2360 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Pos) /*!< Bit mask of CRNGT_BYPASS field. */
2361 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Disabled (0x0UL) /*!< CRNGT is active */
2362 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Enabled (0x1UL) /*!< Bypass CRNGT */
2363 
2364 /* Bit 1 : Bypass the von Neumann corrector post-processing test, including the 32 consecutive bits test. */
2365 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Pos (1UL) /*!< Position of VNC_BYPASS field. */
2366 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_VNC_BYPASS_Pos) /*!< Bit mask of VNC_BYPASS field. */
2367 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Disabled (0x0UL) /*!< von Neumann corrector post-processing is active */
2368 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Enabled (0x1UL) /*!< Bypass the von Neumann corrector */
2369 
2370 /* Register: CC_RNG_RNG_SW_RESET */
2371 /* Description: Reset the RNG engine. */
2372 
2373 /* Bit 0 : Writing any value to this address resets the RNG engine. The reset takes 4 CPU clock cycles to complete. */
2374 #define CC_RNG_RNG_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
2375 #define CC_RNG_RNG_SW_RESET_RESET_Msk (0x1UL << CC_RNG_RNG_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
2376 #define CC_RNG_RNG_SW_RESET_RESET_Enable (0x1UL) /*!< Reset RNG engine. */
2377 
2378 /* Register: CC_RNG_RNG_BUSY */
2379 /* Description: Status register for RNG engine activity. */
2380 
2381 /* Bit 1 : TRNG status. */
2382 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Pos (1UL) /*!< Position of TRNG_STATUS field. */
2383 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Msk (0x1UL << CC_RNG_RNG_BUSY_TRNG_STATUS_Pos) /*!< Bit mask of TRNG_STATUS field. */
2384 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Idle (0x0UL) /*!< TRNG is idle */
2385 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Busy (0x1UL) /*!< TRNG is busy */
2386 
2387 /* Bit 0 : RNG engine status. */
2388 #define CC_RNG_RNG_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
2389 #define CC_RNG_RNG_BUSY_STATUS_Msk (0x1UL << CC_RNG_RNG_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
2390 #define CC_RNG_RNG_BUSY_STATUS_Idle (0x0UL) /*!< RNG engine is idle */
2391 #define CC_RNG_RNG_BUSY_STATUS_Busy (0x1UL) /*!< RNG engine is busy */
2392 
2393 /* Register: CC_RNG_TRNG_RESET */
2394 /* Description: Reset the TRNG, including internal counter of collected bits and registers EHR_DATA and TRNG_VALID. */
2395 
2396 /* Bit 0 : Writing any value to this address resets the internal bits counter and registers EHR_DATA and TRNG_VALID. Register NOISE_SOURCE must be disabled in order for the reset to take place. */
2397 #define CC_RNG_TRNG_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
2398 #define CC_RNG_TRNG_RESET_RESET_Msk (0x1UL << CC_RNG_TRNG_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
2399 #define CC_RNG_TRNG_RESET_RESET_Enable (0x1UL) /*!< Reset TRNG. */
2400 
2401 /* Register: CC_RNG_RNG_HW_FLAGS */
2402 /* Description: Hardware configuration of RNG engine. Reset value holds the supported features. */
2403 
2404 /* Bit 7 :   */
2405 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Pos (7UL) /*!< Position of RNG_USE_5_SBOXES field. */
2406 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Pos) /*!< Bit mask of RNG_USE_5_SBOXES field. */
2407 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Disable (0x0UL) /*!< 20 SBOX AES */
2408 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Enable (0x1UL) /*!< 5 SBOX AES */
2409 
2410 /* Bit 6 : If this flag is set, the engine include support for automatic reseeding. */
2411 #define CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Pos (6UL) /*!< Position of RESEEDING_EXISTS field. */
2412 #define CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Pos) /*!< Bit mask of RESEEDING_EXISTS field. */
2413 
2414 /* Bit 5 : If this flag is set, the engine include support for known answer tests. */
2415 #define CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Pos (5UL) /*!< Position of KAT_EXISTS field. */
2416 #define CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Pos) /*!< Bit mask of KAT_EXISTS field. */
2417 
2418 /* Bit 4 : If this flag is set, the engine include a pseudo-random number generator. */
2419 #define CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Pos (4UL) /*!< Position of PRNG_EXISTS field. */
2420 #define CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Pos) /*!< Bit mask of PRNG_EXISTS field. */
2421 
2422 /* Bit 3 : If this flag is set, the engine include support for bypassing TRNG tests. */
2423 #define CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Pos (3UL) /*!< Position of BYPASS_EXISTS field. */
2424 #define CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Pos) /*!< Bit mask of BYPASS_EXISTS field. */
2425 
2426 /* Bit 2 : If this flag is set, the engine include support for autocorrelation test. */
2427 #define CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Pos (2UL) /*!< Position of AUTOCORR_EXISTS field. */
2428 #define CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Pos) /*!< Bit mask of AUTOCORR_EXISTS field. */
2429 
2430 /* Bit 1 : If this flag is set, the engine include support for continuous random number generator test. */
2431 #define CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Pos (1UL) /*!< Position of CRNGT_EXISTS field. */
2432 #define CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Pos) /*!< Bit mask of CRNGT_EXISTS field. */
2433 
2434 /* Bit 0 : Data width supported by the entropy collector */
2435 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Pos (0UL) /*!< Position of EHR_WIDTH field. */
2436 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Pos) /*!< Bit mask of EHR_WIDTH field. */
2437 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_128Bits (0x0UL) /*!< 128 bits EHR width */
2438 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_192Bits (0x1UL) /*!< 192 bits EHR width */
2439 
2440 /* Register: CC_RNG_RNG_CLK */
2441 /* Description: Control clock for the RNG engine. */
2442 
2443 /* Bit 0 : Enables clock for the RNG engine. */
2444 #define CC_RNG_RNG_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2445 #define CC_RNG_RNG_CLK_ENABLE_Msk (0x1UL << CC_RNG_RNG_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2446 #define CC_RNG_RNG_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for RNG engine. */
2447 #define CC_RNG_RNG_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for RNG engine. */
2448 
2449 /* Register: CC_RNG_RNG_DMA */
2450 /* Description: Writing to this register enables the RNG DMA engine. */
2451 
2452 /* Bit 0 :   */
2453 #define CC_RNG_RNG_DMA_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2454 #define CC_RNG_RNG_DMA_ENABLE_Msk (0x1UL << CC_RNG_RNG_DMA_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2455 #define CC_RNG_RNG_DMA_ENABLE_Disable (0x0UL) /*!< Disable RNG DMA engine */
2456 #define CC_RNG_RNG_DMA_ENABLE_Enable (0x1UL) /*!< Enable RNG DMA engine This value is cleared when the RNG DMA engine completes its operation. */
2457 
2458 /* Register: CC_RNG_RNG_DMA_ROSC_LEN */
2459 /* Description: This register defines which ring oscillator length configuration should be used when using the RNG DMA engine. */
2460 
2461 /* Bit 3 : Use longest ROSC4 ring oscillator configuration. */
2462 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Pos (3UL) /*!< Position of ROSC4 field. */
2463 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */
2464 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Disable (0x0UL) /*!< Disable ROSC4 */
2465 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Enable (0x1UL) /*!< Enable ROSC4 */
2466 
2467 /* Bit 2 : Use ROSC3 ring oscillator configuration. */
2468 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Pos (2UL) /*!< Position of ROSC3 field. */
2469 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */
2470 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Disable (0x0UL) /*!< Disable ROSC3 */
2471 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Enable (0x1UL) /*!< Enable ROSC3 */
2472 
2473 /* Bit 1 : Use ROSC2 ring oscillator configuration. */
2474 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Pos (1UL) /*!< Position of ROSC2 field. */
2475 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */
2476 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Disable (0x0UL) /*!< Disable ROSC2 */
2477 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Enable (0x1UL) /*!< Enable ROSC2 */
2478 
2479 /* Bit 0 : Use shortest ROSC1 ring oscillator configuration. */
2480 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
2481 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */
2482 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Disable (0x0UL) /*!< Disable ROSC1 */
2483 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Enable (0x1UL) /*!< Enable ROSC1 */
2484 
2485 /* Register: CC_RNG_RNG_DMA_SRAM_ADDR */
2486 /* Description: This register defines the start address in TRNG SRAM for the TRNG data to be collected by the RNG DMA engine. */
2487 
2488 /* Bits 10..0 : Start address of the TRNG data in TRNG SRAM. */
2489 #define CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Pos (0UL) /*!< Position of RNG_SRAM_DMA_ADDR field. */
2490 #define CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Msk (0x7FFUL << CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Pos) /*!< Bit mask of RNG_SRAM_DMA_ADDR field. */
2491 
2492 /* Register: CC_RNG_RNG_DMA_SAMPLES_NUM */
2493 /* Description: This register defines the number of 192-bits samples that the RNG DMA engine collects per run. */
2494 
2495 /* Bits 7..0 : Defines the number of 192-bits samples that the DMA engine collects per run. */
2496 #define CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Pos (0UL) /*!< Position of RNG_SAMPLES_NUM field. */
2497 #define CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Msk (0xFFUL << CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Pos) /*!< Bit mask of RNG_SAMPLES_NUM field. */
2498 
2499 /* Register: CC_RNG_RNG_WATCHDOG_VAL */
2500 /* Description: This register defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. */
2501 
2502 /* Bits 31..0 : Defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. */
2503 #define CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Pos (0UL) /*!< Position of RNG_WATCHDOG_VAL field. */
2504 #define CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Msk (0xFFFFFFFFUL << CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Pos) /*!< Bit mask of RNG_WATCHDOG_VAL field. */
2505 
2506 /* Register: CC_RNG_RNG_DMA_BUSY */
2507 /* Description: Status register for RNG DMA engine activity. */
2508 
2509 /* Bits 10..3 : Number of samples already collected using the current ring oscillator configuration. */
2510 #define CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Pos (3UL) /*!< Position of NUM_OF_SAMPLES field. */
2511 #define CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Msk (0xFFUL << CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Pos) /*!< Bit mask of NUM_OF_SAMPLES field. */
2512 
2513 /* Bits 2..1 : The active ring oscillator length configuration used by the RNG DMA engine. */
2514 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Pos (1UL) /*!< Position of ROSC_LEN field. */
2515 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Msk (0x3UL << CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Pos) /*!< Bit mask of ROSC_LEN field. */
2516 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC1 (0x0UL) /*!< Shortest ROSC1 ring oscillator configuration used. */
2517 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC2 (0x1UL) /*!< ROSC2 ring oscillator configuration used. */
2518 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC3 (0x2UL) /*!< ROSC3 ring oscillator configuration used. */
2519 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC4 (0x3UL) /*!< Longest ROSC4 ring oscillator configuration used. */
2520 
2521 /* Bit 0 : RNG DMA engine status. */
2522 #define CC_RNG_RNG_DMA_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
2523 #define CC_RNG_RNG_DMA_BUSY_STATUS_Msk (0x1UL << CC_RNG_RNG_DMA_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
2524 #define CC_RNG_RNG_DMA_BUSY_STATUS_Idle (0x0UL) /*!< RNG DMA engine is idle */
2525 #define CC_RNG_RNG_DMA_BUSY_STATUS_Busy (0x1UL) /*!< RNG DMA engine is busy */
2526 
2527 
2528 /* Peripheral: CC_RNG_SRAM */
2529 /* Description: CRYPTOCELL RNG SRAM interface */
2530 
2531 /* Register: CC_RNG_SRAM_SRAM_DATA */
2532 /* Description: Read/Write data from RNG SRAM */
2533 
2534 /* Bits 31..0 : 32 bits DMA read/write from/to RNG SRAM. A 'read' or 'write' operation to this register will trigger the DMA address to be automatically incremented. */
2535 #define CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Pos (0UL) /*!< Position of SRAM_DATA field. */
2536 #define CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Msk (0xFFFFFFFFUL << CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Pos) /*!< Bit mask of SRAM_DATA field. */
2537 
2538 /* Register: CC_RNG_SRAM_SRAM_ADDR */
2539 /* Description: First address given to RNG SRAM DMA for read/write transactions from/to RNG SRAM. */
2540 
2541 /* Bits 14..0 : RNG SRAM starting address */
2542 #define CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Pos (0UL) /*!< Position of SRAM_ADDR field. */
2543 #define CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Msk (0x7FFFUL << CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Pos) /*!< Bit mask of SRAM_ADDR field. */
2544 
2545 /* Register: CC_RNG_SRAM_SRAM_DATA_READY */
2546 /* Description: RNG SRAM DMA engine is ready to read/write from/to RNG SRAM. */
2547 
2548 /* Bit 0 : RNG SRAM DMA status. */
2549 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Pos (0UL) /*!< Position of SRAM_READY field. */
2550 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Msk (0x1UL << CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Pos) /*!< Bit mask of SRAM_READY field. */
2551 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Busy (0x0UL) /*!< DMA is busy */
2552 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Idle (0x1UL) /*!< DMA is idle */
2553 
2554 
2555 /* Peripheral: CLOCK */
2556 /* Description: Clock management 0 */
2557 
2558 /* Register: CLOCK_TASKS_HFCLKSTART */
2559 /* Description: Start HFCLK source */
2560 
2561 /* Bit 0 : Start HFCLK source */
2562 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
2563 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
2564 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (0x1UL) /*!< Trigger task */
2565 
2566 /* Register: CLOCK_TASKS_HFCLKSTOP */
2567 /* Description: Stop HFCLK source */
2568 
2569 /* Bit 0 : Stop HFCLK source */
2570 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
2571 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
2572 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */
2573 
2574 /* Register: CLOCK_TASKS_LFCLKSTART */
2575 /* Description: Start LFCLK source */
2576 
2577 /* Bit 0 : Start LFCLK source */
2578 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
2579 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
2580 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (0x1UL) /*!< Trigger task */
2581 
2582 /* Register: CLOCK_TASKS_LFCLKSTOP */
2583 /* Description: Stop LFCLK source */
2584 
2585 /* Bit 0 : Stop LFCLK source */
2586 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
2587 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
2588 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */
2589 
2590 /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */
2591 /* Description: Subscribe configuration for task HFCLKSTART */
2592 
2593 /* Bit 31 :   */
2594 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
2595 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
2596 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0x0UL) /*!< Disable subscription */
2597 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (0x1UL) /*!< Enable subscription */
2598 
2599 /* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */
2600 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2601 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2602 
2603 /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */
2604 /* Description: Subscribe configuration for task HFCLKSTOP */
2605 
2606 /* Bit 31 :   */
2607 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
2608 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
2609 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */
2610 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */
2611 
2612 /* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */
2613 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2614 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2615 
2616 /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */
2617 /* Description: Subscribe configuration for task LFCLKSTART */
2618 
2619 /* Bit 31 :   */
2620 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
2621 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
2622 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0x0UL) /*!< Disable subscription */
2623 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (0x1UL) /*!< Enable subscription */
2624 
2625 /* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */
2626 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2627 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2628 
2629 /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */
2630 /* Description: Subscribe configuration for task LFCLKSTOP */
2631 
2632 /* Bit 31 :   */
2633 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
2634 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
2635 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */
2636 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */
2637 
2638 /* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */
2639 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2640 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2641 
2642 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
2643 /* Description: HFCLK oscillator started */
2644 
2645 /* Bit 0 : HFCLK oscillator started */
2646 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
2647 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
2648 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
2649 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (0x1UL) /*!< Event generated */
2650 
2651 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
2652 /* Description: LFCLK started */
2653 
2654 /* Bit 0 : LFCLK started */
2655 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
2656 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
2657 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
2658 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (0x1UL) /*!< Event generated */
2659 
2660 /* Register: CLOCK_PUBLISH_HFCLKSTARTED */
2661 /* Description: Publish configuration for event HFCLKSTARTED */
2662 
2663 /* Bit 31 :   */
2664 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
2665 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
2666 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
2667 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
2668 
2669 /* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to */
2670 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2671 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2672 
2673 /* Register: CLOCK_PUBLISH_LFCLKSTARTED */
2674 /* Description: Publish configuration for event LFCLKSTARTED */
2675 
2676 /* Bit 31 :   */
2677 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
2678 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
2679 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
2680 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
2681 
2682 /* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to */
2683 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2684 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2685 
2686 /* Register: CLOCK_INTEN */
2687 /* Description: Enable or disable interrupt */
2688 
2689 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
2690 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
2691 #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
2692 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0x0UL) /*!< Disable */
2693 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (0x1UL) /*!< Enable */
2694 
2695 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */
2696 #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
2697 #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
2698 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0x0UL) /*!< Disable */
2699 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (0x1UL) /*!< Enable */
2700 
2701 /* Register: CLOCK_INTENSET */
2702 /* Description: Enable interrupt */
2703 
2704 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
2705 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
2706 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
2707 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
2708 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
2709 #define CLOCK_INTENSET_LFCLKSTARTED_Set (0x1UL) /*!< Enable */
2710 
2711 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
2712 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
2713 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
2714 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
2715 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
2716 #define CLOCK_INTENSET_HFCLKSTARTED_Set (0x1UL) /*!< Enable */
2717 
2718 /* Register: CLOCK_INTENCLR */
2719 /* Description: Disable interrupt */
2720 
2721 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
2722 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
2723 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
2724 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
2725 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
2726 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (0x1UL) /*!< Disable */
2727 
2728 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
2729 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
2730 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
2731 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
2732 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
2733 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (0x1UL) /*!< Disable */
2734 
2735 /* Register: CLOCK_INTPEND */
2736 /* Description: Pending interrupts */
2737 
2738 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */
2739 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
2740 #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
2741 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0x0UL) /*!< Read: Not pending */
2742 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (0x1UL) /*!< Read: Pending */
2743 
2744 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */
2745 #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
2746 #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
2747 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0x0UL) /*!< Read: Not pending */
2748 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (0x1UL) /*!< Read: Pending */
2749 
2750 /* Register: CLOCK_HFCLKRUN */
2751 /* Description: Status indicating that HFCLKSTART task has been triggered */
2752 
2753 /* Bit 0 : HFCLKSTART task triggered or not */
2754 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
2755 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
2756 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */
2757 #define CLOCK_HFCLKRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */
2758 
2759 /* Register: CLOCK_HFCLKSTAT */
2760 /* Description: The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE). */
2761 
2762 /* Bit 16 : HFCLK state */
2763 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
2764 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
2765 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0x0UL) /*!< HFXO has not been started or HFCLKSTOP task has been triggered */
2766 #define CLOCK_HFCLKSTAT_STATE_Running (0x1UL) /*!< HFXO has been started (HFCLKSTARTED event has been generated) */
2767 
2768 /* Bit 0 : Active clock source */
2769 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
2770 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
2771 #define CLOCK_HFCLKSTAT_SRC_HFINT (0x0UL) /*!< HFINT - 64 MHz on-chip oscillator */
2772 #define CLOCK_HFCLKSTAT_SRC_HFXO (0x1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */
2773 
2774 /* Register: CLOCK_LFCLKRUN */
2775 /* Description: Status indicating that LFCLKSTART task has been triggered */
2776 
2777 /* Bit 0 : LFCLKSTART task triggered or not */
2778 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
2779 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
2780 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */
2781 #define CLOCK_LFCLKRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */
2782 
2783 /* Register: CLOCK_LFCLKSTAT */
2784 /* Description: The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE). */
2785 
2786 /* Bit 16 : LFCLK state */
2787 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
2788 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
2789 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0x0UL) /*!< Requested LFCLK source has not been started or LFCLKSTOP task has been triggered */
2790 #define CLOCK_LFCLKSTAT_STATE_Running (0x1UL) /*!< Requested LFCLK source has been started (LFCLKSTARTED event has been generated) */
2791 
2792 /* Bits 1..0 : Active clock source */
2793 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
2794 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
2795 #define CLOCK_LFCLKSTAT_SRC_RFU (0x0UL) /*!< Reserved for future use */
2796 #define CLOCK_LFCLKSTAT_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */
2797 #define CLOCK_LFCLKSTAT_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */
2798 
2799 /* Register: CLOCK_LFCLKSRCCOPY */
2800 /* Description: Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered */
2801 
2802 /* Bits 1..0 : Clock source */
2803 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
2804 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
2805 #define CLOCK_LFCLKSRCCOPY_SRC_RFU (0x0UL) /*!< Reserved for future use */
2806 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */
2807 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */
2808 
2809 /* Register: CLOCK_LFCLKSRC */
2810 /* Description: Clock source for the LFCLK. LFCLKSTART task starts a clock source selected with this register. */
2811 
2812 /* Bits 1..0 : Clock source */
2813 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
2814 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
2815 #define CLOCK_LFCLKSRC_SRC_RFU (0x0UL) /*!< Reserved for future use (equals selecting LFRC) */
2816 #define CLOCK_LFCLKSRC_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */
2817 #define CLOCK_LFCLKSRC_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */
2818 
2819 
2820 /* Peripheral: CRYPTOCELL */
2821 /* Description: CRYPTOCELL register interface */
2822 
2823 /* Register: CRYPTOCELL_ENABLE */
2824 /* Description: Enable CRYPTOCELL subsystem. */
2825 
2826 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem. */
2827 #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2828 #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2829 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0x0UL) /*!< CRYPTOCELL subsystem disabled. */
2830 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (0x1UL) /*!< CRYPTOCELL subsystem enabled. */
2831 
2832 
2833 /* Peripheral: CTRLAPPERI */
2834 /* Description: Control access port */
2835 
2836 /* Register: CTRLAPPERI_MAILBOX_RXDATA */
2837 /* Description: Data sent from the debugger to the CPU. */
2838 
2839 /* Bits 31..0 : Data received from debugger */
2840 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */
2841 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */
2842 
2843 /* Register: CTRLAPPERI_MAILBOX_RXSTATUS */
2844 /* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */
2845 
2846 /* Bit 0 : Status of data in register RXDATA */
2847 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */
2848 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */
2849 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register RXDATA */
2850 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (0x1UL) /*!< Data pending in register RXDATA */
2851 
2852 /* Register: CTRLAPPERI_MAILBOX_TXDATA */
2853 /* Description: Data sent from the CPU to the debugger. */
2854 
2855 /* Bits 31..0 : Data sent to debugger */
2856 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */
2857 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */
2858 
2859 /* Register: CTRLAPPERI_MAILBOX_TXSTATUS */
2860 /* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */
2861 
2862 /* Bit 0 : Status of data in register TXDATA */
2863 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */
2864 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */
2865 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register TXDATA */
2866 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (0x1UL) /*!< Data pending in register TXDATA */
2867 
2868 /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */
2869 /* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */
2870 
2871 /* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */
2872 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
2873 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
2874 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0x0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */
2875 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (0x1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */
2876 
2877 /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */
2878 /* Description: This register disables the ERASEPROTECT register and performs an  ERASEALL operation. */
2879 
2880 /* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */
2881 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
2882 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
2883 
2884 
2885 /* Peripheral: DPPIC */
2886 /* Description: Distributed programmable peripheral interconnect controller 0 */
2887 
2888 /* Register: DPPIC_TASKS_CHG_EN */
2889 /* Description: Description cluster: Enable channel group n */
2890 
2891 /* Bit 0 : Enable channel group n */
2892 #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
2893 #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
2894 #define DPPIC_TASKS_CHG_EN_EN_Trigger (0x1UL) /*!< Trigger task */
2895 
2896 /* Register: DPPIC_TASKS_CHG_DIS */
2897 /* Description: Description cluster: Disable channel group n */
2898 
2899 /* Bit 0 : Disable channel group n */
2900 #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
2901 #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
2902 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (0x1UL) /*!< Trigger task */
2903 
2904 /* Register: DPPIC_SUBSCRIBE_CHG_EN */
2905 /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */
2906 
2907 /* Bit 31 :   */
2908 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */
2909 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
2910 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0x0UL) /*!< Disable subscription */
2911 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (0x1UL) /*!< Enable subscription */
2912 
2913 /* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */
2914 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2915 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2916 
2917 /* Register: DPPIC_SUBSCRIBE_CHG_DIS */
2918 /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */
2919 
2920 /* Bit 31 :   */
2921 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */
2922 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */
2923 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0x0UL) /*!< Disable subscription */
2924 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (0x1UL) /*!< Enable subscription */
2925 
2926 /* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */
2927 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2928 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2929 
2930 /* Register: DPPIC_CHEN */
2931 /* Description: Channel enable register */
2932 
2933 /* Bit 15 : Enable or disable channel 15 */
2934 #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
2935 #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
2936 #define DPPIC_CHEN_CH15_Disabled (0x0UL) /*!< Disable channel */
2937 #define DPPIC_CHEN_CH15_Enabled (0x1UL) /*!< Enable channel */
2938 
2939 /* Bit 14 : Enable or disable channel 14 */
2940 #define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
2941 #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
2942 #define DPPIC_CHEN_CH14_Disabled (0x0UL) /*!< Disable channel */
2943 #define DPPIC_CHEN_CH14_Enabled (0x1UL) /*!< Enable channel */
2944 
2945 /* Bit 13 : Enable or disable channel 13 */
2946 #define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
2947 #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
2948 #define DPPIC_CHEN_CH13_Disabled (0x0UL) /*!< Disable channel */
2949 #define DPPIC_CHEN_CH13_Enabled (0x1UL) /*!< Enable channel */
2950 
2951 /* Bit 12 : Enable or disable channel 12 */
2952 #define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
2953 #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
2954 #define DPPIC_CHEN_CH12_Disabled (0x0UL) /*!< Disable channel */
2955 #define DPPIC_CHEN_CH12_Enabled (0x1UL) /*!< Enable channel */
2956 
2957 /* Bit 11 : Enable or disable channel 11 */
2958 #define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
2959 #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
2960 #define DPPIC_CHEN_CH11_Disabled (0x0UL) /*!< Disable channel */
2961 #define DPPIC_CHEN_CH11_Enabled (0x1UL) /*!< Enable channel */
2962 
2963 /* Bit 10 : Enable or disable channel 10 */
2964 #define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
2965 #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
2966 #define DPPIC_CHEN_CH10_Disabled (0x0UL) /*!< Disable channel */
2967 #define DPPIC_CHEN_CH10_Enabled (0x1UL) /*!< Enable channel */
2968 
2969 /* Bit 9 : Enable or disable channel 9 */
2970 #define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
2971 #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
2972 #define DPPIC_CHEN_CH9_Disabled (0x0UL) /*!< Disable channel */
2973 #define DPPIC_CHEN_CH9_Enabled (0x1UL) /*!< Enable channel */
2974 
2975 /* Bit 8 : Enable or disable channel 8 */
2976 #define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
2977 #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
2978 #define DPPIC_CHEN_CH8_Disabled (0x0UL) /*!< Disable channel */
2979 #define DPPIC_CHEN_CH8_Enabled (0x1UL) /*!< Enable channel */
2980 
2981 /* Bit 7 : Enable or disable channel 7 */
2982 #define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
2983 #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
2984 #define DPPIC_CHEN_CH7_Disabled (0x0UL) /*!< Disable channel */
2985 #define DPPIC_CHEN_CH7_Enabled (0x1UL) /*!< Enable channel */
2986 
2987 /* Bit 6 : Enable or disable channel 6 */
2988 #define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
2989 #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
2990 #define DPPIC_CHEN_CH6_Disabled (0x0UL) /*!< Disable channel */
2991 #define DPPIC_CHEN_CH6_Enabled (0x1UL) /*!< Enable channel */
2992 
2993 /* Bit 5 : Enable or disable channel 5 */
2994 #define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
2995 #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
2996 #define DPPIC_CHEN_CH5_Disabled (0x0UL) /*!< Disable channel */
2997 #define DPPIC_CHEN_CH5_Enabled (0x1UL) /*!< Enable channel */
2998 
2999 /* Bit 4 : Enable or disable channel 4 */
3000 #define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
3001 #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
3002 #define DPPIC_CHEN_CH4_Disabled (0x0UL) /*!< Disable channel */
3003 #define DPPIC_CHEN_CH4_Enabled (0x1UL) /*!< Enable channel */
3004 
3005 /* Bit 3 : Enable or disable channel 3 */
3006 #define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
3007 #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
3008 #define DPPIC_CHEN_CH3_Disabled (0x0UL) /*!< Disable channel */
3009 #define DPPIC_CHEN_CH3_Enabled (0x1UL) /*!< Enable channel */
3010 
3011 /* Bit 2 : Enable or disable channel 2 */
3012 #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
3013 #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
3014 #define DPPIC_CHEN_CH2_Disabled (0x0UL) /*!< Disable channel */
3015 #define DPPIC_CHEN_CH2_Enabled (0x1UL) /*!< Enable channel */
3016 
3017 /* Bit 1 : Enable or disable channel 1 */
3018 #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
3019 #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
3020 #define DPPIC_CHEN_CH1_Disabled (0x0UL) /*!< Disable channel */
3021 #define DPPIC_CHEN_CH1_Enabled (0x1UL) /*!< Enable channel */
3022 
3023 /* Bit 0 : Enable or disable channel 0 */
3024 #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
3025 #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
3026 #define DPPIC_CHEN_CH0_Disabled (0x0UL) /*!< Disable channel */
3027 #define DPPIC_CHEN_CH0_Enabled (0x1UL) /*!< Enable channel */
3028 
3029 /* Register: DPPIC_CHENSET */
3030 /* Description: Channel enable set register */
3031 
3032 /* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */
3033 #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
3034 #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
3035 #define DPPIC_CHENSET_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */
3036 #define DPPIC_CHENSET_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */
3037 #define DPPIC_CHENSET_CH15_Set (0x1UL) /*!< Write: Enable channel */
3038 
3039 /* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */
3040 #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
3041 #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
3042 #define DPPIC_CHENSET_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */
3043 #define DPPIC_CHENSET_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */
3044 #define DPPIC_CHENSET_CH14_Set (0x1UL) /*!< Write: Enable channel */
3045 
3046 /* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */
3047 #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
3048 #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
3049 #define DPPIC_CHENSET_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */
3050 #define DPPIC_CHENSET_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */
3051 #define DPPIC_CHENSET_CH13_Set (0x1UL) /*!< Write: Enable channel */
3052 
3053 /* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */
3054 #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
3055 #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
3056 #define DPPIC_CHENSET_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */
3057 #define DPPIC_CHENSET_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */
3058 #define DPPIC_CHENSET_CH12_Set (0x1UL) /*!< Write: Enable channel */
3059 
3060 /* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */
3061 #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
3062 #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
3063 #define DPPIC_CHENSET_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */
3064 #define DPPIC_CHENSET_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */
3065 #define DPPIC_CHENSET_CH11_Set (0x1UL) /*!< Write: Enable channel */
3066 
3067 /* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */
3068 #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
3069 #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
3070 #define DPPIC_CHENSET_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */
3071 #define DPPIC_CHENSET_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */
3072 #define DPPIC_CHENSET_CH10_Set (0x1UL) /*!< Write: Enable channel */
3073 
3074 /* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */
3075 #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
3076 #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
3077 #define DPPIC_CHENSET_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */
3078 #define DPPIC_CHENSET_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */
3079 #define DPPIC_CHENSET_CH9_Set (0x1UL) /*!< Write: Enable channel */
3080 
3081 /* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */
3082 #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
3083 #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
3084 #define DPPIC_CHENSET_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */
3085 #define DPPIC_CHENSET_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */
3086 #define DPPIC_CHENSET_CH8_Set (0x1UL) /*!< Write: Enable channel */
3087 
3088 /* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */
3089 #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
3090 #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
3091 #define DPPIC_CHENSET_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */
3092 #define DPPIC_CHENSET_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */
3093 #define DPPIC_CHENSET_CH7_Set (0x1UL) /*!< Write: Enable channel */
3094 
3095 /* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */
3096 #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
3097 #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
3098 #define DPPIC_CHENSET_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */
3099 #define DPPIC_CHENSET_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */
3100 #define DPPIC_CHENSET_CH6_Set (0x1UL) /*!< Write: Enable channel */
3101 
3102 /* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */
3103 #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
3104 #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
3105 #define DPPIC_CHENSET_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */
3106 #define DPPIC_CHENSET_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */
3107 #define DPPIC_CHENSET_CH5_Set (0x1UL) /*!< Write: Enable channel */
3108 
3109 /* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */
3110 #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
3111 #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
3112 #define DPPIC_CHENSET_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */
3113 #define DPPIC_CHENSET_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */
3114 #define DPPIC_CHENSET_CH4_Set (0x1UL) /*!< Write: Enable channel */
3115 
3116 /* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */
3117 #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
3118 #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
3119 #define DPPIC_CHENSET_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */
3120 #define DPPIC_CHENSET_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */
3121 #define DPPIC_CHENSET_CH3_Set (0x1UL) /*!< Write: Enable channel */
3122 
3123 /* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */
3124 #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
3125 #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
3126 #define DPPIC_CHENSET_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */
3127 #define DPPIC_CHENSET_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */
3128 #define DPPIC_CHENSET_CH2_Set (0x1UL) /*!< Write: Enable channel */
3129 
3130 /* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */
3131 #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
3132 #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
3133 #define DPPIC_CHENSET_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */
3134 #define DPPIC_CHENSET_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */
3135 #define DPPIC_CHENSET_CH1_Set (0x1UL) /*!< Write: Enable channel */
3136 
3137 /* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */
3138 #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
3139 #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
3140 #define DPPIC_CHENSET_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */
3141 #define DPPIC_CHENSET_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */
3142 #define DPPIC_CHENSET_CH0_Set (0x1UL) /*!< Write: Enable channel */
3143 
3144 /* Register: DPPIC_CHENCLR */
3145 /* Description: Channel enable clear register */
3146 
3147 /* Bit 15 : Channel 15 enable clear register.  Writing 0 has no effect. */
3148 #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
3149 #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
3150 #define DPPIC_CHENCLR_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */
3151 #define DPPIC_CHENCLR_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */
3152 #define DPPIC_CHENCLR_CH15_Clear (0x1UL) /*!< Write: Disable channel */
3153 
3154 /* Bit 14 : Channel 14 enable clear register.  Writing 0 has no effect. */
3155 #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
3156 #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
3157 #define DPPIC_CHENCLR_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */
3158 #define DPPIC_CHENCLR_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */
3159 #define DPPIC_CHENCLR_CH14_Clear (0x1UL) /*!< Write: Disable channel */
3160 
3161 /* Bit 13 : Channel 13 enable clear register.  Writing 0 has no effect. */
3162 #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
3163 #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
3164 #define DPPIC_CHENCLR_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */
3165 #define DPPIC_CHENCLR_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */
3166 #define DPPIC_CHENCLR_CH13_Clear (0x1UL) /*!< Write: Disable channel */
3167 
3168 /* Bit 12 : Channel 12 enable clear register.  Writing 0 has no effect. */
3169 #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
3170 #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
3171 #define DPPIC_CHENCLR_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */
3172 #define DPPIC_CHENCLR_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */
3173 #define DPPIC_CHENCLR_CH12_Clear (0x1UL) /*!< Write: Disable channel */
3174 
3175 /* Bit 11 : Channel 11 enable clear register.  Writing 0 has no effect. */
3176 #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
3177 #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
3178 #define DPPIC_CHENCLR_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */
3179 #define DPPIC_CHENCLR_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */
3180 #define DPPIC_CHENCLR_CH11_Clear (0x1UL) /*!< Write: Disable channel */
3181 
3182 /* Bit 10 : Channel 10 enable clear register.  Writing 0 has no effect. */
3183 #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
3184 #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
3185 #define DPPIC_CHENCLR_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */
3186 #define DPPIC_CHENCLR_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */
3187 #define DPPIC_CHENCLR_CH10_Clear (0x1UL) /*!< Write: Disable channel */
3188 
3189 /* Bit 9 : Channel 9 enable clear register.  Writing 0 has no effect. */
3190 #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
3191 #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
3192 #define DPPIC_CHENCLR_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */
3193 #define DPPIC_CHENCLR_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */
3194 #define DPPIC_CHENCLR_CH9_Clear (0x1UL) /*!< Write: Disable channel */
3195 
3196 /* Bit 8 : Channel 8 enable clear register.  Writing 0 has no effect. */
3197 #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
3198 #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
3199 #define DPPIC_CHENCLR_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */
3200 #define DPPIC_CHENCLR_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */
3201 #define DPPIC_CHENCLR_CH8_Clear (0x1UL) /*!< Write: Disable channel */
3202 
3203 /* Bit 7 : Channel 7 enable clear register.  Writing 0 has no effect. */
3204 #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
3205 #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
3206 #define DPPIC_CHENCLR_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */
3207 #define DPPIC_CHENCLR_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */
3208 #define DPPIC_CHENCLR_CH7_Clear (0x1UL) /*!< Write: Disable channel */
3209 
3210 /* Bit 6 : Channel 6 enable clear register.  Writing 0 has no effect. */
3211 #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
3212 #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
3213 #define DPPIC_CHENCLR_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */
3214 #define DPPIC_CHENCLR_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */
3215 #define DPPIC_CHENCLR_CH6_Clear (0x1UL) /*!< Write: Disable channel */
3216 
3217 /* Bit 5 : Channel 5 enable clear register.  Writing 0 has no effect. */
3218 #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
3219 #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
3220 #define DPPIC_CHENCLR_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */
3221 #define DPPIC_CHENCLR_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */
3222 #define DPPIC_CHENCLR_CH5_Clear (0x1UL) /*!< Write: Disable channel */
3223 
3224 /* Bit 4 : Channel 4 enable clear register.  Writing 0 has no effect. */
3225 #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
3226 #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
3227 #define DPPIC_CHENCLR_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */
3228 #define DPPIC_CHENCLR_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */
3229 #define DPPIC_CHENCLR_CH4_Clear (0x1UL) /*!< Write: Disable channel */
3230 
3231 /* Bit 3 : Channel 3 enable clear register.  Writing 0 has no effect. */
3232 #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
3233 #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
3234 #define DPPIC_CHENCLR_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */
3235 #define DPPIC_CHENCLR_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */
3236 #define DPPIC_CHENCLR_CH3_Clear (0x1UL) /*!< Write: Disable channel */
3237 
3238 /* Bit 2 : Channel 2 enable clear register.  Writing 0 has no effect. */
3239 #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
3240 #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
3241 #define DPPIC_CHENCLR_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */
3242 #define DPPIC_CHENCLR_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */
3243 #define DPPIC_CHENCLR_CH2_Clear (0x1UL) /*!< Write: Disable channel */
3244 
3245 /* Bit 1 : Channel 1 enable clear register.  Writing 0 has no effect. */
3246 #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
3247 #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
3248 #define DPPIC_CHENCLR_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */
3249 #define DPPIC_CHENCLR_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */
3250 #define DPPIC_CHENCLR_CH1_Clear (0x1UL) /*!< Write: Disable channel */
3251 
3252 /* Bit 0 : Channel 0 enable clear register.  Writing 0 has no effect. */
3253 #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
3254 #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
3255 #define DPPIC_CHENCLR_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */
3256 #define DPPIC_CHENCLR_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */
3257 #define DPPIC_CHENCLR_CH0_Clear (0x1UL) /*!< Write: Disable channel */
3258 
3259 /* Register: DPPIC_CHG */
3260 /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */
3261 
3262 /* Bit 15 : Include or exclude channel 15 */
3263 #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
3264 #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
3265 #define DPPIC_CHG_CH15_Excluded (0x0UL) /*!< Exclude */
3266 #define DPPIC_CHG_CH15_Included (0x1UL) /*!< Include */
3267 
3268 /* Bit 14 : Include or exclude channel 14 */
3269 #define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
3270 #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
3271 #define DPPIC_CHG_CH14_Excluded (0x0UL) /*!< Exclude */
3272 #define DPPIC_CHG_CH14_Included (0x1UL) /*!< Include */
3273 
3274 /* Bit 13 : Include or exclude channel 13 */
3275 #define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
3276 #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
3277 #define DPPIC_CHG_CH13_Excluded (0x0UL) /*!< Exclude */
3278 #define DPPIC_CHG_CH13_Included (0x1UL) /*!< Include */
3279 
3280 /* Bit 12 : Include or exclude channel 12 */
3281 #define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
3282 #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
3283 #define DPPIC_CHG_CH12_Excluded (0x0UL) /*!< Exclude */
3284 #define DPPIC_CHG_CH12_Included (0x1UL) /*!< Include */
3285 
3286 /* Bit 11 : Include or exclude channel 11 */
3287 #define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
3288 #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
3289 #define DPPIC_CHG_CH11_Excluded (0x0UL) /*!< Exclude */
3290 #define DPPIC_CHG_CH11_Included (0x1UL) /*!< Include */
3291 
3292 /* Bit 10 : Include or exclude channel 10 */
3293 #define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
3294 #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
3295 #define DPPIC_CHG_CH10_Excluded (0x0UL) /*!< Exclude */
3296 #define DPPIC_CHG_CH10_Included (0x1UL) /*!< Include */
3297 
3298 /* Bit 9 : Include or exclude channel 9 */
3299 #define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
3300 #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
3301 #define DPPIC_CHG_CH9_Excluded (0x0UL) /*!< Exclude */
3302 #define DPPIC_CHG_CH9_Included (0x1UL) /*!< Include */
3303 
3304 /* Bit 8 : Include or exclude channel 8 */
3305 #define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
3306 #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
3307 #define DPPIC_CHG_CH8_Excluded (0x0UL) /*!< Exclude */
3308 #define DPPIC_CHG_CH8_Included (0x1UL) /*!< Include */
3309 
3310 /* Bit 7 : Include or exclude channel 7 */
3311 #define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
3312 #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
3313 #define DPPIC_CHG_CH7_Excluded (0x0UL) /*!< Exclude */
3314 #define DPPIC_CHG_CH7_Included (0x1UL) /*!< Include */
3315 
3316 /* Bit 6 : Include or exclude channel 6 */
3317 #define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
3318 #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
3319 #define DPPIC_CHG_CH6_Excluded (0x0UL) /*!< Exclude */
3320 #define DPPIC_CHG_CH6_Included (0x1UL) /*!< Include */
3321 
3322 /* Bit 5 : Include or exclude channel 5 */
3323 #define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
3324 #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
3325 #define DPPIC_CHG_CH5_Excluded (0x0UL) /*!< Exclude */
3326 #define DPPIC_CHG_CH5_Included (0x1UL) /*!< Include */
3327 
3328 /* Bit 4 : Include or exclude channel 4 */
3329 #define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
3330 #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
3331 #define DPPIC_CHG_CH4_Excluded (0x0UL) /*!< Exclude */
3332 #define DPPIC_CHG_CH4_Included (0x1UL) /*!< Include */
3333 
3334 /* Bit 3 : Include or exclude channel 3 */
3335 #define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
3336 #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
3337 #define DPPIC_CHG_CH3_Excluded (0x0UL) /*!< Exclude */
3338 #define DPPIC_CHG_CH3_Included (0x1UL) /*!< Include */
3339 
3340 /* Bit 2 : Include or exclude channel 2 */
3341 #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
3342 #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
3343 #define DPPIC_CHG_CH2_Excluded (0x0UL) /*!< Exclude */
3344 #define DPPIC_CHG_CH2_Included (0x1UL) /*!< Include */
3345 
3346 /* Bit 1 : Include or exclude channel 1 */
3347 #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
3348 #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
3349 #define DPPIC_CHG_CH1_Excluded (0x0UL) /*!< Exclude */
3350 #define DPPIC_CHG_CH1_Included (0x1UL) /*!< Include */
3351 
3352 /* Bit 0 : Include or exclude channel 0 */
3353 #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
3354 #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
3355 #define DPPIC_CHG_CH0_Excluded (0x0UL) /*!< Exclude */
3356 #define DPPIC_CHG_CH0_Included (0x1UL) /*!< Include */
3357 
3358 
3359 /* Peripheral: EGU */
3360 /* Description: Event generator unit 0 */
3361 
3362 /* Register: EGU_TASKS_TRIGGER */
3363 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
3364 
3365 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
3366 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
3367 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
3368 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */
3369 
3370 /* Register: EGU_SUBSCRIBE_TRIGGER */
3371 /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */
3372 
3373 /* Bit 31 :   */
3374 #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */
3375 #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */
3376 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL) /*!< Disable subscription */
3377 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL) /*!< Enable subscription */
3378 
3379 /* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */
3380 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3381 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3382 
3383 /* Register: EGU_EVENTS_TRIGGERED */
3384 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
3385 
3386 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
3387 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
3388 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
3389 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated */
3390 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated */
3391 
3392 /* Register: EGU_PUBLISH_TRIGGERED */
3393 /* Description: Description collection: Publish configuration for event TRIGGERED[n] */
3394 
3395 /* Bit 31 :   */
3396 #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */
3397 #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */
3398 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0x0UL) /*!< Disable publishing */
3399 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (0x1UL) /*!< Enable publishing */
3400 
3401 /* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to */
3402 #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3403 #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3404 
3405 /* Register: EGU_INTEN */
3406 /* Description: Enable or disable interrupt */
3407 
3408 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
3409 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
3410 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
3411 #define EGU_INTEN_TRIGGERED15_Disabled (0x0UL) /*!< Disable */
3412 #define EGU_INTEN_TRIGGERED15_Enabled (0x1UL) /*!< Enable */
3413 
3414 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
3415 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
3416 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
3417 #define EGU_INTEN_TRIGGERED14_Disabled (0x0UL) /*!< Disable */
3418 #define EGU_INTEN_TRIGGERED14_Enabled (0x1UL) /*!< Enable */
3419 
3420 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
3421 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
3422 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
3423 #define EGU_INTEN_TRIGGERED13_Disabled (0x0UL) /*!< Disable */
3424 #define EGU_INTEN_TRIGGERED13_Enabled (0x1UL) /*!< Enable */
3425 
3426 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
3427 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
3428 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
3429 #define EGU_INTEN_TRIGGERED12_Disabled (0x0UL) /*!< Disable */
3430 #define EGU_INTEN_TRIGGERED12_Enabled (0x1UL) /*!< Enable */
3431 
3432 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
3433 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
3434 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
3435 #define EGU_INTEN_TRIGGERED11_Disabled (0x0UL) /*!< Disable */
3436 #define EGU_INTEN_TRIGGERED11_Enabled (0x1UL) /*!< Enable */
3437 
3438 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
3439 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
3440 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
3441 #define EGU_INTEN_TRIGGERED10_Disabled (0x0UL) /*!< Disable */
3442 #define EGU_INTEN_TRIGGERED10_Enabled (0x1UL) /*!< Enable */
3443 
3444 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
3445 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
3446 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
3447 #define EGU_INTEN_TRIGGERED9_Disabled (0x0UL) /*!< Disable */
3448 #define EGU_INTEN_TRIGGERED9_Enabled (0x1UL) /*!< Enable */
3449 
3450 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
3451 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
3452 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
3453 #define EGU_INTEN_TRIGGERED8_Disabled (0x0UL) /*!< Disable */
3454 #define EGU_INTEN_TRIGGERED8_Enabled (0x1UL) /*!< Enable */
3455 
3456 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
3457 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
3458 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
3459 #define EGU_INTEN_TRIGGERED7_Disabled (0x0UL) /*!< Disable */
3460 #define EGU_INTEN_TRIGGERED7_Enabled (0x1UL) /*!< Enable */
3461 
3462 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
3463 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
3464 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
3465 #define EGU_INTEN_TRIGGERED6_Disabled (0x0UL) /*!< Disable */
3466 #define EGU_INTEN_TRIGGERED6_Enabled (0x1UL) /*!< Enable */
3467 
3468 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
3469 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
3470 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
3471 #define EGU_INTEN_TRIGGERED5_Disabled (0x0UL) /*!< Disable */
3472 #define EGU_INTEN_TRIGGERED5_Enabled (0x1UL) /*!< Enable */
3473 
3474 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
3475 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
3476 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
3477 #define EGU_INTEN_TRIGGERED4_Disabled (0x0UL) /*!< Disable */
3478 #define EGU_INTEN_TRIGGERED4_Enabled (0x1UL) /*!< Enable */
3479 
3480 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
3481 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
3482 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
3483 #define EGU_INTEN_TRIGGERED3_Disabled (0x0UL) /*!< Disable */
3484 #define EGU_INTEN_TRIGGERED3_Enabled (0x1UL) /*!< Enable */
3485 
3486 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
3487 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
3488 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
3489 #define EGU_INTEN_TRIGGERED2_Disabled (0x0UL) /*!< Disable */
3490 #define EGU_INTEN_TRIGGERED2_Enabled (0x1UL) /*!< Enable */
3491 
3492 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
3493 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
3494 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
3495 #define EGU_INTEN_TRIGGERED1_Disabled (0x0UL) /*!< Disable */
3496 #define EGU_INTEN_TRIGGERED1_Enabled (0x1UL) /*!< Enable */
3497 
3498 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
3499 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
3500 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
3501 #define EGU_INTEN_TRIGGERED0_Disabled (0x0UL) /*!< Disable */
3502 #define EGU_INTEN_TRIGGERED0_Enabled (0x1UL) /*!< Enable */
3503 
3504 /* Register: EGU_INTENSET */
3505 /* Description: Enable interrupt */
3506 
3507 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
3508 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
3509 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
3510 #define EGU_INTENSET_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */
3511 #define EGU_INTENSET_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */
3512 #define EGU_INTENSET_TRIGGERED15_Set (0x1UL) /*!< Enable */
3513 
3514 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
3515 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
3516 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
3517 #define EGU_INTENSET_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */
3518 #define EGU_INTENSET_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */
3519 #define EGU_INTENSET_TRIGGERED14_Set (0x1UL) /*!< Enable */
3520 
3521 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
3522 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
3523 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
3524 #define EGU_INTENSET_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */
3525 #define EGU_INTENSET_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */
3526 #define EGU_INTENSET_TRIGGERED13_Set (0x1UL) /*!< Enable */
3527 
3528 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
3529 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
3530 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
3531 #define EGU_INTENSET_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */
3532 #define EGU_INTENSET_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */
3533 #define EGU_INTENSET_TRIGGERED12_Set (0x1UL) /*!< Enable */
3534 
3535 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
3536 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
3537 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
3538 #define EGU_INTENSET_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */
3539 #define EGU_INTENSET_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */
3540 #define EGU_INTENSET_TRIGGERED11_Set (0x1UL) /*!< Enable */
3541 
3542 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
3543 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
3544 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
3545 #define EGU_INTENSET_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */
3546 #define EGU_INTENSET_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */
3547 #define EGU_INTENSET_TRIGGERED10_Set (0x1UL) /*!< Enable */
3548 
3549 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
3550 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
3551 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
3552 #define EGU_INTENSET_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */
3553 #define EGU_INTENSET_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */
3554 #define EGU_INTENSET_TRIGGERED9_Set (0x1UL) /*!< Enable */
3555 
3556 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
3557 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
3558 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
3559 #define EGU_INTENSET_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */
3560 #define EGU_INTENSET_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */
3561 #define EGU_INTENSET_TRIGGERED8_Set (0x1UL) /*!< Enable */
3562 
3563 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
3564 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
3565 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
3566 #define EGU_INTENSET_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */
3567 #define EGU_INTENSET_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */
3568 #define EGU_INTENSET_TRIGGERED7_Set (0x1UL) /*!< Enable */
3569 
3570 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
3571 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
3572 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
3573 #define EGU_INTENSET_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */
3574 #define EGU_INTENSET_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */
3575 #define EGU_INTENSET_TRIGGERED6_Set (0x1UL) /*!< Enable */
3576 
3577 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
3578 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
3579 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
3580 #define EGU_INTENSET_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */
3581 #define EGU_INTENSET_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */
3582 #define EGU_INTENSET_TRIGGERED5_Set (0x1UL) /*!< Enable */
3583 
3584 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
3585 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
3586 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
3587 #define EGU_INTENSET_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */
3588 #define EGU_INTENSET_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */
3589 #define EGU_INTENSET_TRIGGERED4_Set (0x1UL) /*!< Enable */
3590 
3591 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
3592 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
3593 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
3594 #define EGU_INTENSET_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */
3595 #define EGU_INTENSET_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */
3596 #define EGU_INTENSET_TRIGGERED3_Set (0x1UL) /*!< Enable */
3597 
3598 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
3599 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
3600 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
3601 #define EGU_INTENSET_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */
3602 #define EGU_INTENSET_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */
3603 #define EGU_INTENSET_TRIGGERED2_Set (0x1UL) /*!< Enable */
3604 
3605 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
3606 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
3607 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
3608 #define EGU_INTENSET_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */
3609 #define EGU_INTENSET_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */
3610 #define EGU_INTENSET_TRIGGERED1_Set (0x1UL) /*!< Enable */
3611 
3612 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
3613 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
3614 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
3615 #define EGU_INTENSET_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */
3616 #define EGU_INTENSET_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */
3617 #define EGU_INTENSET_TRIGGERED0_Set (0x1UL) /*!< Enable */
3618 
3619 /* Register: EGU_INTENCLR */
3620 /* Description: Disable interrupt */
3621 
3622 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
3623 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
3624 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
3625 #define EGU_INTENCLR_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */
3626 #define EGU_INTENCLR_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */
3627 #define EGU_INTENCLR_TRIGGERED15_Clear (0x1UL) /*!< Disable */
3628 
3629 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
3630 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
3631 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
3632 #define EGU_INTENCLR_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */
3633 #define EGU_INTENCLR_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */
3634 #define EGU_INTENCLR_TRIGGERED14_Clear (0x1UL) /*!< Disable */
3635 
3636 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
3637 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
3638 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
3639 #define EGU_INTENCLR_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */
3640 #define EGU_INTENCLR_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */
3641 #define EGU_INTENCLR_TRIGGERED13_Clear (0x1UL) /*!< Disable */
3642 
3643 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
3644 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
3645 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
3646 #define EGU_INTENCLR_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */
3647 #define EGU_INTENCLR_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */
3648 #define EGU_INTENCLR_TRIGGERED12_Clear (0x1UL) /*!< Disable */
3649 
3650 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
3651 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
3652 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
3653 #define EGU_INTENCLR_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */
3654 #define EGU_INTENCLR_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */
3655 #define EGU_INTENCLR_TRIGGERED11_Clear (0x1UL) /*!< Disable */
3656 
3657 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
3658 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
3659 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
3660 #define EGU_INTENCLR_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */
3661 #define EGU_INTENCLR_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */
3662 #define EGU_INTENCLR_TRIGGERED10_Clear (0x1UL) /*!< Disable */
3663 
3664 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
3665 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
3666 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
3667 #define EGU_INTENCLR_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */
3668 #define EGU_INTENCLR_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */
3669 #define EGU_INTENCLR_TRIGGERED9_Clear (0x1UL) /*!< Disable */
3670 
3671 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
3672 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
3673 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
3674 #define EGU_INTENCLR_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */
3675 #define EGU_INTENCLR_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */
3676 #define EGU_INTENCLR_TRIGGERED8_Clear (0x1UL) /*!< Disable */
3677 
3678 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
3679 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
3680 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
3681 #define EGU_INTENCLR_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */
3682 #define EGU_INTENCLR_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */
3683 #define EGU_INTENCLR_TRIGGERED7_Clear (0x1UL) /*!< Disable */
3684 
3685 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
3686 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
3687 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
3688 #define EGU_INTENCLR_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */
3689 #define EGU_INTENCLR_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */
3690 #define EGU_INTENCLR_TRIGGERED6_Clear (0x1UL) /*!< Disable */
3691 
3692 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
3693 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
3694 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
3695 #define EGU_INTENCLR_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */
3696 #define EGU_INTENCLR_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */
3697 #define EGU_INTENCLR_TRIGGERED5_Clear (0x1UL) /*!< Disable */
3698 
3699 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
3700 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
3701 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
3702 #define EGU_INTENCLR_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */
3703 #define EGU_INTENCLR_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */
3704 #define EGU_INTENCLR_TRIGGERED4_Clear (0x1UL) /*!< Disable */
3705 
3706 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
3707 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
3708 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
3709 #define EGU_INTENCLR_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */
3710 #define EGU_INTENCLR_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */
3711 #define EGU_INTENCLR_TRIGGERED3_Clear (0x1UL) /*!< Disable */
3712 
3713 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
3714 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
3715 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
3716 #define EGU_INTENCLR_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */
3717 #define EGU_INTENCLR_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */
3718 #define EGU_INTENCLR_TRIGGERED2_Clear (0x1UL) /*!< Disable */
3719 
3720 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
3721 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
3722 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
3723 #define EGU_INTENCLR_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */
3724 #define EGU_INTENCLR_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */
3725 #define EGU_INTENCLR_TRIGGERED1_Clear (0x1UL) /*!< Disable */
3726 
3727 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
3728 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
3729 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
3730 #define EGU_INTENCLR_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */
3731 #define EGU_INTENCLR_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */
3732 #define EGU_INTENCLR_TRIGGERED0_Clear (0x1UL) /*!< Disable */
3733 
3734 
3735 /* Peripheral: ETB */
3736 /* Description: Embedded Trace Buffer */
3737 
3738 /* Register: ETB_RDP */
3739 /* Description: ETB RAM Depth Register */
3740 
3741 /* Bits 31..0 : Defines the depth, in words, of the trace RAM. */
3742 #define ETB_RDP_ETB_RAM_DEPTH_Pos (0UL) /*!< Position of ETB_RAM_DEPTH field. */
3743 #define ETB_RDP_ETB_RAM_DEPTH_Msk (0xFFFFFFFFUL << ETB_RDP_ETB_RAM_DEPTH_Pos) /*!< Bit mask of ETB_RAM_DEPTH field. */
3744 
3745 /* Register: ETB_STS */
3746 /* Description: ETB Status Register */
3747 
3748 /* Bit 3 : Formatter pipeline empty. All data stored to RAM. */
3749 #define ETB_STS_FTEMPTY_Pos (3UL) /*!< Position of FTEMPTY field. */
3750 #define ETB_STS_FTEMPTY_Msk (0x1UL << ETB_STS_FTEMPTY_Pos) /*!< Bit mask of FTEMPTY field. */
3751 
3752 /* Bit 2 : The acquisition complete flag indicates that capture has been completed when the formatter stops because of any of the methods defined in the Formatter and Flush Control Register, or TraceCaptEn = 0. This also results in FtStopped in the Formatter and Flush Status Register going HIGH. */
3753 #define ETB_STS_ACQCOMP_Pos (2UL) /*!< Position of ACQCOMP field. */
3754 #define ETB_STS_ACQCOMP_Msk (0x1UL << ETB_STS_ACQCOMP_Pos) /*!< Bit mask of ACQCOMP field. */
3755 
3756 /* Bit 1 : The Triggered bit is set when a trigger has been observed. This does not indicate that a trigger has been embedded in the trace data by the formatter, but is determined by the programming of the Formatter and Flush Control Register. */
3757 #define ETB_STS_TRIGGERED_Pos (1UL) /*!< Position of TRIGGERED field. */
3758 #define ETB_STS_TRIGGERED_Msk (0x1UL << ETB_STS_TRIGGERED_Pos) /*!< Bit mask of TRIGGERED field. */
3759 
3760 /* Bit 0 : RAM Full. The flag indicates when the RAM write pointer has wrapped around. */
3761 #define ETB_STS_FULL_Pos (0UL) /*!< Position of FULL field. */
3762 #define ETB_STS_FULL_Msk (0x1UL << ETB_STS_FULL_Pos) /*!< Bit mask of FULL field. */
3763 
3764 /* Register: ETB_RRD */
3765 /* Description: ETB RAM Read Data Register */
3766 
3767 /* Bits 31..0 : Data read from the ETB Trace RAM. */
3768 #define ETB_RRD_RAM_READ_DATA_Pos (0UL) /*!< Position of RAM_READ_DATA field. */
3769 #define ETB_RRD_RAM_READ_DATA_Msk (0xFFFFFFFFUL << ETB_RRD_RAM_READ_DATA_Pos) /*!< Bit mask of RAM_READ_DATA field. */
3770 
3771 /* Register: ETB_RRP */
3772 /* Description: ETB RAM Read Pointer Register */
3773 
3774 /* Bits 9..0 : Sets the read pointer used to read entries from the Trace RAM over the APB interface. */
3775 #define ETB_RRP_RAM_READ_POINTER_Pos (0UL) /*!< Position of RAM_READ_POINTER field. */
3776 #define ETB_RRP_RAM_READ_POINTER_Msk (0x3FFUL << ETB_RRP_RAM_READ_POINTER_Pos) /*!< Bit mask of RAM_READ_POINTER field. */
3777 
3778 /* Register: ETB_RWP */
3779 /* Description: ETB RAM Write Pointer Register */
3780 
3781 /* Bits 9..0 : Sets the write pointer used to write entries from the CoreSight bus into the Trace RAM. */
3782 #define ETB_RWP_RAM_WRITE_POINTER_Pos (0UL) /*!< Position of RAM_WRITE_POINTER field. */
3783 #define ETB_RWP_RAM_WRITE_POINTER_Msk (0x3FFUL << ETB_RWP_RAM_WRITE_POINTER_Pos) /*!< Bit mask of RAM_WRITE_POINTER field. */
3784 
3785 /* Register: ETB_TRG */
3786 /* Description: ETB Trigger Counter Register */
3787 
3788 /* Bits 9..0 : The counter is used as follows:Trace after - The counter is set to a large value, slightly less than the number of entries in the RAM. Trace before - The counter is set to a small value. Trace about - The counter is set to half the depth of the Trace RAM. This register must not be written to when trace capture is enabled (FtStopped=0, TraceCaptEn=1). If a write is attempted, the register is not updated. A read access is permitted with trace capture enabled. */
3789 #define ETB_TRG_TRIGGER_COUNTER_Pos (0UL) /*!< Position of TRIGGER_COUNTER field. */
3790 #define ETB_TRG_TRIGGER_COUNTER_Msk (0x3FFUL << ETB_TRG_TRIGGER_COUNTER_Pos) /*!< Bit mask of TRIGGER_COUNTER field. */
3791 
3792 /* Register: ETB_CTL */
3793 /* Description: ETB Control Register */
3794 
3795 /* Bit 0 : ETB Trace Capture Enable. This is the master enable bit forcing FtStopped HIGH when TraceCaptEn is LOW. When capture is disabled, any remaining data in the ATB formatter is stored to RAM. When all data is stored the formatter outputs FtStopped. Capture is fully disabled, or complete, when FtStopped goes HIGH. See ETB Formatter and Flush Status Register, FFSR, 0x300. */
3796 #define ETB_CTL_TRACECAPTEN_Pos (0UL) /*!< Position of TRACECAPTEN field. */
3797 #define ETB_CTL_TRACECAPTEN_Msk (0x1UL << ETB_CTL_TRACECAPTEN_Pos) /*!< Bit mask of TRACECAPTEN field. */
3798 
3799 /* Register: ETB_RWD */
3800 /* Description: ETB RAM Write Data Register */
3801 
3802 /* Bits 31..0 : Data written to the ETB Trace RAM. When trace capture is disabled, the contents of this register are placed into the ETB Trace RAM when this register is written to. Writing to this register increments the RAM Write Pointer Register. If trace capture is enabled, and this register is accessed, then a read from this register outputs 0xFFFFFFFF. Reads of this register never increment the RAM Write Pointer Register. A constant stream of 1s being output corresponds to a synchronization output from the ETB. If a write access is attempted, the data is not written into Trace RAM. */
3803 #define ETB_RWD_RAM_WRITE_DATA_Pos (0UL) /*!< Position of RAM_WRITE_DATA field. */
3804 #define ETB_RWD_RAM_WRITE_DATA_Msk (0xFFFFFFFFUL << ETB_RWD_RAM_WRITE_DATA_Pos) /*!< Bit mask of RAM_WRITE_DATA field. */
3805 
3806 /* Register: ETB_FFSR */
3807 /* Description: ETB Formatter and Flush Status Register */
3808 
3809 /* Bit 1 : Formatter stopped. The formatter has received a stop request signal and all trace data and post-amble has been output. Any more trace data on the ATB interface is ignored and atreadys goes HIGH. */
3810 #define ETB_FFSR_FTSTOPPED_Pos (1UL) /*!< Position of FTSTOPPED field. */
3811 #define ETB_FFSR_FTSTOPPED_Msk (0x1UL << ETB_FFSR_FTSTOPPED_Pos) /*!< Bit mask of FTSTOPPED field. */
3812 
3813 /* Bit 0 : Flush In Progress. This is an indication of the current state of afvalids. */
3814 #define ETB_FFSR_FLINPROG_Pos (0UL) /*!< Position of FLINPROG field. */
3815 #define ETB_FFSR_FLINPROG_Msk (0x1UL << ETB_FFSR_FLINPROG_Pos) /*!< Bit mask of FLINPROG field. */
3816 
3817 /* Register: ETB_FFCR */
3818 /* Description: ETB Formatter and Flush Control Register */
3819 
3820 /* Bit 13 : Stop the formatter after a Trigger Event is observed. Reset to disabled (zero). */
3821 #define ETB_FFCR_STOPTRIG_Pos (13UL) /*!< Position of STOPTRIG field. */
3822 #define ETB_FFCR_STOPTRIG_Msk (0x1UL << ETB_FFCR_STOPTRIG_Pos) /*!< Bit mask of STOPTRIG field. */
3823 
3824 /* Bit 12 : This forces the FIFO to drain off any part-completed packets. Setting this bit enables this function but this is clear on reset (disabled). */
3825 #define ETB_FFCR_STOPFL_Pos (12UL) /*!< Position of STOPFL field. */
3826 #define ETB_FFCR_STOPFL_Msk (0x1UL << ETB_FFCR_STOPFL_Pos) /*!< Bit mask of STOPFL field. */
3827 
3828 /* Bit 10 : Indicates a trigger on Flush completion (afreadys being returned). */
3829 #define ETB_FFCR_TRIGFL_Pos (10UL) /*!< Position of TRIGFL field. */
3830 #define ETB_FFCR_TRIGFL_Msk (0x1UL << ETB_FFCR_TRIGFL_Pos) /*!< Bit mask of TRIGFL field. */
3831 
3832 /* Bit 9 : Indicate a trigger on a Trigger Event. */
3833 #define ETB_FFCR_TRIGEVT_Pos (9UL) /*!< Position of TRIGEVT field. */
3834 #define ETB_FFCR_TRIGEVT_Msk (0x1UL << ETB_FFCR_TRIGEVT_Pos) /*!< Bit mask of TRIGEVT field. */
3835 
3836 /* Bit 8 : Indicate a trigger on trigin being asserted. */
3837 #define ETB_FFCR_TRIGIN_Pos (8UL) /*!< Position of TRIGIN field. */
3838 #define ETB_FFCR_TRIGIN_Msk (0x1UL << ETB_FFCR_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */
3839 
3840 /* Bit 6 : Setting this bit causes a flush to be generated. This is cleared when this flush has been serviced. This bit is clear on reset. */
3841 #define ETB_FFCR_FONMAN_Pos (6UL) /*!< Position of FONMAN field. */
3842 #define ETB_FFCR_FONMAN_Msk (0x1UL << ETB_FFCR_FONMAN_Pos) /*!< Bit mask of FONMAN field. */
3843 
3844 /* Bit 5 : Generate flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Event occurs. This bit is clear on reset. A Trigger Event is defined as when the Trigger counter reaches zero (where fitted) or, in the case of the trigger counter being zero (or not fitted), when trigin is HIGH. */
3845 #define ETB_FFCR_FONTRIG_Pos (5UL) /*!< Position of FONTRIG field. */
3846 #define ETB_FFCR_FONTRIG_Msk (0x1UL << ETB_FFCR_FONTRIG_Pos) /*!< Bit mask of FONTRIG field. */
3847 
3848 /* Bit 4 : Set this bit to enable use of the flushin connection. This is clear on reset. */
3849 #define ETB_FFCR_FONFLIN_Pos (4UL) /*!< Position of FONFLIN field. */
3850 #define ETB_FFCR_FONFLIN_Msk (0x1UL << ETB_FFCR_FONFLIN_Pos) /*!< Bit mask of FONFLIN field. */
3851 
3852 /* Bit 1 : Continuous mode in the ETB corresponds to normal mode with the embedding of triggers. Can only be changed when FtStopped is HIGH. This bit is clear on reset. */
3853 #define ETB_FFCR_ENFCONT_Pos (1UL) /*!< Position of ENFCONT field. */
3854 #define ETB_FFCR_ENFCONT_Msk (0x1UL << ETB_FFCR_ENFCONT_Pos) /*!< Bit mask of ENFCONT field. */
3855 
3856 /* Bit 0 : Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by TRACECTL, where fitted. Can only be changed when FtStopped is HIGH. This bit is clear on reset. */
3857 #define ETB_FFCR_ENFTC_Pos (0UL) /*!< Position of ENFTC field. */
3858 #define ETB_FFCR_ENFTC_Msk (0x1UL << ETB_FFCR_ENFTC_Pos) /*!< Bit mask of ENFTC field. */
3859 
3860 /* Register: ETB_ITMISCOP0 */
3861 /* Description: Integration Test Miscellaneous Output Register 0 */
3862 
3863 /* Bit 1 : Set the value of full output port. */
3864 #define ETB_ITMISCOP0_FULL_Pos (1UL) /*!< Position of FULL field. */
3865 #define ETB_ITMISCOP0_FULL_Msk (0x1UL << ETB_ITMISCOP0_FULL_Pos) /*!< Bit mask of FULL field. */
3866 
3867 /* Bit 0 : Set the value of acqcomp. */
3868 #define ETB_ITMISCOP0_ACQCOMP_Pos (0UL) /*!< Position of ACQCOMP field. */
3869 #define ETB_ITMISCOP0_ACQCOMP_Msk (0x1UL << ETB_ITMISCOP0_ACQCOMP_Pos) /*!< Bit mask of ACQCOMP field. */
3870 
3871 /* Register: ETB_ITTRFLINACK */
3872 /* Description: Integration Test Trigger In and Flush In Acknowledge Register */
3873 
3874 /* Bit 1 : Set the value of flushinack. */
3875 #define ETB_ITTRFLINACK_FLUSHINACK_Pos (1UL) /*!< Position of FLUSHINACK field. */
3876 #define ETB_ITTRFLINACK_FLUSHINACK_Msk (0x1UL << ETB_ITTRFLINACK_FLUSHINACK_Pos) /*!< Bit mask of FLUSHINACK field. */
3877 
3878 /* Bit 0 : Set the value of triginack. */
3879 #define ETB_ITTRFLINACK_TRIGINACK_Pos (0UL) /*!< Position of TRIGINACK field. */
3880 #define ETB_ITTRFLINACK_TRIGINACK_Msk (0x1UL << ETB_ITTRFLINACK_TRIGINACK_Pos) /*!< Bit mask of TRIGINACK field. */
3881 
3882 /* Register: ETB_ITTRFLIN */
3883 /* Description: Integration Test Trigger In and Flush In Register */
3884 
3885 /* Bit 1 : Read the value of flushin. */
3886 #define ETB_ITTRFLIN_FLUSHIN_Pos (1UL) /*!< Position of FLUSHIN field. */
3887 #define ETB_ITTRFLIN_FLUSHIN_Msk (0x1UL << ETB_ITTRFLIN_FLUSHIN_Pos) /*!< Bit mask of FLUSHIN field. */
3888 
3889 /* Bit 0 : Read the value of trigin. */
3890 #define ETB_ITTRFLIN_TRIGIN_Pos (0UL) /*!< Position of TRIGIN field. */
3891 #define ETB_ITTRFLIN_TRIGIN_Msk (0x1UL << ETB_ITTRFLIN_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */
3892 
3893 /* Register: ETB_ITATBDATA0 */
3894 /* Description: Integration Test ATB Data Register 0 */
3895 
3896 /* Bit 4 : Read the value of atdatas[31]. */
3897 #define ETB_ITATBDATA0_ATDATA_31_Pos (4UL) /*!< Position of ATDATA_31 field. */
3898 #define ETB_ITATBDATA0_ATDATA_31_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_31_Pos) /*!< Bit mask of ATDATA_31 field. */
3899 
3900 /* Bit 3 : Read the value of atdatas[23]. */
3901 #define ETB_ITATBDATA0_ATDATA_23_Pos (3UL) /*!< Position of ATDATA_23 field. */
3902 #define ETB_ITATBDATA0_ATDATA_23_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_23_Pos) /*!< Bit mask of ATDATA_23 field. */
3903 
3904 /* Bit 2 : Read the value of atdatas[15]. */
3905 #define ETB_ITATBDATA0_ATDATA_15_Pos (2UL) /*!< Position of ATDATA_15 field. */
3906 #define ETB_ITATBDATA0_ATDATA_15_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_15_Pos) /*!< Bit mask of ATDATA_15 field. */
3907 
3908 /* Bit 1 : Read the value of atdatas[7]. */
3909 #define ETB_ITATBDATA0_ATDATA_7_Pos (1UL) /*!< Position of ATDATA_7 field. */
3910 #define ETB_ITATBDATA0_ATDATA_7_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_7_Pos) /*!< Bit mask of ATDATA_7 field. */
3911 
3912 /* Bit 0 : Read the value of atdatas[0]. */
3913 #define ETB_ITATBDATA0_ATDATA_0_Pos (0UL) /*!< Position of ATDATA_0 field. */
3914 #define ETB_ITATBDATA0_ATDATA_0_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_0_Pos) /*!< Bit mask of ATDATA_0 field. */
3915 
3916 /* Register: ETB_ITATBCTR2 */
3917 /* Description: Integration Test ATB Control Register 2 */
3918 
3919 /* Bit 1 : Set the value of afvalids. */
3920 #define ETB_ITATBCTR2_AFVALIDS_Pos (1UL) /*!< Position of AFVALIDS field. */
3921 #define ETB_ITATBCTR2_AFVALIDS_Msk (0x1UL << ETB_ITATBCTR2_AFVALIDS_Pos) /*!< Bit mask of AFVALIDS field. */
3922 
3923 /* Bit 0 : Set the value of atreadys. */
3924 #define ETB_ITATBCTR2_ATREADYS_Pos (0UL) /*!< Position of ATREADYS field. */
3925 #define ETB_ITATBCTR2_ATREADYS_Msk (0x1UL << ETB_ITATBCTR2_ATREADYS_Pos) /*!< Bit mask of ATREADYS field. */
3926 
3927 /* Register: ETB_ITATBCTR1 */
3928 /* Description: Integration Test ATB Control Register 1 */
3929 
3930 /* Bits 6..0 : Read the value of atids. */
3931 #define ETB_ITATBCTR1_ATID_Pos (0UL) /*!< Position of ATID field. */
3932 #define ETB_ITATBCTR1_ATID_Msk (0x7FUL << ETB_ITATBCTR1_ATID_Pos) /*!< Bit mask of ATID field. */
3933 
3934 /* Register: ETB_ITATBCTR0 */
3935 /* Description: Integration Test ATB Control Register 0 */
3936 
3937 /* Bits 9..8 : Read the value of atbytess. */
3938 #define ETB_ITATBCTR0_ATBYTES_Pos (8UL) /*!< Position of ATBYTES field. */
3939 #define ETB_ITATBCTR0_ATBYTES_Msk (0x3UL << ETB_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field. */
3940 
3941 /* Bit 1 : Read the value of afreadys. */
3942 #define ETB_ITATBCTR0_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */
3943 #define ETB_ITATBCTR0_AFREADY_Msk (0x1UL << ETB_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field. */
3944 
3945 /* Bit 0 : Read the value of atvalids. */
3946 #define ETB_ITATBCTR0_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */
3947 #define ETB_ITATBCTR0_ATVALID_Msk (0x1UL << ETB_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field. */
3948 
3949 /* Register: ETB_ITCTRL */
3950 /* Description: Integration Mode Control Register */
3951 
3952 /* Bit 0 : Allows the component to switch from functional mode to integration mode or back. */
3953 #define ETB_ITCTRL_INTEGRATION_MODE_Pos (0UL) /*!< Position of INTEGRATION_MODE field. */
3954 #define ETB_ITCTRL_INTEGRATION_MODE_Msk (0x1UL << ETB_ITCTRL_INTEGRATION_MODE_Pos) /*!< Bit mask of INTEGRATION_MODE field. */
3955 
3956 /* Register: ETB_CLAIMSET */
3957 /* Description: Claim Tag Set Register */
3958 
3959 /* Bits 3..0 : This claim tag bit is implemented */
3960 #define ETB_CLAIMSET_CLAIMSET_Pos (0UL) /*!< Position of CLAIMSET field. */
3961 #define ETB_CLAIMSET_CLAIMSET_Msk (0xFUL << ETB_CLAIMSET_CLAIMSET_Pos) /*!< Bit mask of CLAIMSET field. */
3962 
3963 /* Register: ETB_CLAIMCLR */
3964 /* Description: Claim Tag Clear Register */
3965 
3966 /* Bits 3..0 : The value present reflects the current setting of the Claim Tag. */
3967 #define ETB_CLAIMCLR_CLAIMCLR_Pos (0UL) /*!< Position of CLAIMCLR field. */
3968 #define ETB_CLAIMCLR_CLAIMCLR_Msk (0xFUL << ETB_CLAIMCLR_CLAIMCLR_Pos) /*!< Bit mask of CLAIMCLR field. */
3969 
3970 /* Register: ETB_LAR */
3971 /* Description: Lock Access Register */
3972 
3973 /* Bits 31..0 : A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the affect of removing write access. */
3974 #define ETB_LAR_ACCESS_W_Pos (0UL) /*!< Position of ACCESS_W field. */
3975 #define ETB_LAR_ACCESS_W_Msk (0xFFFFFFFFUL << ETB_LAR_ACCESS_W_Pos) /*!< Bit mask of ACCESS_W field. */
3976 
3977 /* Register: ETB_LSR */
3978 /* Description: Lock Status Register */
3979 
3980 /* Bit 2 : Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit */
3981 #define ETB_LSR_LOCKTYPE_Pos (2UL) /*!< Position of LOCKTYPE field. */
3982 #define ETB_LSR_LOCKTYPE_Msk (0x1UL << ETB_LSR_LOCKTYPE_Pos) /*!< Bit mask of LOCKTYPE field. */
3983 
3984 /* Bit 1 : Returns the current status of the Lock. This bit reads as 0 when read from an external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers. */
3985 #define ETB_LSR_LOCKGRANT_Pos (1UL) /*!< Position of LOCKGRANT field. */
3986 #define ETB_LSR_LOCKGRANT_Msk (0x1UL << ETB_LSR_LOCKGRANT_Pos) /*!< Bit mask of LOCKGRANT field. */
3987 
3988 /* Bit 0 : Indicates that a lock control mechanism exists for this device. This bit reads as 0 when read from an external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers. */
3989 #define ETB_LSR_LOCKEXIST_Pos (0UL) /*!< Position of LOCKEXIST field. */
3990 #define ETB_LSR_LOCKEXIST_Msk (0x1UL << ETB_LSR_LOCKEXIST_Pos) /*!< Bit mask of LOCKEXIST field. */
3991 
3992 /* Register: ETB_AUTHSTATUS */
3993 /* Description: Authentication Status Register */
3994 
3995 /* Bits 7..6 : Indicates the security level for secure non-invasive debug */
3996 #define ETB_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */
3997 #define ETB_AUTHSTATUS_SNID_Msk (0x3UL << ETB_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */
3998 
3999 /* Bits 5..4 : Indicates the security level for secure invasive debug */
4000 #define ETB_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */
4001 #define ETB_AUTHSTATUS_SID_Msk (0x3UL << ETB_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */
4002 
4003 /* Bits 3..2 : Indicates the security level for non-secure non-invasive debug */
4004 #define ETB_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */
4005 #define ETB_AUTHSTATUS_NSNID_Msk (0x3UL << ETB_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */
4006 
4007 /* Bits 1..0 : Indicates the security level for non-secure invasive debug */
4008 #define ETB_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */
4009 #define ETB_AUTHSTATUS_NSID_Msk (0x3UL << ETB_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */
4010 
4011 /* Register: ETB_DEVID */
4012 /* Description: Device Configuration Register */
4013 
4014 /* Bit 5 : This bit returns 0 on reads indicating that the ETB RAM operates synchronously to atclk. */
4015 #define ETB_DEVID_RAMCLK_Pos (5UL) /*!< Position of RAMCLK field. */
4016 #define ETB_DEVID_RAMCLK_Msk (0x1UL << ETB_DEVID_RAMCLK_Pos) /*!< Bit mask of RAMCLK field. */
4017 
4018 /* Bits 4..0 : When non-zero this value indicates the type/number of ATB multiplexing present on the input to the ATB. */
4019 #define ETB_DEVID_EXTMUXNUM_Pos (0UL) /*!< Position of EXTMUXNUM field. */
4020 #define ETB_DEVID_EXTMUXNUM_Msk (0x1FUL << ETB_DEVID_EXTMUXNUM_Pos) /*!< Bit mask of EXTMUXNUM field. */
4021 
4022 /* Register: ETB_DEVTYPE */
4023 /* Description: Device Type Identifier Register */
4024 
4025 /* Bits 7..4 : Sub-classification within the major category */
4026 #define ETB_DEVTYPE_SUB_TYPE_Pos (4UL) /*!< Position of SUB_TYPE field. */
4027 #define ETB_DEVTYPE_SUB_TYPE_Msk (0xFUL << ETB_DEVTYPE_SUB_TYPE_Pos) /*!< Bit mask of SUB_TYPE field. */
4028 
4029 /* Bits 3..0 : Major classification grouping for this debug/trace component */
4030 #define ETB_DEVTYPE_MAJOR_TYPE_Pos (0UL) /*!< Position of MAJOR_TYPE field. */
4031 #define ETB_DEVTYPE_MAJOR_TYPE_Msk (0xFUL << ETB_DEVTYPE_MAJOR_TYPE_Pos) /*!< Bit mask of MAJOR_TYPE field. */
4032 
4033 /* Register: ETB_PERIPHID4 */
4034 /* Description: Peripheral ID4 Register */
4035 
4036 /* Bits 7..4 : This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. */
4037 #define ETB_PERIPHID4_SIZE_Pos (4UL) /*!< Position of SIZE field. */
4038 #define ETB_PERIPHID4_SIZE_Msk (0xFUL << ETB_PERIPHID4_SIZE_Pos) /*!< Bit mask of SIZE field. */
4039 
4040 /* Bits 3..0 : JEDEC continuation code indicating the designer of the component (along with the identity code) */
4041 #define ETB_PERIPHID4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */
4042 #define ETB_PERIPHID4_DES_2_Msk (0xFUL << ETB_PERIPHID4_DES_2_Pos) /*!< Bit mask of DES_2 field. */
4043 
4044 /* Register: ETB_PERIPHID0 */
4045 /* Description: Peripheral ID0 Register */
4046 
4047 /* Bits 7..0 : Bits [7:0] of the component's part number. This is selected by the designer of the component. */
4048 #define ETB_PERIPHID0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */
4049 #define ETB_PERIPHID0_PART_0_Msk (0xFFUL << ETB_PERIPHID0_PART_0_Pos) /*!< Bit mask of PART_0 field. */
4050 
4051 /* Register: ETB_PERIPHID1 */
4052 /* Description: Peripheral ID1 Register */
4053 
4054 /* Bits 7..4 : Bits 3:0 of the JEDEC identity code indicating the designer of the component (along with the continuation code) */
4055 #define ETB_PERIPHID1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */
4056 #define ETB_PERIPHID1_DES_0_Msk (0xFUL << ETB_PERIPHID1_DES_0_Pos) /*!< Bit mask of DES_0 field. */
4057 
4058 /* Bits 3..0 : Bits [11:8] of the component's part number. This is selected by the designer of the component. */
4059 #define ETB_PERIPHID1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */
4060 #define ETB_PERIPHID1_PART_1_Msk (0xFUL << ETB_PERIPHID1_PART_1_Pos) /*!< Bit mask of PART_1 field. */
4061 
4062 /* Register: ETB_PERIPHID2 */
4063 /* Description: Peripheral ID2 Register */
4064 
4065 /* Bits 7..4 : The Revision field is an incremental value starting at 0x0 for the first design of this component. This only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the exact major/minor revision. */
4066 #define ETB_PERIPHID2_REVISION_Pos (4UL) /*!< Position of REVISION field. */
4067 #define ETB_PERIPHID2_REVISION_Msk (0xFUL << ETB_PERIPHID2_REVISION_Pos) /*!< Bit mask of REVISION field. */
4068 
4069 /* Bit 3 : Always set. Indicates that a JEDEC assigned value is used */
4070 #define ETB_PERIPHID2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */
4071 #define ETB_PERIPHID2_JEDEC_Msk (0x1UL << ETB_PERIPHID2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */
4072 
4073 /* Bits 2..0 : Bits 6:4 of the JEDEC identity code indicating the designer of the component (along with the continuation code) */
4074 #define ETB_PERIPHID2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */
4075 #define ETB_PERIPHID2_DES_1_Msk (0x7UL << ETB_PERIPHID2_DES_1_Pos) /*!< Bit mask of DES_1 field. */
4076 
4077 /* Register: ETB_PERIPHID3 */
4078 /* Description: Peripheral ID3 Register */
4079 
4080 /* Bits 7..4 : This field indicates minor errata fixes specific to this design, for example metal fixes after implementation. In most cases this field is zero. It is recommended that component designers ensure this field can be changed by a metal fix if required, for example by driving it from registers that reset to zero. */
4081 #define ETB_PERIPHID3_REVAND_Pos (4UL) /*!< Position of REVAND field. */
4082 #define ETB_PERIPHID3_REVAND_Msk (0xFUL << ETB_PERIPHID3_REVAND_Pos) /*!< Bit mask of REVAND field. */
4083 
4084 /* Bits 3..0 : Where the component is reusable IP, this value indicates if the customer has modified the behavior of the component. In most cases this field is zero. */
4085 #define ETB_PERIPHID3_CMOD_Pos (0UL) /*!< Position of CMOD field. */
4086 #define ETB_PERIPHID3_CMOD_Msk (0xFUL << ETB_PERIPHID3_CMOD_Pos) /*!< Bit mask of CMOD field. */
4087 
4088 /* Register: ETB_COMPID0 */
4089 /* Description: Component ID0 Register */
4090 
4091 /* Bits 7..0 : Contains bits [7:0] of the component identification */
4092 #define ETB_COMPID0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */
4093 #define ETB_COMPID0_PRMBL_0_Msk (0xFFUL << ETB_COMPID0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */
4094 
4095 /* Register: ETB_COMPID1 */
4096 /* Description: Component ID1 Register */
4097 
4098 /* Bits 7..4 : Class of the component. E. g. ROM table, CoreSight component etc. Constitutes bits [15:12] of the component identification. */
4099 #define ETB_COMPID1_CLASS_Pos (4UL) /*!< Position of CLASS field. */
4100 #define ETB_COMPID1_CLASS_Msk (0xFUL << ETB_COMPID1_CLASS_Pos) /*!< Bit mask of CLASS field. */
4101 
4102 /* Bits 3..0 : Contains bits [11:8] of the component identification */
4103 #define ETB_COMPID1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */
4104 #define ETB_COMPID1_PRMBL_1_Msk (0xFUL << ETB_COMPID1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */
4105 
4106 /* Register: ETB_COMPID2 */
4107 /* Description: Component ID2 Register */
4108 
4109 /* Bits 7..0 : Contains bits [23:16] of the component identification */
4110 #define ETB_COMPID2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */
4111 #define ETB_COMPID2_PRMBL_2_Msk (0xFFUL << ETB_COMPID2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */
4112 
4113 /* Register: ETB_COMPID3 */
4114 /* Description: Component ID3 Register */
4115 
4116 /* Bits 7..0 : Contains bits [31:24] of the component identification */
4117 #define ETB_COMPID3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */
4118 #define ETB_COMPID3_PRMBL_3_Msk (0xFFUL << ETB_COMPID3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */
4119 
4120 
4121 /* Peripheral: ETM */
4122 /* Description: Embedded Trace Macrocell */
4123 
4124 /* Register: ETM_TRCPRGCTLR */
4125 /* Description: Enables the trace unit. */
4126 
4127 /* Bit 0 : Trace unit enable bit */
4128 #define ETM_TRCPRGCTLR_EN_Pos (0UL) /*!< Position of EN field. */
4129 #define ETM_TRCPRGCTLR_EN_Msk (0x1UL << ETM_TRCPRGCTLR_EN_Pos) /*!< Bit mask of EN field. */
4130 #define ETM_TRCPRGCTLR_EN_Disabled (0x0UL) /*!< The trace unit is disabled. All trace resources are inactive and no trace is generated. */
4131 #define ETM_TRCPRGCTLR_EN_Enabled (0x1UL) /*!< The trace unit is enabled. */
4132 
4133 /* Register: ETM_TRCPROCSELR */
4134 /* Description: Controls which PE to trace. Might ignore writes when the trace unit is enabled or not idle. Before writing to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE. Implemented if TRCIDR3.NUMPROC is greater than zero. */
4135 
4136 /* Bits 4..0 : PE select bits that select the PE to trace. */
4137 #define ETM_TRCPROCSELR_PROCSEL_Pos (0UL) /*!< Position of PROCSEL field. */
4138 #define ETM_TRCPROCSELR_PROCSEL_Msk (0x1FUL << ETM_TRCPROCSELR_PROCSEL_Pos) /*!< Bit mask of PROCSEL field. */
4139 
4140 /* Register: ETM_TRCSTATR */
4141 /* Description: Idle status bit */
4142 
4143 /* Bit 1 : Programmers' model stable bit */
4144 #define ETM_TRCSTATR_PMSTABLE_Pos (1UL) /*!< Position of PMSTABLE field. */
4145 #define ETM_TRCSTATR_PMSTABLE_Msk (0x1UL << ETM_TRCSTATR_PMSTABLE_Pos) /*!< Bit mask of PMSTABLE field. */
4146 #define ETM_TRCSTATR_PMSTABLE_NotStable (0x0UL) /*!< The programmers' model is not stable. */
4147 #define ETM_TRCSTATR_PMSTABLE_Stable (0x1UL) /*!< The programmers' model is stable. */
4148 
4149 /* Bit 0 : Trace unit enable bit */
4150 #define ETM_TRCSTATR_IDLE_Pos (0UL) /*!< Position of IDLE field. */
4151 #define ETM_TRCSTATR_IDLE_Msk (0x1UL << ETM_TRCSTATR_IDLE_Pos) /*!< Bit mask of IDLE field. */
4152 #define ETM_TRCSTATR_IDLE_NotIdle (0x0UL) /*!< The trace unit is not idle. */
4153 #define ETM_TRCSTATR_IDLE_Idle (0x1UL) /*!< The trace unit is idle. */
4154 
4155 /* Register: ETM_TRCCONFIGR */
4156 /* Description: Controls the tracing options This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. */
4157 
4158 /* Bit 17 : Data value tracing bit. */
4159 #define ETM_TRCCONFIGR_DV_Pos (17UL) /*!< Position of DV field. */
4160 #define ETM_TRCCONFIGR_DV_Msk (0x1UL << ETM_TRCCONFIGR_DV_Pos) /*!< Bit mask of DV field. */
4161 #define ETM_TRCCONFIGR_DV_Disabled (0x0UL) /*!< Data value tracing is disabled. */
4162 #define ETM_TRCCONFIGR_DV_Enabled (0x1UL) /*!< Data value tracing is enabled. */
4163 
4164 /* Bit 16 : Data address tracing bit. */
4165 #define ETM_TRCCONFIGR_DA_Pos (16UL) /*!< Position of DA field. */
4166 #define ETM_TRCCONFIGR_DA_Msk (0x1UL << ETM_TRCCONFIGR_DA_Pos) /*!< Bit mask of DA field. */
4167 #define ETM_TRCCONFIGR_DA_Disabled (0x0UL) /*!< Data address tracing is disabled. */
4168 #define ETM_TRCCONFIGR_DA_Enabled (0x1UL) /*!< Data address tracing is enabled. */
4169 
4170 /* Bit 15 : Control bit to select the Virtual context identifier value used by the trace unit, both for trace generation and in the Virtual context identifier comparators. */
4171 #define ETM_TRCCONFIGR_VMIDOPT_Pos (15UL) /*!< Position of VMIDOPT field. */
4172 #define ETM_TRCCONFIGR_VMIDOPT_Msk (0x1UL << ETM_TRCCONFIGR_VMIDOPT_Pos) /*!< Bit mask of VMIDOPT field. */
4173 #define ETM_TRCCONFIGR_VMIDOPT_VTTBR_EL2 (0x0UL) /*!< VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context
4174 identifier larger than the VTTBR_EL2.VMID, the upper unused bits are always
4175 zero. If the trace unit supports a Virtual context identifier larger than 8 bits and
4176 if the VTCR_EL2.VS bit forces use of an 8-bit Virtual context identifier, bits
4177 [15:8] of the trace unit Virtual context identifier are always zero. */
4178 #define ETM_TRCCONFIGR_VMIDOPT_CONTEXTIDR_EL2 (0x1UL) /*!< CONTEXTIDR_EL2 is used. */
4179 
4180 /* Bits 14..13 : Q element enable field. */
4181 #define ETM_TRCCONFIGR_QE_Pos (13UL) /*!< Position of QE field. */
4182 #define ETM_TRCCONFIGR_QE_Msk (0x3UL << ETM_TRCCONFIGR_QE_Pos) /*!< Bit mask of QE field. */
4183 #define ETM_TRCCONFIGR_QE_Disabled (0x0UL) /*!< Q elements are disabled. */
4184 #define ETM_TRCCONFIGR_QE_OnlyWithoutInstCounts (0x1UL) /*!< Q elements with instruction counts are enabled. Q elements without instruction counts are disabled. */
4185 #define ETM_TRCCONFIGR_QE_Enabled (0x3UL) /*!< Q elements with and without instruction counts are enabled. */
4186 
4187 /* Bit 12 : Return stack enable bit. */
4188 #define ETM_TRCCONFIGR_RS_Pos (12UL) /*!< Position of RS field. */
4189 #define ETM_TRCCONFIGR_RS_Msk (0x1UL << ETM_TRCCONFIGR_RS_Pos) /*!< Bit mask of RS field. */
4190 #define ETM_TRCCONFIGR_RS_Disabled (0x0UL) /*!< Return stack is disabled. */
4191 #define ETM_TRCCONFIGR_RS_Enabled (0x1UL) /*!< Return stack is enabled. */
4192 
4193 /* Bit 11 : Global timestamp tracing bit. */
4194 #define ETM_TRCCONFIGR_TS_Pos (11UL) /*!< Position of TS field. */
4195 #define ETM_TRCCONFIGR_TS_Msk (0x1UL << ETM_TRCCONFIGR_TS_Pos) /*!< Bit mask of TS field. */
4196 #define ETM_TRCCONFIGR_TS_Disabled (0x0UL) /*!< Global timestamp tracing is disabled. */
4197 #define ETM_TRCCONFIGR_TS_Enabled (0x1UL) /*!< Global timestamp tracing is enabled. */
4198 
4199 /* Bits 10..8 : Conditional instruction tracing bit. */
4200 #define ETM_TRCCONFIGR_COND_Pos (8UL) /*!< Position of COND field. */
4201 #define ETM_TRCCONFIGR_COND_Msk (0x7UL << ETM_TRCCONFIGR_COND_Pos) /*!< Bit mask of COND field. */
4202 #define ETM_TRCCONFIGR_COND_Disabled (0x0UL) /*!< Conditional instruction tracing is disabled. */
4203 #define ETM_TRCCONFIGR_COND_LoadOnly (0x1UL) /*!< Conditional load instructions are traced. */
4204 #define ETM_TRCCONFIGR_COND_StoreOnly (0x2UL) /*!< Conditional store instructions are traced. */
4205 #define ETM_TRCCONFIGR_COND_LoadAndStore (0x3UL) /*!< Conditional load and store instructions are traced. */
4206 #define ETM_TRCCONFIGR_COND_All (0x7UL) /*!< All conditional instructions are traced. */
4207 
4208 /* Bit 7 : Virtual context identifier tracing bit. */
4209 #define ETM_TRCCONFIGR_VMID_Pos (7UL) /*!< Position of VMID field. */
4210 #define ETM_TRCCONFIGR_VMID_Msk (0x1UL << ETM_TRCCONFIGR_VMID_Pos) /*!< Bit mask of VMID field. */
4211 #define ETM_TRCCONFIGR_VMID_Disabled (0x0UL) /*!< Virtual context identifier tracing is disabled. */
4212 #define ETM_TRCCONFIGR_VMID_Enabled (0x1UL) /*!< Virtual context identifier tracing is enabled. */
4213 
4214 /* Bit 6 : Context ID tracing bit. */
4215 #define ETM_TRCCONFIGR_CID_Pos (6UL) /*!< Position of CID field. */
4216 #define ETM_TRCCONFIGR_CID_Msk (0x1UL << ETM_TRCCONFIGR_CID_Pos) /*!< Bit mask of CID field. */
4217 #define ETM_TRCCONFIGR_CID_Disabled (0x0UL) /*!< Context ID tracing is disabled. */
4218 #define ETM_TRCCONFIGR_CID_Enabled (0x1UL) /*!< Context ID tracing is enabled. */
4219 
4220 /* Bit 4 : Cycle counting instruction trace bit. */
4221 #define ETM_TRCCONFIGR_CCI_Pos (4UL) /*!< Position of CCI field. */
4222 #define ETM_TRCCONFIGR_CCI_Msk (0x1UL << ETM_TRCCONFIGR_CCI_Pos) /*!< Bit mask of CCI field. */
4223 #define ETM_TRCCONFIGR_CCI_Disabled (0x0UL) /*!< Cycle counting in the instruction trace is disabled. */
4224 #define ETM_TRCCONFIGR_CCI_Enabled (0x1UL) /*!< Cycle counting in the instruction trace is enabled. */
4225 
4226 /* Bit 3 : Branch broadcast mode bit. */
4227 #define ETM_TRCCONFIGR_BB_Pos (3UL) /*!< Position of BB field. */
4228 #define ETM_TRCCONFIGR_BB_Msk (0x1UL << ETM_TRCCONFIGR_BB_Pos) /*!< Bit mask of BB field. */
4229 #define ETM_TRCCONFIGR_BB_Disabled (0x0UL) /*!< Branch broadcast mode is disabled. */
4230 #define ETM_TRCCONFIGR_BB_Enabled (0x1UL) /*!< Branch broadcast mode is enabled. */
4231 
4232 /* Bit 2 : Instruction P0 field. This field controls whether store instructions are traced as P0 instructions. */
4233 #define ETM_TRCCONFIGR_STOREASP0INST_Pos (2UL) /*!< Position of STOREASP0INST field. */
4234 #define ETM_TRCCONFIGR_STOREASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_STOREASP0INST_Pos) /*!< Bit mask of STOREASP0INST field. */
4235 #define ETM_TRCCONFIGR_STOREASP0INST_No (0x0UL) /*!< Do not trace store instructions as P0 instructions. */
4236 #define ETM_TRCCONFIGR_STOREASP0INST_Yes (0x1UL) /*!< Trace store instructions as P0 instructions. */
4237 
4238 /* Bit 1 : Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions. */
4239 #define ETM_TRCCONFIGR_LOADASP0INST_Pos (1UL) /*!< Position of LOADASP0INST field. */
4240 #define ETM_TRCCONFIGR_LOADASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_LOADASP0INST_Pos) /*!< Bit mask of LOADASP0INST field. */
4241 #define ETM_TRCCONFIGR_LOADASP0INST_No (0x0UL) /*!< Do not trace load instructions as P0 instructions. */
4242 #define ETM_TRCCONFIGR_LOADASP0INST_Yes (0x1UL) /*!< Trace load instructions as P0 instructions. */
4243 
4244 /* Register: ETM_TRCEVENTCTL0R */
4245 /* Description: Controls the tracing of arbitrary events. If the selected event occurs a trace element is generated in the trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN. */
4246 
4247 /* Bits 7..0 : Select which event should generate trace elements. */
4248 #define ETM_TRCEVENTCTL0R_EVENT_Pos (0UL) /*!< Position of EVENT field. */
4249 #define ETM_TRCEVENTCTL0R_EVENT_Msk (0xFFUL << ETM_TRCEVENTCTL0R_EVENT_Pos) /*!< Bit mask of EVENT field. */
4250 
4251 /* Register: ETM_TRCEVENTCTL1R */
4252 /* Description: Controls the behavior of the events that TRCEVENTCTL0R selects. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. */
4253 
4254 /* Bit 12 : Low-power state behavior override bit. Controls how a trace unit behaves in low-power state. */
4255 #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos (12UL) /*!< Position of LPOVERRIDE field. */
4256 #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Msk (0x1UL << ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos) /*!< Bit mask of LPOVERRIDE field. */
4257 #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Disabled (0x0UL) /*!< Trace unit low-power state behavior is not affected. That is, the trace unit is enabled to enter low-power state. */
4258 #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Enabled (0x1UL) /*!< Trace unit low-power state behavior is overridden. That is, entry to a low-power state does not affect the trace unit resources or trace generation. */
4259 
4260 /* Bit 11 : AMBA Trace Bus (ATB) trigger enable bit. */
4261 #define ETM_TRCEVENTCTL1R_ATB_Pos (11UL) /*!< Position of ATB field. */
4262 #define ETM_TRCEVENTCTL1R_ATB_Msk (0x1UL << ETM_TRCEVENTCTL1R_ATB_Pos) /*!< Bit mask of ATB field. */
4263 #define ETM_TRCEVENTCTL1R_ATB_Disabled (0x0UL) /*!< ATB trigger is disabled. */
4264 #define ETM_TRCEVENTCTL1R_ATB_Enabled (0x1UL) /*!< ATB trigger is enabled. If a CoreSight ATB interface is implemented then when event 0 occurs the trace unit generates an ATB event. */
4265 
4266 /* Bit 4 : Data event enable bit. */
4267 #define ETM_TRCEVENTCTL1R_DATAEN_Pos (4UL) /*!< Position of DATAEN field. */
4268 #define ETM_TRCEVENTCTL1R_DATAEN_Msk (0x1UL << ETM_TRCEVENTCTL1R_DATAEN_Pos) /*!< Bit mask of DATAEN field. */
4269 #define ETM_TRCEVENTCTL1R_DATAEN_Disabled (0x0UL) /*!< The trace unit does not generate an Event element if event 0 occurs. */
4270 #define ETM_TRCEVENTCTL1R_DATAEN_Enabled (0x1UL) /*!< The trace unit generates an Event element in the data trace stream if event 0 occurs. */
4271 
4272 /* Bit 3 : Instruction event enable field. */
4273 #define ETM_TRCEVENTCTL1R_INSTEN_3_Pos (3UL) /*!< Position of INSTEN_3 field. */
4274 #define ETM_TRCEVENTCTL1R_INSTEN_3_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN_3_Pos) /*!< Bit mask of INSTEN_3 field. */
4275 #define ETM_TRCEVENTCTL1R_INSTEN_3_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */
4276 #define ETM_TRCEVENTCTL1R_INSTEN_3_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 3, in the instruction trace stream. */
4277 
4278 /* Bit 2 : Instruction event enable field. */
4279 #define ETM_TRCEVENTCTL1R_INSTEN_2_Pos (2UL) /*!< Position of INSTEN_2 field. */
4280 #define ETM_TRCEVENTCTL1R_INSTEN_2_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN_2_Pos) /*!< Bit mask of INSTEN_2 field. */
4281 #define ETM_TRCEVENTCTL1R_INSTEN_2_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */
4282 #define ETM_TRCEVENTCTL1R_INSTEN_2_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 2, in the instruction trace stream. */
4283 
4284 /* Bit 1 : Instruction event enable field. */
4285 #define ETM_TRCEVENTCTL1R_INSTEN_1_Pos (1UL) /*!< Position of INSTEN_1 field. */
4286 #define ETM_TRCEVENTCTL1R_INSTEN_1_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN_1_Pos) /*!< Bit mask of INSTEN_1 field. */
4287 #define ETM_TRCEVENTCTL1R_INSTEN_1_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */
4288 #define ETM_TRCEVENTCTL1R_INSTEN_1_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 1, in the instruction trace stream. */
4289 
4290 /* Bit 0 : Instruction event enable field. */
4291 #define ETM_TRCEVENTCTL1R_INSTEN_0_Pos (0UL) /*!< Position of INSTEN_0 field. */
4292 #define ETM_TRCEVENTCTL1R_INSTEN_0_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN_0_Pos) /*!< Bit mask of INSTEN_0 field. */
4293 #define ETM_TRCEVENTCTL1R_INSTEN_0_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */
4294 #define ETM_TRCEVENTCTL1R_INSTEN_0_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 0, in the instruction trace stream. */
4295 
4296 /* Register: ETM_TRCSTALLCTLR */
4297 /* Description: Enables trace unit functionality that prevents trace unit buffer overflows. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCIDR3.STALLCTL == 1. */
4298 
4299 /* Bit 13 : Trace overflow prevention bit. */
4300 #define ETM_TRCSTALLCTLR_NOOVERFLOW_Pos (13UL) /*!< Position of NOOVERFLOW field. */
4301 #define ETM_TRCSTALLCTLR_NOOVERFLOW_Msk (0x1UL << ETM_TRCSTALLCTLR_NOOVERFLOW_Pos) /*!< Bit mask of NOOVERFLOW field. */
4302 #define ETM_TRCSTALLCTLR_NOOVERFLOW_Disabled (0x0UL) /*!< Trace overflow prevention is disabled. */
4303 #define ETM_TRCSTALLCTLR_NOOVERFLOW_Enabled (0x1UL) /*!< Trace overflow prevention is enabled. This might cause a significant performance impact. */
4304 
4305 /* Bit 12 : Data discard field. Controls if a trace unit can discard data trace elements on a store when the data trace buffer space is less than LEVEL. */
4306 #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos (12UL) /*!< Position of DATADISCARDSTORE field. */
4307 #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos) /*!< Bit mask of DATADISCARDSTORE field. */
4308 #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements. */
4309 #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with data stores. */
4310 
4311 /* Bit 11 : Data discard field. Controls if a trace unit can discard data trace elements on a load when the data trace buffer space is less than LEVEL. */
4312 #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos (11UL) /*!< Position of DATADISCARDLOAD field. */
4313 #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos) /*!< Bit mask of DATADISCARDLOAD field. */
4314 #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements. */
4315 #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with data loads. */
4316 
4317 /* Bit 10 : Prioritize instruction trace bit. Controls if a trace unit can prioritize instruction trace when the instruction trace buffer space is less than LEVEL. */
4318 #define ETM_TRCSTALLCTLR_INSTPRIORITY_Pos (10UL) /*!< Position of INSTPRIORITY field. */
4319 #define ETM_TRCSTALLCTLR_INSTPRIORITY_Msk (0x1UL << ETM_TRCSTALLCTLR_INSTPRIORITY_Pos) /*!< Bit mask of INSTPRIORITY field. */
4320 #define ETM_TRCSTALLCTLR_INSTPRIORITY_Disabled (0x0UL) /*!< The trace unit must not prioritize instruction trace. */
4321 #define ETM_TRCSTALLCTLR_INSTPRIORITY_Enabled (0x1UL) /*!< The trace unit can prioritize instruction trace. A trace unit might prioritize
4322 instruction trace by preventing output of data trace, or other means which ensure
4323 that the instruction trace has a higher priority than the data trace. */
4324 
4325 /* Bit 9 : Data stall bit. Controls if a trace unit can stall the PE when the data trace buffer space is less than LEVEL. */
4326 #define ETM_TRCSTALLCTLR_DSTALL_Pos (9UL) /*!< Position of DSTALL field. */
4327 #define ETM_TRCSTALLCTLR_DSTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_DSTALL_Pos) /*!< Bit mask of DSTALL field. */
4328 #define ETM_TRCSTALLCTLR_DSTALL_Disabled (0x0UL) /*!< The trace unit must not stall the PE. */
4329 #define ETM_TRCSTALLCTLR_DSTALL_Enabled (0x1UL) /*!< The trace unit can stall the PE. */
4330 
4331 /* Bit 8 : Instruction stall bit. Controls if a trace unit can stall the PE when the instruction trace buffer space is less than LEVEL. */
4332 #define ETM_TRCSTALLCTLR_ISTALL_Pos (8UL) /*!< Position of ISTALL field. */
4333 #define ETM_TRCSTALLCTLR_ISTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_ISTALL_Pos) /*!< Bit mask of ISTALL field. */
4334 #define ETM_TRCSTALLCTLR_ISTALL_Disabled (0x0UL) /*!< The trace unit must not stall the PE. */
4335 #define ETM_TRCSTALLCTLR_ISTALL_Enabled (0x1UL) /*!< The trace unit can stall the PE. */
4336 
4337 /* Bits 3..0 : Threshold level field. If LEVEL is nonzero then a trace unit might suppress the generation of: Global timestamps in the instruction trace stream and the data trace stream. Cycle counting in the instruction trace stream, although the cumulative cycle count remains correct. */
4338 #define ETM_TRCSTALLCTLR_LEVEL_Pos (0UL) /*!< Position of LEVEL field. */
4339 #define ETM_TRCSTALLCTLR_LEVEL_Msk (0xFUL << ETM_TRCSTALLCTLR_LEVEL_Pos) /*!< Bit mask of LEVEL field. */
4340 #define ETM_TRCSTALLCTLR_LEVEL_Min (0x0UL) /*!< Zero invasion. This setting has a greater risk of a FIFO overflow */
4341 #define ETM_TRCSTALLCTLR_LEVEL_Max (0xFUL) /*!< Maximum invasion occurs but there is less risk of a FIFO overflow. */
4342 
4343 /* Register: ETM_TRCTSCTLR */
4344 /* Description: Controls the insertion of global timestamps in the trace streams. When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.TS == 1. */
4345 
4346 /* Bits 7..0 : Select which event should generate time stamps. */
4347 #define ETM_TRCTSCTLR_EVENT_Pos (0UL) /*!< Position of EVENT field. */
4348 #define ETM_TRCTSCTLR_EVENT_Msk (0xFFUL << ETM_TRCTSCTLR_EVENT_Pos) /*!< Bit mask of EVENT field. */
4349 
4350 /* Register: ETM_TRCSYNCPR */
4351 /* Description: Controls how often trace synchronization requests occur. Might ignore writes when the trace unit is enabled or not idle. If writes are permitted then the register must be programmed. */
4352 
4353 /* Bits 4..0 : Controls how many bytes of trace, the sum of instruction and data, that a trace unit can
4354 generate before a trace synchronization request occurs. The number of bytes is always a power of two, calculated by 2^PERIOD */
4355 #define ETM_TRCSYNCPR_PERIOD_Pos (0UL) /*!< Position of PERIOD field. */
4356 #define ETM_TRCSYNCPR_PERIOD_Msk (0x1FUL << ETM_TRCSYNCPR_PERIOD_Pos) /*!< Bit mask of PERIOD field. */
4357 #define ETM_TRCSYNCPR_PERIOD_Disabled (0x00UL) /*!< Trace synchronization requests are disabled. This setting does not disable other types of trace synchronization request. */
4358 
4359 /* Register: ETM_TRCCCCTLR */
4360 /* Description: Sets the threshold value for cycle counting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.CCI==1. */
4361 
4362 /* Bits 11..0 : Sets the threshold value for instruction trace cycle counting. */
4363 #define ETM_TRCCCCTLR_THRESHOLD_Pos (0UL) /*!< Position of THRESHOLD field. */
4364 #define ETM_TRCCCCTLR_THRESHOLD_Msk (0xFFFUL << ETM_TRCCCCTLR_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
4365 
4366 /* Register: ETM_TRCBBCTLR */
4367 /* Description: Controls which regions in the memory map are enabled to use branch broadcasting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.BB == 1. */
4368 
4369 /* Bit 7 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting.
4370         Each field represents an address range comparator pair, so field[7] controls the selection of address range comparator pair 7. */
4371 #define ETM_TRCBBCTLR_RANGE_7_Pos (7UL) /*!< Position of RANGE_7 field. */
4372 #define ETM_TRCBBCTLR_RANGE_7_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_7_Pos) /*!< Bit mask of RANGE_7 field. */
4373 #define ETM_TRCBBCTLR_RANGE_7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not selected. */
4374 #define ETM_TRCBBCTLR_RANGE_7_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */
4375 
4376 /* Bit 6 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting.
4377         Each field represents an address range comparator pair, so field[6] controls the selection of address range comparator pair 6. */
4378 #define ETM_TRCBBCTLR_RANGE_6_Pos (6UL) /*!< Position of RANGE_6 field. */
4379 #define ETM_TRCBBCTLR_RANGE_6_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_6_Pos) /*!< Bit mask of RANGE_6 field. */
4380 #define ETM_TRCBBCTLR_RANGE_6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not selected. */
4381 #define ETM_TRCBBCTLR_RANGE_6_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */
4382 
4383 /* Bit 5 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting.
4384         Each field represents an address range comparator pair, so field[5] controls the selection of address range comparator pair 5. */
4385 #define ETM_TRCBBCTLR_RANGE_5_Pos (5UL) /*!< Position of RANGE_5 field. */
4386 #define ETM_TRCBBCTLR_RANGE_5_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_5_Pos) /*!< Bit mask of RANGE_5 field. */
4387 #define ETM_TRCBBCTLR_RANGE_5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not selected. */
4388 #define ETM_TRCBBCTLR_RANGE_5_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */
4389 
4390 /* Bit 4 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting.
4391         Each field represents an address range comparator pair, so field[4] controls the selection of address range comparator pair 4. */
4392 #define ETM_TRCBBCTLR_RANGE_4_Pos (4UL) /*!< Position of RANGE_4 field. */
4393 #define ETM_TRCBBCTLR_RANGE_4_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_4_Pos) /*!< Bit mask of RANGE_4 field. */
4394 #define ETM_TRCBBCTLR_RANGE_4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not selected. */
4395 #define ETM_TRCBBCTLR_RANGE_4_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */
4396 
4397 /* Bit 3 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting.
4398         Each field represents an address range comparator pair, so field[3] controls the selection of address range comparator pair 3. */
4399 #define ETM_TRCBBCTLR_RANGE_3_Pos (3UL) /*!< Position of RANGE_3 field. */
4400 #define ETM_TRCBBCTLR_RANGE_3_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_3_Pos) /*!< Bit mask of RANGE_3 field. */
4401 #define ETM_TRCBBCTLR_RANGE_3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not selected. */
4402 #define ETM_TRCBBCTLR_RANGE_3_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */
4403 
4404 /* Bit 2 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting.
4405         Each field represents an address range comparator pair, so field[2] controls the selection of address range comparator pair 2. */
4406 #define ETM_TRCBBCTLR_RANGE_2_Pos (2UL) /*!< Position of RANGE_2 field. */
4407 #define ETM_TRCBBCTLR_RANGE_2_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_2_Pos) /*!< Bit mask of RANGE_2 field. */
4408 #define ETM_TRCBBCTLR_RANGE_2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not selected. */
4409 #define ETM_TRCBBCTLR_RANGE_2_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */
4410 
4411 /* Bit 1 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting.
4412         Each field represents an address range comparator pair, so field[1] controls the selection of address range comparator pair 1. */
4413 #define ETM_TRCBBCTLR_RANGE_1_Pos (1UL) /*!< Position of RANGE_1 field. */
4414 #define ETM_TRCBBCTLR_RANGE_1_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_1_Pos) /*!< Bit mask of RANGE_1 field. */
4415 #define ETM_TRCBBCTLR_RANGE_1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not selected. */
4416 #define ETM_TRCBBCTLR_RANGE_1_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */
4417 
4418 /* Bit 0 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting.
4419         Each field represents an address range comparator pair, so field[0] controls the selection of address range comparator pair 0. */
4420 #define ETM_TRCBBCTLR_RANGE_0_Pos (0UL) /*!< Position of RANGE_0 field. */
4421 #define ETM_TRCBBCTLR_RANGE_0_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_0_Pos) /*!< Bit mask of RANGE_0 field. */
4422 #define ETM_TRCBBCTLR_RANGE_0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not selected. */
4423 #define ETM_TRCBBCTLR_RANGE_0_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */
4424 
4425 /* Register: ETM_TRCTRACEIDR */
4426 /* Description: Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data trace, to (trace ID for instruction trace) + 1. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. */
4427 
4428 /* Bits 6..0 : Trace ID field. Sets the trace ID value for instruction trace. Bit[0] must be zero if data trace is enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1. */
4429 #define ETM_TRCTRACEIDR_TRACEID_Pos (0UL) /*!< Position of TRACEID field. */
4430 #define ETM_TRCTRACEIDR_TRACEID_Msk (0x7FUL << ETM_TRCTRACEIDR_TRACEID_Pos) /*!< Bit mask of TRACEID field. */
4431 
4432 /* Register: ETM_TRCQCTLR */
4433 /* Description: Controls when Q elements are enabled. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00. */
4434 
4435 /* Bit 8 : Selects whether the address range comparators selected by the RANGE field indicate
4436 address ranges where the trace unit is permitted to generate Q elements or address ranges
4437 where the trace unit is not permitted to generate Q elements: */
4438 #define ETM_TRCQCTLR_MODE_Pos (8UL) /*!< Position of MODE field. */
4439 #define ETM_TRCQCTLR_MODE_Msk (0x1UL << ETM_TRCQCTLR_MODE_Pos) /*!< Bit mask of MODE field. */
4440 #define ETM_TRCQCTLR_MODE_Exclude (0x0UL) /*!< Exclude mode. The address range comparators selected by the RANGE field
4441 indicate address ranges where the trace unit cannot generate Q elements. If no
4442 ranges are selected, Q elements are permitted across the entire memory map. */
4443 #define ETM_TRCQCTLR_MODE_Include (0x1UL) /*!< Include mode. The address range comparators selected by the RANGE field
4444 indicate address ranges where the trace unit can generate Q elements. If all the
4445 implemented bits in RANGE are set to 0 then Q elements are disabled. */
4446 
4447 /* Bit 7 : Specifies the address range comparators to be used for controlling Q elements. */
4448 #define ETM_TRCQCTLR_RANGE_7_Pos (7UL) /*!< Position of RANGE_7 field. */
4449 #define ETM_TRCQCTLR_RANGE_7_Msk (0x1UL << ETM_TRCQCTLR_RANGE_7_Pos) /*!< Bit mask of RANGE_7 field. */
4450 #define ETM_TRCQCTLR_RANGE_7_Disabled (0x0UL) /*!< Address range comparator 7 is disabled. */
4451 #define ETM_TRCQCTLR_RANGE_7_Enabled (0x1UL) /*!< Address range comparator 7 is selected for use. */
4452 
4453 /* Bit 6 : Specifies the address range comparators to be used for controlling Q elements. */
4454 #define ETM_TRCQCTLR_RANGE_6_Pos (6UL) /*!< Position of RANGE_6 field. */
4455 #define ETM_TRCQCTLR_RANGE_6_Msk (0x1UL << ETM_TRCQCTLR_RANGE_6_Pos) /*!< Bit mask of RANGE_6 field. */
4456 #define ETM_TRCQCTLR_RANGE_6_Disabled (0x0UL) /*!< Address range comparator 6 is disabled. */
4457 #define ETM_TRCQCTLR_RANGE_6_Enabled (0x1UL) /*!< Address range comparator 6 is selected for use. */
4458 
4459 /* Bit 5 : Specifies the address range comparators to be used for controlling Q elements. */
4460 #define ETM_TRCQCTLR_RANGE_5_Pos (5UL) /*!< Position of RANGE_5 field. */
4461 #define ETM_TRCQCTLR_RANGE_5_Msk (0x1UL << ETM_TRCQCTLR_RANGE_5_Pos) /*!< Bit mask of RANGE_5 field. */
4462 #define ETM_TRCQCTLR_RANGE_5_Disabled (0x0UL) /*!< Address range comparator 5 is disabled. */
4463 #define ETM_TRCQCTLR_RANGE_5_Enabled (0x1UL) /*!< Address range comparator 5 is selected for use. */
4464 
4465 /* Bit 4 : Specifies the address range comparators to be used for controlling Q elements. */
4466 #define ETM_TRCQCTLR_RANGE_4_Pos (4UL) /*!< Position of RANGE_4 field. */
4467 #define ETM_TRCQCTLR_RANGE_4_Msk (0x1UL << ETM_TRCQCTLR_RANGE_4_Pos) /*!< Bit mask of RANGE_4 field. */
4468 #define ETM_TRCQCTLR_RANGE_4_Disabled (0x0UL) /*!< Address range comparator 4 is disabled. */
4469 #define ETM_TRCQCTLR_RANGE_4_Enabled (0x1UL) /*!< Address range comparator 4 is selected for use. */
4470 
4471 /* Bit 3 : Specifies the address range comparators to be used for controlling Q elements. */
4472 #define ETM_TRCQCTLR_RANGE_3_Pos (3UL) /*!< Position of RANGE_3 field. */
4473 #define ETM_TRCQCTLR_RANGE_3_Msk (0x1UL << ETM_TRCQCTLR_RANGE_3_Pos) /*!< Bit mask of RANGE_3 field. */
4474 #define ETM_TRCQCTLR_RANGE_3_Disabled (0x0UL) /*!< Address range comparator 3 is disabled. */
4475 #define ETM_TRCQCTLR_RANGE_3_Enabled (0x1UL) /*!< Address range comparator 3 is selected for use. */
4476 
4477 /* Bit 2 : Specifies the address range comparators to be used for controlling Q elements. */
4478 #define ETM_TRCQCTLR_RANGE_2_Pos (2UL) /*!< Position of RANGE_2 field. */
4479 #define ETM_TRCQCTLR_RANGE_2_Msk (0x1UL << ETM_TRCQCTLR_RANGE_2_Pos) /*!< Bit mask of RANGE_2 field. */
4480 #define ETM_TRCQCTLR_RANGE_2_Disabled (0x0UL) /*!< Address range comparator 2 is disabled. */
4481 #define ETM_TRCQCTLR_RANGE_2_Enabled (0x1UL) /*!< Address range comparator 2 is selected for use. */
4482 
4483 /* Bit 1 : Specifies the address range comparators to be used for controlling Q elements. */
4484 #define ETM_TRCQCTLR_RANGE_1_Pos (1UL) /*!< Position of RANGE_1 field. */
4485 #define ETM_TRCQCTLR_RANGE_1_Msk (0x1UL << ETM_TRCQCTLR_RANGE_1_Pos) /*!< Bit mask of RANGE_1 field. */
4486 #define ETM_TRCQCTLR_RANGE_1_Disabled (0x0UL) /*!< Address range comparator 1 is disabled. */
4487 #define ETM_TRCQCTLR_RANGE_1_Enabled (0x1UL) /*!< Address range comparator 1 is selected for use. */
4488 
4489 /* Bit 0 : Specifies the address range comparators to be used for controlling Q elements. */
4490 #define ETM_TRCQCTLR_RANGE_0_Pos (0UL) /*!< Position of RANGE_0 field. */
4491 #define ETM_TRCQCTLR_RANGE_0_Msk (0x1UL << ETM_TRCQCTLR_RANGE_0_Pos) /*!< Bit mask of RANGE_0 field. */
4492 #define ETM_TRCQCTLR_RANGE_0_Disabled (0x0UL) /*!< Address range comparator 0 is disabled. */
4493 #define ETM_TRCQCTLR_RANGE_0_Enabled (0x1UL) /*!< Address range comparator 0 is selected for use. */
4494 
4495 /* Register: ETM_TRCVICTLR */
4496 /* Description: Controls instruction trace filtering. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. Must be programmed, particularly to set the value of the SSSTATUS bit, which sets the state of the start/stop logic. */
4497 
4498 /* Bit 23 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 3. */
4499 #define ETM_TRCVICTLR_EXLEVEL3_NS_Pos (23UL) /*!< Position of EXLEVEL3_NS field. */
4500 #define ETM_TRCVICTLR_EXLEVEL3_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_NS_Pos) /*!< Bit mask of EXLEVEL3_NS field. */
4501 #define ETM_TRCVICTLR_EXLEVEL3_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for Exception level 3. */
4502 #define ETM_TRCVICTLR_EXLEVEL3_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure state, for Exception level 3. */
4503 
4504 /* Bit 22 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 2. */
4505 #define ETM_TRCVICTLR_EXLEVEL2_NS_Pos (22UL) /*!< Position of EXLEVEL2_NS field. */
4506 #define ETM_TRCVICTLR_EXLEVEL2_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_NS_Pos) /*!< Bit mask of EXLEVEL2_NS field. */
4507 #define ETM_TRCVICTLR_EXLEVEL2_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for Exception level 2. */
4508 #define ETM_TRCVICTLR_EXLEVEL2_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure state, for Exception level 2. */
4509 
4510 /* Bit 21 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 1. */
4511 #define ETM_TRCVICTLR_EXLEVEL1_NS_Pos (21UL) /*!< Position of EXLEVEL1_NS field. */
4512 #define ETM_TRCVICTLR_EXLEVEL1_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_NS_Pos) /*!< Bit mask of EXLEVEL1_NS field. */
4513 #define ETM_TRCVICTLR_EXLEVEL1_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for Exception level 1. */
4514 #define ETM_TRCVICTLR_EXLEVEL1_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure state, for Exception level 1. */
4515 
4516 /* Bit 20 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 0. */
4517 #define ETM_TRCVICTLR_EXLEVEL0_NS_Pos (20UL) /*!< Position of EXLEVEL0_NS field. */
4518 #define ETM_TRCVICTLR_EXLEVEL0_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_NS_Pos) /*!< Bit mask of EXLEVEL0_NS field. */
4519 #define ETM_TRCVICTLR_EXLEVEL0_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for Exception level 0. */
4520 #define ETM_TRCVICTLR_EXLEVEL0_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure state, for Exception level 0. */
4521 
4522 /* Bit 19 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 3. */
4523 #define ETM_TRCVICTLR_EXLEVEL3_S_Pos (19UL) /*!< Position of EXLEVEL3_S field. */
4524 #define ETM_TRCVICTLR_EXLEVEL3_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_S_Pos) /*!< Bit mask of EXLEVEL3_S field. */
4525 #define ETM_TRCVICTLR_EXLEVEL3_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for Exception level 3. */
4526 #define ETM_TRCVICTLR_EXLEVEL3_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, for Exception level 3. */
4527 
4528 /* Bit 18 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 2. */
4529 #define ETM_TRCVICTLR_EXLEVEL2_S_Pos (18UL) /*!< Position of EXLEVEL2_S field. */
4530 #define ETM_TRCVICTLR_EXLEVEL2_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_S_Pos) /*!< Bit mask of EXLEVEL2_S field. */
4531 #define ETM_TRCVICTLR_EXLEVEL2_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for Exception level 2. */
4532 #define ETM_TRCVICTLR_EXLEVEL2_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, for Exception level 2. */
4533 
4534 /* Bit 17 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 1. */
4535 #define ETM_TRCVICTLR_EXLEVEL1_S_Pos (17UL) /*!< Position of EXLEVEL1_S field. */
4536 #define ETM_TRCVICTLR_EXLEVEL1_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_S_Pos) /*!< Bit mask of EXLEVEL1_S field. */
4537 #define ETM_TRCVICTLR_EXLEVEL1_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for Exception level 1. */
4538 #define ETM_TRCVICTLR_EXLEVEL1_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, for Exception level 1. */
4539 
4540 /* Bit 16 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 0. */
4541 #define ETM_TRCVICTLR_EXLEVEL0_S_Pos (16UL) /*!< Position of EXLEVEL0_S field. */
4542 #define ETM_TRCVICTLR_EXLEVEL0_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_S_Pos) /*!< Bit mask of EXLEVEL0_S field. */
4543 #define ETM_TRCVICTLR_EXLEVEL0_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for Exception level 0. */
4544 #define ETM_TRCVICTLR_EXLEVEL0_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, for Exception level 0. */
4545 
4546 /* Bit 11 : When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception. */
4547 #define ETM_TRCVICTLR_TRCERR_Pos (11UL) /*!< Position of TRCERR field. */
4548 #define ETM_TRCVICTLR_TRCERR_Msk (0x1UL << ETM_TRCVICTLR_TRCERR_Pos) /*!< Bit mask of TRCERR field. */
4549 #define ETM_TRCVICTLR_TRCERR_Disabled (0x0UL) /*!< The trace unit does not trace a System error exception unless it traces the exception or instruction immediately prior to the System error exception. */
4550 #define ETM_TRCVICTLR_TRCERR_Enabled (0x1UL) /*!< The trace unit always traces a System error exception, regardless of the value of ViewInst. */
4551 
4552 /* Bit 10 : Controls whether a trace unit must trace a Reset exception. */
4553 #define ETM_TRCVICTLR_TRCRESET_Pos (10UL) /*!< Position of TRCRESET field. */
4554 #define ETM_TRCVICTLR_TRCRESET_Msk (0x1UL << ETM_TRCVICTLR_TRCRESET_Pos) /*!< Bit mask of TRCRESET field. */
4555 #define ETM_TRCVICTLR_TRCRESET_Disabled (0x0UL) /*!< The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception. */
4556 #define ETM_TRCVICTLR_TRCRESET_Enabled (0x1UL) /*!< The trace unit always traces a Reset exception. */
4557 
4558 /* Bit 9 : When TRCIDR4.NUMACPAIRS &gt; 0 or TRCIDR4.NUMPC &gt; 0, this bit returns the status of the start/stop logic. */
4559 #define ETM_TRCVICTLR_SSSTATUS_Pos (9UL) /*!< Position of SSSTATUS field. */
4560 #define ETM_TRCVICTLR_SSSTATUS_Msk (0x1UL << ETM_TRCVICTLR_SSSTATUS_Pos) /*!< Bit mask of SSSTATUS field. */
4561 #define ETM_TRCVICTLR_SSSTATUS_Stopped (0x0UL) /*!< The start/stop logic is in the stopped state. */
4562 #define ETM_TRCVICTLR_SSSTATUS_Started (0x1UL) /*!< The start/stop logic is in the started state. */
4563 
4564 /* Bits 4..0 : Select which resource number should be filtered. */
4565 #define ETM_TRCVICTLR_EVENT_SEL_Pos (0UL) /*!< Position of EVENT_SEL field. */
4566 #define ETM_TRCVICTLR_EVENT_SEL_Msk (0x1FUL << ETM_TRCVICTLR_EVENT_SEL_Pos) /*!< Bit mask of EVENT_SEL field. */
4567 #define ETM_TRCVICTLR_EVENT_SEL_Disabled (0x00UL) /*!< This event is not filtered. */
4568 #define ETM_TRCVICTLR_EVENT_SEL_Enabled (0x01UL) /*!< This event is filtered. */
4569 
4570 /* Register: ETM_TRCVIIECTLR */
4571 /* Description: ViewInst exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. */
4572 
4573 /* Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */
4574 #define ETM_TRCVIIECTLR_EXCLUDE_7_Pos (23UL) /*!< Position of EXCLUDE_7 field. */
4575 #define ETM_TRCVIIECTLR_EXCLUDE_7_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_7_Pos) /*!< Bit mask of EXCLUDE_7 field. */
4576 #define ETM_TRCVIIECTLR_EXCLUDE_7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not selected for ViewInst exclude control. */
4577 #define ETM_TRCVIIECTLR_EXCLUDE_7_Enabled (0x1UL) /*!< The address range that address range comparator pair 7 defines, is selected for ViewInst exclude control. */
4578 
4579 /* Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */
4580 #define ETM_TRCVIIECTLR_EXCLUDE_6_Pos (22UL) /*!< Position of EXCLUDE_6 field. */
4581 #define ETM_TRCVIIECTLR_EXCLUDE_6_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_6_Pos) /*!< Bit mask of EXCLUDE_6 field. */
4582 #define ETM_TRCVIIECTLR_EXCLUDE_6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not selected for ViewInst exclude control. */
4583 #define ETM_TRCVIIECTLR_EXCLUDE_6_Enabled (0x1UL) /*!< The address range that address range comparator pair 6 defines, is selected for ViewInst exclude control. */
4584 
4585 /* Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */
4586 #define ETM_TRCVIIECTLR_EXCLUDE_5_Pos (21UL) /*!< Position of EXCLUDE_5 field. */
4587 #define ETM_TRCVIIECTLR_EXCLUDE_5_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_5_Pos) /*!< Bit mask of EXCLUDE_5 field. */
4588 #define ETM_TRCVIIECTLR_EXCLUDE_5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not selected for ViewInst exclude control. */
4589 #define ETM_TRCVIIECTLR_EXCLUDE_5_Enabled (0x1UL) /*!< The address range that address range comparator pair 5 defines, is selected for ViewInst exclude control. */
4590 
4591 /* Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */
4592 #define ETM_TRCVIIECTLR_EXCLUDE_4_Pos (20UL) /*!< Position of EXCLUDE_4 field. */
4593 #define ETM_TRCVIIECTLR_EXCLUDE_4_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_4_Pos) /*!< Bit mask of EXCLUDE_4 field. */
4594 #define ETM_TRCVIIECTLR_EXCLUDE_4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not selected for ViewInst exclude control. */
4595 #define ETM_TRCVIIECTLR_EXCLUDE_4_Enabled (0x1UL) /*!< The address range that address range comparator pair 4 defines, is selected for ViewInst exclude control. */
4596 
4597 /* Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */
4598 #define ETM_TRCVIIECTLR_EXCLUDE_3_Pos (19UL) /*!< Position of EXCLUDE_3 field. */
4599 #define ETM_TRCVIIECTLR_EXCLUDE_3_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_3_Pos) /*!< Bit mask of EXCLUDE_3 field. */
4600 #define ETM_TRCVIIECTLR_EXCLUDE_3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not selected for ViewInst exclude control. */
4601 #define ETM_TRCVIIECTLR_EXCLUDE_3_Enabled (0x1UL) /*!< The address range that address range comparator pair 3 defines, is selected for ViewInst exclude control. */
4602 
4603 /* Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */
4604 #define ETM_TRCVIIECTLR_EXCLUDE_2_Pos (18UL) /*!< Position of EXCLUDE_2 field. */
4605 #define ETM_TRCVIIECTLR_EXCLUDE_2_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_2_Pos) /*!< Bit mask of EXCLUDE_2 field. */
4606 #define ETM_TRCVIIECTLR_EXCLUDE_2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not selected for ViewInst exclude control. */
4607 #define ETM_TRCVIIECTLR_EXCLUDE_2_Enabled (0x1UL) /*!< The address range that address range comparator pair 2 defines, is selected for ViewInst exclude control. */
4608 
4609 /* Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */
4610 #define ETM_TRCVIIECTLR_EXCLUDE_1_Pos (17UL) /*!< Position of EXCLUDE_1 field. */
4611 #define ETM_TRCVIIECTLR_EXCLUDE_1_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_1_Pos) /*!< Bit mask of EXCLUDE_1 field. */
4612 #define ETM_TRCVIIECTLR_EXCLUDE_1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not selected for ViewInst exclude control. */
4613 #define ETM_TRCVIIECTLR_EXCLUDE_1_Enabled (0x1UL) /*!< The address range that address range comparator pair 1 defines, is selected for ViewInst exclude control. */
4614 
4615 /* Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */
4616 #define ETM_TRCVIIECTLR_EXCLUDE_0_Pos (16UL) /*!< Position of EXCLUDE_0 field. */
4617 #define ETM_TRCVIIECTLR_EXCLUDE_0_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_0_Pos) /*!< Bit mask of EXCLUDE_0 field. */
4618 #define ETM_TRCVIIECTLR_EXCLUDE_0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not selected for ViewInst exclude control. */
4619 #define ETM_TRCVIIECTLR_EXCLUDE_0_Enabled (0x1UL) /*!< The address range that address range comparator pair 0 defines, is selected for ViewInst exclude control. */
4620 
4621 /* Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */
4622 #define ETM_TRCVIIECTLR_INCLUDE_7_Pos (7UL) /*!< Position of INCLUDE_7 field. */
4623 #define ETM_TRCVIIECTLR_INCLUDE_7_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_7_Pos) /*!< Bit mask of INCLUDE_7 field. */
4624 #define ETM_TRCVIIECTLR_INCLUDE_7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not selected for ViewInst include control. */
4625 #define ETM_TRCVIIECTLR_INCLUDE_7_Enabled (0x1UL) /*!< The address range that address range comparator pair 7 defines, is selected for ViewInst include control. */
4626 
4627 /* Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */
4628 #define ETM_TRCVIIECTLR_INCLUDE_6_Pos (6UL) /*!< Position of INCLUDE_6 field. */
4629 #define ETM_TRCVIIECTLR_INCLUDE_6_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_6_Pos) /*!< Bit mask of INCLUDE_6 field. */
4630 #define ETM_TRCVIIECTLR_INCLUDE_6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not selected for ViewInst include control. */
4631 #define ETM_TRCVIIECTLR_INCLUDE_6_Enabled (0x1UL) /*!< The address range that address range comparator pair 6 defines, is selected for ViewInst include control. */
4632 
4633 /* Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */
4634 #define ETM_TRCVIIECTLR_INCLUDE_5_Pos (5UL) /*!< Position of INCLUDE_5 field. */
4635 #define ETM_TRCVIIECTLR_INCLUDE_5_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_5_Pos) /*!< Bit mask of INCLUDE_5 field. */
4636 #define ETM_TRCVIIECTLR_INCLUDE_5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not selected for ViewInst include control. */
4637 #define ETM_TRCVIIECTLR_INCLUDE_5_Enabled (0x1UL) /*!< The address range that address range comparator pair 5 defines, is selected for ViewInst include control. */
4638 
4639 /* Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */
4640 #define ETM_TRCVIIECTLR_INCLUDE_4_Pos (4UL) /*!< Position of INCLUDE_4 field. */
4641 #define ETM_TRCVIIECTLR_INCLUDE_4_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_4_Pos) /*!< Bit mask of INCLUDE_4 field. */
4642 #define ETM_TRCVIIECTLR_INCLUDE_4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not selected for ViewInst include control. */
4643 #define ETM_TRCVIIECTLR_INCLUDE_4_Enabled (0x1UL) /*!< The address range that address range comparator pair 4 defines, is selected for ViewInst include control. */
4644 
4645 /* Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */
4646 #define ETM_TRCVIIECTLR_INCLUDE_3_Pos (3UL) /*!< Position of INCLUDE_3 field. */
4647 #define ETM_TRCVIIECTLR_INCLUDE_3_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_3_Pos) /*!< Bit mask of INCLUDE_3 field. */
4648 #define ETM_TRCVIIECTLR_INCLUDE_3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not selected for ViewInst include control. */
4649 #define ETM_TRCVIIECTLR_INCLUDE_3_Enabled (0x1UL) /*!< The address range that address range comparator pair 3 defines, is selected for ViewInst include control. */
4650 
4651 /* Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */
4652 #define ETM_TRCVIIECTLR_INCLUDE_2_Pos (2UL) /*!< Position of INCLUDE_2 field. */
4653 #define ETM_TRCVIIECTLR_INCLUDE_2_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_2_Pos) /*!< Bit mask of INCLUDE_2 field. */
4654 #define ETM_TRCVIIECTLR_INCLUDE_2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not selected for ViewInst include control. */
4655 #define ETM_TRCVIIECTLR_INCLUDE_2_Enabled (0x1UL) /*!< The address range that address range comparator pair 2 defines, is selected for ViewInst include control. */
4656 
4657 /* Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */
4658 #define ETM_TRCVIIECTLR_INCLUDE_1_Pos (1UL) /*!< Position of INCLUDE_1 field. */
4659 #define ETM_TRCVIIECTLR_INCLUDE_1_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_1_Pos) /*!< Bit mask of INCLUDE_1 field. */
4660 #define ETM_TRCVIIECTLR_INCLUDE_1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not selected for ViewInst include control. */
4661 #define ETM_TRCVIIECTLR_INCLUDE_1_Enabled (0x1UL) /*!< The address range that address range comparator pair 1 defines, is selected for ViewInst include control. */
4662 
4663 /* Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */
4664 #define ETM_TRCVIIECTLR_INCLUDE_0_Pos (0UL) /*!< Position of INCLUDE_0 field. */
4665 #define ETM_TRCVIIECTLR_INCLUDE_0_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_0_Pos) /*!< Bit mask of INCLUDE_0 field. */
4666 #define ETM_TRCVIIECTLR_INCLUDE_0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not selected for ViewInst include control. */
4667 #define ETM_TRCVIIECTLR_INCLUDE_0_Enabled (0x1UL) /*!< The address range that address range comparator pair 0 defines, is selected for ViewInst include control. */
4668 
4669 /* Register: ETM_TRCVISSCTLR */
4670 /* Description: Use this to set, or read, the single address comparators that control the ViewInst start/stop
4671 logic. The start/stop logic is active for an instruction which causes a start and remains active
4672 up to and including an instruction which causes a stop, and then the start/stop logic becomes
4673 inactive. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed. */
4674 
4675 /* Bit 23 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */
4676 #define ETM_TRCVISSCTLR_STOP_7_Pos (23UL) /*!< Position of STOP_7 field. */
4677 #define ETM_TRCVISSCTLR_STOP_7_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_7_Pos) /*!< Bit mask of STOP_7 field. */
4678 #define ETM_TRCVISSCTLR_STOP_7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected as a stop resource. */
4679 #define ETM_TRCVISSCTLR_STOP_7_Enabled (0x1UL) /*!< The single address comparator 7, is selected as a stop resource. */
4680 
4681 /* Bit 22 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */
4682 #define ETM_TRCVISSCTLR_STOP_6_Pos (22UL) /*!< Position of STOP_6 field. */
4683 #define ETM_TRCVISSCTLR_STOP_6_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_6_Pos) /*!< Bit mask of STOP_6 field. */
4684 #define ETM_TRCVISSCTLR_STOP_6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected as a stop resource. */
4685 #define ETM_TRCVISSCTLR_STOP_6_Enabled (0x1UL) /*!< The single address comparator 6, is selected as a stop resource. */
4686 
4687 /* Bit 21 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */
4688 #define ETM_TRCVISSCTLR_STOP_5_Pos (21UL) /*!< Position of STOP_5 field. */
4689 #define ETM_TRCVISSCTLR_STOP_5_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_5_Pos) /*!< Bit mask of STOP_5 field. */
4690 #define ETM_TRCVISSCTLR_STOP_5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected as a stop resource. */
4691 #define ETM_TRCVISSCTLR_STOP_5_Enabled (0x1UL) /*!< The single address comparator 5, is selected as a stop resource. */
4692 
4693 /* Bit 20 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */
4694 #define ETM_TRCVISSCTLR_STOP_4_Pos (20UL) /*!< Position of STOP_4 field. */
4695 #define ETM_TRCVISSCTLR_STOP_4_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_4_Pos) /*!< Bit mask of STOP_4 field. */
4696 #define ETM_TRCVISSCTLR_STOP_4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected as a stop resource. */
4697 #define ETM_TRCVISSCTLR_STOP_4_Enabled (0x1UL) /*!< The single address comparator 4, is selected as a stop resource. */
4698 
4699 /* Bit 19 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */
4700 #define ETM_TRCVISSCTLR_STOP_3_Pos (19UL) /*!< Position of STOP_3 field. */
4701 #define ETM_TRCVISSCTLR_STOP_3_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_3_Pos) /*!< Bit mask of STOP_3 field. */
4702 #define ETM_TRCVISSCTLR_STOP_3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected as a stop resource. */
4703 #define ETM_TRCVISSCTLR_STOP_3_Enabled (0x1UL) /*!< The single address comparator 3, is selected as a stop resource. */
4704 
4705 /* Bit 18 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */
4706 #define ETM_TRCVISSCTLR_STOP_2_Pos (18UL) /*!< Position of STOP_2 field. */
4707 #define ETM_TRCVISSCTLR_STOP_2_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_2_Pos) /*!< Bit mask of STOP_2 field. */
4708 #define ETM_TRCVISSCTLR_STOP_2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected as a stop resource. */
4709 #define ETM_TRCVISSCTLR_STOP_2_Enabled (0x1UL) /*!< The single address comparator 2, is selected as a stop resource. */
4710 
4711 /* Bit 17 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */
4712 #define ETM_TRCVISSCTLR_STOP_1_Pos (17UL) /*!< Position of STOP_1 field. */
4713 #define ETM_TRCVISSCTLR_STOP_1_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_1_Pos) /*!< Bit mask of STOP_1 field. */
4714 #define ETM_TRCVISSCTLR_STOP_1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected as a stop resource. */
4715 #define ETM_TRCVISSCTLR_STOP_1_Enabled (0x1UL) /*!< The single address comparator 1, is selected as a stop resource. */
4716 
4717 /* Bit 16 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */
4718 #define ETM_TRCVISSCTLR_STOP_0_Pos (16UL) /*!< Position of STOP_0 field. */
4719 #define ETM_TRCVISSCTLR_STOP_0_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_0_Pos) /*!< Bit mask of STOP_0 field. */
4720 #define ETM_TRCVISSCTLR_STOP_0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected as a stop resource. */
4721 #define ETM_TRCVISSCTLR_STOP_0_Enabled (0x1UL) /*!< The single address comparator 0, is selected as a stop resource. */
4722 
4723 /* Bit 7 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */
4724 #define ETM_TRCVISSCTLR_START_7_Pos (7UL) /*!< Position of START_7 field. */
4725 #define ETM_TRCVISSCTLR_START_7_Msk (0x1UL << ETM_TRCVISSCTLR_START_7_Pos) /*!< Bit mask of START_7 field. */
4726 #define ETM_TRCVISSCTLR_START_7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected as a start resource. */
4727 #define ETM_TRCVISSCTLR_START_7_Enabled (0x1UL) /*!< The single address comparator 7, is selected as a start resource. */
4728 
4729 /* Bit 6 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */
4730 #define ETM_TRCVISSCTLR_START_6_Pos (6UL) /*!< Position of START_6 field. */
4731 #define ETM_TRCVISSCTLR_START_6_Msk (0x1UL << ETM_TRCVISSCTLR_START_6_Pos) /*!< Bit mask of START_6 field. */
4732 #define ETM_TRCVISSCTLR_START_6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected as a start resource. */
4733 #define ETM_TRCVISSCTLR_START_6_Enabled (0x1UL) /*!< The single address comparator 6, is selected as a start resource. */
4734 
4735 /* Bit 5 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */
4736 #define ETM_TRCVISSCTLR_START_5_Pos (5UL) /*!< Position of START_5 field. */
4737 #define ETM_TRCVISSCTLR_START_5_Msk (0x1UL << ETM_TRCVISSCTLR_START_5_Pos) /*!< Bit mask of START_5 field. */
4738 #define ETM_TRCVISSCTLR_START_5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected as a start resource. */
4739 #define ETM_TRCVISSCTLR_START_5_Enabled (0x1UL) /*!< The single address comparator 5, is selected as a start resource. */
4740 
4741 /* Bit 4 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */
4742 #define ETM_TRCVISSCTLR_START_4_Pos (4UL) /*!< Position of START_4 field. */
4743 #define ETM_TRCVISSCTLR_START_4_Msk (0x1UL << ETM_TRCVISSCTLR_START_4_Pos) /*!< Bit mask of START_4 field. */
4744 #define ETM_TRCVISSCTLR_START_4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected as a start resource. */
4745 #define ETM_TRCVISSCTLR_START_4_Enabled (0x1UL) /*!< The single address comparator 4, is selected as a start resource. */
4746 
4747 /* Bit 3 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */
4748 #define ETM_TRCVISSCTLR_START_3_Pos (3UL) /*!< Position of START_3 field. */
4749 #define ETM_TRCVISSCTLR_START_3_Msk (0x1UL << ETM_TRCVISSCTLR_START_3_Pos) /*!< Bit mask of START_3 field. */
4750 #define ETM_TRCVISSCTLR_START_3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected as a start resource. */
4751 #define ETM_TRCVISSCTLR_START_3_Enabled (0x1UL) /*!< The single address comparator 3, is selected as a start resource. */
4752 
4753 /* Bit 2 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */
4754 #define ETM_TRCVISSCTLR_START_2_Pos (2UL) /*!< Position of START_2 field. */
4755 #define ETM_TRCVISSCTLR_START_2_Msk (0x1UL << ETM_TRCVISSCTLR_START_2_Pos) /*!< Bit mask of START_2 field. */
4756 #define ETM_TRCVISSCTLR_START_2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected as a start resource. */
4757 #define ETM_TRCVISSCTLR_START_2_Enabled (0x1UL) /*!< The single address comparator 2, is selected as a start resource. */
4758 
4759 /* Bit 1 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */
4760 #define ETM_TRCVISSCTLR_START_1_Pos (1UL) /*!< Position of START_1 field. */
4761 #define ETM_TRCVISSCTLR_START_1_Msk (0x1UL << ETM_TRCVISSCTLR_START_1_Pos) /*!< Bit mask of START_1 field. */
4762 #define ETM_TRCVISSCTLR_START_1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected as a start resource. */
4763 #define ETM_TRCVISSCTLR_START_1_Enabled (0x1UL) /*!< The single address comparator 1, is selected as a start resource. */
4764 
4765 /* Bit 0 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */
4766 #define ETM_TRCVISSCTLR_START_0_Pos (0UL) /*!< Position of START_0 field. */
4767 #define ETM_TRCVISSCTLR_START_0_Msk (0x1UL << ETM_TRCVISSCTLR_START_0_Pos) /*!< Bit mask of START_0 field. */
4768 #define ETM_TRCVISSCTLR_START_0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected as a start resource. */
4769 #define ETM_TRCVISSCTLR_START_0_Enabled (0x1UL) /*!< The single address comparator 0, is selected as a start resource. */
4770 
4771 /* Register: ETM_TRCVIPCSSCTLR */
4772 /* Description: Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed. */
4773 
4774 /* Bit 23 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */
4775 #define ETM_TRCVIPCSSCTLR_STOP_7_Pos (23UL) /*!< Position of STOP_7 field. */
4776 #define ETM_TRCVIPCSSCTLR_STOP_7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_7_Pos) /*!< Bit mask of STOP_7 field. */
4777 #define ETM_TRCVIPCSSCTLR_STOP_7_Disabled (0x0UL) /*!< The single PE comparator input 7, is not selected as a stop resource. */
4778 #define ETM_TRCVIPCSSCTLR_STOP_7_Enabled (0x1UL) /*!< The single PE comparator input 7, is selected as a stop resource. */
4779 
4780 /* Bit 22 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */
4781 #define ETM_TRCVIPCSSCTLR_STOP_6_Pos (22UL) /*!< Position of STOP_6 field. */
4782 #define ETM_TRCVIPCSSCTLR_STOP_6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_6_Pos) /*!< Bit mask of STOP_6 field. */
4783 #define ETM_TRCVIPCSSCTLR_STOP_6_Disabled (0x0UL) /*!< The single PE comparator input 6, is not selected as a stop resource. */
4784 #define ETM_TRCVIPCSSCTLR_STOP_6_Enabled (0x1UL) /*!< The single PE comparator input 6, is selected as a stop resource. */
4785 
4786 /* Bit 21 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */
4787 #define ETM_TRCVIPCSSCTLR_STOP_5_Pos (21UL) /*!< Position of STOP_5 field. */
4788 #define ETM_TRCVIPCSSCTLR_STOP_5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_5_Pos) /*!< Bit mask of STOP_5 field. */
4789 #define ETM_TRCVIPCSSCTLR_STOP_5_Disabled (0x0UL) /*!< The single PE comparator input 5, is not selected as a stop resource. */
4790 #define ETM_TRCVIPCSSCTLR_STOP_5_Enabled (0x1UL) /*!< The single PE comparator input 5, is selected as a stop resource. */
4791 
4792 /* Bit 20 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */
4793 #define ETM_TRCVIPCSSCTLR_STOP_4_Pos (20UL) /*!< Position of STOP_4 field. */
4794 #define ETM_TRCVIPCSSCTLR_STOP_4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_4_Pos) /*!< Bit mask of STOP_4 field. */
4795 #define ETM_TRCVIPCSSCTLR_STOP_4_Disabled (0x0UL) /*!< The single PE comparator input 4, is not selected as a stop resource. */
4796 #define ETM_TRCVIPCSSCTLR_STOP_4_Enabled (0x1UL) /*!< The single PE comparator input 4, is selected as a stop resource. */
4797 
4798 /* Bit 19 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */
4799 #define ETM_TRCVIPCSSCTLR_STOP_3_Pos (19UL) /*!< Position of STOP_3 field. */
4800 #define ETM_TRCVIPCSSCTLR_STOP_3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_3_Pos) /*!< Bit mask of STOP_3 field. */
4801 #define ETM_TRCVIPCSSCTLR_STOP_3_Disabled (0x0UL) /*!< The single PE comparator input 3, is not selected as a stop resource. */
4802 #define ETM_TRCVIPCSSCTLR_STOP_3_Enabled (0x1UL) /*!< The single PE comparator input 3, is selected as a stop resource. */
4803 
4804 /* Bit 18 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */
4805 #define ETM_TRCVIPCSSCTLR_STOP_2_Pos (18UL) /*!< Position of STOP_2 field. */
4806 #define ETM_TRCVIPCSSCTLR_STOP_2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_2_Pos) /*!< Bit mask of STOP_2 field. */
4807 #define ETM_TRCVIPCSSCTLR_STOP_2_Disabled (0x0UL) /*!< The single PE comparator input 2, is not selected as a stop resource. */
4808 #define ETM_TRCVIPCSSCTLR_STOP_2_Enabled (0x1UL) /*!< The single PE comparator input 2, is selected as a stop resource. */
4809 
4810 /* Bit 17 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */
4811 #define ETM_TRCVIPCSSCTLR_STOP_1_Pos (17UL) /*!< Position of STOP_1 field. */
4812 #define ETM_TRCVIPCSSCTLR_STOP_1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_1_Pos) /*!< Bit mask of STOP_1 field. */
4813 #define ETM_TRCVIPCSSCTLR_STOP_1_Disabled (0x0UL) /*!< The single PE comparator input 1, is not selected as a stop resource. */
4814 #define ETM_TRCVIPCSSCTLR_STOP_1_Enabled (0x1UL) /*!< The single PE comparator input 1, is selected as a stop resource. */
4815 
4816 /* Bit 16 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */
4817 #define ETM_TRCVIPCSSCTLR_STOP_0_Pos (16UL) /*!< Position of STOP_0 field. */
4818 #define ETM_TRCVIPCSSCTLR_STOP_0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_0_Pos) /*!< Bit mask of STOP_0 field. */
4819 #define ETM_TRCVIPCSSCTLR_STOP_0_Disabled (0x0UL) /*!< The single PE comparator input 0, is not selected as a stop resource. */
4820 #define ETM_TRCVIPCSSCTLR_STOP_0_Enabled (0x1UL) /*!< The single PE comparator input 0, is selected as a stop resource. */
4821 
4822 /* Bit 7 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */
4823 #define ETM_TRCVIPCSSCTLR_START_7_Pos (7UL) /*!< Position of START_7 field. */
4824 #define ETM_TRCVIPCSSCTLR_START_7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_7_Pos) /*!< Bit mask of START_7 field. */
4825 #define ETM_TRCVIPCSSCTLR_START_7_Disabled (0x0UL) /*!< The single PE comparator input 7, is not selected as a start resource. */
4826 #define ETM_TRCVIPCSSCTLR_START_7_Enabled (0x1UL) /*!< The single PE comparator input 7, is selected as a start resource. */
4827 
4828 /* Bit 6 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */
4829 #define ETM_TRCVIPCSSCTLR_START_6_Pos (6UL) /*!< Position of START_6 field. */
4830 #define ETM_TRCVIPCSSCTLR_START_6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_6_Pos) /*!< Bit mask of START_6 field. */
4831 #define ETM_TRCVIPCSSCTLR_START_6_Disabled (0x0UL) /*!< The single PE comparator input 6, is not selected as a start resource. */
4832 #define ETM_TRCVIPCSSCTLR_START_6_Enabled (0x1UL) /*!< The single PE comparator input 6, is selected as a start resource. */
4833 
4834 /* Bit 5 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */
4835 #define ETM_TRCVIPCSSCTLR_START_5_Pos (5UL) /*!< Position of START_5 field. */
4836 #define ETM_TRCVIPCSSCTLR_START_5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_5_Pos) /*!< Bit mask of START_5 field. */
4837 #define ETM_TRCVIPCSSCTLR_START_5_Disabled (0x0UL) /*!< The single PE comparator input 5, is not selected as a start resource. */
4838 #define ETM_TRCVIPCSSCTLR_START_5_Enabled (0x1UL) /*!< The single PE comparator input 5, is selected as a start resource. */
4839 
4840 /* Bit 4 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */
4841 #define ETM_TRCVIPCSSCTLR_START_4_Pos (4UL) /*!< Position of START_4 field. */
4842 #define ETM_TRCVIPCSSCTLR_START_4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_4_Pos) /*!< Bit mask of START_4 field. */
4843 #define ETM_TRCVIPCSSCTLR_START_4_Disabled (0x0UL) /*!< The single PE comparator input 4, is not selected as a start resource. */
4844 #define ETM_TRCVIPCSSCTLR_START_4_Enabled (0x1UL) /*!< The single PE comparator input 4, is selected as a start resource. */
4845 
4846 /* Bit 3 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */
4847 #define ETM_TRCVIPCSSCTLR_START_3_Pos (3UL) /*!< Position of START_3 field. */
4848 #define ETM_TRCVIPCSSCTLR_START_3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_3_Pos) /*!< Bit mask of START_3 field. */
4849 #define ETM_TRCVIPCSSCTLR_START_3_Disabled (0x0UL) /*!< The single PE comparator input 3, is not selected as a start resource. */
4850 #define ETM_TRCVIPCSSCTLR_START_3_Enabled (0x1UL) /*!< The single PE comparator input 3, is selected as a start resource. */
4851 
4852 /* Bit 2 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */
4853 #define ETM_TRCVIPCSSCTLR_START_2_Pos (2UL) /*!< Position of START_2 field. */
4854 #define ETM_TRCVIPCSSCTLR_START_2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_2_Pos) /*!< Bit mask of START_2 field. */
4855 #define ETM_TRCVIPCSSCTLR_START_2_Disabled (0x0UL) /*!< The single PE comparator input 2, is not selected as a start resource. */
4856 #define ETM_TRCVIPCSSCTLR_START_2_Enabled (0x1UL) /*!< The single PE comparator input 2, is selected as a start resource. */
4857 
4858 /* Bit 1 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */
4859 #define ETM_TRCVIPCSSCTLR_START_1_Pos (1UL) /*!< Position of START_1 field. */
4860 #define ETM_TRCVIPCSSCTLR_START_1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_1_Pos) /*!< Bit mask of START_1 field. */
4861 #define ETM_TRCVIPCSSCTLR_START_1_Disabled (0x0UL) /*!< The single PE comparator input 1, is not selected as a start resource. */
4862 #define ETM_TRCVIPCSSCTLR_START_1_Enabled (0x1UL) /*!< The single PE comparator input 1, is selected as a start resource. */
4863 
4864 /* Bit 0 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */
4865 #define ETM_TRCVIPCSSCTLR_START_0_Pos (0UL) /*!< Position of START_0 field. */
4866 #define ETM_TRCVIPCSSCTLR_START_0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_0_Pos) /*!< Bit mask of START_0 field. */
4867 #define ETM_TRCVIPCSSCTLR_START_0_Disabled (0x0UL) /*!< The single PE comparator input 0, is not selected as a start resource. */
4868 #define ETM_TRCVIPCSSCTLR_START_0_Enabled (0x1UL) /*!< The single PE comparator input 0, is selected as a start resource. */
4869 
4870 /* Register: ETM_TRCVDCTLR */
4871 /* Description: Controls data trace filtering. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == 1. */
4872 
4873 /* Bit 12 : Controls the tracing of data transfers for exceptions and exception returns on Armv6-M, Armv7-M, and Armv8-M PEs. */
4874 #define ETM_TRCVDCTLR_TRCEXDATA_Pos (12UL) /*!< Position of TRCEXDATA field. */
4875 #define ETM_TRCVDCTLR_TRCEXDATA_Msk (0x1UL << ETM_TRCVDCTLR_TRCEXDATA_Pos) /*!< Bit mask of TRCEXDATA field. */
4876 #define ETM_TRCVDCTLR_TRCEXDATA_Disabled (0x0UL) /*!< Exception and exception return data transfers are not traced. */
4877 #define ETM_TRCVDCTLR_TRCEXDATA_Enabled (0x1UL) /*!< Exception and exception return data transfers are traced if the other aspects of ViewData indicate that the data transfers must be traced. */
4878 
4879 /* Bit 11 : Controls which information a trace unit populates in bits[63:56] of the data address. */
4880 #define ETM_TRCVDCTLR_TBI_Pos (11UL) /*!< Position of TBI field. */
4881 #define ETM_TRCVDCTLR_TBI_Msk (0x1UL << ETM_TRCVDCTLR_TBI_Pos) /*!< Bit mask of TBI field. */
4882 #define ETM_TRCVDCTLR_TBI_SignExtend (0x0UL) /*!< The trace unit assigns bits[63:56] to have the same value as bit[55] of the data address, that is, it sign-extends the value. */
4883 #define ETM_TRCVDCTLR_TBI_Copy (0x1UL) /*!< The trace unit assigns bits[63:56] to have the same value as bits[63:56] of the data address. */
4884 
4885 /* Bit 10 : Controls whether a trace unit traces data for transfers that are relative to the Program Counter (PC). */
4886 #define ETM_TRCVDCTLR_PCREL_Pos (10UL) /*!< Position of PCREL field. */
4887 #define ETM_TRCVDCTLR_PCREL_Msk (0x1UL << ETM_TRCVDCTLR_PCREL_Pos) /*!< Bit mask of PCREL field. */
4888 #define ETM_TRCVDCTLR_PCREL_Enabled (0x0UL) /*!< The trace unit does not affect the tracing of PC-relative transfers. */
4889 #define ETM_TRCVDCTLR_PCREL_Disabled (0x1UL) /*!< The trace unit does not trace the address or value portions of PC-relative transfers. */
4890 
4891 /* Bits 9..8 : Controls whether a trace unit traces data for transfers that are relative to the Stack Pointer (SP). */
4892 #define ETM_TRCVDCTLR_SPREL_Pos (8UL) /*!< Position of SPREL field. */
4893 #define ETM_TRCVDCTLR_SPREL_Msk (0x3UL << ETM_TRCVDCTLR_SPREL_Pos) /*!< Bit mask of SPREL field. */
4894 #define ETM_TRCVDCTLR_SPREL_Enabled (0x0UL) /*!< The trace unit does not affect the tracing of SP-relative transfers. */
4895 #define ETM_TRCVDCTLR_SPREL_DataOnly (0x2UL) /*!< The trace unit does not trace the address portion of SP-relative transfers. If data value tracing is enabled then the trace unit generates a P1 data address element. */
4896 #define ETM_TRCVDCTLR_SPREL_Disabled (0x3UL) /*!< The trace unit does not trace the address or value portions of SP-relative transfers. */
4897 
4898 /* Bit 7 : Event unit enable bit. */
4899 #define ETM_TRCVDCTLR_EVENT_7_Pos (7UL) /*!< Position of EVENT_7 field. */
4900 #define ETM_TRCVDCTLR_EVENT_7_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_7_Pos) /*!< Bit mask of EVENT_7 field. */
4901 #define ETM_TRCVDCTLR_EVENT_7_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */
4902 #define ETM_TRCVDCTLR_EVENT_7_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */
4903 
4904 /* Bit 6 : Event unit enable bit. */
4905 #define ETM_TRCVDCTLR_EVENT_6_Pos (6UL) /*!< Position of EVENT_6 field. */
4906 #define ETM_TRCVDCTLR_EVENT_6_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_6_Pos) /*!< Bit mask of EVENT_6 field. */
4907 #define ETM_TRCVDCTLR_EVENT_6_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */
4908 #define ETM_TRCVDCTLR_EVENT_6_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */
4909 
4910 /* Bit 5 : Event unit enable bit. */
4911 #define ETM_TRCVDCTLR_EVENT_5_Pos (5UL) /*!< Position of EVENT_5 field. */
4912 #define ETM_TRCVDCTLR_EVENT_5_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_5_Pos) /*!< Bit mask of EVENT_5 field. */
4913 #define ETM_TRCVDCTLR_EVENT_5_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */
4914 #define ETM_TRCVDCTLR_EVENT_5_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */
4915 
4916 /* Bit 4 : Event unit enable bit. */
4917 #define ETM_TRCVDCTLR_EVENT_4_Pos (4UL) /*!< Position of EVENT_4 field. */
4918 #define ETM_TRCVDCTLR_EVENT_4_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_4_Pos) /*!< Bit mask of EVENT_4 field. */
4919 #define ETM_TRCVDCTLR_EVENT_4_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */
4920 #define ETM_TRCVDCTLR_EVENT_4_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */
4921 
4922 /* Bit 3 : Event unit enable bit. */
4923 #define ETM_TRCVDCTLR_EVENT_3_Pos (3UL) /*!< Position of EVENT_3 field. */
4924 #define ETM_TRCVDCTLR_EVENT_3_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_3_Pos) /*!< Bit mask of EVENT_3 field. */
4925 #define ETM_TRCVDCTLR_EVENT_3_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */
4926 #define ETM_TRCVDCTLR_EVENT_3_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */
4927 
4928 /* Bit 2 : Event unit enable bit. */
4929 #define ETM_TRCVDCTLR_EVENT_2_Pos (2UL) /*!< Position of EVENT_2 field. */
4930 #define ETM_TRCVDCTLR_EVENT_2_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_2_Pos) /*!< Bit mask of EVENT_2 field. */
4931 #define ETM_TRCVDCTLR_EVENT_2_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */
4932 #define ETM_TRCVDCTLR_EVENT_2_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */
4933 
4934 /* Bit 1 : Event unit enable bit. */
4935 #define ETM_TRCVDCTLR_EVENT_1_Pos (1UL) /*!< Position of EVENT_1 field. */
4936 #define ETM_TRCVDCTLR_EVENT_1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_1_Pos) /*!< Bit mask of EVENT_1 field. */
4937 #define ETM_TRCVDCTLR_EVENT_1_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */
4938 #define ETM_TRCVDCTLR_EVENT_1_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */
4939 
4940 /* Bit 0 : Event unit enable bit. */
4941 #define ETM_TRCVDCTLR_EVENT_0_Pos (0UL) /*!< Position of EVENT_0 field. */
4942 #define ETM_TRCVDCTLR_EVENT_0_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_0_Pos) /*!< Bit mask of EVENT_0 field. */
4943 #define ETM_TRCVDCTLR_EVENT_0_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */
4944 #define ETM_TRCVDCTLR_EVENT_0_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */
4945 
4946 /* Register: ETM_TRCVDSACCTLR */
4947 /* Description: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. */
4948 
4949 /* Bit 23 : Selects which single address comparators are in use with ViewData exclude control. */
4950 #define ETM_TRCVDSACCTLR_EXCLUDE_7_Pos (23UL) /*!< Position of EXCLUDE_7 field. */
4951 #define ETM_TRCVDSACCTLR_EXCLUDE_7_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_7_Pos) /*!< Bit mask of EXCLUDE_7 field. */
4952 #define ETM_TRCVDSACCTLR_EXCLUDE_7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData exclude control. */
4953 #define ETM_TRCVDSACCTLR_EXCLUDE_7_Enabled (0x1UL) /*!< The single address comparator 7, s selected for ViewData exclude control. */
4954 
4955 /* Bit 22 : Selects which single address comparators are in use with ViewData exclude control. */
4956 #define ETM_TRCVDSACCTLR_EXCLUDE_6_Pos (22UL) /*!< Position of EXCLUDE_6 field. */
4957 #define ETM_TRCVDSACCTLR_EXCLUDE_6_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_6_Pos) /*!< Bit mask of EXCLUDE_6 field. */
4958 #define ETM_TRCVDSACCTLR_EXCLUDE_6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData exclude control. */
4959 #define ETM_TRCVDSACCTLR_EXCLUDE_6_Enabled (0x1UL) /*!< The single address comparator 6, s selected for ViewData exclude control. */
4960 
4961 /* Bit 21 : Selects which single address comparators are in use with ViewData exclude control. */
4962 #define ETM_TRCVDSACCTLR_EXCLUDE_5_Pos (21UL) /*!< Position of EXCLUDE_5 field. */
4963 #define ETM_TRCVDSACCTLR_EXCLUDE_5_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_5_Pos) /*!< Bit mask of EXCLUDE_5 field. */
4964 #define ETM_TRCVDSACCTLR_EXCLUDE_5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData exclude control. */
4965 #define ETM_TRCVDSACCTLR_EXCLUDE_5_Enabled (0x1UL) /*!< The single address comparator 5, s selected for ViewData exclude control. */
4966 
4967 /* Bit 20 : Selects which single address comparators are in use with ViewData exclude control. */
4968 #define ETM_TRCVDSACCTLR_EXCLUDE_4_Pos (20UL) /*!< Position of EXCLUDE_4 field. */
4969 #define ETM_TRCVDSACCTLR_EXCLUDE_4_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_4_Pos) /*!< Bit mask of EXCLUDE_4 field. */
4970 #define ETM_TRCVDSACCTLR_EXCLUDE_4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData exclude control. */
4971 #define ETM_TRCVDSACCTLR_EXCLUDE_4_Enabled (0x1UL) /*!< The single address comparator 4, s selected for ViewData exclude control. */
4972 
4973 /* Bit 19 : Selects which single address comparators are in use with ViewData exclude control. */
4974 #define ETM_TRCVDSACCTLR_EXCLUDE_3_Pos (19UL) /*!< Position of EXCLUDE_3 field. */
4975 #define ETM_TRCVDSACCTLR_EXCLUDE_3_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_3_Pos) /*!< Bit mask of EXCLUDE_3 field. */
4976 #define ETM_TRCVDSACCTLR_EXCLUDE_3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData exclude control. */
4977 #define ETM_TRCVDSACCTLR_EXCLUDE_3_Enabled (0x1UL) /*!< The single address comparator 3, s selected for ViewData exclude control. */
4978 
4979 /* Bit 18 : Selects which single address comparators are in use with ViewData exclude control. */
4980 #define ETM_TRCVDSACCTLR_EXCLUDE_2_Pos (18UL) /*!< Position of EXCLUDE_2 field. */
4981 #define ETM_TRCVDSACCTLR_EXCLUDE_2_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_2_Pos) /*!< Bit mask of EXCLUDE_2 field. */
4982 #define ETM_TRCVDSACCTLR_EXCLUDE_2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData exclude control. */
4983 #define ETM_TRCVDSACCTLR_EXCLUDE_2_Enabled (0x1UL) /*!< The single address comparator 2, s selected for ViewData exclude control. */
4984 
4985 /* Bit 17 : Selects which single address comparators are in use with ViewData exclude control. */
4986 #define ETM_TRCVDSACCTLR_EXCLUDE_1_Pos (17UL) /*!< Position of EXCLUDE_1 field. */
4987 #define ETM_TRCVDSACCTLR_EXCLUDE_1_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_1_Pos) /*!< Bit mask of EXCLUDE_1 field. */
4988 #define ETM_TRCVDSACCTLR_EXCLUDE_1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData exclude control. */
4989 #define ETM_TRCVDSACCTLR_EXCLUDE_1_Enabled (0x1UL) /*!< The single address comparator 1, s selected for ViewData exclude control. */
4990 
4991 /* Bit 16 : Selects which single address comparators are in use with ViewData exclude control. */
4992 #define ETM_TRCVDSACCTLR_EXCLUDE_0_Pos (16UL) /*!< Position of EXCLUDE_0 field. */
4993 #define ETM_TRCVDSACCTLR_EXCLUDE_0_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_0_Pos) /*!< Bit mask of EXCLUDE_0 field. */
4994 #define ETM_TRCVDSACCTLR_EXCLUDE_0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData exclude control. */
4995 #define ETM_TRCVDSACCTLR_EXCLUDE_0_Enabled (0x1UL) /*!< The single address comparator 0, s selected for ViewData exclude control. */
4996 
4997 /* Bit 7 : Selects which single address comparators are in use with ViewData include control. */
4998 #define ETM_TRCVDSACCTLR_INCLUDE_7_Pos (7UL) /*!< Position of INCLUDE_7 field. */
4999 #define ETM_TRCVDSACCTLR_INCLUDE_7_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_7_Pos) /*!< Bit mask of INCLUDE_7 field. */
5000 #define ETM_TRCVDSACCTLR_INCLUDE_7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData include control. */
5001 #define ETM_TRCVDSACCTLR_INCLUDE_7_Enabled (0x1UL) /*!< The single address comparator 7, is selected for ViewData include control. */
5002 
5003 /* Bit 6 : Selects which single address comparators are in use with ViewData include control. */
5004 #define ETM_TRCVDSACCTLR_INCLUDE_6_Pos (6UL) /*!< Position of INCLUDE_6 field. */
5005 #define ETM_TRCVDSACCTLR_INCLUDE_6_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_6_Pos) /*!< Bit mask of INCLUDE_6 field. */
5006 #define ETM_TRCVDSACCTLR_INCLUDE_6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData include control. */
5007 #define ETM_TRCVDSACCTLR_INCLUDE_6_Enabled (0x1UL) /*!< The single address comparator 6, is selected for ViewData include control. */
5008 
5009 /* Bit 5 : Selects which single address comparators are in use with ViewData include control. */
5010 #define ETM_TRCVDSACCTLR_INCLUDE_5_Pos (5UL) /*!< Position of INCLUDE_5 field. */
5011 #define ETM_TRCVDSACCTLR_INCLUDE_5_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_5_Pos) /*!< Bit mask of INCLUDE_5 field. */
5012 #define ETM_TRCVDSACCTLR_INCLUDE_5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData include control. */
5013 #define ETM_TRCVDSACCTLR_INCLUDE_5_Enabled (0x1UL) /*!< The single address comparator 5, is selected for ViewData include control. */
5014 
5015 /* Bit 4 : Selects which single address comparators are in use with ViewData include control. */
5016 #define ETM_TRCVDSACCTLR_INCLUDE_4_Pos (4UL) /*!< Position of INCLUDE_4 field. */
5017 #define ETM_TRCVDSACCTLR_INCLUDE_4_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_4_Pos) /*!< Bit mask of INCLUDE_4 field. */
5018 #define ETM_TRCVDSACCTLR_INCLUDE_4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData include control. */
5019 #define ETM_TRCVDSACCTLR_INCLUDE_4_Enabled (0x1UL) /*!< The single address comparator 4, is selected for ViewData include control. */
5020 
5021 /* Bit 3 : Selects which single address comparators are in use with ViewData include control. */
5022 #define ETM_TRCVDSACCTLR_INCLUDE_3_Pos (3UL) /*!< Position of INCLUDE_3 field. */
5023 #define ETM_TRCVDSACCTLR_INCLUDE_3_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_3_Pos) /*!< Bit mask of INCLUDE_3 field. */
5024 #define ETM_TRCVDSACCTLR_INCLUDE_3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData include control. */
5025 #define ETM_TRCVDSACCTLR_INCLUDE_3_Enabled (0x1UL) /*!< The single address comparator 3, is selected for ViewData include control. */
5026 
5027 /* Bit 2 : Selects which single address comparators are in use with ViewData include control. */
5028 #define ETM_TRCVDSACCTLR_INCLUDE_2_Pos (2UL) /*!< Position of INCLUDE_2 field. */
5029 #define ETM_TRCVDSACCTLR_INCLUDE_2_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_2_Pos) /*!< Bit mask of INCLUDE_2 field. */
5030 #define ETM_TRCVDSACCTLR_INCLUDE_2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData include control. */
5031 #define ETM_TRCVDSACCTLR_INCLUDE_2_Enabled (0x1UL) /*!< The single address comparator 2, is selected for ViewData include control. */
5032 
5033 /* Bit 1 : Selects which single address comparators are in use with ViewData include control. */
5034 #define ETM_TRCVDSACCTLR_INCLUDE_1_Pos (1UL) /*!< Position of INCLUDE_1 field. */
5035 #define ETM_TRCVDSACCTLR_INCLUDE_1_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_1_Pos) /*!< Bit mask of INCLUDE_1 field. */
5036 #define ETM_TRCVDSACCTLR_INCLUDE_1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData include control. */
5037 #define ETM_TRCVDSACCTLR_INCLUDE_1_Enabled (0x1UL) /*!< The single address comparator 1, is selected for ViewData include control. */
5038 
5039 /* Bit 0 : Selects which single address comparators are in use with ViewData include control. */
5040 #define ETM_TRCVDSACCTLR_INCLUDE_0_Pos (0UL) /*!< Position of INCLUDE_0 field. */
5041 #define ETM_TRCVDSACCTLR_INCLUDE_0_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_0_Pos) /*!< Bit mask of INCLUDE_0 field. */
5042 #define ETM_TRCVDSACCTLR_INCLUDE_0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData include control. */
5043 #define ETM_TRCVDSACCTLR_INCLUDE_0_Enabled (0x1UL) /*!< The single address comparator 0, is selected for ViewData include control. */
5044 
5045 /* Register: ETM_TRCVDARCCTLR */
5046 /* Description: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. */
5047 
5048 /* Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */
5049 #define ETM_TRCVDARCCTLR_EXCLUDE_7_Pos (23UL) /*!< Position of EXCLUDE_7 field. */
5050 #define ETM_TRCVDARCCTLR_EXCLUDE_7_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_7_Pos) /*!< Bit mask of EXCLUDE_7 field. */
5051 #define ETM_TRCVDARCCTLR_EXCLUDE_7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not selected for ViewData exclude control. */
5052 #define ETM_TRCVDARCCTLR_EXCLUDE_7_Enabled (0x1UL) /*!< The address range that address range comparator 7 defines, s selected for ViewData exclude control. */
5053 
5054 /* Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */
5055 #define ETM_TRCVDARCCTLR_EXCLUDE_6_Pos (22UL) /*!< Position of EXCLUDE_6 field. */
5056 #define ETM_TRCVDARCCTLR_EXCLUDE_6_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_6_Pos) /*!< Bit mask of EXCLUDE_6 field. */
5057 #define ETM_TRCVDARCCTLR_EXCLUDE_6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not selected for ViewData exclude control. */
5058 #define ETM_TRCVDARCCTLR_EXCLUDE_6_Enabled (0x1UL) /*!< The address range that address range comparator 6 defines, s selected for ViewData exclude control. */
5059 
5060 /* Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */
5061 #define ETM_TRCVDARCCTLR_EXCLUDE_5_Pos (21UL) /*!< Position of EXCLUDE_5 field. */
5062 #define ETM_TRCVDARCCTLR_EXCLUDE_5_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_5_Pos) /*!< Bit mask of EXCLUDE_5 field. */
5063 #define ETM_TRCVDARCCTLR_EXCLUDE_5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not selected for ViewData exclude control. */
5064 #define ETM_TRCVDARCCTLR_EXCLUDE_5_Enabled (0x1UL) /*!< The address range that address range comparator 5 defines, s selected for ViewData exclude control. */
5065 
5066 /* Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */
5067 #define ETM_TRCVDARCCTLR_EXCLUDE_4_Pos (20UL) /*!< Position of EXCLUDE_4 field. */
5068 #define ETM_TRCVDARCCTLR_EXCLUDE_4_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_4_Pos) /*!< Bit mask of EXCLUDE_4 field. */
5069 #define ETM_TRCVDARCCTLR_EXCLUDE_4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not selected for ViewData exclude control. */
5070 #define ETM_TRCVDARCCTLR_EXCLUDE_4_Enabled (0x1UL) /*!< The address range that address range comparator 4 defines, s selected for ViewData exclude control. */
5071 
5072 /* Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */
5073 #define ETM_TRCVDARCCTLR_EXCLUDE_3_Pos (19UL) /*!< Position of EXCLUDE_3 field. */
5074 #define ETM_TRCVDARCCTLR_EXCLUDE_3_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_3_Pos) /*!< Bit mask of EXCLUDE_3 field. */
5075 #define ETM_TRCVDARCCTLR_EXCLUDE_3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not selected for ViewData exclude control. */
5076 #define ETM_TRCVDARCCTLR_EXCLUDE_3_Enabled (0x1UL) /*!< The address range that address range comparator 3 defines, s selected for ViewData exclude control. */
5077 
5078 /* Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */
5079 #define ETM_TRCVDARCCTLR_EXCLUDE_2_Pos (18UL) /*!< Position of EXCLUDE_2 field. */
5080 #define ETM_TRCVDARCCTLR_EXCLUDE_2_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_2_Pos) /*!< Bit mask of EXCLUDE_2 field. */
5081 #define ETM_TRCVDARCCTLR_EXCLUDE_2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not selected for ViewData exclude control. */
5082 #define ETM_TRCVDARCCTLR_EXCLUDE_2_Enabled (0x1UL) /*!< The address range that address range comparator 2 defines, s selected for ViewData exclude control. */
5083 
5084 /* Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */
5085 #define ETM_TRCVDARCCTLR_EXCLUDE_1_Pos (17UL) /*!< Position of EXCLUDE_1 field. */
5086 #define ETM_TRCVDARCCTLR_EXCLUDE_1_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_1_Pos) /*!< Bit mask of EXCLUDE_1 field. */
5087 #define ETM_TRCVDARCCTLR_EXCLUDE_1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not selected for ViewData exclude control. */
5088 #define ETM_TRCVDARCCTLR_EXCLUDE_1_Enabled (0x1UL) /*!< The address range that address range comparator 1 defines, s selected for ViewData exclude control. */
5089 
5090 /* Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */
5091 #define ETM_TRCVDARCCTLR_EXCLUDE_0_Pos (16UL) /*!< Position of EXCLUDE_0 field. */
5092 #define ETM_TRCVDARCCTLR_EXCLUDE_0_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_0_Pos) /*!< Bit mask of EXCLUDE_0 field. */
5093 #define ETM_TRCVDARCCTLR_EXCLUDE_0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not selected for ViewData exclude control. */
5094 #define ETM_TRCVDARCCTLR_EXCLUDE_0_Enabled (0x1UL) /*!< The address range that address range comparator 0 defines, s selected for ViewData exclude control. */
5095 
5096 /* Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */
5097 #define ETM_TRCVDARCCTLR_INCLUDE_7_Pos (7UL) /*!< Position of INCLUDE_7 field. */
5098 #define ETM_TRCVDARCCTLR_INCLUDE_7_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_7_Pos) /*!< Bit mask of INCLUDE_7 field. */
5099 #define ETM_TRCVDARCCTLR_INCLUDE_7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not selected for ViewData include control. */
5100 #define ETM_TRCVDARCCTLR_INCLUDE_7_Enabled (0x1UL) /*!< The address range that address range comparator 7 defines, is selected for ViewData include control. */
5101 
5102 /* Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */
5103 #define ETM_TRCVDARCCTLR_INCLUDE_6_Pos (6UL) /*!< Position of INCLUDE_6 field. */
5104 #define ETM_TRCVDARCCTLR_INCLUDE_6_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_6_Pos) /*!< Bit mask of INCLUDE_6 field. */
5105 #define ETM_TRCVDARCCTLR_INCLUDE_6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not selected for ViewData include control. */
5106 #define ETM_TRCVDARCCTLR_INCLUDE_6_Enabled (0x1UL) /*!< The address range that address range comparator 6 defines, is selected for ViewData include control. */
5107 
5108 /* Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */
5109 #define ETM_TRCVDARCCTLR_INCLUDE_5_Pos (5UL) /*!< Position of INCLUDE_5 field. */
5110 #define ETM_TRCVDARCCTLR_INCLUDE_5_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_5_Pos) /*!< Bit mask of INCLUDE_5 field. */
5111 #define ETM_TRCVDARCCTLR_INCLUDE_5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not selected for ViewData include control. */
5112 #define ETM_TRCVDARCCTLR_INCLUDE_5_Enabled (0x1UL) /*!< The address range that address range comparator 5 defines, is selected for ViewData include control. */
5113 
5114 /* Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */
5115 #define ETM_TRCVDARCCTLR_INCLUDE_4_Pos (4UL) /*!< Position of INCLUDE_4 field. */
5116 #define ETM_TRCVDARCCTLR_INCLUDE_4_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_4_Pos) /*!< Bit mask of INCLUDE_4 field. */
5117 #define ETM_TRCVDARCCTLR_INCLUDE_4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not selected for ViewData include control. */
5118 #define ETM_TRCVDARCCTLR_INCLUDE_4_Enabled (0x1UL) /*!< The address range that address range comparator 4 defines, is selected for ViewData include control. */
5119 
5120 /* Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */
5121 #define ETM_TRCVDARCCTLR_INCLUDE_3_Pos (3UL) /*!< Position of INCLUDE_3 field. */
5122 #define ETM_TRCVDARCCTLR_INCLUDE_3_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_3_Pos) /*!< Bit mask of INCLUDE_3 field. */
5123 #define ETM_TRCVDARCCTLR_INCLUDE_3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not selected for ViewData include control. */
5124 #define ETM_TRCVDARCCTLR_INCLUDE_3_Enabled (0x1UL) /*!< The address range that address range comparator 3 defines, is selected for ViewData include control. */
5125 
5126 /* Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */
5127 #define ETM_TRCVDARCCTLR_INCLUDE_2_Pos (2UL) /*!< Position of INCLUDE_2 field. */
5128 #define ETM_TRCVDARCCTLR_INCLUDE_2_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_2_Pos) /*!< Bit mask of INCLUDE_2 field. */
5129 #define ETM_TRCVDARCCTLR_INCLUDE_2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not selected for ViewData include control. */
5130 #define ETM_TRCVDARCCTLR_INCLUDE_2_Enabled (0x1UL) /*!< The address range that address range comparator 2 defines, is selected for ViewData include control. */
5131 
5132 /* Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */
5133 #define ETM_TRCVDARCCTLR_INCLUDE_1_Pos (1UL) /*!< Position of INCLUDE_1 field. */
5134 #define ETM_TRCVDARCCTLR_INCLUDE_1_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_1_Pos) /*!< Bit mask of INCLUDE_1 field. */
5135 #define ETM_TRCVDARCCTLR_INCLUDE_1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not selected for ViewData include control. */
5136 #define ETM_TRCVDARCCTLR_INCLUDE_1_Enabled (0x1UL) /*!< The address range that address range comparator 1 defines, is selected for ViewData include control. */
5137 
5138 /* Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */
5139 #define ETM_TRCVDARCCTLR_INCLUDE_0_Pos (0UL) /*!< Position of INCLUDE_0 field. */
5140 #define ETM_TRCVDARCCTLR_INCLUDE_0_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_0_Pos) /*!< Bit mask of INCLUDE_0 field. */
5141 #define ETM_TRCVDARCCTLR_INCLUDE_0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not selected for ViewData include control. */
5142 #define ETM_TRCVDARCCTLR_INCLUDE_0_Enabled (0x1UL) /*!< The address range that address range comparator 0 defines, is selected for ViewData include control. */
5143 
5144 /* Register: ETM_TRCSEQEVR */
5145 /* Description: Description collection: Moves the sequencer state according to programmed events. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. */
5146 
5147 /* Bit 15 : Backward field. */
5148 #define ETM_TRCSEQEVR_B_7_Pos (15UL) /*!< Position of B_7 field. */
5149 #define ETM_TRCSEQEVR_B_7_Msk (0x1UL << ETM_TRCSEQEVR_B_7_Pos) /*!< Bit mask of B_7 field. */
5150 #define ETM_TRCSEQEVR_B_7_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5151 #define ETM_TRCSEQEVR_B_7_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */
5152 
5153 /* Bit 14 : Backward field. */
5154 #define ETM_TRCSEQEVR_B_6_Pos (14UL) /*!< Position of B_6 field. */
5155 #define ETM_TRCSEQEVR_B_6_Msk (0x1UL << ETM_TRCSEQEVR_B_6_Pos) /*!< Bit mask of B_6 field. */
5156 #define ETM_TRCSEQEVR_B_6_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5157 #define ETM_TRCSEQEVR_B_6_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */
5158 
5159 /* Bit 13 : Backward field. */
5160 #define ETM_TRCSEQEVR_B_5_Pos (13UL) /*!< Position of B_5 field. */
5161 #define ETM_TRCSEQEVR_B_5_Msk (0x1UL << ETM_TRCSEQEVR_B_5_Pos) /*!< Bit mask of B_5 field. */
5162 #define ETM_TRCSEQEVR_B_5_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5163 #define ETM_TRCSEQEVR_B_5_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */
5164 
5165 /* Bit 12 : Backward field. */
5166 #define ETM_TRCSEQEVR_B_4_Pos (12UL) /*!< Position of B_4 field. */
5167 #define ETM_TRCSEQEVR_B_4_Msk (0x1UL << ETM_TRCSEQEVR_B_4_Pos) /*!< Bit mask of B_4 field. */
5168 #define ETM_TRCSEQEVR_B_4_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5169 #define ETM_TRCSEQEVR_B_4_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */
5170 
5171 /* Bit 11 : Backward field. */
5172 #define ETM_TRCSEQEVR_B_3_Pos (11UL) /*!< Position of B_3 field. */
5173 #define ETM_TRCSEQEVR_B_3_Msk (0x1UL << ETM_TRCSEQEVR_B_3_Pos) /*!< Bit mask of B_3 field. */
5174 #define ETM_TRCSEQEVR_B_3_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5175 #define ETM_TRCSEQEVR_B_3_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */
5176 
5177 /* Bit 10 : Backward field. */
5178 #define ETM_TRCSEQEVR_B_2_Pos (10UL) /*!< Position of B_2 field. */
5179 #define ETM_TRCSEQEVR_B_2_Msk (0x1UL << ETM_TRCSEQEVR_B_2_Pos) /*!< Bit mask of B_2 field. */
5180 #define ETM_TRCSEQEVR_B_2_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5181 #define ETM_TRCSEQEVR_B_2_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */
5182 
5183 /* Bit 9 : Backward field. */
5184 #define ETM_TRCSEQEVR_B_1_Pos (9UL) /*!< Position of B_1 field. */
5185 #define ETM_TRCSEQEVR_B_1_Msk (0x1UL << ETM_TRCSEQEVR_B_1_Pos) /*!< Bit mask of B_1 field. */
5186 #define ETM_TRCSEQEVR_B_1_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5187 #define ETM_TRCSEQEVR_B_1_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */
5188 
5189 /* Bit 8 : Backward field. */
5190 #define ETM_TRCSEQEVR_B_0_Pos (8UL) /*!< Position of B_0 field. */
5191 #define ETM_TRCSEQEVR_B_0_Msk (0x1UL << ETM_TRCSEQEVR_B_0_Pos) /*!< Bit mask of B_0 field. */
5192 #define ETM_TRCSEQEVR_B_0_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5193 #define ETM_TRCSEQEVR_B_0_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */
5194 
5195 /* Bit 7 : Forward field. */
5196 #define ETM_TRCSEQEVR_F_7_Pos (7UL) /*!< Position of F_7 field. */
5197 #define ETM_TRCSEQEVR_F_7_Msk (0x1UL << ETM_TRCSEQEVR_F_7_Pos) /*!< Bit mask of F_7 field. */
5198 #define ETM_TRCSEQEVR_F_7_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5199 #define ETM_TRCSEQEVR_F_7_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */
5200 
5201 /* Bit 6 : Forward field. */
5202 #define ETM_TRCSEQEVR_F_6_Pos (6UL) /*!< Position of F_6 field. */
5203 #define ETM_TRCSEQEVR_F_6_Msk (0x1UL << ETM_TRCSEQEVR_F_6_Pos) /*!< Bit mask of F_6 field. */
5204 #define ETM_TRCSEQEVR_F_6_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5205 #define ETM_TRCSEQEVR_F_6_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */
5206 
5207 /* Bit 5 : Forward field. */
5208 #define ETM_TRCSEQEVR_F_5_Pos (5UL) /*!< Position of F_5 field. */
5209 #define ETM_TRCSEQEVR_F_5_Msk (0x1UL << ETM_TRCSEQEVR_F_5_Pos) /*!< Bit mask of F_5 field. */
5210 #define ETM_TRCSEQEVR_F_5_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5211 #define ETM_TRCSEQEVR_F_5_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */
5212 
5213 /* Bit 4 : Forward field. */
5214 #define ETM_TRCSEQEVR_F_4_Pos (4UL) /*!< Position of F_4 field. */
5215 #define ETM_TRCSEQEVR_F_4_Msk (0x1UL << ETM_TRCSEQEVR_F_4_Pos) /*!< Bit mask of F_4 field. */
5216 #define ETM_TRCSEQEVR_F_4_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5217 #define ETM_TRCSEQEVR_F_4_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */
5218 
5219 /* Bit 3 : Forward field. */
5220 #define ETM_TRCSEQEVR_F_3_Pos (3UL) /*!< Position of F_3 field. */
5221 #define ETM_TRCSEQEVR_F_3_Msk (0x1UL << ETM_TRCSEQEVR_F_3_Pos) /*!< Bit mask of F_3 field. */
5222 #define ETM_TRCSEQEVR_F_3_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5223 #define ETM_TRCSEQEVR_F_3_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */
5224 
5225 /* Bit 2 : Forward field. */
5226 #define ETM_TRCSEQEVR_F_2_Pos (2UL) /*!< Position of F_2 field. */
5227 #define ETM_TRCSEQEVR_F_2_Msk (0x1UL << ETM_TRCSEQEVR_F_2_Pos) /*!< Bit mask of F_2 field. */
5228 #define ETM_TRCSEQEVR_F_2_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5229 #define ETM_TRCSEQEVR_F_2_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */
5230 
5231 /* Bit 1 : Forward field. */
5232 #define ETM_TRCSEQEVR_F_1_Pos (1UL) /*!< Position of F_1 field. */
5233 #define ETM_TRCSEQEVR_F_1_Msk (0x1UL << ETM_TRCSEQEVR_F_1_Pos) /*!< Bit mask of F_1 field. */
5234 #define ETM_TRCSEQEVR_F_1_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5235 #define ETM_TRCSEQEVR_F_1_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */
5236 
5237 /* Bit 0 : Forward field. */
5238 #define ETM_TRCSEQEVR_F_0_Pos (0UL) /*!< Position of F_0 field. */
5239 #define ETM_TRCSEQEVR_F_0_Msk (0x1UL << ETM_TRCSEQEVR_F_0_Pos) /*!< Bit mask of F_0 field. */
5240 #define ETM_TRCSEQEVR_F_0_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */
5241 #define ETM_TRCSEQEVR_F_0_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */
5242 
5243 /* Register: ETM_TRCSEQRSTEVR */
5244 /* Description: Moves the sequencer to state 0 when a programmed event occurs. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. */
5245 
5246 /* Bits 7..0 : Select which event should reset the sequencer. */
5247 #define ETM_TRCSEQRSTEVR_EVENT_Pos (0UL) /*!< Position of EVENT field. */
5248 #define ETM_TRCSEQRSTEVR_EVENT_Msk (0xFFUL << ETM_TRCSEQRSTEVR_EVENT_Pos) /*!< Bit mask of EVENT field. */
5249 
5250 /* Register: ETM_TRCSEQSTR */
5251 /* Description: Use this to set, or read, the sequencer state. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. */
5252 
5253 /* Bits 1..0 : Sets or returns the state of the sequencer. */
5254 #define ETM_TRCSEQSTR_STATE_Pos (0UL) /*!< Position of STATE field. */
5255 #define ETM_TRCSEQSTR_STATE_Msk (0x3UL << ETM_TRCSEQSTR_STATE_Pos) /*!< Bit mask of STATE field. */
5256 #define ETM_TRCSEQSTR_STATE_State0 (0x0UL) /*!< The sequencer is in state 0. */
5257 #define ETM_TRCSEQSTR_STATE_State1 (0x1UL) /*!< The sequencer is in state 1. */
5258 #define ETM_TRCSEQSTR_STATE_State2 (0x2UL) /*!< The sequencer is in state 2. */
5259 #define ETM_TRCSEQSTR_STATE_State3 (0x3UL) /*!< The sequencer is in state 3. */
5260 
5261 /* Register: ETM_TRCEXTINSELR */
5262 /* Description: Use this to set, or read, which external inputs are resources to the trace unit. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. */
5263 
5264 /* Bits 31..24 : Each field in this collection selects an external input as a resource for the trace unit. */
5265 #define ETM_TRCEXTINSELR_SEL_3_Pos (24UL) /*!< Position of SEL_3 field. */
5266 #define ETM_TRCEXTINSELR_SEL_3_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL_3_Pos) /*!< Bit mask of SEL_3 field. */
5267 
5268 /* Bits 23..16 : Each field in this collection selects an external input as a resource for the trace unit. */
5269 #define ETM_TRCEXTINSELR_SEL_2_Pos (16UL) /*!< Position of SEL_2 field. */
5270 #define ETM_TRCEXTINSELR_SEL_2_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL_2_Pos) /*!< Bit mask of SEL_2 field. */
5271 
5272 /* Bits 15..8 : Each field in this collection selects an external input as a resource for the trace unit. */
5273 #define ETM_TRCEXTINSELR_SEL_1_Pos (8UL) /*!< Position of SEL_1 field. */
5274 #define ETM_TRCEXTINSELR_SEL_1_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL_1_Pos) /*!< Bit mask of SEL_1 field. */
5275 
5276 /* Bits 7..0 : Each field in this collection selects an external input as a resource for the trace unit. */
5277 #define ETM_TRCEXTINSELR_SEL_0_Pos (0UL) /*!< Position of SEL_0 field. */
5278 #define ETM_TRCEXTINSELR_SEL_0_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL_0_Pos) /*!< Bit mask of SEL_0 field. */
5279 
5280 /* Register: ETM_TRCCNTRLDVR */
5281 /* Description: Description collection: This sets or returns the reload count value for counter n. Might ignore writes when the trace unit is enabled or not idle. */
5282 
5283 /* Bits 15..0 : Contains the reload value for counter n. When a reload event occurs for counter n then the trace unit copies the VALUEn field into counter n. */
5284 #define ETM_TRCCNTRLDVR_VALUE_Pos (0UL) /*!< Position of VALUE field. */
5285 #define ETM_TRCCNTRLDVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTRLDVR_VALUE_Pos) /*!< Bit mask of VALUE field. */
5286 
5287 /* Register: ETM_TRCCNTCTLR */
5288 /* Description: Description collection: Controls the operation of counter n. Might ignore writes when the trace unit is enabled or not idle. */
5289 
5290 /* Bit 17 : For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs for counter n-1. */
5291 #define ETM_TRCCNTCTLR_CNTCHAIN_Pos (17UL) /*!< Position of CNTCHAIN field. */
5292 #define ETM_TRCCNTCTLR_CNTCHAIN_Msk (0x1UL << ETM_TRCCNTCTLR_CNTCHAIN_Pos) /*!< Bit mask of CNTCHAIN field. */
5293 #define ETM_TRCCNTCTLR_CNTCHAIN_Disabled (0x0UL) /*!< Counter n does not decrement when a reload event for counter n-1 occurs. */
5294 #define ETM_TRCCNTCTLR_CNTCHAIN_Enabled (0x1UL) /*!< Counter n decrements when a reload event for counter n-1 occurs. This concatenates counter n and counter n-1, to provide a larger count value. */
5295 
5296 /* Bit 16 : Controls whether a reload event occurs for counter n, when counter n reaches zero. */
5297 #define ETM_TRCCNTCTLR_RLDSELF_Pos (16UL) /*!< Position of RLDSELF field. */
5298 #define ETM_TRCCNTCTLR_RLDSELF_Msk (0x1UL << ETM_TRCCNTCTLR_RLDSELF_Pos) /*!< Bit mask of RLDSELF field. */
5299 #define ETM_TRCCNTCTLR_RLDSELF_Disabled (0x0UL) /*!< The counter is in Normal mode. */
5300 #define ETM_TRCCNTCTLR_RLDSELF_Enabled (0x1UL) /*!< The counter is in Self-reload mode. */
5301 
5302 /* Bits 15..8 : Selects an event, that when it occurs causes a reload event for counter n. */
5303 #define ETM_TRCCNTCTLR_RLDEVENT_Pos (8UL) /*!< Position of RLDEVENT field. */
5304 #define ETM_TRCCNTCTLR_RLDEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_RLDEVENT_Pos) /*!< Bit mask of RLDEVENT field. */
5305 
5306 /* Bits 7..0 : Selects an event, that when it occurs causes counter n to decrement. */
5307 #define ETM_TRCCNTCTLR_CNTEVENT_Pos (0UL) /*!< Position of CNTEVENT field. */
5308 #define ETM_TRCCNTCTLR_CNTEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_CNTEVENT_Pos) /*!< Bit mask of CNTEVENT field. */
5309 
5310 /* Register: ETM_TRCCNTVR */
5311 /* Description: Description collection: This sets or returns the value of counter n. The count value is only stable when TRCSTATR.PMSTABLE == 1. If software uses counter n then it must write to this register to set the initial counter value. Might ignore writes when the trace unit is enabled or not idle. */
5312 
5313 /* Bits 15..0 : Contains the count value of counter n. */
5314 #define ETM_TRCCNTVR_VALUE_Pos (0UL) /*!< Position of VALUE field. */
5315 #define ETM_TRCCNTVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTVR_VALUE_Pos) /*!< Bit mask of VALUE field. */
5316 
5317 /* Register: ETM_TRCRSCTLR */
5318 /* Description: Description collection: Controls the selection of the resources in the trace unit. Might ignore writes when the trace unit is enabled or not idle. If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE
5319 behavior of the resource selector occurs, so the resource selector might fire
5320 unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. */
5321 
5322 /* Bit 0 : Trace unit enable bit */
5323 #define ETM_TRCRSCTLR_EN_Pos (0UL) /*!< Position of EN field. */
5324 #define ETM_TRCRSCTLR_EN_Msk (0x1UL << ETM_TRCRSCTLR_EN_Pos) /*!< Bit mask of EN field. */
5325 #define ETM_TRCRSCTLR_EN_Disabled (0x0UL) /*!< The trace unit is disabled. All trace resources are inactive and no trace is generated. */
5326 #define ETM_TRCRSCTLR_EN_Enabled (0x1UL) /*!< The trace unit is enabled. */
5327 
5328 /* Register: ETM_TRCSSCCR0 */
5329 /* Description: Controls the single-shot comparator. */
5330 
5331 /* Bit 24 : Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected */
5332 #define ETM_TRCSSCCR0_RST_Pos (24UL) /*!< Position of RST field. */
5333 #define ETM_TRCSSCCR0_RST_Msk (0x1UL << ETM_TRCSSCCR0_RST_Pos) /*!< Bit mask of RST field. */
5334 #define ETM_TRCSSCCR0_RST_Disabled (0x0UL) /*!< Multiple matches can not be detected. */
5335 #define ETM_TRCSSCCR0_RST_Enabled (0x1UL) /*!< Multiple matches can occur. */
5336 
5337 /* Register: ETM_TRCSSCSR0 */
5338 /* Description: Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses. */
5339 
5340 /* Bit 31 : Single-shot status. This indicates whether any of the selected comparators have matched. */
5341 #define ETM_TRCSSCSR0_STATUS_Pos (31UL) /*!< Position of STATUS field. */
5342 #define ETM_TRCSSCSR0_STATUS_Msk (0x1UL << ETM_TRCSSCSR0_STATUS_Pos) /*!< Bit mask of STATUS field. */
5343 #define ETM_TRCSSCSR0_STATUS_NoMatch (0x0UL) /*!< Match has not occurred. */
5344 #define ETM_TRCSSCSR0_STATUS_Match (0x1UL) /*!< Match has occurred at least once. */
5345 
5346 /* Bit 3 : Process counter value comparator support */
5347 #define ETM_TRCSSCSR0_PC_Pos (3UL) /*!< Position of PC field. */
5348 #define ETM_TRCSSCSR0_PC_Msk (0x1UL << ETM_TRCSSCSR0_PC_Pos) /*!< Bit mask of PC field. */
5349 #define ETM_TRCSSCSR0_PC_False (0x0UL) /*!< Process counter value comparisons not supported. */
5350 #define ETM_TRCSSCSR0_PC_True (0x1UL) /*!< Process counter value comparisons supported. */
5351 
5352 /* Bit 2 : Data value comparator support */
5353 #define ETM_TRCSSCSR0_DV_Pos (2UL) /*!< Position of DV field. */
5354 #define ETM_TRCSSCSR0_DV_Msk (0x1UL << ETM_TRCSSCSR0_DV_Pos) /*!< Bit mask of DV field. */
5355 #define ETM_TRCSSCSR0_DV_False (0x0UL) /*!< Data value comparisons not supported. */
5356 #define ETM_TRCSSCSR0_DV_True (0x1UL) /*!< Data value comparisons supported. */
5357 
5358 /* Bit 1 : Data address comparator support */
5359 #define ETM_TRCSSCSR0_DA_Pos (1UL) /*!< Position of DA field. */
5360 #define ETM_TRCSSCSR0_DA_Msk (0x1UL << ETM_TRCSSCSR0_DA_Pos) /*!< Bit mask of DA field. */
5361 #define ETM_TRCSSCSR0_DA_False (0x0UL) /*!< Data address comparisons not supported. */
5362 #define ETM_TRCSSCSR0_DA_True (0x1UL) /*!< Data address comparisons supported. */
5363 
5364 /* Bit 0 : Instruction address comparator support */
5365 #define ETM_TRCSSCSR0_INST_Pos (0UL) /*!< Position of INST field. */
5366 #define ETM_TRCSSCSR0_INST_Msk (0x1UL << ETM_TRCSSCSR0_INST_Pos) /*!< Bit mask of INST field. */
5367 #define ETM_TRCSSCSR0_INST_False (0x0UL) /*!< Single-shot instruction address comparisons not supported. */
5368 #define ETM_TRCSSCSR0_INST_True (0x1UL) /*!< Single-shot instruction address comparisons supported. */
5369 
5370 /* Register: ETM_TRCSSPCICR0 */
5371 /* Description: Selects the processor comparator inputs for Single-shot control. */
5372 
5373 /* Bit 3 : Selects processor comparator 3 inputs for Single-shot control */
5374 #define ETM_TRCSSPCICR0_PC_3_Pos (3UL) /*!< Position of PC_3 field. */
5375 #define ETM_TRCSSPCICR0_PC_3_Msk (0x1UL << ETM_TRCSSPCICR0_PC_3_Pos) /*!< Bit mask of PC_3 field. */
5376 #define ETM_TRCSSPCICR0_PC_3_Disabled (0x0UL) /*!< Processor comparator 3 is not selected for Single-shot control. */
5377 #define ETM_TRCSSPCICR0_PC_3_Enabled (0x1UL) /*!< Processor comparator 3 is selected for Single-shot control. */
5378 
5379 /* Bit 2 : Selects processor comparator 2 inputs for Single-shot control */
5380 #define ETM_TRCSSPCICR0_PC_2_Pos (2UL) /*!< Position of PC_2 field. */
5381 #define ETM_TRCSSPCICR0_PC_2_Msk (0x1UL << ETM_TRCSSPCICR0_PC_2_Pos) /*!< Bit mask of PC_2 field. */
5382 #define ETM_TRCSSPCICR0_PC_2_Disabled (0x0UL) /*!< Processor comparator 2 is not selected for Single-shot control. */
5383 #define ETM_TRCSSPCICR0_PC_2_Enabled (0x1UL) /*!< Processor comparator 2 is selected for Single-shot control. */
5384 
5385 /* Bit 1 : Selects processor comparator 1 inputs for Single-shot control */
5386 #define ETM_TRCSSPCICR0_PC_1_Pos (1UL) /*!< Position of PC_1 field. */
5387 #define ETM_TRCSSPCICR0_PC_1_Msk (0x1UL << ETM_TRCSSPCICR0_PC_1_Pos) /*!< Bit mask of PC_1 field. */
5388 #define ETM_TRCSSPCICR0_PC_1_Disabled (0x0UL) /*!< Processor comparator 1 is not selected for Single-shot control. */
5389 #define ETM_TRCSSPCICR0_PC_1_Enabled (0x1UL) /*!< Processor comparator 1 is selected for Single-shot control. */
5390 
5391 /* Bit 0 : Selects processor comparator 0 inputs for Single-shot control */
5392 #define ETM_TRCSSPCICR0_PC_0_Pos (0UL) /*!< Position of PC_0 field. */
5393 #define ETM_TRCSSPCICR0_PC_0_Msk (0x1UL << ETM_TRCSSPCICR0_PC_0_Pos) /*!< Bit mask of PC_0 field. */
5394 #define ETM_TRCSSPCICR0_PC_0_Disabled (0x0UL) /*!< Processor comparator 0 is not selected for Single-shot control. */
5395 #define ETM_TRCSSPCICR0_PC_0_Enabled (0x1UL) /*!< Processor comparator 0 is selected for Single-shot control. */
5396 
5397 /* Register: ETM_TRCPDCR */
5398 /* Description: Controls the single-shot comparator. */
5399 
5400 /* Bit 24 : Power up request, to request that power to ETM and access to the trace registers is maintained. */
5401 #define ETM_TRCPDCR_PU_Pos (24UL) /*!< Position of PU field. */
5402 #define ETM_TRCPDCR_PU_Msk (0x1UL << ETM_TRCPDCR_PU_Pos) /*!< Bit mask of PU field. */
5403 #define ETM_TRCPDCR_PU_Disabled (0x0UL) /*!< Power not requested. */
5404 #define ETM_TRCPDCR_PU_Enabled (0x1UL) /*!< Power requested. */
5405 
5406 /* Register: ETM_TRCPDSR */
5407 /* Description: Indicates the power down status of the ETM. */
5408 
5409 /* Bit 1 : Sticky power down state. This bit is set to 1 when power to the ETM registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR */
5410 #define ETM_TRCPDSR_STICKYPD_Pos (1UL) /*!< Position of STICKYPD field. */
5411 #define ETM_TRCPDSR_STICKYPD_Msk (0x1UL << ETM_TRCPDSR_STICKYPD_Pos) /*!< Bit mask of STICKYPD field. */
5412 #define ETM_TRCPDSR_STICKYPD_NotPoweredDown (0x0UL) /*!< Trace register power has not been removed since the TRCPDSR was last read. */
5413 #define ETM_TRCPDSR_STICKYPD_PoweredDown (0x1UL) /*!< Trace register power has been removed since the TRCPDSR was last read. */
5414 
5415 /* Bit 0 : Indicates ETM is powered up */
5416 #define ETM_TRCPDSR_POWER_Pos (0UL) /*!< Position of POWER field. */
5417 #define ETM_TRCPDSR_POWER_Msk (0x1UL << ETM_TRCPDSR_POWER_Pos) /*!< Bit mask of POWER field. */
5418 #define ETM_TRCPDSR_POWER_NotPoweredUp (0x0UL) /*!< ETM is not powered up. All registers are not accessible. */
5419 #define ETM_TRCPDSR_POWER_PoweredUp (0x1UL) /*!< ETM is powered up. All registers are accessible. */
5420 
5421 /* Register: ETM_TRCITATBIDR */
5422 /* Description: Sets the state of output pins. */
5423 
5424 /* Bit 6 : Drives the ATIDMI[6] output pin. */
5425 #define ETM_TRCITATBIDR_ID_6_Pos (6UL) /*!< Position of ID_6 field. */
5426 #define ETM_TRCITATBIDR_ID_6_Msk (0x1UL << ETM_TRCITATBIDR_ID_6_Pos) /*!< Bit mask of ID_6 field. */
5427 
5428 /* Bit 5 : Drives the ATIDMI[5] output pin. */
5429 #define ETM_TRCITATBIDR_ID_5_Pos (5UL) /*!< Position of ID_5 field. */
5430 #define ETM_TRCITATBIDR_ID_5_Msk (0x1UL << ETM_TRCITATBIDR_ID_5_Pos) /*!< Bit mask of ID_5 field. */
5431 
5432 /* Bit 4 : Drives the ATIDMI[4] output pin. */
5433 #define ETM_TRCITATBIDR_ID_4_Pos (4UL) /*!< Position of ID_4 field. */
5434 #define ETM_TRCITATBIDR_ID_4_Msk (0x1UL << ETM_TRCITATBIDR_ID_4_Pos) /*!< Bit mask of ID_4 field. */
5435 
5436 /* Bit 3 : Drives the ATIDMI[3] output pin. */
5437 #define ETM_TRCITATBIDR_ID_3_Pos (3UL) /*!< Position of ID_3 field. */
5438 #define ETM_TRCITATBIDR_ID_3_Msk (0x1UL << ETM_TRCITATBIDR_ID_3_Pos) /*!< Bit mask of ID_3 field. */
5439 
5440 /* Bit 2 : Drives the ATIDMI[2] output pin. */
5441 #define ETM_TRCITATBIDR_ID_2_Pos (2UL) /*!< Position of ID_2 field. */
5442 #define ETM_TRCITATBIDR_ID_2_Msk (0x1UL << ETM_TRCITATBIDR_ID_2_Pos) /*!< Bit mask of ID_2 field. */
5443 
5444 /* Bit 1 : Drives the ATIDMI[1] output pin. */
5445 #define ETM_TRCITATBIDR_ID_1_Pos (1UL) /*!< Position of ID_1 field. */
5446 #define ETM_TRCITATBIDR_ID_1_Msk (0x1UL << ETM_TRCITATBIDR_ID_1_Pos) /*!< Bit mask of ID_1 field. */
5447 
5448 /* Bit 0 : Drives the ATIDMI[0] output pin. */
5449 #define ETM_TRCITATBIDR_ID_0_Pos (0UL) /*!< Position of ID_0 field. */
5450 #define ETM_TRCITATBIDR_ID_0_Msk (0x1UL << ETM_TRCITATBIDR_ID_0_Pos) /*!< Bit mask of ID_0 field. */
5451 
5452 /* Register: ETM_TRCITIATBINR */
5453 /* Description: Reads the state of the input pins. */
5454 
5455 /* Bit 1 : Returns the value of the AFREADYMI input pin. */
5456 #define ETM_TRCITIATBINR_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */
5457 #define ETM_TRCITIATBINR_AFREADY_Msk (0x1UL << ETM_TRCITIATBINR_AFREADY_Pos) /*!< Bit mask of AFREADY field. */
5458 
5459 /* Bit 0 : Returns the value of the ATVALIDMI input pin. */
5460 #define ETM_TRCITIATBINR_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */
5461 #define ETM_TRCITIATBINR_ATVALID_Msk (0x1UL << ETM_TRCITIATBINR_ATVALID_Pos) /*!< Bit mask of ATVALID field. */
5462 
5463 /* Register: ETM_TRCITIATBOUTR */
5464 /* Description: Sets the state of the output pins. */
5465 
5466 /* Bit 1 : Drives the AFREADYMI output pin. */
5467 #define ETM_TRCITIATBOUTR_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */
5468 #define ETM_TRCITIATBOUTR_AFREADY_Msk (0x1UL << ETM_TRCITIATBOUTR_AFREADY_Pos) /*!< Bit mask of AFREADY field. */
5469 
5470 /* Bit 0 : Drives the ATVALIDMI output pin. */
5471 #define ETM_TRCITIATBOUTR_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */
5472 #define ETM_TRCITIATBOUTR_ATVALID_Msk (0x1UL << ETM_TRCITIATBOUTR_ATVALID_Pos) /*!< Bit mask of ATVALID field. */
5473 
5474 /* Register: ETM_TRCITCTRL */
5475 /* Description: Enables topology detection or integration testing, by putting ETM-M33 into integration mode. */
5476 
5477 /* Bit 0 : Integration mode enable */
5478 #define ETM_TRCITCTRL_IME_Pos (0UL) /*!< Position of IME field. */
5479 #define ETM_TRCITCTRL_IME_Msk (0x1UL << ETM_TRCITCTRL_IME_Pos) /*!< Bit mask of IME field. */
5480 #define ETM_TRCITCTRL_IME_Disabled (0x0UL) /*!< ETM is not in integration mode. */
5481 #define ETM_TRCITCTRL_IME_Enabled (0x1UL) /*!< ETM is in integration mode. */
5482 
5483 /* Register: ETM_TRCCLAIMSET */
5484 /* Description: Sets bits in the claim tag and determines the number of claim tag bits implemented. */
5485 
5486 /* Bit 3 : Claim tag set register */
5487 #define ETM_TRCCLAIMSET_SET_3_Pos (3UL) /*!< Position of SET_3 field. */
5488 #define ETM_TRCCLAIMSET_SET_3_Msk (0x1UL << ETM_TRCCLAIMSET_SET_3_Pos) /*!< Bit mask of SET_3 field. */
5489 #define ETM_TRCCLAIMSET_SET_3_NotSet (0x0UL) /*!< Claim tag 3 is not set. */
5490 #define ETM_TRCCLAIMSET_SET_3_Set (0x1UL) /*!< Claim tag 3 is set. */
5491 #define ETM_TRCCLAIMSET_SET_3_Claim (0x1UL) /*!< Set claim tag 3. */
5492 
5493 /* Bit 2 : Claim tag set register */
5494 #define ETM_TRCCLAIMSET_SET_2_Pos (2UL) /*!< Position of SET_2 field. */
5495 #define ETM_TRCCLAIMSET_SET_2_Msk (0x1UL << ETM_TRCCLAIMSET_SET_2_Pos) /*!< Bit mask of SET_2 field. */
5496 #define ETM_TRCCLAIMSET_SET_2_NotSet (0x0UL) /*!< Claim tag 2 is not set. */
5497 #define ETM_TRCCLAIMSET_SET_2_Set (0x1UL) /*!< Claim tag 2 is set. */
5498 #define ETM_TRCCLAIMSET_SET_2_Claim (0x1UL) /*!< Set claim tag 2. */
5499 
5500 /* Bit 1 : Claim tag set register */
5501 #define ETM_TRCCLAIMSET_SET_1_Pos (1UL) /*!< Position of SET_1 field. */
5502 #define ETM_TRCCLAIMSET_SET_1_Msk (0x1UL << ETM_TRCCLAIMSET_SET_1_Pos) /*!< Bit mask of SET_1 field. */
5503 #define ETM_TRCCLAIMSET_SET_1_NotSet (0x0UL) /*!< Claim tag 1 is not set. */
5504 #define ETM_TRCCLAIMSET_SET_1_Set (0x1UL) /*!< Claim tag 1 is set. */
5505 #define ETM_TRCCLAIMSET_SET_1_Claim (0x1UL) /*!< Set claim tag 1. */
5506 
5507 /* Bit 0 : Claim tag set register */
5508 #define ETM_TRCCLAIMSET_SET_0_Pos (0UL) /*!< Position of SET_0 field. */
5509 #define ETM_TRCCLAIMSET_SET_0_Msk (0x1UL << ETM_TRCCLAIMSET_SET_0_Pos) /*!< Bit mask of SET_0 field. */
5510 #define ETM_TRCCLAIMSET_SET_0_NotSet (0x0UL) /*!< Claim tag 0 is not set. */
5511 #define ETM_TRCCLAIMSET_SET_0_Set (0x1UL) /*!< Claim tag 0 is set. */
5512 #define ETM_TRCCLAIMSET_SET_0_Claim (0x1UL) /*!< Set claim tag 0. */
5513 
5514 /* Register: ETM_TRCCLAIMCLR */
5515 /* Description: Clears bits in the claim tag and determines the current value of the claim tag. */
5516 
5517 /* Bit 3 : Claim tag clear register */
5518 #define ETM_TRCCLAIMCLR_CLR_3_Pos (3UL) /*!< Position of CLR_3 field. */
5519 #define ETM_TRCCLAIMCLR_CLR_3_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR_3_Pos) /*!< Bit mask of CLR_3 field. */
5520 #define ETM_TRCCLAIMCLR_CLR_3_NotSet (0x0UL) /*!< Claim tag 3 is not set. */
5521 #define ETM_TRCCLAIMCLR_CLR_3_Set (0x1UL) /*!< Claim tag 3 is set. */
5522 #define ETM_TRCCLAIMCLR_CLR_3_Clear (0x1UL) /*!< Clear claim tag 3. */
5523 
5524 /* Bit 2 : Claim tag clear register */
5525 #define ETM_TRCCLAIMCLR_CLR_2_Pos (2UL) /*!< Position of CLR_2 field. */
5526 #define ETM_TRCCLAIMCLR_CLR_2_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR_2_Pos) /*!< Bit mask of CLR_2 field. */
5527 #define ETM_TRCCLAIMCLR_CLR_2_NotSet (0x0UL) /*!< Claim tag 2 is not set. */
5528 #define ETM_TRCCLAIMCLR_CLR_2_Set (0x1UL) /*!< Claim tag 2 is set. */
5529 #define ETM_TRCCLAIMCLR_CLR_2_Clear (0x1UL) /*!< Clear claim tag 2. */
5530 
5531 /* Bit 1 : Claim tag clear register */
5532 #define ETM_TRCCLAIMCLR_CLR_1_Pos (1UL) /*!< Position of CLR_1 field. */
5533 #define ETM_TRCCLAIMCLR_CLR_1_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR_1_Pos) /*!< Bit mask of CLR_1 field. */
5534 #define ETM_TRCCLAIMCLR_CLR_1_NotSet (0x0UL) /*!< Claim tag 1 is not set. */
5535 #define ETM_TRCCLAIMCLR_CLR_1_Set (0x1UL) /*!< Claim tag 1 is set. */
5536 #define ETM_TRCCLAIMCLR_CLR_1_Clear (0x1UL) /*!< Clear claim tag 1. */
5537 
5538 /* Bit 0 : Claim tag clear register */
5539 #define ETM_TRCCLAIMCLR_CLR_0_Pos (0UL) /*!< Position of CLR_0 field. */
5540 #define ETM_TRCCLAIMCLR_CLR_0_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR_0_Pos) /*!< Bit mask of CLR_0 field. */
5541 #define ETM_TRCCLAIMCLR_CLR_0_NotSet (0x0UL) /*!< Claim tag 0 is not set. */
5542 #define ETM_TRCCLAIMCLR_CLR_0_Set (0x1UL) /*!< Claim tag 0 is set. */
5543 #define ETM_TRCCLAIMCLR_CLR_0_Clear (0x1UL) /*!< Clear claim tag 0. */
5544 
5545 /* Register: ETM_TRCAUTHSTATUS */
5546 /* Description: Indicates the current level of tracing permitted by the system */
5547 
5548 /* Bits 7..6 : Secure Non-Invasive Debug */
5549 #define ETM_TRCAUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */
5550 #define ETM_TRCAUTHSTATUS_SNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */
5551 #define ETM_TRCAUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
5552 #define ETM_TRCAUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */
5553 
5554 /* Bits 5..4 : Secure Invasive Debug */
5555 #define ETM_TRCAUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */
5556 #define ETM_TRCAUTHSTATUS_SID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */
5557 #define ETM_TRCAUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
5558 #define ETM_TRCAUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */
5559 
5560 /* Bits 3..2 : Non-secure Non-Invasive Debug */
5561 #define ETM_TRCAUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */
5562 #define ETM_TRCAUTHSTATUS_NSNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */
5563 #define ETM_TRCAUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
5564 #define ETM_TRCAUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */
5565 
5566 /* Bits 1..0 : Non-secure Invasive Debug */
5567 #define ETM_TRCAUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */
5568 #define ETM_TRCAUTHSTATUS_NSID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */
5569 #define ETM_TRCAUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
5570 #define ETM_TRCAUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */
5571 
5572 /* Register: ETM_TRCDEVARCH */
5573 /* Description: The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component */
5574 
5575 /* Bits 31..21 : Defines the architect of the component */
5576 #define ETM_TRCDEVARCH_ARCHITECT_Pos (21UL) /*!< Position of ARCHITECT field. */
5577 #define ETM_TRCDEVARCH_ARCHITECT_Msk (0x7FFUL << ETM_TRCDEVARCH_ARCHITECT_Pos) /*!< Bit mask of ARCHITECT field. */
5578 #define ETM_TRCDEVARCH_ARCHITECT_Arm (0x23BUL) /*!< This peripheral was architected by Arm. */
5579 
5580 /* Bit 20 : This register is implemented */
5581 #define ETM_TRCDEVARCH_PRESENT_Pos (20UL) /*!< Position of PRESENT field. */
5582 #define ETM_TRCDEVARCH_PRESENT_Msk (0x1UL << ETM_TRCDEVARCH_PRESENT_Pos) /*!< Bit mask of PRESENT field. */
5583 #define ETM_TRCDEVARCH_PRESENT_Absent (0x0UL) /*!< The register is not implemented. */
5584 #define ETM_TRCDEVARCH_PRESENT_Present (0x1UL) /*!< The register is implemented. */
5585 
5586 /* Bits 19..16 : Architecture revision */
5587 #define ETM_TRCDEVARCH_REVISION_Pos (16UL) /*!< Position of REVISION field. */
5588 #define ETM_TRCDEVARCH_REVISION_Msk (0xFUL << ETM_TRCDEVARCH_REVISION_Pos) /*!< Bit mask of REVISION field. */
5589 #define ETM_TRCDEVARCH_REVISION_v2 (0x2UL) /*!< Component is part of architecture 4.2 */
5590 
5591 /* Bits 15..0 : Architecture ID */
5592 #define ETM_TRCDEVARCH_ARCHID_Pos (0UL) /*!< Position of ARCHID field. */
5593 #define ETM_TRCDEVARCH_ARCHID_Msk (0xFFFFUL << ETM_TRCDEVARCH_ARCHID_Pos) /*!< Bit mask of ARCHID field. */
5594 #define ETM_TRCDEVARCH_ARCHID_ETMv42 (0x4A13UL) /*!< Component is an ETMv4 component */
5595 
5596 /* Register: ETM_TRCDEVTYPE */
5597 /* Description: Controls the single-shot comparator. */
5598 
5599 /* Bits 7..4 : The sub-type of the component */
5600 #define ETM_TRCDEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */
5601 #define ETM_TRCDEVTYPE_SUB_Msk (0xFUL << ETM_TRCDEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */
5602 #define ETM_TRCDEVTYPE_SUB_ProcessorTrace (0x1UL) /*!< Peripheral is a processor trace source. */
5603 
5604 /* Bits 3..0 : The main type of the component */
5605 #define ETM_TRCDEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */
5606 #define ETM_TRCDEVTYPE_MAJOR_Msk (0xFUL << ETM_TRCDEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */
5607 #define ETM_TRCDEVTYPE_MAJOR_TraceSource (0x3UL) /*!< Peripheral is a trace source. */
5608 
5609 
5610 /* Peripheral: FICR */
5611 /* Description: Factory Information Configuration Registers */
5612 
5613 /* Register: FICR_INFO_DEVICEID */
5614 /* Description: Description collection: Device identifier */
5615 
5616 /* Bits 31..0 : 64 bit unique device identifier */
5617 #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
5618 #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
5619 
5620 /* Register: FICR_INFO_PART */
5621 /* Description: Part code */
5622 
5623 /* Bits 31..0 : Part code */
5624 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
5625 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
5626 #define FICR_INFO_PART_PART_N9120 (0x00009120UL) /*!< nRF9120 */
5627 #define FICR_INFO_PART_PART_N9131 (0x00009131UL) /*!< nRF9131 */
5628 #define FICR_INFO_PART_PART_N9151 (0x00009151UL) /*!< nRF9151 */
5629 #define FICR_INFO_PART_PART_N9160 (0x00009160UL) /*!< nRF9160 */
5630 #define FICR_INFO_PART_PART_N9161 (0x00009161UL) /*!< nRF9161 */
5631 
5632 /* Register: FICR_INFO_VARIANT */
5633 /* Description: Part Variant, Hardware version and Production configuration */
5634 
5635 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
5636 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
5637 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
5638 #define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */
5639 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
5640 #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
5641 #define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */
5642 
5643 /* Register: FICR_INFO_PACKAGE */
5644 /* Description: Package option */
5645 
5646 /* Bits 31..0 : Package option */
5647 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
5648 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
5649 #define FICR_INFO_PACKAGE_PACKAGE_CECF (0x00002002UL) /*!< CExx or CFxx - 236 ball WLCSP */
5650 
5651 /* Register: FICR_INFO_RAM */
5652 /* Description: RAM variant */
5653 
5654 /* Bits 31..0 : RAM variant */
5655 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
5656 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
5657 #define FICR_INFO_RAM_RAM_K256 (0x00000100UL) /*!< 256  kByte RAM */
5658 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
5659 
5660 /* Register: FICR_INFO_FLASH */
5661 /* Description: Flash variant */
5662 
5663 /* Bits 31..0 : Flash variant */
5664 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
5665 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
5666 #define FICR_INFO_FLASH_FLASH_K1024 (0x00000400UL) /*!< 1 MByte FLASH */
5667 
5668 /* Register: FICR_INFO_CODEPAGESIZE */
5669 /* Description: Code memory page size */
5670 
5671 /* Bits 31..0 : Code memory page size */
5672 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
5673 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
5674 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x00001000UL) /*!< 4  kByte */
5675 
5676 /* Register: FICR_INFO_CODESIZE */
5677 /* Description: Code memory size */
5678 
5679 /* Bits 31..0 : Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE */
5680 #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
5681 #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
5682 #define FICR_INFO_CODESIZE_CODESIZE_P256 (0x00000100UL) /*!< 256 pages */
5683 
5684 /* Register: FICR_INFO_DEVICETYPE */
5685 /* Description: Device type */
5686 
5687 /* Bits 31..0 : Device type */
5688 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */
5689 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */
5690 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x00000000UL) /*!< Device is an physical DIE */
5691 #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */
5692 
5693 /* Register: FICR_TRIMCNF_ADDR */
5694 /* Description: Description cluster: Address */
5695 
5696 /* Bits 31..0 : Address */
5697 #define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */
5698 #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */
5699 
5700 /* Register: FICR_TRIMCNF_DATA */
5701 /* Description: Description cluster: Data */
5702 
5703 /* Bits 31..0 : Data */
5704 #define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */
5705 #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */
5706 
5707 /* Register: FICR_TRNG90B_BYTES */
5708 /* Description: Amount of bytes for the required entropy bits */
5709 
5710 /* Bits 31..0 : Amount of bytes for the required entropy bits */
5711 #define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */
5712 #define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */
5713 
5714 /* Register: FICR_TRNG90B_RCCUTOFF */
5715 /* Description: Repetition counter cutoff */
5716 
5717 /* Bits 31..0 : Repetition counter cutoff */
5718 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */
5719 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */
5720 
5721 /* Register: FICR_TRNG90B_APCUTOFF */
5722 /* Description: Adaptive proportion cutoff */
5723 
5724 /* Bits 31..0 : Adaptive proportion cutoff */
5725 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */
5726 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */
5727 
5728 /* Register: FICR_TRNG90B_STARTUP */
5729 /* Description: Amount of bytes for the startup tests */
5730 
5731 /* Bits 31..0 : Amount of bytes for the startup tests */
5732 #define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */
5733 #define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */
5734 
5735 /* Register: FICR_TRNG90B_ROSC1 */
5736 /* Description: Sample count for ring oscillator configuration 1 */
5737 
5738 /* Bits 31..0 : Sample count for ring oscillator configuration 1 */
5739 #define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
5740 #define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */
5741 
5742 /* Register: FICR_TRNG90B_ROSC2 */
5743 /* Description: Sample count for ring oscillator configuration 2 */
5744 
5745 /* Bits 31..0 : Sample count for ring oscillator configuration 2 */
5746 #define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */
5747 #define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */
5748 
5749 /* Register: FICR_TRNG90B_ROSC3 */
5750 /* Description: Sample count for ring oscillator configuration 3 */
5751 
5752 /* Bits 31..0 : Sample count for ring oscillator configuration 3 */
5753 #define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */
5754 #define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */
5755 
5756 /* Register: FICR_TRNG90B_ROSC4 */
5757 /* Description: Sample count for ring oscillator configuration 4 */
5758 
5759 /* Bits 31..0 : Sample count for ring oscillator configuration 4 */
5760 #define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */
5761 #define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */
5762 
5763 
5764 /* Peripheral: GPIOTE */
5765 /* Description: GPIO Tasks and Events 0 */
5766 
5767 /* Register: GPIOTE_TASKS_OUT */
5768 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
5769 
5770 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
5771 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
5772 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
5773 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (0x1UL) /*!< Trigger task */
5774 
5775 /* Register: GPIOTE_TASKS_SET */
5776 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
5777 
5778 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
5779 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
5780 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
5781 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (0x1UL) /*!< Trigger task */
5782 
5783 /* Register: GPIOTE_TASKS_CLR */
5784 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
5785 
5786 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
5787 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
5788 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
5789 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (0x1UL) /*!< Trigger task */
5790 
5791 /* Register: GPIOTE_SUBSCRIBE_OUT */
5792 /* Description: Description collection: Subscribe configuration for task OUT[n] */
5793 
5794 /* Bit 31 :   */
5795 #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */
5796 #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */
5797 #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0x0UL) /*!< Disable subscription */
5798 #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (0x1UL) /*!< Enable subscription */
5799 
5800 /* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */
5801 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5802 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5803 
5804 /* Register: GPIOTE_SUBSCRIBE_SET */
5805 /* Description: Description collection: Subscribe configuration for task SET[n] */
5806 
5807 /* Bit 31 :   */
5808 #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */
5809 #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */
5810 #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0x0UL) /*!< Disable subscription */
5811 #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (0x1UL) /*!< Enable subscription */
5812 
5813 /* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */
5814 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5815 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5816 
5817 /* Register: GPIOTE_SUBSCRIBE_CLR */
5818 /* Description: Description collection: Subscribe configuration for task CLR[n] */
5819 
5820 /* Bit 31 :   */
5821 #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */
5822 #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */
5823 #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0x0UL) /*!< Disable subscription */
5824 #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (0x1UL) /*!< Enable subscription */
5825 
5826 /* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */
5827 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5828 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5829 
5830 /* Register: GPIOTE_EVENTS_IN */
5831 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
5832 
5833 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
5834 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
5835 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
5836 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0x0UL) /*!< Event not generated */
5837 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (0x1UL) /*!< Event generated */
5838 
5839 /* Register: GPIOTE_EVENTS_PORT */
5840 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
5841 
5842 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
5843 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
5844 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
5845 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0x0UL) /*!< Event not generated */
5846 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (0x1UL) /*!< Event generated */
5847 
5848 /* Register: GPIOTE_PUBLISH_IN */
5849 /* Description: Description collection: Publish configuration for event IN[n] */
5850 
5851 /* Bit 31 :   */
5852 #define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */
5853 #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */
5854 #define GPIOTE_PUBLISH_IN_EN_Disabled (0x0UL) /*!< Disable publishing */
5855 #define GPIOTE_PUBLISH_IN_EN_Enabled (0x1UL) /*!< Enable publishing */
5856 
5857 /* Bits 7..0 : DPPI channel that event IN[n] will publish to */
5858 #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5859 #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5860 
5861 /* Register: GPIOTE_PUBLISH_PORT */
5862 /* Description: Publish configuration for event PORT */
5863 
5864 /* Bit 31 :   */
5865 #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */
5866 #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */
5867 #define GPIOTE_PUBLISH_PORT_EN_Disabled (0x0UL) /*!< Disable publishing */
5868 #define GPIOTE_PUBLISH_PORT_EN_Enabled (0x1UL) /*!< Enable publishing */
5869 
5870 /* Bits 7..0 : DPPI channel that event PORT will publish to */
5871 #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5872 #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5873 
5874 /* Register: GPIOTE_INTENSET */
5875 /* Description: Enable interrupt */
5876 
5877 /* Bit 31 : Write '1' to enable interrupt for event PORT */
5878 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
5879 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
5880 #define GPIOTE_INTENSET_PORT_Disabled (0x0UL) /*!< Read: Disabled */
5881 #define GPIOTE_INTENSET_PORT_Enabled (0x1UL) /*!< Read: Enabled */
5882 #define GPIOTE_INTENSET_PORT_Set (0x1UL) /*!< Enable */
5883 
5884 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
5885 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
5886 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
5887 #define GPIOTE_INTENSET_IN7_Disabled (0x0UL) /*!< Read: Disabled */
5888 #define GPIOTE_INTENSET_IN7_Enabled (0x1UL) /*!< Read: Enabled */
5889 #define GPIOTE_INTENSET_IN7_Set (0x1UL) /*!< Enable */
5890 
5891 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
5892 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
5893 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
5894 #define GPIOTE_INTENSET_IN6_Disabled (0x0UL) /*!< Read: Disabled */
5895 #define GPIOTE_INTENSET_IN6_Enabled (0x1UL) /*!< Read: Enabled */
5896 #define GPIOTE_INTENSET_IN6_Set (0x1UL) /*!< Enable */
5897 
5898 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
5899 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
5900 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
5901 #define GPIOTE_INTENSET_IN5_Disabled (0x0UL) /*!< Read: Disabled */
5902 #define GPIOTE_INTENSET_IN5_Enabled (0x1UL) /*!< Read: Enabled */
5903 #define GPIOTE_INTENSET_IN5_Set (0x1UL) /*!< Enable */
5904 
5905 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
5906 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
5907 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
5908 #define GPIOTE_INTENSET_IN4_Disabled (0x0UL) /*!< Read: Disabled */
5909 #define GPIOTE_INTENSET_IN4_Enabled (0x1UL) /*!< Read: Enabled */
5910 #define GPIOTE_INTENSET_IN4_Set (0x1UL) /*!< Enable */
5911 
5912 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
5913 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
5914 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
5915 #define GPIOTE_INTENSET_IN3_Disabled (0x0UL) /*!< Read: Disabled */
5916 #define GPIOTE_INTENSET_IN3_Enabled (0x1UL) /*!< Read: Enabled */
5917 #define GPIOTE_INTENSET_IN3_Set (0x1UL) /*!< Enable */
5918 
5919 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
5920 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
5921 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
5922 #define GPIOTE_INTENSET_IN2_Disabled (0x0UL) /*!< Read: Disabled */
5923 #define GPIOTE_INTENSET_IN2_Enabled (0x1UL) /*!< Read: Enabled */
5924 #define GPIOTE_INTENSET_IN2_Set (0x1UL) /*!< Enable */
5925 
5926 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
5927 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
5928 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
5929 #define GPIOTE_INTENSET_IN1_Disabled (0x0UL) /*!< Read: Disabled */
5930 #define GPIOTE_INTENSET_IN1_Enabled (0x1UL) /*!< Read: Enabled */
5931 #define GPIOTE_INTENSET_IN1_Set (0x1UL) /*!< Enable */
5932 
5933 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
5934 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
5935 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
5936 #define GPIOTE_INTENSET_IN0_Disabled (0x0UL) /*!< Read: Disabled */
5937 #define GPIOTE_INTENSET_IN0_Enabled (0x1UL) /*!< Read: Enabled */
5938 #define GPIOTE_INTENSET_IN0_Set (0x1UL) /*!< Enable */
5939 
5940 /* Register: GPIOTE_INTENCLR */
5941 /* Description: Disable interrupt */
5942 
5943 /* Bit 31 : Write '1' to disable interrupt for event PORT */
5944 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
5945 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
5946 #define GPIOTE_INTENCLR_PORT_Disabled (0x0UL) /*!< Read: Disabled */
5947 #define GPIOTE_INTENCLR_PORT_Enabled (0x1UL) /*!< Read: Enabled */
5948 #define GPIOTE_INTENCLR_PORT_Clear (0x1UL) /*!< Disable */
5949 
5950 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
5951 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
5952 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
5953 #define GPIOTE_INTENCLR_IN7_Disabled (0x0UL) /*!< Read: Disabled */
5954 #define GPIOTE_INTENCLR_IN7_Enabled (0x1UL) /*!< Read: Enabled */
5955 #define GPIOTE_INTENCLR_IN7_Clear (0x1UL) /*!< Disable */
5956 
5957 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
5958 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
5959 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
5960 #define GPIOTE_INTENCLR_IN6_Disabled (0x0UL) /*!< Read: Disabled */
5961 #define GPIOTE_INTENCLR_IN6_Enabled (0x1UL) /*!< Read: Enabled */
5962 #define GPIOTE_INTENCLR_IN6_Clear (0x1UL) /*!< Disable */
5963 
5964 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
5965 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
5966 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
5967 #define GPIOTE_INTENCLR_IN5_Disabled (0x0UL) /*!< Read: Disabled */
5968 #define GPIOTE_INTENCLR_IN5_Enabled (0x1UL) /*!< Read: Enabled */
5969 #define GPIOTE_INTENCLR_IN5_Clear (0x1UL) /*!< Disable */
5970 
5971 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
5972 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
5973 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
5974 #define GPIOTE_INTENCLR_IN4_Disabled (0x0UL) /*!< Read: Disabled */
5975 #define GPIOTE_INTENCLR_IN4_Enabled (0x1UL) /*!< Read: Enabled */
5976 #define GPIOTE_INTENCLR_IN4_Clear (0x1UL) /*!< Disable */
5977 
5978 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
5979 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
5980 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
5981 #define GPIOTE_INTENCLR_IN3_Disabled (0x0UL) /*!< Read: Disabled */
5982 #define GPIOTE_INTENCLR_IN3_Enabled (0x1UL) /*!< Read: Enabled */
5983 #define GPIOTE_INTENCLR_IN3_Clear (0x1UL) /*!< Disable */
5984 
5985 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
5986 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
5987 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
5988 #define GPIOTE_INTENCLR_IN2_Disabled (0x0UL) /*!< Read: Disabled */
5989 #define GPIOTE_INTENCLR_IN2_Enabled (0x1UL) /*!< Read: Enabled */
5990 #define GPIOTE_INTENCLR_IN2_Clear (0x1UL) /*!< Disable */
5991 
5992 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
5993 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
5994 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
5995 #define GPIOTE_INTENCLR_IN1_Disabled (0x0UL) /*!< Read: Disabled */
5996 #define GPIOTE_INTENCLR_IN1_Enabled (0x1UL) /*!< Read: Enabled */
5997 #define GPIOTE_INTENCLR_IN1_Clear (0x1UL) /*!< Disable */
5998 
5999 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
6000 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
6001 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
6002 #define GPIOTE_INTENCLR_IN0_Disabled (0x0UL) /*!< Read: Disabled */
6003 #define GPIOTE_INTENCLR_IN0_Enabled (0x1UL) /*!< Read: Enabled */
6004 #define GPIOTE_INTENCLR_IN0_Clear (0x1UL) /*!< Disable */
6005 
6006 /* Register: GPIOTE_CONFIG */
6007 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
6008 
6009 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
6010 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
6011 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
6012 #define GPIOTE_CONFIG_OUTINIT_Low (0x0UL) /*!< Task mode: Initial value of pin before task triggering is low */
6013 #define GPIOTE_CONFIG_OUTINIT_High (0x1UL) /*!< Task mode: Initial value of pin before task triggering is high */
6014 
6015 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
6016 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
6017 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
6018 #define GPIOTE_CONFIG_POLARITY_None (0x0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
6019 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
6020 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
6021 #define GPIOTE_CONFIG_POLARITY_Toggle (0x3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
6022 
6023 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
6024 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
6025 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
6026 
6027 /* Bits 1..0 : Mode */
6028 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
6029 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
6030 #define GPIOTE_CONFIG_MODE_Disabled (0x0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
6031 #define GPIOTE_CONFIG_MODE_Event (0x1UL) /*!< Event mode */
6032 #define GPIOTE_CONFIG_MODE_Task (0x3UL) /*!< Task mode */
6033 
6034 
6035 /* Peripheral: I2S */
6036 /* Description: Inter-IC Sound 0 */
6037 
6038 /* Register: I2S_TASKS_START */
6039 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
6040 
6041 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
6042 #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6043 #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6044 #define I2S_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
6045 
6046 /* Register: I2S_TASKS_STOP */
6047 /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
6048 
6049 /* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
6050 #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6051 #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6052 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
6053 
6054 /* Register: I2S_SUBSCRIBE_START */
6055 /* Description: Subscribe configuration for task START */
6056 
6057 /* Bit 31 :   */
6058 #define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
6059 #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
6060 #define I2S_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
6061 #define I2S_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */
6062 
6063 /* Bits 7..0 : DPPI channel that task START will subscribe to */
6064 #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6065 #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6066 
6067 /* Register: I2S_SUBSCRIBE_STOP */
6068 /* Description: Subscribe configuration for task STOP */
6069 
6070 /* Bit 31 :   */
6071 #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
6072 #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
6073 #define I2S_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
6074 #define I2S_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */
6075 
6076 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
6077 #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6078 #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6079 
6080 /* Register: I2S_EVENTS_RXPTRUPD */
6081 /* Description: The RXD.PTR register has been copied to internal double-buffers.
6082       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
6083 
6084 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
6085       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
6086 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
6087 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
6088 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */
6089 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (0x1UL) /*!< Event generated */
6090 
6091 /* Register: I2S_EVENTS_STOPPED */
6092 /* Description: I2S transfer stopped. */
6093 
6094 /* Bit 0 : I2S transfer stopped. */
6095 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
6096 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
6097 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
6098 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
6099 
6100 /* Register: I2S_EVENTS_TXPTRUPD */
6101 /* Description: The TDX.PTR register has been copied to internal double-buffers.
6102       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
6103 
6104 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
6105       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
6106 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
6107 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
6108 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */
6109 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (0x1UL) /*!< Event generated */
6110 
6111 /* Register: I2S_PUBLISH_RXPTRUPD */
6112 /* Description: Publish configuration for event RXPTRUPD */
6113 
6114 /* Bit 31 :   */
6115 #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
6116 #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
6117 #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */
6118 #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */
6119 
6120 /* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to */
6121 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6122 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6123 
6124 /* Register: I2S_PUBLISH_STOPPED */
6125 /* Description: Publish configuration for event STOPPED */
6126 
6127 /* Bit 31 :   */
6128 #define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
6129 #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
6130 #define I2S_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
6131 #define I2S_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */
6132 
6133 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
6134 #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6135 #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6136 
6137 /* Register: I2S_PUBLISH_TXPTRUPD */
6138 /* Description: Publish configuration for event TXPTRUPD */
6139 
6140 /* Bit 31 :   */
6141 #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
6142 #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
6143 #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */
6144 #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */
6145 
6146 /* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to */
6147 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6148 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6149 
6150 /* Register: I2S_INTEN */
6151 /* Description: Enable or disable interrupt */
6152 
6153 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
6154 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
6155 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
6156 #define I2S_INTEN_TXPTRUPD_Disabled (0x0UL) /*!< Disable */
6157 #define I2S_INTEN_TXPTRUPD_Enabled (0x1UL) /*!< Enable */
6158 
6159 /* Bit 2 : Enable or disable interrupt for event STOPPED */
6160 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
6161 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6162 #define I2S_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
6163 #define I2S_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
6164 
6165 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
6166 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
6167 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
6168 #define I2S_INTEN_RXPTRUPD_Disabled (0x0UL) /*!< Disable */
6169 #define I2S_INTEN_RXPTRUPD_Enabled (0x1UL) /*!< Enable */
6170 
6171 /* Register: I2S_INTENSET */
6172 /* Description: Enable interrupt */
6173 
6174 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
6175 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
6176 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
6177 #define I2S_INTENSET_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
6178 #define I2S_INTENSET_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
6179 #define I2S_INTENSET_TXPTRUPD_Set (0x1UL) /*!< Enable */
6180 
6181 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
6182 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
6183 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6184 #define I2S_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
6185 #define I2S_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
6186 #define I2S_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
6187 
6188 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
6189 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
6190 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
6191 #define I2S_INTENSET_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
6192 #define I2S_INTENSET_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
6193 #define I2S_INTENSET_RXPTRUPD_Set (0x1UL) /*!< Enable */
6194 
6195 /* Register: I2S_INTENCLR */
6196 /* Description: Disable interrupt */
6197 
6198 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
6199 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
6200 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
6201 #define I2S_INTENCLR_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
6202 #define I2S_INTENCLR_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
6203 #define I2S_INTENCLR_TXPTRUPD_Clear (0x1UL) /*!< Disable */
6204 
6205 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
6206 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
6207 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6208 #define I2S_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
6209 #define I2S_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
6210 #define I2S_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
6211 
6212 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
6213 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
6214 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
6215 #define I2S_INTENCLR_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
6216 #define I2S_INTENCLR_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
6217 #define I2S_INTENCLR_RXPTRUPD_Clear (0x1UL) /*!< Disable */
6218 
6219 /* Register: I2S_ENABLE */
6220 /* Description: Enable I2S module. */
6221 
6222 /* Bit 0 : Enable I2S module. */
6223 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6224 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6225 #define I2S_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
6226 #define I2S_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */
6227 
6228 /* Register: I2S_CONFIG_MODE */
6229 /* Description: I2S mode. */
6230 
6231 /* Bit 0 : I2S mode. */
6232 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
6233 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
6234 #define I2S_CONFIG_MODE_MODE_Master (0x0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
6235 #define I2S_CONFIG_MODE_MODE_Slave (0x1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
6236 
6237 /* Register: I2S_CONFIG_RXEN */
6238 /* Description: Reception (RX) enable. */
6239 
6240 /* Bit 0 : Reception (RX) enable. */
6241 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
6242 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
6243 #define I2S_CONFIG_RXEN_RXEN_Disabled (0x0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
6244 #define I2S_CONFIG_RXEN_RXEN_Enabled (0x1UL) /*!< Reception enabled. */
6245 
6246 /* Register: I2S_CONFIG_TXEN */
6247 /* Description: Transmission (TX) enable. */
6248 
6249 /* Bit 0 : Transmission (TX) enable. */
6250 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
6251 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
6252 #define I2S_CONFIG_TXEN_TXEN_Disabled (0x0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
6253 #define I2S_CONFIG_TXEN_TXEN_Enabled (0x1UL) /*!< Transmission enabled. */
6254 
6255 /* Register: I2S_CONFIG_MCKEN */
6256 /* Description: Master clock generator enable. */
6257 
6258 /* Bit 0 : Master clock generator enable. */
6259 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
6260 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
6261 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0x0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
6262 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (0x1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
6263 
6264 /* Register: I2S_CONFIG_MCKFREQ */
6265 /* Description: Master clock generator frequency. */
6266 
6267 /* Bits 31..0 : Master clock generator frequency. */
6268 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
6269 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
6270 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
6271 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
6272 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
6273 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
6274 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
6275 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
6276 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
6277 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
6278 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
6279 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
6280 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
6281 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
6282 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
6283 
6284 /* Register: I2S_CONFIG_RATIO */
6285 /* Description: MCK / LRCK ratio. */
6286 
6287 /* Bits 3..0 : MCK / LRCK ratio. */
6288 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
6289 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
6290 #define I2S_CONFIG_RATIO_RATIO_32X (0x0UL) /*!< LRCK = MCK / 32 */
6291 #define I2S_CONFIG_RATIO_RATIO_48X (0x1UL) /*!< LRCK = MCK / 48 */
6292 #define I2S_CONFIG_RATIO_RATIO_64X (0x2UL) /*!< LRCK = MCK / 64 */
6293 #define I2S_CONFIG_RATIO_RATIO_96X (0x3UL) /*!< LRCK = MCK / 96 */
6294 #define I2S_CONFIG_RATIO_RATIO_128X (0x4UL) /*!< LRCK = MCK / 128 */
6295 #define I2S_CONFIG_RATIO_RATIO_192X (0x5UL) /*!< LRCK = MCK / 192 */
6296 #define I2S_CONFIG_RATIO_RATIO_256X (0x6UL) /*!< LRCK = MCK / 256 */
6297 #define I2S_CONFIG_RATIO_RATIO_384X (0x7UL) /*!< LRCK = MCK / 384 */
6298 #define I2S_CONFIG_RATIO_RATIO_512X (0x8UL) /*!< LRCK = MCK / 512 */
6299 
6300 /* Register: I2S_CONFIG_SWIDTH */
6301 /* Description: Sample width. */
6302 
6303 /* Bits 1..0 : Sample width. */
6304 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
6305 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
6306 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0x0UL) /*!< 8 bit. */
6307 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (0x1UL) /*!< 16 bit. */
6308 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (0x2UL) /*!< 24 bit. */
6309 
6310 /* Register: I2S_CONFIG_ALIGN */
6311 /* Description: Alignment of sample within a frame. */
6312 
6313 /* Bit 0 : Alignment of sample within a frame. */
6314 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
6315 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
6316 #define I2S_CONFIG_ALIGN_ALIGN_Left (0x0UL) /*!< Left-aligned. */
6317 #define I2S_CONFIG_ALIGN_ALIGN_Right (0x1UL) /*!< Right-aligned. */
6318 
6319 /* Register: I2S_CONFIG_FORMAT */
6320 /* Description: Frame format. */
6321 
6322 /* Bit 0 : Frame format. */
6323 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
6324 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
6325 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0x0UL) /*!< Original I2S format. */
6326 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (0x1UL) /*!< Alternate (left- or right-aligned) format. */
6327 
6328 /* Register: I2S_CONFIG_CHANNELS */
6329 /* Description: Enable channels. */
6330 
6331 /* Bits 1..0 : Enable channels. */
6332 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
6333 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
6334 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0x0UL) /*!< Stereo. */
6335 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (0x1UL) /*!< Left only. */
6336 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (0x2UL) /*!< Right only. */
6337 
6338 /* Register: I2S_RXD_PTR */
6339 /* Description: Receive buffer RAM start address. */
6340 
6341 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
6342 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
6343 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
6344 
6345 /* Register: I2S_TXD_PTR */
6346 /* Description: Transmit buffer RAM start address. */
6347 
6348 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
6349 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
6350 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
6351 
6352 /* Register: I2S_RXTXD_MAXCNT */
6353 /* Description: Size of RXD and TXD buffers. */
6354 
6355 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
6356 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
6357 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
6358 
6359 /* Register: I2S_PSEL_MCK */
6360 /* Description: Pin select for MCK signal. */
6361 
6362 /* Bit 31 : Connection */
6363 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6364 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6365 #define I2S_PSEL_MCK_CONNECT_Connected (0x0UL) /*!< Connect */
6366 #define I2S_PSEL_MCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
6367 
6368 /* Bits 4..0 : Pin number */
6369 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
6370 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
6371 
6372 /* Register: I2S_PSEL_SCK */
6373 /* Description: Pin select for SCK signal. */
6374 
6375 /* Bit 31 : Connection */
6376 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6377 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6378 #define I2S_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
6379 #define I2S_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
6380 
6381 /* Bits 4..0 : Pin number */
6382 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
6383 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
6384 
6385 /* Register: I2S_PSEL_LRCK */
6386 /* Description: Pin select for LRCK signal. */
6387 
6388 /* Bit 31 : Connection */
6389 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6390 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6391 #define I2S_PSEL_LRCK_CONNECT_Connected (0x0UL) /*!< Connect */
6392 #define I2S_PSEL_LRCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
6393 
6394 /* Bits 4..0 : Pin number */
6395 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
6396 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
6397 
6398 /* Register: I2S_PSEL_SDIN */
6399 /* Description: Pin select for SDIN signal. */
6400 
6401 /* Bit 31 : Connection */
6402 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6403 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6404 #define I2S_PSEL_SDIN_CONNECT_Connected (0x0UL) /*!< Connect */
6405 #define I2S_PSEL_SDIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
6406 
6407 /* Bits 4..0 : Pin number */
6408 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
6409 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
6410 
6411 /* Register: I2S_PSEL_SDOUT */
6412 /* Description: Pin select for SDOUT signal. */
6413 
6414 /* Bit 31 : Connection */
6415 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6416 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6417 #define I2S_PSEL_SDOUT_CONNECT_Connected (0x0UL) /*!< Connect */
6418 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
6419 
6420 /* Bits 4..0 : Pin number */
6421 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
6422 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
6423 
6424 
6425 /* Peripheral: IPC */
6426 /* Description: Interprocessor communication 0 */
6427 
6428 /* Register: IPC_TASKS_SEND */
6429 /* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */
6430 
6431 /* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */
6432 #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */
6433 #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */
6434 #define IPC_TASKS_SEND_TASKS_SEND_Trigger (0x1UL) /*!< Trigger task */
6435 
6436 /* Register: IPC_SUBSCRIBE_SEND */
6437 /* Description: Description collection: Subscribe configuration for task SEND[n] */
6438 
6439 /* Bit 31 :   */
6440 #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */
6441 #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */
6442 #define IPC_SUBSCRIBE_SEND_EN_Disabled (0x0UL) /*!< Disable subscription */
6443 #define IPC_SUBSCRIBE_SEND_EN_Enabled (0x1UL) /*!< Enable subscription */
6444 
6445 /* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */
6446 #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6447 #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6448 
6449 /* Register: IPC_EVENTS_RECEIVE */
6450 /* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
6451 
6452 /* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
6453 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */
6454 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */
6455 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0x0UL) /*!< Event not generated */
6456 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (0x1UL) /*!< Event generated */
6457 
6458 /* Register: IPC_PUBLISH_RECEIVE */
6459 /* Description: Description collection: Publish configuration for event RECEIVE[n] */
6460 
6461 /* Bit 31 :   */
6462 #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */
6463 #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */
6464 #define IPC_PUBLISH_RECEIVE_EN_Disabled (0x0UL) /*!< Disable publishing */
6465 #define IPC_PUBLISH_RECEIVE_EN_Enabled (0x1UL) /*!< Enable publishing */
6466 
6467 /* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to */
6468 #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6469 #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6470 
6471 /* Register: IPC_INTEN */
6472 /* Description: Enable or disable interrupt */
6473 
6474 /* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
6475 #define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
6476 #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
6477 #define IPC_INTEN_RECEIVE7_Disabled (0x0UL) /*!< Disable */
6478 #define IPC_INTEN_RECEIVE7_Enabled (0x1UL) /*!< Enable */
6479 
6480 /* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
6481 #define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
6482 #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
6483 #define IPC_INTEN_RECEIVE6_Disabled (0x0UL) /*!< Disable */
6484 #define IPC_INTEN_RECEIVE6_Enabled (0x1UL) /*!< Enable */
6485 
6486 /* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
6487 #define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
6488 #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
6489 #define IPC_INTEN_RECEIVE5_Disabled (0x0UL) /*!< Disable */
6490 #define IPC_INTEN_RECEIVE5_Enabled (0x1UL) /*!< Enable */
6491 
6492 /* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
6493 #define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
6494 #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
6495 #define IPC_INTEN_RECEIVE4_Disabled (0x0UL) /*!< Disable */
6496 #define IPC_INTEN_RECEIVE4_Enabled (0x1UL) /*!< Enable */
6497 
6498 /* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
6499 #define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
6500 #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
6501 #define IPC_INTEN_RECEIVE3_Disabled (0x0UL) /*!< Disable */
6502 #define IPC_INTEN_RECEIVE3_Enabled (0x1UL) /*!< Enable */
6503 
6504 /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
6505 #define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
6506 #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
6507 #define IPC_INTEN_RECEIVE2_Disabled (0x0UL) /*!< Disable */
6508 #define IPC_INTEN_RECEIVE2_Enabled (0x1UL) /*!< Enable */
6509 
6510 /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
6511 #define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
6512 #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
6513 #define IPC_INTEN_RECEIVE1_Disabled (0x0UL) /*!< Disable */
6514 #define IPC_INTEN_RECEIVE1_Enabled (0x1UL) /*!< Enable */
6515 
6516 /* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
6517 #define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
6518 #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
6519 #define IPC_INTEN_RECEIVE0_Disabled (0x0UL) /*!< Disable */
6520 #define IPC_INTEN_RECEIVE0_Enabled (0x1UL) /*!< Enable */
6521 
6522 /* Register: IPC_INTENSET */
6523 /* Description: Enable interrupt */
6524 
6525 /* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
6526 #define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
6527 #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
6528 #define IPC_INTENSET_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */
6529 #define IPC_INTENSET_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */
6530 #define IPC_INTENSET_RECEIVE7_Set (0x1UL) /*!< Enable */
6531 
6532 /* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
6533 #define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
6534 #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
6535 #define IPC_INTENSET_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */
6536 #define IPC_INTENSET_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */
6537 #define IPC_INTENSET_RECEIVE6_Set (0x1UL) /*!< Enable */
6538 
6539 /* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
6540 #define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
6541 #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
6542 #define IPC_INTENSET_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */
6543 #define IPC_INTENSET_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */
6544 #define IPC_INTENSET_RECEIVE5_Set (0x1UL) /*!< Enable */
6545 
6546 /* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
6547 #define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
6548 #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
6549 #define IPC_INTENSET_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */
6550 #define IPC_INTENSET_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */
6551 #define IPC_INTENSET_RECEIVE4_Set (0x1UL) /*!< Enable */
6552 
6553 /* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
6554 #define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
6555 #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
6556 #define IPC_INTENSET_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */
6557 #define IPC_INTENSET_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */
6558 #define IPC_INTENSET_RECEIVE3_Set (0x1UL) /*!< Enable */
6559 
6560 /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
6561 #define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
6562 #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
6563 #define IPC_INTENSET_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */
6564 #define IPC_INTENSET_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */
6565 #define IPC_INTENSET_RECEIVE2_Set (0x1UL) /*!< Enable */
6566 
6567 /* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
6568 #define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
6569 #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
6570 #define IPC_INTENSET_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */
6571 #define IPC_INTENSET_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */
6572 #define IPC_INTENSET_RECEIVE1_Set (0x1UL) /*!< Enable */
6573 
6574 /* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
6575 #define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
6576 #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
6577 #define IPC_INTENSET_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */
6578 #define IPC_INTENSET_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */
6579 #define IPC_INTENSET_RECEIVE0_Set (0x1UL) /*!< Enable */
6580 
6581 /* Register: IPC_INTENCLR */
6582 /* Description: Disable interrupt */
6583 
6584 /* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
6585 #define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
6586 #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
6587 #define IPC_INTENCLR_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */
6588 #define IPC_INTENCLR_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */
6589 #define IPC_INTENCLR_RECEIVE7_Clear (0x1UL) /*!< Disable */
6590 
6591 /* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
6592 #define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
6593 #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
6594 #define IPC_INTENCLR_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */
6595 #define IPC_INTENCLR_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */
6596 #define IPC_INTENCLR_RECEIVE6_Clear (0x1UL) /*!< Disable */
6597 
6598 /* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
6599 #define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
6600 #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
6601 #define IPC_INTENCLR_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */
6602 #define IPC_INTENCLR_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */
6603 #define IPC_INTENCLR_RECEIVE5_Clear (0x1UL) /*!< Disable */
6604 
6605 /* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
6606 #define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
6607 #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
6608 #define IPC_INTENCLR_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */
6609 #define IPC_INTENCLR_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */
6610 #define IPC_INTENCLR_RECEIVE4_Clear (0x1UL) /*!< Disable */
6611 
6612 /* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
6613 #define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
6614 #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
6615 #define IPC_INTENCLR_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */
6616 #define IPC_INTENCLR_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */
6617 #define IPC_INTENCLR_RECEIVE3_Clear (0x1UL) /*!< Disable */
6618 
6619 /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
6620 #define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
6621 #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
6622 #define IPC_INTENCLR_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */
6623 #define IPC_INTENCLR_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */
6624 #define IPC_INTENCLR_RECEIVE2_Clear (0x1UL) /*!< Disable */
6625 
6626 /* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
6627 #define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
6628 #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
6629 #define IPC_INTENCLR_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */
6630 #define IPC_INTENCLR_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */
6631 #define IPC_INTENCLR_RECEIVE1_Clear (0x1UL) /*!< Disable */
6632 
6633 /* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
6634 #define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
6635 #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
6636 #define IPC_INTENCLR_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */
6637 #define IPC_INTENCLR_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */
6638 #define IPC_INTENCLR_RECEIVE0_Clear (0x1UL) /*!< Disable */
6639 
6640 /* Register: IPC_INTPEND */
6641 /* Description: Pending interrupts */
6642 
6643 /* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
6644 #define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
6645 #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
6646 #define IPC_INTPEND_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */
6647 #define IPC_INTPEND_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */
6648 
6649 /* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
6650 #define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
6651 #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
6652 #define IPC_INTPEND_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */
6653 #define IPC_INTPEND_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */
6654 
6655 /* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
6656 #define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
6657 #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
6658 #define IPC_INTPEND_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */
6659 #define IPC_INTPEND_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */
6660 
6661 /* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
6662 #define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
6663 #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
6664 #define IPC_INTPEND_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */
6665 #define IPC_INTPEND_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */
6666 
6667 /* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
6668 #define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
6669 #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
6670 #define IPC_INTPEND_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */
6671 #define IPC_INTPEND_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */
6672 
6673 /* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
6674 #define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
6675 #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
6676 #define IPC_INTPEND_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */
6677 #define IPC_INTPEND_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */
6678 
6679 /* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
6680 #define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
6681 #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
6682 #define IPC_INTPEND_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */
6683 #define IPC_INTPEND_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */
6684 
6685 /* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
6686 #define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
6687 #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
6688 #define IPC_INTPEND_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */
6689 #define IPC_INTPEND_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */
6690 
6691 /* Register: IPC_SEND_CNF */
6692 /* Description: Description collection: Send event configuration for TASKS_SEND[n] */
6693 
6694 /* Bit 7 : Enable broadcasting on IPC channel 7 */
6695 #define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
6696 #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
6697 #define IPC_SEND_CNF_CHEN7_Disable (0x0UL) /*!< Disable broadcast */
6698 #define IPC_SEND_CNF_CHEN7_Enable (0x1UL) /*!< Enable broadcast */
6699 
6700 /* Bit 6 : Enable broadcasting on IPC channel 6 */
6701 #define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
6702 #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
6703 #define IPC_SEND_CNF_CHEN6_Disable (0x0UL) /*!< Disable broadcast */
6704 #define IPC_SEND_CNF_CHEN6_Enable (0x1UL) /*!< Enable broadcast */
6705 
6706 /* Bit 5 : Enable broadcasting on IPC channel 5 */
6707 #define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
6708 #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
6709 #define IPC_SEND_CNF_CHEN5_Disable (0x0UL) /*!< Disable broadcast */
6710 #define IPC_SEND_CNF_CHEN5_Enable (0x1UL) /*!< Enable broadcast */
6711 
6712 /* Bit 4 : Enable broadcasting on IPC channel 4 */
6713 #define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
6714 #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
6715 #define IPC_SEND_CNF_CHEN4_Disable (0x0UL) /*!< Disable broadcast */
6716 #define IPC_SEND_CNF_CHEN4_Enable (0x1UL) /*!< Enable broadcast */
6717 
6718 /* Bit 3 : Enable broadcasting on IPC channel 3 */
6719 #define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
6720 #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
6721 #define IPC_SEND_CNF_CHEN3_Disable (0x0UL) /*!< Disable broadcast */
6722 #define IPC_SEND_CNF_CHEN3_Enable (0x1UL) /*!< Enable broadcast */
6723 
6724 /* Bit 2 : Enable broadcasting on IPC channel 2 */
6725 #define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
6726 #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
6727 #define IPC_SEND_CNF_CHEN2_Disable (0x0UL) /*!< Disable broadcast */
6728 #define IPC_SEND_CNF_CHEN2_Enable (0x1UL) /*!< Enable broadcast */
6729 
6730 /* Bit 1 : Enable broadcasting on IPC channel 1 */
6731 #define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
6732 #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
6733 #define IPC_SEND_CNF_CHEN1_Disable (0x0UL) /*!< Disable broadcast */
6734 #define IPC_SEND_CNF_CHEN1_Enable (0x1UL) /*!< Enable broadcast */
6735 
6736 /* Bit 0 : Enable broadcasting on IPC channel 0 */
6737 #define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
6738 #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
6739 #define IPC_SEND_CNF_CHEN0_Disable (0x0UL) /*!< Disable broadcast */
6740 #define IPC_SEND_CNF_CHEN0_Enable (0x1UL) /*!< Enable broadcast */
6741 
6742 /* Register: IPC_RECEIVE_CNF */
6743 /* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */
6744 
6745 /* Bit 7 : Enable subscription to IPC channel 7 */
6746 #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
6747 #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
6748 #define IPC_RECEIVE_CNF_CHEN7_Disable (0x0UL) /*!< Disable events */
6749 #define IPC_RECEIVE_CNF_CHEN7_Enable (0x1UL) /*!< Enable events */
6750 
6751 /* Bit 6 : Enable subscription to IPC channel 6 */
6752 #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
6753 #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
6754 #define IPC_RECEIVE_CNF_CHEN6_Disable (0x0UL) /*!< Disable events */
6755 #define IPC_RECEIVE_CNF_CHEN6_Enable (0x1UL) /*!< Enable events */
6756 
6757 /* Bit 5 : Enable subscription to IPC channel 5 */
6758 #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
6759 #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
6760 #define IPC_RECEIVE_CNF_CHEN5_Disable (0x0UL) /*!< Disable events */
6761 #define IPC_RECEIVE_CNF_CHEN5_Enable (0x1UL) /*!< Enable events */
6762 
6763 /* Bit 4 : Enable subscription to IPC channel 4 */
6764 #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
6765 #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
6766 #define IPC_RECEIVE_CNF_CHEN4_Disable (0x0UL) /*!< Disable events */
6767 #define IPC_RECEIVE_CNF_CHEN4_Enable (0x1UL) /*!< Enable events */
6768 
6769 /* Bit 3 : Enable subscription to IPC channel 3 */
6770 #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
6771 #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
6772 #define IPC_RECEIVE_CNF_CHEN3_Disable (0x0UL) /*!< Disable events */
6773 #define IPC_RECEIVE_CNF_CHEN3_Enable (0x1UL) /*!< Enable events */
6774 
6775 /* Bit 2 : Enable subscription to IPC channel 2 */
6776 #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
6777 #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
6778 #define IPC_RECEIVE_CNF_CHEN2_Disable (0x0UL) /*!< Disable events */
6779 #define IPC_RECEIVE_CNF_CHEN2_Enable (0x1UL) /*!< Enable events */
6780 
6781 /* Bit 1 : Enable subscription to IPC channel 1 */
6782 #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
6783 #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
6784 #define IPC_RECEIVE_CNF_CHEN1_Disable (0x0UL) /*!< Disable events */
6785 #define IPC_RECEIVE_CNF_CHEN1_Enable (0x1UL) /*!< Enable events */
6786 
6787 /* Bit 0 : Enable subscription to IPC channel 0 */
6788 #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
6789 #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
6790 #define IPC_RECEIVE_CNF_CHEN0_Disable (0x0UL) /*!< Disable events */
6791 #define IPC_RECEIVE_CNF_CHEN0_Enable (0x1UL) /*!< Enable events */
6792 
6793 /* Register: IPC_GPMEM */
6794 /* Description: Description collection: General purpose memory */
6795 
6796 /* Bits 31..0 : General purpose memory */
6797 #define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */
6798 #define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos) /*!< Bit mask of GPMEM field. */
6799 
6800 
6801 /* Peripheral: KMU */
6802 /* Description: Key management unit 0 */
6803 
6804 /* Register: KMU_TASKS_PUSH_KEYSLOT */
6805 /* Description: Push a key slot over secure APB */
6806 
6807 /* Bit 0 : Push a key slot over secure APB */
6808 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL) /*!< Position of TASKS_PUSH_KEYSLOT field. */
6809 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos) /*!< Bit mask of TASKS_PUSH_KEYSLOT field. */
6810 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (0x1UL) /*!< Trigger task */
6811 
6812 /* Register: KMU_EVENTS_KEYSLOT_PUSHED */
6813 /* Description: Key slot successfully pushed over secure APB */
6814 
6815 /* Bit 0 : Key slot successfully pushed over secure APB */
6816 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */
6817 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */
6818 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0x0UL) /*!< Event not generated */
6819 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (0x1UL) /*!< Event generated */
6820 
6821 /* Register: KMU_EVENTS_KEYSLOT_REVOKED */
6822 /* Description: Key slot has been revoked and cannot be tasked for selection */
6823 
6824 /* Bit 0 : Key slot has been revoked and cannot be tasked for selection */
6825 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */
6826 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */
6827 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0x0UL) /*!< Event not generated */
6828 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (0x1UL) /*!< Event generated */
6829 
6830 /* Register: KMU_EVENTS_KEYSLOT_ERROR */
6831 /* Description: No key slot selected, no destination address defined, or error during push operation */
6832 
6833 /* Bit 0 : No key slot selected, no destination address defined, or error during push operation */
6834 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_ERROR field. */
6835 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos) /*!< Bit mask of EVENTS_KEYSLOT_ERROR field. */
6836 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
6837 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (0x1UL) /*!< Event generated */
6838 
6839 /* Register: KMU_INTEN */
6840 /* Description: Enable or disable interrupt */
6841 
6842 /* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */
6843 #define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
6844 #define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
6845 #define KMU_INTEN_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Disable */
6846 #define KMU_INTEN_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Enable */
6847 
6848 /* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */
6849 #define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
6850 #define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
6851 #define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Disable */
6852 #define KMU_INTEN_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Enable */
6853 
6854 /* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */
6855 #define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
6856 #define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
6857 #define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Disable */
6858 #define KMU_INTEN_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Enable */
6859 
6860 /* Register: KMU_INTENSET */
6861 /* Description: Enable interrupt */
6862 
6863 /* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */
6864 #define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
6865 #define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
6866 #define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
6867 #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
6868 #define KMU_INTENSET_KEYSLOT_ERROR_Set (0x1UL) /*!< Enable */
6869 
6870 /* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */
6871 #define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
6872 #define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
6873 #define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Read: Disabled */
6874 #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Read: Enabled */
6875 #define KMU_INTENSET_KEYSLOT_REVOKED_Set (0x1UL) /*!< Enable */
6876 
6877 /* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */
6878 #define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
6879 #define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
6880 #define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Read: Disabled */
6881 #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Read: Enabled */
6882 #define KMU_INTENSET_KEYSLOT_PUSHED_Set (0x1UL) /*!< Enable */
6883 
6884 /* Register: KMU_INTENCLR */
6885 /* Description: Disable interrupt */
6886 
6887 /* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */
6888 #define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
6889 #define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
6890 #define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
6891 #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
6892 #define KMU_INTENCLR_KEYSLOT_ERROR_Clear (0x1UL) /*!< Disable */
6893 
6894 /* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */
6895 #define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
6896 #define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
6897 #define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Read: Disabled */
6898 #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Read: Enabled */
6899 #define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (0x1UL) /*!< Disable */
6900 
6901 /* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */
6902 #define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
6903 #define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
6904 #define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Read: Disabled */
6905 #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Read: Enabled */
6906 #define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (0x1UL) /*!< Disable */
6907 
6908 /* Register: KMU_INTPEND */
6909 /* Description: Pending interrupts */
6910 
6911 /* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */
6912 #define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
6913 #define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
6914 #define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0x0UL) /*!< Read: Not pending */
6915 #define KMU_INTPEND_KEYSLOT_ERROR_Pending (0x1UL) /*!< Read: Pending */
6916 
6917 /* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */
6918 #define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
6919 #define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
6920 #define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0x0UL) /*!< Read: Not pending */
6921 #define KMU_INTPEND_KEYSLOT_REVOKED_Pending (0x1UL) /*!< Read: Pending */
6922 
6923 /* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */
6924 #define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
6925 #define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
6926 #define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0x0UL) /*!< Read: Not pending */
6927 #define KMU_INTPEND_KEYSLOT_PUSHED_Pending (0x1UL) /*!< Read: Pending */
6928 
6929 /* Register: KMU_STATUS */
6930 /* Description: Status bits for KMU operation */
6931 
6932 /* Bit 1 : Violation status */
6933 #define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */
6934 #define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos) /*!< Bit mask of BLOCKED field. */
6935 #define KMU_STATUS_BLOCKED_Disabled (0x0UL) /*!< No access violation detected */
6936 #define KMU_STATUS_BLOCKED_Enabled (0x1UL) /*!< Access violation detected and blocked */
6937 
6938 /* Bit 0 : Key slot ID successfully selected by the KMU */
6939 #define KMU_STATUS_SELECTED_Pos (0UL) /*!< Position of SELECTED field. */
6940 #define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
6941 #define KMU_STATUS_SELECTED_Disabled (0x0UL) /*!< No key slot ID selected by KMU */
6942 #define KMU_STATUS_SELECTED_Enabled (0x1UL) /*!< Key slot ID successfully selected by KMU */
6943 
6944 /* Register: KMU_SELECTKEYSLOT */
6945 /* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */
6946 
6947 /* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. */
6948 #define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */
6949 #define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */
6950 
6951 
6952 /* Peripheral: NVMC */
6953 /* Description: Non-volatile memory controller 0 */
6954 
6955 /* Register: NVMC_READY */
6956 /* Description: Ready flag */
6957 
6958 /* Bit 0 : NVMC is ready or busy */
6959 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
6960 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
6961 #define NVMC_READY_READY_Busy (0x0UL) /*!< NVMC is busy (on-going write or erase operation) */
6962 #define NVMC_READY_READY_Ready (0x1UL) /*!< NVMC is ready */
6963 
6964 /* Register: NVMC_READYNEXT */
6965 /* Description: Ready flag */
6966 
6967 /* Bit 0 : NVMC can accept a new write operation */
6968 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
6969 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
6970 #define NVMC_READYNEXT_READYNEXT_Busy (0x0UL) /*!< NVMC cannot accept any write operation */
6971 #define NVMC_READYNEXT_READYNEXT_Ready (0x1UL) /*!< NVMC is ready */
6972 
6973 /* Register: NVMC_CONFIG */
6974 /* Description: Configuration register */
6975 
6976 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
6977 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
6978 #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
6979 #define NVMC_CONFIG_WEN_Ren (0x0UL) /*!< Read only access */
6980 #define NVMC_CONFIG_WEN_Wen (0x1UL) /*!< Write enabled */
6981 #define NVMC_CONFIG_WEN_Een (0x2UL) /*!< Erase enabled */
6982 #define NVMC_CONFIG_WEN_PEen (0x4UL) /*!< Partial erase enabled */
6983 
6984 /* Register: NVMC_ERASEALL */
6985 /* Description: Register for erasing all non-volatile user memory */
6986 
6987 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. */
6988 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
6989 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
6990 #define NVMC_ERASEALL_ERASEALL_NoOperation (0x0UL) /*!< No operation */
6991 #define NVMC_ERASEALL_ERASEALL_Erase (0x1UL) /*!< Start chip erase */
6992 
6993 /* Register: NVMC_ERASEPAGEPARTIALCFG */
6994 /* Description: Register for partial erase configuration */
6995 
6996 /* Bits 6..0 : Duration of the partial erase in milliseconds */
6997 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
6998 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
6999 
7000 /* Register: NVMC_ICACHECNF */
7001 /* Description: I-code cache configuration register */
7002 
7003 /* Bit 8 : Cache profiling enable */
7004 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
7005 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
7006 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0x0UL) /*!< Disable cache profiling */
7007 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (0x1UL) /*!< Enable cache profiling */
7008 
7009 /* Bit 0 : Cache enable */
7010 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
7011 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
7012 #define NVMC_ICACHECNF_CACHEEN_Disabled (0x0UL) /*!< Disable cache. Invalidates all cache entries. */
7013 #define NVMC_ICACHECNF_CACHEEN_Enabled (0x1UL) /*!< Enable cache */
7014 
7015 /* Register: NVMC_IHIT */
7016 /* Description: I-code cache hit counter */
7017 
7018 /* Bits 31..0 : Number of cache hits Write zero to clear */
7019 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
7020 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
7021 
7022 /* Register: NVMC_IMISS */
7023 /* Description: I-code cache miss counter */
7024 
7025 /* Bits 31..0 : Number of cache misses Write zero to clear */
7026 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
7027 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
7028 
7029 /* Register: NVMC_CONFIGNS */
7030 /* Description: Unspecified */
7031 
7032 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
7033 #define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */
7034 #define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */
7035 #define NVMC_CONFIGNS_WEN_Ren (0x0UL) /*!< Read only access */
7036 #define NVMC_CONFIGNS_WEN_Wen (0x1UL) /*!< Write enabled */
7037 #define NVMC_CONFIGNS_WEN_Een (0x2UL) /*!< Erase enabled */
7038 
7039 /* Register: NVMC_WRITEUICRNS */
7040 /* Description: Non-secure APPROTECT enable register */
7041 
7042 /* Bits 31..4 : Key to write in order to validate the write operation */
7043 #define NVMC_WRITEUICRNS_KEY_Pos (4UL) /*!< Position of KEY field. */
7044 #define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos) /*!< Bit mask of KEY field. */
7045 #define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL) /*!< Key value */
7046 
7047 /* Bit 0 : Allow non-secure code to set APPROTECT */
7048 #define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */
7049 #define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */
7050 #define NVMC_WRITEUICRNS_SET_Set (0x1UL) /*!< Set value */
7051 
7052 
7053 /* Peripheral: GPIO */
7054 /* Description: GPIO Port 0 */
7055 
7056 /* Register: GPIO_OUT */
7057 /* Description: Write GPIO port */
7058 
7059 /* Bit 31 : Pin 31 */
7060 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7061 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7062 #define GPIO_OUT_PIN31_Low (0x0UL) /*!< Pin driver is low */
7063 #define GPIO_OUT_PIN31_High (0x1UL) /*!< Pin driver is high */
7064 
7065 /* Bit 30 : Pin 30 */
7066 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7067 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7068 #define GPIO_OUT_PIN30_Low (0x0UL) /*!< Pin driver is low */
7069 #define GPIO_OUT_PIN30_High (0x1UL) /*!< Pin driver is high */
7070 
7071 /* Bit 29 : Pin 29 */
7072 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7073 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7074 #define GPIO_OUT_PIN29_Low (0x0UL) /*!< Pin driver is low */
7075 #define GPIO_OUT_PIN29_High (0x1UL) /*!< Pin driver is high */
7076 
7077 /* Bit 28 : Pin 28 */
7078 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7079 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7080 #define GPIO_OUT_PIN28_Low (0x0UL) /*!< Pin driver is low */
7081 #define GPIO_OUT_PIN28_High (0x1UL) /*!< Pin driver is high */
7082 
7083 /* Bit 27 : Pin 27 */
7084 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7085 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7086 #define GPIO_OUT_PIN27_Low (0x0UL) /*!< Pin driver is low */
7087 #define GPIO_OUT_PIN27_High (0x1UL) /*!< Pin driver is high */
7088 
7089 /* Bit 26 : Pin 26 */
7090 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7091 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7092 #define GPIO_OUT_PIN26_Low (0x0UL) /*!< Pin driver is low */
7093 #define GPIO_OUT_PIN26_High (0x1UL) /*!< Pin driver is high */
7094 
7095 /* Bit 25 : Pin 25 */
7096 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7097 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7098 #define GPIO_OUT_PIN25_Low (0x0UL) /*!< Pin driver is low */
7099 #define GPIO_OUT_PIN25_High (0x1UL) /*!< Pin driver is high */
7100 
7101 /* Bit 24 : Pin 24 */
7102 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7103 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7104 #define GPIO_OUT_PIN24_Low (0x0UL) /*!< Pin driver is low */
7105 #define GPIO_OUT_PIN24_High (0x1UL) /*!< Pin driver is high */
7106 
7107 /* Bit 23 : Pin 23 */
7108 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7109 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7110 #define GPIO_OUT_PIN23_Low (0x0UL) /*!< Pin driver is low */
7111 #define GPIO_OUT_PIN23_High (0x1UL) /*!< Pin driver is high */
7112 
7113 /* Bit 22 : Pin 22 */
7114 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7115 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7116 #define GPIO_OUT_PIN22_Low (0x0UL) /*!< Pin driver is low */
7117 #define GPIO_OUT_PIN22_High (0x1UL) /*!< Pin driver is high */
7118 
7119 /* Bit 21 : Pin 21 */
7120 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7121 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7122 #define GPIO_OUT_PIN21_Low (0x0UL) /*!< Pin driver is low */
7123 #define GPIO_OUT_PIN21_High (0x1UL) /*!< Pin driver is high */
7124 
7125 /* Bit 20 : Pin 20 */
7126 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7127 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7128 #define GPIO_OUT_PIN20_Low (0x0UL) /*!< Pin driver is low */
7129 #define GPIO_OUT_PIN20_High (0x1UL) /*!< Pin driver is high */
7130 
7131 /* Bit 19 : Pin 19 */
7132 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7133 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7134 #define GPIO_OUT_PIN19_Low (0x0UL) /*!< Pin driver is low */
7135 #define GPIO_OUT_PIN19_High (0x1UL) /*!< Pin driver is high */
7136 
7137 /* Bit 18 : Pin 18 */
7138 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7139 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7140 #define GPIO_OUT_PIN18_Low (0x0UL) /*!< Pin driver is low */
7141 #define GPIO_OUT_PIN18_High (0x1UL) /*!< Pin driver is high */
7142 
7143 /* Bit 17 : Pin 17 */
7144 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7145 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7146 #define GPIO_OUT_PIN17_Low (0x0UL) /*!< Pin driver is low */
7147 #define GPIO_OUT_PIN17_High (0x1UL) /*!< Pin driver is high */
7148 
7149 /* Bit 16 : Pin 16 */
7150 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7151 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7152 #define GPIO_OUT_PIN16_Low (0x0UL) /*!< Pin driver is low */
7153 #define GPIO_OUT_PIN16_High (0x1UL) /*!< Pin driver is high */
7154 
7155 /* Bit 15 : Pin 15 */
7156 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7157 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7158 #define GPIO_OUT_PIN15_Low (0x0UL) /*!< Pin driver is low */
7159 #define GPIO_OUT_PIN15_High (0x1UL) /*!< Pin driver is high */
7160 
7161 /* Bit 14 : Pin 14 */
7162 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7163 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7164 #define GPIO_OUT_PIN14_Low (0x0UL) /*!< Pin driver is low */
7165 #define GPIO_OUT_PIN14_High (0x1UL) /*!< Pin driver is high */
7166 
7167 /* Bit 13 : Pin 13 */
7168 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7169 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7170 #define GPIO_OUT_PIN13_Low (0x0UL) /*!< Pin driver is low */
7171 #define GPIO_OUT_PIN13_High (0x1UL) /*!< Pin driver is high */
7172 
7173 /* Bit 12 : Pin 12 */
7174 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7175 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7176 #define GPIO_OUT_PIN12_Low (0x0UL) /*!< Pin driver is low */
7177 #define GPIO_OUT_PIN12_High (0x1UL) /*!< Pin driver is high */
7178 
7179 /* Bit 11 : Pin 11 */
7180 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7181 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7182 #define GPIO_OUT_PIN11_Low (0x0UL) /*!< Pin driver is low */
7183 #define GPIO_OUT_PIN11_High (0x1UL) /*!< Pin driver is high */
7184 
7185 /* Bit 10 : Pin 10 */
7186 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7187 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7188 #define GPIO_OUT_PIN10_Low (0x0UL) /*!< Pin driver is low */
7189 #define GPIO_OUT_PIN10_High (0x1UL) /*!< Pin driver is high */
7190 
7191 /* Bit 9 : Pin 9 */
7192 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7193 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7194 #define GPIO_OUT_PIN9_Low (0x0UL) /*!< Pin driver is low */
7195 #define GPIO_OUT_PIN9_High (0x1UL) /*!< Pin driver is high */
7196 
7197 /* Bit 8 : Pin 8 */
7198 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7199 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7200 #define GPIO_OUT_PIN8_Low (0x0UL) /*!< Pin driver is low */
7201 #define GPIO_OUT_PIN8_High (0x1UL) /*!< Pin driver is high */
7202 
7203 /* Bit 7 : Pin 7 */
7204 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7205 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7206 #define GPIO_OUT_PIN7_Low (0x0UL) /*!< Pin driver is low */
7207 #define GPIO_OUT_PIN7_High (0x1UL) /*!< Pin driver is high */
7208 
7209 /* Bit 6 : Pin 6 */
7210 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7211 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7212 #define GPIO_OUT_PIN6_Low (0x0UL) /*!< Pin driver is low */
7213 #define GPIO_OUT_PIN6_High (0x1UL) /*!< Pin driver is high */
7214 
7215 /* Bit 5 : Pin 5 */
7216 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7217 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7218 #define GPIO_OUT_PIN5_Low (0x0UL) /*!< Pin driver is low */
7219 #define GPIO_OUT_PIN5_High (0x1UL) /*!< Pin driver is high */
7220 
7221 /* Bit 4 : Pin 4 */
7222 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7223 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7224 #define GPIO_OUT_PIN4_Low (0x0UL) /*!< Pin driver is low */
7225 #define GPIO_OUT_PIN4_High (0x1UL) /*!< Pin driver is high */
7226 
7227 /* Bit 3 : Pin 3 */
7228 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7229 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7230 #define GPIO_OUT_PIN3_Low (0x0UL) /*!< Pin driver is low */
7231 #define GPIO_OUT_PIN3_High (0x1UL) /*!< Pin driver is high */
7232 
7233 /* Bit 2 : Pin 2 */
7234 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7235 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7236 #define GPIO_OUT_PIN2_Low (0x0UL) /*!< Pin driver is low */
7237 #define GPIO_OUT_PIN2_High (0x1UL) /*!< Pin driver is high */
7238 
7239 /* Bit 1 : Pin 1 */
7240 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7241 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7242 #define GPIO_OUT_PIN1_Low (0x0UL) /*!< Pin driver is low */
7243 #define GPIO_OUT_PIN1_High (0x1UL) /*!< Pin driver is high */
7244 
7245 /* Bit 0 : Pin 0 */
7246 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7247 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7248 #define GPIO_OUT_PIN0_Low (0x0UL) /*!< Pin driver is low */
7249 #define GPIO_OUT_PIN0_High (0x1UL) /*!< Pin driver is high */
7250 
7251 /* Register: GPIO_OUTSET */
7252 /* Description: Set individual bits in GPIO port */
7253 
7254 /* Bit 31 : Pin 31 */
7255 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7256 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7257 #define GPIO_OUTSET_PIN31_Low (0x0UL) /*!< Read: pin driver is low */
7258 #define GPIO_OUTSET_PIN31_High (0x1UL) /*!< Read: pin driver is high */
7259 #define GPIO_OUTSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7260 
7261 /* Bit 30 : Pin 30 */
7262 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7263 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7264 #define GPIO_OUTSET_PIN30_Low (0x0UL) /*!< Read: pin driver is low */
7265 #define GPIO_OUTSET_PIN30_High (0x1UL) /*!< Read: pin driver is high */
7266 #define GPIO_OUTSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7267 
7268 /* Bit 29 : Pin 29 */
7269 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7270 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7271 #define GPIO_OUTSET_PIN29_Low (0x0UL) /*!< Read: pin driver is low */
7272 #define GPIO_OUTSET_PIN29_High (0x1UL) /*!< Read: pin driver is high */
7273 #define GPIO_OUTSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7274 
7275 /* Bit 28 : Pin 28 */
7276 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7277 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7278 #define GPIO_OUTSET_PIN28_Low (0x0UL) /*!< Read: pin driver is low */
7279 #define GPIO_OUTSET_PIN28_High (0x1UL) /*!< Read: pin driver is high */
7280 #define GPIO_OUTSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7281 
7282 /* Bit 27 : Pin 27 */
7283 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7284 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7285 #define GPIO_OUTSET_PIN27_Low (0x0UL) /*!< Read: pin driver is low */
7286 #define GPIO_OUTSET_PIN27_High (0x1UL) /*!< Read: pin driver is high */
7287 #define GPIO_OUTSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7288 
7289 /* Bit 26 : Pin 26 */
7290 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7291 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7292 #define GPIO_OUTSET_PIN26_Low (0x0UL) /*!< Read: pin driver is low */
7293 #define GPIO_OUTSET_PIN26_High (0x1UL) /*!< Read: pin driver is high */
7294 #define GPIO_OUTSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7295 
7296 /* Bit 25 : Pin 25 */
7297 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7298 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7299 #define GPIO_OUTSET_PIN25_Low (0x0UL) /*!< Read: pin driver is low */
7300 #define GPIO_OUTSET_PIN25_High (0x1UL) /*!< Read: pin driver is high */
7301 #define GPIO_OUTSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7302 
7303 /* Bit 24 : Pin 24 */
7304 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7305 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7306 #define GPIO_OUTSET_PIN24_Low (0x0UL) /*!< Read: pin driver is low */
7307 #define GPIO_OUTSET_PIN24_High (0x1UL) /*!< Read: pin driver is high */
7308 #define GPIO_OUTSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7309 
7310 /* Bit 23 : Pin 23 */
7311 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7312 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7313 #define GPIO_OUTSET_PIN23_Low (0x0UL) /*!< Read: pin driver is low */
7314 #define GPIO_OUTSET_PIN23_High (0x1UL) /*!< Read: pin driver is high */
7315 #define GPIO_OUTSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7316 
7317 /* Bit 22 : Pin 22 */
7318 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7319 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7320 #define GPIO_OUTSET_PIN22_Low (0x0UL) /*!< Read: pin driver is low */
7321 #define GPIO_OUTSET_PIN22_High (0x1UL) /*!< Read: pin driver is high */
7322 #define GPIO_OUTSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7323 
7324 /* Bit 21 : Pin 21 */
7325 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7326 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7327 #define GPIO_OUTSET_PIN21_Low (0x0UL) /*!< Read: pin driver is low */
7328 #define GPIO_OUTSET_PIN21_High (0x1UL) /*!< Read: pin driver is high */
7329 #define GPIO_OUTSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7330 
7331 /* Bit 20 : Pin 20 */
7332 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7333 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7334 #define GPIO_OUTSET_PIN20_Low (0x0UL) /*!< Read: pin driver is low */
7335 #define GPIO_OUTSET_PIN20_High (0x1UL) /*!< Read: pin driver is high */
7336 #define GPIO_OUTSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7337 
7338 /* Bit 19 : Pin 19 */
7339 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7340 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7341 #define GPIO_OUTSET_PIN19_Low (0x0UL) /*!< Read: pin driver is low */
7342 #define GPIO_OUTSET_PIN19_High (0x1UL) /*!< Read: pin driver is high */
7343 #define GPIO_OUTSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7344 
7345 /* Bit 18 : Pin 18 */
7346 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7347 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7348 #define GPIO_OUTSET_PIN18_Low (0x0UL) /*!< Read: pin driver is low */
7349 #define GPIO_OUTSET_PIN18_High (0x1UL) /*!< Read: pin driver is high */
7350 #define GPIO_OUTSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7351 
7352 /* Bit 17 : Pin 17 */
7353 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7354 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7355 #define GPIO_OUTSET_PIN17_Low (0x0UL) /*!< Read: pin driver is low */
7356 #define GPIO_OUTSET_PIN17_High (0x1UL) /*!< Read: pin driver is high */
7357 #define GPIO_OUTSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7358 
7359 /* Bit 16 : Pin 16 */
7360 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7361 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7362 #define GPIO_OUTSET_PIN16_Low (0x0UL) /*!< Read: pin driver is low */
7363 #define GPIO_OUTSET_PIN16_High (0x1UL) /*!< Read: pin driver is high */
7364 #define GPIO_OUTSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7365 
7366 /* Bit 15 : Pin 15 */
7367 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7368 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7369 #define GPIO_OUTSET_PIN15_Low (0x0UL) /*!< Read: pin driver is low */
7370 #define GPIO_OUTSET_PIN15_High (0x1UL) /*!< Read: pin driver is high */
7371 #define GPIO_OUTSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7372 
7373 /* Bit 14 : Pin 14 */
7374 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7375 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7376 #define GPIO_OUTSET_PIN14_Low (0x0UL) /*!< Read: pin driver is low */
7377 #define GPIO_OUTSET_PIN14_High (0x1UL) /*!< Read: pin driver is high */
7378 #define GPIO_OUTSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7379 
7380 /* Bit 13 : Pin 13 */
7381 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7382 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7383 #define GPIO_OUTSET_PIN13_Low (0x0UL) /*!< Read: pin driver is low */
7384 #define GPIO_OUTSET_PIN13_High (0x1UL) /*!< Read: pin driver is high */
7385 #define GPIO_OUTSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7386 
7387 /* Bit 12 : Pin 12 */
7388 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7389 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7390 #define GPIO_OUTSET_PIN12_Low (0x0UL) /*!< Read: pin driver is low */
7391 #define GPIO_OUTSET_PIN12_High (0x1UL) /*!< Read: pin driver is high */
7392 #define GPIO_OUTSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7393 
7394 /* Bit 11 : Pin 11 */
7395 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7396 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7397 #define GPIO_OUTSET_PIN11_Low (0x0UL) /*!< Read: pin driver is low */
7398 #define GPIO_OUTSET_PIN11_High (0x1UL) /*!< Read: pin driver is high */
7399 #define GPIO_OUTSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7400 
7401 /* Bit 10 : Pin 10 */
7402 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7403 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7404 #define GPIO_OUTSET_PIN10_Low (0x0UL) /*!< Read: pin driver is low */
7405 #define GPIO_OUTSET_PIN10_High (0x1UL) /*!< Read: pin driver is high */
7406 #define GPIO_OUTSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7407 
7408 /* Bit 9 : Pin 9 */
7409 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7410 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7411 #define GPIO_OUTSET_PIN9_Low (0x0UL) /*!< Read: pin driver is low */
7412 #define GPIO_OUTSET_PIN9_High (0x1UL) /*!< Read: pin driver is high */
7413 #define GPIO_OUTSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7414 
7415 /* Bit 8 : Pin 8 */
7416 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7417 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7418 #define GPIO_OUTSET_PIN8_Low (0x0UL) /*!< Read: pin driver is low */
7419 #define GPIO_OUTSET_PIN8_High (0x1UL) /*!< Read: pin driver is high */
7420 #define GPIO_OUTSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7421 
7422 /* Bit 7 : Pin 7 */
7423 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7424 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7425 #define GPIO_OUTSET_PIN7_Low (0x0UL) /*!< Read: pin driver is low */
7426 #define GPIO_OUTSET_PIN7_High (0x1UL) /*!< Read: pin driver is high */
7427 #define GPIO_OUTSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7428 
7429 /* Bit 6 : Pin 6 */
7430 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7431 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7432 #define GPIO_OUTSET_PIN6_Low (0x0UL) /*!< Read: pin driver is low */
7433 #define GPIO_OUTSET_PIN6_High (0x1UL) /*!< Read: pin driver is high */
7434 #define GPIO_OUTSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7435 
7436 /* Bit 5 : Pin 5 */
7437 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7438 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7439 #define GPIO_OUTSET_PIN5_Low (0x0UL) /*!< Read: pin driver is low */
7440 #define GPIO_OUTSET_PIN5_High (0x1UL) /*!< Read: pin driver is high */
7441 #define GPIO_OUTSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7442 
7443 /* Bit 4 : Pin 4 */
7444 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7445 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7446 #define GPIO_OUTSET_PIN4_Low (0x0UL) /*!< Read: pin driver is low */
7447 #define GPIO_OUTSET_PIN4_High (0x1UL) /*!< Read: pin driver is high */
7448 #define GPIO_OUTSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7449 
7450 /* Bit 3 : Pin 3 */
7451 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7452 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7453 #define GPIO_OUTSET_PIN3_Low (0x0UL) /*!< Read: pin driver is low */
7454 #define GPIO_OUTSET_PIN3_High (0x1UL) /*!< Read: pin driver is high */
7455 #define GPIO_OUTSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7456 
7457 /* Bit 2 : Pin 2 */
7458 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7459 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7460 #define GPIO_OUTSET_PIN2_Low (0x0UL) /*!< Read: pin driver is low */
7461 #define GPIO_OUTSET_PIN2_High (0x1UL) /*!< Read: pin driver is high */
7462 #define GPIO_OUTSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7463 
7464 /* Bit 1 : Pin 1 */
7465 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7466 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7467 #define GPIO_OUTSET_PIN1_Low (0x0UL) /*!< Read: pin driver is low */
7468 #define GPIO_OUTSET_PIN1_High (0x1UL) /*!< Read: pin driver is high */
7469 #define GPIO_OUTSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7470 
7471 /* Bit 0 : Pin 0 */
7472 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7473 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7474 #define GPIO_OUTSET_PIN0_Low (0x0UL) /*!< Read: pin driver is low */
7475 #define GPIO_OUTSET_PIN0_High (0x1UL) /*!< Read: pin driver is high */
7476 #define GPIO_OUTSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7477 
7478 /* Register: GPIO_OUTCLR */
7479 /* Description: Clear individual bits in GPIO port */
7480 
7481 /* Bit 31 : Pin 31 */
7482 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7483 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7484 #define GPIO_OUTCLR_PIN31_Low (0x0UL) /*!< Read: pin driver is low */
7485 #define GPIO_OUTCLR_PIN31_High (0x1UL) /*!< Read: pin driver is high */
7486 #define GPIO_OUTCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7487 
7488 /* Bit 30 : Pin 30 */
7489 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7490 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7491 #define GPIO_OUTCLR_PIN30_Low (0x0UL) /*!< Read: pin driver is low */
7492 #define GPIO_OUTCLR_PIN30_High (0x1UL) /*!< Read: pin driver is high */
7493 #define GPIO_OUTCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7494 
7495 /* Bit 29 : Pin 29 */
7496 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7497 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7498 #define GPIO_OUTCLR_PIN29_Low (0x0UL) /*!< Read: pin driver is low */
7499 #define GPIO_OUTCLR_PIN29_High (0x1UL) /*!< Read: pin driver is high */
7500 #define GPIO_OUTCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7501 
7502 /* Bit 28 : Pin 28 */
7503 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7504 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7505 #define GPIO_OUTCLR_PIN28_Low (0x0UL) /*!< Read: pin driver is low */
7506 #define GPIO_OUTCLR_PIN28_High (0x1UL) /*!< Read: pin driver is high */
7507 #define GPIO_OUTCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7508 
7509 /* Bit 27 : Pin 27 */
7510 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7511 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7512 #define GPIO_OUTCLR_PIN27_Low (0x0UL) /*!< Read: pin driver is low */
7513 #define GPIO_OUTCLR_PIN27_High (0x1UL) /*!< Read: pin driver is high */
7514 #define GPIO_OUTCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7515 
7516 /* Bit 26 : Pin 26 */
7517 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7518 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7519 #define GPIO_OUTCLR_PIN26_Low (0x0UL) /*!< Read: pin driver is low */
7520 #define GPIO_OUTCLR_PIN26_High (0x1UL) /*!< Read: pin driver is high */
7521 #define GPIO_OUTCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7522 
7523 /* Bit 25 : Pin 25 */
7524 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7525 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7526 #define GPIO_OUTCLR_PIN25_Low (0x0UL) /*!< Read: pin driver is low */
7527 #define GPIO_OUTCLR_PIN25_High (0x1UL) /*!< Read: pin driver is high */
7528 #define GPIO_OUTCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7529 
7530 /* Bit 24 : Pin 24 */
7531 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7532 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7533 #define GPIO_OUTCLR_PIN24_Low (0x0UL) /*!< Read: pin driver is low */
7534 #define GPIO_OUTCLR_PIN24_High (0x1UL) /*!< Read: pin driver is high */
7535 #define GPIO_OUTCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7536 
7537 /* Bit 23 : Pin 23 */
7538 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7539 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7540 #define GPIO_OUTCLR_PIN23_Low (0x0UL) /*!< Read: pin driver is low */
7541 #define GPIO_OUTCLR_PIN23_High (0x1UL) /*!< Read: pin driver is high */
7542 #define GPIO_OUTCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7543 
7544 /* Bit 22 : Pin 22 */
7545 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7546 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7547 #define GPIO_OUTCLR_PIN22_Low (0x0UL) /*!< Read: pin driver is low */
7548 #define GPIO_OUTCLR_PIN22_High (0x1UL) /*!< Read: pin driver is high */
7549 #define GPIO_OUTCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7550 
7551 /* Bit 21 : Pin 21 */
7552 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7553 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7554 #define GPIO_OUTCLR_PIN21_Low (0x0UL) /*!< Read: pin driver is low */
7555 #define GPIO_OUTCLR_PIN21_High (0x1UL) /*!< Read: pin driver is high */
7556 #define GPIO_OUTCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7557 
7558 /* Bit 20 : Pin 20 */
7559 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7560 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7561 #define GPIO_OUTCLR_PIN20_Low (0x0UL) /*!< Read: pin driver is low */
7562 #define GPIO_OUTCLR_PIN20_High (0x1UL) /*!< Read: pin driver is high */
7563 #define GPIO_OUTCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7564 
7565 /* Bit 19 : Pin 19 */
7566 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7567 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7568 #define GPIO_OUTCLR_PIN19_Low (0x0UL) /*!< Read: pin driver is low */
7569 #define GPIO_OUTCLR_PIN19_High (0x1UL) /*!< Read: pin driver is high */
7570 #define GPIO_OUTCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7571 
7572 /* Bit 18 : Pin 18 */
7573 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7574 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7575 #define GPIO_OUTCLR_PIN18_Low (0x0UL) /*!< Read: pin driver is low */
7576 #define GPIO_OUTCLR_PIN18_High (0x1UL) /*!< Read: pin driver is high */
7577 #define GPIO_OUTCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7578 
7579 /* Bit 17 : Pin 17 */
7580 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7581 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7582 #define GPIO_OUTCLR_PIN17_Low (0x0UL) /*!< Read: pin driver is low */
7583 #define GPIO_OUTCLR_PIN17_High (0x1UL) /*!< Read: pin driver is high */
7584 #define GPIO_OUTCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7585 
7586 /* Bit 16 : Pin 16 */
7587 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7588 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7589 #define GPIO_OUTCLR_PIN16_Low (0x0UL) /*!< Read: pin driver is low */
7590 #define GPIO_OUTCLR_PIN16_High (0x1UL) /*!< Read: pin driver is high */
7591 #define GPIO_OUTCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7592 
7593 /* Bit 15 : Pin 15 */
7594 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7595 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7596 #define GPIO_OUTCLR_PIN15_Low (0x0UL) /*!< Read: pin driver is low */
7597 #define GPIO_OUTCLR_PIN15_High (0x1UL) /*!< Read: pin driver is high */
7598 #define GPIO_OUTCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7599 
7600 /* Bit 14 : Pin 14 */
7601 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7602 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7603 #define GPIO_OUTCLR_PIN14_Low (0x0UL) /*!< Read: pin driver is low */
7604 #define GPIO_OUTCLR_PIN14_High (0x1UL) /*!< Read: pin driver is high */
7605 #define GPIO_OUTCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7606 
7607 /* Bit 13 : Pin 13 */
7608 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7609 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7610 #define GPIO_OUTCLR_PIN13_Low (0x0UL) /*!< Read: pin driver is low */
7611 #define GPIO_OUTCLR_PIN13_High (0x1UL) /*!< Read: pin driver is high */
7612 #define GPIO_OUTCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7613 
7614 /* Bit 12 : Pin 12 */
7615 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7616 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7617 #define GPIO_OUTCLR_PIN12_Low (0x0UL) /*!< Read: pin driver is low */
7618 #define GPIO_OUTCLR_PIN12_High (0x1UL) /*!< Read: pin driver is high */
7619 #define GPIO_OUTCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7620 
7621 /* Bit 11 : Pin 11 */
7622 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7623 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7624 #define GPIO_OUTCLR_PIN11_Low (0x0UL) /*!< Read: pin driver is low */
7625 #define GPIO_OUTCLR_PIN11_High (0x1UL) /*!< Read: pin driver is high */
7626 #define GPIO_OUTCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7627 
7628 /* Bit 10 : Pin 10 */
7629 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7630 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7631 #define GPIO_OUTCLR_PIN10_Low (0x0UL) /*!< Read: pin driver is low */
7632 #define GPIO_OUTCLR_PIN10_High (0x1UL) /*!< Read: pin driver is high */
7633 #define GPIO_OUTCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7634 
7635 /* Bit 9 : Pin 9 */
7636 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7637 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7638 #define GPIO_OUTCLR_PIN9_Low (0x0UL) /*!< Read: pin driver is low */
7639 #define GPIO_OUTCLR_PIN9_High (0x1UL) /*!< Read: pin driver is high */
7640 #define GPIO_OUTCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7641 
7642 /* Bit 8 : Pin 8 */
7643 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7644 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7645 #define GPIO_OUTCLR_PIN8_Low (0x0UL) /*!< Read: pin driver is low */
7646 #define GPIO_OUTCLR_PIN8_High (0x1UL) /*!< Read: pin driver is high */
7647 #define GPIO_OUTCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7648 
7649 /* Bit 7 : Pin 7 */
7650 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7651 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7652 #define GPIO_OUTCLR_PIN7_Low (0x0UL) /*!< Read: pin driver is low */
7653 #define GPIO_OUTCLR_PIN7_High (0x1UL) /*!< Read: pin driver is high */
7654 #define GPIO_OUTCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7655 
7656 /* Bit 6 : Pin 6 */
7657 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7658 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7659 #define GPIO_OUTCLR_PIN6_Low (0x0UL) /*!< Read: pin driver is low */
7660 #define GPIO_OUTCLR_PIN6_High (0x1UL) /*!< Read: pin driver is high */
7661 #define GPIO_OUTCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7662 
7663 /* Bit 5 : Pin 5 */
7664 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7665 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7666 #define GPIO_OUTCLR_PIN5_Low (0x0UL) /*!< Read: pin driver is low */
7667 #define GPIO_OUTCLR_PIN5_High (0x1UL) /*!< Read: pin driver is high */
7668 #define GPIO_OUTCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7669 
7670 /* Bit 4 : Pin 4 */
7671 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7672 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7673 #define GPIO_OUTCLR_PIN4_Low (0x0UL) /*!< Read: pin driver is low */
7674 #define GPIO_OUTCLR_PIN4_High (0x1UL) /*!< Read: pin driver is high */
7675 #define GPIO_OUTCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7676 
7677 /* Bit 3 : Pin 3 */
7678 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7679 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7680 #define GPIO_OUTCLR_PIN3_Low (0x0UL) /*!< Read: pin driver is low */
7681 #define GPIO_OUTCLR_PIN3_High (0x1UL) /*!< Read: pin driver is high */
7682 #define GPIO_OUTCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7683 
7684 /* Bit 2 : Pin 2 */
7685 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7686 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7687 #define GPIO_OUTCLR_PIN2_Low (0x0UL) /*!< Read: pin driver is low */
7688 #define GPIO_OUTCLR_PIN2_High (0x1UL) /*!< Read: pin driver is high */
7689 #define GPIO_OUTCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7690 
7691 /* Bit 1 : Pin 1 */
7692 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7693 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7694 #define GPIO_OUTCLR_PIN1_Low (0x0UL) /*!< Read: pin driver is low */
7695 #define GPIO_OUTCLR_PIN1_High (0x1UL) /*!< Read: pin driver is high */
7696 #define GPIO_OUTCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7697 
7698 /* Bit 0 : Pin 0 */
7699 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7700 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7701 #define GPIO_OUTCLR_PIN0_Low (0x0UL) /*!< Read: pin driver is low */
7702 #define GPIO_OUTCLR_PIN0_High (0x1UL) /*!< Read: pin driver is high */
7703 #define GPIO_OUTCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7704 
7705 /* Register: GPIO_IN */
7706 /* Description: Read GPIO port */
7707 
7708 /* Bit 31 : Pin 31 */
7709 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7710 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7711 #define GPIO_IN_PIN31_Low (0x0UL) /*!< Pin input is low */
7712 #define GPIO_IN_PIN31_High (0x1UL) /*!< Pin input is high */
7713 
7714 /* Bit 30 : Pin 30 */
7715 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7716 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7717 #define GPIO_IN_PIN30_Low (0x0UL) /*!< Pin input is low */
7718 #define GPIO_IN_PIN30_High (0x1UL) /*!< Pin input is high */
7719 
7720 /* Bit 29 : Pin 29 */
7721 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7722 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7723 #define GPIO_IN_PIN29_Low (0x0UL) /*!< Pin input is low */
7724 #define GPIO_IN_PIN29_High (0x1UL) /*!< Pin input is high */
7725 
7726 /* Bit 28 : Pin 28 */
7727 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7728 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7729 #define GPIO_IN_PIN28_Low (0x0UL) /*!< Pin input is low */
7730 #define GPIO_IN_PIN28_High (0x1UL) /*!< Pin input is high */
7731 
7732 /* Bit 27 : Pin 27 */
7733 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7734 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7735 #define GPIO_IN_PIN27_Low (0x0UL) /*!< Pin input is low */
7736 #define GPIO_IN_PIN27_High (0x1UL) /*!< Pin input is high */
7737 
7738 /* Bit 26 : Pin 26 */
7739 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7740 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7741 #define GPIO_IN_PIN26_Low (0x0UL) /*!< Pin input is low */
7742 #define GPIO_IN_PIN26_High (0x1UL) /*!< Pin input is high */
7743 
7744 /* Bit 25 : Pin 25 */
7745 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7746 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7747 #define GPIO_IN_PIN25_Low (0x0UL) /*!< Pin input is low */
7748 #define GPIO_IN_PIN25_High (0x1UL) /*!< Pin input is high */
7749 
7750 /* Bit 24 : Pin 24 */
7751 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7752 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7753 #define GPIO_IN_PIN24_Low (0x0UL) /*!< Pin input is low */
7754 #define GPIO_IN_PIN24_High (0x1UL) /*!< Pin input is high */
7755 
7756 /* Bit 23 : Pin 23 */
7757 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7758 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7759 #define GPIO_IN_PIN23_Low (0x0UL) /*!< Pin input is low */
7760 #define GPIO_IN_PIN23_High (0x1UL) /*!< Pin input is high */
7761 
7762 /* Bit 22 : Pin 22 */
7763 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7764 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7765 #define GPIO_IN_PIN22_Low (0x0UL) /*!< Pin input is low */
7766 #define GPIO_IN_PIN22_High (0x1UL) /*!< Pin input is high */
7767 
7768 /* Bit 21 : Pin 21 */
7769 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7770 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7771 #define GPIO_IN_PIN21_Low (0x0UL) /*!< Pin input is low */
7772 #define GPIO_IN_PIN21_High (0x1UL) /*!< Pin input is high */
7773 
7774 /* Bit 20 : Pin 20 */
7775 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7776 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7777 #define GPIO_IN_PIN20_Low (0x0UL) /*!< Pin input is low */
7778 #define GPIO_IN_PIN20_High (0x1UL) /*!< Pin input is high */
7779 
7780 /* Bit 19 : Pin 19 */
7781 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7782 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7783 #define GPIO_IN_PIN19_Low (0x0UL) /*!< Pin input is low */
7784 #define GPIO_IN_PIN19_High (0x1UL) /*!< Pin input is high */
7785 
7786 /* Bit 18 : Pin 18 */
7787 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7788 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7789 #define GPIO_IN_PIN18_Low (0x0UL) /*!< Pin input is low */
7790 #define GPIO_IN_PIN18_High (0x1UL) /*!< Pin input is high */
7791 
7792 /* Bit 17 : Pin 17 */
7793 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7794 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7795 #define GPIO_IN_PIN17_Low (0x0UL) /*!< Pin input is low */
7796 #define GPIO_IN_PIN17_High (0x1UL) /*!< Pin input is high */
7797 
7798 /* Bit 16 : Pin 16 */
7799 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7800 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7801 #define GPIO_IN_PIN16_Low (0x0UL) /*!< Pin input is low */
7802 #define GPIO_IN_PIN16_High (0x1UL) /*!< Pin input is high */
7803 
7804 /* Bit 15 : Pin 15 */
7805 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7806 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7807 #define GPIO_IN_PIN15_Low (0x0UL) /*!< Pin input is low */
7808 #define GPIO_IN_PIN15_High (0x1UL) /*!< Pin input is high */
7809 
7810 /* Bit 14 : Pin 14 */
7811 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7812 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7813 #define GPIO_IN_PIN14_Low (0x0UL) /*!< Pin input is low */
7814 #define GPIO_IN_PIN14_High (0x1UL) /*!< Pin input is high */
7815 
7816 /* Bit 13 : Pin 13 */
7817 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7818 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7819 #define GPIO_IN_PIN13_Low (0x0UL) /*!< Pin input is low */
7820 #define GPIO_IN_PIN13_High (0x1UL) /*!< Pin input is high */
7821 
7822 /* Bit 12 : Pin 12 */
7823 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7824 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7825 #define GPIO_IN_PIN12_Low (0x0UL) /*!< Pin input is low */
7826 #define GPIO_IN_PIN12_High (0x1UL) /*!< Pin input is high */
7827 
7828 /* Bit 11 : Pin 11 */
7829 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7830 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7831 #define GPIO_IN_PIN11_Low (0x0UL) /*!< Pin input is low */
7832 #define GPIO_IN_PIN11_High (0x1UL) /*!< Pin input is high */
7833 
7834 /* Bit 10 : Pin 10 */
7835 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7836 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7837 #define GPIO_IN_PIN10_Low (0x0UL) /*!< Pin input is low */
7838 #define GPIO_IN_PIN10_High (0x1UL) /*!< Pin input is high */
7839 
7840 /* Bit 9 : Pin 9 */
7841 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7842 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7843 #define GPIO_IN_PIN9_Low (0x0UL) /*!< Pin input is low */
7844 #define GPIO_IN_PIN9_High (0x1UL) /*!< Pin input is high */
7845 
7846 /* Bit 8 : Pin 8 */
7847 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7848 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7849 #define GPIO_IN_PIN8_Low (0x0UL) /*!< Pin input is low */
7850 #define GPIO_IN_PIN8_High (0x1UL) /*!< Pin input is high */
7851 
7852 /* Bit 7 : Pin 7 */
7853 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7854 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7855 #define GPIO_IN_PIN7_Low (0x0UL) /*!< Pin input is low */
7856 #define GPIO_IN_PIN7_High (0x1UL) /*!< Pin input is high */
7857 
7858 /* Bit 6 : Pin 6 */
7859 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7860 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7861 #define GPIO_IN_PIN6_Low (0x0UL) /*!< Pin input is low */
7862 #define GPIO_IN_PIN6_High (0x1UL) /*!< Pin input is high */
7863 
7864 /* Bit 5 : Pin 5 */
7865 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7866 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7867 #define GPIO_IN_PIN5_Low (0x0UL) /*!< Pin input is low */
7868 #define GPIO_IN_PIN5_High (0x1UL) /*!< Pin input is high */
7869 
7870 /* Bit 4 : Pin 4 */
7871 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7872 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7873 #define GPIO_IN_PIN4_Low (0x0UL) /*!< Pin input is low */
7874 #define GPIO_IN_PIN4_High (0x1UL) /*!< Pin input is high */
7875 
7876 /* Bit 3 : Pin 3 */
7877 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7878 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7879 #define GPIO_IN_PIN3_Low (0x0UL) /*!< Pin input is low */
7880 #define GPIO_IN_PIN3_High (0x1UL) /*!< Pin input is high */
7881 
7882 /* Bit 2 : Pin 2 */
7883 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7884 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7885 #define GPIO_IN_PIN2_Low (0x0UL) /*!< Pin input is low */
7886 #define GPIO_IN_PIN2_High (0x1UL) /*!< Pin input is high */
7887 
7888 /* Bit 1 : Pin 1 */
7889 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7890 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7891 #define GPIO_IN_PIN1_Low (0x0UL) /*!< Pin input is low */
7892 #define GPIO_IN_PIN1_High (0x1UL) /*!< Pin input is high */
7893 
7894 /* Bit 0 : Pin 0 */
7895 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7896 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7897 #define GPIO_IN_PIN0_Low (0x0UL) /*!< Pin input is low */
7898 #define GPIO_IN_PIN0_High (0x1UL) /*!< Pin input is high */
7899 
7900 /* Register: GPIO_DIR */
7901 /* Description: Direction of GPIO pins */
7902 
7903 /* Bit 31 : Pin 31 */
7904 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7905 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7906 #define GPIO_DIR_PIN31_Input (0x0UL) /*!< Pin set as input */
7907 #define GPIO_DIR_PIN31_Output (0x1UL) /*!< Pin set as output */
7908 
7909 /* Bit 30 : Pin 30 */
7910 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7911 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7912 #define GPIO_DIR_PIN30_Input (0x0UL) /*!< Pin set as input */
7913 #define GPIO_DIR_PIN30_Output (0x1UL) /*!< Pin set as output */
7914 
7915 /* Bit 29 : Pin 29 */
7916 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7917 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7918 #define GPIO_DIR_PIN29_Input (0x0UL) /*!< Pin set as input */
7919 #define GPIO_DIR_PIN29_Output (0x1UL) /*!< Pin set as output */
7920 
7921 /* Bit 28 : Pin 28 */
7922 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7923 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7924 #define GPIO_DIR_PIN28_Input (0x0UL) /*!< Pin set as input */
7925 #define GPIO_DIR_PIN28_Output (0x1UL) /*!< Pin set as output */
7926 
7927 /* Bit 27 : Pin 27 */
7928 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7929 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7930 #define GPIO_DIR_PIN27_Input (0x0UL) /*!< Pin set as input */
7931 #define GPIO_DIR_PIN27_Output (0x1UL) /*!< Pin set as output */
7932 
7933 /* Bit 26 : Pin 26 */
7934 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7935 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7936 #define GPIO_DIR_PIN26_Input (0x0UL) /*!< Pin set as input */
7937 #define GPIO_DIR_PIN26_Output (0x1UL) /*!< Pin set as output */
7938 
7939 /* Bit 25 : Pin 25 */
7940 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7941 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7942 #define GPIO_DIR_PIN25_Input (0x0UL) /*!< Pin set as input */
7943 #define GPIO_DIR_PIN25_Output (0x1UL) /*!< Pin set as output */
7944 
7945 /* Bit 24 : Pin 24 */
7946 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7947 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7948 #define GPIO_DIR_PIN24_Input (0x0UL) /*!< Pin set as input */
7949 #define GPIO_DIR_PIN24_Output (0x1UL) /*!< Pin set as output */
7950 
7951 /* Bit 23 : Pin 23 */
7952 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7953 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7954 #define GPIO_DIR_PIN23_Input (0x0UL) /*!< Pin set as input */
7955 #define GPIO_DIR_PIN23_Output (0x1UL) /*!< Pin set as output */
7956 
7957 /* Bit 22 : Pin 22 */
7958 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7959 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7960 #define GPIO_DIR_PIN22_Input (0x0UL) /*!< Pin set as input */
7961 #define GPIO_DIR_PIN22_Output (0x1UL) /*!< Pin set as output */
7962 
7963 /* Bit 21 : Pin 21 */
7964 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7965 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7966 #define GPIO_DIR_PIN21_Input (0x0UL) /*!< Pin set as input */
7967 #define GPIO_DIR_PIN21_Output (0x1UL) /*!< Pin set as output */
7968 
7969 /* Bit 20 : Pin 20 */
7970 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7971 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7972 #define GPIO_DIR_PIN20_Input (0x0UL) /*!< Pin set as input */
7973 #define GPIO_DIR_PIN20_Output (0x1UL) /*!< Pin set as output */
7974 
7975 /* Bit 19 : Pin 19 */
7976 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7977 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7978 #define GPIO_DIR_PIN19_Input (0x0UL) /*!< Pin set as input */
7979 #define GPIO_DIR_PIN19_Output (0x1UL) /*!< Pin set as output */
7980 
7981 /* Bit 18 : Pin 18 */
7982 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7983 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7984 #define GPIO_DIR_PIN18_Input (0x0UL) /*!< Pin set as input */
7985 #define GPIO_DIR_PIN18_Output (0x1UL) /*!< Pin set as output */
7986 
7987 /* Bit 17 : Pin 17 */
7988 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7989 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7990 #define GPIO_DIR_PIN17_Input (0x0UL) /*!< Pin set as input */
7991 #define GPIO_DIR_PIN17_Output (0x1UL) /*!< Pin set as output */
7992 
7993 /* Bit 16 : Pin 16 */
7994 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7995 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7996 #define GPIO_DIR_PIN16_Input (0x0UL) /*!< Pin set as input */
7997 #define GPIO_DIR_PIN16_Output (0x1UL) /*!< Pin set as output */
7998 
7999 /* Bit 15 : Pin 15 */
8000 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
8001 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
8002 #define GPIO_DIR_PIN15_Input (0x0UL) /*!< Pin set as input */
8003 #define GPIO_DIR_PIN15_Output (0x1UL) /*!< Pin set as output */
8004 
8005 /* Bit 14 : Pin 14 */
8006 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
8007 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
8008 #define GPIO_DIR_PIN14_Input (0x0UL) /*!< Pin set as input */
8009 #define GPIO_DIR_PIN14_Output (0x1UL) /*!< Pin set as output */
8010 
8011 /* Bit 13 : Pin 13 */
8012 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
8013 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
8014 #define GPIO_DIR_PIN13_Input (0x0UL) /*!< Pin set as input */
8015 #define GPIO_DIR_PIN13_Output (0x1UL) /*!< Pin set as output */
8016 
8017 /* Bit 12 : Pin 12 */
8018 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
8019 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
8020 #define GPIO_DIR_PIN12_Input (0x0UL) /*!< Pin set as input */
8021 #define GPIO_DIR_PIN12_Output (0x1UL) /*!< Pin set as output */
8022 
8023 /* Bit 11 : Pin 11 */
8024 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
8025 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
8026 #define GPIO_DIR_PIN11_Input (0x0UL) /*!< Pin set as input */
8027 #define GPIO_DIR_PIN11_Output (0x1UL) /*!< Pin set as output */
8028 
8029 /* Bit 10 : Pin 10 */
8030 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
8031 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
8032 #define GPIO_DIR_PIN10_Input (0x0UL) /*!< Pin set as input */
8033 #define GPIO_DIR_PIN10_Output (0x1UL) /*!< Pin set as output */
8034 
8035 /* Bit 9 : Pin 9 */
8036 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
8037 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
8038 #define GPIO_DIR_PIN9_Input (0x0UL) /*!< Pin set as input */
8039 #define GPIO_DIR_PIN9_Output (0x1UL) /*!< Pin set as output */
8040 
8041 /* Bit 8 : Pin 8 */
8042 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
8043 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
8044 #define GPIO_DIR_PIN8_Input (0x0UL) /*!< Pin set as input */
8045 #define GPIO_DIR_PIN8_Output (0x1UL) /*!< Pin set as output */
8046 
8047 /* Bit 7 : Pin 7 */
8048 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
8049 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
8050 #define GPIO_DIR_PIN7_Input (0x0UL) /*!< Pin set as input */
8051 #define GPIO_DIR_PIN7_Output (0x1UL) /*!< Pin set as output */
8052 
8053 /* Bit 6 : Pin 6 */
8054 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
8055 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
8056 #define GPIO_DIR_PIN6_Input (0x0UL) /*!< Pin set as input */
8057 #define GPIO_DIR_PIN6_Output (0x1UL) /*!< Pin set as output */
8058 
8059 /* Bit 5 : Pin 5 */
8060 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
8061 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
8062 #define GPIO_DIR_PIN5_Input (0x0UL) /*!< Pin set as input */
8063 #define GPIO_DIR_PIN5_Output (0x1UL) /*!< Pin set as output */
8064 
8065 /* Bit 4 : Pin 4 */
8066 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
8067 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
8068 #define GPIO_DIR_PIN4_Input (0x0UL) /*!< Pin set as input */
8069 #define GPIO_DIR_PIN4_Output (0x1UL) /*!< Pin set as output */
8070 
8071 /* Bit 3 : Pin 3 */
8072 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
8073 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
8074 #define GPIO_DIR_PIN3_Input (0x0UL) /*!< Pin set as input */
8075 #define GPIO_DIR_PIN3_Output (0x1UL) /*!< Pin set as output */
8076 
8077 /* Bit 2 : Pin 2 */
8078 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
8079 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
8080 #define GPIO_DIR_PIN2_Input (0x0UL) /*!< Pin set as input */
8081 #define GPIO_DIR_PIN2_Output (0x1UL) /*!< Pin set as output */
8082 
8083 /* Bit 1 : Pin 1 */
8084 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
8085 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
8086 #define GPIO_DIR_PIN1_Input (0x0UL) /*!< Pin set as input */
8087 #define GPIO_DIR_PIN1_Output (0x1UL) /*!< Pin set as output */
8088 
8089 /* Bit 0 : Pin 0 */
8090 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
8091 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
8092 #define GPIO_DIR_PIN0_Input (0x0UL) /*!< Pin set as input */
8093 #define GPIO_DIR_PIN0_Output (0x1UL) /*!< Pin set as output */
8094 
8095 /* Register: GPIO_DIRSET */
8096 /* Description: DIR set register */
8097 
8098 /* Bit 31 : Set as output pin 31 */
8099 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
8100 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
8101 #define GPIO_DIRSET_PIN31_Input (0x0UL) /*!< Read: pin set as input */
8102 #define GPIO_DIRSET_PIN31_Output (0x1UL) /*!< Read: pin set as output */
8103 #define GPIO_DIRSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8104 
8105 /* Bit 30 : Set as output pin 30 */
8106 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
8107 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
8108 #define GPIO_DIRSET_PIN30_Input (0x0UL) /*!< Read: pin set as input */
8109 #define GPIO_DIRSET_PIN30_Output (0x1UL) /*!< Read: pin set as output */
8110 #define GPIO_DIRSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8111 
8112 /* Bit 29 : Set as output pin 29 */
8113 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
8114 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
8115 #define GPIO_DIRSET_PIN29_Input (0x0UL) /*!< Read: pin set as input */
8116 #define GPIO_DIRSET_PIN29_Output (0x1UL) /*!< Read: pin set as output */
8117 #define GPIO_DIRSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8118 
8119 /* Bit 28 : Set as output pin 28 */
8120 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
8121 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
8122 #define GPIO_DIRSET_PIN28_Input (0x0UL) /*!< Read: pin set as input */
8123 #define GPIO_DIRSET_PIN28_Output (0x1UL) /*!< Read: pin set as output */
8124 #define GPIO_DIRSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8125 
8126 /* Bit 27 : Set as output pin 27 */
8127 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
8128 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
8129 #define GPIO_DIRSET_PIN27_Input (0x0UL) /*!< Read: pin set as input */
8130 #define GPIO_DIRSET_PIN27_Output (0x1UL) /*!< Read: pin set as output */
8131 #define GPIO_DIRSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8132 
8133 /* Bit 26 : Set as output pin 26 */
8134 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
8135 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
8136 #define GPIO_DIRSET_PIN26_Input (0x0UL) /*!< Read: pin set as input */
8137 #define GPIO_DIRSET_PIN26_Output (0x1UL) /*!< Read: pin set as output */
8138 #define GPIO_DIRSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8139 
8140 /* Bit 25 : Set as output pin 25 */
8141 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
8142 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
8143 #define GPIO_DIRSET_PIN25_Input (0x0UL) /*!< Read: pin set as input */
8144 #define GPIO_DIRSET_PIN25_Output (0x1UL) /*!< Read: pin set as output */
8145 #define GPIO_DIRSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8146 
8147 /* Bit 24 : Set as output pin 24 */
8148 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
8149 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
8150 #define GPIO_DIRSET_PIN24_Input (0x0UL) /*!< Read: pin set as input */
8151 #define GPIO_DIRSET_PIN24_Output (0x1UL) /*!< Read: pin set as output */
8152 #define GPIO_DIRSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8153 
8154 /* Bit 23 : Set as output pin 23 */
8155 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
8156 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
8157 #define GPIO_DIRSET_PIN23_Input (0x0UL) /*!< Read: pin set as input */
8158 #define GPIO_DIRSET_PIN23_Output (0x1UL) /*!< Read: pin set as output */
8159 #define GPIO_DIRSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8160 
8161 /* Bit 22 : Set as output pin 22 */
8162 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
8163 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
8164 #define GPIO_DIRSET_PIN22_Input (0x0UL) /*!< Read: pin set as input */
8165 #define GPIO_DIRSET_PIN22_Output (0x1UL) /*!< Read: pin set as output */
8166 #define GPIO_DIRSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8167 
8168 /* Bit 21 : Set as output pin 21 */
8169 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
8170 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
8171 #define GPIO_DIRSET_PIN21_Input (0x0UL) /*!< Read: pin set as input */
8172 #define GPIO_DIRSET_PIN21_Output (0x1UL) /*!< Read: pin set as output */
8173 #define GPIO_DIRSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8174 
8175 /* Bit 20 : Set as output pin 20 */
8176 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
8177 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
8178 #define GPIO_DIRSET_PIN20_Input (0x0UL) /*!< Read: pin set as input */
8179 #define GPIO_DIRSET_PIN20_Output (0x1UL) /*!< Read: pin set as output */
8180 #define GPIO_DIRSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8181 
8182 /* Bit 19 : Set as output pin 19 */
8183 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
8184 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
8185 #define GPIO_DIRSET_PIN19_Input (0x0UL) /*!< Read: pin set as input */
8186 #define GPIO_DIRSET_PIN19_Output (0x1UL) /*!< Read: pin set as output */
8187 #define GPIO_DIRSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8188 
8189 /* Bit 18 : Set as output pin 18 */
8190 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
8191 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
8192 #define GPIO_DIRSET_PIN18_Input (0x0UL) /*!< Read: pin set as input */
8193 #define GPIO_DIRSET_PIN18_Output (0x1UL) /*!< Read: pin set as output */
8194 #define GPIO_DIRSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8195 
8196 /* Bit 17 : Set as output pin 17 */
8197 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
8198 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
8199 #define GPIO_DIRSET_PIN17_Input (0x0UL) /*!< Read: pin set as input */
8200 #define GPIO_DIRSET_PIN17_Output (0x1UL) /*!< Read: pin set as output */
8201 #define GPIO_DIRSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8202 
8203 /* Bit 16 : Set as output pin 16 */
8204 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
8205 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
8206 #define GPIO_DIRSET_PIN16_Input (0x0UL) /*!< Read: pin set as input */
8207 #define GPIO_DIRSET_PIN16_Output (0x1UL) /*!< Read: pin set as output */
8208 #define GPIO_DIRSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8209 
8210 /* Bit 15 : Set as output pin 15 */
8211 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
8212 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
8213 #define GPIO_DIRSET_PIN15_Input (0x0UL) /*!< Read: pin set as input */
8214 #define GPIO_DIRSET_PIN15_Output (0x1UL) /*!< Read: pin set as output */
8215 #define GPIO_DIRSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8216 
8217 /* Bit 14 : Set as output pin 14 */
8218 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
8219 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
8220 #define GPIO_DIRSET_PIN14_Input (0x0UL) /*!< Read: pin set as input */
8221 #define GPIO_DIRSET_PIN14_Output (0x1UL) /*!< Read: pin set as output */
8222 #define GPIO_DIRSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8223 
8224 /* Bit 13 : Set as output pin 13 */
8225 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
8226 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
8227 #define GPIO_DIRSET_PIN13_Input (0x0UL) /*!< Read: pin set as input */
8228 #define GPIO_DIRSET_PIN13_Output (0x1UL) /*!< Read: pin set as output */
8229 #define GPIO_DIRSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8230 
8231 /* Bit 12 : Set as output pin 12 */
8232 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
8233 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
8234 #define GPIO_DIRSET_PIN12_Input (0x0UL) /*!< Read: pin set as input */
8235 #define GPIO_DIRSET_PIN12_Output (0x1UL) /*!< Read: pin set as output */
8236 #define GPIO_DIRSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8237 
8238 /* Bit 11 : Set as output pin 11 */
8239 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
8240 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
8241 #define GPIO_DIRSET_PIN11_Input (0x0UL) /*!< Read: pin set as input */
8242 #define GPIO_DIRSET_PIN11_Output (0x1UL) /*!< Read: pin set as output */
8243 #define GPIO_DIRSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8244 
8245 /* Bit 10 : Set as output pin 10 */
8246 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
8247 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
8248 #define GPIO_DIRSET_PIN10_Input (0x0UL) /*!< Read: pin set as input */
8249 #define GPIO_DIRSET_PIN10_Output (0x1UL) /*!< Read: pin set as output */
8250 #define GPIO_DIRSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8251 
8252 /* Bit 9 : Set as output pin 9 */
8253 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
8254 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
8255 #define GPIO_DIRSET_PIN9_Input (0x0UL) /*!< Read: pin set as input */
8256 #define GPIO_DIRSET_PIN9_Output (0x1UL) /*!< Read: pin set as output */
8257 #define GPIO_DIRSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8258 
8259 /* Bit 8 : Set as output pin 8 */
8260 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
8261 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
8262 #define GPIO_DIRSET_PIN8_Input (0x0UL) /*!< Read: pin set as input */
8263 #define GPIO_DIRSET_PIN8_Output (0x1UL) /*!< Read: pin set as output */
8264 #define GPIO_DIRSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8265 
8266 /* Bit 7 : Set as output pin 7 */
8267 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
8268 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
8269 #define GPIO_DIRSET_PIN7_Input (0x0UL) /*!< Read: pin set as input */
8270 #define GPIO_DIRSET_PIN7_Output (0x1UL) /*!< Read: pin set as output */
8271 #define GPIO_DIRSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8272 
8273 /* Bit 6 : Set as output pin 6 */
8274 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
8275 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
8276 #define GPIO_DIRSET_PIN6_Input (0x0UL) /*!< Read: pin set as input */
8277 #define GPIO_DIRSET_PIN6_Output (0x1UL) /*!< Read: pin set as output */
8278 #define GPIO_DIRSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8279 
8280 /* Bit 5 : Set as output pin 5 */
8281 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
8282 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
8283 #define GPIO_DIRSET_PIN5_Input (0x0UL) /*!< Read: pin set as input */
8284 #define GPIO_DIRSET_PIN5_Output (0x1UL) /*!< Read: pin set as output */
8285 #define GPIO_DIRSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8286 
8287 /* Bit 4 : Set as output pin 4 */
8288 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
8289 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
8290 #define GPIO_DIRSET_PIN4_Input (0x0UL) /*!< Read: pin set as input */
8291 #define GPIO_DIRSET_PIN4_Output (0x1UL) /*!< Read: pin set as output */
8292 #define GPIO_DIRSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8293 
8294 /* Bit 3 : Set as output pin 3 */
8295 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
8296 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
8297 #define GPIO_DIRSET_PIN3_Input (0x0UL) /*!< Read: pin set as input */
8298 #define GPIO_DIRSET_PIN3_Output (0x1UL) /*!< Read: pin set as output */
8299 #define GPIO_DIRSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8300 
8301 /* Bit 2 : Set as output pin 2 */
8302 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
8303 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
8304 #define GPIO_DIRSET_PIN2_Input (0x0UL) /*!< Read: pin set as input */
8305 #define GPIO_DIRSET_PIN2_Output (0x1UL) /*!< Read: pin set as output */
8306 #define GPIO_DIRSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8307 
8308 /* Bit 1 : Set as output pin 1 */
8309 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
8310 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
8311 #define GPIO_DIRSET_PIN1_Input (0x0UL) /*!< Read: pin set as input */
8312 #define GPIO_DIRSET_PIN1_Output (0x1UL) /*!< Read: pin set as output */
8313 #define GPIO_DIRSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8314 
8315 /* Bit 0 : Set as output pin 0 */
8316 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
8317 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
8318 #define GPIO_DIRSET_PIN0_Input (0x0UL) /*!< Read: pin set as input */
8319 #define GPIO_DIRSET_PIN0_Output (0x1UL) /*!< Read: pin set as output */
8320 #define GPIO_DIRSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8321 
8322 /* Register: GPIO_DIRCLR */
8323 /* Description: DIR clear register */
8324 
8325 /* Bit 31 : Set as input pin 31 */
8326 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
8327 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
8328 #define GPIO_DIRCLR_PIN31_Input (0x0UL) /*!< Read: pin set as input */
8329 #define GPIO_DIRCLR_PIN31_Output (0x1UL) /*!< Read: pin set as output */
8330 #define GPIO_DIRCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8331 
8332 /* Bit 30 : Set as input pin 30 */
8333 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
8334 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
8335 #define GPIO_DIRCLR_PIN30_Input (0x0UL) /*!< Read: pin set as input */
8336 #define GPIO_DIRCLR_PIN30_Output (0x1UL) /*!< Read: pin set as output */
8337 #define GPIO_DIRCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8338 
8339 /* Bit 29 : Set as input pin 29 */
8340 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
8341 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
8342 #define GPIO_DIRCLR_PIN29_Input (0x0UL) /*!< Read: pin set as input */
8343 #define GPIO_DIRCLR_PIN29_Output (0x1UL) /*!< Read: pin set as output */
8344 #define GPIO_DIRCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8345 
8346 /* Bit 28 : Set as input pin 28 */
8347 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
8348 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
8349 #define GPIO_DIRCLR_PIN28_Input (0x0UL) /*!< Read: pin set as input */
8350 #define GPIO_DIRCLR_PIN28_Output (0x1UL) /*!< Read: pin set as output */
8351 #define GPIO_DIRCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8352 
8353 /* Bit 27 : Set as input pin 27 */
8354 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
8355 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
8356 #define GPIO_DIRCLR_PIN27_Input (0x0UL) /*!< Read: pin set as input */
8357 #define GPIO_DIRCLR_PIN27_Output (0x1UL) /*!< Read: pin set as output */
8358 #define GPIO_DIRCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8359 
8360 /* Bit 26 : Set as input pin 26 */
8361 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
8362 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
8363 #define GPIO_DIRCLR_PIN26_Input (0x0UL) /*!< Read: pin set as input */
8364 #define GPIO_DIRCLR_PIN26_Output (0x1UL) /*!< Read: pin set as output */
8365 #define GPIO_DIRCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8366 
8367 /* Bit 25 : Set as input pin 25 */
8368 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
8369 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
8370 #define GPIO_DIRCLR_PIN25_Input (0x0UL) /*!< Read: pin set as input */
8371 #define GPIO_DIRCLR_PIN25_Output (0x1UL) /*!< Read: pin set as output */
8372 #define GPIO_DIRCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8373 
8374 /* Bit 24 : Set as input pin 24 */
8375 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
8376 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
8377 #define GPIO_DIRCLR_PIN24_Input (0x0UL) /*!< Read: pin set as input */
8378 #define GPIO_DIRCLR_PIN24_Output (0x1UL) /*!< Read: pin set as output */
8379 #define GPIO_DIRCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8380 
8381 /* Bit 23 : Set as input pin 23 */
8382 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
8383 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
8384 #define GPIO_DIRCLR_PIN23_Input (0x0UL) /*!< Read: pin set as input */
8385 #define GPIO_DIRCLR_PIN23_Output (0x1UL) /*!< Read: pin set as output */
8386 #define GPIO_DIRCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8387 
8388 /* Bit 22 : Set as input pin 22 */
8389 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
8390 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
8391 #define GPIO_DIRCLR_PIN22_Input (0x0UL) /*!< Read: pin set as input */
8392 #define GPIO_DIRCLR_PIN22_Output (0x1UL) /*!< Read: pin set as output */
8393 #define GPIO_DIRCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8394 
8395 /* Bit 21 : Set as input pin 21 */
8396 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
8397 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
8398 #define GPIO_DIRCLR_PIN21_Input (0x0UL) /*!< Read: pin set as input */
8399 #define GPIO_DIRCLR_PIN21_Output (0x1UL) /*!< Read: pin set as output */
8400 #define GPIO_DIRCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8401 
8402 /* Bit 20 : Set as input pin 20 */
8403 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
8404 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
8405 #define GPIO_DIRCLR_PIN20_Input (0x0UL) /*!< Read: pin set as input */
8406 #define GPIO_DIRCLR_PIN20_Output (0x1UL) /*!< Read: pin set as output */
8407 #define GPIO_DIRCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8408 
8409 /* Bit 19 : Set as input pin 19 */
8410 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
8411 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
8412 #define GPIO_DIRCLR_PIN19_Input (0x0UL) /*!< Read: pin set as input */
8413 #define GPIO_DIRCLR_PIN19_Output (0x1UL) /*!< Read: pin set as output */
8414 #define GPIO_DIRCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8415 
8416 /* Bit 18 : Set as input pin 18 */
8417 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
8418 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
8419 #define GPIO_DIRCLR_PIN18_Input (0x0UL) /*!< Read: pin set as input */
8420 #define GPIO_DIRCLR_PIN18_Output (0x1UL) /*!< Read: pin set as output */
8421 #define GPIO_DIRCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8422 
8423 /* Bit 17 : Set as input pin 17 */
8424 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
8425 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
8426 #define GPIO_DIRCLR_PIN17_Input (0x0UL) /*!< Read: pin set as input */
8427 #define GPIO_DIRCLR_PIN17_Output (0x1UL) /*!< Read: pin set as output */
8428 #define GPIO_DIRCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8429 
8430 /* Bit 16 : Set as input pin 16 */
8431 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
8432 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
8433 #define GPIO_DIRCLR_PIN16_Input (0x0UL) /*!< Read: pin set as input */
8434 #define GPIO_DIRCLR_PIN16_Output (0x1UL) /*!< Read: pin set as output */
8435 #define GPIO_DIRCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8436 
8437 /* Bit 15 : Set as input pin 15 */
8438 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
8439 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
8440 #define GPIO_DIRCLR_PIN15_Input (0x0UL) /*!< Read: pin set as input */
8441 #define GPIO_DIRCLR_PIN15_Output (0x1UL) /*!< Read: pin set as output */
8442 #define GPIO_DIRCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8443 
8444 /* Bit 14 : Set as input pin 14 */
8445 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
8446 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
8447 #define GPIO_DIRCLR_PIN14_Input (0x0UL) /*!< Read: pin set as input */
8448 #define GPIO_DIRCLR_PIN14_Output (0x1UL) /*!< Read: pin set as output */
8449 #define GPIO_DIRCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8450 
8451 /* Bit 13 : Set as input pin 13 */
8452 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
8453 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
8454 #define GPIO_DIRCLR_PIN13_Input (0x0UL) /*!< Read: pin set as input */
8455 #define GPIO_DIRCLR_PIN13_Output (0x1UL) /*!< Read: pin set as output */
8456 #define GPIO_DIRCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8457 
8458 /* Bit 12 : Set as input pin 12 */
8459 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
8460 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
8461 #define GPIO_DIRCLR_PIN12_Input (0x0UL) /*!< Read: pin set as input */
8462 #define GPIO_DIRCLR_PIN12_Output (0x1UL) /*!< Read: pin set as output */
8463 #define GPIO_DIRCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8464 
8465 /* Bit 11 : Set as input pin 11 */
8466 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
8467 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
8468 #define GPIO_DIRCLR_PIN11_Input (0x0UL) /*!< Read: pin set as input */
8469 #define GPIO_DIRCLR_PIN11_Output (0x1UL) /*!< Read: pin set as output */
8470 #define GPIO_DIRCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8471 
8472 /* Bit 10 : Set as input pin 10 */
8473 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
8474 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
8475 #define GPIO_DIRCLR_PIN10_Input (0x0UL) /*!< Read: pin set as input */
8476 #define GPIO_DIRCLR_PIN10_Output (0x1UL) /*!< Read: pin set as output */
8477 #define GPIO_DIRCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8478 
8479 /* Bit 9 : Set as input pin 9 */
8480 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
8481 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
8482 #define GPIO_DIRCLR_PIN9_Input (0x0UL) /*!< Read: pin set as input */
8483 #define GPIO_DIRCLR_PIN9_Output (0x1UL) /*!< Read: pin set as output */
8484 #define GPIO_DIRCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8485 
8486 /* Bit 8 : Set as input pin 8 */
8487 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
8488 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
8489 #define GPIO_DIRCLR_PIN8_Input (0x0UL) /*!< Read: pin set as input */
8490 #define GPIO_DIRCLR_PIN8_Output (0x1UL) /*!< Read: pin set as output */
8491 #define GPIO_DIRCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8492 
8493 /* Bit 7 : Set as input pin 7 */
8494 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
8495 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
8496 #define GPIO_DIRCLR_PIN7_Input (0x0UL) /*!< Read: pin set as input */
8497 #define GPIO_DIRCLR_PIN7_Output (0x1UL) /*!< Read: pin set as output */
8498 #define GPIO_DIRCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8499 
8500 /* Bit 6 : Set as input pin 6 */
8501 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
8502 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
8503 #define GPIO_DIRCLR_PIN6_Input (0x0UL) /*!< Read: pin set as input */
8504 #define GPIO_DIRCLR_PIN6_Output (0x1UL) /*!< Read: pin set as output */
8505 #define GPIO_DIRCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8506 
8507 /* Bit 5 : Set as input pin 5 */
8508 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
8509 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
8510 #define GPIO_DIRCLR_PIN5_Input (0x0UL) /*!< Read: pin set as input */
8511 #define GPIO_DIRCLR_PIN5_Output (0x1UL) /*!< Read: pin set as output */
8512 #define GPIO_DIRCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8513 
8514 /* Bit 4 : Set as input pin 4 */
8515 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
8516 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
8517 #define GPIO_DIRCLR_PIN4_Input (0x0UL) /*!< Read: pin set as input */
8518 #define GPIO_DIRCLR_PIN4_Output (0x1UL) /*!< Read: pin set as output */
8519 #define GPIO_DIRCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8520 
8521 /* Bit 3 : Set as input pin 3 */
8522 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
8523 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
8524 #define GPIO_DIRCLR_PIN3_Input (0x0UL) /*!< Read: pin set as input */
8525 #define GPIO_DIRCLR_PIN3_Output (0x1UL) /*!< Read: pin set as output */
8526 #define GPIO_DIRCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8527 
8528 /* Bit 2 : Set as input pin 2 */
8529 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
8530 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
8531 #define GPIO_DIRCLR_PIN2_Input (0x0UL) /*!< Read: pin set as input */
8532 #define GPIO_DIRCLR_PIN2_Output (0x1UL) /*!< Read: pin set as output */
8533 #define GPIO_DIRCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8534 
8535 /* Bit 1 : Set as input pin 1 */
8536 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
8537 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
8538 #define GPIO_DIRCLR_PIN1_Input (0x0UL) /*!< Read: pin set as input */
8539 #define GPIO_DIRCLR_PIN1_Output (0x1UL) /*!< Read: pin set as output */
8540 #define GPIO_DIRCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8541 
8542 /* Bit 0 : Set as input pin 0 */
8543 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
8544 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
8545 #define GPIO_DIRCLR_PIN0_Input (0x0UL) /*!< Read: pin set as input */
8546 #define GPIO_DIRCLR_PIN0_Output (0x1UL) /*!< Read: pin set as output */
8547 #define GPIO_DIRCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8548 
8549 /* Register: GPIO_LATCH */
8550 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
8551 
8552 /* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */
8553 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
8554 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
8555 #define GPIO_LATCH_PIN31_NotLatched (0x0UL) /*!< Criteria has not been met */
8556 #define GPIO_LATCH_PIN31_Latched (0x1UL) /*!< Criteria has been met */
8557 
8558 /* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */
8559 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
8560 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
8561 #define GPIO_LATCH_PIN30_NotLatched (0x0UL) /*!< Criteria has not been met */
8562 #define GPIO_LATCH_PIN30_Latched (0x1UL) /*!< Criteria has been met */
8563 
8564 /* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */
8565 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
8566 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
8567 #define GPIO_LATCH_PIN29_NotLatched (0x0UL) /*!< Criteria has not been met */
8568 #define GPIO_LATCH_PIN29_Latched (0x1UL) /*!< Criteria has been met */
8569 
8570 /* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */
8571 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
8572 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
8573 #define GPIO_LATCH_PIN28_NotLatched (0x0UL) /*!< Criteria has not been met */
8574 #define GPIO_LATCH_PIN28_Latched (0x1UL) /*!< Criteria has been met */
8575 
8576 /* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */
8577 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
8578 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
8579 #define GPIO_LATCH_PIN27_NotLatched (0x0UL) /*!< Criteria has not been met */
8580 #define GPIO_LATCH_PIN27_Latched (0x1UL) /*!< Criteria has been met */
8581 
8582 /* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */
8583 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
8584 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
8585 #define GPIO_LATCH_PIN26_NotLatched (0x0UL) /*!< Criteria has not been met */
8586 #define GPIO_LATCH_PIN26_Latched (0x1UL) /*!< Criteria has been met */
8587 
8588 /* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */
8589 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
8590 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
8591 #define GPIO_LATCH_PIN25_NotLatched (0x0UL) /*!< Criteria has not been met */
8592 #define GPIO_LATCH_PIN25_Latched (0x1UL) /*!< Criteria has been met */
8593 
8594 /* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */
8595 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
8596 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
8597 #define GPIO_LATCH_PIN24_NotLatched (0x0UL) /*!< Criteria has not been met */
8598 #define GPIO_LATCH_PIN24_Latched (0x1UL) /*!< Criteria has been met */
8599 
8600 /* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */
8601 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
8602 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
8603 #define GPIO_LATCH_PIN23_NotLatched (0x0UL) /*!< Criteria has not been met */
8604 #define GPIO_LATCH_PIN23_Latched (0x1UL) /*!< Criteria has been met */
8605 
8606 /* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */
8607 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
8608 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
8609 #define GPIO_LATCH_PIN22_NotLatched (0x0UL) /*!< Criteria has not been met */
8610 #define GPIO_LATCH_PIN22_Latched (0x1UL) /*!< Criteria has been met */
8611 
8612 /* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */
8613 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
8614 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
8615 #define GPIO_LATCH_PIN21_NotLatched (0x0UL) /*!< Criteria has not been met */
8616 #define GPIO_LATCH_PIN21_Latched (0x1UL) /*!< Criteria has been met */
8617 
8618 /* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */
8619 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
8620 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
8621 #define GPIO_LATCH_PIN20_NotLatched (0x0UL) /*!< Criteria has not been met */
8622 #define GPIO_LATCH_PIN20_Latched (0x1UL) /*!< Criteria has been met */
8623 
8624 /* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */
8625 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
8626 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
8627 #define GPIO_LATCH_PIN19_NotLatched (0x0UL) /*!< Criteria has not been met */
8628 #define GPIO_LATCH_PIN19_Latched (0x1UL) /*!< Criteria has been met */
8629 
8630 /* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */
8631 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
8632 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
8633 #define GPIO_LATCH_PIN18_NotLatched (0x0UL) /*!< Criteria has not been met */
8634 #define GPIO_LATCH_PIN18_Latched (0x1UL) /*!< Criteria has been met */
8635 
8636 /* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */
8637 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
8638 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
8639 #define GPIO_LATCH_PIN17_NotLatched (0x0UL) /*!< Criteria has not been met */
8640 #define GPIO_LATCH_PIN17_Latched (0x1UL) /*!< Criteria has been met */
8641 
8642 /* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */
8643 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
8644 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
8645 #define GPIO_LATCH_PIN16_NotLatched (0x0UL) /*!< Criteria has not been met */
8646 #define GPIO_LATCH_PIN16_Latched (0x1UL) /*!< Criteria has been met */
8647 
8648 /* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */
8649 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
8650 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
8651 #define GPIO_LATCH_PIN15_NotLatched (0x0UL) /*!< Criteria has not been met */
8652 #define GPIO_LATCH_PIN15_Latched (0x1UL) /*!< Criteria has been met */
8653 
8654 /* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */
8655 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
8656 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
8657 #define GPIO_LATCH_PIN14_NotLatched (0x0UL) /*!< Criteria has not been met */
8658 #define GPIO_LATCH_PIN14_Latched (0x1UL) /*!< Criteria has been met */
8659 
8660 /* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */
8661 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
8662 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
8663 #define GPIO_LATCH_PIN13_NotLatched (0x0UL) /*!< Criteria has not been met */
8664 #define GPIO_LATCH_PIN13_Latched (0x1UL) /*!< Criteria has been met */
8665 
8666 /* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */
8667 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
8668 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
8669 #define GPIO_LATCH_PIN12_NotLatched (0x0UL) /*!< Criteria has not been met */
8670 #define GPIO_LATCH_PIN12_Latched (0x1UL) /*!< Criteria has been met */
8671 
8672 /* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */
8673 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
8674 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
8675 #define GPIO_LATCH_PIN11_NotLatched (0x0UL) /*!< Criteria has not been met */
8676 #define GPIO_LATCH_PIN11_Latched (0x1UL) /*!< Criteria has been met */
8677 
8678 /* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */
8679 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
8680 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
8681 #define GPIO_LATCH_PIN10_NotLatched (0x0UL) /*!< Criteria has not been met */
8682 #define GPIO_LATCH_PIN10_Latched (0x1UL) /*!< Criteria has been met */
8683 
8684 /* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */
8685 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
8686 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
8687 #define GPIO_LATCH_PIN9_NotLatched (0x0UL) /*!< Criteria has not been met */
8688 #define GPIO_LATCH_PIN9_Latched (0x1UL) /*!< Criteria has been met */
8689 
8690 /* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */
8691 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
8692 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
8693 #define GPIO_LATCH_PIN8_NotLatched (0x0UL) /*!< Criteria has not been met */
8694 #define GPIO_LATCH_PIN8_Latched (0x1UL) /*!< Criteria has been met */
8695 
8696 /* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */
8697 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
8698 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
8699 #define GPIO_LATCH_PIN7_NotLatched (0x0UL) /*!< Criteria has not been met */
8700 #define GPIO_LATCH_PIN7_Latched (0x1UL) /*!< Criteria has been met */
8701 
8702 /* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */
8703 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
8704 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
8705 #define GPIO_LATCH_PIN6_NotLatched (0x0UL) /*!< Criteria has not been met */
8706 #define GPIO_LATCH_PIN6_Latched (0x1UL) /*!< Criteria has been met */
8707 
8708 /* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */
8709 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
8710 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
8711 #define GPIO_LATCH_PIN5_NotLatched (0x0UL) /*!< Criteria has not been met */
8712 #define GPIO_LATCH_PIN5_Latched (0x1UL) /*!< Criteria has been met */
8713 
8714 /* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */
8715 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
8716 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
8717 #define GPIO_LATCH_PIN4_NotLatched (0x0UL) /*!< Criteria has not been met */
8718 #define GPIO_LATCH_PIN4_Latched (0x1UL) /*!< Criteria has been met */
8719 
8720 /* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */
8721 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
8722 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
8723 #define GPIO_LATCH_PIN3_NotLatched (0x0UL) /*!< Criteria has not been met */
8724 #define GPIO_LATCH_PIN3_Latched (0x1UL) /*!< Criteria has been met */
8725 
8726 /* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */
8727 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
8728 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
8729 #define GPIO_LATCH_PIN2_NotLatched (0x0UL) /*!< Criteria has not been met */
8730 #define GPIO_LATCH_PIN2_Latched (0x1UL) /*!< Criteria has been met */
8731 
8732 /* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */
8733 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
8734 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
8735 #define GPIO_LATCH_PIN1_NotLatched (0x0UL) /*!< Criteria has not been met */
8736 #define GPIO_LATCH_PIN1_Latched (0x1UL) /*!< Criteria has been met */
8737 
8738 /* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */
8739 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
8740 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
8741 #define GPIO_LATCH_PIN0_NotLatched (0x0UL) /*!< Criteria has not been met */
8742 #define GPIO_LATCH_PIN0_Latched (0x1UL) /*!< Criteria has been met */
8743 
8744 /* Register: GPIO_DETECTMODE */
8745 /* Description: Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) */
8746 
8747 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
8748 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
8749 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
8750 #define GPIO_DETECTMODE_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */
8751 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */
8752 
8753 /* Register: GPIO_DETECTMODE_SEC */
8754 /* Description: Select between default DETECT signal behavior and LDETECT mode (For secure pin only) */
8755 
8756 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
8757 #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
8758 #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
8759 #define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */
8760 #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */
8761 
8762 /* Register: GPIO_PIN_CNF */
8763 /* Description: Description collection: Configuration of GPIO pins */
8764 
8765 /* Bits 17..16 : Pin sensing mechanism */
8766 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
8767 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
8768 #define GPIO_PIN_CNF_SENSE_Disabled (0x0UL) /*!< Disabled */
8769 #define GPIO_PIN_CNF_SENSE_High (0x2UL) /*!< Sense for high level */
8770 #define GPIO_PIN_CNF_SENSE_Low (0x3UL) /*!< Sense for low level */
8771 
8772 /* Bits 10..8 : Drive configuration */
8773 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
8774 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
8775 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x0UL) /*!< Standard '0', standard '1' */
8776 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x1UL) /*!< High drive '0', standard '1' */
8777 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x2UL) /*!< Standard '0', high drive '1' */
8778 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x3UL) /*!< High drive '0', high 'drive '1'' */
8779 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */
8780 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
8781 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */
8782 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
8783 
8784 /* Bits 3..2 : Pull configuration */
8785 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
8786 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
8787 #define GPIO_PIN_CNF_PULL_Disabled (0x0UL) /*!< No pull */
8788 #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull down on pin */
8789 #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull up on pin */
8790 
8791 /* Bit 1 : Connect or disconnect input buffer */
8792 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
8793 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
8794 #define GPIO_PIN_CNF_INPUT_Connect (0x0UL) /*!< Connect input buffer */
8795 #define GPIO_PIN_CNF_INPUT_Disconnect (0x1UL) /*!< Disconnect input buffer */
8796 
8797 /* Bit 0 : Pin direction. Same physical register as DIR register */
8798 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
8799 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
8800 #define GPIO_PIN_CNF_DIR_Input (0x0UL) /*!< Configure pin as an input pin */
8801 #define GPIO_PIN_CNF_DIR_Output (0x1UL) /*!< Configure pin as an output pin */
8802 
8803 
8804 /* Peripheral: PDM */
8805 /* Description: Pulse Density Modulation (Digital Microphone) Interface 0 */
8806 
8807 /* Register: PDM_TASKS_START */
8808 /* Description: Starts continuous PDM transfer */
8809 
8810 /* Bit 0 : Starts continuous PDM transfer */
8811 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8812 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8813 #define PDM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
8814 
8815 /* Register: PDM_TASKS_STOP */
8816 /* Description: Stops PDM transfer */
8817 
8818 /* Bit 0 : Stops PDM transfer */
8819 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8820 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8821 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
8822 
8823 /* Register: PDM_SUBSCRIBE_START */
8824 /* Description: Subscribe configuration for task START */
8825 
8826 /* Bit 31 :   */
8827 #define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
8828 #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
8829 #define PDM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
8830 #define PDM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */
8831 
8832 /* Bits 7..0 : DPPI channel that task START will subscribe to */
8833 #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8834 #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8835 
8836 /* Register: PDM_SUBSCRIBE_STOP */
8837 /* Description: Subscribe configuration for task STOP */
8838 
8839 /* Bit 31 :   */
8840 #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
8841 #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
8842 #define PDM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
8843 #define PDM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */
8844 
8845 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
8846 #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8847 #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8848 
8849 /* Register: PDM_EVENTS_STARTED */
8850 /* Description: PDM transfer has started */
8851 
8852 /* Bit 0 : PDM transfer has started */
8853 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
8854 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
8855 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
8856 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */
8857 
8858 /* Register: PDM_EVENTS_STOPPED */
8859 /* Description: PDM transfer has finished */
8860 
8861 /* Bit 0 : PDM transfer has finished */
8862 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8863 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8864 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
8865 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
8866 
8867 /* Register: PDM_EVENTS_END */
8868 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
8869 
8870 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
8871 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
8872 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
8873 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
8874 #define PDM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */
8875 
8876 /* Register: PDM_PUBLISH_STARTED */
8877 /* Description: Publish configuration for event STARTED */
8878 
8879 /* Bit 31 :   */
8880 #define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
8881 #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
8882 #define PDM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
8883 #define PDM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
8884 
8885 /* Bits 7..0 : DPPI channel that event STARTED will publish to */
8886 #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8887 #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8888 
8889 /* Register: PDM_PUBLISH_STOPPED */
8890 /* Description: Publish configuration for event STOPPED */
8891 
8892 /* Bit 31 :   */
8893 #define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
8894 #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
8895 #define PDM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
8896 #define PDM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */
8897 
8898 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
8899 #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8900 #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8901 
8902 /* Register: PDM_PUBLISH_END */
8903 /* Description: Publish configuration for event END */
8904 
8905 /* Bit 31 :   */
8906 #define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
8907 #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
8908 #define PDM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */
8909 #define PDM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */
8910 
8911 /* Bits 7..0 : DPPI channel that event END will publish to */
8912 #define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8913 #define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8914 
8915 /* Register: PDM_INTEN */
8916 /* Description: Enable or disable interrupt */
8917 
8918 /* Bit 2 : Enable or disable interrupt for event END */
8919 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
8920 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
8921 #define PDM_INTEN_END_Disabled (0x0UL) /*!< Disable */
8922 #define PDM_INTEN_END_Enabled (0x1UL) /*!< Enable */
8923 
8924 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8925 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8926 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8927 #define PDM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
8928 #define PDM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
8929 
8930 /* Bit 0 : Enable or disable interrupt for event STARTED */
8931 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
8932 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
8933 #define PDM_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */
8934 #define PDM_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */
8935 
8936 /* Register: PDM_INTENSET */
8937 /* Description: Enable interrupt */
8938 
8939 /* Bit 2 : Write '1' to enable interrupt for event END */
8940 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
8941 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
8942 #define PDM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
8943 #define PDM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
8944 #define PDM_INTENSET_END_Set (0x1UL) /*!< Enable */
8945 
8946 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
8947 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8948 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8949 #define PDM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
8950 #define PDM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
8951 #define PDM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
8952 
8953 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
8954 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
8955 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
8956 #define PDM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
8957 #define PDM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
8958 #define PDM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */
8959 
8960 /* Register: PDM_INTENCLR */
8961 /* Description: Disable interrupt */
8962 
8963 /* Bit 2 : Write '1' to disable interrupt for event END */
8964 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
8965 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
8966 #define PDM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
8967 #define PDM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
8968 #define PDM_INTENCLR_END_Clear (0x1UL) /*!< Disable */
8969 
8970 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
8971 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8972 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8973 #define PDM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
8974 #define PDM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
8975 #define PDM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
8976 
8977 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
8978 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
8979 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
8980 #define PDM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
8981 #define PDM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
8982 #define PDM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */
8983 
8984 /* Register: PDM_ENABLE */
8985 /* Description: PDM module enable register */
8986 
8987 /* Bit 0 : Enable or disable PDM module */
8988 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8989 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8990 #define PDM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
8991 #define PDM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */
8992 
8993 /* Register: PDM_PDMCLKCTRL */
8994 /* Description: PDM clock generator control */
8995 
8996 /* Bits 31..0 : PDM_CLK frequency configuration. */
8997 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
8998 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
8999 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
9000 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
9001 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
9002 #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
9003 #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
9004 #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
9005 
9006 /* Register: PDM_MODE */
9007 /* Description: Defines the routing of the connected PDM microphones' signals */
9008 
9009 /* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */
9010 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
9011 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
9012 #define PDM_MODE_EDGE_LeftFalling (0x0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
9013 #define PDM_MODE_EDGE_LeftRising (0x1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
9014 
9015 /* Bit 0 : Mono or stereo operation */
9016 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
9017 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
9018 #define PDM_MODE_OPERATION_Stereo (0x0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */
9019 #define PDM_MODE_OPERATION_Mono (0x1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */
9020 
9021 /* Register: PDM_GAINL */
9022 /* Description: Left output gain adjustment */
9023 
9024 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
9025 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
9026 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
9027 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
9028 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
9029 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
9030 
9031 /* Register: PDM_GAINR */
9032 /* Description: Right output gain adjustment */
9033 
9034 /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
9035 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
9036 #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
9037 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
9038 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
9039 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
9040 
9041 /* Register: PDM_RATIO */
9042 /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
9043 
9044 /* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
9045 #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
9046 #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
9047 #define PDM_RATIO_RATIO_Ratio64 (0x0UL) /*!< Ratio of 64 */
9048 #define PDM_RATIO_RATIO_Ratio80 (0x1UL) /*!< Ratio of 80 */
9049 
9050 /* Register: PDM_PSEL_CLK */
9051 /* Description: Pin number configuration for PDM CLK signal */
9052 
9053 /* Bit 31 : Connection */
9054 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9055 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9056 #define PDM_PSEL_CLK_CONNECT_Connected (0x0UL) /*!< Connect */
9057 #define PDM_PSEL_CLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
9058 
9059 /* Bits 4..0 : Pin number */
9060 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
9061 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
9062 
9063 /* Register: PDM_PSEL_DIN */
9064 /* Description: Pin number configuration for PDM DIN signal */
9065 
9066 /* Bit 31 : Connection */
9067 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9068 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9069 #define PDM_PSEL_DIN_CONNECT_Connected (0x0UL) /*!< Connect */
9070 #define PDM_PSEL_DIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
9071 
9072 /* Bits 4..0 : Pin number */
9073 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
9074 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
9075 
9076 /* Register: PDM_SAMPLE_PTR */
9077 /* Description: RAM address pointer to write samples to with EasyDMA */
9078 
9079 /* Bits 31..0 : Address to write PDM samples to over DMA */
9080 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
9081 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
9082 
9083 /* Register: PDM_SAMPLE_MAXCNT */
9084 /* Description: Number of samples to allocate memory for in EasyDMA mode */
9085 
9086 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
9087 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
9088 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
9089 
9090 
9091 /* Peripheral: POWER */
9092 /* Description: Power control 0 */
9093 
9094 /* Register: POWER_TASKS_PWMREQSTART */
9095 /* Description: Request forcing PWM mode in PMIC DC/DC buck regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). */
9096 
9097 /* Bit 0 : Request forcing PWM mode in PMIC DC/DC buck regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). */
9098 #define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Pos (0UL) /*!< Position of TASKS_PWMREQSTART field. */
9099 #define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Msk (0x1UL << POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Pos) /*!< Bit mask of TASKS_PWMREQSTART field. */
9100 #define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Trigger (0x1UL) /*!< Trigger task */
9101 
9102 /* Register: POWER_TASKS_PWMREQSTOP */
9103 /* Description: Stop requesting forcing PWM mode in PMIC DC/DC buck regulator */
9104 
9105 /* Bit 0 : Stop requesting forcing PWM mode in PMIC DC/DC buck regulator */
9106 #define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Pos (0UL) /*!< Position of TASKS_PWMREQSTOP field. */
9107 #define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Msk (0x1UL << POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Pos) /*!< Bit mask of TASKS_PWMREQSTOP field. */
9108 #define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Trigger (0x1UL) /*!< Trigger task */
9109 
9110 /* Register: POWER_TASKS_CONSTLAT */
9111 /* Description: Enable constant latency mode. */
9112 
9113 /* Bit 0 : Enable constant latency mode. */
9114 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
9115 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
9116 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (0x1UL) /*!< Trigger task */
9117 
9118 /* Register: POWER_TASKS_LOWPWR */
9119 /* Description: Enable low power mode (variable latency) */
9120 
9121 /* Bit 0 : Enable low power mode (variable latency) */
9122 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
9123 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
9124 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (0x1UL) /*!< Trigger task */
9125 
9126 /* Register: POWER_SUBSCRIBE_PWMREQSTART */
9127 /* Description: Subscribe configuration for task PWMREQSTART */
9128 
9129 /* Bit 31 :   */
9130 #define POWER_SUBSCRIBE_PWMREQSTART_EN_Pos (31UL) /*!< Position of EN field. */
9131 #define POWER_SUBSCRIBE_PWMREQSTART_EN_Msk (0x1UL << POWER_SUBSCRIBE_PWMREQSTART_EN_Pos) /*!< Bit mask of EN field. */
9132 #define POWER_SUBSCRIBE_PWMREQSTART_EN_Disabled (0x0UL) /*!< Disable subscription */
9133 #define POWER_SUBSCRIBE_PWMREQSTART_EN_Enabled (0x1UL) /*!< Enable subscription */
9134 
9135 /* Bits 7..0 : DPPI channel that task PWMREQSTART will subscribe to */
9136 #define POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9137 #define POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9138 
9139 /* Register: POWER_SUBSCRIBE_PWMREQSTOP */
9140 /* Description: Subscribe configuration for task PWMREQSTOP */
9141 
9142 /* Bit 31 :   */
9143 #define POWER_SUBSCRIBE_PWMREQSTOP_EN_Pos (31UL) /*!< Position of EN field. */
9144 #define POWER_SUBSCRIBE_PWMREQSTOP_EN_Msk (0x1UL << POWER_SUBSCRIBE_PWMREQSTOP_EN_Pos) /*!< Bit mask of EN field. */
9145 #define POWER_SUBSCRIBE_PWMREQSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */
9146 #define POWER_SUBSCRIBE_PWMREQSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */
9147 
9148 /* Bits 7..0 : DPPI channel that task PWMREQSTOP will subscribe to */
9149 #define POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9150 #define POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9151 
9152 /* Register: POWER_SUBSCRIBE_CONSTLAT */
9153 /* Description: Subscribe configuration for task CONSTLAT */
9154 
9155 /* Bit 31 :   */
9156 #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */
9157 #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */
9158 #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0x0UL) /*!< Disable subscription */
9159 #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (0x1UL) /*!< Enable subscription */
9160 
9161 /* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */
9162 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9163 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9164 
9165 /* Register: POWER_SUBSCRIBE_LOWPWR */
9166 /* Description: Subscribe configuration for task LOWPWR */
9167 
9168 /* Bit 31 :   */
9169 #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */
9170 #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */
9171 #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0x0UL) /*!< Disable subscription */
9172 #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (0x1UL) /*!< Enable subscription */
9173 
9174 /* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */
9175 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9176 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9177 
9178 /* Register: POWER_EVENTS_POFWARN */
9179 /* Description: Power failure warning */
9180 
9181 /* Bit 0 : Power failure warning */
9182 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
9183 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
9184 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0x0UL) /*!< Event not generated */
9185 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (0x1UL) /*!< Event generated */
9186 
9187 /* Register: POWER_EVENTS_SLEEPENTER */
9188 /* Description: CPU entered WFI/WFE sleep */
9189 
9190 /* Bit 0 : CPU entered WFI/WFE sleep */
9191 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
9192 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
9193 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0x0UL) /*!< Event not generated */
9194 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (0x1UL) /*!< Event generated */
9195 
9196 /* Register: POWER_EVENTS_SLEEPEXIT */
9197 /* Description: CPU exited WFI/WFE sleep */
9198 
9199 /* Bit 0 : CPU exited WFI/WFE sleep */
9200 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
9201 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
9202 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0x0UL) /*!< Event not generated */
9203 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (0x1UL) /*!< Event generated */
9204 
9205 /* Register: POWER_PUBLISH_POFWARN */
9206 /* Description: Publish configuration for event POFWARN */
9207 
9208 /* Bit 31 :   */
9209 #define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */
9210 #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */
9211 #define POWER_PUBLISH_POFWARN_EN_Disabled (0x0UL) /*!< Disable publishing */
9212 #define POWER_PUBLISH_POFWARN_EN_Enabled (0x1UL) /*!< Enable publishing */
9213 
9214 /* Bits 7..0 : DPPI channel that event POFWARN will publish to */
9215 #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9216 #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9217 
9218 /* Register: POWER_PUBLISH_SLEEPENTER */
9219 /* Description: Publish configuration for event SLEEPENTER */
9220 
9221 /* Bit 31 :   */
9222 #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */
9223 #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */
9224 #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0x0UL) /*!< Disable publishing */
9225 #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (0x1UL) /*!< Enable publishing */
9226 
9227 /* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to */
9228 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9229 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9230 
9231 /* Register: POWER_PUBLISH_SLEEPEXIT */
9232 /* Description: Publish configuration for event SLEEPEXIT */
9233 
9234 /* Bit 31 :   */
9235 #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */
9236 #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */
9237 #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0x0UL) /*!< Disable publishing */
9238 #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (0x1UL) /*!< Enable publishing */
9239 
9240 /* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to */
9241 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9242 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9243 
9244 /* Register: POWER_INTEN */
9245 /* Description: Enable or disable interrupt */
9246 
9247 /* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */
9248 #define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
9249 #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
9250 #define POWER_INTEN_SLEEPEXIT_Disabled (0x0UL) /*!< Disable */
9251 #define POWER_INTEN_SLEEPEXIT_Enabled (0x1UL) /*!< Enable */
9252 
9253 /* Bit 5 : Enable or disable interrupt for event SLEEPENTER */
9254 #define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
9255 #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
9256 #define POWER_INTEN_SLEEPENTER_Disabled (0x0UL) /*!< Disable */
9257 #define POWER_INTEN_SLEEPENTER_Enabled (0x1UL) /*!< Enable */
9258 
9259 /* Bit 2 : Enable or disable interrupt for event POFWARN */
9260 #define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
9261 #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
9262 #define POWER_INTEN_POFWARN_Disabled (0x0UL) /*!< Disable */
9263 #define POWER_INTEN_POFWARN_Enabled (0x1UL) /*!< Enable */
9264 
9265 /* Register: POWER_INTENSET */
9266 /* Description: Enable interrupt */
9267 
9268 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
9269 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
9270 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
9271 #define POWER_INTENSET_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */
9272 #define POWER_INTENSET_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */
9273 #define POWER_INTENSET_SLEEPEXIT_Set (0x1UL) /*!< Enable */
9274 
9275 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
9276 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
9277 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
9278 #define POWER_INTENSET_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */
9279 #define POWER_INTENSET_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */
9280 #define POWER_INTENSET_SLEEPENTER_Set (0x1UL) /*!< Enable */
9281 
9282 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
9283 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
9284 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
9285 #define POWER_INTENSET_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */
9286 #define POWER_INTENSET_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */
9287 #define POWER_INTENSET_POFWARN_Set (0x1UL) /*!< Enable */
9288 
9289 /* Register: POWER_INTENCLR */
9290 /* Description: Disable interrupt */
9291 
9292 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
9293 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
9294 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
9295 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */
9296 #define POWER_INTENCLR_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */
9297 #define POWER_INTENCLR_SLEEPEXIT_Clear (0x1UL) /*!< Disable */
9298 
9299 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
9300 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
9301 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
9302 #define POWER_INTENCLR_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */
9303 #define POWER_INTENCLR_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */
9304 #define POWER_INTENCLR_SLEEPENTER_Clear (0x1UL) /*!< Disable */
9305 
9306 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
9307 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
9308 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
9309 #define POWER_INTENCLR_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */
9310 #define POWER_INTENCLR_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */
9311 #define POWER_INTENCLR_POFWARN_Clear (0x1UL) /*!< Disable */
9312 
9313 /* Register: POWER_RESETREAS */
9314 /* Description: Reset reason */
9315 
9316 /* Bit 18 : Reset triggered through CTRL-AP */
9317 #define POWER_RESETREAS_CTRLAP_Pos (18UL) /*!< Position of CTRLAP field. */
9318 #define POWER_RESETREAS_CTRLAP_Msk (0x1UL << POWER_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */
9319 #define POWER_RESETREAS_CTRLAP_NotDetected (0x0UL) /*!< Not detected */
9320 #define POWER_RESETREAS_CTRLAP_Detected (0x1UL) /*!< Detected */
9321 
9322 /* Bit 17 : Reset from CPU lock-up detected */
9323 #define POWER_RESETREAS_LOCKUP_Pos (17UL) /*!< Position of LOCKUP field. */
9324 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
9325 #define POWER_RESETREAS_LOCKUP_NotDetected (0x0UL) /*!< Not detected */
9326 #define POWER_RESETREAS_LOCKUP_Detected (0x1UL) /*!< Detected */
9327 
9328 /* Bit 16 : Reset from AIRCR.SYSRESETREQ detected */
9329 #define POWER_RESETREAS_SREQ_Pos (16UL) /*!< Position of SREQ field. */
9330 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
9331 #define POWER_RESETREAS_SREQ_NotDetected (0x0UL) /*!< Not detected */
9332 #define POWER_RESETREAS_SREQ_Detected (0x1UL) /*!< Detected */
9333 
9334 /* Bit 4 : Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode */
9335 #define POWER_RESETREAS_DIF_Pos (4UL) /*!< Position of DIF field. */
9336 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
9337 #define POWER_RESETREAS_DIF_NotDetected (0x0UL) /*!< Not detected */
9338 #define POWER_RESETREAS_DIF_Detected (0x1UL) /*!< Detected */
9339 
9340 /* Bit 2 : Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO */
9341 #define POWER_RESETREAS_OFF_Pos (2UL) /*!< Position of OFF field. */
9342 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
9343 #define POWER_RESETREAS_OFF_NotDetected (0x0UL) /*!< Not detected */
9344 #define POWER_RESETREAS_OFF_Detected (0x1UL) /*!< Detected */
9345 
9346 /* Bit 1 : Reset from global watchdog detected */
9347 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
9348 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
9349 #define POWER_RESETREAS_DOG_NotDetected (0x0UL) /*!< Not detected */
9350 #define POWER_RESETREAS_DOG_Detected (0x1UL) /*!< Detected */
9351 
9352 /* Bit 0 : Reset from pin reset detected */
9353 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
9354 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
9355 #define POWER_RESETREAS_RESETPIN_NotDetected (0x0UL) /*!< Not detected */
9356 #define POWER_RESETREAS_RESETPIN_Detected (0x1UL) /*!< Detected */
9357 
9358 /* Register: POWER_POWERSTATUS */
9359 /* Description: Modem domain power status */
9360 
9361 /* Bit 0 : LTE modem domain status */
9362 #define POWER_POWERSTATUS_LTEMODEM_Pos (0UL) /*!< Position of LTEMODEM field. */
9363 #define POWER_POWERSTATUS_LTEMODEM_Msk (0x1UL << POWER_POWERSTATUS_LTEMODEM_Pos) /*!< Bit mask of LTEMODEM field. */
9364 #define POWER_POWERSTATUS_LTEMODEM_OFF (0x0UL) /*!< LTE modem domain is powered off */
9365 #define POWER_POWERSTATUS_LTEMODEM_ON (0x1UL) /*!< LTE modem domain is powered on */
9366 
9367 /* Register: POWER_GPREGRET */
9368 /* Description: Description collection: General purpose retention register */
9369 
9370 /* Bits 7..0 : General purpose retention register */
9371 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
9372 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
9373 
9374 /* Register: POWER_LTEMODEM_STARTN */
9375 /* Description: Start LTE modem */
9376 
9377 /* Bit 0 : Start LTE modem */
9378 #define POWER_LTEMODEM_STARTN_STARTN_Pos (0UL) /*!< Position of STARTN field. */
9379 #define POWER_LTEMODEM_STARTN_STARTN_Msk (0x1UL << POWER_LTEMODEM_STARTN_STARTN_Pos) /*!< Bit mask of STARTN field. */
9380 #define POWER_LTEMODEM_STARTN_STARTN_Start (0x0UL) /*!< Start LTE modem */
9381 #define POWER_LTEMODEM_STARTN_STARTN_Hold (0x1UL) /*!< Hold LTE modem disabled */
9382 
9383 /* Register: POWER_LTEMODEM_FORCEOFF */
9384 /* Description: Force off LTE modem */
9385 
9386 /* Bit 0 : Force off LTE modem */
9387 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
9388 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Msk (0x1UL << POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
9389 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Release (0x0UL) /*!< Release force off */
9390 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Hold (0x1UL) /*!< Hold force off active */
9391 
9392 
9393 /* Peripheral: PWM */
9394 /* Description: Pulse width modulation unit 0 */
9395 
9396 /* Register: PWM_TASKS_STOP */
9397 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
9398 
9399 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
9400 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9401 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9402 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
9403 
9404 /* Register: PWM_TASKS_SEQSTART */
9405 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
9406 
9407 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
9408 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
9409 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
9410 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (0x1UL) /*!< Trigger task */
9411 
9412 /* Register: PWM_TASKS_NEXTSTEP */
9413 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
9414 
9415 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
9416 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
9417 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
9418 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (0x1UL) /*!< Trigger task */
9419 
9420 /* Register: PWM_SUBSCRIBE_STOP */
9421 /* Description: Subscribe configuration for task STOP */
9422 
9423 /* Bit 31 :   */
9424 #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
9425 #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
9426 #define PWM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
9427 #define PWM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */
9428 
9429 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
9430 #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9431 #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9432 
9433 /* Register: PWM_SUBSCRIBE_SEQSTART */
9434 /* Description: Description collection: Subscribe configuration for task SEQSTART[n] */
9435 
9436 /* Bit 31 :   */
9437 #define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL) /*!< Position of EN field. */
9438 #define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field. */
9439 #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0x0UL) /*!< Disable subscription */
9440 #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (0x1UL) /*!< Enable subscription */
9441 
9442 /* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */
9443 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9444 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9445 
9446 /* Register: PWM_SUBSCRIBE_NEXTSTEP */
9447 /* Description: Subscribe configuration for task NEXTSTEP */
9448 
9449 /* Bit 31 :   */
9450 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */
9451 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */
9452 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0x0UL) /*!< Disable subscription */
9453 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (0x1UL) /*!< Enable subscription */
9454 
9455 /* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */
9456 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9457 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9458 
9459 /* Register: PWM_EVENTS_STOPPED */
9460 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
9461 
9462 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
9463 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9464 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9465 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
9466 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
9467 
9468 /* Register: PWM_EVENTS_SEQSTARTED */
9469 /* Description: Description collection: First PWM period started on sequence n */
9470 
9471 /* Bit 0 : First PWM period started on sequence n */
9472 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
9473 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
9474 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
9475 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (0x1UL) /*!< Event generated */
9476 
9477 /* Register: PWM_EVENTS_SEQEND */
9478 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
9479 
9480 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
9481 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
9482 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
9483 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0x0UL) /*!< Event not generated */
9484 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (0x1UL) /*!< Event generated */
9485 
9486 /* Register: PWM_EVENTS_PWMPERIODEND */
9487 /* Description: Emitted at the end of each PWM period */
9488 
9489 /* Bit 0 : Emitted at the end of each PWM period */
9490 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
9491 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
9492 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated */
9493 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated */
9494 
9495 /* Register: PWM_EVENTS_LOOPSDONE */
9496 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
9497 
9498 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
9499 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
9500 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
9501 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0x0UL) /*!< Event not generated */
9502 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (0x1UL) /*!< Event generated */
9503 
9504 /* Register: PWM_PUBLISH_STOPPED */
9505 /* Description: Publish configuration for event STOPPED */
9506 
9507 /* Bit 31 :   */
9508 #define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
9509 #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
9510 #define PWM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
9511 #define PWM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */
9512 
9513 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
9514 #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9515 #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9516 
9517 /* Register: PWM_PUBLISH_SEQSTARTED */
9518 /* Description: Description collection: Publish configuration for event SEQSTARTED[n] */
9519 
9520 /* Bit 31 :   */
9521 #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
9522 #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */
9523 #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
9524 #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
9525 
9526 /* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to */
9527 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9528 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9529 
9530 /* Register: PWM_PUBLISH_SEQEND */
9531 /* Description: Description collection: Publish configuration for event SEQEND[n] */
9532 
9533 /* Bit 31 :   */
9534 #define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */
9535 #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */
9536 #define PWM_PUBLISH_SEQEND_EN_Disabled (0x0UL) /*!< Disable publishing */
9537 #define PWM_PUBLISH_SEQEND_EN_Enabled (0x1UL) /*!< Enable publishing */
9538 
9539 /* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to */
9540 #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9541 #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9542 
9543 /* Register: PWM_PUBLISH_PWMPERIODEND */
9544 /* Description: Publish configuration for event PWMPERIODEND */
9545 
9546 /* Bit 31 :   */
9547 #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */
9548 #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */
9549 #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0x0UL) /*!< Disable publishing */
9550 #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (0x1UL) /*!< Enable publishing */
9551 
9552 /* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to */
9553 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9554 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9555 
9556 /* Register: PWM_PUBLISH_LOOPSDONE */
9557 /* Description: Publish configuration for event LOOPSDONE */
9558 
9559 /* Bit 31 :   */
9560 #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */
9561 #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */
9562 #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0x0UL) /*!< Disable publishing */
9563 #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (0x1UL) /*!< Enable publishing */
9564 
9565 /* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to */
9566 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9567 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9568 
9569 /* Register: PWM_SHORTS */
9570 /* Description: Shortcuts between local events and tasks */
9571 
9572 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
9573 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
9574 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
9575 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0x0UL) /*!< Disable shortcut */
9576 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (0x1UL) /*!< Enable shortcut */
9577 
9578 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
9579 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
9580 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
9581 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0x0UL) /*!< Disable shortcut */
9582 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (0x1UL) /*!< Enable shortcut */
9583 
9584 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
9585 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
9586 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
9587 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0x0UL) /*!< Disable shortcut */
9588 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (0x1UL) /*!< Enable shortcut */
9589 
9590 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
9591 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
9592 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
9593 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL) /*!< Disable shortcut */
9594 #define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL) /*!< Enable shortcut */
9595 
9596 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
9597 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
9598 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
9599 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0x0UL) /*!< Disable shortcut */
9600 #define PWM_SHORTS_SEQEND0_STOP_Enabled (0x1UL) /*!< Enable shortcut */
9601 
9602 /* Register: PWM_INTEN */
9603 /* Description: Enable or disable interrupt */
9604 
9605 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
9606 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
9607 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
9608 #define PWM_INTEN_LOOPSDONE_Disabled (0x0UL) /*!< Disable */
9609 #define PWM_INTEN_LOOPSDONE_Enabled (0x1UL) /*!< Enable */
9610 
9611 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
9612 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
9613 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
9614 #define PWM_INTEN_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */
9615 #define PWM_INTEN_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */
9616 
9617 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
9618 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
9619 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
9620 #define PWM_INTEN_SEQEND1_Disabled (0x0UL) /*!< Disable */
9621 #define PWM_INTEN_SEQEND1_Enabled (0x1UL) /*!< Enable */
9622 
9623 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
9624 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
9625 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
9626 #define PWM_INTEN_SEQEND0_Disabled (0x0UL) /*!< Disable */
9627 #define PWM_INTEN_SEQEND0_Enabled (0x1UL) /*!< Enable */
9628 
9629 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
9630 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
9631 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
9632 #define PWM_INTEN_SEQSTARTED1_Disabled (0x0UL) /*!< Disable */
9633 #define PWM_INTEN_SEQSTARTED1_Enabled (0x1UL) /*!< Enable */
9634 
9635 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
9636 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
9637 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
9638 #define PWM_INTEN_SEQSTARTED0_Disabled (0x0UL) /*!< Disable */
9639 #define PWM_INTEN_SEQSTARTED0_Enabled (0x1UL) /*!< Enable */
9640 
9641 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9642 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9643 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9644 #define PWM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
9645 #define PWM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
9646 
9647 /* Register: PWM_INTENSET */
9648 /* Description: Enable interrupt */
9649 
9650 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
9651 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
9652 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
9653 #define PWM_INTENSET_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */
9654 #define PWM_INTENSET_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */
9655 #define PWM_INTENSET_LOOPSDONE_Set (0x1UL) /*!< Enable */
9656 
9657 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
9658 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
9659 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
9660 #define PWM_INTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */
9661 #define PWM_INTENSET_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */
9662 #define PWM_INTENSET_PWMPERIODEND_Set (0x1UL) /*!< Enable */
9663 
9664 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
9665 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
9666 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
9667 #define PWM_INTENSET_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */
9668 #define PWM_INTENSET_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */
9669 #define PWM_INTENSET_SEQEND1_Set (0x1UL) /*!< Enable */
9670 
9671 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
9672 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
9673 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
9674 #define PWM_INTENSET_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */
9675 #define PWM_INTENSET_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */
9676 #define PWM_INTENSET_SEQEND0_Set (0x1UL) /*!< Enable */
9677 
9678 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
9679 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
9680 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
9681 #define PWM_INTENSET_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */
9682 #define PWM_INTENSET_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */
9683 #define PWM_INTENSET_SEQSTARTED1_Set (0x1UL) /*!< Enable */
9684 
9685 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
9686 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
9687 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
9688 #define PWM_INTENSET_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */
9689 #define PWM_INTENSET_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */
9690 #define PWM_INTENSET_SEQSTARTED0_Set (0x1UL) /*!< Enable */
9691 
9692 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9693 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9694 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9695 #define PWM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
9696 #define PWM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
9697 #define PWM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
9698 
9699 /* Register: PWM_INTENCLR */
9700 /* Description: Disable interrupt */
9701 
9702 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
9703 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
9704 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
9705 #define PWM_INTENCLR_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */
9706 #define PWM_INTENCLR_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */
9707 #define PWM_INTENCLR_LOOPSDONE_Clear (0x1UL) /*!< Disable */
9708 
9709 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
9710 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
9711 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
9712 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */
9713 #define PWM_INTENCLR_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */
9714 #define PWM_INTENCLR_PWMPERIODEND_Clear (0x1UL) /*!< Disable */
9715 
9716 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
9717 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
9718 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
9719 #define PWM_INTENCLR_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */
9720 #define PWM_INTENCLR_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */
9721 #define PWM_INTENCLR_SEQEND1_Clear (0x1UL) /*!< Disable */
9722 
9723 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
9724 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
9725 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
9726 #define PWM_INTENCLR_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */
9727 #define PWM_INTENCLR_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */
9728 #define PWM_INTENCLR_SEQEND0_Clear (0x1UL) /*!< Disable */
9729 
9730 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
9731 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
9732 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
9733 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */
9734 #define PWM_INTENCLR_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */
9735 #define PWM_INTENCLR_SEQSTARTED1_Clear (0x1UL) /*!< Disable */
9736 
9737 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
9738 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
9739 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
9740 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */
9741 #define PWM_INTENCLR_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */
9742 #define PWM_INTENCLR_SEQSTARTED0_Clear (0x1UL) /*!< Disable */
9743 
9744 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9745 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9746 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9747 #define PWM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
9748 #define PWM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
9749 #define PWM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
9750 
9751 /* Register: PWM_ENABLE */
9752 /* Description: PWM module enable register */
9753 
9754 /* Bit 0 : Enable or disable PWM module */
9755 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9756 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9757 #define PWM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disabled */
9758 #define PWM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */
9759 
9760 /* Register: PWM_MODE */
9761 /* Description: Selects operating mode of the wave counter */
9762 
9763 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
9764 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
9765 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
9766 #define PWM_MODE_UPDOWN_Up (0x0UL) /*!< Up counter, edge-aligned PWM duty cycle */
9767 #define PWM_MODE_UPDOWN_UpAndDown (0x1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
9768 
9769 /* Register: PWM_COUNTERTOP */
9770 /* Description: Value up to which the pulse generator counter counts */
9771 
9772 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
9773 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
9774 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
9775 
9776 /* Register: PWM_PRESCALER */
9777 /* Description: Configuration for PWM_CLK */
9778 
9779 /* Bits 2..0 : Prescaler of PWM_CLK */
9780 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
9781 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
9782 #define PWM_PRESCALER_PRESCALER_DIV_1 (0x0UL) /*!< Divide by 1 (16 MHz) */
9783 #define PWM_PRESCALER_PRESCALER_DIV_2 (0x1UL) /*!< Divide by 2 (8 MHz) */
9784 #define PWM_PRESCALER_PRESCALER_DIV_4 (0x2UL) /*!< Divide by 4 (4 MHz) */
9785 #define PWM_PRESCALER_PRESCALER_DIV_8 (0x3UL) /*!< Divide by 8 (2 MHz) */
9786 #define PWM_PRESCALER_PRESCALER_DIV_16 (0x4UL) /*!< Divide by 16 (1 MHz) */
9787 #define PWM_PRESCALER_PRESCALER_DIV_32 (0x5UL) /*!< Divide by 32 (500 kHz) */
9788 #define PWM_PRESCALER_PRESCALER_DIV_64 (0x6UL) /*!< Divide by 64 (250 kHz) */
9789 #define PWM_PRESCALER_PRESCALER_DIV_128 (0x7UL) /*!< Divide by 128 (125 kHz) */
9790 
9791 /* Register: PWM_DECODER */
9792 /* Description: Configuration of the decoder */
9793 
9794 /* Bit 8 : Selects source for advancing the active sequence */
9795 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
9796 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
9797 #define PWM_DECODER_MODE_RefreshCount (0x0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
9798 #define PWM_DECODER_MODE_NextStep (0x1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
9799 
9800 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
9801 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
9802 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
9803 #define PWM_DECODER_LOAD_Common (0x0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
9804 #define PWM_DECODER_LOAD_Grouped (0x1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
9805 #define PWM_DECODER_LOAD_Individual (0x2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
9806 #define PWM_DECODER_LOAD_WaveForm (0x3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
9807 
9808 /* Register: PWM_LOOP */
9809 /* Description: Number of playbacks of a loop */
9810 
9811 /* Bits 15..0 : Number of playbacks of pattern cycles */
9812 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
9813 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
9814 #define PWM_LOOP_CNT_Disabled (0x0000UL) /*!< Looping disabled (stop at the end of the sequence) */
9815 
9816 /* Register: PWM_SEQ_PTR */
9817 /* Description: Description cluster: Beginning address in RAM of this sequence */
9818 
9819 /* Bits 31..0 : Beginning address in RAM of this sequence */
9820 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9821 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9822 
9823 /* Register: PWM_SEQ_CNT */
9824 /* Description: Description cluster: Number of values (duty cycles) in this sequence */
9825 
9826 /* Bits 14..0 : Number of values (duty cycles) in this sequence */
9827 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
9828 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
9829 #define PWM_SEQ_CNT_CNT_Disabled (0x0000UL) /*!< Sequence is disabled, and shall not be started as it is empty */
9830 
9831 /* Register: PWM_SEQ_REFRESH */
9832 /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */
9833 
9834 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
9835 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
9836 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
9837 #define PWM_SEQ_REFRESH_CNT_Continuous (0x000000UL) /*!< Update every PWM period */
9838 
9839 /* Register: PWM_SEQ_ENDDELAY */
9840 /* Description: Description cluster: Time added after the sequence */
9841 
9842 /* Bits 23..0 : Time added after the sequence in PWM periods */
9843 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
9844 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
9845 
9846 /* Register: PWM_PSEL_OUT */
9847 /* Description: Description collection: Output pin select for PWM channel n */
9848 
9849 /* Bit 31 : Connection */
9850 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9851 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9852 #define PWM_PSEL_OUT_CONNECT_Connected (0x0UL) /*!< Connect */
9853 #define PWM_PSEL_OUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
9854 
9855 /* Bits 4..0 : Pin number */
9856 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
9857 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
9858 
9859 
9860 /* Peripheral: REGULATORS */
9861 /* Description: Voltage regulators control 0 */
9862 
9863 /* Register: REGULATORS_SYSTEMOFF */
9864 /* Description: System OFF register */
9865 
9866 /* Bit 0 : Enable System OFF mode */
9867 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
9868 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
9869 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (0x1UL) /*!< Enable System OFF mode */
9870 
9871 /* Register: REGULATORS_EXTPOFCON */
9872 /* Description: External power failure warning configuration */
9873 
9874 /* Bit 0 : Enable or disable external power failure warning */
9875 #define REGULATORS_EXTPOFCON_POF_Pos (0UL) /*!< Position of POF field. */
9876 #define REGULATORS_EXTPOFCON_POF_Msk (0x1UL << REGULATORS_EXTPOFCON_POF_Pos) /*!< Bit mask of POF field. */
9877 #define REGULATORS_EXTPOFCON_POF_Disabled (0x0UL) /*!< Disable */
9878 #define REGULATORS_EXTPOFCON_POF_Enabled (0x1UL) /*!< Enable */
9879 
9880 /* Register: REGULATORS_DCDCEN */
9881 /* Description: Enable a step-down DC/DC voltage regulator. */
9882 
9883 /* Bit 0 : Enable DC/DC buck regulator */
9884 #define REGULATORS_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
9885 #define REGULATORS_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
9886 #define REGULATORS_DCDCEN_DCDCEN_Disabled (0x0UL) /*!< DC/DC buck regulator is disabled */
9887 #define REGULATORS_DCDCEN_DCDCEN_Enabled (0x1UL) /*!< DC/DC buck regulator is enabled */
9888 
9889 
9890 /* Peripheral: RTC */
9891 /* Description: Real-time counter 0 */
9892 
9893 /* Register: RTC_TASKS_START */
9894 /* Description: Start RTC counter */
9895 
9896 /* Bit 0 : Start RTC counter */
9897 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
9898 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
9899 #define RTC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
9900 
9901 /* Register: RTC_TASKS_STOP */
9902 /* Description: Stop RTC counter */
9903 
9904 /* Bit 0 : Stop RTC counter */
9905 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9906 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9907 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
9908 
9909 /* Register: RTC_TASKS_CLEAR */
9910 /* Description: Clear RTC counter */
9911 
9912 /* Bit 0 : Clear RTC counter */
9913 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
9914 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
9915 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */
9916 
9917 /* Register: RTC_TASKS_TRIGOVRFLW */
9918 /* Description: Set counter to 0xFFFFF0 */
9919 
9920 /* Bit 0 : Set counter to 0xFFFFF0 */
9921 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
9922 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
9923 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (0x1UL) /*!< Trigger task */
9924 
9925 /* Register: RTC_SUBSCRIBE_START */
9926 /* Description: Subscribe configuration for task START */
9927 
9928 /* Bit 31 :   */
9929 #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
9930 #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
9931 #define RTC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
9932 #define RTC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */
9933 
9934 /* Bits 7..0 : DPPI channel that task START will subscribe to */
9935 #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9936 #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9937 
9938 /* Register: RTC_SUBSCRIBE_STOP */
9939 /* Description: Subscribe configuration for task STOP */
9940 
9941 /* Bit 31 :   */
9942 #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
9943 #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
9944 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
9945 #define RTC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */
9946 
9947 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
9948 #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9949 #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9950 
9951 /* Register: RTC_SUBSCRIBE_CLEAR */
9952 /* Description: Subscribe configuration for task CLEAR */
9953 
9954 /* Bit 31 :   */
9955 #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
9956 #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
9957 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */
9958 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */
9959 
9960 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
9961 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9962 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9963 
9964 /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */
9965 /* Description: Subscribe configuration for task TRIGOVRFLW */
9966 
9967 /* Bit 31 :   */
9968 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
9969 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */
9970 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0x0UL) /*!< Disable subscription */
9971 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (0x1UL) /*!< Enable subscription */
9972 
9973 /* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */
9974 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9975 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9976 
9977 /* Register: RTC_EVENTS_TICK */
9978 /* Description: Event on counter increment */
9979 
9980 /* Bit 0 : Event on counter increment */
9981 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
9982 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
9983 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0x0UL) /*!< Event not generated */
9984 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (0x1UL) /*!< Event generated */
9985 
9986 /* Register: RTC_EVENTS_OVRFLW */
9987 /* Description: Event on counter overflow */
9988 
9989 /* Bit 0 : Event on counter overflow */
9990 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
9991 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
9992 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0x0UL) /*!< Event not generated */
9993 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (0x1UL) /*!< Event generated */
9994 
9995 /* Register: RTC_EVENTS_COMPARE */
9996 /* Description: Description collection: Compare event on CC[n] match */
9997 
9998 /* Bit 0 : Compare event on CC[n] match */
9999 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
10000 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
10001 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */
10002 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */
10003 
10004 /* Register: RTC_PUBLISH_TICK */
10005 /* Description: Publish configuration for event TICK */
10006 
10007 /* Bit 31 :   */
10008 #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */
10009 #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */
10010 #define RTC_PUBLISH_TICK_EN_Disabled (0x0UL) /*!< Disable publishing */
10011 #define RTC_PUBLISH_TICK_EN_Enabled (0x1UL) /*!< Enable publishing */
10012 
10013 /* Bits 7..0 : DPPI channel that event TICK will publish to */
10014 #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10015 #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10016 
10017 /* Register: RTC_PUBLISH_OVRFLW */
10018 /* Description: Publish configuration for event OVRFLW */
10019 
10020 /* Bit 31 :   */
10021 #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
10022 #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */
10023 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0x0UL) /*!< Disable publishing */
10024 #define RTC_PUBLISH_OVRFLW_EN_Enabled (0x1UL) /*!< Enable publishing */
10025 
10026 /* Bits 7..0 : DPPI channel that event OVRFLW will publish to */
10027 #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10028 #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10029 
10030 /* Register: RTC_PUBLISH_COMPARE */
10031 /* Description: Description collection: Publish configuration for event COMPARE[n] */
10032 
10033 /* Bit 31 :   */
10034 #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
10035 #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
10036 #define RTC_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */
10037 #define RTC_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */
10038 
10039 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */
10040 #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10041 #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10042 
10043 /* Register: RTC_INTENSET */
10044 /* Description: Enable interrupt */
10045 
10046 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
10047 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10048 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10049 #define RTC_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
10050 #define RTC_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
10051 #define RTC_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */
10052 
10053 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
10054 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10055 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10056 #define RTC_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
10057 #define RTC_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
10058 #define RTC_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */
10059 
10060 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
10061 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10062 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10063 #define RTC_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
10064 #define RTC_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
10065 #define RTC_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */
10066 
10067 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
10068 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10069 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10070 #define RTC_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
10071 #define RTC_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
10072 #define RTC_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */
10073 
10074 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
10075 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
10076 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
10077 #define RTC_INTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
10078 #define RTC_INTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
10079 #define RTC_INTENSET_OVRFLW_Set (0x1UL) /*!< Enable */
10080 
10081 /* Bit 0 : Write '1' to enable interrupt for event TICK */
10082 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
10083 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
10084 #define RTC_INTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */
10085 #define RTC_INTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */
10086 #define RTC_INTENSET_TICK_Set (0x1UL) /*!< Enable */
10087 
10088 /* Register: RTC_INTENCLR */
10089 /* Description: Disable interrupt */
10090 
10091 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
10092 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10093 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10094 #define RTC_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
10095 #define RTC_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
10096 #define RTC_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */
10097 
10098 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
10099 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10100 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10101 #define RTC_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
10102 #define RTC_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
10103 #define RTC_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */
10104 
10105 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
10106 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10107 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10108 #define RTC_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
10109 #define RTC_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
10110 #define RTC_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */
10111 
10112 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
10113 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10114 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10115 #define RTC_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
10116 #define RTC_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
10117 #define RTC_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */
10118 
10119 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
10120 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
10121 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
10122 #define RTC_INTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
10123 #define RTC_INTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
10124 #define RTC_INTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */
10125 
10126 /* Bit 0 : Write '1' to disable interrupt for event TICK */
10127 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
10128 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
10129 #define RTC_INTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */
10130 #define RTC_INTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */
10131 #define RTC_INTENCLR_TICK_Clear (0x1UL) /*!< Disable */
10132 
10133 /* Register: RTC_EVTEN */
10134 /* Description: Enable or disable event routing */
10135 
10136 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
10137 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10138 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10139 #define RTC_EVTEN_COMPARE3_Disabled (0x0UL) /*!< Disable */
10140 #define RTC_EVTEN_COMPARE3_Enabled (0x1UL) /*!< Enable */
10141 
10142 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
10143 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10144 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10145 #define RTC_EVTEN_COMPARE2_Disabled (0x0UL) /*!< Disable */
10146 #define RTC_EVTEN_COMPARE2_Enabled (0x1UL) /*!< Enable */
10147 
10148 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
10149 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10150 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10151 #define RTC_EVTEN_COMPARE1_Disabled (0x0UL) /*!< Disable */
10152 #define RTC_EVTEN_COMPARE1_Enabled (0x1UL) /*!< Enable */
10153 
10154 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
10155 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10156 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10157 #define RTC_EVTEN_COMPARE0_Disabled (0x0UL) /*!< Disable */
10158 #define RTC_EVTEN_COMPARE0_Enabled (0x1UL) /*!< Enable */
10159 
10160 /* Bit 1 : Enable or disable event routing for event OVRFLW */
10161 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
10162 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
10163 #define RTC_EVTEN_OVRFLW_Disabled (0x0UL) /*!< Disable */
10164 #define RTC_EVTEN_OVRFLW_Enabled (0x1UL) /*!< Enable */
10165 
10166 /* Bit 0 : Enable or disable event routing for event TICK */
10167 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
10168 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
10169 #define RTC_EVTEN_TICK_Disabled (0x0UL) /*!< Disable */
10170 #define RTC_EVTEN_TICK_Enabled (0x1UL) /*!< Enable */
10171 
10172 /* Register: RTC_EVTENSET */
10173 /* Description: Enable event routing */
10174 
10175 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
10176 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10177 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10178 #define RTC_EVTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
10179 #define RTC_EVTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
10180 #define RTC_EVTENSET_COMPARE3_Set (0x1UL) /*!< Enable */
10181 
10182 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
10183 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10184 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10185 #define RTC_EVTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
10186 #define RTC_EVTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
10187 #define RTC_EVTENSET_COMPARE2_Set (0x1UL) /*!< Enable */
10188 
10189 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
10190 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10191 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10192 #define RTC_EVTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
10193 #define RTC_EVTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
10194 #define RTC_EVTENSET_COMPARE1_Set (0x1UL) /*!< Enable */
10195 
10196 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
10197 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10198 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10199 #define RTC_EVTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
10200 #define RTC_EVTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
10201 #define RTC_EVTENSET_COMPARE0_Set (0x1UL) /*!< Enable */
10202 
10203 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
10204 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
10205 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
10206 #define RTC_EVTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
10207 #define RTC_EVTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
10208 #define RTC_EVTENSET_OVRFLW_Set (0x1UL) /*!< Enable */
10209 
10210 /* Bit 0 : Write '1' to enable event routing for event TICK */
10211 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
10212 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
10213 #define RTC_EVTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */
10214 #define RTC_EVTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */
10215 #define RTC_EVTENSET_TICK_Set (0x1UL) /*!< Enable */
10216 
10217 /* Register: RTC_EVTENCLR */
10218 /* Description: Disable event routing */
10219 
10220 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
10221 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10222 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10223 #define RTC_EVTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
10224 #define RTC_EVTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
10225 #define RTC_EVTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */
10226 
10227 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
10228 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10229 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10230 #define RTC_EVTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
10231 #define RTC_EVTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
10232 #define RTC_EVTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */
10233 
10234 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
10235 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10236 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10237 #define RTC_EVTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
10238 #define RTC_EVTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
10239 #define RTC_EVTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */
10240 
10241 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
10242 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10243 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10244 #define RTC_EVTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
10245 #define RTC_EVTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
10246 #define RTC_EVTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */
10247 
10248 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
10249 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
10250 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
10251 #define RTC_EVTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
10252 #define RTC_EVTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
10253 #define RTC_EVTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */
10254 
10255 /* Bit 0 : Write '1' to disable event routing for event TICK */
10256 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
10257 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
10258 #define RTC_EVTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */
10259 #define RTC_EVTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */
10260 #define RTC_EVTENCLR_TICK_Clear (0x1UL) /*!< Disable */
10261 
10262 /* Register: RTC_COUNTER */
10263 /* Description: Current counter value */
10264 
10265 /* Bits 23..0 : Counter value */
10266 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
10267 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
10268 
10269 /* Register: RTC_PRESCALER */
10270 /* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */
10271 
10272 /* Bits 11..0 : Prescaler value */
10273 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
10274 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
10275 
10276 /* Register: RTC_CC */
10277 /* Description: Description collection: Compare register n */
10278 
10279 /* Bits 23..0 : Compare value */
10280 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
10281 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
10282 
10283 
10284 /* Peripheral: SAADC */
10285 /* Description: Analog to Digital Converter 0 */
10286 
10287 /* Register: SAADC_TASKS_START */
10288 /* Description: Start the ADC and prepare the result buffer in RAM */
10289 
10290 /* Bit 0 : Start the ADC and prepare the result buffer in RAM */
10291 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
10292 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
10293 #define SAADC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
10294 
10295 /* Register: SAADC_TASKS_SAMPLE */
10296 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */
10297 
10298 /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
10299 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
10300 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
10301 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */
10302 
10303 /* Register: SAADC_TASKS_STOP */
10304 /* Description: Stop the ADC and terminate any on-going conversion */
10305 
10306 /* Bit 0 : Stop the ADC and terminate any on-going conversion */
10307 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10308 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10309 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
10310 
10311 /* Register: SAADC_TASKS_CALIBRATEOFFSET */
10312 /* Description: Starts offset auto-calibration */
10313 
10314 /* Bit 0 : Starts offset auto-calibration */
10315 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
10316 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
10317 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (0x1UL) /*!< Trigger task */
10318 
10319 /* Register: SAADC_SUBSCRIBE_START */
10320 /* Description: Subscribe configuration for task START */
10321 
10322 /* Bit 31 :   */
10323 #define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
10324 #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
10325 #define SAADC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
10326 #define SAADC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */
10327 
10328 /* Bits 7..0 : DPPI channel that task START will subscribe to */
10329 #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10330 #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10331 
10332 /* Register: SAADC_SUBSCRIBE_SAMPLE */
10333 /* Description: Subscribe configuration for task SAMPLE */
10334 
10335 /* Bit 31 :   */
10336 #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */
10337 #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */
10338 #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */
10339 #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */
10340 
10341 /* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */
10342 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10343 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10344 
10345 /* Register: SAADC_SUBSCRIBE_STOP */
10346 /* Description: Subscribe configuration for task STOP */
10347 
10348 /* Bit 31 :   */
10349 #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
10350 #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
10351 #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
10352 #define SAADC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */
10353 
10354 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
10355 #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10356 #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10357 
10358 /* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */
10359 /* Description: Subscribe configuration for task CALIBRATEOFFSET */
10360 
10361 /* Bit 31 :   */
10362 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */
10363 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */
10364 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0x0UL) /*!< Disable subscription */
10365 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (0x1UL) /*!< Enable subscription */
10366 
10367 /* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */
10368 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10369 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10370 
10371 /* Register: SAADC_EVENTS_STARTED */
10372 /* Description: The ADC has started */
10373 
10374 /* Bit 0 : The ADC has started */
10375 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
10376 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
10377 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
10378 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */
10379 
10380 /* Register: SAADC_EVENTS_END */
10381 /* Description: The ADC has filled up the Result buffer */
10382 
10383 /* Bit 0 : The ADC has filled up the Result buffer */
10384 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
10385 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
10386 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
10387 #define SAADC_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */
10388 
10389 /* Register: SAADC_EVENTS_DONE */
10390 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
10391 
10392 /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
10393 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
10394 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
10395 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */
10396 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */
10397 
10398 /* Register: SAADC_EVENTS_RESULTDONE */
10399 /* Description: A result is ready to get transferred to RAM. */
10400 
10401 /* Bit 0 : A result is ready to get transferred to RAM. */
10402 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
10403 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
10404 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0x0UL) /*!< Event not generated */
10405 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (0x1UL) /*!< Event generated */
10406 
10407 /* Register: SAADC_EVENTS_CALIBRATEDONE */
10408 /* Description: Calibration is complete */
10409 
10410 /* Bit 0 : Calibration is complete */
10411 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
10412 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
10413 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0x0UL) /*!< Event not generated */
10414 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (0x1UL) /*!< Event generated */
10415 
10416 /* Register: SAADC_EVENTS_STOPPED */
10417 /* Description: The ADC has stopped */
10418 
10419 /* Bit 0 : The ADC has stopped */
10420 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
10421 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
10422 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
10423 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
10424 
10425 /* Register: SAADC_EVENTS_CH_LIMITH */
10426 /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */
10427 
10428 /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
10429 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
10430 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
10431 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0x0UL) /*!< Event not generated */
10432 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (0x1UL) /*!< Event generated */
10433 
10434 /* Register: SAADC_EVENTS_CH_LIMITL */
10435 /* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */
10436 
10437 /* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
10438 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
10439 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
10440 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0x0UL) /*!< Event not generated */
10441 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (0x1UL) /*!< Event generated */
10442 
10443 /* Register: SAADC_PUBLISH_STARTED */
10444 /* Description: Publish configuration for event STARTED */
10445 
10446 /* Bit 31 :   */
10447 #define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
10448 #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
10449 #define SAADC_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
10450 #define SAADC_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
10451 
10452 /* Bits 7..0 : DPPI channel that event STARTED will publish to */
10453 #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10454 #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10455 
10456 /* Register: SAADC_PUBLISH_END */
10457 /* Description: Publish configuration for event END */
10458 
10459 /* Bit 31 :   */
10460 #define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
10461 #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
10462 #define SAADC_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */
10463 #define SAADC_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */
10464 
10465 /* Bits 7..0 : DPPI channel that event END will publish to */
10466 #define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10467 #define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10468 
10469 /* Register: SAADC_PUBLISH_DONE */
10470 /* Description: Publish configuration for event DONE */
10471 
10472 /* Bit 31 :   */
10473 #define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */
10474 #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */
10475 #define SAADC_PUBLISH_DONE_EN_Disabled (0x0UL) /*!< Disable publishing */
10476 #define SAADC_PUBLISH_DONE_EN_Enabled (0x1UL) /*!< Enable publishing */
10477 
10478 /* Bits 7..0 : DPPI channel that event DONE will publish to */
10479 #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10480 #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10481 
10482 /* Register: SAADC_PUBLISH_RESULTDONE */
10483 /* Description: Publish configuration for event RESULTDONE */
10484 
10485 /* Bit 31 :   */
10486 #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */
10487 #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */
10488 #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0x0UL) /*!< Disable publishing */
10489 #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (0x1UL) /*!< Enable publishing */
10490 
10491 /* Bits 7..0 : DPPI channel that event RESULTDONE will publish to */
10492 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10493 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10494 
10495 /* Register: SAADC_PUBLISH_CALIBRATEDONE */
10496 /* Description: Publish configuration for event CALIBRATEDONE */
10497 
10498 /* Bit 31 :   */
10499 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */
10500 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */
10501 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0x0UL) /*!< Disable publishing */
10502 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (0x1UL) /*!< Enable publishing */
10503 
10504 /* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to */
10505 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10506 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10507 
10508 /* Register: SAADC_PUBLISH_STOPPED */
10509 /* Description: Publish configuration for event STOPPED */
10510 
10511 /* Bit 31 :   */
10512 #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
10513 #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
10514 #define SAADC_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
10515 #define SAADC_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */
10516 
10517 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
10518 #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10519 #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10520 
10521 /* Register: SAADC_PUBLISH_CH_LIMITH */
10522 /* Description: Description cluster: Publish configuration for event CH[n].LIMITH */
10523 
10524 /* Bit 31 :   */
10525 #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */
10526 #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */
10527 #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0x0UL) /*!< Disable publishing */
10528 #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (0x1UL) /*!< Enable publishing */
10529 
10530 /* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to */
10531 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10532 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10533 
10534 /* Register: SAADC_PUBLISH_CH_LIMITL */
10535 /* Description: Description cluster: Publish configuration for event CH[n].LIMITL */
10536 
10537 /* Bit 31 :   */
10538 #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */
10539 #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */
10540 #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0x0UL) /*!< Disable publishing */
10541 #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (0x1UL) /*!< Enable publishing */
10542 
10543 /* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to */
10544 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10545 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10546 
10547 /* Register: SAADC_INTEN */
10548 /* Description: Enable or disable interrupt */
10549 
10550 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
10551 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
10552 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
10553 #define SAADC_INTEN_CH7LIMITL_Disabled (0x0UL) /*!< Disable */
10554 #define SAADC_INTEN_CH7LIMITL_Enabled (0x1UL) /*!< Enable */
10555 
10556 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
10557 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
10558 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
10559 #define SAADC_INTEN_CH7LIMITH_Disabled (0x0UL) /*!< Disable */
10560 #define SAADC_INTEN_CH7LIMITH_Enabled (0x1UL) /*!< Enable */
10561 
10562 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
10563 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
10564 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
10565 #define SAADC_INTEN_CH6LIMITL_Disabled (0x0UL) /*!< Disable */
10566 #define SAADC_INTEN_CH6LIMITL_Enabled (0x1UL) /*!< Enable */
10567 
10568 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
10569 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
10570 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
10571 #define SAADC_INTEN_CH6LIMITH_Disabled (0x0UL) /*!< Disable */
10572 #define SAADC_INTEN_CH6LIMITH_Enabled (0x1UL) /*!< Enable */
10573 
10574 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
10575 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
10576 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
10577 #define SAADC_INTEN_CH5LIMITL_Disabled (0x0UL) /*!< Disable */
10578 #define SAADC_INTEN_CH5LIMITL_Enabled (0x1UL) /*!< Enable */
10579 
10580 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
10581 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
10582 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
10583 #define SAADC_INTEN_CH5LIMITH_Disabled (0x0UL) /*!< Disable */
10584 #define SAADC_INTEN_CH5LIMITH_Enabled (0x1UL) /*!< Enable */
10585 
10586 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
10587 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
10588 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
10589 #define SAADC_INTEN_CH4LIMITL_Disabled (0x0UL) /*!< Disable */
10590 #define SAADC_INTEN_CH4LIMITL_Enabled (0x1UL) /*!< Enable */
10591 
10592 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
10593 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
10594 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
10595 #define SAADC_INTEN_CH4LIMITH_Disabled (0x0UL) /*!< Disable */
10596 #define SAADC_INTEN_CH4LIMITH_Enabled (0x1UL) /*!< Enable */
10597 
10598 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
10599 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
10600 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
10601 #define SAADC_INTEN_CH3LIMITL_Disabled (0x0UL) /*!< Disable */
10602 #define SAADC_INTEN_CH3LIMITL_Enabled (0x1UL) /*!< Enable */
10603 
10604 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
10605 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
10606 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
10607 #define SAADC_INTEN_CH3LIMITH_Disabled (0x0UL) /*!< Disable */
10608 #define SAADC_INTEN_CH3LIMITH_Enabled (0x1UL) /*!< Enable */
10609 
10610 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
10611 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
10612 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
10613 #define SAADC_INTEN_CH2LIMITL_Disabled (0x0UL) /*!< Disable */
10614 #define SAADC_INTEN_CH2LIMITL_Enabled (0x1UL) /*!< Enable */
10615 
10616 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
10617 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
10618 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
10619 #define SAADC_INTEN_CH2LIMITH_Disabled (0x0UL) /*!< Disable */
10620 #define SAADC_INTEN_CH2LIMITH_Enabled (0x1UL) /*!< Enable */
10621 
10622 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
10623 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
10624 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
10625 #define SAADC_INTEN_CH1LIMITL_Disabled (0x0UL) /*!< Disable */
10626 #define SAADC_INTEN_CH1LIMITL_Enabled (0x1UL) /*!< Enable */
10627 
10628 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
10629 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
10630 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
10631 #define SAADC_INTEN_CH1LIMITH_Disabled (0x0UL) /*!< Disable */
10632 #define SAADC_INTEN_CH1LIMITH_Enabled (0x1UL) /*!< Enable */
10633 
10634 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
10635 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
10636 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
10637 #define SAADC_INTEN_CH0LIMITL_Disabled (0x0UL) /*!< Disable */
10638 #define SAADC_INTEN_CH0LIMITL_Enabled (0x1UL) /*!< Enable */
10639 
10640 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
10641 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
10642 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
10643 #define SAADC_INTEN_CH0LIMITH_Disabled (0x0UL) /*!< Disable */
10644 #define SAADC_INTEN_CH0LIMITH_Enabled (0x1UL) /*!< Enable */
10645 
10646 /* Bit 5 : Enable or disable interrupt for event STOPPED */
10647 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
10648 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10649 #define SAADC_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
10650 #define SAADC_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
10651 
10652 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
10653 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
10654 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
10655 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0x0UL) /*!< Disable */
10656 #define SAADC_INTEN_CALIBRATEDONE_Enabled (0x1UL) /*!< Enable */
10657 
10658 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
10659 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
10660 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
10661 #define SAADC_INTEN_RESULTDONE_Disabled (0x0UL) /*!< Disable */
10662 #define SAADC_INTEN_RESULTDONE_Enabled (0x1UL) /*!< Enable */
10663 
10664 /* Bit 2 : Enable or disable interrupt for event DONE */
10665 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
10666 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
10667 #define SAADC_INTEN_DONE_Disabled (0x0UL) /*!< Disable */
10668 #define SAADC_INTEN_DONE_Enabled (0x1UL) /*!< Enable */
10669 
10670 /* Bit 1 : Enable or disable interrupt for event END */
10671 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
10672 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
10673 #define SAADC_INTEN_END_Disabled (0x0UL) /*!< Disable */
10674 #define SAADC_INTEN_END_Enabled (0x1UL) /*!< Enable */
10675 
10676 /* Bit 0 : Enable or disable interrupt for event STARTED */
10677 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
10678 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
10679 #define SAADC_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */
10680 #define SAADC_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */
10681 
10682 /* Register: SAADC_INTENSET */
10683 /* Description: Enable interrupt */
10684 
10685 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
10686 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
10687 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
10688 #define SAADC_INTENSET_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10689 #define SAADC_INTENSET_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10690 #define SAADC_INTENSET_CH7LIMITL_Set (0x1UL) /*!< Enable */
10691 
10692 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
10693 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
10694 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
10695 #define SAADC_INTENSET_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10696 #define SAADC_INTENSET_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10697 #define SAADC_INTENSET_CH7LIMITH_Set (0x1UL) /*!< Enable */
10698 
10699 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
10700 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
10701 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
10702 #define SAADC_INTENSET_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10703 #define SAADC_INTENSET_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10704 #define SAADC_INTENSET_CH6LIMITL_Set (0x1UL) /*!< Enable */
10705 
10706 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
10707 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
10708 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
10709 #define SAADC_INTENSET_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10710 #define SAADC_INTENSET_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10711 #define SAADC_INTENSET_CH6LIMITH_Set (0x1UL) /*!< Enable */
10712 
10713 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
10714 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
10715 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
10716 #define SAADC_INTENSET_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10717 #define SAADC_INTENSET_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10718 #define SAADC_INTENSET_CH5LIMITL_Set (0x1UL) /*!< Enable */
10719 
10720 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
10721 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
10722 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
10723 #define SAADC_INTENSET_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10724 #define SAADC_INTENSET_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10725 #define SAADC_INTENSET_CH5LIMITH_Set (0x1UL) /*!< Enable */
10726 
10727 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
10728 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
10729 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
10730 #define SAADC_INTENSET_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10731 #define SAADC_INTENSET_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10732 #define SAADC_INTENSET_CH4LIMITL_Set (0x1UL) /*!< Enable */
10733 
10734 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
10735 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
10736 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
10737 #define SAADC_INTENSET_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10738 #define SAADC_INTENSET_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10739 #define SAADC_INTENSET_CH4LIMITH_Set (0x1UL) /*!< Enable */
10740 
10741 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
10742 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
10743 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
10744 #define SAADC_INTENSET_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10745 #define SAADC_INTENSET_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10746 #define SAADC_INTENSET_CH3LIMITL_Set (0x1UL) /*!< Enable */
10747 
10748 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
10749 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
10750 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
10751 #define SAADC_INTENSET_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10752 #define SAADC_INTENSET_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10753 #define SAADC_INTENSET_CH3LIMITH_Set (0x1UL) /*!< Enable */
10754 
10755 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
10756 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
10757 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
10758 #define SAADC_INTENSET_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10759 #define SAADC_INTENSET_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10760 #define SAADC_INTENSET_CH2LIMITL_Set (0x1UL) /*!< Enable */
10761 
10762 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
10763 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
10764 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
10765 #define SAADC_INTENSET_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10766 #define SAADC_INTENSET_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10767 #define SAADC_INTENSET_CH2LIMITH_Set (0x1UL) /*!< Enable */
10768 
10769 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
10770 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
10771 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
10772 #define SAADC_INTENSET_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10773 #define SAADC_INTENSET_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10774 #define SAADC_INTENSET_CH1LIMITL_Set (0x1UL) /*!< Enable */
10775 
10776 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
10777 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
10778 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
10779 #define SAADC_INTENSET_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10780 #define SAADC_INTENSET_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10781 #define SAADC_INTENSET_CH1LIMITH_Set (0x1UL) /*!< Enable */
10782 
10783 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
10784 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
10785 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
10786 #define SAADC_INTENSET_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10787 #define SAADC_INTENSET_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10788 #define SAADC_INTENSET_CH0LIMITL_Set (0x1UL) /*!< Enable */
10789 
10790 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
10791 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
10792 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
10793 #define SAADC_INTENSET_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10794 #define SAADC_INTENSET_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10795 #define SAADC_INTENSET_CH0LIMITH_Set (0x1UL) /*!< Enable */
10796 
10797 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
10798 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
10799 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10800 #define SAADC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
10801 #define SAADC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
10802 #define SAADC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
10803 
10804 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
10805 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
10806 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
10807 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */
10808 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */
10809 #define SAADC_INTENSET_CALIBRATEDONE_Set (0x1UL) /*!< Enable */
10810 
10811 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
10812 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
10813 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
10814 #define SAADC_INTENSET_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */
10815 #define SAADC_INTENSET_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */
10816 #define SAADC_INTENSET_RESULTDONE_Set (0x1UL) /*!< Enable */
10817 
10818 /* Bit 2 : Write '1' to enable interrupt for event DONE */
10819 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
10820 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
10821 #define SAADC_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */
10822 #define SAADC_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */
10823 #define SAADC_INTENSET_DONE_Set (0x1UL) /*!< Enable */
10824 
10825 /* Bit 1 : Write '1' to enable interrupt for event END */
10826 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
10827 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
10828 #define SAADC_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
10829 #define SAADC_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
10830 #define SAADC_INTENSET_END_Set (0x1UL) /*!< Enable */
10831 
10832 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
10833 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
10834 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
10835 #define SAADC_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
10836 #define SAADC_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
10837 #define SAADC_INTENSET_STARTED_Set (0x1UL) /*!< Enable */
10838 
10839 /* Register: SAADC_INTENCLR */
10840 /* Description: Disable interrupt */
10841 
10842 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
10843 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
10844 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
10845 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10846 #define SAADC_INTENCLR_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10847 #define SAADC_INTENCLR_CH7LIMITL_Clear (0x1UL) /*!< Disable */
10848 
10849 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
10850 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
10851 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
10852 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10853 #define SAADC_INTENCLR_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10854 #define SAADC_INTENCLR_CH7LIMITH_Clear (0x1UL) /*!< Disable */
10855 
10856 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
10857 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
10858 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
10859 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10860 #define SAADC_INTENCLR_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10861 #define SAADC_INTENCLR_CH6LIMITL_Clear (0x1UL) /*!< Disable */
10862 
10863 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
10864 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
10865 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
10866 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10867 #define SAADC_INTENCLR_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10868 #define SAADC_INTENCLR_CH6LIMITH_Clear (0x1UL) /*!< Disable */
10869 
10870 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
10871 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
10872 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
10873 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10874 #define SAADC_INTENCLR_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10875 #define SAADC_INTENCLR_CH5LIMITL_Clear (0x1UL) /*!< Disable */
10876 
10877 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
10878 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
10879 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
10880 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10881 #define SAADC_INTENCLR_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10882 #define SAADC_INTENCLR_CH5LIMITH_Clear (0x1UL) /*!< Disable */
10883 
10884 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
10885 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
10886 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
10887 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10888 #define SAADC_INTENCLR_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10889 #define SAADC_INTENCLR_CH4LIMITL_Clear (0x1UL) /*!< Disable */
10890 
10891 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
10892 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
10893 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
10894 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10895 #define SAADC_INTENCLR_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10896 #define SAADC_INTENCLR_CH4LIMITH_Clear (0x1UL) /*!< Disable */
10897 
10898 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
10899 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
10900 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
10901 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10902 #define SAADC_INTENCLR_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10903 #define SAADC_INTENCLR_CH3LIMITL_Clear (0x1UL) /*!< Disable */
10904 
10905 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
10906 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
10907 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
10908 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10909 #define SAADC_INTENCLR_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10910 #define SAADC_INTENCLR_CH3LIMITH_Clear (0x1UL) /*!< Disable */
10911 
10912 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
10913 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
10914 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
10915 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10916 #define SAADC_INTENCLR_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10917 #define SAADC_INTENCLR_CH2LIMITL_Clear (0x1UL) /*!< Disable */
10918 
10919 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
10920 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
10921 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
10922 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10923 #define SAADC_INTENCLR_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10924 #define SAADC_INTENCLR_CH2LIMITH_Clear (0x1UL) /*!< Disable */
10925 
10926 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
10927 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
10928 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
10929 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10930 #define SAADC_INTENCLR_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10931 #define SAADC_INTENCLR_CH1LIMITL_Clear (0x1UL) /*!< Disable */
10932 
10933 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
10934 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
10935 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
10936 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10937 #define SAADC_INTENCLR_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10938 #define SAADC_INTENCLR_CH1LIMITH_Clear (0x1UL) /*!< Disable */
10939 
10940 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
10941 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
10942 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
10943 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
10944 #define SAADC_INTENCLR_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
10945 #define SAADC_INTENCLR_CH0LIMITL_Clear (0x1UL) /*!< Disable */
10946 
10947 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
10948 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
10949 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
10950 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
10951 #define SAADC_INTENCLR_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
10952 #define SAADC_INTENCLR_CH0LIMITH_Clear (0x1UL) /*!< Disable */
10953 
10954 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
10955 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
10956 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10957 #define SAADC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
10958 #define SAADC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
10959 #define SAADC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
10960 
10961 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
10962 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
10963 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
10964 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */
10965 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */
10966 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (0x1UL) /*!< Disable */
10967 
10968 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
10969 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
10970 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
10971 #define SAADC_INTENCLR_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */
10972 #define SAADC_INTENCLR_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */
10973 #define SAADC_INTENCLR_RESULTDONE_Clear (0x1UL) /*!< Disable */
10974 
10975 /* Bit 2 : Write '1' to disable interrupt for event DONE */
10976 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
10977 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
10978 #define SAADC_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */
10979 #define SAADC_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */
10980 #define SAADC_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */
10981 
10982 /* Bit 1 : Write '1' to disable interrupt for event END */
10983 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
10984 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
10985 #define SAADC_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
10986 #define SAADC_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
10987 #define SAADC_INTENCLR_END_Clear (0x1UL) /*!< Disable */
10988 
10989 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
10990 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
10991 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
10992 #define SAADC_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
10993 #define SAADC_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
10994 #define SAADC_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */
10995 
10996 /* Register: SAADC_STATUS */
10997 /* Description: Status */
10998 
10999 /* Bit 0 : Status */
11000 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
11001 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
11002 #define SAADC_STATUS_STATUS_Ready (0x0UL) /*!< ADC is ready. No on-going conversion. */
11003 #define SAADC_STATUS_STATUS_Busy (0x1UL) /*!< ADC is busy. Single conversion in progress. */
11004 
11005 /* Register: SAADC_ENABLE */
11006 /* Description: Enable or disable ADC */
11007 
11008 /* Bit 0 : Enable or disable ADC */
11009 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11010 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11011 #define SAADC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable ADC */
11012 #define SAADC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable ADC */
11013 
11014 /* Register: SAADC_CH_PSELP */
11015 /* Description: Description cluster: Input positive pin selection for CH[n] */
11016 
11017 /* Bits 4..0 : Analog positive input channel */
11018 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
11019 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
11020 #define SAADC_CH_PSELP_PSELP_NC (0x00UL) /*!< Not connected */
11021 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (0x01UL) /*!< AIN0 */
11022 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (0x02UL) /*!< AIN1 */
11023 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (0x03UL) /*!< AIN2 */
11024 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (0x04UL) /*!< AIN3 */
11025 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (0x05UL) /*!< AIN4 */
11026 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (0x06UL) /*!< AIN5 */
11027 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (0x07UL) /*!< AIN6 */
11028 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (0x08UL) /*!< AIN7 */
11029 #define SAADC_CH_PSELP_PSELP_VDDGPIO (0x09UL) /*!< VDD_GPIO */
11030 
11031 /* Register: SAADC_CH_PSELN */
11032 /* Description: Description cluster: Input negative pin selection for CH[n] */
11033 
11034 /* Bits 4..0 : Analog negative input, enables differential channel */
11035 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
11036 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
11037 #define SAADC_CH_PSELN_PSELN_NC (0x00UL) /*!< Not connected */
11038 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (0x01UL) /*!< AIN0 */
11039 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (0x02UL) /*!< AIN1 */
11040 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (0x03UL) /*!< AIN2 */
11041 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (0x04UL) /*!< AIN3 */
11042 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (0x05UL) /*!< AIN4 */
11043 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (0x06UL) /*!< AIN5 */
11044 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (0x07UL) /*!< AIN6 */
11045 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (0x08UL) /*!< AIN7 */
11046 #define SAADC_CH_PSELN_PSELN_VDD_GPIO (0x09UL) /*!< VDD_GPIO */
11047 
11048 /* Register: SAADC_CH_CONFIG */
11049 /* Description: Description cluster: Input configuration for CH[n] */
11050 
11051 /* Bit 24 : Enable burst mode */
11052 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
11053 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
11054 #define SAADC_CH_CONFIG_BURST_Disabled (0x0UL) /*!< Burst mode is disabled (normal operation) */
11055 #define SAADC_CH_CONFIG_BURST_Enabled (0x1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
11056 
11057 /* Bit 20 : Enable differential mode */
11058 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
11059 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
11060 #define SAADC_CH_CONFIG_MODE_SE (0x0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
11061 #define SAADC_CH_CONFIG_MODE_Diff (0x1UL) /*!< Differential */
11062 
11063 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
11064 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
11065 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
11066 #define SAADC_CH_CONFIG_TACQ_3us (0x0UL) /*!< 3 us */
11067 #define SAADC_CH_CONFIG_TACQ_5us (0x1UL) /*!< 5 us */
11068 #define SAADC_CH_CONFIG_TACQ_10us (0x2UL) /*!< 10 us */
11069 #define SAADC_CH_CONFIG_TACQ_15us (0x3UL) /*!< 15 us */
11070 #define SAADC_CH_CONFIG_TACQ_20us (0x4UL) /*!< 20 us */
11071 #define SAADC_CH_CONFIG_TACQ_40us (0x5UL) /*!< 40 us */
11072 
11073 /* Bit 12 : Reference control */
11074 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
11075 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
11076 #define SAADC_CH_CONFIG_REFSEL_Internal (0x0UL) /*!< Internal reference (0.6 V) */
11077 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (0x1UL) /*!< VDD_GPIO/4 as reference */
11078 
11079 /* Bits 10..8 : Gain control */
11080 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
11081 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
11082 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0x0UL) /*!< 1/6 */
11083 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (0x1UL) /*!< 1/5 */
11084 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (0x2UL) /*!< 1/4 */
11085 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (0x3UL) /*!< 1/3 */
11086 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (0x4UL) /*!< 1/2 */
11087 #define SAADC_CH_CONFIG_GAIN_Gain1 (0x5UL) /*!< 1 */
11088 #define SAADC_CH_CONFIG_GAIN_Gain2 (0x6UL) /*!< 2 */
11089 #define SAADC_CH_CONFIG_GAIN_Gain4 (0x7UL) /*!< 4 */
11090 
11091 /* Bits 5..4 : Negative channel resistor control */
11092 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
11093 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
11094 #define SAADC_CH_CONFIG_RESN_Bypass (0x0UL) /*!< Bypass resistor ladder */
11095 #define SAADC_CH_CONFIG_RESN_Pulldown (0x1UL) /*!< Pull-down to GND */
11096 #define SAADC_CH_CONFIG_RESN_Pullup (0x2UL) /*!< Pull-up to VDD_GPIO */
11097 #define SAADC_CH_CONFIG_RESN_VDD1_2 (0x3UL) /*!< Set input at VDD_GPIO/2 */
11098 
11099 /* Bits 1..0 : Positive channel resistor control */
11100 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
11101 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
11102 #define SAADC_CH_CONFIG_RESP_Bypass (0x0UL) /*!< Bypass resistor ladder */
11103 #define SAADC_CH_CONFIG_RESP_Pulldown (0x1UL) /*!< Pull-down to GND */
11104 #define SAADC_CH_CONFIG_RESP_Pullup (0x2UL) /*!< Pull-up to VDD_GPIO */
11105 #define SAADC_CH_CONFIG_RESP_VDD1_2 (0x3UL) /*!< Set input at VDD_GPIO/2 */
11106 
11107 /* Register: SAADC_CH_LIMIT */
11108 /* Description: Description cluster: High/low limits for event monitoring a channel */
11109 
11110 /* Bits 31..16 : High level limit */
11111 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
11112 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
11113 
11114 /* Bits 15..0 : Low level limit */
11115 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
11116 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
11117 
11118 /* Register: SAADC_RESOLUTION */
11119 /* Description: Resolution configuration */
11120 
11121 /* Bits 2..0 : Set the resolution */
11122 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
11123 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
11124 #define SAADC_RESOLUTION_VAL_8bit (0x0UL) /*!< 8 bit */
11125 #define SAADC_RESOLUTION_VAL_10bit (0x1UL) /*!< 10 bit */
11126 #define SAADC_RESOLUTION_VAL_12bit (0x2UL) /*!< 12 bit */
11127 #define SAADC_RESOLUTION_VAL_14bit (0x3UL) /*!< 14 bit */
11128 
11129 /* Register: SAADC_OVERSAMPLE */
11130 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
11131 
11132 /* Bits 3..0 : Oversample control */
11133 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
11134 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
11135 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0x0UL) /*!< Bypass oversampling */
11136 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (0x1UL) /*!< Oversample 2x */
11137 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (0x2UL) /*!< Oversample 4x */
11138 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (0x3UL) /*!< Oversample 8x */
11139 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (0x4UL) /*!< Oversample 16x */
11140 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (0x5UL) /*!< Oversample 32x */
11141 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (0x6UL) /*!< Oversample 64x */
11142 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (0x7UL) /*!< Oversample 128x */
11143 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (0x8UL) /*!< Oversample 256x */
11144 
11145 /* Register: SAADC_SAMPLERATE */
11146 /* Description: Controls normal or continuous sample rate */
11147 
11148 /* Bit 12 : Select mode for sample rate control */
11149 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
11150 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
11151 #define SAADC_SAMPLERATE_MODE_Task (0x0UL) /*!< Rate is controlled from SAMPLE task */
11152 #define SAADC_SAMPLERATE_MODE_Timers (0x1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
11153 
11154 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
11155 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
11156 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
11157 
11158 /* Register: SAADC_RESULT_PTR */
11159 /* Description: Data pointer */
11160 
11161 /* Bits 31..0 : Data pointer */
11162 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11163 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11164 
11165 /* Register: SAADC_RESULT_MAXCNT */
11166 /* Description: Maximum number of buffer words to transfer */
11167 
11168 /* Bits 14..0 : Maximum number of buffer words to transfer */
11169 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11170 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11171 
11172 /* Register: SAADC_RESULT_AMOUNT */
11173 /* Description: Number of buffer words transferred since last START */
11174 
11175 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
11176 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11177 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11178 
11179 
11180 /* Peripheral: SPIM */
11181 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
11182 
11183 /* Register: SPIM_TASKS_START */
11184 /* Description: Start SPI transaction */
11185 
11186 /* Bit 0 : Start SPI transaction */
11187 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11188 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11189 #define SPIM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
11190 
11191 /* Register: SPIM_TASKS_STOP */
11192 /* Description: Stop SPI transaction */
11193 
11194 /* Bit 0 : Stop SPI transaction */
11195 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
11196 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
11197 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
11198 
11199 /* Register: SPIM_TASKS_SUSPEND */
11200 /* Description: Suspend SPI transaction */
11201 
11202 /* Bit 0 : Suspend SPI transaction */
11203 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
11204 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
11205 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */
11206 
11207 /* Register: SPIM_TASKS_RESUME */
11208 /* Description: Resume SPI transaction */
11209 
11210 /* Bit 0 : Resume SPI transaction */
11211 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
11212 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
11213 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */
11214 
11215 /* Register: SPIM_SUBSCRIBE_START */
11216 /* Description: Subscribe configuration for task START */
11217 
11218 /* Bit 31 :   */
11219 #define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
11220 #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
11221 #define SPIM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
11222 #define SPIM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */
11223 
11224 /* Bits 7..0 : DPPI channel that task START will subscribe to */
11225 #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11226 #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11227 
11228 /* Register: SPIM_SUBSCRIBE_STOP */
11229 /* Description: Subscribe configuration for task STOP */
11230 
11231 /* Bit 31 :   */
11232 #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
11233 #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
11234 #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
11235 #define SPIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */
11236 
11237 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
11238 #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11239 #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11240 
11241 /* Register: SPIM_SUBSCRIBE_SUSPEND */
11242 /* Description: Subscribe configuration for task SUSPEND */
11243 
11244 /* Bit 31 :   */
11245 #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
11246 #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
11247 #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */
11248 #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */
11249 
11250 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
11251 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11252 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11253 
11254 /* Register: SPIM_SUBSCRIBE_RESUME */
11255 /* Description: Subscribe configuration for task RESUME */
11256 
11257 /* Bit 31 :   */
11258 #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
11259 #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
11260 #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */
11261 #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */
11262 
11263 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
11264 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11265 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11266 
11267 /* Register: SPIM_EVENTS_STOPPED */
11268 /* Description: SPI transaction has stopped */
11269 
11270 /* Bit 0 : SPI transaction has stopped */
11271 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
11272 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
11273 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
11274 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
11275 
11276 /* Register: SPIM_EVENTS_ENDRX */
11277 /* Description: End of RXD buffer reached */
11278 
11279 /* Bit 0 : End of RXD buffer reached */
11280 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
11281 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
11282 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
11283 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */
11284 
11285 /* Register: SPIM_EVENTS_END */
11286 /* Description: End of RXD buffer and TXD buffer reached */
11287 
11288 /* Bit 0 : End of RXD buffer and TXD buffer reached */
11289 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
11290 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
11291 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
11292 #define SPIM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */
11293 
11294 /* Register: SPIM_EVENTS_ENDTX */
11295 /* Description: End of TXD buffer reached */
11296 
11297 /* Bit 0 : End of TXD buffer reached */
11298 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
11299 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
11300 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */
11301 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */
11302 
11303 /* Register: SPIM_EVENTS_STARTED */
11304 /* Description: Transaction started */
11305 
11306 /* Bit 0 : Transaction started */
11307 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
11308 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
11309 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
11310 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */
11311 
11312 /* Register: SPIM_PUBLISH_STOPPED */
11313 /* Description: Publish configuration for event STOPPED */
11314 
11315 /* Bit 31 :   */
11316 #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
11317 #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
11318 #define SPIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
11319 #define SPIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */
11320 
11321 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
11322 #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11323 #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11324 
11325 /* Register: SPIM_PUBLISH_ENDRX */
11326 /* Description: Publish configuration for event ENDRX */
11327 
11328 /* Bit 31 :   */
11329 #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
11330 #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
11331 #define SPIM_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */
11332 #define SPIM_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */
11333 
11334 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */
11335 #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11336 #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11337 
11338 /* Register: SPIM_PUBLISH_END */
11339 /* Description: Publish configuration for event END */
11340 
11341 /* Bit 31 :   */
11342 #define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
11343 #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
11344 #define SPIM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */
11345 #define SPIM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */
11346 
11347 /* Bits 7..0 : DPPI channel that event END will publish to */
11348 #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11349 #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11350 
11351 /* Register: SPIM_PUBLISH_ENDTX */
11352 /* Description: Publish configuration for event ENDTX */
11353 
11354 /* Bit 31 :   */
11355 #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
11356 #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
11357 #define SPIM_PUBLISH_ENDTX_EN_Disabled (0x0UL) /*!< Disable publishing */
11358 #define SPIM_PUBLISH_ENDTX_EN_Enabled (0x1UL) /*!< Enable publishing */
11359 
11360 /* Bits 7..0 : DPPI channel that event ENDTX will publish to */
11361 #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11362 #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11363 
11364 /* Register: SPIM_PUBLISH_STARTED */
11365 /* Description: Publish configuration for event STARTED */
11366 
11367 /* Bit 31 :   */
11368 #define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
11369 #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
11370 #define SPIM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
11371 #define SPIM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
11372 
11373 /* Bits 7..0 : DPPI channel that event STARTED will publish to */
11374 #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11375 #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11376 
11377 /* Register: SPIM_SHORTS */
11378 /* Description: Shortcuts between local events and tasks */
11379 
11380 /* Bit 17 : Shortcut between event END and task START */
11381 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
11382 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
11383 #define SPIM_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */
11384 #define SPIM_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */
11385 
11386 /* Register: SPIM_INTENSET */
11387 /* Description: Enable interrupt */
11388 
11389 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
11390 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
11391 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
11392 #define SPIM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
11393 #define SPIM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
11394 #define SPIM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */
11395 
11396 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
11397 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
11398 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
11399 #define SPIM_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
11400 #define SPIM_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
11401 #define SPIM_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */
11402 
11403 /* Bit 6 : Write '1' to enable interrupt for event END */
11404 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
11405 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
11406 #define SPIM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
11407 #define SPIM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
11408 #define SPIM_INTENSET_END_Set (0x1UL) /*!< Enable */
11409 
11410 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
11411 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
11412 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
11413 #define SPIM_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
11414 #define SPIM_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
11415 #define SPIM_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */
11416 
11417 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
11418 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11419 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11420 #define SPIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
11421 #define SPIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
11422 #define SPIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
11423 
11424 /* Register: SPIM_INTENCLR */
11425 /* Description: Disable interrupt */
11426 
11427 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
11428 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
11429 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
11430 #define SPIM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
11431 #define SPIM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
11432 #define SPIM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */
11433 
11434 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
11435 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
11436 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
11437 #define SPIM_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
11438 #define SPIM_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
11439 #define SPIM_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */
11440 
11441 /* Bit 6 : Write '1' to disable interrupt for event END */
11442 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
11443 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
11444 #define SPIM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
11445 #define SPIM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
11446 #define SPIM_INTENCLR_END_Clear (0x1UL) /*!< Disable */
11447 
11448 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
11449 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
11450 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
11451 #define SPIM_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
11452 #define SPIM_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
11453 #define SPIM_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */
11454 
11455 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
11456 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11457 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11458 #define SPIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
11459 #define SPIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
11460 #define SPIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
11461 
11462 /* Register: SPIM_ENABLE */
11463 /* Description: Enable SPIM */
11464 
11465 /* Bits 3..0 : Enable or disable SPIM */
11466 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11467 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11468 #define SPIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPIM */
11469 #define SPIM_ENABLE_ENABLE_Enabled (0x7UL) /*!< Enable SPIM */
11470 
11471 /* Register: SPIM_PSEL_SCK */
11472 /* Description: Pin select for SCK */
11473 
11474 /* Bit 31 : Connection */
11475 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11476 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11477 #define SPIM_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
11478 #define SPIM_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11479 
11480 /* Bits 4..0 : Pin number */
11481 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
11482 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
11483 
11484 /* Register: SPIM_PSEL_MOSI */
11485 /* Description: Pin select for MOSI signal */
11486 
11487 /* Bit 31 : Connection */
11488 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11489 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11490 #define SPIM_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */
11491 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11492 
11493 /* Bits 4..0 : Pin number */
11494 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
11495 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
11496 
11497 /* Register: SPIM_PSEL_MISO */
11498 /* Description: Pin select for MISO signal */
11499 
11500 /* Bit 31 : Connection */
11501 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11502 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11503 #define SPIM_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */
11504 #define SPIM_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11505 
11506 /* Bits 4..0 : Pin number */
11507 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
11508 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
11509 
11510 /* Register: SPIM_FREQUENCY */
11511 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
11512 
11513 /* Bits 31..0 : SPI master data rate */
11514 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
11515 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
11516 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
11517 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
11518 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
11519 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
11520 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
11521 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
11522 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
11523 
11524 /* Register: SPIM_RXD_PTR */
11525 /* Description: Data pointer */
11526 
11527 /* Bits 31..0 : Data pointer */
11528 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11529 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11530 
11531 /* Register: SPIM_RXD_MAXCNT */
11532 /* Description: Maximum number of bytes in receive buffer */
11533 
11534 /* Bits 12..0 : Maximum number of bytes in receive buffer */
11535 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11536 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11537 
11538 /* Register: SPIM_RXD_AMOUNT */
11539 /* Description: Number of bytes transferred in the last transaction */
11540 
11541 /* Bits 12..0 : Number of bytes transferred in the last transaction */
11542 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11543 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11544 
11545 /* Register: SPIM_RXD_LIST */
11546 /* Description: EasyDMA list type */
11547 
11548 /* Bits 1..0 : List type */
11549 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11550 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11551 #define SPIM_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
11552 #define SPIM_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
11553 
11554 /* Register: SPIM_TXD_PTR */
11555 /* Description: Data pointer */
11556 
11557 /* Bits 31..0 : Data pointer */
11558 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11559 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11560 
11561 /* Register: SPIM_TXD_MAXCNT */
11562 /* Description: Maximum number of bytes in transmit buffer */
11563 
11564 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
11565 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11566 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11567 
11568 /* Register: SPIM_TXD_AMOUNT */
11569 /* Description: Number of bytes transferred in the last transaction */
11570 
11571 /* Bits 12..0 : Number of bytes transferred in the last transaction */
11572 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11573 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11574 
11575 /* Register: SPIM_TXD_LIST */
11576 /* Description: EasyDMA list type */
11577 
11578 /* Bits 1..0 : List type */
11579 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11580 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11581 #define SPIM_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
11582 #define SPIM_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
11583 
11584 /* Register: SPIM_CONFIG */
11585 /* Description: Configuration register */
11586 
11587 /* Bit 2 : Serial clock (SCK) polarity */
11588 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
11589 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
11590 #define SPIM_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */
11591 #define SPIM_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */
11592 
11593 /* Bit 1 : Serial clock (SCK) phase */
11594 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
11595 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
11596 #define SPIM_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
11597 #define SPIM_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
11598 
11599 /* Bit 0 : Bit order */
11600 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
11601 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
11602 #define SPIM_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */
11603 #define SPIM_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */
11604 
11605 /* Register: SPIM_ORC */
11606 /* Description: Over-read character. Character clocked out in case an over-read of the TXD buffer. */
11607 
11608 /* Bits 7..0 : Over-read character. Character clocked out in case an over-read of the TXD buffer. */
11609 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
11610 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
11611 
11612 
11613 /* Peripheral: SPIS */
11614 /* Description: SPI Slave 0 */
11615 
11616 /* Register: SPIS_TASKS_ACQUIRE */
11617 /* Description: Acquire SPI semaphore */
11618 
11619 /* Bit 0 : Acquire SPI semaphore */
11620 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
11621 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
11622 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (0x1UL) /*!< Trigger task */
11623 
11624 /* Register: SPIS_TASKS_RELEASE */
11625 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
11626 
11627 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
11628 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
11629 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
11630 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (0x1UL) /*!< Trigger task */
11631 
11632 /* Register: SPIS_SUBSCRIBE_ACQUIRE */
11633 /* Description: Subscribe configuration for task ACQUIRE */
11634 
11635 /* Bit 31 :   */
11636 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */
11637 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */
11638 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0x0UL) /*!< Disable subscription */
11639 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (0x1UL) /*!< Enable subscription */
11640 
11641 /* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */
11642 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11643 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11644 
11645 /* Register: SPIS_SUBSCRIBE_RELEASE */
11646 /* Description: Subscribe configuration for task RELEASE */
11647 
11648 /* Bit 31 :   */
11649 #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */
11650 #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */
11651 #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0x0UL) /*!< Disable subscription */
11652 #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (0x1UL) /*!< Enable subscription */
11653 
11654 /* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */
11655 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11656 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11657 
11658 /* Register: SPIS_EVENTS_END */
11659 /* Description: Granted transaction completed */
11660 
11661 /* Bit 0 : Granted transaction completed */
11662 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
11663 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
11664 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
11665 #define SPIS_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */
11666 
11667 /* Register: SPIS_EVENTS_ENDRX */
11668 /* Description: End of RXD buffer reached */
11669 
11670 /* Bit 0 : End of RXD buffer reached */
11671 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
11672 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
11673 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
11674 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */
11675 
11676 /* Register: SPIS_EVENTS_ACQUIRED */
11677 /* Description: Semaphore acquired */
11678 
11679 /* Bit 0 : Semaphore acquired */
11680 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
11681 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
11682 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0x0UL) /*!< Event not generated */
11683 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (0x1UL) /*!< Event generated */
11684 
11685 /* Register: SPIS_PUBLISH_END */
11686 /* Description: Publish configuration for event END */
11687 
11688 /* Bit 31 :   */
11689 #define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
11690 #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
11691 #define SPIS_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */
11692 #define SPIS_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */
11693 
11694 /* Bits 7..0 : DPPI channel that event END will publish to */
11695 #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11696 #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11697 
11698 /* Register: SPIS_PUBLISH_ENDRX */
11699 /* Description: Publish configuration for event ENDRX */
11700 
11701 /* Bit 31 :   */
11702 #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
11703 #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
11704 #define SPIS_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */
11705 #define SPIS_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */
11706 
11707 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */
11708 #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11709 #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11710 
11711 /* Register: SPIS_PUBLISH_ACQUIRED */
11712 /* Description: Publish configuration for event ACQUIRED */
11713 
11714 /* Bit 31 :   */
11715 #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */
11716 #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */
11717 #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0x0UL) /*!< Disable publishing */
11718 #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (0x1UL) /*!< Enable publishing */
11719 
11720 /* Bits 7..0 : DPPI channel that event ACQUIRED will publish to */
11721 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11722 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11723 
11724 /* Register: SPIS_SHORTS */
11725 /* Description: Shortcuts between local events and tasks */
11726 
11727 /* Bit 2 : Shortcut between event END and task ACQUIRE */
11728 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
11729 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
11730 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0x0UL) /*!< Disable shortcut */
11731 #define SPIS_SHORTS_END_ACQUIRE_Enabled (0x1UL) /*!< Enable shortcut */
11732 
11733 /* Register: SPIS_INTENSET */
11734 /* Description: Enable interrupt */
11735 
11736 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
11737 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
11738 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
11739 #define SPIS_INTENSET_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */
11740 #define SPIS_INTENSET_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */
11741 #define SPIS_INTENSET_ACQUIRED_Set (0x1UL) /*!< Enable */
11742 
11743 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
11744 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
11745 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
11746 #define SPIS_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
11747 #define SPIS_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
11748 #define SPIS_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */
11749 
11750 /* Bit 1 : Write '1' to enable interrupt for event END */
11751 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
11752 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
11753 #define SPIS_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
11754 #define SPIS_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
11755 #define SPIS_INTENSET_END_Set (0x1UL) /*!< Enable */
11756 
11757 /* Register: SPIS_INTENCLR */
11758 /* Description: Disable interrupt */
11759 
11760 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
11761 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
11762 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
11763 #define SPIS_INTENCLR_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */
11764 #define SPIS_INTENCLR_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */
11765 #define SPIS_INTENCLR_ACQUIRED_Clear (0x1UL) /*!< Disable */
11766 
11767 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
11768 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
11769 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
11770 #define SPIS_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
11771 #define SPIS_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
11772 #define SPIS_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */
11773 
11774 /* Bit 1 : Write '1' to disable interrupt for event END */
11775 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
11776 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
11777 #define SPIS_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
11778 #define SPIS_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
11779 #define SPIS_INTENCLR_END_Clear (0x1UL) /*!< Disable */
11780 
11781 /* Register: SPIS_SEMSTAT */
11782 /* Description: Semaphore status register */
11783 
11784 /* Bits 1..0 : Semaphore status */
11785 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
11786 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
11787 #define SPIS_SEMSTAT_SEMSTAT_Free (0x0UL) /*!< Semaphore is free */
11788 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x1UL) /*!< Semaphore is assigned to CPU */
11789 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x2UL) /*!< Semaphore is assigned to SPI slave */
11790 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
11791 
11792 /* Register: SPIS_STATUS */
11793 /* Description: Status from last transaction */
11794 
11795 /* Bit 1 : RX buffer overflow detected, and prevented */
11796 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
11797 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
11798 #define SPIS_STATUS_OVERFLOW_NotPresent (0x0UL) /*!< Read: error not present */
11799 #define SPIS_STATUS_OVERFLOW_Present (0x1UL) /*!< Read: error present */
11800 #define SPIS_STATUS_OVERFLOW_Clear (0x1UL) /*!< Write: clear error on writing '1' */
11801 
11802 /* Bit 0 : TX buffer over-read detected, and prevented */
11803 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
11804 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
11805 #define SPIS_STATUS_OVERREAD_NotPresent (0x0UL) /*!< Read: error not present */
11806 #define SPIS_STATUS_OVERREAD_Present (0x1UL) /*!< Read: error present */
11807 #define SPIS_STATUS_OVERREAD_Clear (0x1UL) /*!< Write: clear error on writing '1' */
11808 
11809 /* Register: SPIS_ENABLE */
11810 /* Description: Enable SPI slave */
11811 
11812 /* Bits 3..0 : Enable or disable SPI slave */
11813 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11814 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11815 #define SPIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPI slave */
11816 #define SPIS_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable SPI slave */
11817 
11818 /* Register: SPIS_PSEL_SCK */
11819 /* Description: Pin select for SCK */
11820 
11821 /* Bit 31 : Connection */
11822 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11823 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11824 #define SPIS_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
11825 #define SPIS_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11826 
11827 /* Bits 4..0 : Pin number */
11828 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
11829 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
11830 
11831 /* Register: SPIS_PSEL_MISO */
11832 /* Description: Pin select for MISO signal */
11833 
11834 /* Bit 31 : Connection */
11835 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11836 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11837 #define SPIS_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */
11838 #define SPIS_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11839 
11840 /* Bits 4..0 : Pin number */
11841 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
11842 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
11843 
11844 /* Register: SPIS_PSEL_MOSI */
11845 /* Description: Pin select for MOSI signal */
11846 
11847 /* Bit 31 : Connection */
11848 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11849 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11850 #define SPIS_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */
11851 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11852 
11853 /* Bits 4..0 : Pin number */
11854 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
11855 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
11856 
11857 /* Register: SPIS_PSEL_CSN */
11858 /* Description: Pin select for CSN signal */
11859 
11860 /* Bit 31 : Connection */
11861 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11862 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11863 #define SPIS_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */
11864 #define SPIS_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11865 
11866 /* Bits 4..0 : Pin number */
11867 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
11868 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
11869 
11870 /* Register: SPIS_RXD_PTR */
11871 /* Description: RXD data pointer */
11872 
11873 /* Bits 31..0 : RXD data pointer */
11874 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11875 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11876 
11877 /* Register: SPIS_RXD_MAXCNT */
11878 /* Description: Maximum number of bytes in receive buffer */
11879 
11880 /* Bits 12..0 : Maximum number of bytes in receive buffer */
11881 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11882 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11883 
11884 /* Register: SPIS_RXD_AMOUNT */
11885 /* Description: Number of bytes received in last granted transaction */
11886 
11887 /* Bits 12..0 : Number of bytes received in the last granted transaction */
11888 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11889 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11890 
11891 /* Register: SPIS_RXD_LIST */
11892 /* Description: EasyDMA list type */
11893 
11894 /* Bits 1..0 : List type */
11895 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11896 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11897 #define SPIS_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
11898 #define SPIS_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
11899 
11900 /* Register: SPIS_TXD_PTR */
11901 /* Description: TXD data pointer */
11902 
11903 /* Bits 31..0 : TXD data pointer */
11904 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11905 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11906 
11907 /* Register: SPIS_TXD_MAXCNT */
11908 /* Description: Maximum number of bytes in transmit buffer */
11909 
11910 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
11911 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11912 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11913 
11914 /* Register: SPIS_TXD_AMOUNT */
11915 /* Description: Number of bytes transmitted in last granted transaction */
11916 
11917 /* Bits 12..0 : Number of bytes transmitted in last granted transaction */
11918 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11919 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11920 
11921 /* Register: SPIS_TXD_LIST */
11922 /* Description: EasyDMA list type */
11923 
11924 /* Bits 1..0 : List type */
11925 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11926 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11927 #define SPIS_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
11928 #define SPIS_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
11929 
11930 /* Register: SPIS_CONFIG */
11931 /* Description: Configuration register */
11932 
11933 /* Bit 2 : Serial clock (SCK) polarity */
11934 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
11935 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
11936 #define SPIS_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */
11937 #define SPIS_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */
11938 
11939 /* Bit 1 : Serial clock (SCK) phase */
11940 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
11941 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
11942 #define SPIS_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
11943 #define SPIS_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
11944 
11945 /* Bit 0 : Bit order */
11946 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
11947 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
11948 #define SPIS_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */
11949 #define SPIS_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */
11950 
11951 /* Register: SPIS_DEF */
11952 /* Description: Default character. Character clocked out in case of an ignored transaction. */
11953 
11954 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
11955 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
11956 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
11957 
11958 /* Register: SPIS_ORC */
11959 /* Description: Over-read character */
11960 
11961 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
11962 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
11963 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
11964 
11965 
11966 /* Peripheral: SPU */
11967 /* Description: System protection unit */
11968 
11969 /* Register: SPU_EVENTS_RAMACCERR */
11970 /* Description: A security violation has been detected for the RAM memory space */
11971 
11972 /* Bit 0 : A security violation has been detected for the RAM memory space */
11973 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL) /*!< Position of EVENTS_RAMACCERR field. */
11974 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos) /*!< Bit mask of EVENTS_RAMACCERR field. */
11975 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0x0UL) /*!< Event not generated */
11976 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (0x1UL) /*!< Event generated */
11977 
11978 /* Register: SPU_EVENTS_FLASHACCERR */
11979 /* Description: A security violation has been detected for the flash memory space */
11980 
11981 /* Bit 0 : A security violation has been detected for the flash memory space */
11982 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL) /*!< Position of EVENTS_FLASHACCERR field. */
11983 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos) /*!< Bit mask of EVENTS_FLASHACCERR field. */
11984 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0x0UL) /*!< Event not generated */
11985 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (0x1UL) /*!< Event generated */
11986 
11987 /* Register: SPU_EVENTS_PERIPHACCERR */
11988 /* Description: A security violation has been detected on one or several peripherals */
11989 
11990 /* Bit 0 : A security violation has been detected on one or several peripherals */
11991 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */
11992 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit mask of EVENTS_PERIPHACCERR field. */
11993 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0x0UL) /*!< Event not generated */
11994 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (0x1UL) /*!< Event generated */
11995 
11996 /* Register: SPU_PUBLISH_RAMACCERR */
11997 /* Description: Publish configuration for event RAMACCERR */
11998 
11999 /* Bit 31 :   */
12000 #define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL) /*!< Position of EN field. */
12001 #define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos) /*!< Bit mask of EN field. */
12002 #define SPU_PUBLISH_RAMACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */
12003 #define SPU_PUBLISH_RAMACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */
12004 
12005 /* Bits 7..0 : DPPI channel that event RAMACCERR will publish to */
12006 #define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12007 #define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12008 
12009 /* Register: SPU_PUBLISH_FLASHACCERR */
12010 /* Description: Publish configuration for event FLASHACCERR */
12011 
12012 /* Bit 31 :   */
12013 #define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
12014 #define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos) /*!< Bit mask of EN field. */
12015 #define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */
12016 #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */
12017 
12018 /* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to */
12019 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12020 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12021 
12022 /* Register: SPU_PUBLISH_PERIPHACCERR */
12023 /* Description: Publish configuration for event PERIPHACCERR */
12024 
12025 /* Bit 31 :   */
12026 #define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
12027 #define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos) /*!< Bit mask of EN field. */
12028 #define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */
12029 #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */
12030 
12031 /* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to */
12032 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12033 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12034 
12035 /* Register: SPU_INTEN */
12036 /* Description: Enable or disable interrupt */
12037 
12038 /* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */
12039 #define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
12040 #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
12041 #define SPU_INTEN_PERIPHACCERR_Disabled (0x0UL) /*!< Disable */
12042 #define SPU_INTEN_PERIPHACCERR_Enabled (0x1UL) /*!< Enable */
12043 
12044 /* Bit 1 : Enable or disable interrupt for event FLASHACCERR */
12045 #define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
12046 #define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
12047 #define SPU_INTEN_FLASHACCERR_Disabled (0x0UL) /*!< Disable */
12048 #define SPU_INTEN_FLASHACCERR_Enabled (0x1UL) /*!< Enable */
12049 
12050 /* Bit 0 : Enable or disable interrupt for event RAMACCERR */
12051 #define SPU_INTEN_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
12052 #define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
12053 #define SPU_INTEN_RAMACCERR_Disabled (0x0UL) /*!< Disable */
12054 #define SPU_INTEN_RAMACCERR_Enabled (0x1UL) /*!< Enable */
12055 
12056 /* Register: SPU_INTENSET */
12057 /* Description: Enable interrupt */
12058 
12059 /* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */
12060 #define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
12061 #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
12062 #define SPU_INTENSET_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */
12063 #define SPU_INTENSET_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */
12064 #define SPU_INTENSET_PERIPHACCERR_Set (0x1UL) /*!< Enable */
12065 
12066 /* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */
12067 #define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
12068 #define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
12069 #define SPU_INTENSET_FLASHACCERR_Disabled (0x0UL) /*!< Read: Disabled */
12070 #define SPU_INTENSET_FLASHACCERR_Enabled (0x1UL) /*!< Read: Enabled */
12071 #define SPU_INTENSET_FLASHACCERR_Set (0x1UL) /*!< Enable */
12072 
12073 /* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */
12074 #define SPU_INTENSET_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
12075 #define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
12076 #define SPU_INTENSET_RAMACCERR_Disabled (0x0UL) /*!< Read: Disabled */
12077 #define SPU_INTENSET_RAMACCERR_Enabled (0x1UL) /*!< Read: Enabled */
12078 #define SPU_INTENSET_RAMACCERR_Set (0x1UL) /*!< Enable */
12079 
12080 /* Register: SPU_INTENCLR */
12081 /* Description: Disable interrupt */
12082 
12083 /* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */
12084 #define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
12085 #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
12086 #define SPU_INTENCLR_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */
12087 #define SPU_INTENCLR_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */
12088 #define SPU_INTENCLR_PERIPHACCERR_Clear (0x1UL) /*!< Disable */
12089 
12090 /* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */
12091 #define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
12092 #define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
12093 #define SPU_INTENCLR_FLASHACCERR_Disabled (0x0UL) /*!< Read: Disabled */
12094 #define SPU_INTENCLR_FLASHACCERR_Enabled (0x1UL) /*!< Read: Enabled */
12095 #define SPU_INTENCLR_FLASHACCERR_Clear (0x1UL) /*!< Disable */
12096 
12097 /* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */
12098 #define SPU_INTENCLR_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
12099 #define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
12100 #define SPU_INTENCLR_RAMACCERR_Disabled (0x0UL) /*!< Read: Disabled */
12101 #define SPU_INTENCLR_RAMACCERR_Enabled (0x1UL) /*!< Read: Enabled */
12102 #define SPU_INTENCLR_RAMACCERR_Clear (0x1UL) /*!< Disable */
12103 
12104 /* Register: SPU_CAP */
12105 /* Description: Show implemented features for the current device */
12106 
12107 /* Bit 0 : Show ARM TrustZone status */
12108 #define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */
12109 #define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */
12110 #define SPU_CAP_TZM_NotAvailable (0x0UL) /*!< ARM TrustZone support not available */
12111 #define SPU_CAP_TZM_Enabled (0x1UL) /*!< ARM TrustZone support is available */
12112 
12113 /* Register: SPU_EXTDOMAIN_PERM */
12114 /* Description: Description cluster: Access  for bus access generated from the external domain n List capabilities of the external domain  n */
12115 
12116 /* Bit 8 :   */
12117 #define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
12118 #define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
12119 #define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
12120 #define SPU_EXTDOMAIN_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */
12121 
12122 /* Bit 4 : Peripheral security mapping */
12123 #define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
12124 #define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
12125 #define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0x0UL) /*!< Bus accesses from this domain have the non-secure attribute set */
12126 #define SPU_EXTDOMAIN_PERM_SECATTR_Secure (0x1UL) /*!< Bus accesses from this domain have secure attribute set */
12127 
12128 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
12129 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
12130 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
12131 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< The bus access from this external domain always have the non-secure attribute set */
12132 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (0x1UL) /*!< The bus access from this external domain always have the secure attribute set */
12133 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */
12134 
12135 /* Register: SPU_DPPI_PERM */
12136 /* Description: Description cluster: Select between secure and non-secure attribute  for the DPPI channels. */
12137 
12138 /* Bit 15 : Select secure attribute. */
12139 #define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */
12140 #define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */
12141 #define SPU_DPPI_PERM_CHANNEL15_NonSecure (0x0UL) /*!< Channel15 has its non-secure attribute set */
12142 #define SPU_DPPI_PERM_CHANNEL15_Secure (0x1UL) /*!< Channel15 has its secure attribute set */
12143 
12144 /* Bit 14 : Select secure attribute. */
12145 #define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */
12146 #define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */
12147 #define SPU_DPPI_PERM_CHANNEL14_NonSecure (0x0UL) /*!< Channel14 has its non-secure attribute set */
12148 #define SPU_DPPI_PERM_CHANNEL14_Secure (0x1UL) /*!< Channel14 has its secure attribute set */
12149 
12150 /* Bit 13 : Select secure attribute. */
12151 #define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */
12152 #define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */
12153 #define SPU_DPPI_PERM_CHANNEL13_NonSecure (0x0UL) /*!< Channel13 has its non-secure attribute set */
12154 #define SPU_DPPI_PERM_CHANNEL13_Secure (0x1UL) /*!< Channel13 has its secure attribute set */
12155 
12156 /* Bit 12 : Select secure attribute. */
12157 #define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */
12158 #define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */
12159 #define SPU_DPPI_PERM_CHANNEL12_NonSecure (0x0UL) /*!< Channel12 has its non-secure attribute set */
12160 #define SPU_DPPI_PERM_CHANNEL12_Secure (0x1UL) /*!< Channel12 has its secure attribute set */
12161 
12162 /* Bit 11 : Select secure attribute. */
12163 #define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */
12164 #define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */
12165 #define SPU_DPPI_PERM_CHANNEL11_NonSecure (0x0UL) /*!< Channel11 has its non-secure attribute set */
12166 #define SPU_DPPI_PERM_CHANNEL11_Secure (0x1UL) /*!< Channel11 has its secure attribute set */
12167 
12168 /* Bit 10 : Select secure attribute. */
12169 #define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */
12170 #define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */
12171 #define SPU_DPPI_PERM_CHANNEL10_NonSecure (0x0UL) /*!< Channel10 has its non-secure attribute set */
12172 #define SPU_DPPI_PERM_CHANNEL10_Secure (0x1UL) /*!< Channel10 has its secure attribute set */
12173 
12174 /* Bit 9 : Select secure attribute. */
12175 #define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */
12176 #define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */
12177 #define SPU_DPPI_PERM_CHANNEL9_NonSecure (0x0UL) /*!< Channel9 has its non-secure attribute set */
12178 #define SPU_DPPI_PERM_CHANNEL9_Secure (0x1UL) /*!< Channel9 has its secure attribute set */
12179 
12180 /* Bit 8 : Select secure attribute. */
12181 #define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */
12182 #define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */
12183 #define SPU_DPPI_PERM_CHANNEL8_NonSecure (0x0UL) /*!< Channel8 has its non-secure attribute set */
12184 #define SPU_DPPI_PERM_CHANNEL8_Secure (0x1UL) /*!< Channel8 has its secure attribute set */
12185 
12186 /* Bit 7 : Select secure attribute. */
12187 #define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */
12188 #define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */
12189 #define SPU_DPPI_PERM_CHANNEL7_NonSecure (0x0UL) /*!< Channel7 has its non-secure attribute set */
12190 #define SPU_DPPI_PERM_CHANNEL7_Secure (0x1UL) /*!< Channel7 has its secure attribute set */
12191 
12192 /* Bit 6 : Select secure attribute. */
12193 #define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */
12194 #define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */
12195 #define SPU_DPPI_PERM_CHANNEL6_NonSecure (0x0UL) /*!< Channel6 has its non-secure attribute set */
12196 #define SPU_DPPI_PERM_CHANNEL6_Secure (0x1UL) /*!< Channel6 has its secure attribute set */
12197 
12198 /* Bit 5 : Select secure attribute. */
12199 #define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */
12200 #define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */
12201 #define SPU_DPPI_PERM_CHANNEL5_NonSecure (0x0UL) /*!< Channel5 has its non-secure attribute set */
12202 #define SPU_DPPI_PERM_CHANNEL5_Secure (0x1UL) /*!< Channel5 has its secure attribute set */
12203 
12204 /* Bit 4 : Select secure attribute. */
12205 #define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */
12206 #define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */
12207 #define SPU_DPPI_PERM_CHANNEL4_NonSecure (0x0UL) /*!< Channel4 has its non-secure attribute set */
12208 #define SPU_DPPI_PERM_CHANNEL4_Secure (0x1UL) /*!< Channel4 has its secure attribute set */
12209 
12210 /* Bit 3 : Select secure attribute. */
12211 #define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */
12212 #define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */
12213 #define SPU_DPPI_PERM_CHANNEL3_NonSecure (0x0UL) /*!< Channel3 has its non-secure attribute set */
12214 #define SPU_DPPI_PERM_CHANNEL3_Secure (0x1UL) /*!< Channel3 has its secure attribute set */
12215 
12216 /* Bit 2 : Select secure attribute. */
12217 #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */
12218 #define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */
12219 #define SPU_DPPI_PERM_CHANNEL2_NonSecure (0x0UL) /*!< Channel2 has its non-secure attribute set */
12220 #define SPU_DPPI_PERM_CHANNEL2_Secure (0x1UL) /*!< Channel2 has its secure attribute set */
12221 
12222 /* Bit 1 : Select secure attribute. */
12223 #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */
12224 #define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */
12225 #define SPU_DPPI_PERM_CHANNEL1_NonSecure (0x0UL) /*!< Channel1 has its non-secure attribute set */
12226 #define SPU_DPPI_PERM_CHANNEL1_Secure (0x1UL) /*!< Channel1 has its secure attribute set */
12227 
12228 /* Bit 0 : Select secure attribute. */
12229 #define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */
12230 #define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */
12231 #define SPU_DPPI_PERM_CHANNEL0_NonSecure (0x0UL) /*!< Channel0 has its non-secure attribute set */
12232 #define SPU_DPPI_PERM_CHANNEL0_Secure (0x1UL) /*!< Channel0 has its secure attribute set */
12233 
12234 /* Register: SPU_DPPI_LOCK */
12235 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */
12236 
12237 /* Bit 0 :   */
12238 #define SPU_DPPI_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
12239 #define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
12240 #define SPU_DPPI_LOCK_LOCK_Unlocked (0x0UL) /*!< DPPI[n].PERM register content can be changed */
12241 #define SPU_DPPI_LOCK_LOCK_Locked (0x1UL) /*!< DPPI[n].PERM register can't be changed until next reset */
12242 
12243 /* Register: SPU_GPIOPORT_PERM */
12244 /* Description: Description cluster: Select between secure and non-secure attribute  for pins 0 to 31  of port n. */
12245 
12246 /* Bit 31 : Select secure attribute attribute for PIN 31. */
12247 #define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
12248 #define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos) /*!< Bit mask of PIN31 field. */
12249 #define SPU_GPIOPORT_PERM_PIN31_NonSecure (0x0UL) /*!< Pin 31 has its non-secure attribute set */
12250 #define SPU_GPIOPORT_PERM_PIN31_Secure (0x1UL) /*!< Pin 31 has its secure attribute set */
12251 
12252 /* Bit 30 : Select secure attribute attribute for PIN 30. */
12253 #define SPU_GPIOPORT_PERM_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
12254 #define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos) /*!< Bit mask of PIN30 field. */
12255 #define SPU_GPIOPORT_PERM_PIN30_NonSecure (0x0UL) /*!< Pin 30 has its non-secure attribute set */
12256 #define SPU_GPIOPORT_PERM_PIN30_Secure (0x1UL) /*!< Pin 30 has its secure attribute set */
12257 
12258 /* Bit 29 : Select secure attribute attribute for PIN 29. */
12259 #define SPU_GPIOPORT_PERM_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
12260 #define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos) /*!< Bit mask of PIN29 field. */
12261 #define SPU_GPIOPORT_PERM_PIN29_NonSecure (0x0UL) /*!< Pin 29 has its non-secure attribute set */
12262 #define SPU_GPIOPORT_PERM_PIN29_Secure (0x1UL) /*!< Pin 29 has its secure attribute set */
12263 
12264 /* Bit 28 : Select secure attribute attribute for PIN 28. */
12265 #define SPU_GPIOPORT_PERM_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
12266 #define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos) /*!< Bit mask of PIN28 field. */
12267 #define SPU_GPIOPORT_PERM_PIN28_NonSecure (0x0UL) /*!< Pin 28 has its non-secure attribute set */
12268 #define SPU_GPIOPORT_PERM_PIN28_Secure (0x1UL) /*!< Pin 28 has its secure attribute set */
12269 
12270 /* Bit 27 : Select secure attribute attribute for PIN 27. */
12271 #define SPU_GPIOPORT_PERM_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
12272 #define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos) /*!< Bit mask of PIN27 field. */
12273 #define SPU_GPIOPORT_PERM_PIN27_NonSecure (0x0UL) /*!< Pin 27 has its non-secure attribute set */
12274 #define SPU_GPIOPORT_PERM_PIN27_Secure (0x1UL) /*!< Pin 27 has its secure attribute set */
12275 
12276 /* Bit 26 : Select secure attribute attribute for PIN 26. */
12277 #define SPU_GPIOPORT_PERM_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
12278 #define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos) /*!< Bit mask of PIN26 field. */
12279 #define SPU_GPIOPORT_PERM_PIN26_NonSecure (0x0UL) /*!< Pin 26 has its non-secure attribute set */
12280 #define SPU_GPIOPORT_PERM_PIN26_Secure (0x1UL) /*!< Pin 26 has its secure attribute set */
12281 
12282 /* Bit 25 : Select secure attribute attribute for PIN 25. */
12283 #define SPU_GPIOPORT_PERM_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
12284 #define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos) /*!< Bit mask of PIN25 field. */
12285 #define SPU_GPIOPORT_PERM_PIN25_NonSecure (0x0UL) /*!< Pin 25 has its non-secure attribute set */
12286 #define SPU_GPIOPORT_PERM_PIN25_Secure (0x1UL) /*!< Pin 25 has its secure attribute set */
12287 
12288 /* Bit 24 : Select secure attribute attribute for PIN 24. */
12289 #define SPU_GPIOPORT_PERM_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
12290 #define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos) /*!< Bit mask of PIN24 field. */
12291 #define SPU_GPIOPORT_PERM_PIN24_NonSecure (0x0UL) /*!< Pin 24 has its non-secure attribute set */
12292 #define SPU_GPIOPORT_PERM_PIN24_Secure (0x1UL) /*!< Pin 24 has its secure attribute set */
12293 
12294 /* Bit 23 : Select secure attribute attribute for PIN 23. */
12295 #define SPU_GPIOPORT_PERM_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
12296 #define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos) /*!< Bit mask of PIN23 field. */
12297 #define SPU_GPIOPORT_PERM_PIN23_NonSecure (0x0UL) /*!< Pin 23 has its non-secure attribute set */
12298 #define SPU_GPIOPORT_PERM_PIN23_Secure (0x1UL) /*!< Pin 23 has its secure attribute set */
12299 
12300 /* Bit 22 : Select secure attribute attribute for PIN 22. */
12301 #define SPU_GPIOPORT_PERM_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
12302 #define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos) /*!< Bit mask of PIN22 field. */
12303 #define SPU_GPIOPORT_PERM_PIN22_NonSecure (0x0UL) /*!< Pin 22 has its non-secure attribute set */
12304 #define SPU_GPIOPORT_PERM_PIN22_Secure (0x1UL) /*!< Pin 22 has its secure attribute set */
12305 
12306 /* Bit 21 : Select secure attribute attribute for PIN 21. */
12307 #define SPU_GPIOPORT_PERM_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
12308 #define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos) /*!< Bit mask of PIN21 field. */
12309 #define SPU_GPIOPORT_PERM_PIN21_NonSecure (0x0UL) /*!< Pin 21 has its non-secure attribute set */
12310 #define SPU_GPIOPORT_PERM_PIN21_Secure (0x1UL) /*!< Pin 21 has its secure attribute set */
12311 
12312 /* Bit 20 : Select secure attribute attribute for PIN 20. */
12313 #define SPU_GPIOPORT_PERM_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
12314 #define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos) /*!< Bit mask of PIN20 field. */
12315 #define SPU_GPIOPORT_PERM_PIN20_NonSecure (0x0UL) /*!< Pin 20 has its non-secure attribute set */
12316 #define SPU_GPIOPORT_PERM_PIN20_Secure (0x1UL) /*!< Pin 20 has its secure attribute set */
12317 
12318 /* Bit 19 : Select secure attribute attribute for PIN 19. */
12319 #define SPU_GPIOPORT_PERM_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
12320 #define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos) /*!< Bit mask of PIN19 field. */
12321 #define SPU_GPIOPORT_PERM_PIN19_NonSecure (0x0UL) /*!< Pin 19 has its non-secure attribute set */
12322 #define SPU_GPIOPORT_PERM_PIN19_Secure (0x1UL) /*!< Pin 19 has its secure attribute set */
12323 
12324 /* Bit 18 : Select secure attribute attribute for PIN 18. */
12325 #define SPU_GPIOPORT_PERM_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
12326 #define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos) /*!< Bit mask of PIN18 field. */
12327 #define SPU_GPIOPORT_PERM_PIN18_NonSecure (0x0UL) /*!< Pin 18 has its non-secure attribute set */
12328 #define SPU_GPIOPORT_PERM_PIN18_Secure (0x1UL) /*!< Pin 18 has its secure attribute set */
12329 
12330 /* Bit 17 : Select secure attribute attribute for PIN 17. */
12331 #define SPU_GPIOPORT_PERM_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
12332 #define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos) /*!< Bit mask of PIN17 field. */
12333 #define SPU_GPIOPORT_PERM_PIN17_NonSecure (0x0UL) /*!< Pin 17 has its non-secure attribute set */
12334 #define SPU_GPIOPORT_PERM_PIN17_Secure (0x1UL) /*!< Pin 17 has its secure attribute set */
12335 
12336 /* Bit 16 : Select secure attribute attribute for PIN 16. */
12337 #define SPU_GPIOPORT_PERM_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
12338 #define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos) /*!< Bit mask of PIN16 field. */
12339 #define SPU_GPIOPORT_PERM_PIN16_NonSecure (0x0UL) /*!< Pin 16 has its non-secure attribute set */
12340 #define SPU_GPIOPORT_PERM_PIN16_Secure (0x1UL) /*!< Pin 16 has its secure attribute set */
12341 
12342 /* Bit 15 : Select secure attribute attribute for PIN 15. */
12343 #define SPU_GPIOPORT_PERM_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
12344 #define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos) /*!< Bit mask of PIN15 field. */
12345 #define SPU_GPIOPORT_PERM_PIN15_NonSecure (0x0UL) /*!< Pin 15 has its non-secure attribute set */
12346 #define SPU_GPIOPORT_PERM_PIN15_Secure (0x1UL) /*!< Pin 15 has its secure attribute set */
12347 
12348 /* Bit 14 : Select secure attribute attribute for PIN 14. */
12349 #define SPU_GPIOPORT_PERM_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
12350 #define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos) /*!< Bit mask of PIN14 field. */
12351 #define SPU_GPIOPORT_PERM_PIN14_NonSecure (0x0UL) /*!< Pin 14 has its non-secure attribute set */
12352 #define SPU_GPIOPORT_PERM_PIN14_Secure (0x1UL) /*!< Pin 14 has its secure attribute set */
12353 
12354 /* Bit 13 : Select secure attribute attribute for PIN 13. */
12355 #define SPU_GPIOPORT_PERM_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
12356 #define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos) /*!< Bit mask of PIN13 field. */
12357 #define SPU_GPIOPORT_PERM_PIN13_NonSecure (0x0UL) /*!< Pin 13 has its non-secure attribute set */
12358 #define SPU_GPIOPORT_PERM_PIN13_Secure (0x1UL) /*!< Pin 13 has its secure attribute set */
12359 
12360 /* Bit 12 : Select secure attribute attribute for PIN 12. */
12361 #define SPU_GPIOPORT_PERM_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
12362 #define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos) /*!< Bit mask of PIN12 field. */
12363 #define SPU_GPIOPORT_PERM_PIN12_NonSecure (0x0UL) /*!< Pin 12 has its non-secure attribute set */
12364 #define SPU_GPIOPORT_PERM_PIN12_Secure (0x1UL) /*!< Pin 12 has its secure attribute set */
12365 
12366 /* Bit 11 : Select secure attribute attribute for PIN 11. */
12367 #define SPU_GPIOPORT_PERM_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
12368 #define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos) /*!< Bit mask of PIN11 field. */
12369 #define SPU_GPIOPORT_PERM_PIN11_NonSecure (0x0UL) /*!< Pin 11 has its non-secure attribute set */
12370 #define SPU_GPIOPORT_PERM_PIN11_Secure (0x1UL) /*!< Pin 11 has its secure attribute set */
12371 
12372 /* Bit 10 : Select secure attribute attribute for PIN 10. */
12373 #define SPU_GPIOPORT_PERM_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
12374 #define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos) /*!< Bit mask of PIN10 field. */
12375 #define SPU_GPIOPORT_PERM_PIN10_NonSecure (0x0UL) /*!< Pin 10 has its non-secure attribute set */
12376 #define SPU_GPIOPORT_PERM_PIN10_Secure (0x1UL) /*!< Pin 10 has its secure attribute set */
12377 
12378 /* Bit 9 : Select secure attribute attribute for PIN 9. */
12379 #define SPU_GPIOPORT_PERM_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
12380 #define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos) /*!< Bit mask of PIN9 field. */
12381 #define SPU_GPIOPORT_PERM_PIN9_NonSecure (0x0UL) /*!< Pin 9 has its non-secure attribute set */
12382 #define SPU_GPIOPORT_PERM_PIN9_Secure (0x1UL) /*!< Pin 9 has its secure attribute set */
12383 
12384 /* Bit 8 : Select secure attribute attribute for PIN 8. */
12385 #define SPU_GPIOPORT_PERM_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
12386 #define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos) /*!< Bit mask of PIN8 field. */
12387 #define SPU_GPIOPORT_PERM_PIN8_NonSecure (0x0UL) /*!< Pin 8 has its non-secure attribute set */
12388 #define SPU_GPIOPORT_PERM_PIN8_Secure (0x1UL) /*!< Pin 8 has its secure attribute set */
12389 
12390 /* Bit 7 : Select secure attribute attribute for PIN 7. */
12391 #define SPU_GPIOPORT_PERM_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
12392 #define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos) /*!< Bit mask of PIN7 field. */
12393 #define SPU_GPIOPORT_PERM_PIN7_NonSecure (0x0UL) /*!< Pin 7 has its non-secure attribute set */
12394 #define SPU_GPIOPORT_PERM_PIN7_Secure (0x1UL) /*!< Pin 7 has its secure attribute set */
12395 
12396 /* Bit 6 : Select secure attribute attribute for PIN 6. */
12397 #define SPU_GPIOPORT_PERM_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
12398 #define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos) /*!< Bit mask of PIN6 field. */
12399 #define SPU_GPIOPORT_PERM_PIN6_NonSecure (0x0UL) /*!< Pin 6 has its non-secure attribute set */
12400 #define SPU_GPIOPORT_PERM_PIN6_Secure (0x1UL) /*!< Pin 6 has its secure attribute set */
12401 
12402 /* Bit 5 : Select secure attribute attribute for PIN 5. */
12403 #define SPU_GPIOPORT_PERM_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
12404 #define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos) /*!< Bit mask of PIN5 field. */
12405 #define SPU_GPIOPORT_PERM_PIN5_NonSecure (0x0UL) /*!< Pin 5 has its non-secure attribute set */
12406 #define SPU_GPIOPORT_PERM_PIN5_Secure (0x1UL) /*!< Pin 5 has its secure attribute set */
12407 
12408 /* Bit 4 : Select secure attribute attribute for PIN 4. */
12409 #define SPU_GPIOPORT_PERM_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
12410 #define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos) /*!< Bit mask of PIN4 field. */
12411 #define SPU_GPIOPORT_PERM_PIN4_NonSecure (0x0UL) /*!< Pin 4 has its non-secure attribute set */
12412 #define SPU_GPIOPORT_PERM_PIN4_Secure (0x1UL) /*!< Pin 4 has its secure attribute set */
12413 
12414 /* Bit 3 : Select secure attribute attribute for PIN 3. */
12415 #define SPU_GPIOPORT_PERM_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
12416 #define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos) /*!< Bit mask of PIN3 field. */
12417 #define SPU_GPIOPORT_PERM_PIN3_NonSecure (0x0UL) /*!< Pin 3 has its non-secure attribute set */
12418 #define SPU_GPIOPORT_PERM_PIN3_Secure (0x1UL) /*!< Pin 3 has its secure attribute set */
12419 
12420 /* Bit 2 : Select secure attribute attribute for PIN 2. */
12421 #define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
12422 #define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos) /*!< Bit mask of PIN2 field. */
12423 #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0x0UL) /*!< Pin 2 has its non-secure attribute set */
12424 #define SPU_GPIOPORT_PERM_PIN2_Secure (0x1UL) /*!< Pin 2 has its secure attribute set */
12425 
12426 /* Bit 1 : Select secure attribute attribute for PIN 1. */
12427 #define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
12428 #define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos) /*!< Bit mask of PIN1 field. */
12429 #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0x0UL) /*!< Pin 1 has its non-secure attribute set */
12430 #define SPU_GPIOPORT_PERM_PIN1_Secure (0x1UL) /*!< Pin 1 has its secure attribute set */
12431 
12432 /* Bit 0 : Select secure attribute attribute for PIN 0. */
12433 #define SPU_GPIOPORT_PERM_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
12434 #define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos) /*!< Bit mask of PIN0 field. */
12435 #define SPU_GPIOPORT_PERM_PIN0_NonSecure (0x0UL) /*!< Pin 0 has its non-secure attribute set */
12436 #define SPU_GPIOPORT_PERM_PIN0_Secure (0x1UL) /*!< Pin 0 has its secure attribute set */
12437 
12438 /* Register: SPU_GPIOPORT_LOCK */
12439 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */
12440 
12441 /* Bit 0 :   */
12442 #define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
12443 #define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
12444 #define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0x0UL) /*!< GPIOPORT[n].PERM register content can be changed */
12445 #define SPU_GPIOPORT_LOCK_LOCK_Locked (0x1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */
12446 
12447 /* Register: SPU_FLASHNSC_REGION */
12448 /* Description: Description cluster: Define which flash region can contain the non-secure callable (NSC) region n */
12449 
12450 /* Bit 8 :   */
12451 #define SPU_FLASHNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
12452 #define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
12453 #define SPU_FLASHNSC_REGION_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
12454 #define SPU_FLASHNSC_REGION_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */
12455 
12456 /* Bits 4..0 : Region number */
12457 #define SPU_FLASHNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
12458 #define SPU_FLASHNSC_REGION_REGION_Msk (0x1FUL << SPU_FLASHNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
12459 
12460 /* Register: SPU_FLASHNSC_SIZE */
12461 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
12462 
12463 /* Bit 8 :   */
12464 #define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
12465 #define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
12466 #define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
12467 #define SPU_FLASHNSC_SIZE_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */
12468 
12469 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
12470 #define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
12471 #define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
12472 #define SPU_FLASHNSC_SIZE_SIZE_Disabled (0x0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
12473 #define SPU_FLASHNSC_SIZE_SIZE_32 (0x1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */
12474 #define SPU_FLASHNSC_SIZE_SIZE_64 (0x2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */
12475 #define SPU_FLASHNSC_SIZE_SIZE_128 (0x3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */
12476 #define SPU_FLASHNSC_SIZE_SIZE_256 (0x4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */
12477 #define SPU_FLASHNSC_SIZE_SIZE_512 (0x5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */
12478 #define SPU_FLASHNSC_SIZE_SIZE_1024 (0x6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */
12479 #define SPU_FLASHNSC_SIZE_SIZE_2048 (0x7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */
12480 #define SPU_FLASHNSC_SIZE_SIZE_4096 (0x8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */
12481 
12482 /* Register: SPU_RAMNSC_REGION */
12483 /* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */
12484 
12485 /* Bit 8 :   */
12486 #define SPU_RAMNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
12487 #define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
12488 #define SPU_RAMNSC_REGION_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
12489 #define SPU_RAMNSC_REGION_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */
12490 
12491 /* Bits 4..0 : Region number */
12492 #define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
12493 #define SPU_RAMNSC_REGION_REGION_Msk (0x1FUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
12494 
12495 /* Register: SPU_RAMNSC_SIZE */
12496 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
12497 
12498 /* Bit 8 :   */
12499 #define SPU_RAMNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
12500 #define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
12501 #define SPU_RAMNSC_SIZE_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
12502 #define SPU_RAMNSC_SIZE_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */
12503 
12504 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
12505 #define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
12506 #define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
12507 #define SPU_RAMNSC_SIZE_SIZE_Disabled (0x0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
12508 #define SPU_RAMNSC_SIZE_SIZE_32 (0x1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */
12509 #define SPU_RAMNSC_SIZE_SIZE_64 (0x2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */
12510 #define SPU_RAMNSC_SIZE_SIZE_128 (0x3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */
12511 #define SPU_RAMNSC_SIZE_SIZE_256 (0x4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */
12512 #define SPU_RAMNSC_SIZE_SIZE_512 (0x5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */
12513 #define SPU_RAMNSC_SIZE_SIZE_1024 (0x6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */
12514 #define SPU_RAMNSC_SIZE_SIZE_2048 (0x7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */
12515 #define SPU_RAMNSC_SIZE_SIZE_4096 (0x8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */
12516 
12517 /* Register: SPU_FLASHREGION_PERM */
12518 /* Description: Description cluster: Access permissions for flash region n */
12519 
12520 /* Bit 8 :   */
12521 #define SPU_FLASHREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
12522 #define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
12523 #define SPU_FLASHREGION_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
12524 #define SPU_FLASHREGION_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */
12525 
12526 /* Bit 4 : Security attribute for flash region n */
12527 #define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
12528 #define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
12529 #define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0x0UL) /*!< Flash region n security attribute is non-secure */
12530 #define SPU_FLASHREGION_PERM_SECATTR_Secure (0x1UL) /*!< Flash region n security attribute is secure */
12531 
12532 /* Bit 2 : Configure read permissions for flash region n */
12533 #define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
12534 #define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
12535 #define SPU_FLASHREGION_PERM_READ_Disable (0x0UL) /*!< Block read operation from flash region n */
12536 #define SPU_FLASHREGION_PERM_READ_Enable (0x1UL) /*!< Allow read operation from flash region n */
12537 
12538 /* Bit 1 : Configure write permission for flash region n */
12539 #define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
12540 #define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
12541 #define SPU_FLASHREGION_PERM_WRITE_Disable (0x0UL) /*!< Block write operation to region n */
12542 #define SPU_FLASHREGION_PERM_WRITE_Enable (0x1UL) /*!< Allow write operation to region n */
12543 
12544 /* Bit 0 : Configure instruction fetch permissions from flash region n */
12545 #define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
12546 #define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
12547 #define SPU_FLASHREGION_PERM_EXECUTE_Disable (0x0UL) /*!< Block instruction fetches from flash region n */
12548 #define SPU_FLASHREGION_PERM_EXECUTE_Enable (0x1UL) /*!< Allow instruction fetches from flash region n */
12549 
12550 /* Register: SPU_RAMREGION_PERM */
12551 /* Description: Description cluster: Access permissions for RAM region n */
12552 
12553 /* Bit 8 :   */
12554 #define SPU_RAMREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
12555 #define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
12556 #define SPU_RAMREGION_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
12557 #define SPU_RAMREGION_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */
12558 
12559 /* Bit 4 : Security attribute for RAM region n */
12560 #define SPU_RAMREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
12561 #define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
12562 #define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0x0UL) /*!< RAM region n security attribute is non-secure */
12563 #define SPU_RAMREGION_PERM_SECATTR_Secure (0x1UL) /*!< RAM region n security attribute is secure */
12564 
12565 /* Bit 2 : Configure read permissions for RAM region n */
12566 #define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
12567 #define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
12568 #define SPU_RAMREGION_PERM_READ_Disable (0x0UL) /*!< Block read operation from RAM region n */
12569 #define SPU_RAMREGION_PERM_READ_Enable (0x1UL) /*!< Allow read operation from RAM region n */
12570 
12571 /* Bit 1 : Configure write permission for RAM region n */
12572 #define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
12573 #define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
12574 #define SPU_RAMREGION_PERM_WRITE_Disable (0x0UL) /*!< Block write operation to RAM region n */
12575 #define SPU_RAMREGION_PERM_WRITE_Enable (0x1UL) /*!< Allow write operation to RAM region n */
12576 
12577 /* Bit 0 : Configure instruction fetch permissions from RAM region n */
12578 #define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
12579 #define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
12580 #define SPU_RAMREGION_PERM_EXECUTE_Disable (0x0UL) /*!< Block instruction fetches from RAM region n */
12581 #define SPU_RAMREGION_PERM_EXECUTE_Enable (0x1UL) /*!< Allow instruction fetches from RAM region n */
12582 
12583 /* Register: SPU_PERIPHID_PERM */
12584 /* Description: Description cluster: List capabilities and access permissions for the peripheral with ID n */
12585 
12586 /* Bit 31 : Indicate if a peripheral is present with ID n */
12587 #define SPU_PERIPHID_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */
12588 #define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */
12589 #define SPU_PERIPHID_PERM_PRESENT_NotPresent (0x0UL) /*!< Peripheral is not present */
12590 #define SPU_PERIPHID_PERM_PRESENT_IsPresent (0x1UL) /*!< Peripheral is present */
12591 
12592 /* Bit 8 :   */
12593 #define SPU_PERIPHID_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
12594 #define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
12595 #define SPU_PERIPHID_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
12596 #define SPU_PERIPHID_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */
12597 
12598 /* Bit 5 : Security attribution for the DMA transfer */
12599 #define SPU_PERIPHID_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */
12600 #define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */
12601 #define SPU_PERIPHID_PERM_DMASEC_NonSecure (0x0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */
12602 #define SPU_PERIPHID_PERM_DMASEC_Secure (0x1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */
12603 
12604 /* Bit 4 : Peripheral security mapping */
12605 #define SPU_PERIPHID_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
12606 #define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
12607 #define SPU_PERIPHID_PERM_SECATTR_NonSecure (0x0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */
12608 #define SPU_PERIPHID_PERM_SECATTR_Secure (0x1UL) /*!< Peripheral is mapped in secure peripheral address space */
12609 
12610 /* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */
12611 #define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */
12612 #define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */
12613 #define SPU_PERIPHID_PERM_DMA_NoDMA (0x0UL) /*!< Peripheral has no DMA capability */
12614 #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (0x1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */
12615 #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (0x2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */
12616 
12617 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
12618 #define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
12619 #define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
12620 #define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< This peripheral is always accessible as a non-secure peripheral */
12621 #define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (0x1UL) /*!< This peripheral is always accessible as a secure peripheral */
12622 #define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */
12623 #define SPU_PERIPHID_PERM_SECUREMAPPING_Split (0x3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */
12624 
12625 
12626 /* Peripheral: TAD */
12627 /* Description: Trace and debug control */
12628 
12629 /* Register: TAD_TASKS_CLOCKSTART */
12630 /* Description: Start all trace and debug clocks. */
12631 
12632 /* Bit 0 : Start all trace and debug clocks. */
12633 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos (0UL) /*!< Position of TASKS_CLOCKSTART field. */
12634 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk (0x1UL << TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos) /*!< Bit mask of TASKS_CLOCKSTART field. */
12635 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger (0x1UL) /*!< Trigger task */
12636 
12637 /* Register: TAD_TASKS_CLOCKSTOP */
12638 /* Description: Stop all trace and debug clocks. */
12639 
12640 /* Bit 0 : Stop all trace and debug clocks. */
12641 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos (0UL) /*!< Position of TASKS_CLOCKSTOP field. */
12642 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk (0x1UL << TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos) /*!< Bit mask of TASKS_CLOCKSTOP field. */
12643 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger (0x1UL) /*!< Trigger task */
12644 
12645 /* Register: TAD_ENABLE */
12646 /* Description: Enable debug domain and aquire selected GPIOs */
12647 
12648 /* Bit 0 :   */
12649 #define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12650 #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12651 #define TAD_ENABLE_ENABLE_DISABLED (0x0UL) /*!< Disable debug domain and release selected GPIOs */
12652 #define TAD_ENABLE_ENABLE_ENABLED (0x1UL) /*!< Enable debug domain and aquire selected GPIOs */
12653 
12654 /* Register: TAD_PSEL_TRACECLK */
12655 /* Description: Pin configuration for TRACECLK */
12656 
12657 /* Bit 31 : Connection */
12658 #define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12659 #define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12660 #define TAD_PSEL_TRACECLK_CONNECT_Connected (0x0UL) /*!< Connect */
12661 #define TAD_PSEL_TRACECLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
12662 
12663 /* Bits 4..0 : Pin number */
12664 #define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */
12665 #define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */
12666 #define TAD_PSEL_TRACECLK_PIN_Traceclk (0x15UL) /*!< TRACECLK pin */
12667 
12668 /* Register: TAD_PSEL_TRACEDATA0 */
12669 /* Description: Pin configuration for TRACEDATA[0] */
12670 
12671 /* Bit 31 : Connection */
12672 #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12673 #define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12674 #define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0x0UL) /*!< Connect */
12675 #define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
12676 
12677 /* Bits 4..0 : Pin number */
12678 #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */
12679 #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */
12680 #define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (0x16UL) /*!< TRACEDATA0 pin */
12681 
12682 /* Register: TAD_PSEL_TRACEDATA1 */
12683 /* Description: Pin configuration for TRACEDATA[1] */
12684 
12685 /* Bit 31 : Connection */
12686 #define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12687 #define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12688 #define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0x0UL) /*!< Connect */
12689 #define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
12690 
12691 /* Bits 4..0 : Pin number */
12692 #define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */
12693 #define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */
12694 #define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (0x17UL) /*!< TRACEDATA1 pin */
12695 
12696 /* Register: TAD_PSEL_TRACEDATA2 */
12697 /* Description: Pin configuration for TRACEDATA[2] */
12698 
12699 /* Bit 31 : Connection */
12700 #define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12701 #define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12702 #define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0x0UL) /*!< Connect */
12703 #define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
12704 
12705 /* Bits 4..0 : Pin number */
12706 #define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */
12707 #define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */
12708 #define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (0x18UL) /*!< TRACEDATA2 pin */
12709 
12710 /* Register: TAD_PSEL_TRACEDATA3 */
12711 /* Description: Pin configuration for TRACEDATA[3] */
12712 
12713 /* Bit 31 : Connection */
12714 #define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12715 #define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12716 #define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0x0UL) /*!< Connect */
12717 #define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
12718 
12719 /* Bits 4..0 : Pin number */
12720 #define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */
12721 #define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */
12722 #define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (0x19UL) /*!< TRACEDATA3 pin */
12723 
12724 /* Register: TAD_TRACEPORTSPEED */
12725 /* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */
12726 
12727 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */
12728 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
12729 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
12730 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0x0UL) /*!< Trace Port clock is: 32MHz */
12731 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (0x1UL) /*!< Trace Port clock is: 16MHz */
12732 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (0x2UL) /*!< Trace Port clock is: 8MHz */
12733 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (0x3UL) /*!< Trace Port clock is: 4MHz */
12734 
12735 
12736 /* Peripheral: TIMER */
12737 /* Description: Timer/Counter 0 */
12738 
12739 /* Register: TIMER_TASKS_START */
12740 /* Description: Start Timer */
12741 
12742 /* Bit 0 : Start Timer */
12743 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
12744 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
12745 #define TIMER_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
12746 
12747 /* Register: TIMER_TASKS_STOP */
12748 /* Description: Stop Timer */
12749 
12750 /* Bit 0 : Stop Timer */
12751 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12752 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12753 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
12754 
12755 /* Register: TIMER_TASKS_COUNT */
12756 /* Description: Increment Timer (Counter mode only) */
12757 
12758 /* Bit 0 : Increment Timer (Counter mode only) */
12759 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
12760 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
12761 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (0x1UL) /*!< Trigger task */
12762 
12763 /* Register: TIMER_TASKS_CLEAR */
12764 /* Description: Clear time */
12765 
12766 /* Bit 0 : Clear time */
12767 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
12768 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
12769 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */
12770 
12771 /* Register: TIMER_TASKS_SHUTDOWN */
12772 /* Description: Deprecated register - Shut down timer */
12773 
12774 /* Bit 0 : Deprecated field -  Shut down timer */
12775 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
12776 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
12777 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (0x1UL) /*!< Trigger task */
12778 
12779 /* Register: TIMER_TASKS_CAPTURE */
12780 /* Description: Description collection: Capture Timer value to CC[n] register */
12781 
12782 /* Bit 0 : Capture Timer value to CC[n] register */
12783 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
12784 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
12785 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */
12786 
12787 /* Register: TIMER_SUBSCRIBE_START */
12788 /* Description: Subscribe configuration for task START */
12789 
12790 /* Bit 31 :   */
12791 #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
12792 #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
12793 #define TIMER_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
12794 #define TIMER_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */
12795 
12796 /* Bits 7..0 : DPPI channel that task START will subscribe to */
12797 #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12798 #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12799 
12800 /* Register: TIMER_SUBSCRIBE_STOP */
12801 /* Description: Subscribe configuration for task STOP */
12802 
12803 /* Bit 31 :   */
12804 #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
12805 #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
12806 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
12807 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */
12808 
12809 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
12810 #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12811 #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12812 
12813 /* Register: TIMER_SUBSCRIBE_COUNT */
12814 /* Description: Subscribe configuration for task COUNT */
12815 
12816 /* Bit 31 :   */
12817 #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */
12818 #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */
12819 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0x0UL) /*!< Disable subscription */
12820 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (0x1UL) /*!< Enable subscription */
12821 
12822 /* Bits 7..0 : DPPI channel that task COUNT will subscribe to */
12823 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12824 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12825 
12826 /* Register: TIMER_SUBSCRIBE_CLEAR */
12827 /* Description: Subscribe configuration for task CLEAR */
12828 
12829 /* Bit 31 :   */
12830 #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
12831 #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
12832 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */
12833 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */
12834 
12835 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
12836 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12837 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12838 
12839 /* Register: TIMER_SUBSCRIBE_SHUTDOWN */
12840 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */
12841 
12842 /* Bit 31 :   */
12843 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */
12844 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */
12845 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0x0UL) /*!< Disable subscription */
12846 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (0x1UL) /*!< Enable subscription */
12847 
12848 /* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */
12849 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12850 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12851 
12852 /* Register: TIMER_SUBSCRIBE_CAPTURE */
12853 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
12854 
12855 /* Bit 31 :   */
12856 #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
12857 #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
12858 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription */
12859 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription */
12860 
12861 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
12862 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12863 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12864 
12865 /* Register: TIMER_EVENTS_COMPARE */
12866 /* Description: Description collection: Compare event on CC[n] match */
12867 
12868 /* Bit 0 : Compare event on CC[n] match */
12869 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
12870 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
12871 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */
12872 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */
12873 
12874 /* Register: TIMER_PUBLISH_COMPARE */
12875 /* Description: Description collection: Publish configuration for event COMPARE[n] */
12876 
12877 /* Bit 31 :   */
12878 #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
12879 #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
12880 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */
12881 #define TIMER_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */
12882 
12883 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */
12884 #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12885 #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12886 
12887 /* Register: TIMER_SHORTS */
12888 /* Description: Shortcuts between local events and tasks */
12889 
12890 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
12891 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
12892 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
12893 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0x0UL) /*!< Disable shortcut */
12894 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (0x1UL) /*!< Enable shortcut */
12895 
12896 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
12897 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
12898 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
12899 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0x0UL) /*!< Disable shortcut */
12900 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (0x1UL) /*!< Enable shortcut */
12901 
12902 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
12903 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
12904 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
12905 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0x0UL) /*!< Disable shortcut */
12906 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (0x1UL) /*!< Enable shortcut */
12907 
12908 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
12909 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
12910 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
12911 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0x0UL) /*!< Disable shortcut */
12912 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (0x1UL) /*!< Enable shortcut */
12913 
12914 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
12915 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
12916 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
12917 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0x0UL) /*!< Disable shortcut */
12918 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (0x1UL) /*!< Enable shortcut */
12919 
12920 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
12921 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
12922 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
12923 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0x0UL) /*!< Disable shortcut */
12924 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (0x1UL) /*!< Enable shortcut */
12925 
12926 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
12927 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
12928 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
12929 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
12930 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
12931 
12932 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
12933 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
12934 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
12935 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
12936 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
12937 
12938 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
12939 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
12940 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
12941 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
12942 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
12943 
12944 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
12945 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
12946 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
12947 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
12948 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
12949 
12950 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
12951 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
12952 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
12953 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
12954 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
12955 
12956 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
12957 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
12958 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
12959 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
12960 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
12961 
12962 /* Register: TIMER_INTENSET */
12963 /* Description: Enable interrupt */
12964 
12965 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
12966 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
12967 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
12968 #define TIMER_INTENSET_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */
12969 #define TIMER_INTENSET_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */
12970 #define TIMER_INTENSET_COMPARE5_Set (0x1UL) /*!< Enable */
12971 
12972 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
12973 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
12974 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
12975 #define TIMER_INTENSET_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */
12976 #define TIMER_INTENSET_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */
12977 #define TIMER_INTENSET_COMPARE4_Set (0x1UL) /*!< Enable */
12978 
12979 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
12980 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
12981 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
12982 #define TIMER_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
12983 #define TIMER_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
12984 #define TIMER_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */
12985 
12986 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
12987 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
12988 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
12989 #define TIMER_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
12990 #define TIMER_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
12991 #define TIMER_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */
12992 
12993 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
12994 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
12995 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
12996 #define TIMER_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
12997 #define TIMER_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
12998 #define TIMER_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */
12999 
13000 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
13001 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13002 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13003 #define TIMER_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
13004 #define TIMER_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
13005 #define TIMER_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */
13006 
13007 /* Register: TIMER_INTENCLR */
13008 /* Description: Disable interrupt */
13009 
13010 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
13011 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
13012 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
13013 #define TIMER_INTENCLR_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */
13014 #define TIMER_INTENCLR_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */
13015 #define TIMER_INTENCLR_COMPARE5_Clear (0x1UL) /*!< Disable */
13016 
13017 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
13018 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
13019 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
13020 #define TIMER_INTENCLR_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */
13021 #define TIMER_INTENCLR_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */
13022 #define TIMER_INTENCLR_COMPARE4_Clear (0x1UL) /*!< Disable */
13023 
13024 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
13025 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
13026 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
13027 #define TIMER_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
13028 #define TIMER_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
13029 #define TIMER_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */
13030 
13031 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
13032 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
13033 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
13034 #define TIMER_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
13035 #define TIMER_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
13036 #define TIMER_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */
13037 
13038 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
13039 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
13040 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
13041 #define TIMER_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
13042 #define TIMER_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
13043 #define TIMER_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */
13044 
13045 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
13046 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13047 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13048 #define TIMER_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
13049 #define TIMER_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
13050 #define TIMER_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */
13051 
13052 /* Register: TIMER_MODE */
13053 /* Description: Timer mode selection */
13054 
13055 /* Bits 1..0 : Timer mode */
13056 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
13057 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
13058 #define TIMER_MODE_MODE_Timer (0x0UL) /*!< Select Timer mode */
13059 #define TIMER_MODE_MODE_Counter (0x1UL) /*!< Deprecated enumerator -  Select Counter mode */
13060 #define TIMER_MODE_MODE_LowPowerCounter (0x2UL) /*!< Select Low Power Counter mode */
13061 
13062 /* Register: TIMER_BITMODE */
13063 /* Description: Configure the number of bits used by the TIMER */
13064 
13065 /* Bits 1..0 : Timer bit width */
13066 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
13067 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
13068 #define TIMER_BITMODE_BITMODE_16Bit (0x0UL) /*!< 16 bit timer bit width */
13069 #define TIMER_BITMODE_BITMODE_08Bit (0x1UL) /*!< 8 bit timer bit width */
13070 #define TIMER_BITMODE_BITMODE_24Bit (0x2UL) /*!< 24 bit timer bit width */
13071 #define TIMER_BITMODE_BITMODE_32Bit (0x3UL) /*!< 32 bit timer bit width */
13072 
13073 /* Register: TIMER_PRESCALER */
13074 /* Description: Timer prescaler register */
13075 
13076 /* Bits 3..0 : Prescaler value */
13077 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
13078 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
13079 
13080 /* Register: TIMER_ONESHOTEN */
13081 /* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */
13082 
13083 /* Bit 0 : Enable one-shot operation */
13084 #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */
13085 #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */
13086 #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0x0UL) /*!< Disable one-shot operation */
13087 #define TIMER_ONESHOTEN_ONESHOTEN_Enable (0x1UL) /*!< Enable one-shot operation */
13088 
13089 /* Register: TIMER_CC */
13090 /* Description: Description collection: Capture/Compare register n */
13091 
13092 /* Bits 31..0 : Capture/Compare value */
13093 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
13094 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
13095 
13096 
13097 /* Peripheral: TPIU */
13098 /* Description: Trace Port Interface Unit */
13099 
13100 /* Register: TPIU_SUPPORTEDPORTSIZES */
13101 /* Description: Each bit location is a single port size that is supported on the device. */
13102 
13103 /* Bit 31 : Indicates whether the TPIU supports port size of 32-bit. */
13104 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Pos (31UL) /*!< Position of PORT_SIZE_32 field. */
13105 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Pos) /*!< Bit mask of PORT_SIZE_32 field. */
13106 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_NotSupported (0x0UL) /*!< Port size 32 is not supported. */
13107 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Supported (0x1UL) /*!< Port size 32 is supported. */
13108 
13109 /* Bit 30 : Indicates whether the TPIU supports port size of 31-bit. */
13110 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Pos (30UL) /*!< Position of PORT_SIZE_31 field. */
13111 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Pos) /*!< Bit mask of PORT_SIZE_31 field. */
13112 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_NotSupported (0x0UL) /*!< Port size 31 is not supported. */
13113 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Supported (0x1UL) /*!< Port size 31 is supported. */
13114 
13115 /* Bit 29 : Indicates whether the TPIU supports port size of 30-bit. */
13116 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Pos (29UL) /*!< Position of PORT_SIZE_30 field. */
13117 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Pos) /*!< Bit mask of PORT_SIZE_30 field. */
13118 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_NotSupported (0x0UL) /*!< Port size 30 is not supported. */
13119 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Supported (0x1UL) /*!< Port size 30 is supported. */
13120 
13121 /* Bit 28 : Indicates whether the TPIU supports port size of 29-bit. */
13122 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Pos (28UL) /*!< Position of PORT_SIZE_29 field. */
13123 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Pos) /*!< Bit mask of PORT_SIZE_29 field. */
13124 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_NotSupported (0x0UL) /*!< Port size 29 is not supported. */
13125 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Supported (0x1UL) /*!< Port size 29 is supported. */
13126 
13127 /* Bit 27 : Indicates whether the TPIU supports port size of 28-bit. */
13128 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Pos (27UL) /*!< Position of PORT_SIZE_28 field. */
13129 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Pos) /*!< Bit mask of PORT_SIZE_28 field. */
13130 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_NotSupported (0x0UL) /*!< Port size 28 is not supported. */
13131 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Supported (0x1UL) /*!< Port size 28 is supported. */
13132 
13133 /* Bit 26 : Indicates whether the TPIU supports port size of 27-bit. */
13134 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Pos (26UL) /*!< Position of PORT_SIZE_27 field. */
13135 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Pos) /*!< Bit mask of PORT_SIZE_27 field. */
13136 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_NotSupported (0x0UL) /*!< Port size 27 is not supported. */
13137 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Supported (0x1UL) /*!< Port size 27 is supported. */
13138 
13139 /* Bit 25 : Indicates whether the TPIU supports port size of 26-bit. */
13140 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Pos (25UL) /*!< Position of PORT_SIZE_26 field. */
13141 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Pos) /*!< Bit mask of PORT_SIZE_26 field. */
13142 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_NotSupported (0x0UL) /*!< Port size 26 is not supported. */
13143 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Supported (0x1UL) /*!< Port size 26 is supported. */
13144 
13145 /* Bit 24 : Indicates whether the TPIU supports port size of 25-bit. */
13146 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Pos (24UL) /*!< Position of PORT_SIZE_25 field. */
13147 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Pos) /*!< Bit mask of PORT_SIZE_25 field. */
13148 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_NotSupported (0x0UL) /*!< Port size 25 is not supported. */
13149 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Supported (0x1UL) /*!< Port size 25 is supported. */
13150 
13151 /* Bit 23 : Indicates whether the TPIU supports port size of 24-bit. */
13152 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Pos (23UL) /*!< Position of PORT_SIZE_24 field. */
13153 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Pos) /*!< Bit mask of PORT_SIZE_24 field. */
13154 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_NotSupported (0x0UL) /*!< Port size 24 is not supported. */
13155 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Supported (0x1UL) /*!< Port size 24 is supported. */
13156 
13157 /* Bit 22 : Indicates whether the TPIU supports port size of 23-bit. */
13158 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Pos (22UL) /*!< Position of PORT_SIZE_23 field. */
13159 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Pos) /*!< Bit mask of PORT_SIZE_23 field. */
13160 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_NotSupported (0x0UL) /*!< Port size 23 is not supported. */
13161 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Supported (0x1UL) /*!< Port size 23 is supported. */
13162 
13163 /* Bit 21 : Indicates whether the TPIU supports port size of 22-bit. */
13164 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Pos (21UL) /*!< Position of PORT_SIZE_22 field. */
13165 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Pos) /*!< Bit mask of PORT_SIZE_22 field. */
13166 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_NotSupported (0x0UL) /*!< Port size 22 is not supported. */
13167 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Supported (0x1UL) /*!< Port size 22 is supported. */
13168 
13169 /* Bit 20 : Indicates whether the TPIU supports port size of 21-bit. */
13170 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Pos (20UL) /*!< Position of PORT_SIZE_21 field. */
13171 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Pos) /*!< Bit mask of PORT_SIZE_21 field. */
13172 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_NotSupported (0x0UL) /*!< Port size 21 is not supported. */
13173 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Supported (0x1UL) /*!< Port size 21 is supported. */
13174 
13175 /* Bit 19 : Indicates whether the TPIU supports port size of 20-bit. */
13176 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Pos (19UL) /*!< Position of PORT_SIZE_20 field. */
13177 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Pos) /*!< Bit mask of PORT_SIZE_20 field. */
13178 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_NotSupported (0x0UL) /*!< Port size 20 is not supported. */
13179 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Supported (0x1UL) /*!< Port size 20 is supported. */
13180 
13181 /* Bit 18 : Indicates whether the TPIU supports port size of 19-bit. */
13182 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Pos (18UL) /*!< Position of PORT_SIZE_19 field. */
13183 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Pos) /*!< Bit mask of PORT_SIZE_19 field. */
13184 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_NotSupported (0x0UL) /*!< Port size 19 is not supported. */
13185 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Supported (0x1UL) /*!< Port size 19 is supported. */
13186 
13187 /* Bit 17 : Indicates whether the TPIU supports port size of 18-bit. */
13188 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Pos (17UL) /*!< Position of PORT_SIZE_18 field. */
13189 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Pos) /*!< Bit mask of PORT_SIZE_18 field. */
13190 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_NotSupported (0x0UL) /*!< Port size 18 is not supported. */
13191 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Supported (0x1UL) /*!< Port size 18 is supported. */
13192 
13193 /* Bit 16 : Indicates whether the TPIU supports port size of 17-bit. */
13194 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Pos (16UL) /*!< Position of PORT_SIZE_17 field. */
13195 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Pos) /*!< Bit mask of PORT_SIZE_17 field. */
13196 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_NotSupported (0x0UL) /*!< Port size 17 is not supported. */
13197 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Supported (0x1UL) /*!< Port size 17 is supported. */
13198 
13199 /* Bit 15 : Indicates whether the TPIU supports port size of 16-bit. */
13200 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Pos (15UL) /*!< Position of PORT_SIZE_16 field. */
13201 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Pos) /*!< Bit mask of PORT_SIZE_16 field. */
13202 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_NotSupported (0x0UL) /*!< Port size 16 is not supported. */
13203 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Supported (0x1UL) /*!< Port size 16 is supported. */
13204 
13205 /* Bit 14 : Indicates whether the TPIU supports port size of 15-bit. */
13206 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Pos (14UL) /*!< Position of PORT_SIZE_15 field. */
13207 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Pos) /*!< Bit mask of PORT_SIZE_15 field. */
13208 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_NotSupported (0x0UL) /*!< Port size 15 is not supported. */
13209 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Supported (0x1UL) /*!< Port size 15 is supported. */
13210 
13211 /* Bit 13 : Indicates whether the TPIU supports port size of 14-bit. */
13212 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Pos (13UL) /*!< Position of PORT_SIZE_14 field. */
13213 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Pos) /*!< Bit mask of PORT_SIZE_14 field. */
13214 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_NotSupported (0x0UL) /*!< Port size 14 is not supported. */
13215 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Supported (0x1UL) /*!< Port size 14 is supported. */
13216 
13217 /* Bit 12 : Indicates whether the TPIU supports port size of 13-bit. */
13218 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Pos (12UL) /*!< Position of PORT_SIZE_13 field. */
13219 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Pos) /*!< Bit mask of PORT_SIZE_13 field. */
13220 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_NotSupported (0x0UL) /*!< Port size 13 is not supported. */
13221 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Supported (0x1UL) /*!< Port size 13 is supported. */
13222 
13223 /* Bit 11 : Indicates whether the TPIU supports port size of 12-bit. */
13224 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Pos (11UL) /*!< Position of PORT_SIZE_12 field. */
13225 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Pos) /*!< Bit mask of PORT_SIZE_12 field. */
13226 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_NotSupported (0x0UL) /*!< Port size 12 is not supported. */
13227 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Supported (0x1UL) /*!< Port size 12 is supported. */
13228 
13229 /* Bit 10 : Indicates whether the TPIU supports port size of 11-bit. */
13230 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Pos (10UL) /*!< Position of PORT_SIZE_11 field. */
13231 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Pos) /*!< Bit mask of PORT_SIZE_11 field. */
13232 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_NotSupported (0x0UL) /*!< Port size 11 is not supported. */
13233 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Supported (0x1UL) /*!< Port size 11 is supported. */
13234 
13235 /* Bit 9 : Indicates whether the TPIU supports port size of 10-bit. */
13236 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Pos (9UL) /*!< Position of PORT_SIZE_10 field. */
13237 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Pos) /*!< Bit mask of PORT_SIZE_10 field. */
13238 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_NotSupported (0x0UL) /*!< Port size 10 is not supported. */
13239 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Supported (0x1UL) /*!< Port size 10 is supported. */
13240 
13241 /* Bit 8 : Indicates whether the TPIU supports port size of 9-bit. */
13242 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Pos (8UL) /*!< Position of PORT_SIZE_9 field. */
13243 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Pos) /*!< Bit mask of PORT_SIZE_9 field. */
13244 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_NotSupported (0x0UL) /*!< Port size 9 is not supported. */
13245 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Supported (0x1UL) /*!< Port size 9 is supported. */
13246 
13247 /* Bit 7 : Indicates whether the TPIU supports port size of 8-bit. */
13248 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Pos (7UL) /*!< Position of PORT_SIZE_8 field. */
13249 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Pos) /*!< Bit mask of PORT_SIZE_8 field. */
13250 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_NotSupported (0x0UL) /*!< Port size 8 is not supported. */
13251 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Supported (0x1UL) /*!< Port size 8 is supported. */
13252 
13253 /* Bit 6 : Indicates whether the TPIU supports port size of 7-bit. */
13254 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Pos (6UL) /*!< Position of PORT_SIZE_7 field. */
13255 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Pos) /*!< Bit mask of PORT_SIZE_7 field. */
13256 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_NotSupported (0x0UL) /*!< Port size 7 is not supported. */
13257 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Supported (0x1UL) /*!< Port size 7 is supported. */
13258 
13259 /* Bit 5 : Indicates whether the TPIU supports port size of 6-bit. */
13260 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Pos (5UL) /*!< Position of PORT_SIZE_6 field. */
13261 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Pos) /*!< Bit mask of PORT_SIZE_6 field. */
13262 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_NotSupported (0x0UL) /*!< Port size 6 is not supported. */
13263 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Supported (0x1UL) /*!< Port size 6 is supported. */
13264 
13265 /* Bit 4 : Indicates whether the TPIU supports port size of 5-bit. */
13266 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Pos (4UL) /*!< Position of PORT_SIZE_5 field. */
13267 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Pos) /*!< Bit mask of PORT_SIZE_5 field. */
13268 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_NotSupported (0x0UL) /*!< Port size 5 is not supported. */
13269 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Supported (0x1UL) /*!< Port size 5 is supported. */
13270 
13271 /* Bit 3 : Indicates whether the TPIU supports port size of 4-bit. */
13272 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Pos (3UL) /*!< Position of PORT_SIZE_4 field. */
13273 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Pos) /*!< Bit mask of PORT_SIZE_4 field. */
13274 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_NotSupported (0x0UL) /*!< Port size 4 is not supported. */
13275 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Supported (0x1UL) /*!< Port size 4 is supported. */
13276 
13277 /* Bit 2 : Indicates whether the TPIU supports port size of 3-bit. */
13278 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Pos (2UL) /*!< Position of PORT_SIZE_3 field. */
13279 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Pos) /*!< Bit mask of PORT_SIZE_3 field. */
13280 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_NotSupported (0x0UL) /*!< Port size 3 is not supported. */
13281 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Supported (0x1UL) /*!< Port size 3 is supported. */
13282 
13283 /* Bit 1 : Indicates whether the TPIU supports port size of 2-bit. */
13284 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Pos (1UL) /*!< Position of PORT_SIZE_2 field. */
13285 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Pos) /*!< Bit mask of PORT_SIZE_2 field. */
13286 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_NotSupported (0x0UL) /*!< Port size 2 is not supported. */
13287 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Supported (0x1UL) /*!< Port size 2 is supported. */
13288 
13289 /* Bit 0 : Indicates whether the TPIU supports port size of 1-bit. */
13290 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Pos (0UL) /*!< Position of PORT_SIZE_1 field. */
13291 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Pos) /*!< Bit mask of PORT_SIZE_1 field. */
13292 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_NotSupported (0x0UL) /*!< Port size 1 is not supported. */
13293 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Supported (0x1UL) /*!< Port size 1 is supported. */
13294 
13295 /* Register: TPIU_CURRENTPORTSIZE */
13296 /* Description: Each bit location is a single port size. One bit can be set, and indicates the current port size. */
13297 
13298 /* Bit 31 : Indicates which port size is currently selected. */
13299 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Pos (31UL) /*!< Position of PORT_SIZE_32 field. */
13300 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Pos) /*!< Bit mask of PORT_SIZE_32 field. */
13301 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_NotSelected (0x0UL) /*!< Port size 32 is not selected. */
13302 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Selected (0x1UL) /*!< Port size 32 is selected. */
13303 
13304 /* Bit 30 : Indicates which port size is currently selected. */
13305 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Pos (30UL) /*!< Position of PORT_SIZE_31 field. */
13306 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Pos) /*!< Bit mask of PORT_SIZE_31 field. */
13307 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_NotSelected (0x0UL) /*!< Port size 31 is not selected. */
13308 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Selected (0x1UL) /*!< Port size 31 is selected. */
13309 
13310 /* Bit 29 : Indicates which port size is currently selected. */
13311 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Pos (29UL) /*!< Position of PORT_SIZE_30 field. */
13312 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Pos) /*!< Bit mask of PORT_SIZE_30 field. */
13313 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_NotSelected (0x0UL) /*!< Port size 30 is not selected. */
13314 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Selected (0x1UL) /*!< Port size 30 is selected. */
13315 
13316 /* Bit 28 : Indicates which port size is currently selected. */
13317 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Pos (28UL) /*!< Position of PORT_SIZE_29 field. */
13318 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Pos) /*!< Bit mask of PORT_SIZE_29 field. */
13319 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_NotSelected (0x0UL) /*!< Port size 29 is not selected. */
13320 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Selected (0x1UL) /*!< Port size 29 is selected. */
13321 
13322 /* Bit 27 : Indicates which port size is currently selected. */
13323 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Pos (27UL) /*!< Position of PORT_SIZE_28 field. */
13324 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Pos) /*!< Bit mask of PORT_SIZE_28 field. */
13325 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_NotSelected (0x0UL) /*!< Port size 28 is not selected. */
13326 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Selected (0x1UL) /*!< Port size 28 is selected. */
13327 
13328 /* Bit 26 : Indicates which port size is currently selected. */
13329 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Pos (26UL) /*!< Position of PORT_SIZE_27 field. */
13330 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Pos) /*!< Bit mask of PORT_SIZE_27 field. */
13331 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_NotSelected (0x0UL) /*!< Port size 27 is not selected. */
13332 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Selected (0x1UL) /*!< Port size 27 is selected. */
13333 
13334 /* Bit 25 : Indicates which port size is currently selected. */
13335 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Pos (25UL) /*!< Position of PORT_SIZE_26 field. */
13336 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Pos) /*!< Bit mask of PORT_SIZE_26 field. */
13337 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_NotSelected (0x0UL) /*!< Port size 26 is not selected. */
13338 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Selected (0x1UL) /*!< Port size 26 is selected. */
13339 
13340 /* Bit 24 : Indicates which port size is currently selected. */
13341 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Pos (24UL) /*!< Position of PORT_SIZE_25 field. */
13342 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Pos) /*!< Bit mask of PORT_SIZE_25 field. */
13343 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_NotSelected (0x0UL) /*!< Port size 25 is not selected. */
13344 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Selected (0x1UL) /*!< Port size 25 is selected. */
13345 
13346 /* Bit 23 : Indicates which port size is currently selected. */
13347 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Pos (23UL) /*!< Position of PORT_SIZE_24 field. */
13348 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Pos) /*!< Bit mask of PORT_SIZE_24 field. */
13349 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_NotSelected (0x0UL) /*!< Port size 24 is not selected. */
13350 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Selected (0x1UL) /*!< Port size 24 is selected. */
13351 
13352 /* Bit 22 : Indicates which port size is currently selected. */
13353 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Pos (22UL) /*!< Position of PORT_SIZE_23 field. */
13354 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Pos) /*!< Bit mask of PORT_SIZE_23 field. */
13355 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_NotSelected (0x0UL) /*!< Port size 23 is not selected. */
13356 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Selected (0x1UL) /*!< Port size 23 is selected. */
13357 
13358 /* Bit 21 : Indicates which port size is currently selected. */
13359 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Pos (21UL) /*!< Position of PORT_SIZE_22 field. */
13360 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Pos) /*!< Bit mask of PORT_SIZE_22 field. */
13361 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_NotSelected (0x0UL) /*!< Port size 22 is not selected. */
13362 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Selected (0x1UL) /*!< Port size 22 is selected. */
13363 
13364 /* Bit 20 : Indicates which port size is currently selected. */
13365 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Pos (20UL) /*!< Position of PORT_SIZE_21 field. */
13366 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Pos) /*!< Bit mask of PORT_SIZE_21 field. */
13367 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_NotSelected (0x0UL) /*!< Port size 21 is not selected. */
13368 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Selected (0x1UL) /*!< Port size 21 is selected. */
13369 
13370 /* Bit 19 : Indicates which port size is currently selected. */
13371 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Pos (19UL) /*!< Position of PORT_SIZE_20 field. */
13372 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Pos) /*!< Bit mask of PORT_SIZE_20 field. */
13373 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_NotSelected (0x0UL) /*!< Port size 20 is not selected. */
13374 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Selected (0x1UL) /*!< Port size 20 is selected. */
13375 
13376 /* Bit 18 : Indicates which port size is currently selected. */
13377 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Pos (18UL) /*!< Position of PORT_SIZE_19 field. */
13378 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Pos) /*!< Bit mask of PORT_SIZE_19 field. */
13379 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_NotSelected (0x0UL) /*!< Port size 19 is not selected. */
13380 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Selected (0x1UL) /*!< Port size 19 is selected. */
13381 
13382 /* Bit 17 : Indicates which port size is currently selected. */
13383 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Pos (17UL) /*!< Position of PORT_SIZE_18 field. */
13384 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Pos) /*!< Bit mask of PORT_SIZE_18 field. */
13385 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_NotSelected (0x0UL) /*!< Port size 18 is not selected. */
13386 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Selected (0x1UL) /*!< Port size 18 is selected. */
13387 
13388 /* Bit 16 : Indicates which port size is currently selected. */
13389 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Pos (16UL) /*!< Position of PORT_SIZE_17 field. */
13390 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Pos) /*!< Bit mask of PORT_SIZE_17 field. */
13391 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_NotSelected (0x0UL) /*!< Port size 17 is not selected. */
13392 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Selected (0x1UL) /*!< Port size 17 is selected. */
13393 
13394 /* Bit 15 : Indicates which port size is currently selected. */
13395 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Pos (15UL) /*!< Position of PORT_SIZE_16 field. */
13396 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Pos) /*!< Bit mask of PORT_SIZE_16 field. */
13397 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_NotSelected (0x0UL) /*!< Port size 16 is not selected. */
13398 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Selected (0x1UL) /*!< Port size 16 is selected. */
13399 
13400 /* Bit 14 : Indicates which port size is currently selected. */
13401 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Pos (14UL) /*!< Position of PORT_SIZE_15 field. */
13402 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Pos) /*!< Bit mask of PORT_SIZE_15 field. */
13403 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_NotSelected (0x0UL) /*!< Port size 15 is not selected. */
13404 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Selected (0x1UL) /*!< Port size 15 is selected. */
13405 
13406 /* Bit 13 : Indicates which port size is currently selected. */
13407 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Pos (13UL) /*!< Position of PORT_SIZE_14 field. */
13408 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Pos) /*!< Bit mask of PORT_SIZE_14 field. */
13409 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_NotSelected (0x0UL) /*!< Port size 14 is not selected. */
13410 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Selected (0x1UL) /*!< Port size 14 is selected. */
13411 
13412 /* Bit 12 : Indicates which port size is currently selected. */
13413 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Pos (12UL) /*!< Position of PORT_SIZE_13 field. */
13414 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Pos) /*!< Bit mask of PORT_SIZE_13 field. */
13415 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_NotSelected (0x0UL) /*!< Port size 13 is not selected. */
13416 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Selected (0x1UL) /*!< Port size 13 is selected. */
13417 
13418 /* Bit 11 : Indicates which port size is currently selected. */
13419 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Pos (11UL) /*!< Position of PORT_SIZE_12 field. */
13420 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Pos) /*!< Bit mask of PORT_SIZE_12 field. */
13421 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_NotSelected (0x0UL) /*!< Port size 12 is not selected. */
13422 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Selected (0x1UL) /*!< Port size 12 is selected. */
13423 
13424 /* Bit 10 : Indicates which port size is currently selected. */
13425 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Pos (10UL) /*!< Position of PORT_SIZE_11 field. */
13426 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Pos) /*!< Bit mask of PORT_SIZE_11 field. */
13427 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_NotSelected (0x0UL) /*!< Port size 11 is not selected. */
13428 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Selected (0x1UL) /*!< Port size 11 is selected. */
13429 
13430 /* Bit 9 : Indicates which port size is currently selected. */
13431 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Pos (9UL) /*!< Position of PORT_SIZE_10 field. */
13432 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Pos) /*!< Bit mask of PORT_SIZE_10 field. */
13433 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_NotSelected (0x0UL) /*!< Port size 10 is not selected. */
13434 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Selected (0x1UL) /*!< Port size 10 is selected. */
13435 
13436 /* Bit 8 : Indicates which port size is currently selected. */
13437 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Pos (8UL) /*!< Position of PORT_SIZE_9 field. */
13438 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Pos) /*!< Bit mask of PORT_SIZE_9 field. */
13439 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_NotSelected (0x0UL) /*!< Port size 9 is not selected. */
13440 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Selected (0x1UL) /*!< Port size 9 is selected. */
13441 
13442 /* Bit 7 : Indicates which port size is currently selected. */
13443 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Pos (7UL) /*!< Position of PORT_SIZE_8 field. */
13444 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Pos) /*!< Bit mask of PORT_SIZE_8 field. */
13445 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_NotSelected (0x0UL) /*!< Port size 8 is not selected. */
13446 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Selected (0x1UL) /*!< Port size 8 is selected. */
13447 
13448 /* Bit 6 : Indicates which port size is currently selected. */
13449 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Pos (6UL) /*!< Position of PORT_SIZE_7 field. */
13450 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Pos) /*!< Bit mask of PORT_SIZE_7 field. */
13451 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_NotSelected (0x0UL) /*!< Port size 7 is not selected. */
13452 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Selected (0x1UL) /*!< Port size 7 is selected. */
13453 
13454 /* Bit 5 : Indicates which port size is currently selected. */
13455 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Pos (5UL) /*!< Position of PORT_SIZE_6 field. */
13456 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Pos) /*!< Bit mask of PORT_SIZE_6 field. */
13457 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_NotSelected (0x0UL) /*!< Port size 6 is not selected. */
13458 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Selected (0x1UL) /*!< Port size 6 is selected. */
13459 
13460 /* Bit 4 : Indicates which port size is currently selected. */
13461 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Pos (4UL) /*!< Position of PORT_SIZE_5 field. */
13462 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Pos) /*!< Bit mask of PORT_SIZE_5 field. */
13463 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_NotSelected (0x0UL) /*!< Port size 5 is not selected. */
13464 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Selected (0x1UL) /*!< Port size 5 is selected. */
13465 
13466 /* Bit 3 : Indicates which port size is currently selected. */
13467 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Pos (3UL) /*!< Position of PORT_SIZE_4 field. */
13468 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Pos) /*!< Bit mask of PORT_SIZE_4 field. */
13469 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_NotSelected (0x0UL) /*!< Port size 4 is not selected. */
13470 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Selected (0x1UL) /*!< Port size 4 is selected. */
13471 
13472 /* Bit 2 : Indicates which port size is currently selected. */
13473 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Pos (2UL) /*!< Position of PORT_SIZE_3 field. */
13474 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Pos) /*!< Bit mask of PORT_SIZE_3 field. */
13475 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_NotSelected (0x0UL) /*!< Port size 3 is not selected. */
13476 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Selected (0x1UL) /*!< Port size 3 is selected. */
13477 
13478 /* Bit 1 : Indicates which port size is currently selected. */
13479 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Pos (1UL) /*!< Position of PORT_SIZE_2 field. */
13480 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Pos) /*!< Bit mask of PORT_SIZE_2 field. */
13481 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_NotSelected (0x0UL) /*!< Port size 2 is not selected. */
13482 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Selected (0x1UL) /*!< Port size 2 is selected. */
13483 
13484 /* Bit 0 : Indicates which port size is currently selected. */
13485 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Pos (0UL) /*!< Position of PORT_SIZE_1 field. */
13486 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Pos) /*!< Bit mask of PORT_SIZE_1 field. */
13487 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_NotSelected (0x0UL) /*!< Port size 1 is not selected. */
13488 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Selected (0x1UL) /*!< Port size 1 is selected. */
13489 
13490 /* Register: TPIU_SUPPORTEDTRIGGERMODES */
13491 /* Description: The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system. */
13492 
13493 /* Bit 17 : A trigger has occurred but the counter is not at 0. */
13494 #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Pos (17UL) /*!< Position of TRGRUN field. */
13495 #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Pos) /*!< Bit mask of TRGRUN field. */
13496 #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_NotOccured (0x0UL) /*!< Either a trigger has not occurred or the counter is at 0. */
13497 #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Occured (0x1UL) /*!< A trigger has occurred but the counter is not at 0. */
13498 
13499 /* Bit 16 : A trigger has occurred and the counter has reached 0. */
13500 #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Pos (16UL) /*!< Position of TRIGGERED field. */
13501 #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Pos) /*!< Bit mask of TRIGGERED field. */
13502 #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_NotOccured (0x0UL) /*!< Trigger has not occurred. */
13503 #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Occured (0x1UL) /*!< Trigger has occurred. */
13504 
13505 /* Bit 8 : Indicates whether an 8-bit wide counter register is implemented. */
13506 #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Pos (8UL) /*!< Position of TCOUNT8 field. */
13507 #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Pos) /*!< Bit mask of TCOUNT8 field. */
13508 #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_NotImplemented (0x0UL) /*!< An 8-bit wide counter register is implemented. */
13509 #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Implemented (0x1UL) /*!< An 8-bit wide counter register is implemented. */
13510 
13511 /* Bit 4 : Indicates whether multiplying the trigger counter by 2^(4+1) is supported. */
13512 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_4_Pos (4UL) /*!< Position of MULT_4 field. */
13513 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_4_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT_4_Pos) /*!< Bit mask of MULT_4 field. */
13514 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_4_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(4+1) is supported. */
13515 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_4_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(4+1) is supported. */
13516 
13517 /* Bit 3 : Indicates whether multiplying the trigger counter by 2^(3+1) is supported. */
13518 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_3_Pos (3UL) /*!< Position of MULT_3 field. */
13519 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_3_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT_3_Pos) /*!< Bit mask of MULT_3 field. */
13520 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_3_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(3+1) is supported. */
13521 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_3_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(3+1) is supported. */
13522 
13523 /* Bit 2 : Indicates whether multiplying the trigger counter by 2^(2+1) is supported. */
13524 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_2_Pos (2UL) /*!< Position of MULT_2 field. */
13525 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_2_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT_2_Pos) /*!< Bit mask of MULT_2 field. */
13526 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_2_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(2+1) is supported. */
13527 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_2_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(2+1) is supported. */
13528 
13529 /* Bit 1 : Indicates whether multiplying the trigger counter by 2^(1+1) is supported. */
13530 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_1_Pos (1UL) /*!< Position of MULT_1 field. */
13531 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_1_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT_1_Pos) /*!< Bit mask of MULT_1 field. */
13532 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_1_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(1+1) is supported. */
13533 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_1_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(1+1) is supported. */
13534 
13535 /* Bit 0 : Indicates whether multiplying the trigger counter by 2^(0+1) is supported. */
13536 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_0_Pos (0UL) /*!< Position of MULT_0 field. */
13537 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_0_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT_0_Pos) /*!< Bit mask of MULT_0 field. */
13538 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_0_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(0+1) is supported. */
13539 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_0_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(0+1) is supported. */
13540 
13541 /* Register: TPIU_TRIGGERCOUNTERVALUE */
13542 /* Description: The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices. */
13543 
13544 /* Bits 7..0 : 8-bit counter value for the number of words to be output from the formatter before a trigger is inserted. */
13545 #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Pos (0UL) /*!< Position of TrigCount field. */
13546 #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Msk (0xFFUL << TPIU_TRIGGERCOUNTERVALUE_TrigCount_Pos) /*!< Bit mask of TrigCount field. */
13547 
13548 /* Register: TPIU_TRIGGERMULTIPLIER */
13549 /* Description: The Trigger_multiplier register contains the selectors for the trigger counter multiplier. */
13550 
13551 /* Bit 4 : Multiply the Trigger Counter by 2^n. */
13552 #define TPIU_TRIGGERMULTIPLIER_MULT_4_Pos (4UL) /*!< Position of MULT_4 field. */
13553 #define TPIU_TRIGGERMULTIPLIER_MULT_4_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT_4_Pos) /*!< Bit mask of MULT_4 field. */
13554 #define TPIU_TRIGGERMULTIPLIER_MULT_4_Disabled (0x0UL) /*!< Multiplier disabled. */
13555 #define TPIU_TRIGGERMULTIPLIER_MULT_4_Enabled (0x1UL) /*!< Multiplier enabled. */
13556 
13557 /* Bit 3 : Multiply the Trigger Counter by 2^n. */
13558 #define TPIU_TRIGGERMULTIPLIER_MULT_3_Pos (3UL) /*!< Position of MULT_3 field. */
13559 #define TPIU_TRIGGERMULTIPLIER_MULT_3_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT_3_Pos) /*!< Bit mask of MULT_3 field. */
13560 #define TPIU_TRIGGERMULTIPLIER_MULT_3_Disabled (0x0UL) /*!< Multiplier disabled. */
13561 #define TPIU_TRIGGERMULTIPLIER_MULT_3_Enabled (0x1UL) /*!< Multiplier enabled. */
13562 
13563 /* Bit 2 : Multiply the Trigger Counter by 2^n. */
13564 #define TPIU_TRIGGERMULTIPLIER_MULT_2_Pos (2UL) /*!< Position of MULT_2 field. */
13565 #define TPIU_TRIGGERMULTIPLIER_MULT_2_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT_2_Pos) /*!< Bit mask of MULT_2 field. */
13566 #define TPIU_TRIGGERMULTIPLIER_MULT_2_Disabled (0x0UL) /*!< Multiplier disabled. */
13567 #define TPIU_TRIGGERMULTIPLIER_MULT_2_Enabled (0x1UL) /*!< Multiplier enabled. */
13568 
13569 /* Bit 1 : Multiply the Trigger Counter by 2^n. */
13570 #define TPIU_TRIGGERMULTIPLIER_MULT_1_Pos (1UL) /*!< Position of MULT_1 field. */
13571 #define TPIU_TRIGGERMULTIPLIER_MULT_1_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT_1_Pos) /*!< Bit mask of MULT_1 field. */
13572 #define TPIU_TRIGGERMULTIPLIER_MULT_1_Disabled (0x0UL) /*!< Multiplier disabled. */
13573 #define TPIU_TRIGGERMULTIPLIER_MULT_1_Enabled (0x1UL) /*!< Multiplier enabled. */
13574 
13575 /* Bit 0 : Multiply the Trigger Counter by 2^n. */
13576 #define TPIU_TRIGGERMULTIPLIER_MULT_0_Pos (0UL) /*!< Position of MULT_0 field. */
13577 #define TPIU_TRIGGERMULTIPLIER_MULT_0_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT_0_Pos) /*!< Bit mask of MULT_0 field. */
13578 #define TPIU_TRIGGERMULTIPLIER_MULT_0_Disabled (0x0UL) /*!< Multiplier disabled. */
13579 #define TPIU_TRIGGERMULTIPLIER_MULT_0_Enabled (0x1UL) /*!< Multiplier enabled. */
13580 
13581 /* Register: TPIU_SUPPPORTEDTESTPATTERNMODES */
13582 /* Description: The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device. */
13583 
13584 /* Bit 17 : Indicates whether continuous mode is supported. */
13585 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Pos (17UL) /*!< Position of PCONTEN field. */
13586 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Pos) /*!< Bit mask of PCONTEN field. */
13587 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_NotSupported (0x0UL) /*!< Mode is not supported. */
13588 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Supported (0x1UL) /*!< Mode is supported. */
13589 
13590 /* Bit 16 : Indicates whether timed mode is supported. */
13591 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Pos (16UL) /*!< Position of PTIMEEN field. */
13592 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Pos) /*!< Bit mask of PTIMEEN field. */
13593 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_NotSupported (0x0UL) /*!< Mode is not supported. */
13594 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Supported (0x1UL) /*!< Mode is supported. */
13595 
13596 /* Bit 3 : Indicates whether the FF/00 pattern is supported as output over the trace port. */
13597 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Pos (3UL) /*!< Position of PATF0 field. */
13598 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Pos) /*!< Bit mask of PATF0 field. */
13599 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_NotSupported (0x0UL) /*!< Test pattern is not supported. */
13600 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Supported (0x1UL) /*!< Test pattern is supported. */
13601 
13602 /* Bit 2 : Indicates whether the AA/55 pattern is supported as output over the trace port. */
13603 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Pos (2UL) /*!< Position of PATA5 field. */
13604 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Pos) /*!< Bit mask of PATA5 field. */
13605 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_NotSupported (0x0UL) /*!< Test pattern is not supported. */
13606 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Supported (0x1UL) /*!< Test pattern is supported. */
13607 
13608 /* Bit 1 : Indicates whether the walking 0s pattern is supported as output over the trace port. */
13609 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Pos (1UL) /*!< Position of PATW0 field. */
13610 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Pos) /*!< Bit mask of PATW0 field. */
13611 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_NotSupported (0x0UL) /*!< Test pattern is not supported. */
13612 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Supported (0x1UL) /*!< Test pattern is supported. */
13613 
13614 /* Bit 0 : Indicates whether the walking 1s pattern is supported as output over the trace port. */
13615 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Pos (0UL) /*!< Position of PATW1 field. */
13616 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Pos) /*!< Bit mask of PATW1 field. */
13617 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_NotSupported (0x0UL) /*!< Test pattern is not supported. */
13618 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Supported (0x1UL) /*!< Test pattern is supported. */
13619 
13620 /* Register: TPIU_CURRENTTESTPATTERNMODES */
13621 /* Description: Current_test_pattern_mode indicates the current test pattern or mode selected. */
13622 
13623 /* Bit 17 : Indicates whether continuous mode is supported. */
13624 #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Pos (17UL) /*!< Position of PCONTEN field. */
13625 #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Pos) /*!< Bit mask of PCONTEN field. */
13626 #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Disabled (0x0UL) /*!< Mode is disabled. */
13627 #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Enabled (0x1UL) /*!< Mode is enabled. */
13628 
13629 /* Bit 16 : Indicates whether timed mode is supported. */
13630 #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Pos (16UL) /*!< Position of PTIMEEN field. */
13631 #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Pos) /*!< Bit mask of PTIMEEN field. */
13632 #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Disabled (0x0UL) /*!< Mode is disabled. */
13633 #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Enabled (0x1UL) /*!< Mode is enabled. */
13634 
13635 /* Bit 3 : Indicates whether the FF/00 pattern is supported as output over the trace port. */
13636 #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Pos (3UL) /*!< Position of PATF0 field. */
13637 #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATF0_Pos) /*!< Bit mask of PATF0 field. */
13638 #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Disabled (0x0UL) /*!< Test pattern is disabled. */
13639 #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Enabled (0x1UL) /*!< Test pattern is enabled. */
13640 
13641 /* Bit 2 : Indicates whether the AA/55 pattern is supported as output over the trace port. */
13642 #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Pos (2UL) /*!< Position of PATA5 field. */
13643 #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATA5_Pos) /*!< Bit mask of PATA5 field. */
13644 #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Disabled (0x0UL) /*!< Test pattern is disabled. */
13645 #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Enabled (0x1UL) /*!< Test pattern is enabled. */
13646 
13647 /* Bit 1 : Indicates whether the walking 0s pattern is supported as output over the trace port. */
13648 #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Pos (1UL) /*!< Position of PATW0 field. */
13649 #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATW0_Pos) /*!< Bit mask of PATW0 field. */
13650 #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Disabled (0x0UL) /*!< Test pattern is disabled. */
13651 #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Enabled (0x1UL) /*!< Test pattern is enabled. */
13652 
13653 /* Bit 0 : Indicates whether the walking 1s pattern is supported as output over the trace port. */
13654 #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Pos (0UL) /*!< Position of PATW1 field. */
13655 #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATW1_Pos) /*!< Bit mask of PATW1 field. */
13656 #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Disabled (0x0UL) /*!< Test pattern is disabled. */
13657 #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Enabled (0x1UL) /*!< Test pattern is enabled. */
13658 
13659 /* Register: TPIU_TPRCR */
13660 /* Description: The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value. */
13661 
13662 /* Bits 7..0 : 8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it switches to the next pattern. */
13663 #define TPIU_TPRCR_PATTCOUNT_Pos (0UL) /*!< Position of PATTCOUNT field. */
13664 #define TPIU_TPRCR_PATTCOUNT_Msk (0xFFUL << TPIU_TPRCR_PATTCOUNT_Pos) /*!< Bit mask of PATTCOUNT field. */
13665 
13666 /* Register: TPIU_FFSR */
13667 /* Description: The FFSR register indicates the current status of the formatter and flush features available in the TPIU. */
13668 
13669 /* Bit 2 : Indicates whether the TRACECTL pin is available for use. */
13670 #define TPIU_FFSR_TCPRESENT_Pos (2UL) /*!< Position of TCPRESENT field. */
13671 #define TPIU_FFSR_TCPRESENT_Msk (0x1UL << TPIU_FFSR_TCPRESENT_Pos) /*!< Bit mask of TCPRESENT field. */
13672 #define TPIU_FFSR_TCPRESENT_NotPresent (0x0UL) /*!< TRACECTL pin is not present. */
13673 #define TPIU_FFSR_TCPRESENT_Present (0x1UL) /*!< TRACECTL pin is present. */
13674 
13675 /* Bit 1 : The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes HIGH. */
13676 #define TPIU_FFSR_FTSTOPPED_Pos (1UL) /*!< Position of FTSTOPPED field. */
13677 #define TPIU_FFSR_FTSTOPPED_Msk (0x1UL << TPIU_FFSR_FTSTOPPED_Pos) /*!< Bit mask of FTSTOPPED field. */
13678 #define TPIU_FFSR_FTSTOPPED_Running (0x0UL) /*!< Formatter has not stopped. */
13679 #define TPIU_FFSR_FTSTOPPED_Stopped (0x1UL) /*!< Formatter has stopped. */
13680 
13681 /* Bit 0 : Flush in progress. */
13682 #define TPIU_FFSR_FLINPROG_Pos (0UL) /*!< Position of FLINPROG field. */
13683 #define TPIU_FFSR_FLINPROG_Msk (0x1UL << TPIU_FFSR_FLINPROG_Pos) /*!< Bit mask of FLINPROG field. */
13684 #define TPIU_FFSR_FLINPROG_NotInProgress (0x0UL) /*!< A flush is not in progress. */
13685 #define TPIU_FFSR_FLINPROG_InProgress (0x1UL) /*!< A flush is in progress. */
13686 
13687 /* Register: TPIU_FFCR */
13688 /* Description: The FFCR register controls the generation of stop, trigger, and flush events. */
13689 
13690 /* Bit 13 : Stops the formatter after a trigger event is observed. Reset to disabled or 0. */
13691 #define TPIU_FFCR_STOPTRIG_Pos (13UL) /*!< Position of STOPTRIG field. */
13692 #define TPIU_FFCR_STOPTRIG_Msk (0x1UL << TPIU_FFCR_STOPTRIG_Pos) /*!< Bit mask of STOPTRIG field. */
13693 #define TPIU_FFCR_STOPTRIG_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13694 #define TPIU_FFCR_STOPTRIG_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13695 
13696 /* Bit 12 : Forces the FIFO to drain off any part-completed packets. */
13697 #define TPIU_FFCR_STOPFL_Pos (12UL) /*!< Position of STOPFL field. */
13698 #define TPIU_FFCR_STOPFL_Msk (0x1UL << TPIU_FFCR_STOPFL_Pos) /*!< Bit mask of STOPFL field. */
13699 #define TPIU_FFCR_STOPFL_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13700 #define TPIU_FFCR_STOPFL_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13701 
13702 /* Bit 10 : Indicates a trigger when flush completion on afreadys is returned. */
13703 #define TPIU_FFCR_TRIGFL_Pos (10UL) /*!< Position of TRIGFL field. */
13704 #define TPIU_FFCR_TRIGFL_Msk (0x1UL << TPIU_FFCR_TRIGFL_Pos) /*!< Bit mask of TRIGFL field. */
13705 #define TPIU_FFCR_TRIGFL_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13706 #define TPIU_FFCR_TRIGFL_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13707 
13708 /* Bit 9 : Indicates a trigger on a trigger event. */
13709 #define TPIU_FFCR_TRIGEVT_Pos (9UL) /*!< Position of TRIGEVT field. */
13710 #define TPIU_FFCR_TRIGEVT_Msk (0x1UL << TPIU_FFCR_TRIGEVT_Pos) /*!< Bit mask of TRIGEVT field. */
13711 #define TPIU_FFCR_TRIGEVT_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13712 #define TPIU_FFCR_TRIGEVT_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13713 
13714 /* Bit 8 : Indicates a trigger when trigin is asserted. */
13715 #define TPIU_FFCR_TRIGIN_Pos (8UL) /*!< Position of TRIGIN field. */
13716 #define TPIU_FFCR_TRIGIN_Msk (0x1UL << TPIU_FFCR_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */
13717 #define TPIU_FFCR_TRIGIN_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13718 #define TPIU_FFCR_TRIGIN_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13719 
13720 /* Bit 7 : Generates a flush. This bit is set to 1 when this flush is serviced. */
13721 #define TPIU_FFCR_FONMANW_Pos (7UL) /*!< Position of FONMANW field. */
13722 #define TPIU_FFCR_FONMANW_Msk (0x1UL << TPIU_FFCR_FONMANW_Pos) /*!< Bit mask of FONMANW field. */
13723 #define TPIU_FFCR_FONMANW_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13724 #define TPIU_FFCR_FONMANW_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13725 
13726 /* Bit 6 : Generates a flush. This bit is set to 0 when this flush is serviced. */
13727 #define TPIU_FFCR_FONMANR_Pos (6UL) /*!< Position of FONMANR field. */
13728 #define TPIU_FFCR_FONMANR_Msk (0x1UL << TPIU_FFCR_FONMANR_Pos) /*!< Bit mask of FONMANR field. */
13729 #define TPIU_FFCR_FONMANR_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13730 #define TPIU_FFCR_FONMANR_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13731 
13732 /* Bit 5 : Initiates a manual flush of data in the system when a trigger event occurs. */
13733 #define TPIU_FFCR_FONTRIG_Pos (5UL) /*!< Position of FONTRIG field. */
13734 #define TPIU_FFCR_FONTRIG_Msk (0x1UL << TPIU_FFCR_FONTRIG_Pos) /*!< Bit mask of FONTRIG field. */
13735 #define TPIU_FFCR_FONTRIG_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13736 #define TPIU_FFCR_FONTRIG_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13737 
13738 /* Bit 4 : Enables the use of the flushin connection. */
13739 #define TPIU_FFCR_FONFLIN_Pos (4UL) /*!< Position of FONFLIN field. */
13740 #define TPIU_FFCR_FONFLIN_Msk (0x1UL << TPIU_FFCR_FONFLIN_Pos) /*!< Bit mask of FONFLIN field. */
13741 #define TPIU_FFCR_FONFLIN_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13742 #define TPIU_FFCR_FONFLIN_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13743 
13744 /* Bit 1 : Is embedded in trigger packets and indicates that no cycle is using sync packets. */
13745 #define TPIU_FFCR_ENFCONT_Pos (1UL) /*!< Position of ENFCONT field. */
13746 #define TPIU_FFCR_ENFCONT_Msk (0x1UL << TPIU_FFCR_ENFCONT_Pos) /*!< Bit mask of ENFCONT field. */
13747 #define TPIU_FFCR_ENFCONT_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13748 #define TPIU_FFCR_ENFCONT_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13749 
13750 /* Bit 0 : Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, where present. */
13751 #define TPIU_FFCR_ENFTC_Pos (0UL) /*!< Position of ENFTC field. */
13752 #define TPIU_FFCR_ENFTC_Msk (0x1UL << TPIU_FFCR_ENFTC_Pos) /*!< Bit mask of ENFTC field. */
13753 #define TPIU_FFCR_ENFTC_Disabled (0x0UL) /*!< The formatting feature is disabled. */
13754 #define TPIU_FFCR_ENFTC_Enabled (0x1UL) /*!< The formatting feature is enabled. */
13755 
13756 /* Register: TPIU_FSCR */
13757 /* Description: The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size. */
13758 
13759 /* Bits 11..0 : 12-bit counter reload value. Indicates the number of complete frames between full synchronization packets. */
13760 #define TPIU_FSCR_CYCCOUNT_Pos (0UL) /*!< Position of CYCCOUNT field. */
13761 #define TPIU_FSCR_CYCCOUNT_Msk (0xFFFUL << TPIU_FSCR_CYCCOUNT_Pos) /*!< Bit mask of CYCCOUNT field. */
13762 
13763 /* Register: TPIU_EXTCTLINPORT */
13764 /* Description: Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution. */
13765 
13766 /* Bit 7 : EXTCTL inputs. */
13767 #define TPIU_EXTCTLINPORT_EXTCTLIN_7_Pos (7UL) /*!< Position of EXTCTLIN_7 field. */
13768 #define TPIU_EXTCTLINPORT_EXTCTLIN_7_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_7_Pos) /*!< Bit mask of EXTCTLIN_7 field. */
13769 #define TPIU_EXTCTLINPORT_EXTCTLIN_7_Low (0x0UL) /*!< Input EXTCTL7 is low. */
13770 #define TPIU_EXTCTLINPORT_EXTCTLIN_7_High (0x1UL) /*!< Input EXTCTL7 is high. */
13771 
13772 /* Bit 6 : EXTCTL inputs. */
13773 #define TPIU_EXTCTLINPORT_EXTCTLIN_6_Pos (6UL) /*!< Position of EXTCTLIN_6 field. */
13774 #define TPIU_EXTCTLINPORT_EXTCTLIN_6_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_6_Pos) /*!< Bit mask of EXTCTLIN_6 field. */
13775 #define TPIU_EXTCTLINPORT_EXTCTLIN_6_Low (0x0UL) /*!< Input EXTCTL6 is low. */
13776 #define TPIU_EXTCTLINPORT_EXTCTLIN_6_High (0x1UL) /*!< Input EXTCTL6 is high. */
13777 
13778 /* Bit 5 : EXTCTL inputs. */
13779 #define TPIU_EXTCTLINPORT_EXTCTLIN_5_Pos (5UL) /*!< Position of EXTCTLIN_5 field. */
13780 #define TPIU_EXTCTLINPORT_EXTCTLIN_5_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_5_Pos) /*!< Bit mask of EXTCTLIN_5 field. */
13781 #define TPIU_EXTCTLINPORT_EXTCTLIN_5_Low (0x0UL) /*!< Input EXTCTL5 is low. */
13782 #define TPIU_EXTCTLINPORT_EXTCTLIN_5_High (0x1UL) /*!< Input EXTCTL5 is high. */
13783 
13784 /* Bit 4 : EXTCTL inputs. */
13785 #define TPIU_EXTCTLINPORT_EXTCTLIN_4_Pos (4UL) /*!< Position of EXTCTLIN_4 field. */
13786 #define TPIU_EXTCTLINPORT_EXTCTLIN_4_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_4_Pos) /*!< Bit mask of EXTCTLIN_4 field. */
13787 #define TPIU_EXTCTLINPORT_EXTCTLIN_4_Low (0x0UL) /*!< Input EXTCTL4 is low. */
13788 #define TPIU_EXTCTLINPORT_EXTCTLIN_4_High (0x1UL) /*!< Input EXTCTL4 is high. */
13789 
13790 /* Bit 3 : EXTCTL inputs. */
13791 #define TPIU_EXTCTLINPORT_EXTCTLIN_3_Pos (3UL) /*!< Position of EXTCTLIN_3 field. */
13792 #define TPIU_EXTCTLINPORT_EXTCTLIN_3_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_3_Pos) /*!< Bit mask of EXTCTLIN_3 field. */
13793 #define TPIU_EXTCTLINPORT_EXTCTLIN_3_Low (0x0UL) /*!< Input EXTCTL3 is low. */
13794 #define TPIU_EXTCTLINPORT_EXTCTLIN_3_High (0x1UL) /*!< Input EXTCTL3 is high. */
13795 
13796 /* Bit 2 : EXTCTL inputs. */
13797 #define TPIU_EXTCTLINPORT_EXTCTLIN_2_Pos (2UL) /*!< Position of EXTCTLIN_2 field. */
13798 #define TPIU_EXTCTLINPORT_EXTCTLIN_2_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_2_Pos) /*!< Bit mask of EXTCTLIN_2 field. */
13799 #define TPIU_EXTCTLINPORT_EXTCTLIN_2_Low (0x0UL) /*!< Input EXTCTL2 is low. */
13800 #define TPIU_EXTCTLINPORT_EXTCTLIN_2_High (0x1UL) /*!< Input EXTCTL2 is high. */
13801 
13802 /* Bit 1 : EXTCTL inputs. */
13803 #define TPIU_EXTCTLINPORT_EXTCTLIN_1_Pos (1UL) /*!< Position of EXTCTLIN_1 field. */
13804 #define TPIU_EXTCTLINPORT_EXTCTLIN_1_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_1_Pos) /*!< Bit mask of EXTCTLIN_1 field. */
13805 #define TPIU_EXTCTLINPORT_EXTCTLIN_1_Low (0x0UL) /*!< Input EXTCTL1 is low. */
13806 #define TPIU_EXTCTLINPORT_EXTCTLIN_1_High (0x1UL) /*!< Input EXTCTL1 is high. */
13807 
13808 /* Bit 0 : EXTCTL inputs. */
13809 #define TPIU_EXTCTLINPORT_EXTCTLIN_0_Pos (0UL) /*!< Position of EXTCTLIN_0 field. */
13810 #define TPIU_EXTCTLINPORT_EXTCTLIN_0_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_0_Pos) /*!< Bit mask of EXTCTLIN_0 field. */
13811 #define TPIU_EXTCTLINPORT_EXTCTLIN_0_Low (0x0UL) /*!< Input EXTCTL0 is low. */
13812 #define TPIU_EXTCTLINPORT_EXTCTLIN_0_High (0x1UL) /*!< Input EXTCTL0 is high. */
13813 
13814 /* Register: TPIU_EXTCTLOUTPORT */
13815 /* Description: Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. */
13816 
13817 /* Bit 7 : EXTCTL outputs. */
13818 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_7_Pos (7UL) /*!< Position of EXTCTLOUT_7 field. */
13819 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_7_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_7_Pos) /*!< Bit mask of EXTCTLOUT_7 field. */
13820 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_7_Low (0x0UL) /*!< Output EXTCTL7 is low. */
13821 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_7_High (0x1UL) /*!< Output EXTCTL7 is high. */
13822 
13823 /* Bit 6 : EXTCTL outputs. */
13824 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_6_Pos (6UL) /*!< Position of EXTCTLOUT_6 field. */
13825 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_6_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_6_Pos) /*!< Bit mask of EXTCTLOUT_6 field. */
13826 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_6_Low (0x0UL) /*!< Output EXTCTL6 is low. */
13827 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_6_High (0x1UL) /*!< Output EXTCTL6 is high. */
13828 
13829 /* Bit 5 : EXTCTL outputs. */
13830 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_5_Pos (5UL) /*!< Position of EXTCTLOUT_5 field. */
13831 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_5_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_5_Pos) /*!< Bit mask of EXTCTLOUT_5 field. */
13832 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_5_Low (0x0UL) /*!< Output EXTCTL5 is low. */
13833 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_5_High (0x1UL) /*!< Output EXTCTL5 is high. */
13834 
13835 /* Bit 4 : EXTCTL outputs. */
13836 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_4_Pos (4UL) /*!< Position of EXTCTLOUT_4 field. */
13837 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_4_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_4_Pos) /*!< Bit mask of EXTCTLOUT_4 field. */
13838 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_4_Low (0x0UL) /*!< Output EXTCTL4 is low. */
13839 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_4_High (0x1UL) /*!< Output EXTCTL4 is high. */
13840 
13841 /* Bit 3 : EXTCTL outputs. */
13842 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_3_Pos (3UL) /*!< Position of EXTCTLOUT_3 field. */
13843 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_3_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_3_Pos) /*!< Bit mask of EXTCTLOUT_3 field. */
13844 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_3_Low (0x0UL) /*!< Output EXTCTL3 is low. */
13845 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_3_High (0x1UL) /*!< Output EXTCTL3 is high. */
13846 
13847 /* Bit 2 : EXTCTL outputs. */
13848 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_2_Pos (2UL) /*!< Position of EXTCTLOUT_2 field. */
13849 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_2_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_2_Pos) /*!< Bit mask of EXTCTLOUT_2 field. */
13850 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_2_Low (0x0UL) /*!< Output EXTCTL2 is low. */
13851 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_2_High (0x1UL) /*!< Output EXTCTL2 is high. */
13852 
13853 /* Bit 1 : EXTCTL outputs. */
13854 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_1_Pos (1UL) /*!< Position of EXTCTLOUT_1 field. */
13855 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_1_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_1_Pos) /*!< Bit mask of EXTCTLOUT_1 field. */
13856 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_1_Low (0x0UL) /*!< Output EXTCTL1 is low. */
13857 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_1_High (0x1UL) /*!< Output EXTCTL1 is high. */
13858 
13859 /* Bit 0 : EXTCTL outputs. */
13860 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_0_Pos (0UL) /*!< Position of EXTCTLOUT_0 field. */
13861 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_0_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_0_Pos) /*!< Bit mask of EXTCTLOUT_0 field. */
13862 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_0_Low (0x0UL) /*!< Output EXTCTL0 is low. */
13863 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_0_High (0x1UL) /*!< Output EXTCTL0 is high. */
13864 
13865 /* Register: TPIU_ITTRFLINACK */
13866 /* Description: The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU. */
13867 
13868 /* Bit 1 : Sets the value of flushinack. */
13869 #define TPIU_ITTRFLINACK_FLUSHINACK_Pos (1UL) /*!< Position of FLUSHINACK field. */
13870 #define TPIU_ITTRFLINACK_FLUSHINACK_Msk (0x1UL << TPIU_ITTRFLINACK_FLUSHINACK_Pos) /*!< Bit mask of FLUSHINACK field. */
13871 #define TPIU_ITTRFLINACK_FLUSHINACK_Low (0x0UL) /*!< Pin is logic 0. */
13872 #define TPIU_ITTRFLINACK_FLUSHINACK_High (0x1UL) /*!< Pin is logic 1. */
13873 
13874 /* Bit 0 : Sets the value of triginack. */
13875 #define TPIU_ITTRFLINACK_TRIGINACK_Pos (0UL) /*!< Position of TRIGINACK field. */
13876 #define TPIU_ITTRFLINACK_TRIGINACK_Msk (0x1UL << TPIU_ITTRFLINACK_TRIGINACK_Pos) /*!< Bit mask of TRIGINACK field. */
13877 #define TPIU_ITTRFLINACK_TRIGINACK_Low (0x0UL) /*!< Pin is logic 0. */
13878 #define TPIU_ITTRFLINACK_TRIGINACK_High (0x1UL) /*!< Pin is logic 1. */
13879 
13880 /* Register: TPIU_ITTRFLIN */
13881 /* Description: The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU. */
13882 
13883 /* Bit 1 : Reads  the value of flushin. */
13884 #define TPIU_ITTRFLIN_FLUSHIN_Pos (1UL) /*!< Position of FLUSHIN field. */
13885 #define TPIU_ITTRFLIN_FLUSHIN_Msk (0x1UL << TPIU_ITTRFLIN_FLUSHIN_Pos) /*!< Bit mask of FLUSHIN field. */
13886 #define TPIU_ITTRFLIN_FLUSHIN_Low (0x0UL) /*!< Pin is logic 0. */
13887 #define TPIU_ITTRFLIN_FLUSHIN_High (0x1UL) /*!< Pin is logic 1. */
13888 
13889 /* Bit 0 : Reads  the value of trigin. */
13890 #define TPIU_ITTRFLIN_TRIGIN_Pos (0UL) /*!< Position of TRIGIN field. */
13891 #define TPIU_ITTRFLIN_TRIGIN_Msk (0x1UL << TPIU_ITTRFLIN_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */
13892 #define TPIU_ITTRFLIN_TRIGIN_Low (0x0UL) /*!< Pin is logic 0. */
13893 #define TPIU_ITTRFLIN_TRIGIN_High (0x1UL) /*!< Pin is logic 1. */
13894 
13895 /* Register: TPIU_ITATBDATA0 */
13896 /* Description: The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH. */
13897 
13898 /* Bit 4 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
13899 #define TPIU_ITATBDATA0_ATDATA_4_Pos (4UL) /*!< Position of ATDATA_4 field. */
13900 #define TPIU_ITATBDATA0_ATDATA_4_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA_4_Pos) /*!< Bit mask of ATDATA_4 field. */
13901 #define TPIU_ITATBDATA0_ATDATA_4_Low (0x0UL) /*!< Pin is logic 0. */
13902 #define TPIU_ITATBDATA0_ATDATA_4_High (0x1UL) /*!< Pin is logic 1. */
13903 
13904 /* Bit 3 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
13905 #define TPIU_ITATBDATA0_ATDATA_3_Pos (3UL) /*!< Position of ATDATA_3 field. */
13906 #define TPIU_ITATBDATA0_ATDATA_3_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA_3_Pos) /*!< Bit mask of ATDATA_3 field. */
13907 #define TPIU_ITATBDATA0_ATDATA_3_Low (0x0UL) /*!< Pin is logic 0. */
13908 #define TPIU_ITATBDATA0_ATDATA_3_High (0x1UL) /*!< Pin is logic 1. */
13909 
13910 /* Bit 2 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
13911 #define TPIU_ITATBDATA0_ATDATA_2_Pos (2UL) /*!< Position of ATDATA_2 field. */
13912 #define TPIU_ITATBDATA0_ATDATA_2_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA_2_Pos) /*!< Bit mask of ATDATA_2 field. */
13913 #define TPIU_ITATBDATA0_ATDATA_2_Low (0x0UL) /*!< Pin is logic 0. */
13914 #define TPIU_ITATBDATA0_ATDATA_2_High (0x1UL) /*!< Pin is logic 1. */
13915 
13916 /* Bit 1 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
13917 #define TPIU_ITATBDATA0_ATDATA_1_Pos (1UL) /*!< Position of ATDATA_1 field. */
13918 #define TPIU_ITATBDATA0_ATDATA_1_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA_1_Pos) /*!< Bit mask of ATDATA_1 field. */
13919 #define TPIU_ITATBDATA0_ATDATA_1_Low (0x0UL) /*!< Pin is logic 0. */
13920 #define TPIU_ITATBDATA0_ATDATA_1_High (0x1UL) /*!< Pin is logic 1. */
13921 
13922 /* Bit 0 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */
13923 #define TPIU_ITATBDATA0_ATDATA_0_Pos (0UL) /*!< Position of ATDATA_0 field. */
13924 #define TPIU_ITATBDATA0_ATDATA_0_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA_0_Pos) /*!< Bit mask of ATDATA_0 field. */
13925 #define TPIU_ITATBDATA0_ATDATA_0_Low (0x0UL) /*!< Pin is logic 0. */
13926 #define TPIU_ITATBDATA0_ATDATA_0_High (0x1UL) /*!< Pin is logic 1. */
13927 
13928 /* Register: TPIU_ITATBCTR2 */
13929 /* Description: Enables control of the atreadys and afvalids outputs of the TPIU. */
13930 
13931 /* Bit 1 : Sets the value of atready. */
13932 #define TPIU_ITATBCTR2_AFVALID_Pos (1UL) /*!< Position of AFVALID field. */
13933 #define TPIU_ITATBCTR2_AFVALID_Msk (0x1UL << TPIU_ITATBCTR2_AFVALID_Pos) /*!< Bit mask of AFVALID field. */
13934 #define TPIU_ITATBCTR2_AFVALID_Low (0x0UL) /*!< Pin is logic 0. */
13935 #define TPIU_ITATBCTR2_AFVALID_High (0x1UL) /*!< Pin is logic 1. */
13936 
13937 /* Bit 0 : Sets the value of afvalid. */
13938 #define TPIU_ITATBCTR2_ATREADY_Pos (0UL) /*!< Position of ATREADY field. */
13939 #define TPIU_ITATBCTR2_ATREADY_Msk (0x1UL << TPIU_ITATBCTR2_ATREADY_Pos) /*!< Bit mask of ATREADY field. */
13940 #define TPIU_ITATBCTR2_ATREADY_Low (0x0UL) /*!< Pin is logic 0. */
13941 #define TPIU_ITATBCTR2_ATREADY_High (0x1UL) /*!< Pin is logic 1. */
13942 
13943 /* Register: TPIU_ITATBCTR1 */
13944 /* Description: The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH. */
13945 
13946 /* Bits 6..0 : Reads the value of atids. */
13947 #define TPIU_ITATBCTR1_ATID_Pos (0UL) /*!< Position of ATID field. */
13948 #define TPIU_ITATBCTR1_ATID_Msk (0x7FUL << TPIU_ITATBCTR1_ATID_Pos) /*!< Bit mask of ATID field. */
13949 #define TPIU_ITATBCTR1_ATID_Low (0x00UL) /*!< Pin is logic 0. */
13950 #define TPIU_ITATBCTR1_ATID_High (0x01UL) /*!< Pin is logic 1. */
13951 
13952 /* Register: TPIU_ITATBCTR0 */
13953 /* Description: The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU.
13954       To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH. */
13955 
13956 /* Bits 9..8 : Reads the value of atbytess. */
13957 #define TPIU_ITATBCTR0_ATBYTES_Pos (8UL) /*!< Position of ATBYTES field. */
13958 #define TPIU_ITATBCTR0_ATBYTES_Msk (0x3UL << TPIU_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field. */
13959 #define TPIU_ITATBCTR0_ATBYTES_Low (0x0UL) /*!< Pin is logic 0. */
13960 #define TPIU_ITATBCTR0_ATBYTES_High (0x1UL) /*!< Pin is logic 1. */
13961 
13962 /* Bit 2 : Reads the value of afreadys. */
13963 #define TPIU_ITATBCTR0_AFREADY_Pos (2UL) /*!< Position of AFREADY field. */
13964 #define TPIU_ITATBCTR0_AFREADY_Msk (0x1UL << TPIU_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field. */
13965 #define TPIU_ITATBCTR0_AFREADY_Low (0x0UL) /*!< Pin is logic 0. */
13966 #define TPIU_ITATBCTR0_AFREADY_High (0x1UL) /*!< Pin is logic 1. */
13967 
13968 /* Bit 0 : Reads the value of atvalids. */
13969 #define TPIU_ITATBCTR0_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */
13970 #define TPIU_ITATBCTR0_ATVALID_Msk (0x1UL << TPIU_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field. */
13971 #define TPIU_ITATBCTR0_ATVALID_Low (0x0UL) /*!< Pin is logic 0. */
13972 #define TPIU_ITATBCTR0_ATVALID_High (0x1UL) /*!< Pin is logic 1. */
13973 
13974 /* Register: TPIU_ITCTRL */
13975 /* Description: Used to enable topology detection.
13976         This register enables the component to switch from a functional mode, the default behavior,
13977         to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. */
13978 
13979 /* Bit 0 : Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. */
13980 #define TPIU_ITCTRL_INTEGRATIONMODE_Pos (0UL) /*!< Position of INTEGRATIONMODE field. */
13981 #define TPIU_ITCTRL_INTEGRATIONMODE_Msk (0x1UL << TPIU_ITCTRL_INTEGRATIONMODE_Pos) /*!< Bit mask of INTEGRATIONMODE field. */
13982 #define TPIU_ITCTRL_INTEGRATIONMODE_Disabled (0x0UL) /*!< Integration mode is disabled. */
13983 #define TPIU_ITCTRL_INTEGRATIONMODE_Enabled (0x1UL) /*!< Integration mode is Enabled. */
13984 
13985 /* Register: TPIU_CLAIMSET */
13986 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality.
13987       The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. */
13988 
13989 /* Bit 3 : Set claim bit 3 and check if bit is implemented or not. */
13990 #define TPIU_CLAIMSET_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */
13991 #define TPIU_CLAIMSET_BIT_3_Msk (0x1UL << TPIU_CLAIMSET_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */
13992 #define TPIU_CLAIMSET_BIT_3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented. */
13993 #define TPIU_CLAIMSET_BIT_3_Implemented (0x1UL) /*!< Claim bit 3 is implemented. */
13994 #define TPIU_CLAIMSET_BIT_3_Set (0x1UL) /*!< Set claim bit 3. */
13995 
13996 /* Bit 2 : Set claim bit 2 and check if bit is implemented or not. */
13997 #define TPIU_CLAIMSET_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */
13998 #define TPIU_CLAIMSET_BIT_2_Msk (0x1UL << TPIU_CLAIMSET_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */
13999 #define TPIU_CLAIMSET_BIT_2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented. */
14000 #define TPIU_CLAIMSET_BIT_2_Implemented (0x1UL) /*!< Claim bit 2 is implemented. */
14001 #define TPIU_CLAIMSET_BIT_2_Set (0x1UL) /*!< Set claim bit 2. */
14002 
14003 /* Bit 1 : Set claim bit 1 and check if bit is implemented or not. */
14004 #define TPIU_CLAIMSET_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */
14005 #define TPIU_CLAIMSET_BIT_1_Msk (0x1UL << TPIU_CLAIMSET_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */
14006 #define TPIU_CLAIMSET_BIT_1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented. */
14007 #define TPIU_CLAIMSET_BIT_1_Implemented (0x1UL) /*!< Claim bit 1 is implemented. */
14008 #define TPIU_CLAIMSET_BIT_1_Set (0x1UL) /*!< Set claim bit 1. */
14009 
14010 /* Bit 0 : Set claim bit 0 and check if bit is implemented or not. */
14011 #define TPIU_CLAIMSET_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */
14012 #define TPIU_CLAIMSET_BIT_0_Msk (0x1UL << TPIU_CLAIMSET_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */
14013 #define TPIU_CLAIMSET_BIT_0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented. */
14014 #define TPIU_CLAIMSET_BIT_0_Implemented (0x1UL) /*!< Claim bit 0 is implemented. */
14015 #define TPIU_CLAIMSET_BIT_0_Set (0x1UL) /*!< Set claim bit 0. */
14016 
14017 /* Register: TPIU_CLAIMCLR */
14018 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality.
14019       The claim tags have no effect on the operation of the component.
14020       The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. */
14021 
14022 /* Bit 3 : Read or clear claim bit 3. */
14023 #define TPIU_CLAIMCLR_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */
14024 #define TPIU_CLAIMCLR_BIT_3_Msk (0x1UL << TPIU_CLAIMCLR_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */
14025 #define TPIU_CLAIMCLR_BIT_3_Cleared (0x0UL) /*!< Claim bit 3 is not set. */
14026 #define TPIU_CLAIMCLR_BIT_3_Set (0x1UL) /*!< Claim bit 3 is set. */
14027 #define TPIU_CLAIMCLR_BIT_3_Clear (0x1UL) /*!< Clear claim bit 3. */
14028 
14029 /* Bit 2 : Read or clear claim bit 2. */
14030 #define TPIU_CLAIMCLR_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */
14031 #define TPIU_CLAIMCLR_BIT_2_Msk (0x1UL << TPIU_CLAIMCLR_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */
14032 #define TPIU_CLAIMCLR_BIT_2_Cleared (0x0UL) /*!< Claim bit 2 is not set. */
14033 #define TPIU_CLAIMCLR_BIT_2_Set (0x1UL) /*!< Claim bit 2 is set. */
14034 #define TPIU_CLAIMCLR_BIT_2_Clear (0x1UL) /*!< Clear claim bit 2. */
14035 
14036 /* Bit 1 : Read or clear claim bit 1. */
14037 #define TPIU_CLAIMCLR_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */
14038 #define TPIU_CLAIMCLR_BIT_1_Msk (0x1UL << TPIU_CLAIMCLR_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */
14039 #define TPIU_CLAIMCLR_BIT_1_Cleared (0x0UL) /*!< Claim bit 1 is not set. */
14040 #define TPIU_CLAIMCLR_BIT_1_Set (0x1UL) /*!< Claim bit 1 is set. */
14041 #define TPIU_CLAIMCLR_BIT_1_Clear (0x1UL) /*!< Clear claim bit 1. */
14042 
14043 /* Bit 0 : Read or clear claim bit 0. */
14044 #define TPIU_CLAIMCLR_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */
14045 #define TPIU_CLAIMCLR_BIT_0_Msk (0x1UL << TPIU_CLAIMCLR_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */
14046 #define TPIU_CLAIMCLR_BIT_0_Cleared (0x0UL) /*!< Claim bit 0 is not set. */
14047 #define TPIU_CLAIMCLR_BIT_0_Set (0x1UL) /*!< Claim bit 0 is set. */
14048 #define TPIU_CLAIMCLR_BIT_0_Clear (0x1UL) /*!< Clear claim bit 0. */
14049 
14050 /* Register: TPIU_LAR */
14051 /* Description: This is used to enable write access to device registers. */
14052 
14053 /* Bits 31..0 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. */
14054 #define TPIU_LAR_ACCESS_Pos (0UL) /*!< Position of ACCESS field. */
14055 #define TPIU_LAR_ACCESS_Msk (0xFFFFFFFFUL << TPIU_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field. */
14056 #define TPIU_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface. */
14057 
14058 /* Register: TPIU_LSR */
14059 /* Description: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug.
14060       Accesses to the extended stimulus port registers are not affected by the lock mechanism.
14061       This register must always be present although there might not be any lock access control mechanism.
14062       The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register.
14063       For most components this covers all registers except for the Lock Access Register. */
14064 
14065 /* Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */
14066 #define TPIU_LSR_TYPE_Pos (2UL) /*!< Position of TYPE field. */
14067 #define TPIU_LSR_TYPE_Msk (0x1UL << TPIU_LSR_TYPE_Pos) /*!< Bit mask of TYPE field. */
14068 #define TPIU_LSR_TYPE_Bits32 (0x0UL) /*!< This component implements a 32-bit Lock Access Register. */
14069 #define TPIU_LSR_TYPE_Bits8 (0x1UL) /*!< This component implements an 8-bit Lock Access Register. */
14070 
14071 /* Bit 1 : Returns the current status of the Lock. */
14072 #define TPIU_LSR_LOCKED_Pos (1UL) /*!< Position of LOCKED field. */
14073 #define TPIU_LSR_LOCKED_Msk (0x1UL << TPIU_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */
14074 #define TPIU_LSR_LOCKED_UnLocked (0x0UL) /*!< Write access is allowed to this device. */
14075 #define TPIU_LSR_LOCKED_Locked (0x1UL) /*!< Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. */
14076 
14077 /* Bit 0 : Indicates that a lock control mechanism exists for this device. */
14078 #define TPIU_LSR_PRESENT_Pos (0UL) /*!< Position of PRESENT field. */
14079 #define TPIU_LSR_PRESENT_Msk (0x1UL << TPIU_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field. */
14080 #define TPIU_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access Register are ignored. */
14081 #define TPIU_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present. */
14082 
14083 /* Register: TPIU_AUTHSTATUS */
14084 /* Description: Indicates the current level of tracing permitted by the system */
14085 
14086 /* Bits 7..6 : Secure Non-Invasive Debug */
14087 #define TPIU_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */
14088 #define TPIU_AUTHSTATUS_SNID_Msk (0x3UL << TPIU_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */
14089 #define TPIU_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
14090 #define TPIU_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */
14091 
14092 /* Bits 5..4 : Secure Invasive Debug */
14093 #define TPIU_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */
14094 #define TPIU_AUTHSTATUS_SID_Msk (0x3UL << TPIU_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */
14095 #define TPIU_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
14096 #define TPIU_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */
14097 
14098 /* Bits 3..2 : Non-secure Non-Invasive Debug */
14099 #define TPIU_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */
14100 #define TPIU_AUTHSTATUS_NSNID_Msk (0x3UL << TPIU_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */
14101 #define TPIU_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
14102 #define TPIU_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */
14103 
14104 /* Bits 1..0 : Non-secure Invasive Debug */
14105 #define TPIU_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */
14106 #define TPIU_AUTHSTATUS_NSID_Msk (0x3UL << TPIU_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */
14107 #define TPIU_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */
14108 #define TPIU_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */
14109 
14110 /* Register: TPIU_DEVID */
14111 /* Description: Indicates the capabilities of the component. */
14112 
14113 /* Bit 11 : Indicates whether Serial Wire Output, UART or NRZ, is supported. */
14114 #define TPIU_DEVID_SWOUARTNRZ_Pos (11UL) /*!< Position of SWOUARTNRZ field. */
14115 #define TPIU_DEVID_SWOUARTNRZ_Msk (0x1UL << TPIU_DEVID_SWOUARTNRZ_Pos) /*!< Bit mask of SWOUARTNRZ field. */
14116 #define TPIU_DEVID_SWOUARTNRZ_NotSupported (0x0UL) /*!< Serial Wire Output, UART or NRZ, is not supported. */
14117 #define TPIU_DEVID_SWOUARTNRZ_Supported (0x1UL) /*!< Serial Wire Output, UART or NRZ, is supported. */
14118 
14119 /* Bit 10 : Indicates whether Serial Wire Output, Manchester encoded format, is supported. */
14120 #define TPIU_DEVID_SWOMAN_Pos (10UL) /*!< Position of SWOMAN field. */
14121 #define TPIU_DEVID_SWOMAN_Msk (0x1UL << TPIU_DEVID_SWOMAN_Pos) /*!< Bit mask of SWOMAN field. */
14122 #define TPIU_DEVID_SWOMAN_NotSupported (0x0UL) /*!< Serial Wire Output, Manchester encoded format, is not supported. */
14123 #define TPIU_DEVID_SWOMAN_Supported (0x1UL) /*!< Serial Wire Output, Manchester encoded format, is supported. */
14124 
14125 /* Bit 9 : Indicates whether trace clock plus data is supported. */
14126 #define TPIU_DEVID_TCLKDATA_Pos (9UL) /*!< Position of TCLKDATA field. */
14127 #define TPIU_DEVID_TCLKDATA_Msk (0x1UL << TPIU_DEVID_TCLKDATA_Pos) /*!< Bit mask of TCLKDATA field. */
14128 #define TPIU_DEVID_TCLKDATA_Supported (0x0UL) /*!< Trace clock and data is supported. */
14129 #define TPIU_DEVID_TCLKDATA_NotSupported (0x1UL) /*!< Trace clock and data is not supported. */
14130 
14131 /* Bits 8..6 : FIFO size in powers of 2. */
14132 #define TPIU_DEVID_FIFOSIZE_Pos (6UL) /*!< Position of FIFOSIZE field. */
14133 #define TPIU_DEVID_FIFOSIZE_Msk (0x7UL << TPIU_DEVID_FIFOSIZE_Pos) /*!< Bit mask of FIFOSIZE field. */
14134 #define TPIU_DEVID_FIFOSIZE_Entries4 (0x2UL) /*!< FIFO size of 4 entries, that is, 16 bytes. */
14135 
14136 /* Bit 5 : Indicates the relationship between atclk and traceclkin. */
14137 #define TPIU_DEVID_CLKRELAT_Pos (5UL) /*!< Position of CLKRELAT field. */
14138 #define TPIU_DEVID_CLKRELAT_Msk (0x1UL << TPIU_DEVID_CLKRELAT_Pos) /*!< Bit mask of CLKRELAT field. */
14139 #define TPIU_DEVID_CLKRELAT_Synchronous (0x0UL) /*!< atclk and traceclkin are synchronous. */
14140 #define TPIU_DEVID_CLKRELAT_ASynchronous (0x1UL) /*!< atclk and traceclkin are asynchronous. */
14141 
14142 /* Bits 4..0 : Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of multiplexing on the input to the ATB.
14143         Currently only 0x00 is supported, that is, no multiplexing is present. This value helps detect the ATB structure. */
14144 #define TPIU_DEVID_MUXNUM_Pos (0UL) /*!< Position of MUXNUM field. */
14145 #define TPIU_DEVID_MUXNUM_Msk (0x1FUL << TPIU_DEVID_MUXNUM_Pos) /*!< Bit mask of MUXNUM field. */
14146 
14147 /* Register: TPIU_DEVTYPE */
14148 /* Description: The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. */
14149 
14150 /* Bits 7..4 : The sub-type of the component */
14151 #define TPIU_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */
14152 #define TPIU_DEVTYPE_SUB_Msk (0xFUL << TPIU_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */
14153 #define TPIU_DEVTYPE_SUB_TracePort (0x1UL) /*!< Indicates that this component is a trace port component. */
14154 
14155 /* Bits 3..0 : The main type of the component */
14156 #define TPIU_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */
14157 #define TPIU_DEVTYPE_MAJOR_Msk (0xFUL << TPIU_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */
14158 #define TPIU_DEVTYPE_MAJOR_TraceSource (0x1UL) /*!< Peripheral is a trace sink. */
14159 
14160 
14161 /* Peripheral: TWIM */
14162 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
14163 
14164 /* Register: TWIM_TASKS_STARTRX */
14165 /* Description: Start TWI receive sequence */
14166 
14167 /* Bit 0 : Start TWI receive sequence */
14168 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
14169 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
14170 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */
14171 
14172 /* Register: TWIM_TASKS_STARTTX */
14173 /* Description: Start TWI transmit sequence */
14174 
14175 /* Bit 0 : Start TWI transmit sequence */
14176 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
14177 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
14178 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */
14179 
14180 /* Register: TWIM_TASKS_STOP */
14181 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
14182 
14183 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
14184 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
14185 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
14186 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
14187 
14188 /* Register: TWIM_TASKS_SUSPEND */
14189 /* Description: Suspend TWI transaction */
14190 
14191 /* Bit 0 : Suspend TWI transaction */
14192 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
14193 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
14194 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */
14195 
14196 /* Register: TWIM_TASKS_RESUME */
14197 /* Description: Resume TWI transaction */
14198 
14199 /* Bit 0 : Resume TWI transaction */
14200 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
14201 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
14202 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */
14203 
14204 /* Register: TWIM_SUBSCRIBE_STARTRX */
14205 /* Description: Subscribe configuration for task STARTRX */
14206 
14207 /* Bit 31 :   */
14208 #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
14209 #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
14210 #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0x0UL) /*!< Disable subscription */
14211 #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (0x1UL) /*!< Enable subscription */
14212 
14213 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
14214 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14215 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14216 
14217 /* Register: TWIM_SUBSCRIBE_STARTTX */
14218 /* Description: Subscribe configuration for task STARTTX */
14219 
14220 /* Bit 31 :   */
14221 #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
14222 #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
14223 #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription */
14224 #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription */
14225 
14226 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
14227 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14228 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14229 
14230 /* Register: TWIM_SUBSCRIBE_STOP */
14231 /* Description: Subscribe configuration for task STOP */
14232 
14233 /* Bit 31 :   */
14234 #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
14235 #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
14236 #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
14237 #define TWIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */
14238 
14239 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
14240 #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14241 #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14242 
14243 /* Register: TWIM_SUBSCRIBE_SUSPEND */
14244 /* Description: Subscribe configuration for task SUSPEND */
14245 
14246 /* Bit 31 :   */
14247 #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
14248 #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
14249 #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */
14250 #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */
14251 
14252 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
14253 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14254 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14255 
14256 /* Register: TWIM_SUBSCRIBE_RESUME */
14257 /* Description: Subscribe configuration for task RESUME */
14258 
14259 /* Bit 31 :   */
14260 #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
14261 #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
14262 #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */
14263 #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */
14264 
14265 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
14266 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14267 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14268 
14269 /* Register: TWIM_EVENTS_STOPPED */
14270 /* Description: TWI stopped */
14271 
14272 /* Bit 0 : TWI stopped */
14273 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
14274 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
14275 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
14276 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
14277 
14278 /* Register: TWIM_EVENTS_ERROR */
14279 /* Description: TWI error */
14280 
14281 /* Bit 0 : TWI error */
14282 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
14283 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
14284 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
14285 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */
14286 
14287 /* Register: TWIM_EVENTS_SUSPENDED */
14288 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */
14289 
14290 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
14291 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
14292 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
14293 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0x0UL) /*!< Event not generated */
14294 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (0x1UL) /*!< Event generated */
14295 
14296 /* Register: TWIM_EVENTS_RXSTARTED */
14297 /* Description: Receive sequence started */
14298 
14299 /* Bit 0 : Receive sequence started */
14300 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
14301 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
14302 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
14303 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */
14304 
14305 /* Register: TWIM_EVENTS_TXSTARTED */
14306 /* Description: Transmit sequence started */
14307 
14308 /* Bit 0 : Transmit sequence started */
14309 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
14310 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
14311 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
14312 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */
14313 
14314 /* Register: TWIM_EVENTS_LASTRX */
14315 /* Description: Byte boundary, starting to receive the last byte */
14316 
14317 /* Bit 0 : Byte boundary, starting to receive the last byte */
14318 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
14319 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
14320 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0x0UL) /*!< Event not generated */
14321 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (0x1UL) /*!< Event generated */
14322 
14323 /* Register: TWIM_EVENTS_LASTTX */
14324 /* Description: Byte boundary, starting to transmit the last byte */
14325 
14326 /* Bit 0 : Byte boundary, starting to transmit the last byte */
14327 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
14328 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
14329 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0x0UL) /*!< Event not generated */
14330 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (0x1UL) /*!< Event generated */
14331 
14332 /* Register: TWIM_PUBLISH_STOPPED */
14333 /* Description: Publish configuration for event STOPPED */
14334 
14335 /* Bit 31 :   */
14336 #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
14337 #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
14338 #define TWIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
14339 #define TWIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */
14340 
14341 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
14342 #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14343 #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14344 
14345 /* Register: TWIM_PUBLISH_ERROR */
14346 /* Description: Publish configuration for event ERROR */
14347 
14348 /* Bit 31 :   */
14349 #define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
14350 #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
14351 #define TWIM_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */
14352 #define TWIM_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */
14353 
14354 /* Bits 7..0 : DPPI channel that event ERROR will publish to */
14355 #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14356 #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14357 
14358 /* Register: TWIM_PUBLISH_SUSPENDED */
14359 /* Description: Publish configuration for event SUSPENDED */
14360 
14361 /* Bit 31 :   */
14362 #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */
14363 #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */
14364 #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0x0UL) /*!< Disable publishing */
14365 #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (0x1UL) /*!< Enable publishing */
14366 
14367 /* Bits 7..0 : DPPI channel that event SUSPENDED will publish to */
14368 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14369 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14370 
14371 /* Register: TWIM_PUBLISH_RXSTARTED */
14372 /* Description: Publish configuration for event RXSTARTED */
14373 
14374 /* Bit 31 :   */
14375 #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
14376 #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
14377 #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
14378 #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
14379 
14380 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
14381 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14382 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14383 
14384 /* Register: TWIM_PUBLISH_TXSTARTED */
14385 /* Description: Publish configuration for event TXSTARTED */
14386 
14387 /* Bit 31 :   */
14388 #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
14389 #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
14390 #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
14391 #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
14392 
14393 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
14394 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14395 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14396 
14397 /* Register: TWIM_PUBLISH_LASTRX */
14398 /* Description: Publish configuration for event LASTRX */
14399 
14400 /* Bit 31 :   */
14401 #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */
14402 #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */
14403 #define TWIM_PUBLISH_LASTRX_EN_Disabled (0x0UL) /*!< Disable publishing */
14404 #define TWIM_PUBLISH_LASTRX_EN_Enabled (0x1UL) /*!< Enable publishing */
14405 
14406 /* Bits 7..0 : DPPI channel that event LASTRX will publish to */
14407 #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14408 #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14409 
14410 /* Register: TWIM_PUBLISH_LASTTX */
14411 /* Description: Publish configuration for event LASTTX */
14412 
14413 /* Bit 31 :   */
14414 #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */
14415 #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */
14416 #define TWIM_PUBLISH_LASTTX_EN_Disabled (0x0UL) /*!< Disable publishing */
14417 #define TWIM_PUBLISH_LASTTX_EN_Enabled (0x1UL) /*!< Enable publishing */
14418 
14419 /* Bits 7..0 : DPPI channel that event LASTTX will publish to */
14420 #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14421 #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14422 
14423 /* Register: TWIM_SHORTS */
14424 /* Description: Shortcuts between local events and tasks */
14425 
14426 /* Bit 12 : Shortcut between event LASTRX and task STOP */
14427 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
14428 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
14429 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0x0UL) /*!< Disable shortcut */
14430 #define TWIM_SHORTS_LASTRX_STOP_Enabled (0x1UL) /*!< Enable shortcut */
14431 
14432 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
14433 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
14434 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
14435 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0x0UL) /*!< Disable shortcut */
14436 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (0x1UL) /*!< Enable shortcut */
14437 
14438 /* Bit 9 : Shortcut between event LASTTX and task STOP */
14439 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
14440 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
14441 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0x0UL) /*!< Disable shortcut */
14442 #define TWIM_SHORTS_LASTTX_STOP_Enabled (0x1UL) /*!< Enable shortcut */
14443 
14444 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
14445 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
14446 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
14447 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
14448 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */
14449 
14450 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
14451 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
14452 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
14453 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */
14454 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */
14455 
14456 /* Register: TWIM_INTEN */
14457 /* Description: Enable or disable interrupt */
14458 
14459 /* Bit 24 : Enable or disable interrupt for event LASTTX */
14460 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
14461 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
14462 #define TWIM_INTEN_LASTTX_Disabled (0x0UL) /*!< Disable */
14463 #define TWIM_INTEN_LASTTX_Enabled (0x1UL) /*!< Enable */
14464 
14465 /* Bit 23 : Enable or disable interrupt for event LASTRX */
14466 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
14467 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
14468 #define TWIM_INTEN_LASTRX_Disabled (0x0UL) /*!< Disable */
14469 #define TWIM_INTEN_LASTRX_Enabled (0x1UL) /*!< Enable */
14470 
14471 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
14472 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14473 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14474 #define TWIM_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */
14475 #define TWIM_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */
14476 
14477 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
14478 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14479 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14480 #define TWIM_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */
14481 #define TWIM_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */
14482 
14483 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
14484 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
14485 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
14486 #define TWIM_INTEN_SUSPENDED_Disabled (0x0UL) /*!< Disable */
14487 #define TWIM_INTEN_SUSPENDED_Enabled (0x1UL) /*!< Enable */
14488 
14489 /* Bit 9 : Enable or disable interrupt for event ERROR */
14490 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14491 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
14492 #define TWIM_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
14493 #define TWIM_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */
14494 
14495 /* Bit 1 : Enable or disable interrupt for event STOPPED */
14496 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14497 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14498 #define TWIM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
14499 #define TWIM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
14500 
14501 /* Register: TWIM_INTENSET */
14502 /* Description: Enable interrupt */
14503 
14504 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
14505 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
14506 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
14507 #define TWIM_INTENSET_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */
14508 #define TWIM_INTENSET_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */
14509 #define TWIM_INTENSET_LASTTX_Set (0x1UL) /*!< Enable */
14510 
14511 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
14512 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
14513 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
14514 #define TWIM_INTENSET_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */
14515 #define TWIM_INTENSET_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */
14516 #define TWIM_INTENSET_LASTRX_Set (0x1UL) /*!< Enable */
14517 
14518 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
14519 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14520 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14521 #define TWIM_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
14522 #define TWIM_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
14523 #define TWIM_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */
14524 
14525 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
14526 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14527 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14528 #define TWIM_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
14529 #define TWIM_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
14530 #define TWIM_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */
14531 
14532 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
14533 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
14534 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
14535 #define TWIM_INTENSET_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */
14536 #define TWIM_INTENSET_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */
14537 #define TWIM_INTENSET_SUSPENDED_Set (0x1UL) /*!< Enable */
14538 
14539 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
14540 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14541 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
14542 #define TWIM_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
14543 #define TWIM_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
14544 #define TWIM_INTENSET_ERROR_Set (0x1UL) /*!< Enable */
14545 
14546 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
14547 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14548 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14549 #define TWIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
14550 #define TWIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
14551 #define TWIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
14552 
14553 /* Register: TWIM_INTENCLR */
14554 /* Description: Disable interrupt */
14555 
14556 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
14557 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
14558 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
14559 #define TWIM_INTENCLR_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */
14560 #define TWIM_INTENCLR_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */
14561 #define TWIM_INTENCLR_LASTTX_Clear (0x1UL) /*!< Disable */
14562 
14563 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
14564 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
14565 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
14566 #define TWIM_INTENCLR_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */
14567 #define TWIM_INTENCLR_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */
14568 #define TWIM_INTENCLR_LASTRX_Clear (0x1UL) /*!< Disable */
14569 
14570 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
14571 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14572 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14573 #define TWIM_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
14574 #define TWIM_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
14575 #define TWIM_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */
14576 
14577 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
14578 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14579 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14580 #define TWIM_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
14581 #define TWIM_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
14582 #define TWIM_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */
14583 
14584 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
14585 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
14586 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
14587 #define TWIM_INTENCLR_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */
14588 #define TWIM_INTENCLR_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */
14589 #define TWIM_INTENCLR_SUSPENDED_Clear (0x1UL) /*!< Disable */
14590 
14591 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
14592 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14593 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
14594 #define TWIM_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
14595 #define TWIM_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
14596 #define TWIM_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */
14597 
14598 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
14599 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14600 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14601 #define TWIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
14602 #define TWIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
14603 #define TWIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
14604 
14605 /* Register: TWIM_ERRORSRC */
14606 /* Description: Error source */
14607 
14608 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
14609 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
14610 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
14611 #define TWIM_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */
14612 #define TWIM_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */
14613 
14614 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
14615 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
14616 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
14617 #define TWIM_ERRORSRC_ANACK_NotReceived (0x0UL) /*!< Error did not occur */
14618 #define TWIM_ERRORSRC_ANACK_Received (0x1UL) /*!< Error occurred */
14619 
14620 /* Bit 0 : Overrun error */
14621 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
14622 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
14623 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0x0UL) /*!< Error did not occur */
14624 #define TWIM_ERRORSRC_OVERRUN_Received (0x1UL) /*!< Error occurred */
14625 
14626 /* Register: TWIM_ENABLE */
14627 /* Description: Enable TWIM */
14628 
14629 /* Bits 3..0 : Enable or disable TWIM */
14630 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14631 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14632 #define TWIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIM */
14633 #define TWIM_ENABLE_ENABLE_Enabled (0x6UL) /*!< Enable TWIM */
14634 
14635 /* Register: TWIM_PSEL_SCL */
14636 /* Description: Pin select for SCL signal */
14637 
14638 /* Bit 31 : Connection */
14639 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14640 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14641 #define TWIM_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */
14642 #define TWIM_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14643 
14644 /* Bits 4..0 : Pin number */
14645 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
14646 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
14647 
14648 /* Register: TWIM_PSEL_SDA */
14649 /* Description: Pin select for SDA signal */
14650 
14651 /* Bit 31 : Connection */
14652 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14653 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14654 #define TWIM_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */
14655 #define TWIM_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14656 
14657 /* Bits 4..0 : Pin number */
14658 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
14659 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
14660 
14661 /* Register: TWIM_FREQUENCY */
14662 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
14663 
14664 /* Bits 31..0 : TWI master clock frequency */
14665 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
14666 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
14667 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
14668 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
14669 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
14670 
14671 /* Register: TWIM_RXD_PTR */
14672 /* Description: Data pointer */
14673 
14674 /* Bits 31..0 : Data pointer */
14675 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14676 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14677 
14678 /* Register: TWIM_RXD_MAXCNT */
14679 /* Description: Maximum number of bytes in receive buffer */
14680 
14681 /* Bits 12..0 : Maximum number of bytes in receive buffer */
14682 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14683 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14684 
14685 /* Register: TWIM_RXD_AMOUNT */
14686 /* Description: Number of bytes transferred in the last transaction */
14687 
14688 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
14689 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14690 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14691 
14692 /* Register: TWIM_RXD_LIST */
14693 /* Description: EasyDMA list type */
14694 
14695 /* Bits 1..0 : List type */
14696 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14697 #define TWIM_RXD_LIST_LIST_Msk (0x3UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14698 #define TWIM_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
14699 #define TWIM_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
14700 
14701 /* Register: TWIM_TXD_PTR */
14702 /* Description: Data pointer */
14703 
14704 /* Bits 31..0 : Data pointer */
14705 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14706 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14707 
14708 /* Register: TWIM_TXD_MAXCNT */
14709 /* Description: Maximum number of bytes in transmit buffer */
14710 
14711 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
14712 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14713 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14714 
14715 /* Register: TWIM_TXD_AMOUNT */
14716 /* Description: Number of bytes transferred in the last transaction */
14717 
14718 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
14719 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14720 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14721 
14722 /* Register: TWIM_TXD_LIST */
14723 /* Description: EasyDMA list type */
14724 
14725 /* Bits 1..0 : List type */
14726 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14727 #define TWIM_TXD_LIST_LIST_Msk (0x3UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14728 #define TWIM_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
14729 #define TWIM_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
14730 
14731 /* Register: TWIM_ADDRESS */
14732 /* Description: Address used in the TWI transfer */
14733 
14734 /* Bits 6..0 : Address used in the TWI transfer */
14735 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
14736 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
14737 
14738 
14739 /* Peripheral: TWIS */
14740 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
14741 
14742 /* Register: TWIS_TASKS_STOP */
14743 /* Description: Stop TWI transaction */
14744 
14745 /* Bit 0 : Stop TWI transaction */
14746 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
14747 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
14748 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
14749 
14750 /* Register: TWIS_TASKS_SUSPEND */
14751 /* Description: Suspend TWI transaction */
14752 
14753 /* Bit 0 : Suspend TWI transaction */
14754 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
14755 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
14756 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */
14757 
14758 /* Register: TWIS_TASKS_RESUME */
14759 /* Description: Resume TWI transaction */
14760 
14761 /* Bit 0 : Resume TWI transaction */
14762 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
14763 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
14764 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */
14765 
14766 /* Register: TWIS_TASKS_PREPARERX */
14767 /* Description: Prepare the TWI slave to respond to a write command */
14768 
14769 /* Bit 0 : Prepare the TWI slave to respond to a write command */
14770 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
14771 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
14772 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (0x1UL) /*!< Trigger task */
14773 
14774 /* Register: TWIS_TASKS_PREPARETX */
14775 /* Description: Prepare the TWI slave to respond to a read command */
14776 
14777 /* Bit 0 : Prepare the TWI slave to respond to a read command */
14778 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
14779 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
14780 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (0x1UL) /*!< Trigger task */
14781 
14782 /* Register: TWIS_SUBSCRIBE_STOP */
14783 /* Description: Subscribe configuration for task STOP */
14784 
14785 /* Bit 31 :   */
14786 #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
14787 #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
14788 #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
14789 #define TWIS_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */
14790 
14791 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
14792 #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14793 #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14794 
14795 /* Register: TWIS_SUBSCRIBE_SUSPEND */
14796 /* Description: Subscribe configuration for task SUSPEND */
14797 
14798 /* Bit 31 :   */
14799 #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
14800 #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
14801 #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */
14802 #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */
14803 
14804 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
14805 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14806 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14807 
14808 /* Register: TWIS_SUBSCRIBE_RESUME */
14809 /* Description: Subscribe configuration for task RESUME */
14810 
14811 /* Bit 31 :   */
14812 #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
14813 #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
14814 #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */
14815 #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */
14816 
14817 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
14818 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14819 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14820 
14821 /* Register: TWIS_SUBSCRIBE_PREPARERX */
14822 /* Description: Subscribe configuration for task PREPARERX */
14823 
14824 /* Bit 31 :   */
14825 #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */
14826 #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */
14827 #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0x0UL) /*!< Disable subscription */
14828 #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (0x1UL) /*!< Enable subscription */
14829 
14830 /* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */
14831 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14832 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14833 
14834 /* Register: TWIS_SUBSCRIBE_PREPARETX */
14835 /* Description: Subscribe configuration for task PREPARETX */
14836 
14837 /* Bit 31 :   */
14838 #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */
14839 #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */
14840 #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0x0UL) /*!< Disable subscription */
14841 #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (0x1UL) /*!< Enable subscription */
14842 
14843 /* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */
14844 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14845 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14846 
14847 /* Register: TWIS_EVENTS_STOPPED */
14848 /* Description: TWI stopped */
14849 
14850 /* Bit 0 : TWI stopped */
14851 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
14852 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
14853 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
14854 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
14855 
14856 /* Register: TWIS_EVENTS_ERROR */
14857 /* Description: TWI error */
14858 
14859 /* Bit 0 : TWI error */
14860 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
14861 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
14862 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
14863 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */
14864 
14865 /* Register: TWIS_EVENTS_RXSTARTED */
14866 /* Description: Receive sequence started */
14867 
14868 /* Bit 0 : Receive sequence started */
14869 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
14870 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
14871 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
14872 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */
14873 
14874 /* Register: TWIS_EVENTS_TXSTARTED */
14875 /* Description: Transmit sequence started */
14876 
14877 /* Bit 0 : Transmit sequence started */
14878 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
14879 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
14880 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
14881 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */
14882 
14883 /* Register: TWIS_EVENTS_WRITE */
14884 /* Description: Write command received */
14885 
14886 /* Bit 0 : Write command received */
14887 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
14888 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
14889 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0x0UL) /*!< Event not generated */
14890 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (0x1UL) /*!< Event generated */
14891 
14892 /* Register: TWIS_EVENTS_READ */
14893 /* Description: Read command received */
14894 
14895 /* Bit 0 : Read command received */
14896 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
14897 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
14898 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0x0UL) /*!< Event not generated */
14899 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (0x1UL) /*!< Event generated */
14900 
14901 /* Register: TWIS_PUBLISH_STOPPED */
14902 /* Description: Publish configuration for event STOPPED */
14903 
14904 /* Bit 31 :   */
14905 #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
14906 #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
14907 #define TWIS_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
14908 #define TWIS_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */
14909 
14910 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */
14911 #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14912 #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14913 
14914 /* Register: TWIS_PUBLISH_ERROR */
14915 /* Description: Publish configuration for event ERROR */
14916 
14917 /* Bit 31 :   */
14918 #define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
14919 #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
14920 #define TWIS_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */
14921 #define TWIS_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */
14922 
14923 /* Bits 7..0 : DPPI channel that event ERROR will publish to */
14924 #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14925 #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14926 
14927 /* Register: TWIS_PUBLISH_RXSTARTED */
14928 /* Description: Publish configuration for event RXSTARTED */
14929 
14930 /* Bit 31 :   */
14931 #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
14932 #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
14933 #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
14934 #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
14935 
14936 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
14937 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14938 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14939 
14940 /* Register: TWIS_PUBLISH_TXSTARTED */
14941 /* Description: Publish configuration for event TXSTARTED */
14942 
14943 /* Bit 31 :   */
14944 #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
14945 #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
14946 #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
14947 #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
14948 
14949 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
14950 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14951 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14952 
14953 /* Register: TWIS_PUBLISH_WRITE */
14954 /* Description: Publish configuration for event WRITE */
14955 
14956 /* Bit 31 :   */
14957 #define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */
14958 #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */
14959 #define TWIS_PUBLISH_WRITE_EN_Disabled (0x0UL) /*!< Disable publishing */
14960 #define TWIS_PUBLISH_WRITE_EN_Enabled (0x1UL) /*!< Enable publishing */
14961 
14962 /* Bits 7..0 : DPPI channel that event WRITE will publish to */
14963 #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14964 #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14965 
14966 /* Register: TWIS_PUBLISH_READ */
14967 /* Description: Publish configuration for event READ */
14968 
14969 /* Bit 31 :   */
14970 #define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */
14971 #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */
14972 #define TWIS_PUBLISH_READ_EN_Disabled (0x0UL) /*!< Disable publishing */
14973 #define TWIS_PUBLISH_READ_EN_Enabled (0x1UL) /*!< Enable publishing */
14974 
14975 /* Bits 7..0 : DPPI channel that event READ will publish to */
14976 #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14977 #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14978 
14979 /* Register: TWIS_SHORTS */
14980 /* Description: Shortcuts between local events and tasks */
14981 
14982 /* Bit 14 : Shortcut between event READ and task SUSPEND */
14983 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
14984 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
14985 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
14986 #define TWIS_SHORTS_READ_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */
14987 
14988 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
14989 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
14990 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
14991 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
14992 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */
14993 
14994 /* Register: TWIS_INTEN */
14995 /* Description: Enable or disable interrupt */
14996 
14997 /* Bit 26 : Enable or disable interrupt for event READ */
14998 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
14999 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
15000 #define TWIS_INTEN_READ_Disabled (0x0UL) /*!< Disable */
15001 #define TWIS_INTEN_READ_Enabled (0x1UL) /*!< Enable */
15002 
15003 /* Bit 25 : Enable or disable interrupt for event WRITE */
15004 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
15005 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
15006 #define TWIS_INTEN_WRITE_Disabled (0x0UL) /*!< Disable */
15007 #define TWIS_INTEN_WRITE_Enabled (0x1UL) /*!< Enable */
15008 
15009 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
15010 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15011 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15012 #define TWIS_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */
15013 #define TWIS_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */
15014 
15015 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
15016 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15017 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15018 #define TWIS_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */
15019 #define TWIS_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */
15020 
15021 /* Bit 9 : Enable or disable interrupt for event ERROR */
15022 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15023 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
15024 #define TWIS_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
15025 #define TWIS_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */
15026 
15027 /* Bit 1 : Enable or disable interrupt for event STOPPED */
15028 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15029 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15030 #define TWIS_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
15031 #define TWIS_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
15032 
15033 /* Register: TWIS_INTENSET */
15034 /* Description: Enable interrupt */
15035 
15036 /* Bit 26 : Write '1' to enable interrupt for event READ */
15037 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
15038 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
15039 #define TWIS_INTENSET_READ_Disabled (0x0UL) /*!< Read: Disabled */
15040 #define TWIS_INTENSET_READ_Enabled (0x1UL) /*!< Read: Enabled */
15041 #define TWIS_INTENSET_READ_Set (0x1UL) /*!< Enable */
15042 
15043 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
15044 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
15045 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
15046 #define TWIS_INTENSET_WRITE_Disabled (0x0UL) /*!< Read: Disabled */
15047 #define TWIS_INTENSET_WRITE_Enabled (0x1UL) /*!< Read: Enabled */
15048 #define TWIS_INTENSET_WRITE_Set (0x1UL) /*!< Enable */
15049 
15050 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
15051 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15052 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15053 #define TWIS_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15054 #define TWIS_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15055 #define TWIS_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */
15056 
15057 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
15058 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15059 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15060 #define TWIS_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15061 #define TWIS_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15062 #define TWIS_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */
15063 
15064 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
15065 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15066 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
15067 #define TWIS_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
15068 #define TWIS_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
15069 #define TWIS_INTENSET_ERROR_Set (0x1UL) /*!< Enable */
15070 
15071 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
15072 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15073 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15074 #define TWIS_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
15075 #define TWIS_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
15076 #define TWIS_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
15077 
15078 /* Register: TWIS_INTENCLR */
15079 /* Description: Disable interrupt */
15080 
15081 /* Bit 26 : Write '1' to disable interrupt for event READ */
15082 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
15083 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
15084 #define TWIS_INTENCLR_READ_Disabled (0x0UL) /*!< Read: Disabled */
15085 #define TWIS_INTENCLR_READ_Enabled (0x1UL) /*!< Read: Enabled */
15086 #define TWIS_INTENCLR_READ_Clear (0x1UL) /*!< Disable */
15087 
15088 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
15089 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
15090 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
15091 #define TWIS_INTENCLR_WRITE_Disabled (0x0UL) /*!< Read: Disabled */
15092 #define TWIS_INTENCLR_WRITE_Enabled (0x1UL) /*!< Read: Enabled */
15093 #define TWIS_INTENCLR_WRITE_Clear (0x1UL) /*!< Disable */
15094 
15095 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
15096 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15097 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15098 #define TWIS_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15099 #define TWIS_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15100 #define TWIS_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */
15101 
15102 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
15103 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15104 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15105 #define TWIS_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15106 #define TWIS_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15107 #define TWIS_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */
15108 
15109 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
15110 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15111 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
15112 #define TWIS_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
15113 #define TWIS_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
15114 #define TWIS_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */
15115 
15116 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
15117 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15118 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15119 #define TWIS_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
15120 #define TWIS_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
15121 #define TWIS_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
15122 
15123 /* Register: TWIS_ERRORSRC */
15124 /* Description: Error source */
15125 
15126 /* Bit 3 : TX buffer over-read detected, and prevented */
15127 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
15128 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
15129 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0x0UL) /*!< Error did not occur */
15130 #define TWIS_ERRORSRC_OVERREAD_Detected (0x1UL) /*!< Error occurred */
15131 
15132 /* Bit 2 : NACK sent after receiving a data byte */
15133 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
15134 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
15135 #define TWIS_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */
15136 #define TWIS_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */
15137 
15138 /* Bit 0 : RX buffer overflow detected, and prevented */
15139 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
15140 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
15141 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0x0UL) /*!< Error did not occur */
15142 #define TWIS_ERRORSRC_OVERFLOW_Detected (0x1UL) /*!< Error occurred */
15143 
15144 /* Register: TWIS_MATCH */
15145 /* Description: Status register indicating which address had a match */
15146 
15147 /* Bit 0 : Indication of which address in ADDRESS that matched the incoming address */
15148 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
15149 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
15150 
15151 /* Register: TWIS_ENABLE */
15152 /* Description: Enable TWIS */
15153 
15154 /* Bits 3..0 : Enable or disable TWIS */
15155 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
15156 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
15157 #define TWIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIS */
15158 #define TWIS_ENABLE_ENABLE_Enabled (0x9UL) /*!< Enable TWIS */
15159 
15160 /* Register: TWIS_PSEL_SCL */
15161 /* Description: Pin select for SCL signal */
15162 
15163 /* Bit 31 : Connection */
15164 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15165 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15166 #define TWIS_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */
15167 #define TWIS_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
15168 
15169 /* Bits 4..0 : Pin number */
15170 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
15171 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
15172 
15173 /* Register: TWIS_PSEL_SDA */
15174 /* Description: Pin select for SDA signal */
15175 
15176 /* Bit 31 : Connection */
15177 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15178 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15179 #define TWIS_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */
15180 #define TWIS_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
15181 
15182 /* Bits 4..0 : Pin number */
15183 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
15184 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
15185 
15186 /* Register: TWIS_RXD_PTR */
15187 /* Description: RXD Data pointer */
15188 
15189 /* Bits 31..0 : RXD Data pointer */
15190 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
15191 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
15192 
15193 /* Register: TWIS_RXD_MAXCNT */
15194 /* Description: Maximum number of bytes in RXD buffer */
15195 
15196 /* Bits 12..0 : Maximum number of bytes in RXD buffer */
15197 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
15198 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
15199 
15200 /* Register: TWIS_RXD_AMOUNT */
15201 /* Description: Number of bytes transferred in the last RXD transaction */
15202 
15203 /* Bits 12..0 : Number of bytes transferred in the last RXD transaction */
15204 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
15205 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
15206 
15207 /* Register: TWIS_RXD_LIST */
15208 /* Description: EasyDMA list type */
15209 
15210 /* Bits 1..0 : List type */
15211 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
15212 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
15213 #define TWIS_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
15214 #define TWIS_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
15215 
15216 /* Register: TWIS_TXD_PTR */
15217 /* Description: TXD Data pointer */
15218 
15219 /* Bits 31..0 : TXD Data pointer */
15220 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
15221 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
15222 
15223 /* Register: TWIS_TXD_MAXCNT */
15224 /* Description: Maximum number of bytes in TXD buffer */
15225 
15226 /* Bits 12..0 : Maximum number of bytes in TXD buffer */
15227 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
15228 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
15229 
15230 /* Register: TWIS_TXD_AMOUNT */
15231 /* Description: Number of bytes transferred in the last TXD transaction */
15232 
15233 /* Bits 12..0 : Number of bytes transferred in the last TXD transaction */
15234 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
15235 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
15236 
15237 /* Register: TWIS_TXD_LIST */
15238 /* Description: EasyDMA list type */
15239 
15240 /* Bits 1..0 : List type */
15241 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
15242 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
15243 #define TWIS_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
15244 #define TWIS_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
15245 
15246 /* Register: TWIS_ADDRESS */
15247 /* Description: Description collection: TWI slave address n */
15248 
15249 /* Bits 6..0 : TWI slave address */
15250 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
15251 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
15252 
15253 /* Register: TWIS_CONFIG */
15254 /* Description: Configuration register for the address match mechanism */
15255 
15256 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
15257 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
15258 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
15259 #define TWIS_CONFIG_ADDRESS1_Disabled (0x0UL) /*!< Disabled */
15260 #define TWIS_CONFIG_ADDRESS1_Enabled (0x1UL) /*!< Enabled */
15261 
15262 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
15263 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
15264 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
15265 #define TWIS_CONFIG_ADDRESS0_Disabled (0x0UL) /*!< Disabled */
15266 #define TWIS_CONFIG_ADDRESS0_Enabled (0x1UL) /*!< Enabled */
15267 
15268 /* Register: TWIS_ORC */
15269 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
15270 
15271 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
15272 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
15273 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
15274 
15275 
15276 /* Peripheral: UARTE */
15277 /* Description: UART with EasyDMA 0 */
15278 
15279 /* Register: UARTE_TASKS_STARTRX */
15280 /* Description: Start UART receiver */
15281 
15282 /* Bit 0 : Start UART receiver */
15283 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
15284 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
15285 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */
15286 
15287 /* Register: UARTE_TASKS_STOPRX */
15288 /* Description: Stop UART receiver */
15289 
15290 /* Bit 0 : Stop UART receiver */
15291 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
15292 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
15293 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (0x1UL) /*!< Trigger task */
15294 
15295 /* Register: UARTE_TASKS_STARTTX */
15296 /* Description: Start UART transmitter */
15297 
15298 /* Bit 0 : Start UART transmitter */
15299 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
15300 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
15301 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */
15302 
15303 /* Register: UARTE_TASKS_STOPTX */
15304 /* Description: Stop UART transmitter */
15305 
15306 /* Bit 0 : Stop UART transmitter */
15307 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
15308 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
15309 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (0x1UL) /*!< Trigger task */
15310 
15311 /* Register: UARTE_TASKS_FLUSHRX */
15312 /* Description: Flush RX FIFO into RX buffer */
15313 
15314 /* Bit 0 : Flush RX FIFO into RX buffer */
15315 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
15316 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
15317 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (0x1UL) /*!< Trigger task */
15318 
15319 /* Register: UARTE_SUBSCRIBE_STARTRX */
15320 /* Description: Subscribe configuration for task STARTRX */
15321 
15322 /* Bit 31 :   */
15323 #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
15324 #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
15325 #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0x0UL) /*!< Disable subscription */
15326 #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (0x1UL) /*!< Enable subscription */
15327 
15328 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
15329 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15330 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15331 
15332 /* Register: UARTE_SUBSCRIBE_STOPRX */
15333 /* Description: Subscribe configuration for task STOPRX */
15334 
15335 /* Bit 31 :   */
15336 #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */
15337 #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */
15338 #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0x0UL) /*!< Disable subscription */
15339 #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (0x1UL) /*!< Enable subscription */
15340 
15341 /* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */
15342 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15343 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15344 
15345 /* Register: UARTE_SUBSCRIBE_STARTTX */
15346 /* Description: Subscribe configuration for task STARTTX */
15347 
15348 /* Bit 31 :   */
15349 #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
15350 #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
15351 #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription */
15352 #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription */
15353 
15354 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
15355 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15356 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15357 
15358 /* Register: UARTE_SUBSCRIBE_STOPTX */
15359 /* Description: Subscribe configuration for task STOPTX */
15360 
15361 /* Bit 31 :   */
15362 #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */
15363 #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */
15364 #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0x0UL) /*!< Disable subscription */
15365 #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (0x1UL) /*!< Enable subscription */
15366 
15367 /* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */
15368 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15369 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15370 
15371 /* Register: UARTE_SUBSCRIBE_FLUSHRX */
15372 /* Description: Subscribe configuration for task FLUSHRX */
15373 
15374 /* Bit 31 :   */
15375 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */
15376 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */
15377 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0x0UL) /*!< Disable subscription */
15378 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (0x1UL) /*!< Enable subscription */
15379 
15380 /* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */
15381 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15382 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15383 
15384 /* Register: UARTE_EVENTS_CTS */
15385 /* Description: CTS is activated (set low). Clear To Send. */
15386 
15387 /* Bit 0 : CTS is activated (set low). Clear To Send. */
15388 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
15389 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
15390 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0x0UL) /*!< Event not generated */
15391 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (0x1UL) /*!< Event generated */
15392 
15393 /* Register: UARTE_EVENTS_NCTS */
15394 /* Description: CTS is deactivated (set high). Not Clear To Send. */
15395 
15396 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
15397 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
15398 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
15399 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0x0UL) /*!< Event not generated */
15400 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (0x1UL) /*!< Event generated */
15401 
15402 /* Register: UARTE_EVENTS_RXDRDY */
15403 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
15404 
15405 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
15406 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
15407 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
15408 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0x0UL) /*!< Event not generated */
15409 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (0x1UL) /*!< Event generated */
15410 
15411 /* Register: UARTE_EVENTS_ENDRX */
15412 /* Description: Receive buffer is filled up */
15413 
15414 /* Bit 0 : Receive buffer is filled up */
15415 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
15416 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
15417 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
15418 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */
15419 
15420 /* Register: UARTE_EVENTS_TXDRDY */
15421 /* Description: Data sent from TXD */
15422 
15423 /* Bit 0 : Data sent from TXD */
15424 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
15425 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
15426 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0x0UL) /*!< Event not generated */
15427 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (0x1UL) /*!< Event generated */
15428 
15429 /* Register: UARTE_EVENTS_ENDTX */
15430 /* Description: Last TX byte transmitted */
15431 
15432 /* Bit 0 : Last TX byte transmitted */
15433 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
15434 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
15435 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */
15436 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */
15437 
15438 /* Register: UARTE_EVENTS_ERROR */
15439 /* Description: Error detected */
15440 
15441 /* Bit 0 : Error detected */
15442 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
15443 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
15444 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
15445 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */
15446 
15447 /* Register: UARTE_EVENTS_RXTO */
15448 /* Description: Receiver timeout */
15449 
15450 /* Bit 0 : Receiver timeout */
15451 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
15452 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
15453 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0x0UL) /*!< Event not generated */
15454 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (0x1UL) /*!< Event generated */
15455 
15456 /* Register: UARTE_EVENTS_RXSTARTED */
15457 /* Description: UART receiver has started */
15458 
15459 /* Bit 0 : UART receiver has started */
15460 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
15461 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
15462 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
15463 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */
15464 
15465 /* Register: UARTE_EVENTS_TXSTARTED */
15466 /* Description: UART transmitter has started */
15467 
15468 /* Bit 0 : UART transmitter has started */
15469 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
15470 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
15471 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
15472 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */
15473 
15474 /* Register: UARTE_EVENTS_TXSTOPPED */
15475 /* Description: Transmitter stopped */
15476 
15477 /* Bit 0 : Transmitter stopped */
15478 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
15479 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
15480 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */
15481 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (0x1UL) /*!< Event generated */
15482 
15483 /* Register: UARTE_PUBLISH_CTS */
15484 /* Description: Publish configuration for event CTS */
15485 
15486 /* Bit 31 :   */
15487 #define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */
15488 #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */
15489 #define UARTE_PUBLISH_CTS_EN_Disabled (0x0UL) /*!< Disable publishing */
15490 #define UARTE_PUBLISH_CTS_EN_Enabled (0x1UL) /*!< Enable publishing */
15491 
15492 /* Bits 7..0 : DPPI channel that event CTS will publish to */
15493 #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15494 #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15495 
15496 /* Register: UARTE_PUBLISH_NCTS */
15497 /* Description: Publish configuration for event NCTS */
15498 
15499 /* Bit 31 :   */
15500 #define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */
15501 #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */
15502 #define UARTE_PUBLISH_NCTS_EN_Disabled (0x0UL) /*!< Disable publishing */
15503 #define UARTE_PUBLISH_NCTS_EN_Enabled (0x1UL) /*!< Enable publishing */
15504 
15505 /* Bits 7..0 : DPPI channel that event NCTS will publish to */
15506 #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15507 #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15508 
15509 /* Register: UARTE_PUBLISH_RXDRDY */
15510 /* Description: Publish configuration for event RXDRDY */
15511 
15512 /* Bit 31 :   */
15513 #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
15514 #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */
15515 #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */
15516 #define UARTE_PUBLISH_RXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */
15517 
15518 /* Bits 7..0 : DPPI channel that event RXDRDY will publish to */
15519 #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15520 #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15521 
15522 /* Register: UARTE_PUBLISH_ENDRX */
15523 /* Description: Publish configuration for event ENDRX */
15524 
15525 /* Bit 31 :   */
15526 #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
15527 #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
15528 #define UARTE_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */
15529 #define UARTE_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */
15530 
15531 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */
15532 #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15533 #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15534 
15535 /* Register: UARTE_PUBLISH_TXDRDY */
15536 /* Description: Publish configuration for event TXDRDY */
15537 
15538 /* Bit 31 :   */
15539 #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
15540 #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */
15541 #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */
15542 #define UARTE_PUBLISH_TXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */
15543 
15544 /* Bits 7..0 : DPPI channel that event TXDRDY will publish to */
15545 #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15546 #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15547 
15548 /* Register: UARTE_PUBLISH_ENDTX */
15549 /* Description: Publish configuration for event ENDTX */
15550 
15551 /* Bit 31 :   */
15552 #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
15553 #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
15554 #define UARTE_PUBLISH_ENDTX_EN_Disabled (0x0UL) /*!< Disable publishing */
15555 #define UARTE_PUBLISH_ENDTX_EN_Enabled (0x1UL) /*!< Enable publishing */
15556 
15557 /* Bits 7..0 : DPPI channel that event ENDTX will publish to */
15558 #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15559 #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15560 
15561 /* Register: UARTE_PUBLISH_ERROR */
15562 /* Description: Publish configuration for event ERROR */
15563 
15564 /* Bit 31 :   */
15565 #define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
15566 #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
15567 #define UARTE_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */
15568 #define UARTE_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */
15569 
15570 /* Bits 7..0 : DPPI channel that event ERROR will publish to */
15571 #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15572 #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15573 
15574 /* Register: UARTE_PUBLISH_RXTO */
15575 /* Description: Publish configuration for event RXTO */
15576 
15577 /* Bit 31 :   */
15578 #define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */
15579 #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */
15580 #define UARTE_PUBLISH_RXTO_EN_Disabled (0x0UL) /*!< Disable publishing */
15581 #define UARTE_PUBLISH_RXTO_EN_Enabled (0x1UL) /*!< Enable publishing */
15582 
15583 /* Bits 7..0 : DPPI channel that event RXTO will publish to */
15584 #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15585 #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15586 
15587 /* Register: UARTE_PUBLISH_RXSTARTED */
15588 /* Description: Publish configuration for event RXSTARTED */
15589 
15590 /* Bit 31 :   */
15591 #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
15592 #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
15593 #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
15594 #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
15595 
15596 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
15597 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15598 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15599 
15600 /* Register: UARTE_PUBLISH_TXSTARTED */
15601 /* Description: Publish configuration for event TXSTARTED */
15602 
15603 /* Bit 31 :   */
15604 #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
15605 #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
15606 #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
15607 #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */
15608 
15609 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
15610 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15611 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15612 
15613 /* Register: UARTE_PUBLISH_TXSTOPPED */
15614 /* Description: Publish configuration for event TXSTOPPED */
15615 
15616 /* Bit 31 :   */
15617 #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
15618 #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */
15619 #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
15620 #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */
15621 
15622 /* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to */
15623 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15624 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15625 
15626 /* Register: UARTE_SHORTS */
15627 /* Description: Shortcuts between local events and tasks */
15628 
15629 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
15630 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
15631 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
15632 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0x0UL) /*!< Disable shortcut */
15633 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (0x1UL) /*!< Enable shortcut */
15634 
15635 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
15636 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
15637 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
15638 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */
15639 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */
15640 
15641 /* Register: UARTE_INTEN */
15642 /* Description: Enable or disable interrupt */
15643 
15644 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
15645 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
15646 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
15647 #define UARTE_INTEN_TXSTOPPED_Disabled (0x0UL) /*!< Disable */
15648 #define UARTE_INTEN_TXSTOPPED_Enabled (0x1UL) /*!< Enable */
15649 
15650 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
15651 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15652 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15653 #define UARTE_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */
15654 #define UARTE_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */
15655 
15656 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
15657 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15658 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15659 #define UARTE_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */
15660 #define UARTE_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */
15661 
15662 /* Bit 17 : Enable or disable interrupt for event RXTO */
15663 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15664 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
15665 #define UARTE_INTEN_RXTO_Disabled (0x0UL) /*!< Disable */
15666 #define UARTE_INTEN_RXTO_Enabled (0x1UL) /*!< Enable */
15667 
15668 /* Bit 9 : Enable or disable interrupt for event ERROR */
15669 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15670 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
15671 #define UARTE_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
15672 #define UARTE_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */
15673 
15674 /* Bit 8 : Enable or disable interrupt for event ENDTX */
15675 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
15676 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
15677 #define UARTE_INTEN_ENDTX_Disabled (0x0UL) /*!< Disable */
15678 #define UARTE_INTEN_ENDTX_Enabled (0x1UL) /*!< Enable */
15679 
15680 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
15681 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15682 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15683 #define UARTE_INTEN_TXDRDY_Disabled (0x0UL) /*!< Disable */
15684 #define UARTE_INTEN_TXDRDY_Enabled (0x1UL) /*!< Enable */
15685 
15686 /* Bit 4 : Enable or disable interrupt for event ENDRX */
15687 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
15688 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
15689 #define UARTE_INTEN_ENDRX_Disabled (0x0UL) /*!< Disable */
15690 #define UARTE_INTEN_ENDRX_Enabled (0x1UL) /*!< Enable */
15691 
15692 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
15693 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15694 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15695 #define UARTE_INTEN_RXDRDY_Disabled (0x0UL) /*!< Disable */
15696 #define UARTE_INTEN_RXDRDY_Enabled (0x1UL) /*!< Enable */
15697 
15698 /* Bit 1 : Enable or disable interrupt for event NCTS */
15699 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15700 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
15701 #define UARTE_INTEN_NCTS_Disabled (0x0UL) /*!< Disable */
15702 #define UARTE_INTEN_NCTS_Enabled (0x1UL) /*!< Enable */
15703 
15704 /* Bit 0 : Enable or disable interrupt for event CTS */
15705 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
15706 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
15707 #define UARTE_INTEN_CTS_Disabled (0x0UL) /*!< Disable */
15708 #define UARTE_INTEN_CTS_Enabled (0x1UL) /*!< Enable */
15709 
15710 /* Register: UARTE_INTENSET */
15711 /* Description: Enable interrupt */
15712 
15713 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
15714 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
15715 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
15716 #define UARTE_INTENSET_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
15717 #define UARTE_INTENSET_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
15718 #define UARTE_INTENSET_TXSTOPPED_Set (0x1UL) /*!< Enable */
15719 
15720 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
15721 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15722 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15723 #define UARTE_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15724 #define UARTE_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15725 #define UARTE_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */
15726 
15727 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
15728 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15729 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15730 #define UARTE_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15731 #define UARTE_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15732 #define UARTE_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */
15733 
15734 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
15735 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15736 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
15737 #define UARTE_INTENSET_RXTO_Disabled (0x0UL) /*!< Read: Disabled */
15738 #define UARTE_INTENSET_RXTO_Enabled (0x1UL) /*!< Read: Enabled */
15739 #define UARTE_INTENSET_RXTO_Set (0x1UL) /*!< Enable */
15740 
15741 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
15742 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15743 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
15744 #define UARTE_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
15745 #define UARTE_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
15746 #define UARTE_INTENSET_ERROR_Set (0x1UL) /*!< Enable */
15747 
15748 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
15749 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
15750 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
15751 #define UARTE_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
15752 #define UARTE_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
15753 #define UARTE_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */
15754 
15755 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
15756 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15757 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15758 #define UARTE_INTENSET_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
15759 #define UARTE_INTENSET_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
15760 #define UARTE_INTENSET_TXDRDY_Set (0x1UL) /*!< Enable */
15761 
15762 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
15763 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
15764 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
15765 #define UARTE_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
15766 #define UARTE_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
15767 #define UARTE_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */
15768 
15769 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
15770 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15771 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15772 #define UARTE_INTENSET_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
15773 #define UARTE_INTENSET_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
15774 #define UARTE_INTENSET_RXDRDY_Set (0x1UL) /*!< Enable */
15775 
15776 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
15777 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15778 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
15779 #define UARTE_INTENSET_NCTS_Disabled (0x0UL) /*!< Read: Disabled */
15780 #define UARTE_INTENSET_NCTS_Enabled (0x1UL) /*!< Read: Enabled */
15781 #define UARTE_INTENSET_NCTS_Set (0x1UL) /*!< Enable */
15782 
15783 /* Bit 0 : Write '1' to enable interrupt for event CTS */
15784 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
15785 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
15786 #define UARTE_INTENSET_CTS_Disabled (0x0UL) /*!< Read: Disabled */
15787 #define UARTE_INTENSET_CTS_Enabled (0x1UL) /*!< Read: Enabled */
15788 #define UARTE_INTENSET_CTS_Set (0x1UL) /*!< Enable */
15789 
15790 /* Register: UARTE_INTENCLR */
15791 /* Description: Disable interrupt */
15792 
15793 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
15794 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
15795 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
15796 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
15797 #define UARTE_INTENCLR_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
15798 #define UARTE_INTENCLR_TXSTOPPED_Clear (0x1UL) /*!< Disable */
15799 
15800 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
15801 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15802 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15803 #define UARTE_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15804 #define UARTE_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15805 #define UARTE_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */
15806 
15807 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
15808 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15809 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15810 #define UARTE_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15811 #define UARTE_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15812 #define UARTE_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */
15813 
15814 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
15815 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15816 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
15817 #define UARTE_INTENCLR_RXTO_Disabled (0x0UL) /*!< Read: Disabled */
15818 #define UARTE_INTENCLR_RXTO_Enabled (0x1UL) /*!< Read: Enabled */
15819 #define UARTE_INTENCLR_RXTO_Clear (0x1UL) /*!< Disable */
15820 
15821 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
15822 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15823 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
15824 #define UARTE_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
15825 #define UARTE_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
15826 #define UARTE_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */
15827 
15828 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
15829 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
15830 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
15831 #define UARTE_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
15832 #define UARTE_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
15833 #define UARTE_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */
15834 
15835 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
15836 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15837 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15838 #define UARTE_INTENCLR_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
15839 #define UARTE_INTENCLR_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
15840 #define UARTE_INTENCLR_TXDRDY_Clear (0x1UL) /*!< Disable */
15841 
15842 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
15843 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
15844 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
15845 #define UARTE_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
15846 #define UARTE_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
15847 #define UARTE_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */
15848 
15849 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
15850 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15851 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15852 #define UARTE_INTENCLR_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
15853 #define UARTE_INTENCLR_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
15854 #define UARTE_INTENCLR_RXDRDY_Clear (0x1UL) /*!< Disable */
15855 
15856 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
15857 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15858 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
15859 #define UARTE_INTENCLR_NCTS_Disabled (0x0UL) /*!< Read: Disabled */
15860 #define UARTE_INTENCLR_NCTS_Enabled (0x1UL) /*!< Read: Enabled */
15861 #define UARTE_INTENCLR_NCTS_Clear (0x1UL) /*!< Disable */
15862 
15863 /* Bit 0 : Write '1' to disable interrupt for event CTS */
15864 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
15865 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
15866 #define UARTE_INTENCLR_CTS_Disabled (0x0UL) /*!< Read: Disabled */
15867 #define UARTE_INTENCLR_CTS_Enabled (0x1UL) /*!< Read: Enabled */
15868 #define UARTE_INTENCLR_CTS_Clear (0x1UL) /*!< Disable */
15869 
15870 /* Register: UARTE_ERRORSRC */
15871 /* Description: Error source This register is read/write one to clear. */
15872 
15873 /* Bit 3 : Break condition */
15874 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
15875 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
15876 #define UARTE_ERRORSRC_BREAK_NotPresent (0x0UL) /*!< Read: error not present */
15877 #define UARTE_ERRORSRC_BREAK_Present (0x1UL) /*!< Read: error present */
15878 
15879 /* Bit 2 : Framing error occurred */
15880 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
15881 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
15882 #define UARTE_ERRORSRC_FRAMING_NotPresent (0x0UL) /*!< Read: error not present */
15883 #define UARTE_ERRORSRC_FRAMING_Present (0x1UL) /*!< Read: error present */
15884 
15885 /* Bit 1 : Parity error */
15886 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
15887 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
15888 #define UARTE_ERRORSRC_PARITY_NotPresent (0x0UL) /*!< Read: error not present */
15889 #define UARTE_ERRORSRC_PARITY_Present (0x1UL) /*!< Read: error present */
15890 
15891 /* Bit 0 : Overrun error */
15892 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
15893 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
15894 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0x0UL) /*!< Read: error not present */
15895 #define UARTE_ERRORSRC_OVERRUN_Present (0x1UL) /*!< Read: error present */
15896 
15897 /* Register: UARTE_ENABLE */
15898 /* Description: Enable UART */
15899 
15900 /* Bits 3..0 : Enable or disable UARTE */
15901 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
15902 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
15903 #define UARTE_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable UARTE */
15904 #define UARTE_ENABLE_ENABLE_Enabled (0x8UL) /*!< Enable UARTE */
15905 
15906 /* Register: UARTE_PSEL_RTS */
15907 /* Description: Pin select for RTS signal */
15908 
15909 /* Bit 31 : Connection */
15910 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15911 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15912 #define UARTE_PSEL_RTS_CONNECT_Connected (0x0UL) /*!< Connect */
15913 #define UARTE_PSEL_RTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
15914 
15915 /* Bits 4..0 : Pin number */
15916 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
15917 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
15918 
15919 /* Register: UARTE_PSEL_TXD */
15920 /* Description: Pin select for TXD signal */
15921 
15922 /* Bit 31 : Connection */
15923 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15924 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15925 #define UARTE_PSEL_TXD_CONNECT_Connected (0x0UL) /*!< Connect */
15926 #define UARTE_PSEL_TXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
15927 
15928 /* Bits 4..0 : Pin number */
15929 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
15930 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
15931 
15932 /* Register: UARTE_PSEL_CTS */
15933 /* Description: Pin select for CTS signal */
15934 
15935 /* Bit 31 : Connection */
15936 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15937 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15938 #define UARTE_PSEL_CTS_CONNECT_Connected (0x0UL) /*!< Connect */
15939 #define UARTE_PSEL_CTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
15940 
15941 /* Bits 4..0 : Pin number */
15942 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
15943 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
15944 
15945 /* Register: UARTE_PSEL_RXD */
15946 /* Description: Pin select for RXD signal */
15947 
15948 /* Bit 31 : Connection */
15949 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15950 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15951 #define UARTE_PSEL_RXD_CONNECT_Connected (0x0UL) /*!< Connect */
15952 #define UARTE_PSEL_RXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
15953 
15954 /* Bits 4..0 : Pin number */
15955 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
15956 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
15957 
15958 /* Register: UARTE_BAUDRATE */
15959 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
15960 
15961 /* Bits 31..0 : Baud rate */
15962 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
15963 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
15964 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
15965 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
15966 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
15967 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
15968 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
15969 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
15970 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
15971 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
15972 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
15973 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
15974 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
15975 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
15976 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
15977 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
15978 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
15979 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
15980 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
15981 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
15982 
15983 /* Register: UARTE_RXD_PTR */
15984 /* Description: Data pointer */
15985 
15986 /* Bits 31..0 : Data pointer */
15987 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
15988 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
15989 
15990 /* Register: UARTE_RXD_MAXCNT */
15991 /* Description: Maximum number of bytes in receive buffer */
15992 
15993 /* Bits 12..0 : Maximum number of bytes in receive buffer */
15994 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
15995 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
15996 
15997 /* Register: UARTE_RXD_AMOUNT */
15998 /* Description: Number of bytes transferred in the last transaction */
15999 
16000 /* Bits 12..0 : Number of bytes transferred in the last transaction */
16001 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16002 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16003 
16004 /* Register: UARTE_TXD_PTR */
16005 /* Description: Data pointer */
16006 
16007 /* Bits 31..0 : Data pointer */
16008 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16009 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16010 
16011 /* Register: UARTE_TXD_MAXCNT */
16012 /* Description: Maximum number of bytes in transmit buffer */
16013 
16014 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
16015 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16016 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16017 
16018 /* Register: UARTE_TXD_AMOUNT */
16019 /* Description: Number of bytes transferred in the last transaction */
16020 
16021 /* Bits 12..0 : Number of bytes transferred in the last transaction */
16022 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16023 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16024 
16025 /* Register: UARTE_CONFIG */
16026 /* Description: Configuration of parity and hardware flow control */
16027 
16028 /* Bit 4 : Stop bits */
16029 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
16030 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
16031 #define UARTE_CONFIG_STOP_One (0x0UL) /*!< One stop bit */
16032 #define UARTE_CONFIG_STOP_Two (0x1UL) /*!< Two stop bits */
16033 
16034 /* Bits 3..1 : Parity */
16035 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
16036 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
16037 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
16038 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
16039 
16040 /* Bit 0 : Hardware flow control */
16041 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
16042 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
16043 #define UARTE_CONFIG_HWFC_Disabled (0x0UL) /*!< Disabled */
16044 #define UARTE_CONFIG_HWFC_Enabled (0x1UL) /*!< Enabled */
16045 
16046 
16047 /* Peripheral: UICR */
16048 /* Description: User information configuration registers User information configuration registers */
16049 
16050 /* Register: UICR_APPROTECT */
16051 /* Description: Access port protection */
16052 
16053 /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and
16054           memory mapped addresses */
16055 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
16056 #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
16057 #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
16058 #define UICR_APPROTECT_PALL_HwUnprotected (0x50FA50FAUL) /*!< HwUnprotected */
16059 
16060 /* Register: UICR_XOSC32M */
16061 /* Description: Oscillator control */
16062 
16063 /* Bits 5..0 : Pierce current DAC control signals */
16064 #define UICR_XOSC32M_CTRL_Pos (0UL) /*!< Position of CTRL field. */
16065 #define UICR_XOSC32M_CTRL_Msk (0x3FUL << UICR_XOSC32M_CTRL_Pos) /*!< Bit mask of CTRL field. */
16066 
16067 /* Register: UICR_HFXOSRC */
16068 /* Description: HFXO clock source selection */
16069 
16070 /* Bit 0 : HFXO clock source selection */
16071 #define UICR_HFXOSRC_HFXOSRC_Pos (0UL) /*!< Position of HFXOSRC field. */
16072 #define UICR_HFXOSRC_HFXOSRC_Msk (0x1UL << UICR_HFXOSRC_HFXOSRC_Pos) /*!< Bit mask of HFXOSRC field. */
16073 #define UICR_HFXOSRC_HFXOSRC_TCXO (0x0UL) /*!< 32 MHz temperature compensated crystal oscillator (TCXO) */
16074 #define UICR_HFXOSRC_HFXOSRC_XTAL (0x1UL) /*!< 32 MHz crystal oscillator */
16075 
16076 /* Register: UICR_HFXOCNT */
16077 /* Description: HFXO startup counter */
16078 
16079 /* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */
16080 #define UICR_HFXOCNT_HFXOCNT_Pos (0UL) /*!< Position of HFXOCNT field. */
16081 #define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos) /*!< Bit mask of HFXOCNT field. */
16082 #define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0x00UL) /*!< Min debounce time = (0*64 us + 0.5 us) */
16083 #define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (0xFFUL) /*!< Max debounce time = (255*64 us + 0.5 us) */
16084 
16085 /* Register: UICR_APPNVMCPOFGUARD */
16086 /* Description: Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition. */
16087 
16088 /* Bit 0 : Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition */
16089 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos (0UL) /*!< Position of NVMCPOFGUARDEN field. */
16090 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Msk (0x1UL << UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos) /*!< Bit mask of NVMCPOFGUARDEN field. */
16091 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Disabled (0x0UL) /*!< NVM WRITE and NVM ERASE are not blocked in POFWARN condition */
16092 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Enabled (0x1UL) /*!< NVM WRITE and NVM ERASE are blocked in POFWARN condition */
16093 
16094 /* Register: UICR_PMICCONF */
16095 /* Description: Polarity of PMIC polarity configuration signals. */
16096 
16097 /* Bit 0 : Polarity of PMIC_FPWM signal. */
16098 #define UICR_PMICCONF_PMICFPWMPOL_Pos (0UL) /*!< Position of PMICFPWMPOL field. */
16099 #define UICR_PMICCONF_PMICFPWMPOL_Msk (0x1UL << UICR_PMICCONF_PMICFPWMPOL_Pos) /*!< Bit mask of PMICFPWMPOL field. */
16100 #define UICR_PMICCONF_PMICFPWMPOL_ActiveLow (0x0UL) /*!< PMIC_FPWM output signal is active-low */
16101 #define UICR_PMICCONF_PMICFPWMPOL_ActiveHigh (0x1UL) /*!< PMIC_FPWM output signal is active-high */
16102 
16103 /* Register: UICR_SECUREAPPROTECT */
16104 /* Description: Secure access port protection */
16105 
16106 /* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure
16107           memory mapped addresses */
16108 #define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
16109 #define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
16110 #define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
16111 #define UICR_SECUREAPPROTECT_PALL_HwUnprotected (0x50FA50FAUL) /*!< HwUnprotected */
16112 
16113 /* Register: UICR_ERASEPROTECT */
16114 /* Description: Erase protection */
16115 
16116 /* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality */
16117 #define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
16118 #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
16119 #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
16120 #define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
16121 
16122 /* Register: UICR_OTP */
16123 /* Description: Description collection: One time programmable memory */
16124 
16125 /* Bits 31..16 : Upper half word */
16126 #define UICR_OTP_UPPER_Pos (16UL) /*!< Position of UPPER field. */
16127 #define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos) /*!< Bit mask of UPPER field. */
16128 
16129 /* Bits 15..0 : Lower half word */
16130 #define UICR_OTP_LOWER_Pos (0UL) /*!< Position of LOWER field. */
16131 #define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos) /*!< Bit mask of LOWER field. */
16132 
16133 /* Register: UICR_KEYSLOT_CONFIG_DEST */
16134 /* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3])
16135           will be pushed by KMU. Note that this address must match that of a peripheral's
16136           APB mapped write-only key registers, otherwise the KMU can push this key value into
16137           an address range which the CPU can potentially read. */
16138 
16139 /* Bits 31..0 : Secure APB destination address */
16140 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */
16141 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos) /*!< Bit mask of DEST field. */
16142 
16143 /* Register: UICR_KEYSLOT_CONFIG_PERM */
16144 /* Description: Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. */
16145 
16146 /* Bit 16 : Revocation state for the key slot */
16147 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */
16148 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos) /*!< Bit mask of STATE field. */
16149 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0x0UL) /*!< Key value registers can no longer be read or pushed */
16150 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (0x1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */
16151 
16152 /* Bit 2 : Push permission for key slot */
16153 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */
16154 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos) /*!< Bit mask of PUSH field. */
16155 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0x0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */
16156 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (0x1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */
16157 
16158 /* Bit 1 : Read permission for key slot */
16159 #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */
16160 #define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */
16161 #define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0x0UL) /*!< Disable read from key value registers */
16162 #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (0x1UL) /*!< Enable read from key value registers */
16163 
16164 /* Bit 0 : Write permission for key slot */
16165 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL) /*!< Position of WRITE field. */
16166 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
16167 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0x0UL) /*!< Disable write to the key value registers */
16168 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (0x1UL) /*!< Enable write to the key value registers */
16169 
16170 /* Register: UICR_KEYSLOT_KEY_VALUE */
16171 /* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */
16172 
16173 /* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot */
16174 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
16175 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
16176 
16177 
16178 /* Peripheral: VMC */
16179 /* Description: Volatile Memory controller 0 */
16180 
16181 /* Register: VMC_RAM_POWER */
16182 /* Description: Description cluster: RAMn power control register */
16183 
16184 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
16185 #define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
16186 #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
16187 #define VMC_RAM_POWER_S3RETENTION_Off (0x0UL) /*!< Off */
16188 #define VMC_RAM_POWER_S3RETENTION_On (0x1UL) /*!< On */
16189 
16190 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
16191 #define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
16192 #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
16193 #define VMC_RAM_POWER_S2RETENTION_Off (0x0UL) /*!< Off */
16194 #define VMC_RAM_POWER_S2RETENTION_On (0x1UL) /*!< On */
16195 
16196 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
16197 #define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
16198 #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
16199 #define VMC_RAM_POWER_S1RETENTION_Off (0x0UL) /*!< Off */
16200 #define VMC_RAM_POWER_S1RETENTION_On (0x1UL) /*!< On */
16201 
16202 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
16203 #define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
16204 #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
16205 #define VMC_RAM_POWER_S0RETENTION_Off (0x0UL) /*!< Off */
16206 #define VMC_RAM_POWER_S0RETENTION_On (0x1UL) /*!< On */
16207 
16208 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
16209 #define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
16210 #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
16211 #define VMC_RAM_POWER_S3POWER_Off (0x0UL) /*!< Off */
16212 #define VMC_RAM_POWER_S3POWER_On (0x1UL) /*!< On */
16213 
16214 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
16215 #define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
16216 #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
16217 #define VMC_RAM_POWER_S2POWER_Off (0x0UL) /*!< Off */
16218 #define VMC_RAM_POWER_S2POWER_On (0x1UL) /*!< On */
16219 
16220 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
16221 #define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
16222 #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
16223 #define VMC_RAM_POWER_S1POWER_Off (0x0UL) /*!< Off */
16224 #define VMC_RAM_POWER_S1POWER_On (0x1UL) /*!< On */
16225 
16226 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
16227 #define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
16228 #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
16229 #define VMC_RAM_POWER_S0POWER_Off (0x0UL) /*!< Off */
16230 #define VMC_RAM_POWER_S0POWER_On (0x1UL) /*!< On */
16231 
16232 /* Register: VMC_RAM_POWERSET */
16233 /* Description: Description cluster: RAMn power control set register */
16234 
16235 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
16236 #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
16237 #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
16238 #define VMC_RAM_POWERSET_S3RETENTION_On (0x1UL) /*!< On */
16239 
16240 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
16241 #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
16242 #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
16243 #define VMC_RAM_POWERSET_S2RETENTION_On (0x1UL) /*!< On */
16244 
16245 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
16246 #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
16247 #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
16248 #define VMC_RAM_POWERSET_S1RETENTION_On (0x1UL) /*!< On */
16249 
16250 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
16251 #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
16252 #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
16253 #define VMC_RAM_POWERSET_S0RETENTION_On (0x1UL) /*!< On */
16254 
16255 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
16256 #define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
16257 #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
16258 #define VMC_RAM_POWERSET_S3POWER_On (0x1UL) /*!< On */
16259 
16260 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
16261 #define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
16262 #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
16263 #define VMC_RAM_POWERSET_S2POWER_On (0x1UL) /*!< On */
16264 
16265 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
16266 #define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
16267 #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
16268 #define VMC_RAM_POWERSET_S1POWER_On (0x1UL) /*!< On */
16269 
16270 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
16271 #define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
16272 #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
16273 #define VMC_RAM_POWERSET_S0POWER_On (0x1UL) /*!< On */
16274 
16275 /* Register: VMC_RAM_POWERCLR */
16276 /* Description: Description cluster: RAMn power control clear register */
16277 
16278 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
16279 #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
16280 #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
16281 #define VMC_RAM_POWERCLR_S3RETENTION_Off (0x1UL) /*!< Off */
16282 
16283 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
16284 #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
16285 #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
16286 #define VMC_RAM_POWERCLR_S2RETENTION_Off (0x1UL) /*!< Off */
16287 
16288 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
16289 #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
16290 #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
16291 #define VMC_RAM_POWERCLR_S1RETENTION_Off (0x1UL) /*!< Off */
16292 
16293 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
16294 #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
16295 #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
16296 #define VMC_RAM_POWERCLR_S0RETENTION_Off (0x1UL) /*!< Off */
16297 
16298 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
16299 #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
16300 #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
16301 #define VMC_RAM_POWERCLR_S3POWER_Off (0x1UL) /*!< Off */
16302 
16303 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
16304 #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
16305 #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
16306 #define VMC_RAM_POWERCLR_S2POWER_Off (0x1UL) /*!< Off */
16307 
16308 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
16309 #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
16310 #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
16311 #define VMC_RAM_POWERCLR_S1POWER_Off (0x1UL) /*!< Off */
16312 
16313 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
16314 #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
16315 #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
16316 #define VMC_RAM_POWERCLR_S0POWER_Off (0x1UL) /*!< Off */
16317 
16318 
16319 /* Peripheral: WDT */
16320 /* Description: Watchdog Timer 0 */
16321 
16322 /* Register: WDT_TASKS_START */
16323 /* Description: Start the watchdog */
16324 
16325 /* Bit 0 : Start the watchdog */
16326 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
16327 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
16328 #define WDT_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
16329 
16330 /* Register: WDT_SUBSCRIBE_START */
16331 /* Description: Subscribe configuration for task START */
16332 
16333 /* Bit 31 :   */
16334 #define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
16335 #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
16336 #define WDT_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
16337 #define WDT_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */
16338 
16339 /* Bits 7..0 : DPPI channel that task START will subscribe to */
16340 #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16341 #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16342 
16343 /* Register: WDT_EVENTS_TIMEOUT */
16344 /* Description: Watchdog timeout */
16345 
16346 /* Bit 0 : Watchdog timeout */
16347 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
16348 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
16349 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0x0UL) /*!< Event not generated */
16350 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (0x1UL) /*!< Event generated */
16351 
16352 /* Register: WDT_PUBLISH_TIMEOUT */
16353 /* Description: Publish configuration for event TIMEOUT */
16354 
16355 /* Bit 31 :   */
16356 #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */
16357 #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */
16358 #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0x0UL) /*!< Disable publishing */
16359 #define WDT_PUBLISH_TIMEOUT_EN_Enabled (0x1UL) /*!< Enable publishing */
16360 
16361 /* Bits 7..0 : DPPI channel that event TIMEOUT will publish to */
16362 #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16363 #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16364 
16365 /* Register: WDT_INTENSET */
16366 /* Description: Enable interrupt */
16367 
16368 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
16369 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
16370 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
16371 #define WDT_INTENSET_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */
16372 #define WDT_INTENSET_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */
16373 #define WDT_INTENSET_TIMEOUT_Set (0x1UL) /*!< Enable */
16374 
16375 /* Register: WDT_INTENCLR */
16376 /* Description: Disable interrupt */
16377 
16378 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
16379 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
16380 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
16381 #define WDT_INTENCLR_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */
16382 #define WDT_INTENCLR_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */
16383 #define WDT_INTENCLR_TIMEOUT_Clear (0x1UL) /*!< Disable */
16384 
16385 /* Register: WDT_RUNSTATUS */
16386 /* Description: Run status */
16387 
16388 /* Bit 0 : Indicates whether or not the watchdog is running */
16389 #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */
16390 #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */
16391 #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0x0UL) /*!< Watchdog not running */
16392 #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (0x1UL) /*!< Watchdog is running */
16393 
16394 /* Register: WDT_REQSTATUS */
16395 /* Description: Request status */
16396 
16397 /* Bit 7 : Request status for RR[7] register */
16398 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
16399 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
16400 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0x0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
16401 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (0x1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
16402 
16403 /* Bit 6 : Request status for RR[6] register */
16404 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
16405 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
16406 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0x0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
16407 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (0x1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
16408 
16409 /* Bit 5 : Request status for RR[5] register */
16410 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
16411 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
16412 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0x0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
16413 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (0x1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
16414 
16415 /* Bit 4 : Request status for RR[4] register */
16416 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
16417 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
16418 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0x0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
16419 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (0x1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
16420 
16421 /* Bit 3 : Request status for RR[3] register */
16422 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
16423 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
16424 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0x0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
16425 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (0x1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
16426 
16427 /* Bit 2 : Request status for RR[2] register */
16428 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
16429 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
16430 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0x0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
16431 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (0x1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
16432 
16433 /* Bit 1 : Request status for RR[1] register */
16434 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
16435 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
16436 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0x0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
16437 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (0x1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
16438 
16439 /* Bit 0 : Request status for RR[0] register */
16440 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
16441 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
16442 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0x0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
16443 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (0x1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
16444 
16445 /* Register: WDT_CRV */
16446 /* Description: Counter reload value */
16447 
16448 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
16449 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
16450 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
16451 
16452 /* Register: WDT_RREN */
16453 /* Description: Enable register for reload request registers */
16454 
16455 /* Bit 7 : Enable or disable RR[7] register */
16456 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
16457 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
16458 #define WDT_RREN_RR7_Disabled (0x0UL) /*!< Disable RR[7] register */
16459 #define WDT_RREN_RR7_Enabled (0x1UL) /*!< Enable RR[7] register */
16460 
16461 /* Bit 6 : Enable or disable RR[6] register */
16462 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
16463 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
16464 #define WDT_RREN_RR6_Disabled (0x0UL) /*!< Disable RR[6] register */
16465 #define WDT_RREN_RR6_Enabled (0x1UL) /*!< Enable RR[6] register */
16466 
16467 /* Bit 5 : Enable or disable RR[5] register */
16468 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
16469 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
16470 #define WDT_RREN_RR5_Disabled (0x0UL) /*!< Disable RR[5] register */
16471 #define WDT_RREN_RR5_Enabled (0x1UL) /*!< Enable RR[5] register */
16472 
16473 /* Bit 4 : Enable or disable RR[4] register */
16474 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
16475 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
16476 #define WDT_RREN_RR4_Disabled (0x0UL) /*!< Disable RR[4] register */
16477 #define WDT_RREN_RR4_Enabled (0x1UL) /*!< Enable RR[4] register */
16478 
16479 /* Bit 3 : Enable or disable RR[3] register */
16480 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
16481 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
16482 #define WDT_RREN_RR3_Disabled (0x0UL) /*!< Disable RR[3] register */
16483 #define WDT_RREN_RR3_Enabled (0x1UL) /*!< Enable RR[3] register */
16484 
16485 /* Bit 2 : Enable or disable RR[2] register */
16486 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
16487 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
16488 #define WDT_RREN_RR2_Disabled (0x0UL) /*!< Disable RR[2] register */
16489 #define WDT_RREN_RR2_Enabled (0x1UL) /*!< Enable RR[2] register */
16490 
16491 /* Bit 1 : Enable or disable RR[1] register */
16492 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
16493 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
16494 #define WDT_RREN_RR1_Disabled (0x0UL) /*!< Disable RR[1] register */
16495 #define WDT_RREN_RR1_Enabled (0x1UL) /*!< Enable RR[1] register */
16496 
16497 /* Bit 0 : Enable or disable RR[0] register */
16498 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
16499 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
16500 #define WDT_RREN_RR0_Disabled (0x0UL) /*!< Disable RR[0] register */
16501 #define WDT_RREN_RR0_Enabled (0x1UL) /*!< Enable RR[0] register */
16502 
16503 /* Register: WDT_CONFIG */
16504 /* Description: Configuration register */
16505 
16506 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
16507 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
16508 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
16509 #define WDT_CONFIG_HALT_Pause (0x0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
16510 #define WDT_CONFIG_HALT_Run (0x1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
16511 
16512 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
16513 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
16514 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
16515 #define WDT_CONFIG_SLEEP_Pause (0x0UL) /*!< Pause watchdog while the CPU is sleeping */
16516 #define WDT_CONFIG_SLEEP_Run (0x1UL) /*!< Keep the watchdog running while the CPU is sleeping */
16517 
16518 /* Register: WDT_RR */
16519 /* Description: Description collection: Reload request n */
16520 
16521 /* Bits 31..0 : Reload request register */
16522 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
16523 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
16524 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
16525 
16526 
16527 /*lint --flb "Leave library region" */
16528 #endif
16529