1 /* 2 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 3 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, this 10 list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its 17 contributors may be used to endorse or promote products derived from this 18 software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 * 32 * @file nrf9120.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 07. January 2025 36 * @note Generated by SVDConv V3.3.35 on Tuesday, 07.01.2025 15:34:29 37 * from File 'nrf9120.svd', 38 * last modified on Friday, 13.12.2024 08:41:27 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf9120 49 * @{ 50 */ 51 52 53 #ifndef NRF9120_H 54 #define NRF9120_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 82 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 83 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 84 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 85 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 86 /* ========================================== nrf9120 Specific Interrupt Numbers =========================================== */ 87 SPU_IRQn = 3, /*!< 3 SPU */ 88 CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 89 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 8, /*!< 8 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */ 90 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn= 9, /*!< 9 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 */ 91 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn= 10, /*!< 10 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 */ 92 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn= 11, /*!< 11 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 */ 93 GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ 94 SAADC_IRQn = 14, /*!< 14 SAADC */ 95 TIMER0_IRQn = 15, /*!< 15 TIMER0 */ 96 TIMER1_IRQn = 16, /*!< 16 TIMER1 */ 97 TIMER2_IRQn = 17, /*!< 17 TIMER2 */ 98 RTC0_IRQn = 20, /*!< 20 RTC0 */ 99 RTC1_IRQn = 21, /*!< 21 RTC1 */ 100 WDT_IRQn = 24, /*!< 24 WDT */ 101 EGU0_IRQn = 27, /*!< 27 EGU0 */ 102 EGU1_IRQn = 28, /*!< 28 EGU1 */ 103 EGU2_IRQn = 29, /*!< 29 EGU2 */ 104 EGU3_IRQn = 30, /*!< 30 EGU3 */ 105 EGU4_IRQn = 31, /*!< 31 EGU4 */ 106 EGU5_IRQn = 32, /*!< 32 EGU5 */ 107 PWM0_IRQn = 33, /*!< 33 PWM0 */ 108 PWM1_IRQn = 34, /*!< 34 PWM1 */ 109 PWM2_IRQn = 35, /*!< 35 PWM2 */ 110 PWM3_IRQn = 36, /*!< 36 PWM3 */ 111 PDM_IRQn = 38, /*!< 38 PDM */ 112 I2S_IRQn = 40, /*!< 40 I2S */ 113 IPC_IRQn = 42, /*!< 42 IPC */ 114 FPU_IRQn = 44, /*!< 44 FPU */ 115 GPIOTE1_IRQn = 49, /*!< 49 GPIOTE1 */ 116 KMU_IRQn = 57, /*!< 57 KMU */ 117 CRYPTOCELL_IRQn = 64 /*!< 64 CRYPTOCELL */ 118 } IRQn_Type; 119 120 121 122 /* =========================================================================================================================== */ 123 /* ================ Processor and Core Peripheral Section ================ */ 124 /* =========================================================================================================================== */ 125 126 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 127 #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 128 #define __INTERRUPTS_MAX 240 /*!< Top interrupt number */ 129 #define __DSP_PRESENT 1 /*!< DSP present or not */ 130 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 131 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 132 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 133 #define __MPU_PRESENT 1 /*!< MPU present */ 134 #define __FPU_PRESENT 1 /*!< FPU present */ 135 #define __FPU_DP 0 /*!< Double Precision FPU */ 136 #define __SAUREGION_PRESENT 0 /*!< SAU region present */ 137 138 139 /** @} */ /* End of group Configuration_of_CMSIS */ 140 141 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 142 #include "system_nrf9120.h" /*!< nrf9120 System */ 143 144 #ifndef __IM /*!< Fallback for older CMSIS versions */ 145 #define __IM __I 146 #endif 147 #ifndef __OM /*!< Fallback for older CMSIS versions */ 148 #define __OM __O 149 #endif 150 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 151 #define __IOM __IO 152 #endif 153 154 155 /* ======================================== Start of section using anonymous unions ======================================== */ 156 #if defined (__CC_ARM) 157 #pragma push 158 #pragma anon_unions 159 #elif defined (__ICCARM__) 160 #pragma language=extended 161 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 162 #pragma clang diagnostic push 163 #pragma clang diagnostic ignored "-Wc11-extensions" 164 #pragma clang diagnostic ignored "-Wreserved-id-macro" 165 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 166 #pragma clang diagnostic ignored "-Wnested-anon-types" 167 #elif defined (__GNUC__) 168 /* anonymous unions are enabled by default */ 169 #elif defined (__TMS470__) 170 /* anonymous unions are enabled by default */ 171 #elif defined (__TASKING__) 172 #pragma warning 586 173 #elif defined (__CSMC__) 174 /* anonymous unions are enabled by default */ 175 #else 176 #warning Not supported compiler type 177 #endif 178 179 180 /* =========================================================================================================================== */ 181 /* ================ Device Specific Cluster Section ================ */ 182 /* =========================================================================================================================== */ 183 184 185 /** @addtogroup Device_Peripheral_clusters 186 * @{ 187 */ 188 189 190 /** 191 * @brief FICR_INFO [INFO] (Device info) 192 */ 193 typedef struct { 194 __IM uint32_t RESERVED; 195 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 196 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 197 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 198 configuration */ 199 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 200 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 201 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 202 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */ 203 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 204 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 205 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 206 207 208 /** 209 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 210 */ 211 typedef struct { 212 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 213 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 214 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 215 216 217 /** 218 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 219 */ 220 typedef struct { 221 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 222 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 223 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 224 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 225 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator configuration 226 1 */ 227 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator configuration 228 2 */ 229 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator configuration 230 3 */ 231 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator configuration 232 4 */ 233 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 234 235 236 /** 237 * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified) 238 */ 239 typedef struct { 240 __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where 241 content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 242 ) will be pushed by KMU. Note that this 243 address must match that of a peripheral's 244 APB mapped write-only key registers, otherwise 245 the KMU can push this key value into an 246 address range which the CPU can potentially 247 read. */ 248 __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the 249 key slot. Bits 0-15 and 16-31 can only be 250 written when equal to 0xFFFF. */ 251 } UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */ 252 253 254 /** 255 * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified) 256 */ 257 typedef struct { 258 __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32] 259 of value assigned to KMU key slot. */ 260 } UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */ 261 262 263 /** 264 * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified) 265 */ 266 typedef struct { 267 __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */ 268 __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */ 269 } UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */ 270 271 272 /** 273 * @brief TAD_PSEL [PSEL] (Unspecified) 274 */ 275 typedef struct { 276 __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */ 277 __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */ 278 __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */ 279 __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */ 280 __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */ 281 } TAD_PSEL_Type; /*!< Size = 20 (0x14) */ 282 283 284 /** 285 * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified) 286 */ 287 typedef struct { 288 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated 289 from the external domain n List capabilities 290 of the external domain n */ 291 } SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */ 292 293 294 /** 295 * @brief SPU_DPPI [DPPI] (Unspecified) 296 */ 297 typedef struct { 298 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 299 non-secure attribute for the DPPI channels. */ 300 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 301 of the corresponding PERM register */ 302 } SPU_DPPI_Type; /*!< Size = 8 (0x8) */ 303 304 305 /** 306 * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified) 307 */ 308 typedef struct { 309 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 310 non-secure attribute for pins 0 to 31 of 311 port n. */ 312 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 313 of the corresponding PERM register */ 314 } SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ 315 316 317 /** 318 * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified) 319 */ 320 typedef struct { 321 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region 322 can contain the non-secure callable (NSC) 323 region n */ 324 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 325 callable (NSC) region n */ 326 } SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */ 327 328 329 /** 330 * @brief SPU_RAMNSC [RAMNSC] (Unspecified) 331 */ 332 typedef struct { 333 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region 334 can contain the non-secure callable (NSC) 335 region n */ 336 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 337 callable (NSC) region n */ 338 } SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */ 339 340 341 /** 342 * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified) 343 */ 344 typedef struct { 345 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash 346 region n */ 347 } SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */ 348 349 350 /** 351 * @brief SPU_RAMREGION [RAMREGION] (Unspecified) 352 */ 353 typedef struct { 354 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM 355 region n */ 356 } SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */ 357 358 359 /** 360 * @brief SPU_PERIPHID [PERIPHID] (Unspecified) 361 */ 362 typedef struct { 363 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access 364 permissions for the peripheral with ID n */ 365 } SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ 366 367 368 /** 369 * @brief POWER_LTEMODEM [LTEMODEM] (LTE Modem) 370 */ 371 typedef struct { 372 __IOM uint32_t STARTN; /*!< (@ 0x00000000) Start LTE modem */ 373 __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off LTE modem */ 374 } POWER_LTEMODEM_Type; /*!< Size = 8 (0x8) */ 375 376 377 /** 378 * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 379 */ 380 typedef struct { 381 __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ 382 __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if 383 data sent from the debugger to the CPU has 384 been read. */ 385 __IM uint32_t RESERVED[30]; 386 __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ 387 __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if 388 the data sent from the CPU to the debugger 389 has been read. */ 390 } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 391 392 393 /** 394 * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 395 */ 396 typedef struct { 397 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE 398 register from being written until next reset. */ 399 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register 400 and performs an ERASEALL operation. */ 401 } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 402 403 404 /** 405 * @brief SPIM_PSEL [PSEL] (Unspecified) 406 */ 407 typedef struct { 408 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 409 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 410 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 411 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 412 413 414 /** 415 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 416 */ 417 typedef struct { 418 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 419 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 420 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 421 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 422 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 423 424 425 /** 426 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 427 */ 428 typedef struct { 429 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 430 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 431 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 432 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 433 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 434 435 436 /** 437 * @brief SPIS_PSEL [PSEL] (Unspecified) 438 */ 439 typedef struct { 440 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 441 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 442 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 443 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 444 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 445 446 447 /** 448 * @brief SPIS_RXD [RXD] (Unspecified) 449 */ 450 typedef struct { 451 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 452 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 453 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 454 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 455 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 456 457 458 /** 459 * @brief SPIS_TXD [TXD] (Unspecified) 460 */ 461 typedef struct { 462 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 463 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 464 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 465 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 466 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 467 468 469 /** 470 * @brief TWIM_PSEL [PSEL] (Unspecified) 471 */ 472 typedef struct { 473 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 474 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 475 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 476 477 478 /** 479 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 480 */ 481 typedef struct { 482 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 483 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 484 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 485 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 486 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 487 488 489 /** 490 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 491 */ 492 typedef struct { 493 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 494 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 495 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 496 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 497 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 498 499 500 /** 501 * @brief TWIS_PSEL [PSEL] (Unspecified) 502 */ 503 typedef struct { 504 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 505 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 506 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 507 508 509 /** 510 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 511 */ 512 typedef struct { 513 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 514 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 515 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 516 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 517 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 518 519 520 /** 521 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 522 */ 523 typedef struct { 524 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 525 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 526 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 527 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 528 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 529 530 531 /** 532 * @brief UARTE_PSEL [PSEL] (Unspecified) 533 */ 534 typedef struct { 535 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 536 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 537 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 538 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 539 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 540 541 542 /** 543 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 544 */ 545 typedef struct { 546 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 547 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 548 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 549 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 550 551 552 /** 553 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 554 */ 555 typedef struct { 556 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 557 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 558 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 559 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 560 561 562 /** 563 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 564 */ 565 typedef struct { 566 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 567 above CH[n].LIMIT.HIGH */ 568 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 569 below CH[n].LIMIT.LOW */ 570 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 571 572 573 /** 574 * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events) 575 */ 576 typedef struct { 577 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for 578 event CH[n].LIMITH */ 579 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for 580 event CH[n].LIMITL */ 581 } SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */ 582 583 584 /** 585 * @brief SAADC_CH [CH] (Unspecified) 586 */ 587 typedef struct { 588 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 589 for CH[n] */ 590 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 591 for CH[n] */ 592 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 593 CH[n] */ 594 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 595 monitoring a channel */ 596 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 597 598 599 /** 600 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 601 */ 602 typedef struct { 603 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 604 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 605 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 606 START */ 607 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 608 609 610 /** 611 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 612 */ 613 typedef struct { 614 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 615 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 616 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 617 618 619 /** 620 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 621 */ 622 typedef struct { 623 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 624 for task CHG[n].EN */ 625 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 626 for task CHG[n].DIS */ 627 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 628 629 630 /** 631 * @brief PWM_SEQ [SEQ] (Unspecified) 632 */ 633 typedef struct { 634 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 635 of this sequence */ 636 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 637 in this sequence */ 638 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 639 periods between samples loaded into compare 640 register */ 641 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 642 __IM uint32_t RESERVED[4]; 643 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 644 645 646 /** 647 * @brief PWM_PSEL [PSEL] (Unspecified) 648 */ 649 typedef struct { 650 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 651 PWM channel n */ 652 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 653 654 655 /** 656 * @brief PDM_PSEL [PSEL] (Unspecified) 657 */ 658 typedef struct { 659 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 660 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 661 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 662 663 664 /** 665 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 666 */ 667 typedef struct { 668 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 669 EasyDMA */ 670 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 671 mode */ 672 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 673 674 675 /** 676 * @brief I2S_CONFIG [CONFIG] (Unspecified) 677 */ 678 typedef struct { 679 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 680 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 681 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 682 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 683 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 684 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 685 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 686 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 687 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 688 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 689 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 690 691 692 /** 693 * @brief I2S_RXD [RXD] (Unspecified) 694 */ 695 typedef struct { 696 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 697 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 698 699 700 /** 701 * @brief I2S_TXD [TXD] (Unspecified) 702 */ 703 typedef struct { 704 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 705 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 706 707 708 /** 709 * @brief I2S_RXTXD [RXTXD] (Unspecified) 710 */ 711 typedef struct { 712 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 713 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 714 715 716 /** 717 * @brief I2S_PSEL [PSEL] (Unspecified) 718 */ 719 typedef struct { 720 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 721 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 722 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 723 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 724 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 725 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 726 727 728 /** 729 * @brief APPROTECT_SECUREAPPROTECT [SECUREAPPROTECT] (Unspecified) 730 */ 731 typedef struct { 732 union { 733 __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable SECUREAPPROTECT mechanism */ 734 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000000) Software force SECUREAPPROTECT mechanism */ 735 }; 736 } APPROTECT_SECUREAPPROTECT_Type; /*!< Size = 4 (0x4) */ 737 738 739 /** 740 * @brief APPROTECT_APPROTECT [APPROTECT] (Unspecified) 741 */ 742 typedef struct { 743 union { 744 __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable APPROTECT mechanism */ 745 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000000) Software force APPROTECT mechanism */ 746 }; 747 } APPROTECT_APPROTECT_Type; /*!< Size = 4 (0x4) */ 748 749 750 /** 751 * @brief VMC_RAM [RAM] (Unspecified) 752 */ 753 typedef struct { 754 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 755 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 756 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 757 register */ 758 __IM uint32_t RESERVED; 759 } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 760 761 762 /** @} */ /* End of group Device_Peripheral_clusters */ 763 764 765 /* =========================================================================================================================== */ 766 /* ================ Device Specific Peripheral Section ================ */ 767 /* =========================================================================================================================== */ 768 769 770 /** @addtogroup Device_Peripheral_peripherals 771 * @{ 772 */ 773 774 775 776 /* =========================================================================================================================== */ 777 /* ================ FICR_S ================ */ 778 /* =========================================================================================================================== */ 779 780 781 /** 782 * @brief Factory Information Configuration Registers (FICR_S) 783 */ 784 785 typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 786 __IM uint32_t RESERVED[128]; 787 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 788 __IM uint32_t RESERVED1[53]; 789 __IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */ 790 __IM uint32_t RESERVED2[64]; 791 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 792 } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 793 794 795 796 /* =========================================================================================================================== */ 797 /* ================ UICR_S ================ */ 798 /* =========================================================================================================================== */ 799 800 801 /** 802 * @brief User information configuration registers User information configuration registers (UICR_S) 803 */ 804 805 typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ 806 __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 807 __IM uint32_t RESERVED[4]; 808 __IOM uint32_t XOSC32M; /*!< (@ 0x00000014) Oscillator control */ 809 __IM uint32_t RESERVED1; 810 __IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */ 811 __IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */ 812 __IOM uint32_t APPNVMCPOFGUARD; /*!< (@ 0x00000024) Enable blocking NVM WRITE and aborting NVM ERASE 813 for Application NVM in POFWARN condition. */ 814 __IOM uint32_t PMICCONF; /*!< (@ 0x00000028) Polarity of PMIC polarity configuration signals. */ 815 __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */ 816 __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */ 817 __IM uint32_t RESERVED2[53]; 818 __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: One time programmable 819 memory */ 820 __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */ 821 } NRF_UICR_Type; /*!< Size = 4096 (0x1000) */ 822 823 824 825 /* =========================================================================================================================== */ 826 /* ================ ETM_NS ================ */ 827 /* =========================================================================================================================== */ 828 829 830 /** 831 * @brief Embedded Trace Macrocell (ETM_NS) 832 */ 833 834 typedef struct { /*!< (@ 0xE0041000) ETM_NS Structure */ 835 __IM uint32_t RESERVED; 836 __IOM uint32_t TRCPRGCTLR; /*!< (@ 0x00000004) Enables the trace unit. */ 837 __IOM uint32_t TRCPROCSELR; /*!< (@ 0x00000008) Controls which PE to trace. Might ignore writes 838 when the trace unit is enabled or not idle. 839 Before writing to this register, ensure 840 that TRCSTATR.IDLE == 1 so that the trace 841 unit can synchronize with the chosen PE. 842 Implemented if TRCIDR3.NUMPROC is greater 843 than zero. */ 844 __IOM uint32_t TRCSTATR; /*!< (@ 0x0000000C) Idle status bit */ 845 __IOM uint32_t TRCCONFIGR; /*!< (@ 0x00000010) Controls the tracing options This register must 846 always be programmed as part of trace unit 847 initialization. Might ignore writes when 848 the trace unit is enabled or not idle. */ 849 __IM uint32_t RESERVED1[3]; 850 __IOM uint32_t TRCEVENTCTL0R; /*!< (@ 0x00000020) Controls the tracing of arbitrary events. If 851 the selected event occurs a trace element 852 is generated in the trace stream according 853 to the settings in TRCEVENTCTL1R.DATAEN 854 and TRCEVENTCTL1R.INSTEN. */ 855 __IOM uint32_t TRCEVENTCTL1R; /*!< (@ 0x00000024) Controls the behavior of the events that TRCEVENTCTL0R 856 selects. This register must always be programmed 857 as part of trace unit initialization. Might 858 ignore writes when the trace unit is enabled 859 or not idle. */ 860 __IM uint32_t RESERVED2; 861 __IOM uint32_t TRCSTALLCTLR; /*!< (@ 0x0000002C) Enables trace unit functionality that prevents 862 trace unit buffer overflows. Might ignore 863 writes when the trace unit is enabled or 864 not idle. Must be programmed if TRCIDR3.STALLCTL 865 == 1. */ 866 __IOM uint32_t TRCTSCTLR; /*!< (@ 0x00000030) Controls the insertion of global timestamps in 867 the trace streams. When the selected event 868 is triggered, the trace unit inserts a global 869 timestamp into the trace streams. Might 870 ignore writes when the trace unit is enabled 871 or not idle. Must be programmed if TRCCONFIGR.TS 872 == 1. */ 873 __IOM uint32_t TRCSYNCPR; /*!< (@ 0x00000034) Controls how often trace synchronization requests 874 occur. Might ignore writes when the trace 875 unit is enabled or not idle. If writes are 876 permitted then the register must be programmed. */ 877 __IOM uint32_t TRCCCCTLR; /*!< (@ 0x00000038) Sets the threshold value for cycle counting. 878 Might ignore writes when the trace unit 879 is enabled or not idle. Must be programmed 880 if TRCCONFIGR.CCI==1. */ 881 __IOM uint32_t TRCBBCTLR; /*!< (@ 0x0000003C) Controls which regions in the memory map are 882 enabled to use branch broadcasting. Might 883 ignore writes when the trace unit is enabled 884 or not idle. Must be programmed if TRCCONFIGR.BB 885 == 1. */ 886 __IOM uint32_t TRCTRACEIDR; /*!< (@ 0x00000040) Sets the trace ID for instruction trace. If data 887 trace is enabled then it also sets the trace 888 ID for data trace, to (trace ID for instruction 889 trace) + 1. This register must always be 890 programmed as part of trace unit initialization. 891 Might ignore writes when the trace unit 892 is enabled or not idle. */ 893 __IOM uint32_t TRCQCTLR; /*!< (@ 0x00000044) Controls when Q elements are enabled. Might ignore 894 writes when the trace unit is enabled or 895 not idle. This register must be programmed 896 if it is implemented and TRCCONFIGR.QE is 897 set to any value other than 0b00. */ 898 __IM uint32_t RESERVED3[14]; 899 __IOM uint32_t TRCVICTLR; /*!< (@ 0x00000080) Controls instruction trace filtering. Might ignore 900 writes when the trace unit is enabled or 901 not idle. Only returns stable data when 902 TRCSTATR.PMSTABLE == 1. Must be programmed, 903 particularly to set the value of the SSSTATUS 904 bit, which sets the state of the start/stop 905 logic. */ 906 __IOM uint32_t TRCVIIECTLR; /*!< (@ 0x00000084) ViewInst exclude control. Might ignore writes 907 when the trace unit is enabled or not idle. 908 This register must be programmed when one 909 or more address comparators are implemented. */ 910 __IOM uint32_t TRCVISSCTLR; /*!< (@ 0x00000088) Use this to set, or read, the single address 911 comparators that control the ViewInst start/stoplogic. 912 The start/stop logic is active for an instruction 913 which causes a start and remains activeup 914 to and including an instruction which causes 915 a stop, and then the start/stop logic becomesinactive. 916 Might ignore writes when the trace unit 917 is enabled or not idle. If implemented then 918 this register must be programmed. */ 919 __IOM uint32_t TRCVIPCSSCTLR; /*!< (@ 0x0000008C) Use this to set, or read, which PE comparator 920 inputs can control the ViewInst start/stop 921 logic. Might ignore writes when the trace 922 unit is enabled or not idle. If implemented 923 then this register must be programmed. */ 924 __IM uint32_t RESERVED4[4]; 925 __IOM uint32_t TRCVDCTLR; /*!< (@ 0x000000A0) Controls data trace filtering. Might ignore writes 926 when the trace unit is enabled or not idle. 927 This register must be programmed when data 928 tracing is enabled, that is, when either 929 TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == 1. */ 930 __IOM uint32_t TRCVDSACCTLR; /*!< (@ 0x000000A4) ViewData include / exclude control. Might ignore 931 writes when the trace unit is enabled or 932 not idle. This register must be programmed 933 when one or more address comparators are 934 implemented. */ 935 __IOM uint32_t TRCVDARCCTLR; /*!< (@ 0x000000A8) ViewData include / exclude control. Might ignore 936 writes when the trace unit is enabled or 937 not idle. This register must be programmed 938 when one or more address comparators are 939 implemented. */ 940 __IM uint32_t RESERVED5[21]; 941 __IOM uint32_t TRCSEQEVR[3]; /*!< (@ 0x00000100) Description collection: Moves the sequencer state 942 according to programmed events. Might ignore 943 writes when the trace unit is enabled or 944 not idle. When the sequencer is used, all 945 sequencer state transitions must be programmed 946 with a valid event. */ 947 __IM uint32_t RESERVED6[3]; 948 __IOM uint32_t TRCSEQRSTEVR; /*!< (@ 0x00000118) Moves the sequencer to state 0 when a programmed 949 event occurs. Might ignore writes when the 950 trace unit is enabled or not idle. When 951 the sequencer is used, all sequencer state 952 transitions must be programmed with a valid 953 event. */ 954 __IOM uint32_t TRCSEQSTR; /*!< (@ 0x0000011C) Use this to set, or read, the sequencer state. 955 Might ignore writes when the trace unit 956 is enabled or not idle. Only returns stable 957 data when TRCSTATR.PMSTABLE == 1. When the 958 sequencer is used, all sequencer state transitions 959 must be programmed with a valid event. */ 960 __IOM uint32_t TRCEXTINSELR; /*!< (@ 0x00000120) Use this to set, or read, which external inputs 961 are resources to the trace unit. Might ignore 962 writes when the trace unit is enabled or 963 not idle. Only returns stable data when 964 TRCSTATR.PMSTABLE == 1. When the sequencer 965 is used, all sequencer state transitions 966 must be programmed with a valid event. */ 967 __IM uint32_t RESERVED7[7]; 968 __IOM uint32_t TRCCNTRLDVR[4]; /*!< (@ 0x00000140) Description collection: This sets or returns 969 the reload count value for counter n. Might 970 ignore writes when the trace unit is enabled 971 or not idle. */ 972 __IOM uint32_t TRCCNTCTLR[4]; /*!< (@ 0x00000150) Description collection: Controls the operation 973 of counter n. Might ignore writes when the 974 trace unit is enabled or not idle. */ 975 __IOM uint32_t TRCCNTVR[4]; /*!< (@ 0x00000160) Description collection: This sets or returns 976 the value of counter n. The count value 977 is only stable when TRCSTATR.PMSTABLE == 978 1. If software uses counter n then it must 979 write to this register to set the initial 980 counter value. Might ignore writes when 981 the trace unit is enabled or not idle. */ 982 __IM uint32_t RESERVED8[36]; 983 __IOM uint32_t TRCRSCTLR[30]; /*!< (@ 0x00000200) Description collection: Controls the selection 984 of the resources in the trace unit. Might 985 ignore writes when the trace unit is enabled 986 or not idle. If software selects a non-implemented 987 resource then CONSTRAINED UNPREDICTABLEbehavior 988 of the resource selector occurs, so the 989 resource selector might fireunexpectedly 990 or might not fire. Reads of the TRCRSCTLRn 991 might return UNKNOWN. */ 992 __IM uint32_t RESERVED9[2]; 993 __IOM uint32_t TRCSSCCR0; /*!< (@ 0x00000280) Controls the single-shot comparator. */ 994 __IM uint32_t RESERVED10[7]; 995 __IOM uint32_t TRCSSCSR0; /*!< (@ 0x000002A0) Indicates the status of the single-shot comparators. 996 TRCSSCSR0 is sensitive toinstruction addresses. */ 997 __IM uint32_t RESERVED11[7]; 998 __IOM uint32_t TRCSSPCICR0; /*!< (@ 0x000002C0) Selects the processor comparator inputs for Single-shot 999 control. */ 1000 __IM uint32_t RESERVED12[19]; 1001 __IOM uint32_t TRCPDCR; /*!< (@ 0x00000310) Controls the single-shot comparator. */ 1002 __IOM uint32_t TRCPDSR; /*!< (@ 0x00000314) Indicates the power down status of the ETM. */ 1003 __IM uint32_t RESERVED13[755]; 1004 __IOM uint32_t TRCITATBIDR; /*!< (@ 0x00000EE4) Sets the state of output pins. */ 1005 __IM uint32_t RESERVED14[3]; 1006 __IOM uint32_t TRCITIATBINR; /*!< (@ 0x00000EF4) Reads the state of the input pins. */ 1007 __IM uint32_t RESERVED15; 1008 __IOM uint32_t TRCITIATBOUTR; /*!< (@ 0x00000EFC) Sets the state of the output pins. */ 1009 __IOM uint32_t TRCITCTRL; /*!< (@ 0x00000F00) Enables topology detection or integration testing, 1010 by putting ETM-M33 into integration mode. */ 1011 __IM uint32_t RESERVED16[39]; 1012 __IOM uint32_t TRCCLAIMSET; /*!< (@ 0x00000FA0) Sets bits in the claim tag and determines the 1013 number of claim tag bits implemented. */ 1014 __IOM uint32_t TRCCLAIMCLR; /*!< (@ 0x00000FA4) Clears bits in the claim tag and determines the 1015 current value of the claim tag. */ 1016 __IM uint32_t RESERVED17[4]; 1017 __IOM uint32_t TRCAUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted 1018 by the system */ 1019 __IM uint32_t TRCDEVARCH; /*!< (@ 0x00000FBC) The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 1020 component */ 1021 __IM uint32_t RESERVED18[3]; 1022 __IM uint32_t TRCDEVTYPE; /*!< (@ 0x00000FCC) Controls the single-shot comparator. */ 1023 __IOM uint32_t TRCPIDR[8]; /*!< (@ 0x00000FD0) Description collection: Coresight peripheral 1024 identification registers. */ 1025 __IOM uint32_t TRCCIDR[4]; /*!< (@ 0x00000FF0) Description collection: Coresight component identification 1026 registers. */ 1027 } NRF_ETM_Type; /*!< Size = 4096 (0x1000) */ 1028 1029 1030 1031 /* =========================================================================================================================== */ 1032 /* ================ ETB_NS ================ */ 1033 /* =========================================================================================================================== */ 1034 1035 1036 /** 1037 * @brief Embedded Trace Buffer (ETB_NS) 1038 */ 1039 1040 typedef struct { /*!< (@ 0xE0051000) ETB_NS Structure */ 1041 __IM uint32_t RESERVED; 1042 __IM uint32_t RDP; /*!< (@ 0x00000004) ETB RAM Depth Register */ 1043 __IM uint32_t RESERVED1; 1044 __IM uint32_t STS; /*!< (@ 0x0000000C) ETB Status Register */ 1045 __IM uint32_t RRD; /*!< (@ 0x00000010) ETB RAM Read Data Register */ 1046 __IOM uint32_t RRP; /*!< (@ 0x00000014) ETB RAM Read Pointer Register */ 1047 __IOM uint32_t RWP; /*!< (@ 0x00000018) ETB RAM Write Pointer Register */ 1048 __IOM uint32_t TRG; /*!< (@ 0x0000001C) ETB Trigger Counter Register */ 1049 __IOM uint32_t CTL; /*!< (@ 0x00000020) ETB Control Register */ 1050 __IOM uint32_t RWD; /*!< (@ 0x00000024) ETB RAM Write Data Register */ 1051 __IM uint32_t RESERVED2[182]; 1052 __IM uint32_t FFSR; /*!< (@ 0x00000300) ETB Formatter and Flush Status Register */ 1053 __IOM uint32_t FFCR; /*!< (@ 0x00000304) ETB Formatter and Flush Control Register */ 1054 __IM uint32_t RESERVED3[758]; 1055 __OM uint32_t ITMISCOP0; /*!< (@ 0x00000EE0) Integration Test Miscellaneous Output Register 1056 0 */ 1057 __OM uint32_t ITTRFLINACK; /*!< (@ 0x00000EE4) Integration Test Trigger In and Flush In Acknowledge 1058 Register */ 1059 __IM uint32_t ITTRFLIN; /*!< (@ 0x00000EE8) Integration Test Trigger In and Flush In Register */ 1060 __IM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) Integration Test ATB Data Register 0 */ 1061 __OM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) Integration Test ATB Control Register 2 */ 1062 __IM uint32_t ITATBCTR1; /*!< (@ 0x00000EF4) Integration Test ATB Control Register 1 */ 1063 __IM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) Integration Test ATB Control Register 0 */ 1064 __IM uint32_t RESERVED4; 1065 __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) Integration Mode Control Register */ 1066 __IM uint32_t RESERVED5[39]; 1067 __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Claim Tag Set Register */ 1068 __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Claim Tag Clear Register */ 1069 __IM uint32_t RESERVED6[2]; 1070 __OM uint32_t LAR; /*!< (@ 0x00000FB0) Lock Access Register */ 1071 __IM uint32_t LSR; /*!< (@ 0x00000FB4) Lock Status Register */ 1072 __IM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Authentication Status Register */ 1073 __IM uint32_t RESERVED7[3]; 1074 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Device Configuration Register */ 1075 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Device Type Identifier Register */ 1076 __IM uint32_t PERIPHID4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ 1077 __IM uint32_t RESERVED8[3]; 1078 __IM uint32_t PERIPHID0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ 1079 __IM uint32_t PERIPHID1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ 1080 __IM uint32_t PERIPHID2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ 1081 __IM uint32_t PERIPHID3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ 1082 __IM uint32_t COMPID0; /*!< (@ 0x00000FF0) Component ID0 Register */ 1083 __IM uint32_t COMPID1; /*!< (@ 0x00000FF4) Component ID1 Register */ 1084 __IM uint32_t COMPID2; /*!< (@ 0x00000FF8) Component ID2 Register */ 1085 __IM uint32_t COMPID3; /*!< (@ 0x00000FFC) Component ID3 Register */ 1086 } NRF_ETB_Type; /*!< Size = 4096 (0x1000) */ 1087 1088 1089 1090 /* =========================================================================================================================== */ 1091 /* ================ TPIU_NS ================ */ 1092 /* =========================================================================================================================== */ 1093 1094 1095 /** 1096 * @brief Trace Port Interface Unit (TPIU_NS) 1097 */ 1098 1099 typedef struct { /*!< (@ 0xE0054000) TPIU_NS Structure */ 1100 __IOM uint32_t SUPPORTEDPORTSIZES; /*!< (@ 0x00000000) Each bit location is a single port size that 1101 is supported on the device. */ 1102 __IOM uint32_t CURRENTPORTSIZE; /*!< (@ 0x00000004) Each bit location is a single port size. One 1103 bit can be set, and indicates the current 1104 port size. */ 1105 __IM uint32_t RESERVED[62]; 1106 __IOM uint32_t SUPPORTEDTRIGGERMODES; /*!< (@ 0x00000100) The Supported_trigger_modes register indicates 1107 the implemented trigger counter multipliers 1108 and other supported features of the trigger 1109 system. */ 1110 __IOM uint32_t TRIGGERCOUNTERVALUE; /*!< (@ 0x00000104) The Trigger_counter_value register enables delaying 1111 the indication of triggers to any external 1112 connected trace capture or storage devices. */ 1113 __IOM uint32_t TRIGGERMULTIPLIER; /*!< (@ 0x00000108) The Trigger_multiplier register contains the 1114 selectors for the trigger counter multiplier. */ 1115 __IM uint32_t RESERVED1[61]; 1116 __IOM uint32_t SUPPPORTEDTESTPATTERNMODES; /*!< (@ 0x00000200) The Supported_test_pattern_modes register provides 1117 a set of known bit sequences or patterns 1118 that can be output over the trace port and 1119 can be detected by the TPA or other associated 1120 trace capture device. */ 1121 __IOM uint32_t CURRENTTESTPATTERNMODES; /*!< (@ 0x00000204) Current_test_pattern_mode indicates the current 1122 test pattern or mode selected. */ 1123 __IOM uint32_t TPRCR; /*!< (@ 0x00000208) The TPRCR register is an 8-bit counter start 1124 value that is decremented. A write sets 1125 the initial counter value and a read returns 1126 the programmed value. */ 1127 __IM uint32_t RESERVED2[61]; 1128 __IOM uint32_t FFSR; /*!< (@ 0x00000300) The FFSR register indicates the current status 1129 of the formatter and flush features available 1130 in the TPIU. */ 1131 __IOM uint32_t FFCR; /*!< (@ 0x00000304) The FFCR register controls the generation of 1132 stop, trigger, and flush events. */ 1133 __IOM uint32_t FSCR; /*!< (@ 0x00000308) The FSCR register enables the frequency of synchronization 1134 information to be optimized to suit the 1135 Trace Port Analyzer (TPA) capture buffer 1136 size. */ 1137 __IM uint32_t RESERVED3[61]; 1138 __IOM uint32_t EXTCTLINPORT; /*!< (@ 0x00000400) Two ports can be used as a control and feedback 1139 mechanism for any serializers, pin sharing 1140 multiplexers, or other solutions that might 1141 be added to the trace output pins either 1142 for pin control or a high-speed trace port 1143 solution. */ 1144 __IOM uint32_t EXTCTLOUTPORT; /*!< (@ 0x00000404) Two ports can be used as a control and feedback 1145 mechanism for any serializers, pin sharing 1146 multiplexers, or other solutions that might 1147 be added to the trace output pins either 1148 for pin control or a high speed trace port 1149 solution. These ports are raw register banks 1150 that sample or export the corresponding 1151 external pins. */ 1152 __IM uint32_t RESERVED4[695]; 1153 __IOM uint32_t ITTRFLINACK; /*!< (@ 0x00000EE4) The ITTRFLINACK register enables control of the 1154 triginack and flushinack outputs from the 1155 TPIU. */ 1156 __IOM uint32_t ITTRFLIN; /*!< (@ 0x00000EE8) The ITTRFLIN register contains the values of 1157 the flushin and trigin inputs to the TPIU. */ 1158 __IOM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) The ITATBDATA0 register contains the value of 1159 the atdatas inputs to the TPIU. The values 1160 are valid only when atvalids is HIGH. */ 1161 __IOM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) Enables control of the atreadys and afvalids 1162 outputs of the TPIU. */ 1163 __IOM uint32_t ITATBCTR1; /*!< (@ 0x00000EF4) The ITATBCTR1 register contains the value of 1164 the atids input to the TPIU. This is only 1165 valid when atvalids is HIGH. */ 1166 __IOM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) The ITATBCTR0 register captures the values of 1167 the atvalids, afreadys, and atbytess inputs 1168 to the TPIU. To ensure the integration 1169 registers work correctly in a system, the 1170 value of atbytess is only valid when atvalids, 1171 bit[0], is HIGH. */ 1172 __IM uint32_t RESERVED5; 1173 __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) Used to enable topology detection. This register 1174 enables the component to switch from a functional 1175 mode, the default behavior, to integration 1176 mode where the inputs and outputs of the 1177 component can be directly controlled for 1178 integration testing and topology solving. */ 1179 __IM uint32_t RESERVED6[39]; 1180 __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate 1181 application and debugger access to trace 1182 unit functionality. The claim tags have 1183 no effect on the operation of the component. 1184 The CLAIMSET register sets bits in the claim 1185 tag, and determines the number of claim 1186 bits implemented. */ 1187 __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate 1188 application and debugger access to trace 1189 unit functionality. The claim tags have 1190 no effect on the operation of the component. 1191 The CLAIMCLR register sets the bits in the 1192 claim tag to 0 and determines the current 1193 value of the claim tag. */ 1194 __IM uint32_t RESERVED7[2]; 1195 __IOM uint32_t LAR; /*!< (@ 0x00000FB0) This is used to enable write access to device 1196 registers. */ 1197 __IOM uint32_t LSR; /*!< (@ 0x00000FB4) This indicates the status of the lock control 1198 mechanism. This lock prevents accidental 1199 writes by code under debug. Accesses to 1200 the extended stimulus port registers are 1201 not affected by the lock mechanism. This 1202 register must always be present although 1203 there might not be any lock access control 1204 mechanism. The lock mechanism, where present 1205 and locked, must block write accesses to 1206 any control register, except the Lock Access 1207 Register. For most components this cover */ 1208 __IOM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted 1209 by the system */ 1210 __IM uint32_t RESERVED8[3]; 1211 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Indicates the capabilities of the component. */ 1212 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with 1213 information about the component when the 1214 Part Number field is not recognized. The 1215 debugger can then report this information. */ 1216 __IOM uint32_t PIDR4; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ 1217 __IM uint32_t RESERVED9[3]; 1218 __IOM uint32_t PIDR_0; /*!< (@ 0x00000FE0) Coresight peripheral identification registers. */ 1219 __IOM uint32_t PIDR_1; /*!< (@ 0x00000FE4) Coresight peripheral identification registers. */ 1220 __IOM uint32_t PIDR_2; /*!< (@ 0x00000FE8) Coresight peripheral identification registers. */ 1221 __IOM uint32_t PIDR_3; /*!< (@ 0x00000FEC) Coresight peripheral identification registers. */ 1222 __IOM uint32_t CIDR_0; /*!< (@ 0x00000FF0) Coresight component identification registers. */ 1223 __IOM uint32_t CIDR_1; /*!< (@ 0x00000FF4) Coresight component identification registers. */ 1224 __IOM uint32_t CIDR_2; /*!< (@ 0x00000FF8) Coresight component identification registers. */ 1225 __IOM uint32_t CIDR_3; /*!< (@ 0x00000FFC) Coresight component identification registers. */ 1226 } NRF_TPIU_Type; /*!< Size = 4096 (0x1000) */ 1227 1228 1229 1230 /* =========================================================================================================================== */ 1231 /* ================ ATBREPLICATOR_NS ================ */ 1232 /* =========================================================================================================================== */ 1233 1234 1235 /** 1236 * @brief ATB Replicator module (ATBREPLICATOR_NS) 1237 */ 1238 1239 typedef struct { /*!< (@ 0xE0058000) ATBREPLICATOR_NS Structure */ 1240 __IOM uint32_t IDFILTER0; /*!< (@ 0x00000000) The IDFILTER0 register enables the programming 1241 of ID filtering for master port 0. */ 1242 __IOM uint32_t IDFILTER1; /*!< (@ 0x00000004) The IDFILTER1 register enables the programming 1243 of ID filtering for master port 1. */ 1244 __IM uint32_t RESERVED[956]; 1245 __IOM uint32_t ITATBCTR1; /*!< (@ 0x00000EF8) The ITATBCTR1 register returns the value of the 1246 atreadym0, atreadym1, and atvalids inputs 1247 in integration mode. */ 1248 __IOM uint32_t ITATBCTR0; /*!< (@ 0x00000EFC) The ITATBCTR0 register controls the value of 1249 the atvalidm0, atvalidm1, and atreadys outputs 1250 in integration mode. */ 1251 __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) The ITCTRL register enables the component to 1252 switch from a functional mode, which is 1253 the default behavior, to integration mode 1254 where the inputs and outputs of the component 1255 can be directly controlled for the purposes 1256 of integration testing and topology detection. */ 1257 __IM uint32_t RESERVED1[39]; 1258 __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate 1259 application and debugger access to trace 1260 unit functionality. The claim tags have 1261 no effect on the operation of the component. 1262 The CLAIMSET register sets bits in the claim 1263 tag, and determines the number of claim 1264 bits implemented. */ 1265 __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate 1266 application and debugger access to trace 1267 unit functionality. The claim tags have 1268 no effect on the operation of the component. 1269 The CLAIMCLR register sets the bits in the 1270 claim tag to 0 and determines the current 1271 value of the claim tag. */ 1272 __IM uint32_t RESERVED2[2]; 1273 __IOM uint32_t LAR; /*!< (@ 0x00000FB0) This is used to enable write access to device 1274 registers. */ 1275 __IOM uint32_t LSR; /*!< (@ 0x00000FB4) This indicates the status of the lock control 1276 mechanism. This lock prevents accidental 1277 writes by code under debug. Accesses to 1278 the extended stimulus port registers are 1279 not affected by the lock mechanism. This 1280 register must always be present although 1281 there might not be any lock access control 1282 mechanism. The lock mechanism, where present 1283 and locked, must block write accesses to 1284 any control register, except the Lock Access 1285 Register. For most components this cover */ 1286 __IOM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted 1287 by the system */ 1288 __IM uint32_t RESERVED3[3]; 1289 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Indicates the capabilities of the component. */ 1290 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with 1291 information about the component when the 1292 Part Number field is not recognized. The 1293 debugger can then report this information. */ 1294 __IOM uint32_t PIDR4; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ 1295 __IM uint32_t RESERVED4[3]; 1296 __IOM uint32_t PIDR_0; /*!< (@ 0x00000FE0) Coresight peripheral identification registers. */ 1297 __IOM uint32_t PIDR_1; /*!< (@ 0x00000FE4) Coresight peripheral identification registers. */ 1298 __IOM uint32_t PIDR_2; /*!< (@ 0x00000FE8) Coresight peripheral identification registers. */ 1299 __IOM uint32_t PIDR_3; /*!< (@ 0x00000FEC) Coresight peripheral identification registers. */ 1300 __IOM uint32_t CIDR_0; /*!< (@ 0x00000FF0) Coresight component identification registers. */ 1301 __IOM uint32_t CIDR_1; /*!< (@ 0x00000FF4) Coresight component identification registers. */ 1302 __IOM uint32_t CIDR_2; /*!< (@ 0x00000FF8) Coresight component identification registers. */ 1303 __IOM uint32_t CIDR_3; /*!< (@ 0x00000FFC) Coresight component identification registers. */ 1304 } NRF_ATBREPLICATOR_Type; /*!< Size = 4096 (0x1000) */ 1305 1306 1307 1308 /* =========================================================================================================================== */ 1309 /* ================ ATBFUNNEL1_NS ================ */ 1310 /* =========================================================================================================================== */ 1311 1312 1313 /** 1314 * @brief ATB funnel module 0 (ATBFUNNEL1_NS) 1315 */ 1316 1317 typedef struct { /*!< (@ 0xE005A000) ATBFUNNEL1_NS Structure */ 1318 __IOM uint32_t CTRLREG; /*!< (@ 0x00000000) The IDFILTER0 register enables the programming 1319 of ID filtering for master port 0. */ 1320 __IOM uint32_t PRIORITYCTRLREG; /*!< (@ 0x00000004) The Priority_Ctrl_Reg register defines the order 1321 in which inputs are selected. Each 3-bit 1322 field is a priority for each particular 1323 slave interface. */ 1324 __IM uint32_t RESERVED[953]; 1325 __IOM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) The ITATBDATA0 register performs different functions 1326 depending on whether the access is a read 1327 or a write. */ 1328 __IOM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) The ITATBCTR2 register performs different functions 1329 depending on whether the access is a read 1330 or a write. */ 1331 __IOM uint32_t ITATBCTR1; /*!< (@ 0x00000EF4) The ITATBCTR1 register performs different functions 1332 depending on whether the access is a read 1333 or a write. */ 1334 __IOM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) The ITATBCTR0 register performs different functions 1335 depending on whether the access is a read 1336 or a write. */ 1337 __IM uint32_t RESERVED1; 1338 __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) The ITCTRL register enables the component to 1339 switch from a functional mode, which is 1340 the default behavior, to integration mode 1341 where the inputs and outputs of the component 1342 can be directly controlled for the purposes 1343 of integration testing and topology detection. */ 1344 __IM uint32_t RESERVED2[39]; 1345 __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate 1346 application and debugger access to trace 1347 unit functionality. The claim tags have 1348 no effect on the operation of the component. 1349 The CLAIMSET register sets bits in the claim 1350 tag, and determines the number of claim 1351 bits implemented. */ 1352 __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate 1353 application and debugger access to trace 1354 unit functionality. The claim tags have 1355 no effect on the operation of the component. 1356 The CLAIMCLR register sets the bits in the 1357 claim tag to 0 and determines the current 1358 value of the claim tag. */ 1359 __IM uint32_t RESERVED3[2]; 1360 __IOM uint32_t LAR; /*!< (@ 0x00000FB0) This is used to enable write access to device 1361 registers. */ 1362 __IOM uint32_t LSR; /*!< (@ 0x00000FB4) This indicates the status of the lock control 1363 mechanism. This lock prevents accidental 1364 writes by code under debug. Accesses to 1365 the extended stimulus port registers are 1366 not affected by the lock mechanism. This 1367 register must always be present although 1368 there might not be any lock access control 1369 mechanism. The lock mechanism, where present 1370 and locked, must block write accesses to 1371 any control register, except the Lock Access 1372 Register. For most components this cover */ 1373 __IOM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted 1374 by the system */ 1375 __IM uint32_t RESERVED4[3]; 1376 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Indicates the capabilities of the component. */ 1377 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with 1378 information about the component when the 1379 Part Number field is not recognized. The 1380 debugger can then report this information. */ 1381 __IOM uint32_t PIDR4; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ 1382 __IM uint32_t RESERVED5[3]; 1383 __IOM uint32_t PIDR_0; /*!< (@ 0x00000FE0) Coresight peripheral identification registers. */ 1384 __IOM uint32_t PIDR_1; /*!< (@ 0x00000FE4) Coresight peripheral identification registers. */ 1385 __IOM uint32_t PIDR_2; /*!< (@ 0x00000FE8) Coresight peripheral identification registers. */ 1386 __IOM uint32_t PIDR_3; /*!< (@ 0x00000FEC) Coresight peripheral identification registers. */ 1387 __IOM uint32_t CIDR_0; /*!< (@ 0x00000FF0) Coresight component identification registers. */ 1388 __IOM uint32_t CIDR_1; /*!< (@ 0x00000FF4) Coresight component identification registers. */ 1389 __IOM uint32_t CIDR_2; /*!< (@ 0x00000FF8) Coresight component identification registers. */ 1390 __IOM uint32_t CIDR_3; /*!< (@ 0x00000FFC) Coresight component identification registers. */ 1391 } NRF_ATBFUNNEL_Type; /*!< Size = 4096 (0x1000) */ 1392 1393 1394 1395 /* =========================================================================================================================== */ 1396 /* ================ TAD_S ================ */ 1397 /* =========================================================================================================================== */ 1398 1399 1400 /** 1401 * @brief Trace and debug control (TAD_S) 1402 */ 1403 1404 typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ 1405 __OM uint32_t TASKS_CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */ 1406 __OM uint32_t TASKS_CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */ 1407 __IM uint32_t RESERVED[318]; 1408 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ 1409 __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ 1410 __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface 1411 Reset behavior is the same as debug components */ 1412 } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ 1413 1414 1415 1416 /* =========================================================================================================================== */ 1417 /* ================ SPU_S ================ */ 1418 /* =========================================================================================================================== */ 1419 1420 1421 /** 1422 * @brief System protection unit (SPU_S) 1423 */ 1424 1425 typedef struct { /*!< (@ 0x50003000) SPU_S Structure */ 1426 __IM uint32_t RESERVED[64]; 1427 __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the 1428 RAM memory space */ 1429 __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the 1430 flash memory space */ 1431 __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one 1432 or several peripherals */ 1433 __IM uint32_t RESERVED1[29]; 1434 __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */ 1435 __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */ 1436 __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */ 1437 __IM uint32_t RESERVED2[93]; 1438 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1439 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1440 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1441 __IM uint32_t RESERVED3[61]; 1442 __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */ 1443 __IM uint32_t RESERVED4[15]; 1444 __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */ 1445 __IM uint32_t RESERVED5[15]; 1446 __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */ 1447 __IM uint32_t RESERVED6[14]; 1448 __IOM SPU_GPIOPORT_Type GPIOPORT[1]; /*!< (@ 0x000004C0) Unspecified */ 1449 __IM uint32_t RESERVED7[14]; 1450 __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */ 1451 __IM uint32_t RESERVED8[12]; 1452 __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */ 1453 __IM uint32_t RESERVED9[44]; 1454 __IOM SPU_FLASHREGION_Type FLASHREGION[32]; /*!< (@ 0x00000600) Unspecified */ 1455 __IM uint32_t RESERVED10[32]; 1456 __IOM SPU_RAMREGION_Type RAMREGION[32]; /*!< (@ 0x00000700) Unspecified */ 1457 __IM uint32_t RESERVED11[32]; 1458 __IOM SPU_PERIPHID_Type PERIPHID[67]; /*!< (@ 0x00000800) Unspecified */ 1459 } NRF_SPU_Type; /*!< Size = 2316 (0x90c) */ 1460 1461 1462 1463 /* =========================================================================================================================== */ 1464 /* ================ REGULATORS_NS ================ */ 1465 /* =========================================================================================================================== */ 1466 1467 1468 /** 1469 * @brief Voltage regulators control 0 (REGULATORS_NS) 1470 */ 1471 1472 typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ 1473 __IM uint32_t RESERVED[320]; 1474 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 1475 __IM uint32_t RESERVED1[4]; 1476 __IOM uint32_t EXTPOFCON; /*!< (@ 0x00000514) External power failure warning configuration */ 1477 __IM uint32_t RESERVED2[24]; 1478 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable a step-down DC/DC voltage regulator. */ 1479 } NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */ 1480 1481 1482 1483 /* =========================================================================================================================== */ 1484 /* ================ CLOCK_NS ================ */ 1485 /* =========================================================================================================================== */ 1486 1487 1488 /** 1489 * @brief Clock management 0 (CLOCK_NS) 1490 */ 1491 1492 typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 1493 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK source */ 1494 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK source */ 1495 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 1496 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 1497 __IM uint32_t RESERVED[28]; 1498 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 1499 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 1500 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 1501 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 1502 __IM uint32_t RESERVED1[28]; 1503 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 1504 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 1505 __IM uint32_t RESERVED2[30]; 1506 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 1507 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 1508 __IM uint32_t RESERVED3[94]; 1509 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1510 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1511 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1512 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1513 __IM uint32_t RESERVED4[62]; 1514 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 1515 triggered */ 1516 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) The register shows if HFXO has been requested 1517 by triggering HFCLKSTART task and if it 1518 has been started (STATE). */ 1519 __IM uint32_t RESERVED5; 1520 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 1521 triggered */ 1522 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) The register shows which LFCLK source has been 1523 requested (SRC) when triggering LFCLKSTART 1524 task and if the source has been started 1525 (STATE). */ 1526 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set after LFCLKSTART 1527 task has been triggered */ 1528 __IM uint32_t RESERVED6[62]; 1529 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK. LFCLKSTART task starts 1530 a clock source selected with this register. */ 1531 } NRF_CLOCK_Type; /*!< Size = 1308 (0x51c) */ 1532 1533 1534 1535 /* =========================================================================================================================== */ 1536 /* ================ POWER_NS ================ */ 1537 /* =========================================================================================================================== */ 1538 1539 1540 /** 1541 * @brief Power control 0 (POWER_NS) 1542 */ 1543 1544 typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 1545 __IM uint32_t RESERVED[28]; 1546 __OM uint32_t TASKS_PWMREQSTART; /*!< (@ 0x00000070) Request forcing PWM mode in PMIC DC/DC buck regulator. 1547 (Drives FPWM_DCDC pin high or low depending 1548 on a setting in UICR). */ 1549 __OM uint32_t TASKS_PWMREQSTOP; /*!< (@ 0x00000074) Stop requesting forcing PWM mode in PMIC DC/DC 1550 buck regulator */ 1551 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ 1552 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 1553 __IM uint32_t RESERVED1[28]; 1554 __IOM uint32_t SUBSCRIBE_PWMREQSTART; /*!< (@ 0x000000F0) Subscribe configuration for task PWMREQSTART */ 1555 __IOM uint32_t SUBSCRIBE_PWMREQSTOP; /*!< (@ 0x000000F4) Subscribe configuration for task PWMREQSTOP */ 1556 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 1557 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 1558 __IM uint32_t RESERVED2[2]; 1559 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 1560 __IM uint32_t RESERVED3[2]; 1561 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1562 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1563 __IM uint32_t RESERVED4[27]; 1564 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 1565 __IM uint32_t RESERVED5[2]; 1566 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 1567 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 1568 __IM uint32_t RESERVED6[89]; 1569 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1570 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1571 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1572 __IM uint32_t RESERVED7[61]; 1573 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1574 __IM uint32_t RESERVED8[15]; 1575 __IM uint32_t POWERSTATUS; /*!< (@ 0x00000440) Modem domain power status */ 1576 __IM uint32_t RESERVED9[54]; 1577 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 1578 register */ 1579 __IM uint32_t RESERVED10[59]; 1580 __IOM POWER_LTEMODEM_Type LTEMODEM; /*!< (@ 0x00000610) LTE Modem */ 1581 } NRF_POWER_Type; /*!< Size = 1560 (0x618) */ 1582 1583 1584 1585 /* =========================================================================================================================== */ 1586 /* ================ CTRL_AP_PERI_S ================ */ 1587 /* =========================================================================================================================== */ 1588 1589 1590 /** 1591 * @brief Control access port (CTRL_AP_PERI_S) 1592 */ 1593 1594 typedef struct { /*!< (@ 0x50006000) CTRL_AP_PERI_S Structure */ 1595 __IM uint32_t RESERVED[256]; 1596 __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 1597 __IM uint32_t RESERVED1[30]; 1598 __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 1599 } NRF_CTRLAPPERI_Type; /*!< Size = 1288 (0x508) */ 1600 1601 1602 1603 /* =========================================================================================================================== */ 1604 /* ================ SPIM0_NS ================ */ 1605 /* =========================================================================================================================== */ 1606 1607 1608 /** 1609 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) 1610 */ 1611 1612 typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */ 1613 __IM uint32_t RESERVED[4]; 1614 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1615 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1616 __IM uint32_t RESERVED1; 1617 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1618 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1619 __IM uint32_t RESERVED2[27]; 1620 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 1621 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1622 __IM uint32_t RESERVED3; 1623 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1624 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1625 __IM uint32_t RESERVED4[24]; 1626 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1627 __IM uint32_t RESERVED5[2]; 1628 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1629 __IM uint32_t RESERVED6; 1630 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1631 __IM uint32_t RESERVED7; 1632 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1633 __IM uint32_t RESERVED8[10]; 1634 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1635 __IM uint32_t RESERVED9[13]; 1636 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1637 __IM uint32_t RESERVED10[2]; 1638 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1639 __IM uint32_t RESERVED11; 1640 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 1641 __IM uint32_t RESERVED12; 1642 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1643 __IM uint32_t RESERVED13[10]; 1644 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 1645 __IM uint32_t RESERVED14[12]; 1646 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1647 __IM uint32_t RESERVED15[64]; 1648 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1649 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1650 __IM uint32_t RESERVED16[125]; 1651 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1652 __IM uint32_t RESERVED17; 1653 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1654 __IM uint32_t RESERVED18[4]; 1655 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1656 source selected. */ 1657 __IM uint32_t RESERVED19[3]; 1658 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1659 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1660 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1661 __IM uint32_t RESERVED20[26]; 1662 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1663 case an over-read of the TXD buffer. */ 1664 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1665 1666 1667 1668 /* =========================================================================================================================== */ 1669 /* ================ SPIS0_NS ================ */ 1670 /* =========================================================================================================================== */ 1671 1672 1673 /** 1674 * @brief SPI Slave 0 (SPIS0_NS) 1675 */ 1676 1677 typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */ 1678 __IM uint32_t RESERVED[9]; 1679 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1680 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1681 to acquire it */ 1682 __IM uint32_t RESERVED1[30]; 1683 __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1684 __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1685 __IM uint32_t RESERVED2[22]; 1686 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1687 __IM uint32_t RESERVED3[2]; 1688 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1689 __IM uint32_t RESERVED4[5]; 1690 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1691 __IM uint32_t RESERVED5[22]; 1692 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1693 __IM uint32_t RESERVED6[2]; 1694 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1695 __IM uint32_t RESERVED7[5]; 1696 __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1697 __IM uint32_t RESERVED8[21]; 1698 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1699 __IM uint32_t RESERVED9[64]; 1700 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1701 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1702 __IM uint32_t RESERVED10[61]; 1703 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1704 __IM uint32_t RESERVED11[15]; 1705 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1706 __IM uint32_t RESERVED12[47]; 1707 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1708 __IM uint32_t RESERVED13; 1709 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1710 __IM uint32_t RESERVED14[7]; 1711 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1712 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1713 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1714 __IM uint32_t RESERVED15; 1715 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1716 of an ignored transaction. */ 1717 __IM uint32_t RESERVED16[24]; 1718 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1719 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1720 1721 1722 1723 /* =========================================================================================================================== */ 1724 /* ================ TWIM0_NS ================ */ 1725 /* =========================================================================================================================== */ 1726 1727 1728 /** 1729 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS) 1730 */ 1731 1732 typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */ 1733 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1734 __IM uint32_t RESERVED; 1735 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1736 __IM uint32_t RESERVED1[2]; 1737 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1738 TWI master is not suspended. */ 1739 __IM uint32_t RESERVED2; 1740 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1741 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1742 __IM uint32_t RESERVED3[23]; 1743 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1744 __IM uint32_t RESERVED4; 1745 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1746 __IM uint32_t RESERVED5[2]; 1747 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1748 __IM uint32_t RESERVED6; 1749 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1750 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1751 __IM uint32_t RESERVED7[24]; 1752 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1753 __IM uint32_t RESERVED8[7]; 1754 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1755 __IM uint32_t RESERVED9[8]; 1756 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1757 now suspended. */ 1758 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1759 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1760 __IM uint32_t RESERVED10[2]; 1761 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1762 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1763 byte */ 1764 __IM uint32_t RESERVED11[8]; 1765 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1766 __IM uint32_t RESERVED12[7]; 1767 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1768 __IM uint32_t RESERVED13[8]; 1769 __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1770 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1771 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1772 __IM uint32_t RESERVED14[2]; 1773 __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1774 __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1775 __IM uint32_t RESERVED15[7]; 1776 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1777 __IM uint32_t RESERVED16[63]; 1778 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1779 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1780 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1781 __IM uint32_t RESERVED17[110]; 1782 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1783 __IM uint32_t RESERVED18[14]; 1784 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1785 __IM uint32_t RESERVED19; 1786 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1787 __IM uint32_t RESERVED20[5]; 1788 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1789 source selected. */ 1790 __IM uint32_t RESERVED21[3]; 1791 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1792 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1793 __IM uint32_t RESERVED22[13]; 1794 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1795 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1796 1797 1798 1799 /* =========================================================================================================================== */ 1800 /* ================ TWIS0_NS ================ */ 1801 /* =========================================================================================================================== */ 1802 1803 1804 /** 1805 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS) 1806 */ 1807 1808 typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */ 1809 __IM uint32_t RESERVED[5]; 1810 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1811 __IM uint32_t RESERVED1; 1812 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1813 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1814 __IM uint32_t RESERVED2[3]; 1815 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1816 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1817 __IM uint32_t RESERVED3[23]; 1818 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1819 __IM uint32_t RESERVED4; 1820 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1821 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1822 __IM uint32_t RESERVED5[3]; 1823 __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1824 __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1825 __IM uint32_t RESERVED6[19]; 1826 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1827 __IM uint32_t RESERVED7[7]; 1828 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1829 __IM uint32_t RESERVED8[9]; 1830 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1831 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1832 __IM uint32_t RESERVED9[4]; 1833 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1834 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1835 __IM uint32_t RESERVED10[6]; 1836 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1837 __IM uint32_t RESERVED11[7]; 1838 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1839 __IM uint32_t RESERVED12[9]; 1840 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1841 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1842 __IM uint32_t RESERVED13[4]; 1843 __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1844 __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1845 __IM uint32_t RESERVED14[5]; 1846 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1847 __IM uint32_t RESERVED15[63]; 1848 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1849 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1850 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1851 __IM uint32_t RESERVED16[113]; 1852 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1853 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1854 a match */ 1855 __IM uint32_t RESERVED17[10]; 1856 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1857 __IM uint32_t RESERVED18; 1858 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1859 __IM uint32_t RESERVED19[9]; 1860 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1861 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1862 __IM uint32_t RESERVED20[13]; 1863 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1864 __IM uint32_t RESERVED21; 1865 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1866 mechanism */ 1867 __IM uint32_t RESERVED22[10]; 1868 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1869 of an over-read of the transmit buffer. */ 1870 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1871 1872 1873 1874 /* =========================================================================================================================== */ 1875 /* ================ UARTE0_NS ================ */ 1876 /* =========================================================================================================================== */ 1877 1878 1879 /** 1880 * @brief UART with EasyDMA 0 (UARTE0_NS) 1881 */ 1882 1883 typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ 1884 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1885 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1886 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1887 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1888 __IM uint32_t RESERVED[7]; 1889 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1890 __IM uint32_t RESERVED1[20]; 1891 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1892 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1893 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1894 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1895 __IM uint32_t RESERVED2[7]; 1896 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1897 __IM uint32_t RESERVED3[20]; 1898 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1899 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1900 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1901 transferred to Data RAM) */ 1902 __IM uint32_t RESERVED4; 1903 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1904 __IM uint32_t RESERVED5[2]; 1905 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1906 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1907 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1908 __IM uint32_t RESERVED6[7]; 1909 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1910 __IM uint32_t RESERVED7; 1911 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1912 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1913 __IM uint32_t RESERVED8; 1914 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1915 __IM uint32_t RESERVED9[9]; 1916 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1917 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1918 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1919 __IM uint32_t RESERVED10; 1920 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1921 __IM uint32_t RESERVED11[2]; 1922 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1923 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1924 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1925 __IM uint32_t RESERVED12[7]; 1926 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1927 __IM uint32_t RESERVED13; 1928 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1929 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1930 __IM uint32_t RESERVED14; 1931 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1932 __IM uint32_t RESERVED15[9]; 1933 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1934 __IM uint32_t RESERVED16[63]; 1935 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1936 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1937 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1938 __IM uint32_t RESERVED17[93]; 1939 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one 1940 to clear. */ 1941 __IM uint32_t RESERVED18[31]; 1942 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1943 __IM uint32_t RESERVED19; 1944 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1945 __IM uint32_t RESERVED20[3]; 1946 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1947 selected. */ 1948 __IM uint32_t RESERVED21[3]; 1949 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1950 __IM uint32_t RESERVED22; 1951 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1952 __IM uint32_t RESERVED23[7]; 1953 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1954 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1955 1956 1957 1958 /* =========================================================================================================================== */ 1959 /* ================ GPIOTE0_S ================ */ 1960 /* =========================================================================================================================== */ 1961 1962 1963 /** 1964 * @brief GPIO Tasks and Events 0 (GPIOTE0_S) 1965 */ 1966 1967 typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */ 1968 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1969 specified in CONFIG[n].PSEL. Action on pin 1970 is configured in CONFIG[n].POLARITY. */ 1971 __IM uint32_t RESERVED[4]; 1972 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1973 specified in CONFIG[n].PSEL. Action on pin 1974 is to set it high. */ 1975 __IM uint32_t RESERVED1[4]; 1976 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1977 specified in CONFIG[n].PSEL. Action on pin 1978 is to set it low. */ 1979 __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1980 for task OUT[n] */ 1981 __IM uint32_t RESERVED2[4]; 1982 __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 1983 for task SET[n] */ 1984 __IM uint32_t RESERVED3[4]; 1985 __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 1986 for task CLR[n] */ 1987 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1988 pin specified in CONFIG[n].PSEL */ 1989 __IM uint32_t RESERVED4[23]; 1990 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1991 with SENSE mechanism enabled */ 1992 __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1993 for event IN[n] */ 1994 __IM uint32_t RESERVED5[23]; 1995 __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 1996 __IM uint32_t RESERVED6[65]; 1997 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1998 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1999 __IM uint32_t RESERVED7[129]; 2000 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 2001 SET[n], and CLR[n] tasks and IN[n] event */ 2002 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 2003 2004 2005 2006 /* =========================================================================================================================== */ 2007 /* ================ SAADC_NS ================ */ 2008 /* =========================================================================================================================== */ 2009 2010 2011 /** 2012 * @brief Analog to Digital Converter 0 (SAADC_NS) 2013 */ 2014 2015 typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */ 2016 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 2017 RAM */ 2018 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 2019 are sampled */ 2020 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 2021 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 2022 __IM uint32_t RESERVED[28]; 2023 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2024 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ 2025 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 2026 __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ 2027 __IM uint32_t RESERVED1[28]; 2028 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 2029 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 2030 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 2031 on the mode, multiple conversions might 2032 be needed for a result to be transferred 2033 to RAM. */ 2034 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 2035 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 2036 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 2037 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 2038 __IM uint32_t RESERVED2[10]; 2039 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 2040 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 2041 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ 2042 __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ 2043 __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ 2044 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ 2045 __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ 2046 __IM uint32_t RESERVED3[74]; 2047 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2048 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2049 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2050 __IM uint32_t RESERVED4[61]; 2051 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 2052 __IM uint32_t RESERVED5[63]; 2053 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 2054 __IM uint32_t RESERVED6[3]; 2055 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 2056 __IM uint32_t RESERVED7[24]; 2057 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 2058 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 2059 not be combined with SCAN. The RESOLUTION 2060 is applied before averaging, thus for high 2061 OVERSAMPLE a higher RESOLUTION should be 2062 used. */ 2063 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 2064 __IM uint32_t RESERVED8[12]; 2065 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 2066 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 2067 2068 2069 2070 /* =========================================================================================================================== */ 2071 /* ================ TIMER0_NS ================ */ 2072 /* =========================================================================================================================== */ 2073 2074 2075 /** 2076 * @brief Timer/Counter 0 (TIMER0_NS) 2077 */ 2078 2079 typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */ 2080 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 2081 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 2082 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 2083 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 2084 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 2085 __IM uint32_t RESERVED[11]; 2086 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 2087 CC[n] register */ 2088 __IM uint32_t RESERVED1[10]; 2089 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2090 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2091 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 2092 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 2093 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 2094 for task SHUTDOWN */ 2095 __IM uint32_t RESERVED2[11]; 2096 __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 2097 for task CAPTURE[n] */ 2098 __IM uint32_t RESERVED3[26]; 2099 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 2100 match */ 2101 __IM uint32_t RESERVED4[26]; 2102 __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration 2103 for event COMPARE[n] */ 2104 __IM uint32_t RESERVED5[10]; 2105 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2106 __IM uint32_t RESERVED6[64]; 2107 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2108 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2109 __IM uint32_t RESERVED7[126]; 2110 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 2111 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 2112 __IM uint32_t RESERVED8; 2113 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 2114 __IOM uint32_t ONESHOTEN[6]; /*!< (@ 0x00000514) Description collection: Enable one-shot operation 2115 for Capture/Compare channel n */ 2116 __IM uint32_t RESERVED9[5]; 2117 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 2118 n */ 2119 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 2120 2121 2122 2123 /* =========================================================================================================================== */ 2124 /* ================ RTC0_NS ================ */ 2125 /* =========================================================================================================================== */ 2126 2127 2128 /** 2129 * @brief Real-time counter 0 (RTC0_NS) 2130 */ 2131 2132 typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */ 2133 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 2134 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 2135 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 2136 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 2137 __IM uint32_t RESERVED[28]; 2138 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2139 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2140 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 2141 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 2142 __IM uint32_t RESERVED1[28]; 2143 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 2144 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 2145 __IM uint32_t RESERVED2[14]; 2146 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 2147 match */ 2148 __IM uint32_t RESERVED3[12]; 2149 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 2150 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 2151 __IM uint32_t RESERVED4[14]; 2152 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 2153 for event COMPARE[n] */ 2154 __IM uint32_t RESERVED5[77]; 2155 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2156 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2157 __IM uint32_t RESERVED6[13]; 2158 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 2159 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 2160 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 2161 __IM uint32_t RESERVED7[110]; 2162 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 2163 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). 2164 Must be written when RTC is stopped. */ 2165 __IM uint32_t RESERVED8[13]; 2166 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 2167 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 2168 2169 2170 2171 /* =========================================================================================================================== */ 2172 /* ================ DPPIC_NS ================ */ 2173 /* =========================================================================================================================== */ 2174 2175 2176 /** 2177 * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS) 2178 */ 2179 2180 typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ 2181 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2182 __IM uint32_t RESERVED[20]; 2183 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 2184 __IM uint32_t RESERVED1[276]; 2185 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2186 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2187 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2188 __IM uint32_t RESERVED2[189]; 2189 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 2190 Writes to this register are ignored if either 2191 SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS 2192 is enabled */ 2193 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 2194 2195 2196 2197 /* =========================================================================================================================== */ 2198 /* ================ WDT_NS ================ */ 2199 /* =========================================================================================================================== */ 2200 2201 2202 /** 2203 * @brief Watchdog Timer 0 (WDT_NS) 2204 */ 2205 2206 typedef struct { /*!< (@ 0x40018000) WDT_NS Structure */ 2207 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 2208 __IM uint32_t RESERVED[31]; 2209 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2210 __IM uint32_t RESERVED1[31]; 2211 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 2212 __IM uint32_t RESERVED2[31]; 2213 __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 2214 __IM uint32_t RESERVED3[96]; 2215 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2216 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2217 __IM uint32_t RESERVED4[61]; 2218 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 2219 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 2220 __IM uint32_t RESERVED5[63]; 2221 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 2222 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 2223 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 2224 __IM uint32_t RESERVED6[60]; 2225 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 2226 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 2227 2228 2229 2230 /* =========================================================================================================================== */ 2231 /* ================ EGU0_NS ================ */ 2232 /* =========================================================================================================================== */ 2233 2234 2235 /** 2236 * @brief Event generator unit 0 (EGU0_NS) 2237 */ 2238 2239 typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 2240 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 2241 the corresponding TRIGGERED[n] event */ 2242 __IM uint32_t RESERVED[16]; 2243 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 2244 for task TRIGGER[n] */ 2245 __IM uint32_t RESERVED1[16]; 2246 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 2247 by triggering the corresponding TRIGGER[n] 2248 task */ 2249 __IM uint32_t RESERVED2[16]; 2250 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 2251 for event TRIGGERED[n] */ 2252 __IM uint32_t RESERVED3[80]; 2253 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2254 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2255 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2256 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 2257 2258 2259 2260 /* =========================================================================================================================== */ 2261 /* ================ PWM0_NS ================ */ 2262 /* =========================================================================================================================== */ 2263 2264 2265 /** 2266 * @brief Pulse width modulation unit 0 (PWM0_NS) 2267 */ 2268 2269 typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */ 2270 __IM uint32_t RESERVED; 2271 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2272 the end of current PWM period, and stops 2273 sequence playback */ 2274 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 2275 on all enabled channels from sequence n, 2276 and starts playing that sequence at the 2277 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2278 Causes PWM generation to start if not running. */ 2279 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2280 all enabled channels if DECODER.MODE=NextStep. 2281 Does not cause PWM generation to start if 2282 not running. */ 2283 __IM uint32_t RESERVED1[28]; 2284 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2285 __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration 2286 for task SEQSTART[n] */ 2287 __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */ 2288 __IM uint32_t RESERVED2[28]; 2289 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2290 are no longer generated */ 2291 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 2292 on sequence n */ 2293 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 2294 sequence n, when last value from RAM has 2295 been applied to wave counter */ 2296 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2297 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2298 of times defined in LOOP.CNT */ 2299 __IM uint32_t RESERVED3[25]; 2300 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 2301 __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration 2302 for event SEQSTARTED[n] */ 2303 __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration 2304 for event SEQEND[n] */ 2305 __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ 2306 __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ 2307 __IM uint32_t RESERVED4[24]; 2308 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2309 __IM uint32_t RESERVED5[63]; 2310 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2311 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2312 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2313 __IM uint32_t RESERVED6[125]; 2314 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2315 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2316 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2317 counts */ 2318 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2319 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2320 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 2321 __IM uint32_t RESERVED7[2]; 2322 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2323 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2324 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2325 2326 2327 2328 /* =========================================================================================================================== */ 2329 /* ================ PDM_NS ================ */ 2330 /* =========================================================================================================================== */ 2331 2332 2333 /** 2334 * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM_NS) 2335 */ 2336 2337 typedef struct { /*!< (@ 0x40026000) PDM_NS Structure */ 2338 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2339 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2340 __IM uint32_t RESERVED[30]; 2341 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2342 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2343 __IM uint32_t RESERVED1[30]; 2344 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2345 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2346 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2347 by SAMPLE.MAXCNT (or the last sample after 2348 a STOP task has been received) to Data RAM */ 2349 __IM uint32_t RESERVED2[29]; 2350 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 2351 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 2352 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ 2353 __IM uint32_t RESERVED3[93]; 2354 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2355 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2356 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2357 __IM uint32_t RESERVED4[125]; 2358 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2359 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2360 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2361 signals */ 2362 __IM uint32_t RESERVED5[3]; 2363 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2364 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2365 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 2366 sample rate. Change PDMCLKCTRL accordingly. */ 2367 __IM uint32_t RESERVED6[7]; 2368 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2369 __IM uint32_t RESERVED7[6]; 2370 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2371 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2372 2373 2374 2375 /* =========================================================================================================================== */ 2376 /* ================ I2S_NS ================ */ 2377 /* =========================================================================================================================== */ 2378 2379 2380 /** 2381 * @brief Inter-IC Sound 0 (I2S_NS) 2382 */ 2383 2384 typedef struct { /*!< (@ 0x40028000) I2S_NS Structure */ 2385 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2386 generator when this is enabled. */ 2387 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2388 Triggering this task will cause the STOPPED 2389 event to be generated. */ 2390 __IM uint32_t RESERVED[30]; 2391 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2392 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2393 __IM uint32_t RESERVED1[31]; 2394 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2395 double-buffers. When the I2S module is started 2396 and RX is enabled, this event will be generated 2397 for every RXTXD.MAXCNT words that are received 2398 on the SDIN pin. */ 2399 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2400 __IM uint32_t RESERVED2[2]; 2401 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2402 double-buffers. When the I2S module is started 2403 and TX is enabled, this event will be generated 2404 for every RXTXD.MAXCNT words that are sent 2405 on the SDOUT pin. */ 2406 __IM uint32_t RESERVED3[27]; 2407 __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ 2408 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ 2409 __IM uint32_t RESERVED4[2]; 2410 __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ 2411 __IM uint32_t RESERVED5[90]; 2412 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2413 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2414 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2415 __IM uint32_t RESERVED6[125]; 2416 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2417 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2418 __IM uint32_t RESERVED7[3]; 2419 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2420 __IM uint32_t RESERVED8; 2421 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2422 __IM uint32_t RESERVED9[3]; 2423 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2424 __IM uint32_t RESERVED10[3]; 2425 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2426 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2427 2428 2429 2430 /* =========================================================================================================================== */ 2431 /* ================ IPC_NS ================ */ 2432 /* =========================================================================================================================== */ 2433 2434 2435 /** 2436 * @brief Interprocessor communication 0 (IPC_NS) 2437 */ 2438 2439 typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ 2440 __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC 2441 channel enabled in SEND_CNF[n] */ 2442 __IM uint32_t RESERVED[24]; 2443 __IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 2444 for task SEND[n] */ 2445 __IM uint32_t RESERVED1[24]; 2446 __IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one 2447 or more of the enabled IPC channels in RECEIVE_CNF[n] */ 2448 __IM uint32_t RESERVED2[24]; 2449 __IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 2450 for event RECEIVE[n] */ 2451 __IM uint32_t RESERVED3[88]; 2452 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2453 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2454 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2455 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 2456 __IM uint32_t RESERVED4[128]; 2457 __IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration 2458 for TASKS_SEND[n] */ 2459 __IM uint32_t RESERVED5[24]; 2460 __IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration 2461 for EVENTS_RECEIVE[n] */ 2462 __IM uint32_t RESERVED6[24]; 2463 __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory */ 2464 } NRF_IPC_Type; /*!< Size = 1568 (0x620) */ 2465 2466 2467 2468 /* =========================================================================================================================== */ 2469 /* ================ FPU_NS ================ */ 2470 /* =========================================================================================================================== */ 2471 2472 2473 /** 2474 * @brief FPU (FPU_NS) 2475 */ 2476 2477 typedef struct { /*!< (@ 0x4002C000) FPU_NS Structure */ 2478 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2479 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2480 2481 2482 2483 /* =========================================================================================================================== */ 2484 /* ================ APPROTECT_NS ================ */ 2485 /* =========================================================================================================================== */ 2486 2487 2488 /** 2489 * @brief Access Port Protection 0 (APPROTECT_NS) 2490 */ 2491 2492 typedef struct { /*!< (@ 0x40039000) APPROTECT_NS Structure */ 2493 __IM uint32_t RESERVED[896]; 2494 __IOM APPROTECT_SECUREAPPROTECT_Type SECUREAPPROTECT;/*!< (@ 0x00000E00) Unspecified */ 2495 __IM uint32_t RESERVED1[3]; 2496 __IOM APPROTECT_APPROTECT_Type APPROTECT; /*!< (@ 0x00000E10) Unspecified */ 2497 } NRF_APPROTECT_Type; /*!< Size = 3604 (0xe14) */ 2498 2499 2500 2501 /* =========================================================================================================================== */ 2502 /* ================ KMU_NS ================ */ 2503 /* =========================================================================================================================== */ 2504 2505 2506 /** 2507 * @brief Key management unit 0 (KMU_NS) 2508 */ 2509 2510 typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */ 2511 __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */ 2512 __IM uint32_t RESERVED[63]; 2513 __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key slot successfully pushed over secure APB */ 2514 __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked 2515 for selection */ 2516 __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address 2517 defined, or error during push operation */ 2518 __IM uint32_t RESERVED1[125]; 2519 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2520 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2521 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2522 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 2523 __IM uint32_t RESERVED2[63]; 2524 __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */ 2525 __IM uint32_t RESERVED3[60]; 2526 __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed 2527 over secure APB when TASKS_PUSH_KEYSLOT 2528 is started */ 2529 } NRF_KMU_Type; /*!< Size = 1284 (0x504) */ 2530 2531 2532 2533 /* =========================================================================================================================== */ 2534 /* ================ NVMC_NS ================ */ 2535 /* =========================================================================================================================== */ 2536 2537 2538 /** 2539 * @brief Non-volatile memory controller 0 (NVMC_NS) 2540 */ 2541 2542 typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 2543 __IM uint32_t RESERVED[256]; 2544 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2545 __IM uint32_t RESERVED1; 2546 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 2547 __IM uint32_t RESERVED2[62]; 2548 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2549 __IM uint32_t RESERVED3; 2550 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2551 __IM uint32_t RESERVED4[3]; 2552 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 2553 __IM uint32_t RESERVED5[8]; 2554 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 2555 __IM uint32_t RESERVED6; 2556 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 2557 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 2558 __IM uint32_t RESERVED7[13]; 2559 __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ 2560 __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 2561 } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ 2562 2563 2564 2565 /* =========================================================================================================================== */ 2566 /* ================ VMC_NS ================ */ 2567 /* =========================================================================================================================== */ 2568 2569 2570 /** 2571 * @brief Volatile Memory controller 0 (VMC_NS) 2572 */ 2573 2574 typedef struct { /*!< (@ 0x4003A000) VMC_NS Structure */ 2575 __IM uint32_t RESERVED[384]; 2576 __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */ 2577 } NRF_VMC_Type; /*!< Size = 1664 (0x680) */ 2578 2579 2580 2581 /* =========================================================================================================================== */ 2582 /* ================ CRYPTOCELL_S ================ */ 2583 /* =========================================================================================================================== */ 2584 2585 2586 /** 2587 * @brief CRYPTOCELL register interface (CRYPTOCELL_S) 2588 */ 2589 2590 typedef struct { /*!< (@ 0x50840000) CRYPTOCELL_S Structure */ 2591 __IM uint32_t RESERVED[320]; 2592 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem. */ 2593 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 2594 2595 2596 2597 /* =========================================================================================================================== */ 2598 /* ================ CC_AES_S ================ */ 2599 /* =========================================================================================================================== */ 2600 2601 2602 /** 2603 * @brief CRYPTOCELL AES engine (CC_AES_S) 2604 */ 2605 2606 typedef struct { /*!< (@ 0x50841000) CC_AES_S Structure */ 2607 __IM uint32_t RESERVED[256]; 2608 __OM uint32_t AES_KEY_0[8]; /*!< (@ 0x00000400) Description collection: AES key value to use. 2609 The initial AES_KEY_0[0] register holds 2610 the least significant bits [31:0] of the 2611 key value. */ 2612 __IM uint32_t RESERVED1[8]; 2613 __IOM uint32_t AES_IV_0[4]; /*!< (@ 0x00000440) Description collection: AES Initialization Vector 2614 (IV) to use. The initial AES_IV_0[0] register 2615 holds the least significant bits [31:0] 2616 of the IV. */ 2617 __IM uint32_t RESERVED2[4]; 2618 __IOM uint32_t AES_CTR[4]; /*!< (@ 0x00000460) Description collection: AES counter (CTR) to 2619 use. The initial AES_CTR[0] register holds 2620 the least significant bits [31:0] of the 2621 CTR. */ 2622 __IM uint32_t AES_BUSY; /*!< (@ 0x00000470) Status register for AES engine activity. */ 2623 __IM uint32_t RESERVED3; 2624 __OM uint32_t AES_SK; /*!< (@ 0x00000478) Writing to this address trigger sampling of the 2625 HW key to the AES_KEY_0 register */ 2626 __OM uint32_t AES_CMAC_INIT; /*!< (@ 0x0000047C) Writing to this address triggers the AES engine 2627 to generate K1 and K2 for AES-CMAC operations. */ 2628 __IM uint32_t RESERVED4[15]; 2629 __IOM uint32_t AES_REMAINING_BYTES; /*!< (@ 0x000004BC) This register should be set with the amount of 2630 remaining bytes until the end of the current 2631 AES operation. */ 2632 __IOM uint32_t AES_CONTROL; /*!< (@ 0x000004C0) Control the AES engine behavior. */ 2633 __IM uint32_t RESERVED5; 2634 __IM uint32_t AES_HW_FLAGS; /*!< (@ 0x000004C8) Hardware configuration of the AES engine. Reset 2635 value holds the supported features. */ 2636 __IM uint32_t RESERVED6[3]; 2637 __IOM uint32_t AES_CTR_NO_INCREMENT; /*!< (@ 0x000004D8) This register enables the AES CTR no increment 2638 mode in which the counter mode is not incremented 2639 between two blocks */ 2640 __IM uint32_t RESERVED7[6]; 2641 __OM uint32_t AES_SW_RESET; /*!< (@ 0x000004F4) Reset the AES engine. */ 2642 __IM uint32_t RESERVED8[11]; 2643 __OM uint32_t AES_CMAC_SIZE0_KICK; /*!< (@ 0x00000524) Writing to this address triggers the AES engine 2644 to perform a CMAC operation with size 0. 2645 The CMAC result can be read from the AES_IV_0 2646 register. */ 2647 } NRF_CC_AES_Type; /*!< Size = 1320 (0x528) */ 2648 2649 2650 2651 /* =========================================================================================================================== */ 2652 /* ================ CC_AHB_S ================ */ 2653 /* =========================================================================================================================== */ 2654 2655 2656 /** 2657 * @brief CRYPTOCELL AHB interface (CC_AHB_S) 2658 */ 2659 2660 typedef struct { /*!< (@ 0x50841000) CC_AHB_S Structure */ 2661 __IM uint32_t RESERVED[704]; 2662 __IOM uint32_t AHBM_SINGLES; /*!< (@ 0x00000B00) This register forces the AHB transactions from 2663 CRYPTOCELL master to be always singles. */ 2664 __IOM uint32_t AHBM_HPROT; /*!< (@ 0x00000B04) This register holds the AHB HPROT value */ 2665 __IOM uint32_t AHBM_HMASTLOCK; /*!< (@ 0x00000B08) This register holds AHB HMASTLOCK value */ 2666 __IOM uint32_t AHBM_HNONSEC; /*!< (@ 0x00000B0C) This register holds AHB HNONSEC value */ 2667 } NRF_CC_AHB_Type; /*!< Size = 2832 (0xb10) */ 2668 2669 2670 2671 /* =========================================================================================================================== */ 2672 /* ================ CC_CHACHA_S ================ */ 2673 /* =========================================================================================================================== */ 2674 2675 2676 /** 2677 * @brief CRYPTOCELL CHACHA engine (CC_CHACHA_S) 2678 */ 2679 2680 typedef struct { /*!< (@ 0x50841000) CC_CHACHA_S Structure */ 2681 __IM uint32_t RESERVED[224]; 2682 __IOM uint32_t CHACHA_CONTROL; /*!< (@ 0x00000380) Control the CHACHA engine behavior. */ 2683 __IM uint32_t CHACHA_VERSION; /*!< (@ 0x00000384) CHACHA engine HW version */ 2684 __OM uint32_t CHACHA_KEY[8]; /*!< (@ 0x00000388) Description collection: CHACHA key value to use. 2685 The initial CHACHA_KEY[0] register holds 2686 the least significant bits [31:0] of the 2687 key value. */ 2688 __IOM uint32_t CHACHA_IV[2]; /*!< (@ 0x000003A8) Description collection: CHACHA Initialization 2689 Vector (IV) to use. The IV is also known 2690 as the nonce. */ 2691 __IM uint32_t CHACHA_BUSY; /*!< (@ 0x000003B0) Status register for CHACHA engine activity. */ 2692 __IM uint32_t CHACHA_HW_FLAGS; /*!< (@ 0x000003B4) Hardware configuration of the CHACHA engine. 2693 Reset value holds the supported features. */ 2694 __IOM uint32_t CHACHA_BLOCK_CNT_LSB; /*!< (@ 0x000003B8) Store the LSB value of the block counter, in 2695 order to support suspend/resume of operation */ 2696 __IOM uint32_t CHACHA_BLOCK_CNT_MSB; /*!< (@ 0x000003BC) Store the MSB value of the block counter, in 2697 order to support suspend/resume of operation */ 2698 __OM uint32_t CHACHA_SW_RESET; /*!< (@ 0x000003C0) Reset the CHACHA engine. */ 2699 __IM uint32_t CHACHA_POLY1305_KEY[8]; /*!< (@ 0x000003C4) Description collection: The auto-generated key 2700 to use in Poly1305 MAC calculation. The 2701 initial CHACHA_POLY1305_KEY[0] register 2702 holds the least significant bits [31:0] 2703 of the key value. */ 2704 __IOM uint32_t CHACHA_ENDIANNESS; /*!< (@ 0x000003E4) CHACHA engine data order configuration. */ 2705 __IM uint32_t CHACHA_DEBUG; /*!< (@ 0x000003E8) Debug register for the CHACHA engine */ 2706 } NRF_CC_CHACHA_Type; /*!< Size = 1004 (0x3ec) */ 2707 2708 2709 2710 /* =========================================================================================================================== */ 2711 /* ================ CC_CTL_S ================ */ 2712 /* =========================================================================================================================== */ 2713 2714 2715 /** 2716 * @brief CRYPTOCELL CTL interface (CC_CTL_S) 2717 */ 2718 2719 typedef struct { /*!< (@ 0x50841000) CC_CTL_S Structure */ 2720 __IM uint32_t RESERVED[576]; 2721 __OM uint32_t CRYPTO_CTL; /*!< (@ 0x00000900) Defines the cryptographic flow. */ 2722 __IM uint32_t RESERVED1[3]; 2723 __IM uint32_t CRYPTO_BUSY; /*!< (@ 0x00000910) Status register for cryptographic cores engine 2724 activity. */ 2725 __IM uint32_t RESERVED2[2]; 2726 __IM uint32_t HASH_BUSY; /*!< (@ 0x0000091C) Status register for HASH engine activity. */ 2727 __IM uint32_t RESERVED3[4]; 2728 __IOM uint32_t CONTEXT_ID; /*!< (@ 0x00000930) A general-purpose read/write register. */ 2729 } NRF_CC_CTL_Type; /*!< Size = 2356 (0x934) */ 2730 2731 2732 2733 /* =========================================================================================================================== */ 2734 /* ================ CC_DIN_S ================ */ 2735 /* =========================================================================================================================== */ 2736 2737 2738 /** 2739 * @brief CRYPTOCELL Data IN interface (CC_DIN_S) 2740 */ 2741 2742 typedef struct { /*!< (@ 0x50841000) CC_DIN_S Structure */ 2743 __IM uint32_t RESERVED[768]; 2744 __OM uint32_t DIN_BUFFER; /*!< (@ 0x00000C00) Used by CPU to write data directly to the DIN 2745 buffer, which is then sent to the cryptographic 2746 engines for processing. */ 2747 __IM uint32_t RESERVED1[7]; 2748 __IM uint32_t DIN_DMA_MEM_BUSY; /*!< (@ 0x00000C20) Status register for DIN DMA engine activity when 2749 accessing memory. */ 2750 __IM uint32_t RESERVED2; 2751 __OM uint32_t SRC_MEM_ADDR; /*!< (@ 0x00000C28) Data source address in memory. */ 2752 __OM uint32_t SRC_MEM_SIZE; /*!< (@ 0x00000C2C) The number of bytes to be read from memory. Writing 2753 to this register triggers the DMA operation. */ 2754 __IOM uint32_t SRC_SRAM_ADDR; /*!< (@ 0x00000C30) Data source address in RNG SRAM. */ 2755 __OM uint32_t SRC_SRAM_SIZE; /*!< (@ 0x00000C34) The number of bytes to be read from RNG SRAM. 2756 Writing to this register triggers the DMA 2757 operation. */ 2758 __IM uint32_t DIN_DMA_SRAM_BUSY; /*!< (@ 0x00000C38) Status register for DIN DMA engine activity when 2759 accessing RNG SRAM. */ 2760 __IOM uint32_t DIN_DMA_SRAM_ENDIANNESS; /*!< (@ 0x00000C3C) Configure the endianness of DIN DMA transactions 2761 towards RNG SRAM. */ 2762 __IM uint32_t RESERVED3; 2763 __OM uint32_t DIN_SW_RESET; /*!< (@ 0x00000C44) Reset the DIN DMA engine. */ 2764 __OM uint32_t DIN_CPU_DATA; /*!< (@ 0x00000C48) Specifies the number of bytes the CPU will write 2765 to the DIN_BUFFER, ensuring the cryptographic 2766 engine processes the correct amount of data. */ 2767 __OM uint32_t DIN_WRITE_ALIGN; /*!< (@ 0x00000C4C) Indicates that the next CPU write to the DIN_BUFFER 2768 is the last in the sequence. This is needed 2769 only when the data size is NOT modulo 4 2770 (e.g. HASH padding). */ 2771 __IM uint32_t DIN_FIFO_EMPTY; /*!< (@ 0x00000C50) Register indicating if DIN FIFO is empty and 2772 if more data can be accepted. */ 2773 __IM uint32_t RESERVED4; 2774 __OM uint32_t DIN_FIFO_RESET; /*!< (@ 0x00000C58) Reset the DIN FIFO, effectively clearing the 2775 FIFO for new data. */ 2776 } NRF_CC_DIN_Type; /*!< Size = 3164 (0xc5c) */ 2777 2778 2779 2780 /* =========================================================================================================================== */ 2781 /* ================ CC_DOUT_S ================ */ 2782 /* =========================================================================================================================== */ 2783 2784 2785 /** 2786 * @brief CRYPTOCELL Data OUT interface (CC_DOUT_S) 2787 */ 2788 2789 typedef struct { /*!< (@ 0x50841000) CC_DOUT_S Structure */ 2790 __IM uint32_t RESERVED[768]; 2791 __IM uint32_t DOUT_BUFFER; /*!< (@ 0x00000C00) Cryptographic results directly accessible by 2792 the CPU. */ 2793 __IM uint32_t RESERVED1[71]; 2794 __IM uint32_t DOUT_DMA_MEM_BUSY; /*!< (@ 0x00000D20) Status register for DOUT DMA engine activity 2795 when accessing memory. */ 2796 __IM uint32_t RESERVED2; 2797 __OM uint32_t DST_MEM_ADDR; /*!< (@ 0x00000D28) Data destination address in memory. */ 2798 __OM uint32_t DST_MEM_SIZE; /*!< (@ 0x00000D2C) The number of bytes to be written to memory. */ 2799 __IOM uint32_t DST_SRAM_ADDR; /*!< (@ 0x00000D30) Data destination address in RNG SRAM. */ 2800 __OM uint32_t DST_SRAM_SIZE; /*!< (@ 0x00000D34) The number of bytes to be written to RNG SRAM. */ 2801 __IM uint32_t DOUT_DMA_SRAM_BUSY; /*!< (@ 0x00000D38) Status register for DOUT DMA engine activity 2802 when accessing RNG SRAM. */ 2803 __IOM uint32_t DOUT_DMA_SRAM_ENDIANNESS; /*!< (@ 0x00000D3C) Configure the endianness of DOUT DMA transactions 2804 towards RNG SRAM. */ 2805 __IM uint32_t RESERVED3; 2806 __OM uint32_t DOUT_READ_ALIGN; /*!< (@ 0x00000D44) Indication that the next CPU read from the DOUT_BUFFER 2807 is the last in the sequence. This is needed 2808 only when the data size is NOT modulo 4 2809 (e.g. HASH padding). */ 2810 __IM uint32_t RESERVED4[2]; 2811 __IM uint32_t DOUT_FIFO_EMPTY; /*!< (@ 0x00000D50) Register indicating if DOUT FIFO is empty or 2812 if more data will come. */ 2813 __IM uint32_t RESERVED5; 2814 __OM uint32_t DOUT_SW_RESET; /*!< (@ 0x00000D58) Reset the DOUT DMA engine. */ 2815 } NRF_CC_DOUT_Type; /*!< Size = 3420 (0xd5c) */ 2816 2817 2818 2819 /* =========================================================================================================================== */ 2820 /* ================ CC_HASH_S ================ */ 2821 /* =========================================================================================================================== */ 2822 2823 2824 /** 2825 * @brief CRYPTOCELL HASH engine (CC_HASH_S) 2826 */ 2827 2828 typedef struct { /*!< (@ 0x50841000) CC_HASH_S Structure */ 2829 __IM uint32_t RESERVED[400]; 2830 __IOM uint32_t HASH_H[8]; /*!< (@ 0x00000640) Description collection: HASH_H value registers. 2831 The initial HASH_H[0] register holds the 2832 least significant bits [31:0] of the value. */ 2833 __IM uint32_t RESERVED1[9]; 2834 __OM uint32_t HASH_PAD_AUTO; /*!< (@ 0x00000684) Configure the HASH engine to automatically pad 2835 data at the end of the DMA transfer to complete 2836 the digest operation. */ 2837 __IM uint32_t RESERVED2[3]; 2838 __OM uint32_t HASH_INIT_STATE; /*!< (@ 0x00000694) Configure HASH engine initial state registers. */ 2839 __IM uint32_t RESERVED3[70]; 2840 __IM uint32_t HASH_VERSION; /*!< (@ 0x000007B0) HASH engine HW version */ 2841 __IM uint32_t RESERVED4[3]; 2842 __IOM uint32_t HASH_CONTROL; /*!< (@ 0x000007C0) Control the HASH engine behavior. */ 2843 __IOM uint32_t HASH_PAD; /*!< (@ 0x000007C4) Enable the hardware padding feature of the HASH 2844 engine. */ 2845 __IOM uint32_t HASH_PAD_FORCE; /*!< (@ 0x000007C8) Force the hardware padding operation to trigger 2846 if the input data length is zero bytes. */ 2847 __IOM uint32_t HASH_CUR_LEN_0; /*!< (@ 0x000007CC) Bits [31:0] of the number of bytes that have 2848 been digested so far. */ 2849 __IOM uint32_t HASH_CUR_LEN_1; /*!< (@ 0x000007D0) Bits [63:32] of the number of bytes that have 2850 been digested so far. */ 2851 __IM uint32_t RESERVED5[2]; 2852 __IM uint32_t HASH_HW_FLAGS; /*!< (@ 0x000007DC) Hardware configuration of the HASH engine. Reset 2853 value holds the supported features. */ 2854 __IM uint32_t RESERVED6; 2855 __OM uint32_t HASH_SW_RESET; /*!< (@ 0x000007E4) Reset the HASH engine. */ 2856 __IOM uint32_t HASH_ENDIANNESS; /*!< (@ 0x000007E8) Configure the endianness of HASH data and padding 2857 generation. */ 2858 } NRF_CC_HASH_Type; /*!< Size = 2028 (0x7ec) */ 2859 2860 2861 2862 /* =========================================================================================================================== */ 2863 /* ================ CC_HOST_RGF_S ================ */ 2864 /* =========================================================================================================================== */ 2865 2866 2867 /** 2868 * @brief CRYPTOCELL HOST register interface (CC_HOST_RGF_S) 2869 */ 2870 2871 typedef struct { /*!< (@ 0x50841000) CC_HOST_RGF_S Structure */ 2872 __IM uint32_t RESERVED[640]; 2873 __IM uint32_t IRR; /*!< (@ 0x00000A00) Interrupt request register. Each bit of this 2874 register holds the interrupt status of a 2875 single interrupt source. If corresponding 2876 IMR bit is unmasked, an interrupt is generated. */ 2877 __IOM uint32_t IMR; /*!< (@ 0x00000A04) Interrupt mask register. Each bit of this register 2878 holds the mask of a single interrupt source. */ 2879 __OM uint32_t ICR; /*!< (@ 0x00000A08) Interrupt clear register. Writing a 1 bit into 2880 a field in this register will clear the 2881 corresponding bit in IRR. */ 2882 __IOM uint32_t ENDIANNESS; /*!< (@ 0x00000A0C) This register defines the endianness of the Host-accessible 2883 registers, and can only be written once. */ 2884 __IM uint32_t RESERVED1[5]; 2885 __IM uint32_t HOST_SIGNATURE; /*!< (@ 0x00000A24) This register holds the CRYPTOCELL subsystem 2886 signature. See reset value. */ 2887 __IM uint32_t HOST_BOOT; /*!< (@ 0x00000A28) Hardware configuration of the CRYPTOCELL subsystem. 2888 Reset value holds the supported features. */ 2889 __IM uint32_t RESERVED2[3]; 2890 __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00000A38) AES hardware key select. */ 2891 __IM uint32_t RESERVED3[4]; 2892 __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00000A4C) This write-once register is the K_PRTL lock register. 2893 When this register is set, K_PRTL cannot 2894 be used and a zeroed key will be used instead. 2895 The value of this register is saved in the 2896 CRYPTOCELL AO power domain. */ 2897 __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00000A50) This register holds bits 31:0 of K_DR. The value 2898 of this register is saved in the CRYPTOCELL 2899 AO power domain. Reading from this address 2900 returns the K_DR valid status indicating 2901 if K_DR is successfully retained. */ 2902 __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00000A54) This register holds bits 63:32 of K_DR. The value 2903 of this register is saved in the CRYPTOCELL 2904 AO power domain. */ 2905 __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00000A58) This register holds bits 95:64 of K_DR. The value 2906 of this register is saved in the CRYPTOCELL 2907 AO power domain. */ 2908 __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00000A5C) This register holds bits 127:96 of K_DR. The 2909 value of this register is saved in the CRYPTOCELL 2910 AO power domain. */ 2911 __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00000A60) Controls life-cycle state (LCS) for CRYPTOCELL 2912 subsystem */ 2913 } NRF_CC_HOST_RGF_Type; /*!< Size = 2660 (0xa64) */ 2914 2915 2916 2917 /* =========================================================================================================================== */ 2918 /* ================ CC_MISC_S ================ */ 2919 /* =========================================================================================================================== */ 2920 2921 2922 /** 2923 * @brief CRYPTOCELL MISC interface (CC_MISC_S) 2924 */ 2925 2926 typedef struct { /*!< (@ 0x50841000) CC_MISC_S Structure */ 2927 __IM uint32_t RESERVED[516]; 2928 __OM uint32_t AES_CLK; /*!< (@ 0x00000810) Clock control for the AES engine. */ 2929 __IM uint32_t RESERVED1; 2930 __OM uint32_t HASH_CLK; /*!< (@ 0x00000818) Clock control for the HASH engine. */ 2931 __OM uint32_t PKA_CLK; /*!< (@ 0x0000081C) Clock control for the PKA engine. */ 2932 __OM uint32_t DMA_CLK; /*!< (@ 0x00000820) Clock control for the DMA engines. */ 2933 __IM uint32_t CLK_STATUS; /*!< (@ 0x00000824) CRYPTOCELL clocks status register. */ 2934 __IM uint32_t RESERVED2[12]; 2935 __OM uint32_t CHACHA_CLK; /*!< (@ 0x00000858) Clock control for the CHACHA engine. */ 2936 } NRF_CC_MISC_Type; /*!< Size = 2140 (0x85c) */ 2937 2938 2939 2940 /* =========================================================================================================================== */ 2941 /* ================ CC_PKA_S ================ */ 2942 /* =========================================================================================================================== */ 2943 2944 2945 /** 2946 * @brief CRYPTOCELL PKA engine (CC_PKA_S) 2947 */ 2948 2949 typedef struct { /*!< (@ 0x50841000) CC_PKA_S Structure */ 2950 __IOM uint32_t MEMORY_MAP[32]; /*!< (@ 0x00000000) Description collection: Register for mapping 2951 the virtual register R[n] to a physical 2952 address in the PKA SRAM. */ 2953 __IOM uint32_t OPCODE; /*!< (@ 0x00000080) Operation code to be executed by the PKA engine. 2954 Writing to this register triggers the PKA 2955 operation. */ 2956 __IOM uint32_t N_NP_T0_T1_ADDR; /*!< (@ 0x00000084) This register defines the N, Np, T0, and T1 virtual 2957 register index. */ 2958 __IM uint32_t PKA_STATUS; /*!< (@ 0x00000088) This register holds the status for the PKA pipeline. */ 2959 __OM uint32_t PKA_SW_RESET; /*!< (@ 0x0000008C) Reset the PKA engine. */ 2960 __IOM uint32_t PKA_L[8]; /*!< (@ 0x00000090) Description collection: This register holds the 2961 operands bit size. */ 2962 __IM uint32_t PKA_PIPE; /*!< (@ 0x000000B0) Status register indicating if the PKA pipeline 2963 is ready to receive a new OPCODE. */ 2964 __IM uint32_t PKA_DONE; /*!< (@ 0x000000B4) Status register indicating if the PKA operation 2965 has been completed. */ 2966 __IM uint32_t RESERVED[3]; 2967 __IM uint32_t PKA_VERSION; /*!< (@ 0x000000C4) PKA engine HW version. Reset value holds the 2968 version. */ 2969 __IM uint32_t RESERVED1[3]; 2970 __OM uint32_t PKA_SRAM_WADDR; /*!< (@ 0x000000D4) Start address in PKA SRAM for subsequent write 2971 transactions. */ 2972 __OM uint32_t PKA_SRAM_WDATA; /*!< (@ 0x000000D8) Write data to PKA SRAM. Writing to this register 2973 triggers a DMA transaction writing data 2974 into PKA SRAM. The DMA address offset is 2975 automatically incremented during write. */ 2976 __IM uint32_t PKA_SRAM_RDATA; /*!< (@ 0x000000DC) Read data from PKA SRAM. Reading from this register 2977 triggers a DMA transaction read data from 2978 PKA SRAM. The DMA address offset is automatically 2979 incremented during read. */ 2980 __OM uint32_t PKA_SRAM_WCLEAR; /*!< (@ 0x000000E0) Register for clearing PKA SRAM write buffer. */ 2981 __OM uint32_t PKA_SRAM_RADDR; /*!< (@ 0x000000E4) Start address in PKA SRAM for subsequent read 2982 transactions. */ 2983 } NRF_CC_PKA_Type; /*!< Size = 232 (0xe8) */ 2984 2985 2986 2987 /* =========================================================================================================================== */ 2988 /* ================ CC_RNG_S ================ */ 2989 /* =========================================================================================================================== */ 2990 2991 2992 /** 2993 * @brief CRYPTOCELL RNG engine (CC_RNG_S) 2994 */ 2995 2996 typedef struct { /*!< (@ 0x50841000) CC_RNG_S Structure */ 2997 __IM uint32_t RESERVED[64]; 2998 __IOM uint32_t RNG_IMR; /*!< (@ 0x00000100) Interrupt mask register. Each bit of this register 2999 holds the mask of a single interrupt source. */ 3000 __IM uint32_t RNG_ISR; /*!< (@ 0x00000104) Interrupt status register. Each bit of this register 3001 holds the interrupt status of a single interrupt 3002 source. If corresponding RNG_IMR bit is 3003 unmasked, an interrupt is generated. */ 3004 __OM uint32_t RNG_ICR; /*!< (@ 0x00000108) Interrupt clear register. Writing a 1 bit into 3005 a field in this register will clear the 3006 corresponding bit in RNG_ISR. */ 3007 __IOM uint32_t TRNG_CONFIG; /*!< (@ 0x0000010C) TRNG ring oscillator length configuration */ 3008 __IM uint32_t TRNG_VALID; /*!< (@ 0x00000110) This register indicates if TRNG entropy collection 3009 is valid. */ 3010 __IM uint32_t EHR_DATA[6]; /*!< (@ 0x00000114) Description collection: The entropy holding registers 3011 (EHR) hold 192-bits random data collected 3012 by the TRNG. The initial EHR_DATA[0] register 3013 holds the least significant bits [31:0] 3014 of the random data value. */ 3015 __IOM uint32_t NOISE_SOURCE; /*!< (@ 0x0000012C) This register controls the ring oscillator circuit 3016 used as a noise source. */ 3017 __IOM uint32_t SAMPLE_CNT; /*!< (@ 0x00000130) Sample count defining the number of CPU clock 3018 cycles between two consecutive noise source 3019 samples. */ 3020 __IOM uint32_t AUTOCORR_STATISTIC; /*!< (@ 0x00000134) Statistics counter for autocorrelation test activations. 3021 Statistics collection is stopped if one 3022 of the counters reach its limit of all ones. */ 3023 __IOM uint32_t TRNG_DEBUG; /*!< (@ 0x00000138) Debug register for the TRNG. This register is 3024 used to bypass TRNG tests in hardware. */ 3025 __IM uint32_t RESERVED1; 3026 __OM uint32_t RNG_SW_RESET; /*!< (@ 0x00000140) Reset the RNG engine. */ 3027 __IM uint32_t RESERVED2[29]; 3028 __IM uint32_t RNG_BUSY; /*!< (@ 0x000001B8) Status register for RNG engine activity. */ 3029 __OM uint32_t TRNG_RESET; /*!< (@ 0x000001BC) Reset the TRNG, including internal counter of 3030 collected bits and registers EHR_DATA and 3031 TRNG_VALID. */ 3032 __IM uint32_t RNG_HW_FLAGS; /*!< (@ 0x000001C0) Hardware configuration of RNG engine. Reset value 3033 holds the supported features. */ 3034 __OM uint32_t RNG_CLK; /*!< (@ 0x000001C4) Control clock for the RNG engine. */ 3035 __IOM uint32_t RNG_DMA; /*!< (@ 0x000001C8) Writing to this register enables the RNG DMA 3036 engine. */ 3037 __IOM uint32_t RNG_DMA_ROSC_LEN; /*!< (@ 0x000001CC) This register defines which ring oscillator length 3038 configuration should be used when using 3039 the RNG DMA engine. */ 3040 __IOM uint32_t RNG_DMA_SRAM_ADDR; /*!< (@ 0x000001D0) This register defines the start address in TRNG 3041 SRAM for the TRNG data to be collected by 3042 the RNG DMA engine. */ 3043 __IOM uint32_t RNG_DMA_SAMPLES_NUM; /*!< (@ 0x000001D4) This register defines the number of 192-bits 3044 samples that the RNG DMA engine collects 3045 per run. */ 3046 __IOM uint32_t RNG_WATCHDOG_VAL; /*!< (@ 0x000001D8) This register defines the maximum number of CPU 3047 clock cycles per TRNG collection of 192-bits 3048 samples. If the number of cycles for a collection 3049 exceeds this threshold the WATCHDOG interrupt 3050 is triggered. */ 3051 __IM uint32_t RNG_DMA_BUSY; /*!< (@ 0x000001DC) Status register for RNG DMA engine activity. */ 3052 } NRF_CC_RNG_Type; /*!< Size = 480 (0x1e0) */ 3053 3054 3055 3056 /* =========================================================================================================================== */ 3057 /* ================ CC_RNG_SRAM_S ================ */ 3058 /* =========================================================================================================================== */ 3059 3060 3061 /** 3062 * @brief CRYPTOCELL RNG SRAM interface (CC_RNG_SRAM_S) 3063 */ 3064 3065 typedef struct { /*!< (@ 0x50841000) CC_RNG_SRAM_S Structure */ 3066 __IM uint32_t RESERVED[960]; 3067 __IOM uint32_t SRAM_DATA; /*!< (@ 0x00000F00) Read/Write data from RNG SRAM */ 3068 __OM uint32_t SRAM_ADDR; /*!< (@ 0x00000F04) First address given to RNG SRAM DMA for read/write 3069 transactions from/to RNG SRAM. */ 3070 __IM uint32_t SRAM_DATA_READY; /*!< (@ 0x00000F08) RNG SRAM DMA engine is ready to read/write from/to 3071 RNG SRAM. */ 3072 } NRF_CC_RNG_SRAM_Type; /*!< Size = 3852 (0xf0c) */ 3073 3074 3075 3076 /* =========================================================================================================================== */ 3077 /* ================ P0_NS ================ */ 3078 /* =========================================================================================================================== */ 3079 3080 3081 /** 3082 * @brief GPIO Port 0 (P0_NS) 3083 */ 3084 3085 typedef struct { /*!< (@ 0x40842500) P0_NS Structure */ 3086 __IM uint32_t RESERVED; 3087 __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 3088 __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 3089 __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 3090 __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 3091 __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 3092 __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 3093 __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 3094 __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 3095 have met the criteria set in the PIN_CNF[n].SENSE 3096 registers */ 3097 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior 3098 and LDETECT mode (For non-secure pin only) */ 3099 __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior 3100 and LDETECT mode (For secure pin only) */ 3101 __IM uint32_t RESERVED1[117]; 3102 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 3103 pins */ 3104 } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 3105 3106 3107 /** @} */ /* End of group Device_Peripheral_peripherals */ 3108 3109 3110 /* =========================================================================================================================== */ 3111 /* ================ Device Specific Peripheral Address Map ================ */ 3112 /* =========================================================================================================================== */ 3113 3114 3115 /** @addtogroup Device_Peripheral_peripheralAddr 3116 * @{ 3117 */ 3118 3119 #define NRF_FICR_S_BASE 0x00FF0000UL 3120 #define NRF_UICR_S_BASE 0x00FF8000UL 3121 #define NRF_ETM_NS_BASE 0xE0041000UL 3122 #define NRF_ETB_NS_BASE 0xE0051000UL 3123 #define NRF_TPIU_NS_BASE 0xE0054000UL 3124 #define NRF_ATBREPLICATOR_NS_BASE 0xE0058000UL 3125 #define NRF_ATBFUNNEL1_NS_BASE 0xE005A000UL 3126 #define NRF_ATBFUNNEL2_NS_BASE 0xE005B000UL 3127 #define NRF_TAD_S_BASE 0xE0080000UL 3128 #define NRF_SPU_S_BASE 0x50003000UL 3129 #define NRF_REGULATORS_NS_BASE 0x40004000UL 3130 #define NRF_REGULATORS_S_BASE 0x50004000UL 3131 #define NRF_CLOCK_NS_BASE 0x40005000UL 3132 #define NRF_POWER_NS_BASE 0x40005000UL 3133 #define NRF_CLOCK_S_BASE 0x50005000UL 3134 #define NRF_POWER_S_BASE 0x50005000UL 3135 #define NRF_CTRL_AP_PERI_S_BASE 0x50006000UL 3136 #define NRF_SPIM0_NS_BASE 0x40008000UL 3137 #define NRF_SPIS0_NS_BASE 0x40008000UL 3138 #define NRF_TWIM0_NS_BASE 0x40008000UL 3139 #define NRF_TWIS0_NS_BASE 0x40008000UL 3140 #define NRF_UARTE0_NS_BASE 0x40008000UL 3141 #define NRF_SPIM0_S_BASE 0x50008000UL 3142 #define NRF_SPIS0_S_BASE 0x50008000UL 3143 #define NRF_TWIM0_S_BASE 0x50008000UL 3144 #define NRF_TWIS0_S_BASE 0x50008000UL 3145 #define NRF_UARTE0_S_BASE 0x50008000UL 3146 #define NRF_SPIM1_NS_BASE 0x40009000UL 3147 #define NRF_SPIS1_NS_BASE 0x40009000UL 3148 #define NRF_TWIM1_NS_BASE 0x40009000UL 3149 #define NRF_TWIS1_NS_BASE 0x40009000UL 3150 #define NRF_UARTE1_NS_BASE 0x40009000UL 3151 #define NRF_SPIM1_S_BASE 0x50009000UL 3152 #define NRF_SPIS1_S_BASE 0x50009000UL 3153 #define NRF_TWIM1_S_BASE 0x50009000UL 3154 #define NRF_TWIS1_S_BASE 0x50009000UL 3155 #define NRF_UARTE1_S_BASE 0x50009000UL 3156 #define NRF_SPIM2_NS_BASE 0x4000A000UL 3157 #define NRF_SPIS2_NS_BASE 0x4000A000UL 3158 #define NRF_TWIM2_NS_BASE 0x4000A000UL 3159 #define NRF_TWIS2_NS_BASE 0x4000A000UL 3160 #define NRF_UARTE2_NS_BASE 0x4000A000UL 3161 #define NRF_SPIM2_S_BASE 0x5000A000UL 3162 #define NRF_SPIS2_S_BASE 0x5000A000UL 3163 #define NRF_TWIM2_S_BASE 0x5000A000UL 3164 #define NRF_TWIS2_S_BASE 0x5000A000UL 3165 #define NRF_UARTE2_S_BASE 0x5000A000UL 3166 #define NRF_SPIM3_NS_BASE 0x4000B000UL 3167 #define NRF_SPIS3_NS_BASE 0x4000B000UL 3168 #define NRF_TWIM3_NS_BASE 0x4000B000UL 3169 #define NRF_TWIS3_NS_BASE 0x4000B000UL 3170 #define NRF_UARTE3_NS_BASE 0x4000B000UL 3171 #define NRF_SPIM3_S_BASE 0x5000B000UL 3172 #define NRF_SPIS3_S_BASE 0x5000B000UL 3173 #define NRF_TWIM3_S_BASE 0x5000B000UL 3174 #define NRF_TWIS3_S_BASE 0x5000B000UL 3175 #define NRF_UARTE3_S_BASE 0x5000B000UL 3176 #define NRF_GPIOTE0_S_BASE 0x5000D000UL 3177 #define NRF_SAADC_NS_BASE 0x4000E000UL 3178 #define NRF_SAADC_S_BASE 0x5000E000UL 3179 #define NRF_TIMER0_NS_BASE 0x4000F000UL 3180 #define NRF_TIMER0_S_BASE 0x5000F000UL 3181 #define NRF_TIMER1_NS_BASE 0x40010000UL 3182 #define NRF_TIMER1_S_BASE 0x50010000UL 3183 #define NRF_TIMER2_NS_BASE 0x40011000UL 3184 #define NRF_TIMER2_S_BASE 0x50011000UL 3185 #define NRF_RTC0_NS_BASE 0x40014000UL 3186 #define NRF_RTC0_S_BASE 0x50014000UL 3187 #define NRF_RTC1_NS_BASE 0x40015000UL 3188 #define NRF_RTC1_S_BASE 0x50015000UL 3189 #define NRF_DPPIC_NS_BASE 0x40017000UL 3190 #define NRF_DPPIC_S_BASE 0x50017000UL 3191 #define NRF_WDT_NS_BASE 0x40018000UL 3192 #define NRF_WDT_S_BASE 0x50018000UL 3193 #define NRF_EGU0_NS_BASE 0x4001B000UL 3194 #define NRF_EGU0_S_BASE 0x5001B000UL 3195 #define NRF_EGU1_NS_BASE 0x4001C000UL 3196 #define NRF_EGU1_S_BASE 0x5001C000UL 3197 #define NRF_EGU2_NS_BASE 0x4001D000UL 3198 #define NRF_EGU2_S_BASE 0x5001D000UL 3199 #define NRF_EGU3_NS_BASE 0x4001E000UL 3200 #define NRF_EGU3_S_BASE 0x5001E000UL 3201 #define NRF_EGU4_NS_BASE 0x4001F000UL 3202 #define NRF_EGU4_S_BASE 0x5001F000UL 3203 #define NRF_EGU5_NS_BASE 0x40020000UL 3204 #define NRF_EGU5_S_BASE 0x50020000UL 3205 #define NRF_PWM0_NS_BASE 0x40021000UL 3206 #define NRF_PWM0_S_BASE 0x50021000UL 3207 #define NRF_PWM1_NS_BASE 0x40022000UL 3208 #define NRF_PWM1_S_BASE 0x50022000UL 3209 #define NRF_PWM2_NS_BASE 0x40023000UL 3210 #define NRF_PWM2_S_BASE 0x50023000UL 3211 #define NRF_PWM3_NS_BASE 0x40024000UL 3212 #define NRF_PWM3_S_BASE 0x50024000UL 3213 #define NRF_PDM_NS_BASE 0x40026000UL 3214 #define NRF_PDM_S_BASE 0x50026000UL 3215 #define NRF_I2S_NS_BASE 0x40028000UL 3216 #define NRF_I2S_S_BASE 0x50028000UL 3217 #define NRF_IPC_NS_BASE 0x4002A000UL 3218 #define NRF_IPC_S_BASE 0x5002A000UL 3219 #define NRF_FPU_NS_BASE 0x4002C000UL 3220 #define NRF_GPIOTE1_NS_BASE 0x40031000UL 3221 #define NRF_APPROTECT_NS_BASE 0x40039000UL 3222 #define NRF_KMU_NS_BASE 0x40039000UL 3223 #define NRF_NVMC_NS_BASE 0x40039000UL 3224 #define NRF_APPROTECT_S_BASE 0x50039000UL 3225 #define NRF_KMU_S_BASE 0x50039000UL 3226 #define NRF_NVMC_S_BASE 0x50039000UL 3227 #define NRF_VMC_NS_BASE 0x4003A000UL 3228 #define NRF_VMC_S_BASE 0x5003A000UL 3229 #define NRF_CRYPTOCELL_S_BASE 0x50840000UL 3230 #define NRF_CC_AES_S_BASE 0x50841000UL 3231 #define NRF_CC_AHB_S_BASE 0x50841000UL 3232 #define NRF_CC_CHACHA_S_BASE 0x50841000UL 3233 #define NRF_CC_CTL_S_BASE 0x50841000UL 3234 #define NRF_CC_DIN_S_BASE 0x50841000UL 3235 #define NRF_CC_DOUT_S_BASE 0x50841000UL 3236 #define NRF_CC_HASH_S_BASE 0x50841000UL 3237 #define NRF_CC_HOST_RGF_S_BASE 0x50841000UL 3238 #define NRF_CC_MISC_S_BASE 0x50841000UL 3239 #define NRF_CC_PKA_S_BASE 0x50841000UL 3240 #define NRF_CC_RNG_S_BASE 0x50841000UL 3241 #define NRF_CC_RNG_SRAM_S_BASE 0x50841000UL 3242 #define NRF_P0_NS_BASE 0x40842500UL 3243 #define NRF_P0_S_BASE 0x50842500UL 3244 3245 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 3246 3247 3248 /* =========================================================================================================================== */ 3249 /* ================ Peripheral declaration ================ */ 3250 /* =========================================================================================================================== */ 3251 3252 3253 /** @addtogroup Device_Peripheral_declaration 3254 * @{ 3255 */ 3256 3257 #define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE) 3258 #define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) 3259 #define NRF_ETM_NS ((NRF_ETM_Type*) NRF_ETM_NS_BASE) 3260 #define NRF_ETB_NS ((NRF_ETB_Type*) NRF_ETB_NS_BASE) 3261 #define NRF_TPIU_NS ((NRF_TPIU_Type*) NRF_TPIU_NS_BASE) 3262 #define NRF_ATBREPLICATOR_NS ((NRF_ATBREPLICATOR_Type*) NRF_ATBREPLICATOR_NS_BASE) 3263 #define NRF_ATBFUNNEL1_NS ((NRF_ATBFUNNEL_Type*) NRF_ATBFUNNEL1_NS_BASE) 3264 #define NRF_ATBFUNNEL2_NS ((NRF_ATBFUNNEL_Type*) NRF_ATBFUNNEL2_NS_BASE) 3265 #define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) 3266 #define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE) 3267 #define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) 3268 #define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) 3269 #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 3270 #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 3271 #define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) 3272 #define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) 3273 #define NRF_CTRL_AP_PERI_S ((NRF_CTRLAPPERI_Type*) NRF_CTRL_AP_PERI_S_BASE) 3274 #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 3275 #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 3276 #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 3277 #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 3278 #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 3279 #define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE) 3280 #define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE) 3281 #define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE) 3282 #define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE) 3283 #define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE) 3284 #define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE) 3285 #define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE) 3286 #define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE) 3287 #define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE) 3288 #define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE) 3289 #define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE) 3290 #define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE) 3291 #define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE) 3292 #define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE) 3293 #define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE) 3294 #define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE) 3295 #define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE) 3296 #define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE) 3297 #define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE) 3298 #define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE) 3299 #define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE) 3300 #define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE) 3301 #define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE) 3302 #define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE) 3303 #define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE) 3304 #define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE) 3305 #define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE) 3306 #define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE) 3307 #define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE) 3308 #define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE) 3309 #define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE) 3310 #define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE) 3311 #define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE) 3312 #define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE) 3313 #define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE) 3314 #define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE) 3315 #define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) 3316 #define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) 3317 #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 3318 #define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE) 3319 #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 3320 #define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE) 3321 #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 3322 #define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE) 3323 #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 3324 #define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE) 3325 #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 3326 #define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE) 3327 #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 3328 #define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE) 3329 #define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE) 3330 #define NRF_WDT_S ((NRF_WDT_Type*) NRF_WDT_S_BASE) 3331 #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 3332 #define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE) 3333 #define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE) 3334 #define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE) 3335 #define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE) 3336 #define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE) 3337 #define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE) 3338 #define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE) 3339 #define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE) 3340 #define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE) 3341 #define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE) 3342 #define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE) 3343 #define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE) 3344 #define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE) 3345 #define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE) 3346 #define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE) 3347 #define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE) 3348 #define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE) 3349 #define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE) 3350 #define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE) 3351 #define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE) 3352 #define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE) 3353 #define NRF_I2S_NS ((NRF_I2S_Type*) NRF_I2S_NS_BASE) 3354 #define NRF_I2S_S ((NRF_I2S_Type*) NRF_I2S_S_BASE) 3355 #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 3356 #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) 3357 #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) 3358 #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) 3359 #define NRF_APPROTECT_NS ((NRF_APPROTECT_Type*) NRF_APPROTECT_NS_BASE) 3360 #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) 3361 #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 3362 #define NRF_APPROTECT_S ((NRF_APPROTECT_Type*) NRF_APPROTECT_S_BASE) 3363 #define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) 3364 #define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE) 3365 #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 3366 #define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE) 3367 #define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE) 3368 #define NRF_CC_AES_S ((NRF_CC_AES_Type*) NRF_CC_AES_S_BASE) 3369 #define NRF_CC_AHB_S ((NRF_CC_AHB_Type*) NRF_CC_AHB_S_BASE) 3370 #define NRF_CC_CHACHA_S ((NRF_CC_CHACHA_Type*) NRF_CC_CHACHA_S_BASE) 3371 #define NRF_CC_CTL_S ((NRF_CC_CTL_Type*) NRF_CC_CTL_S_BASE) 3372 #define NRF_CC_DIN_S ((NRF_CC_DIN_Type*) NRF_CC_DIN_S_BASE) 3373 #define NRF_CC_DOUT_S ((NRF_CC_DOUT_Type*) NRF_CC_DOUT_S_BASE) 3374 #define NRF_CC_HASH_S ((NRF_CC_HASH_Type*) NRF_CC_HASH_S_BASE) 3375 #define NRF_CC_HOST_RGF_S ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_S_BASE) 3376 #define NRF_CC_MISC_S ((NRF_CC_MISC_Type*) NRF_CC_MISC_S_BASE) 3377 #define NRF_CC_PKA_S ((NRF_CC_PKA_Type*) NRF_CC_PKA_S_BASE) 3378 #define NRF_CC_RNG_S ((NRF_CC_RNG_Type*) NRF_CC_RNG_S_BASE) 3379 #define NRF_CC_RNG_SRAM_S ((NRF_CC_RNG_SRAM_Type*) NRF_CC_RNG_SRAM_S_BASE) 3380 #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 3381 #define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) 3382 3383 /** @} */ /* End of group Device_Peripheral_declaration */ 3384 3385 3386 /* ========================================= End of section using anonymous unions ========================================= */ 3387 #if defined (__CC_ARM) 3388 #pragma pop 3389 #elif defined (__ICCARM__) 3390 /* leave anonymous unions enabled */ 3391 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 3392 #pragma clang diagnostic pop 3393 #elif defined (__GNUC__) 3394 /* anonymous unions are enabled by default */ 3395 #elif defined (__TMS470__) 3396 /* anonymous unions are enabled by default */ 3397 #elif defined (__TASKING__) 3398 #pragma warning restore 3399 #elif defined (__CSMC__) 3400 /* anonymous unions are enabled by default */ 3401 #endif 3402 3403 3404 #ifdef __cplusplus 3405 } 3406 #endif 3407 3408 #endif /* NRF9120_H */ 3409 3410 3411 /** @} */ /* End of group nrf9120 */ 3412 3413 /** @} */ /* End of group Nordic Semiconductor */ 3414
