Searched refs:PWM_INTEN_SEQEND1_Pos (Results 1 – 16 of 16) sorted by relevance
5404 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ macro5405 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
9541 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ macro9542 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
9618 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ macro9619 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8847 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ macro8848 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
10566 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ macro10567 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8807 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ macro8808 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
11221 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ macro11222 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
22002 …#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. … macro22003 …#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. …
21685 …#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. … macro21686 …#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. …
29845 …#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. … macro29846 …#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. …
60793 …#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. … macro60794 …#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. …
59053 …#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. … macro59054 …#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. …
60267 …#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. … macro60268 …#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. …
