1 /*
2 * Copyright (c) 2023 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_HSFLL_H__
35 #define NRF_HSFLL_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_hsfll_hal HSFLL HAL
45 * @{
46 * @ingroup nrf_clock
47 * @brief Hardware access layer for managing the High Speed Frequency Locked Loop (HSFLL).
48 */
49
50 #if defined(HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Msk) || defined(__NRFX_DOXYGEN__)
51 /** @brief Symbol indicating whether initial value for clock dithering configuration is present. */
52 #define NRF_HSFLL_HAS_DITHERING_INITVALUE 1
53 #else
54 #define NRF_HSFLL_HAS_DITHERING_INITVALUE 0
55 #endif
56
57 #if defined(HSFLL_CLOCKCTRL_DITHERINIT_ResetValue) || defined(__NRFX_DOXYGEN__)
58 /** @brief Symbol indicating whether initial value for clock dithering seed configuration is present. */
59 #define NRF_HSFLL_HAS_DITHERINIT 1
60 #else
61 #define NRF_HSFLL_HAS_DITHERINIT 0
62 #endif
63
64 #if defined(HSFLL_TRIM_TCOEF_VALUE_Msk) || defined(__NRFX_DOXYGEN__)
65 /** @brief Symbol indicating whether HSFLL has temperature coefficient trimming. */
66 #define NRF_HSFLL_HAS_TCOEF_TRIM 1
67 #else
68 #define NRF_HSFLL_HAS_TCOEF_TRIM 0
69 #endif
70
71 /** @brief HSFLL tasks. */
72 typedef enum
73 {
74 NRF_HSFLL_TASK_START = offsetof(NRF_HSFLL_Type, TASKS_START), ///< Start the HSFLL.
75 NRF_HSFLL_TASK_STOP = offsetof(NRF_HSFLL_Type, TASKS_STOP), ///< Stop the HSFLL.
76 NRF_HSFLL_TASK_FREQ_MEAS = offsetof(NRF_HSFLL_Type, TASKS_FREQMEAS), ///< Start frequency measurement in software-controlled mode.
77 NRF_HSFLL_TASK_FREQ_CHANGE = offsetof(NRF_HSFLL_Type, TASKS_FREQCHANGE), ///< Trigger frequency change.
78 } nrf_hsfll_task_t;
79
80 /** @brief HSFLL events. */
81 typedef enum
82 {
83 NRF_HSFLL_EVENT_STARTED = offsetof(NRF_HSFLL_Type, EVENTS_STARTED), ///< HSFLL started.
84 NRF_HSFLL_EVENT_STOPPED = offsetof(NRF_HSFLL_Type, EVENTS_STOPPED), ///< HSFLL stopped.
85 NRF_HSFLL_EVENT_FREQM_DONE = offsetof(NRF_HSFLL_Type, EVENTS_FREQMDONE), ///< HSFLL frequency measurement done.
86 NRF_HSFLL_EVENT_FREQ_CHANGED = offsetof(NRF_HSFLL_Type, EVENTS_FREQCHANGED), ///< HSFLL frequency change done.
87 } nrf_hsfll_event_t;
88
89 /** @brief HSFLL clock status operating modes. */
90 typedef enum
91 {
92 NRF_HSFLL_MODE_STATUS_OPEN_LOOP = HSFLL_CLOCKSTATUS_MODE_OpenLoop, ///< Open loop mode.
93 NRF_HSFLL_MODE_STATUS_CLOSED_LOOP = HSFLL_CLOCKSTATUS_MODE_ClosedLoop, ///< Closed loop mode.
94 NRF_HSFLL_MODE_STATUS_BYPASS = HSFLL_CLOCKSTATUS_MODE_Bypass, ///< Bypass mode.
95 } nrf_hsfll_mode_status_t;
96
97 /** @brief HSFLL clock status. */
98 typedef struct
99 {
100 nrf_hsfll_mode_status_t mode; ///< HSFLL operating mode.
101 bool override; ///< HSFLL override mode is enabled.
102 bool accuracy; ///< Clock accurracy is within 2%.
103 bool locked; ///< HSFLL locked to reference clock.
104 } nrf_hsfll_status_clk_t;
105
106 /** @brief HSFLL frequency measurements errors. */
107 typedef struct
108 {
109 bool error; ///< Trim error status. True if outside limit, false if within.
110 bool trim_underflow; ///< Underflow error status. True if outside limit, false if within.
111 bool trim_overflow; ///< Overflow error status. True if outside limit, false if within.
112 } nrf_hsfll_freqm_error_t;
113
114 /** @brief HSFLL clock control operating mode settings. */
115 typedef enum
116 {
117 NRF_HSFLL_MODE_CTRL_AUTO = HSFLL_CLOCKCTRL_MODE_MODE_Auto, ///< The PCGC controls the mode automatically.
118 NRF_HSFLL_MODE_CTRL_OPEN_LOOP = HSFLL_CLOCKCTRL_MODE_MODE_OpenLoop, ///< Open loop mode.
119 NRF_HSFLL_MODE_CTRL_CLOSED_LOOP = HSFLL_CLOCKCTRL_MODE_MODE_ClosedLoop, ///< Closed loop mode.
120 NRF_HSFLL_MODE_CTRL_BYPASS = HSFLL_CLOCKCTRL_MODE_MODE_Bypass, ///< Bypass mode.
121 } nrf_hsfll_mode_ctrl_t;
122
123 /** @brief HSFLL clock control. */
124 typedef struct
125 {
126 nrf_hsfll_mode_ctrl_t mode; ///< HSFLL operating mode.
127 bool override; ///< HSFLL override mode. True if enabled, false otherwise.
128 } nrf_hsfll_clkctrl_t;
129
130 /** @brief HSFLL clock dithering configuration. */
131 typedef struct
132 {
133 uint8_t cyclecount; ///< Cycle count configuration for clock dithering.
134 uint8_t maxoffset; ///< Maximum offset configuration for clock dithering.
135 #if NRF_HSFLL_HAS_DITHERING_INITVALUE
136 uint16_t initvalue; ///< Initial value for the clock dithering.
137 #endif
138 bool enable; ///< Enable the clock dithering.
139 } nrf_hsfll_dithering_t;
140
141 /** @brief HSFLL clock sleep configuration. */
142 typedef struct
143 {
144 bool mode; ///< Power down the HSFLL core. True if powered down, false if in normal mode.
145 bool retain; ///< Retain all inputs while powered down. True if retention is enabled, false otherwise.
146 } nrf_hsfll_sleep_t;
147
148 /** @brief HSFLL trims configuration. */
149 typedef struct
150 {
151 uint16_t coarse; ///< Coarse frequance trimming.
152 uint16_t fine; ///< Fine frequency trimming.
153 uint8_t vsup; ///< Internal regulator voltage supply level trimming.
154 #if NRF_HSFLL_HAS_TCOEF_TRIM
155 uint8_t tcoef; ///< Temperature coefficient trimming.
156 #endif
157 } nrf_hsfll_trim_t;
158
159 /**
160 * @brief Function for getting the address of the specified task.
161 *
162 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
163 * @param[in] task HSFLL task.
164 *
165 * @return Address of the requested task register.
166 */
167 NRF_STATIC_INLINE uint32_t nrf_hsfll_task_address_get(NRF_HSFLL_Type const * p_reg,
168 nrf_hsfll_task_t task);
169
170 /**
171 * @brief Function for triggering the specified task.
172 *
173 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
174 * @param[in] task Task to be activated.
175 */
176 NRF_STATIC_INLINE void nrf_hsfll_task_trigger(NRF_HSFLL_Type * p_reg, nrf_hsfll_task_t task);
177
178 /**
179 * @brief Function for retrieving the address of the specified event.
180 *
181 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
182 * @param[in] event HSFLL event.
183 *
184 * @return Address of the specified event register.
185 */
186 NRF_STATIC_INLINE uint32_t nrf_hsfll_event_address_get(NRF_HSFLL_Type const * p_reg,
187 nrf_hsfll_event_t event);
188
189 /**
190 * @brief Function for clearing the specified event.
191 *
192 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
193 * @param[in] event Event to be cleared.
194 */
195 NRF_STATIC_INLINE void nrf_hsfll_event_clear(NRF_HSFLL_Type * p_reg, nrf_hsfll_event_t event);
196
197 /**
198 * @brief Function for retrieving the state of the specified event.
199 *
200 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
201 * @param[in] event Event to be checked.
202 *
203 * @retval true The event has been generated.
204 * @retval false The event has not been generated.
205 */
206 NRF_STATIC_INLINE bool nrf_hsfll_event_check(NRF_HSFLL_Type const * p_reg,
207 nrf_hsfll_event_t event);
208
209 /**
210 * @brief Function for getting the HSFLL status.
211 *
212 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
213 * @param[out] p_status Pointer to the structure to be filled with the HSFLL status.
214 */
215 NRF_STATIC_INLINE void nrf_hsfll_status_clk_get(NRF_HSFLL_Type const * p_reg,
216 nrf_hsfll_status_clk_t * p_status);
217
218 /**
219 * @brief Function for checking whether the HSFLL frequency measurement is completed.
220 *
221 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
222 *
223 * @retval true The frequency measurement is completed.
224 * @retval false The frequency measurement is in progress.
225 */
226 NRF_STATIC_INLINE bool nrf_hsfll_freqm_done_check(NRF_HSFLL_Type const * p_reg);
227
228 /**
229 * @brief Function for getting HSFLL frequency measurement errors.
230 *
231 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
232 * @param[out] p_error Pointer to the structure to be filled with HSFLL frequency measurement
233 * errors.
234 */
235 NRF_STATIC_INLINE void nrf_hsfll_freqm_error_get(NRF_HSFLL_Type const * p_reg,
236 nrf_hsfll_freqm_error_t * p_error);
237
238 /**
239 * @brief Function for getting HSFLL frequency measurement.
240 *
241 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
242 *
243 * @return The last frequency measurement value. Measures the number of reference clock cycles.
244 */
245 NRF_STATIC_INLINE uint32_t nrf_hsfll_freqm_meas_get(NRF_HSFLL_Type const * p_reg);
246
247 /**
248 * @brief Function for setting HSFLL clock control mode settings.
249 *
250 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
251 * @param[in] p_clkctrl Pointer to the structure with new HSFLL clock control mode settings.
252 */
253 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mode_set(NRF_HSFLL_Type * p_reg,
254 nrf_hsfll_clkctrl_t const * p_clkctrl);
255
256 /**
257 * @brief Function for getting HSFLL clock control mode settings.
258 *
259 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
260 * @param[out] p_clkctrl Pointer to the structure to be filled with HSFLL clock control settings.
261 */
262 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mode_get(NRF_HSFLL_Type const * p_reg,
263 nrf_hsfll_clkctrl_t * p_clkctrl);
264
265 /**
266 * @brief Function for setting HSFLL clock dithering configuration.
267 *
268 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
269 * @param[in] p_config Pointer to the structure with new HSFLL clock dithering configuration.
270 */
271 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dithering_set(NRF_HSFLL_Type * p_reg,
272 nrf_hsfll_dithering_t const * p_config);
273
274 /**
275 * @brief Function for getting HSFLL clock dithering configuration.
276 *
277 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
278 * @param[out] p_config Pointer to the structure to be filled with HSFLL clock dithering
279 * configuration.
280 */
281 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dithering_get(NRF_HSFLL_Type const * p_reg,
282 nrf_hsfll_dithering_t * p_config);
283
284 /**
285 * @brief Function for setting HSFLL frequency multiplier.
286 *
287 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
288 * @param[in] multiplier Value of new multiplier. Valid @c multiplier range is from 4 to 25.
289 */
290 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mult_set(NRF_HSFLL_Type * p_reg, uint32_t multiplier);
291
292 /**
293 * @brief Function for getting HSFLL frequency multiplier.
294 *
295 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
296 *
297 * @return Current value of frequency multiplier used by HSFLL.
298 */
299 NRF_STATIC_INLINE uint32_t nrf_hsfll_clkctrl_mult_get(NRF_HSFLL_Type const * p_reg);
300
301 /**
302 * @brief Function for setting HSFLL clock sleep configuration.
303 *
304 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
305 * @param[in] p_config Pointer to the structure with new HSFLL clock sleep configuration.
306 */
307 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_sleep_set(NRF_HSFLL_Type * p_reg,
308 nrf_hsfll_sleep_t const * p_config);
309
310 /**
311 * @brief Function for getting HSFLL clock sleep configuration.
312 *
313 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
314 * @param[out] p_config Pointer to the structure to be filled with HSFLL clock sleep configuration.
315 */
316 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_sleep_get(NRF_HSFLL_Type const * p_reg,
317 nrf_hsfll_sleep_t * p_config);
318
319 /**
320 * @brief Function for enabling or disabling the retention of HSFLL fine trim control.
321 *
322 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
323 * @param[in] retain True if the fine trim control is to be retained when HSFLL goes to open-loop
324 * mode, false otherwise.
325 */
326 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_retainfinetrim_enable_set(NRF_HSFLL_Type * p_reg,
327 bool retain);
328
329 /**
330 * @brief Function for enabling or disabling the override of the HSFLL LOCKED signal.
331 *
332 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
333 * @param[in] override True if the override is to be enabled, false otherwise.
334 */
335 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_overridelocked_enable_set(NRF_HSFLL_Type * p_reg,
336 bool override);
337
338 #if NRF_HSFLL_HAS_DITHERINIT
339 /**
340 * @brief Function for setting the configurable seed of HSFLL clock dithering.
341 *
342 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
343 * @param[in] seed 32-bit initial value for the PRBS.
344 */
345 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dither_init_set(NRF_HSFLL_Type * p_reg, uint32_t seed);
346 #endif // NRF_HSFLL_HAS_DITHERINIT
347
348 /**
349 * @brief Function for enabling or disabling lock for mirrored registers.
350 *
351 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
352 * @param[in] enable True if the lock is to be enabled, false otherwise.
353 */
354 NRF_STATIC_INLINE void nrf_hsfll_mirror_lock_set(NRF_HSFLL_Type * p_reg, bool enable);
355
356 /**
357 * @brief Function to setup trims configuration.
358 *
359 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
360 * @param[in] p_trim Pointer to the structure with new HSFLL trim configuration.
361 */
362 NRF_STATIC_INLINE void nrf_hsfll_trim_set(NRF_HSFLL_Type * p_reg,
363 nrf_hsfll_trim_t const * p_trim);
364
365 /**
366 * @brief Function to getting trims configuration.
367 *
368 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
369 * @param[in] p_trim Pointer to the structure to be filled with HSFLL trim configuration.
370 */
371 NRF_STATIC_INLINE void nrf_hsfll_trim_get(NRF_HSFLL_Type const * p_reg,
372 nrf_hsfll_trim_t * p_trim);
373
374 #ifndef NRF_DECLARE_ONLY
375
nrf_hsfll_task_address_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_task_t task)376 NRF_STATIC_INLINE uint32_t nrf_hsfll_task_address_get(NRF_HSFLL_Type const * p_reg,
377 nrf_hsfll_task_t task)
378 {
379 return nrf_task_event_address_get(p_reg, task);
380 }
381
nrf_hsfll_task_trigger(NRF_HSFLL_Type * p_reg,nrf_hsfll_task_t task)382 NRF_STATIC_INLINE void nrf_hsfll_task_trigger(NRF_HSFLL_Type * p_reg, nrf_hsfll_task_t task)
383 {
384 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
385 }
386
nrf_hsfll_event_address_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_event_t event)387 NRF_STATIC_INLINE uint32_t nrf_hsfll_event_address_get(NRF_HSFLL_Type const * p_reg,
388 nrf_hsfll_event_t event)
389 {
390 return nrf_task_event_address_get(p_reg, event);
391 }
392
nrf_hsfll_event_clear(NRF_HSFLL_Type * p_reg,nrf_hsfll_event_t event)393 NRF_STATIC_INLINE void nrf_hsfll_event_clear(NRF_HSFLL_Type * p_reg, nrf_hsfll_event_t event)
394 {
395 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
396 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
397 }
398
nrf_hsfll_event_check(NRF_HSFLL_Type const * p_reg,nrf_hsfll_event_t event)399 NRF_STATIC_INLINE bool nrf_hsfll_event_check(NRF_HSFLL_Type const * p_reg,
400 nrf_hsfll_event_t event)
401 {
402 return nrf_event_check(p_reg, event);
403 }
404
nrf_hsfll_status_clk_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_status_clk_t * p_status)405 NRF_STATIC_INLINE void nrf_hsfll_status_clk_get(NRF_HSFLL_Type const * p_reg,
406 nrf_hsfll_status_clk_t * p_status)
407 {
408 NRFX_ASSERT(p_status);
409 uint32_t reg = p_reg->CLOCKSTATUS;
410
411 p_status->mode =
412 (nrf_hsfll_mode_status_t)((reg & HSFLL_CLOCKSTATUS_MODE_Msk) >> HSFLL_CLOCKSTATUS_MODE_Pos);
413 p_status->override = ((reg & HSFLL_CLOCKSTATUS_OVERRIDE_Msk)
414 >> HSFLL_CLOCKSTATUS_OVERRIDE_Pos) ==
415 HSFLL_CLOCKSTATUS_OVERRIDE_Enabled;
416 p_status->accuracy = ((reg & HSFLL_CLOCKSTATUS_ACCURACY_Msk)
417 >> HSFLL_CLOCKSTATUS_ACCURACY_Pos) ==
418 HSFLL_CLOCKSTATUS_ACCURACY_WithinLimit;
419 p_status->locked = ((reg & HSFLL_CLOCKSTATUS_LOCKED_Msk)
420 >> HSFLL_CLOCKSTATUS_LOCKED_Pos) ==
421 HSFLL_CLOCKSTATUS_LOCKED_Locked;
422 }
423
nrf_hsfll_freqm_done_check(NRF_HSFLL_Type const * p_reg)424 NRF_STATIC_INLINE bool nrf_hsfll_freqm_done_check(NRF_HSFLL_Type const * p_reg)
425 {
426 return ((p_reg->FREQM.DONE & HSFLL_FREQM_DONE_DONE_Msk) >> HSFLL_FREQM_DONE_DONE_Pos) ==
427 HSFLL_FREQM_DONE_DONE_Completed;
428 }
429
nrf_hsfll_freqm_error_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_freqm_error_t * p_error)430 NRF_STATIC_INLINE void nrf_hsfll_freqm_error_get(NRF_HSFLL_Type const * p_reg,
431 nrf_hsfll_freqm_error_t * p_error)
432 {
433 NRFX_ASSERT(p_error);
434 p_error->error =
435 ((p_reg->FREQM.ERROR & HSFLL_FREQM_ERROR_ERROR_Msk) >> HSFLL_FREQM_ERROR_ERROR_Pos) ==
436 HSFLL_FREQM_ERROR_ERROR_OutsideLimit;
437 p_error->trim_underflow = ((p_reg->FREQM.ERROR & HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Msk)
438 >> HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Pos) ==
439 HSFLL_FREQM_ERROR_TRIMUNDERFLOW_OutsideLimit;
440 p_error->trim_overflow = ((p_reg->FREQM.ERROR & HSFLL_FREQM_ERROR_TRIMOVERFLOW_Msk)
441 >> HSFLL_FREQM_ERROR_TRIMOVERFLOW_Pos) ==
442 HSFLL_FREQM_ERROR_TRIMOVERFLOW_OutsideLimit;
443 }
444
nrf_hsfll_freqm_meas_get(NRF_HSFLL_Type const * p_reg)445 NRF_STATIC_INLINE uint32_t nrf_hsfll_freqm_meas_get(NRF_HSFLL_Type const * p_reg)
446 {
447 return (p_reg->FREQM.MEAS & HSFLL_FREQM_MEAS_VALUE_Msk) >> HSFLL_FREQM_MEAS_VALUE_Pos;
448 }
449
nrf_hsfll_clkctrl_mode_set(NRF_HSFLL_Type * p_reg,nrf_hsfll_clkctrl_t const * p_clkctrl)450 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mode_set(NRF_HSFLL_Type * p_reg,
451 nrf_hsfll_clkctrl_t const * p_clkctrl)
452 {
453 NRFX_ASSERT(p_clkctrl);
454 p_reg->CLOCKCTRL.MODE = ((p_clkctrl->mode << HSFLL_CLOCKCTRL_MODE_MODE_Pos) &
455 HSFLL_CLOCKCTRL_MODE_MODE_Msk) |
456 (((p_clkctrl->override ?
457 HSFLL_CLOCKCTRL_MODE_OVERRIDE_Enabled :
458 HSFLL_CLOCKCTRL_MODE_OVERRIDE_Disabled)
459 << HSFLL_CLOCKCTRL_MODE_OVERRIDE_Pos) &
460 HSFLL_CLOCKCTRL_MODE_OVERRIDE_Msk);
461 }
462
nrf_hsfll_clkctrl_mode_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_clkctrl_t * p_clkctrl)463 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mode_get(NRF_HSFLL_Type const * p_reg,
464 nrf_hsfll_clkctrl_t * p_clkctrl)
465 {
466 NRFX_ASSERT(p_clkctrl);
467 uint32_t reg = p_reg->CLOCKCTRL.MODE;
468
469 p_clkctrl->mode =
470 (nrf_hsfll_mode_ctrl_t)((reg & HSFLL_CLOCKCTRL_MODE_MODE_Msk)
471 >> HSFLL_CLOCKCTRL_MODE_MODE_Pos);
472 p_clkctrl->override = ((reg & HSFLL_CLOCKCTRL_MODE_OVERRIDE_Msk)
473 >> HSFLL_CLOCKCTRL_MODE_OVERRIDE_Pos) ==
474 HSFLL_CLOCKCTRL_MODE_OVERRIDE_Enabled;
475 }
476
nrf_hsfll_clkctrl_dithering_set(NRF_HSFLL_Type * p_reg,nrf_hsfll_dithering_t const * p_config)477 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dithering_set(NRF_HSFLL_Type * p_reg,
478 nrf_hsfll_dithering_t const * p_config)
479 {
480 NRFX_ASSERT(p_config);
481 p_reg->CLOCKCTRL.DITHERING =
482 #if NRF_HSFLL_HAS_DITHERING_INITVALUE
483 ((p_config->initvalue << HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Pos) &
484 HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Msk) |
485 #endif
486 ((p_config->cyclecount << HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Pos) &
487 HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Msk) |
488 ((p_config->maxoffset << HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Pos) &
489 HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Msk) |
490 (((p_config->enable ?
491 HSFLL_CLOCKCTRL_DITHERING_EN_Enabled :
492 HSFLL_CLOCKCTRL_DITHERING_EN_Disabled) << HSFLL_CLOCKCTRL_DITHERING_EN_Pos) &
493 HSFLL_CLOCKCTRL_DITHERING_EN_Msk);
494 }
495
nrf_hsfll_clkctrl_dithering_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_dithering_t * p_config)496 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dithering_get(NRF_HSFLL_Type const * p_reg,
497 nrf_hsfll_dithering_t * p_config)
498 {
499 NRFX_ASSERT(p_config);
500 p_config->cyclecount = (p_reg->CLOCKCTRL.MODE & HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Msk)
501 >> HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Pos;
502 p_config->maxoffset = (p_reg->CLOCKCTRL.MODE & HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Msk)
503 >> HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Pos;
504 p_config->enable = ((p_reg->CLOCKCTRL.MODE & HSFLL_CLOCKCTRL_DITHERING_EN_Msk)
505 >> HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Pos) ==
506 HSFLL_CLOCKCTRL_DITHERING_EN_Enabled;
507 #if NRF_HSFLL_HAS_DITHERING_INITVALUE
508 p_config->initvalue = (p_reg->CLOCKCTRL.MODE & HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Msk)
509 >> HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Pos;
510 #endif
511 }
512
nrf_hsfll_clkctrl_mult_set(NRF_HSFLL_Type * p_reg,uint32_t multiplier)513 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_mult_set(NRF_HSFLL_Type * p_reg,
514 uint32_t multiplier)
515 {
516 p_reg->CLOCKCTRL.MULT = (multiplier << HSFLL_CLOCKCTRL_MULT_VAL_Pos) &
517 HSFLL_CLOCKCTRL_MULT_VAL_Msk;
518 }
519
nrf_hsfll_clkctrl_mult_get(NRF_HSFLL_Type const * p_reg)520 NRF_STATIC_INLINE uint32_t nrf_hsfll_clkctrl_mult_get(NRF_HSFLL_Type const * p_reg)
521 {
522 return (p_reg->CLOCKCTRL.MULT & HSFLL_CLOCKCTRL_MULT_VAL_Msk) >> HSFLL_CLOCKCTRL_MULT_VAL_Pos;
523 }
524
nrf_hsfll_clkctrl_sleep_set(NRF_HSFLL_Type * p_reg,nrf_hsfll_sleep_t const * p_config)525 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_sleep_set(NRF_HSFLL_Type * p_reg,
526 nrf_hsfll_sleep_t const * p_config)
527 {
528 NRFX_ASSERT(p_config);
529 p_reg->CLOCKCTRL.SLEEP = (((p_config->mode ?
530 HSFLL_CLOCKCTRL_SLEEP_MODE_Sleep :
531 HSFLL_CLOCKCTRL_SLEEP_MODE_Normal)
532 << HSFLL_CLOCKCTRL_SLEEP_MODE_Pos) &
533 HSFLL_CLOCKCTRL_SLEEP_MODE_Msk) |
534 (((p_config->retain ?
535 HSFLL_CLOCKCTRL_SLEEP_RETAIN_Enabled :
536 HSFLL_CLOCKCTRL_SLEEP_RETAIN_Disabled)
537 << HSFLL_CLOCKCTRL_SLEEP_RETAIN_Pos) &
538 HSFLL_CLOCKCTRL_SLEEP_RETAIN_Msk);
539 }
540
nrf_hsfll_clkctrl_sleep_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_sleep_t * p_config)541 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_sleep_get(NRF_HSFLL_Type const * p_reg,
542 nrf_hsfll_sleep_t * p_config)
543 {
544 NRFX_ASSERT(p_config);
545 p_config->mode = ((p_reg->CLOCKCTRL.SLEEP & HSFLL_CLOCKCTRL_SLEEP_MODE_Msk)
546 >> HSFLL_CLOCKCTRL_SLEEP_MODE_Pos) == HSFLL_CLOCKCTRL_SLEEP_MODE_Sleep;
547 p_config->retain = ((p_reg->CLOCKCTRL.SLEEP & HSFLL_CLOCKCTRL_SLEEP_RETAIN_Msk)
548 >> HSFLL_CLOCKCTRL_SLEEP_RETAIN_Pos) ==
549 HSFLL_CLOCKCTRL_SLEEP_RETAIN_Enabled;
550 }
551
nrf_hsfll_clkctrl_retainfinetrim_enable_set(NRF_HSFLL_Type * p_reg,bool retain)552 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_retainfinetrim_enable_set(NRF_HSFLL_Type * p_reg,
553 bool retain)
554 {
555 p_reg->CLOCKCTRL.RETAINFINETRIM = ((retain ?
556 HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Retain :
557 HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_NoRetain)
558 << HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Pos) &
559 HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Msk;
560 }
561
nrf_hsfll_clkctrl_overridelocked_enable_set(NRF_HSFLL_Type * p_reg,bool override)562 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_overridelocked_enable_set(NRF_HSFLL_Type * p_reg,
563 bool override)
564 {
565 p_reg->CLOCKCTRL.OVERRIDELOCKED = ((override ?
566 HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Override :
567 HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_NoOperation)
568 << HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Pos) &
569 HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Msk;
570 }
571
572 #if NRF_HSFLL_HAS_DITHERINIT
nrf_hsfll_clkctrl_dither_init_set(NRF_HSFLL_Type * p_reg,uint32_t seed)573 NRF_STATIC_INLINE void nrf_hsfll_clkctrl_dither_init_set(NRF_HSFLL_Type * p_reg, uint32_t seed)
574 {
575 p_reg->CLOCKCTRL.DITHERINIT = (seed << HSFLL_CLOCKCTRL_DITHERINIT_SEED_Pos) &
576 HSFLL_CLOCKCTRL_DITHERINIT_SEED_Msk;
577 }
578
579 #endif // NRF_HSFLL_HAS_DITHERINIT
580
nrf_hsfll_mirror_lock_set(NRF_HSFLL_Type * p_reg,bool enable)581 NRF_STATIC_INLINE void nrf_hsfll_mirror_lock_set(NRF_HSFLL_Type * p_reg, bool enable)
582 {
583 p_reg->MIRROR = ((enable ? HSFLL_MIRROR_LOCK_Enabled : HSFLL_MIRROR_LOCK_Disabled)
584 << HSFLL_MIRROR_LOCK_Pos) & HSFLL_MIRROR_LOCK_Msk;
585 }
586
nrf_hsfll_trim_set(NRF_HSFLL_Type * p_reg,nrf_hsfll_trim_t const * p_trim)587 NRF_STATIC_INLINE void nrf_hsfll_trim_set(NRF_HSFLL_Type * p_reg,
588 nrf_hsfll_trim_t const * p_trim)
589 {
590 NRFX_ASSERT(p_trim);
591 nrf_hsfll_mirror_lock_set(p_reg, true);
592
593 p_reg->TRIM.VSUP = p_trim->vsup;
594 p_reg->TRIM.COARSE = p_trim->coarse;
595 p_reg->TRIM.FINE = p_trim->fine;
596 #if NRF_HSFLL_HAS_TCOEF_TRIM
597 p_reg->TRIM.TCOEF = p_trim->tcoef;
598 #endif
599
600 nrf_hsfll_mirror_lock_set(p_reg, false);
601 }
602
nrf_hsfll_trim_get(NRF_HSFLL_Type const * p_reg,nrf_hsfll_trim_t * p_trim)603 NRF_STATIC_INLINE void nrf_hsfll_trim_get(NRF_HSFLL_Type const * p_reg,
604 nrf_hsfll_trim_t * p_trim)
605 {
606 NRFX_ASSERT(p_trim);
607
608 p_trim->vsup = (uint8_t)p_reg->TRIM.VSUP;
609 p_trim->coarse = (uint8_t)p_reg->TRIM.COARSE;
610 p_trim->fine = (uint8_t)p_reg->TRIM.FINE;
611 #if NRF_HSFLL_HAS_TCOEF_TRIM
612 p_trim->tcoef = (uint8_t)p_reg->TRIM.TCOEF;
613 #endif
614 }
615
616 #endif // NRF_DECLARE_ONLY
617
618 /** @} */
619
620 #ifdef __cplusplus
621 }
622 #endif
623
624 #endif // NRF_HSFLL_H__
625
