1 /*
2 * Copyright (c) 2015 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_CLOCK_H__
35 #define NRF_CLOCK_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_clock_hal Clock HAL
45 * @{
46 * @ingroup nrf_clock
47 * @brief Hardware access layer for managing the CLOCK peripheral.
48 *
49 * This code can be used to manage low-frequency clock (LFCLK), high-frequency clock (HFCLK),
50 * high-frequency 192 MHz clock (HFCLK192M) and high-frequency audio clock (HFCLKAUDIO)
51 * settings.
52 */
53
54 #if defined(CLOCK_LFCLKSRC_BYPASS_Msk) && defined(CLOCK_LFCLKSRC_EXTERNAL_Msk)
55 // Enable support for external LFCLK sources. Read more in the Product Specification.
56 #define NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES
57 #endif
58
59 #if defined(CLOCK_INTENSET_DONE_Msk) || defined(__NRFX_DOXYGEN__)
60 /** @brief Symbol indicating whether the Low Frequency Clock calibration is present. */
61 #define NRF_CLOCK_HAS_CALIBRATION 1
62 #else
63 #define NRF_CLOCK_HAS_CALIBRATION 0
64 #endif
65
66 #if defined(CLOCK_CTIV_CTIV_Msk) || defined(__NRFX_DOXYGEN__)
67 /** @brief Symbol indicating whether the Low Frequency Clock calibration timer is present. */
68 #define NRF_CLOCK_HAS_CALIBRATION_TIMER 1
69 #else
70 #define NRF_CLOCK_HAS_CALIBRATION_TIMER 0
71 #endif
72
73 #if (defined(CLOCK_INTENSET_HFCLK192MSTARTED_Msk) && !defined(NRF5340_XXAA_NETWORK)) \
74 || defined(__NRFX_DOXYGEN__)
75 /** @brief Symbol indicating whether the 192 MHz clock is present. */
76 #define NRF_CLOCK_HAS_HFCLK192M 1
77 #else
78 #define NRF_CLOCK_HAS_HFCLK192M 0
79 #endif
80
81 #if (defined(CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk) && !defined(NRF5340_XXAA_NETWORK)) \
82 || defined(__NRFX_DOXYGEN__)
83 /** @brief Symbol indicating whether the Audio clock is present. */
84 #define NRF_CLOCK_HAS_HFCLKAUDIO 1
85 #else
86 #define NRF_CLOCK_HAS_HFCLKAUDIO 0
87 #endif
88
89 #if (defined(CLOCK_HFCLKCTRL_HCLK_Div1) && !defined(NRF5340_XXAA_NETWORK)) \
90 || defined(__NRFX_DOXYGEN__)
91 /** @brief Symbol indicating whether the HFCLK frequency configuration is present. */
92 #define NRF_CLOCK_HAS_HFCLK_DIV 1
93 #else
94 #define NRF_CLOCK_HAS_HFCLK_DIV 0
95 #endif
96
97 #if defined(CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk) || defined(CLOCK_LFCLK_ALWAYSRUN_ALWAYSRUN_Msk) || \
98 defined(__NRFX_DOXYGEN__)
99 /** @brief Symbol indicating whether the ALWAYSRUN register is present for LFCLK. */
100 #define NRF_CLOCK_HAS_LFCLK_ALWAYSRUN 1
101 #else
102 #define NRF_CLOCK_HAS_LFCLK_ALWAYSRUN 0
103 #endif
104
105 #if defined(CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk) || defined(__NRFX_DOXYGEN__)
106 /** @brief Symbol indicating whether the ALWAYSRUN register is present for HFCLK. */
107 #define NRF_CLOCK_HAS_HFCLK_ALWAYSRUN 1
108 #else
109 #define NRF_CLOCK_HAS_HFCLK_ALWAYSRUN 0
110 #endif
111
112 #if defined(CLOCK_HFCLKSRC_SRC_Msk) || defined(__NRFX_DOXYGEN__)
113 /** @brief Symbol indicating whether the HFCLKSRC register is present. */
114 #define NRF_CLOCK_HAS_HFCLKSRC 1
115 #else
116 #define NRF_CLOCK_HAS_HFCLKSRC 0
117 #endif
118
119 #if defined(CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Msk) || defined(__NRFX_DOXYGEN__)
120 /** @brief Symbol indicating whether the PLL section is present. */
121 #define NRF_CLOCK_HAS_PLL 1
122 #else
123 #define NRF_CLOCK_HAS_PLL 0
124 #endif
125
126 #if defined(CLOCK_TASKS_XOSTART_TASKS_XOSTART_Msk) || defined(__NRFX_DOXYGEN__)
127 /** @brief Symbol indicating whether XO registers are present. */
128 #define NRF_CLOCK_HAS_XO 1
129 #else
130 #define NRF_CLOCK_HAS_XO 0
131 #endif
132
133 #if defined(CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Msk) || defined(__NRFX_DOXYGEN__)
134 /** @brief Symbol indicating whether XOTUNE registers are present. */
135 #define NRF_CLOCK_HAS_XO_TUNE 1
136 #else
137 #define NRF_CLOCK_HAS_XO_TUNE 0
138 #endif
139
140 #if defined(CLOCK_LFCLK_SRC_SRC_Msk) || defined(__NRFX_DOXYGEN__)
141 /** @brief Symbol indicating whether the CLOCK type contains LFCLK subtype. */
142 #define NRF_CLOCK_HAS_LFCLK_TYPE 1
143 #else
144 #define NRF_CLOCK_HAS_LFCLK_TYPE 0
145 #endif
146
147 #if defined(CLOCK_INTPEND_ResetValue) || defined(__NRFX_DOXYGEN__)
148 /** @brief Symbol indicating whether INTPEND register is present. */
149 #define NRF_CLOCK_HAS_INTPEND 1
150 #else
151 #define NRF_CLOCK_HAS_INTPEND 0
152 #endif
153
154 #if defined(CLOCK_LFCLKCTRL_SRC_ResetValue) || defined(__NRFX_DOXYGEN__)
155 /** @brief Symbol indicating whether the CLOCK type contains LFCLKCTRL subtype. */
156 #define NRF_CLOCK_HAS_LFCLKCTRL 1
157 #else
158 #define NRF_CLOCK_HAS_LFCLKCTRL 0
159 #endif
160
161 #if defined(CLOCK_LFCLKSTAT_RUN_ResetValue) || defined(__NRFX_DOXYGEN__)
162 /** @brief Symbol indicating whether the CLOCK type contains LFCLKSTAT subtype. */
163 #define NRF_CLOCK_HAS_LFCLKSTAT 1
164 #else
165 #define NRF_CLOCK_HAS_LFCLKSTAT 0
166 #endif
167
168 #if defined(CLOCK_CONFIG_SETUP_ResetValue) || defined(__NRFX_DOXYGEN__)
169 /** @brief Symbol indicating whether the CLOCK type contains CONFIG subtype. */
170 #define NRF_CLOCK_HAS_CONFIG 1
171 #else
172 #define NRF_CLOCK_HAS_CONFIG 0
173 #endif
174
175 #if defined(CLOCK_INTENSET_LFCLKSRCCHANGED_Msk) || defined(__NRFX_DOXYGEN__)
176 /** @brief Symbol indicating whether LFCLK source change event is present. */
177 #define NRF_CLOCK_HAS_LFCLK_SRC_CHANGED 1
178 #else
179 #define NRF_CLOCK_HAS_LFCLK_SRC_CHANGED 0
180 #endif
181
182 #if defined(CLOCK_LFCLK_SRCCOPY_SRC_Msk) || defined(CLOCK_LFCLKSRCCOPY_SRC_Msk) || \
183 defined(__NRFX_DOXYGEN__)
184 /** @brief Symbol indicating whether SRCCOPY register for LFCLK is present. */
185 #define NRF_CLOCK_HAS_SRC_COPY 1
186 #else
187 #define NRF_CLOCK_HAS_SRC_COPY 0
188 #endif
189
190 #if defined(CLOCK_LFCLK_STAT_ALWAYSRUNNING_Msk) || defined(CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk) || \
191 defined(__NRFX_DOXYGEN__)
192 /** @brief Symbol indicating whether clock domain always run setting is available. */
193 #define NRF_CLOCK_HAS_ALWAYSRUN_ACTIVE 1
194 #else
195 #define NRF_CLOCK_HAS_ALWAYSRUN_ACTIVE 0
196 #endif
197
198 #if !NRF_CLOCK_HAS_LFCLKCTRL || defined(__NRFX_DOXYGEN__)
199 /** @brief Symbol indicating whether high frequency clock domain is present. */
200 #define NRF_CLOCK_HAS_HFDOMAIN 1
201 #else
202 #define NRF_CLOCK_HAS_HFDOMAIN 0
203 #endif
204
205 #if NRF_CLOCK_HAS_LFCLK_TYPE
206 #define NRF_CLOCK_LFCLKRUN_STATUS_NotTriggered CLOCK_LFCLK_RUN_STATUS_NotTriggered /**< Task LFCLKSTART/HFCLKSTART has not been triggered definiton. */
207 #define NRF_CLOCK_LFCLKRUN_STATUS_Triggered CLOCK_LFCLK_RUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */
208 #define NRF_CLOCK_INTENSET_LFCLKSTARTED_Msk CLOCK_INTENSET_LFCLKSTARTED_Msk /**< Interrupt on LFCLKSTARTED event mask definition. */
209 #define NRF_LFCLKSRCCOPY LFCLK.SRCCOPY /**< LF clock SRCCOPY register definition. */
210 #define NRF_LFCLKRUN LFCLK.RUN /**< LF clock RUN register definition. */
211 #define NRF_LFCLKSTAT LFCLK.STAT /**< LF clock STAT register definition. */
212 #define NRF_LFCLKSRC LFCLK.SRC /**< LF clock SRC register definition. */
213 #define NRF_LFCLKALWAYSRUN LFCLK.ALWAYSRUN /**< LF clock ALWAYSRUN register definition. */
214 #define NRF_CLOCK_LFCLKSRCCOPY_SRC_Msk CLOCK_LFCLK_SRCCOPY_SRC_Msk /**< LF clock SRCCOPY status mask definition. */
215 #define NRF_CLOCK_LFCLKSRCCOPY_SRC_Pos CLOCK_LFCLK_SRCCOPY_SRC_Pos /**< LF clock SRCCOPY status position definition. */
216 #define NRF_CLOCK_LFCLKRUN_STATUS_Msk CLOCK_LFCLK_RUN_STATUS_Msk /**< LF clock RUN status mask definition. */
217 #define NRF_CLOCK_LFCLKRUN_STATUS_Pos CLOCK_LFCLK_RUN_STATUS_Pos /**< LF clock RUN status position definition. */
218 #define NRF_CLOCK_LFCLKSTAT_SRC_Msk CLOCK_LFCLK_STAT_SRC_Msk /**< LF clock STAT source mask definition. */
219 #define NRF_CLOCK_LFCLKSTAT_SRC_Pos CLOCK_LFCLK_STAT_SRC_Pos /**< LF clock STAT source position definition. */
220 #define NRF_CLOCK_LFCLKSTAT_STATE_Msk CLOCK_LFCLK_STAT_STATE_Msk /**< LF clock STAT state mask definition. */
221 #define NRF_CLOCK_LFCLKSTAT_STATE_Pos CLOCK_LFCLK_STAT_STATE_Pos /**< LF clock STAT state position definition. */
222 #define NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk CLOCK_LFCLK_STAT_ALWAYSRUNNING_Msk /**< LF clock STAT alwaysrunning position definition. */
223 #define NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos CLOCK_LFCLK_STAT_ALWAYSRUNNING_Pos /**< LF clock STAT alwaysrunning mask definition. */
224 #define NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk CLOCK_LFCLK_ALWAYSRUN_ALWAYSRUN_Msk /**< LF clock ALWAYSRUN position definition. */
225 #define NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos CLOCK_LFCLK_ALWAYSRUN_ALWAYSRUN_Pos /**< LF clock ALWAYSRUN mask definition. */
226 #elif NRF_CLOCK_HAS_LFCLKCTRL
227 #define NRF_LFCLKRUN LFCLKSTAT.RUN
228 #define NRF_CLOCK_LFCLKRUN_STATUS_NotTriggered CLOCK_LFCLKSTAT_RUN_STATUS_NotTriggered
229 #define NRF_CLOCK_LFCLKRUN_STATUS_Triggered CLOCK_LFCLKSTAT_RUN_STATUS_Triggered
230 #define NRF_CLOCK_LFCLKRUN_STATUS_Msk CLOCK_LFCLKSTAT_RUN_STATUS_Msk
231 #define NRF_CLOCK_LFCLKRUN_STATUS_Pos CLOCK_LFCLKSTAT_RUN_STATUS_Pos
232 #define NRF_CLOCK_LFCLKSTAT_STATE_Msk CLOCK_LFCLKSTAT_STATE_Msk
233 #define NRF_CLOCK_LFCLKSTAT_STATE_Pos CLOCK_LFCLKSTAT_STATE_Pos
234 #define NRF_CLOCK_INTENSET_LFCLKSTARTED_Msk CLOCK_INTENSET_LFCLKSTARTED_Msk
235 #define NRF_LFCLKALWAYSRUN LFCLKCTRL.ALWAYSRUN
236 #define NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk CLOCK_LFCLKCTRL_ALWAYSRUN_FORCE_Msk
237 #define NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos CLOCK_LFCLKCTRL_ALWAYSRUN_FORCE_Pos
238 #else
239 #define NRF_CLOCK_LFCLKRUN_STATUS_NotTriggered CLOCK_LFCLKRUN_STATUS_NotTriggered
240 #define NRF_CLOCK_LFCLKRUN_STATUS_Triggered CLOCK_LFCLKRUN_STATUS_Triggered
241 #define NRF_CLOCK_INTENSET_LFCLKSTARTED_Msk CLOCK_INTENSET_LFCLKSTARTED_Msk
242 #define NRF_LFCLKSRCCOPY LFCLKSRCCOPY
243 #define NRF_LFCLKRUN LFCLKRUN
244 #define NRF_LFCLKSTAT LFCLKSTAT
245 #define NRF_LFCLKSRC LFCLKSRC
246 #define NRF_LFCLKALWAYSRUN LFCLKALWAYSRUN
247 #define NRF_CLOCK_LFCLKSRCCOPY_SRC_Msk CLOCK_LFCLKSRCCOPY_SRC_Msk
248 #define NRF_CLOCK_LFCLKSRCCOPY_SRC_Pos CLOCK_LFCLKSRCCOPY_SRC_Pos
249 #define NRF_CLOCK_LFCLKRUN_STATUS_Msk CLOCK_LFCLKRUN_STATUS_Msk
250 #define NRF_CLOCK_LFCLKRUN_STATUS_Pos CLOCK_LFCLKRUN_STATUS_Pos
251 #define NRF_CLOCK_LFCLKSTAT_SRC_Msk CLOCK_LFCLKSTAT_SRC_Msk
252 #define NRF_CLOCK_LFCLKSTAT_SRC_Pos CLOCK_LFCLKSTAT_SRC_Pos
253 #define NRF_CLOCK_LFCLKSTAT_STATE_Msk CLOCK_LFCLKSTAT_STATE_Msk
254 #define NRF_CLOCK_LFCLKSTAT_STATE_Pos CLOCK_LFCLKSTAT_STATE_Pos
255 #define NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk
256 #define NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos
257 #define NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk
258 #define NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos
259 #endif
260
261 #if NRF_CLOCK_HAS_XO
262 #define NRF_CLOCK_INTENSET_HFCLKSTARTED_Msk CLOCK_INTEN_XOSTARTED_Msk /**< HF clock bit mask in interrupt register. */
263 #define NRF_TASKS_HFCLKSTART TASKS_XOSTART /**< Task HF clock start definition. */
264 #define NRF_TASKS_HFCLKSTOP TASKS_XOSTOP /**< Task HF clock stop definition. */
265 #define NRF_EVENTS_HFCLKSTARTED EVENTS_XOSTARTED /**< Event HF clock startrd definition. */
266 #define NRF_HFCLKRUN XO.RUN /**< HF clock RUN register definition. */
267 #define NRF_HFCLKSTAT XO.STAT /**< HF clock STAT register definition. */
268 #define NRF_CLOCK_HFCLKRUN_STATUS_Msk CLOCK_XO_RUN_STATUS_Msk /**< HF clock RUN status mask definition. */
269 #define NRF_CLOCK_HFCLKRUN_STATUS_Pos CLOCK_XO_RUN_STATUS_Pos /**< HF clock RUN status position definition. */
270 #define NRF_CLOCK_HFCLKSTAT_STATE_Msk CLOCK_XO_STAT_STATE_Msk /**< HF clock STAT state mask definition. */
271 #define NRF_CLOCK_HFCLKSTAT_STATE_Pos CLOCK_XO_STAT_STATE_Pos /**< HF clock STAT state position definition. */
272 #elif NRF_CLOCK_HAS_HFDOMAIN
273 #define NRF_CLOCK_INTENSET_HFCLKSTARTED_Msk CLOCK_INTENSET_HFCLKSTARTED_Msk
274 #define NRF_TASKS_HFCLKSTART TASKS_HFCLKSTART
275 #define NRF_TASKS_HFCLKSTOP TASKS_HFCLKSTOP
276 #define NRF_EVENTS_HFCLKSTARTED EVENTS_HFCLKSTARTED
277 #define NRF_HFCLKRUN HFCLKRUN
278 #define NRF_HFCLKSTAT HFCLKSTAT
279 #define NRF_CLOCK_HFCLKRUN_STATUS_Msk CLOCK_HFCLKRUN_STATUS_Msk
280 #define NRF_CLOCK_HFCLKRUN_STATUS_Pos CLOCK_HFCLKRUN_STATUS_Pos
281 #define NRF_CLOCK_HFCLKSTAT_STATE_Msk CLOCK_HFCLKSTAT_STATE_Msk
282 #define NRF_CLOCK_HFCLKSTAT_STATE_Pos CLOCK_HFCLKSTAT_STATE_Pos
283 #endif
284
285 /**
286 * @brief Low-frequency clock sources.
287 * @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers.
288 */
289 typedef enum
290 {
291 #if NRF_CLOCK_HAS_LFCLKSTAT
292 NRF_CLOCK_LFCLK_LPRC = (CLOCK_LFCLKSTAT_SRC_LFLPRC_Active << CLOCK_LFCLKSTAT_SRC_LFLPRC_Pos), /**< Internal 32 kHz low power RC oscillator. */
293 #endif
294 #if defined(CLOCK_LFCLKSRC_SRC_LFULP) || defined(__NRFX_DOXYGEN__)
295 NRF_CLOCK_LFCLK_LFULP = CLOCK_LFCLKSRC_SRC_LFULP, /**< Internal 32 kHz Ultra-low power oscillator. */
296 #endif
297
298 #if defined(CLOCK_LFCLKSRC_SRC_RC) || defined(__NRFX_DOXYGEN__)
299 NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */
300 #elif NRF_CLOCK_HAS_LFCLK_TYPE
301 NRF_CLOCK_LFCLK_RC = CLOCK_LFCLK_SRC_SRC_LFRC, /**< Internal 32 kHz RC oscillator. */
302 #elif NRF_CLOCK_HAS_LFCLKSTAT
303 NRF_CLOCK_LFCLK_RC = (CLOCK_LFCLKSTAT_SRC_LFRC_Active << CLOCK_LFCLKSTAT_SRC_LFRC_Pos), /**< Internal 32 kHz RC oscillator. */
304 #else
305 NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_LFRC, /**< Internal 32 kHz RC oscillator. */
306 #endif
307
308 #if defined(CLOCK_LFCLKSRC_SRC_Xtal) || defined(__NRFX_DOXYGEN__)
309 NRF_CLOCK_LFCLK_XTAL = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */
310 #elif NRF_CLOCK_HAS_LFCLK_TYPE
311 NRF_CLOCK_LFCLK_XTAL = CLOCK_LFCLK_SRC_SRC_LFXO, /**< External 32 kHz crystal. */
312 #elif NRF_CLOCK_HAS_LFCLKSTAT
313 NRF_CLOCK_LFCLK_XTAL = (CLOCK_LFCLKSTAT_SRC_LFXO_Active << CLOCK_LFCLKSTAT_SRC_LFXO_Pos), /**< External 32 kHz crystal. */
314 #else
315 NRF_CLOCK_LFCLK_XTAL = CLOCK_LFCLKSRC_SRC_LFXO, /**< External 32 kHz crystal. */
316 #endif
317
318 #if defined(CLOCK_LFCLKSRC_SRC_Synth) || defined(__NRFX_DOXYGEN__)
319 NRF_CLOCK_LFCLK_SYNTH = CLOCK_LFCLKSRC_SRC_Synth, /**< Internal 32 kHz synthesized from HFCLK system clock. */
320 #elif NRF_CLOCK_HAS_LFCLK_TYPE
321 NRF_CLOCK_LFCLK_SYNTH = CLOCK_LFCLK_SRC_SRC_LFSYNT, /**< Internal 32 kHz synthesized from HFCLK system clock. */
322 #elif defined(CLOCK_LFCLKSRC_SRC_LFSYNT)
323 NRF_CLOCK_LFCLK_SYNTH = CLOCK_LFCLKSRC_SRC_LFSYNT, /**< Internal 32 kHz synthesized from HFCLK system clock. */
324 #elif NRF_CLOCK_HAS_LFCLKSTAT
325 NRF_CLOCK_LFCLK_SYNTH = (CLOCK_LFCLKSTAT_SRC_SYNTH_Active << CLOCK_LFCLKSTAT_SRC_SYNTH_Pos), /**< Internal 32 kHz synthesized. */
326 #endif
327
328 #if NRF_CLOCK_HAS_LFCLKSTAT
329 NRF_CLOCK_LFCLK_LPRC_XTAL = NRF_CLOCK_LFCLK_LPRC | NRF_CLOCK_LFCLK_XTAL, /**< Internal 32 kHz low power RC oscillator and external 32 kHz crystal. */
330 NRF_CLOCK_LFCLK_RC_XTAL = NRF_CLOCK_LFCLK_RC | NRF_CLOCK_LFCLK_XTAL, /**< Internal 32 kHz RC oscillator and external 32 kHz crystal. */
331 NRF_CLOCK_LFCLK_SYNTH_XTAL = NRF_CLOCK_LFCLK_SYNTH | NRF_CLOCK_LFCLK_XTAL, /**< Internal 32 kHz synthesized and external 32 kHz crystal. */
332 #endif
333
334 #if defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__)
335 /**
336 * External 32 kHz low swing signal. Used only with the LFCLKSRC register.
337 * For the others @ref NRF_CLOCK_LFCLK_XTAL is returned for this setting.
338 */
339 NRF_CLOCK_LFCLK_XTAL_LOW_SWING = (CLOCK_LFCLKSRC_SRC_Xtal |
340 (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)),
341 /**
342 * External 32 kHz full swing signal. Used only with the LFCLKSRC register.
343 * For the others @ref NRF_CLOCK_LFCLK_XTAL is returned for this setting.
344 */
345 NRF_CLOCK_LFCLK_XTAL_FULL_SWING = (CLOCK_LFCLKSRC_SRC_Xtal |
346 (CLOCK_LFCLKSRC_BYPASS_Enabled << CLOCK_LFCLKSRC_BYPASS_Pos) |
347 (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)),
348 #endif // defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__)
349 } nrf_clock_lfclk_t;
350
351 #if NRF_CLOCK_HAS_HFDOMAIN
352 /**
353 * @brief High-frequency clock sources.
354 * @details Used by HFCLKSTAT and HFCLK192MSTAT registers.
355 */
356 typedef enum
357 {
358 #if defined(CLOCK_HFCLKSTAT_SRC_Xtal) || defined(__NRFX_DOXYGEN__)
359 NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal, /**< External 16 MHz/32 MHz crystal oscillator. */
360 #elif NRF_CLOCK_HAS_XO
361 NRF_CLOCK_HFCLK_HIGH_ACCURACY, /**< External 32 MHz crystal oscillator. */
362 #else
363 NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_HFXO, /**< External 32 MHz crystal oscillator. */
364 #endif
365
366 #if defined(CLOCK_HFCLKSTAT_SRC_RC) || defined(__NRFX_DOXYGEN__)
367 NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_RC, /**< Internal 16 MHz RC oscillator. */
368 #elif defined(CLOCK_HFCLKSTAT_SRC_HFINT)
369 NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_HFINT, /**< Internal 16 MHz RC oscillator. */
370 #else
371 NRF_CLOCK_HFCLK_LOW_ACCURACY, /**< Internal RC oscillator. */
372 #endif
373 } nrf_clock_hfclk_t;
374 #endif
375
376 /** @brief Clock domains. */
377 typedef enum
378 {
379 NRF_CLOCK_DOMAIN_LFCLK,
380 #if NRF_CLOCK_HAS_HFDOMAIN
381 NRF_CLOCK_DOMAIN_HFCLK,
382 #endif
383 #if NRF_CLOCK_HAS_HFCLK192M
384 NRF_CLOCK_DOMAIN_HFCLK192M,
385 #endif
386 #if NRF_CLOCK_HAS_HFCLKAUDIO
387 NRF_CLOCK_DOMAIN_HFCLKAUDIO,
388 #endif
389 } nrf_clock_domain_t;
390
391 #if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M
392 /**
393 * @brief High-frequency clock frequency configuration.
394 * @details Used by HFCLKCTRL and HFCLK192MCTRL registers.
395 */
396 typedef enum
397 {
398 NRF_CLOCK_HFCLK_DIV_1 = CLOCK_HFCLKCTRL_HCLK_Div1, /**< Divide HFCLK/HFCLK192M by 1 */
399 NRF_CLOCK_HFCLK_DIV_2 = CLOCK_HFCLKCTRL_HCLK_Div2, /**< Divide HFCLK/HFCLK192M by 2 */
400 #if NRF_CLOCK_HAS_HFCLK192M
401 NRF_CLOCK_HFCLK_DIV_4 = CLOCK_HFCLK192MCTRL_HCLK192M_Div4, /**< Divide HFCLK192M by 4 */
402 #endif
403 } nrf_clock_hfclk_div_t;
404 #endif // defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M
405
406 /**
407 * @brief Trigger status of task LFCLKSTART/HFCLKSTART.
408 *
409 * @note This enum is deprecated.
410 *
411 * @details Used by LFCLKRUN and HFCLKRUN registers.
412 */
413 typedef enum
414 {
415 NRF_CLOCK_START_TASK_NOT_TRIGGERED = NRF_CLOCK_LFCLKRUN_STATUS_NotTriggered, /**< Task LFCLKSTART/HFCLKSTART has not been triggered. */
416 NRF_CLOCK_START_TASK_TRIGGERED = NRF_CLOCK_LFCLKRUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */
417 } nrf_clock_start_task_status_t;
418
419 /** @brief Interrupts. */
420 typedef enum
421 {
422 #if NRF_CLOCK_HAS_HFDOMAIN
423 NRF_CLOCK_INT_HF_STARTED_MASK = NRF_CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */
424 #endif
425 NRF_CLOCK_INT_LF_STARTED_MASK = NRF_CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */
426 #if NRF_CLOCK_HAS_LFCLK_SRC_CHANGED
427 NRF_CLOCK_INT_LF_SRC_CHANGED_MASK = CLOCK_INTENSET_LFCLKSRCCHANGED_Msk, /**< Interrupt on LFCLKCHANGED event. */
428 #endif
429 #if NRF_CLOCK_HAS_PLL
430 NRFX_CLOCK_INT_PLL_STARTED_MASK = CLOCK_INTENSET_PLLSTARTED_Msk, /**< Interrupt on PLLSTARTED event. */
431 #endif
432 #if NRF_CLOCK_HAS_CALIBRATION
433 NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */
434 #endif
435 #if NRF_CLOCK_HAS_CALIBRATION_TIMER
436 NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk, /**< Interrupt on CTTO event. */
437 #endif
438 #if defined(CLOCK_INTENSET_CTSTARTED_Msk) || defined(__NRFX_DOXYGEN__)
439 NRF_CLOCK_INT_CTSTARTED_MASK = CLOCK_INTENSET_CTSTARTED_Msk, /**< Interrupt on CTSTARTED event. */
440 NRF_CLOCK_INT_CTSTOPPED_MASK = CLOCK_INTENSET_CTSTOPPED_Msk /**< Interrupt on CTSTOPPED event. */
441 #endif
442 #if NRF_CLOCK_HAS_HFCLKAUDIO
443 NRF_CLOCK_INT_HFAUDIO_STARTED_MASK = CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk, /**< Interrupt on HFCLKAUDIOSTARTED event. */
444 #endif
445
446 #if NRF_CLOCK_HAS_HFCLK192M
447 NRF_CLOCK_INT_HF192M_STARTED_MASK = CLOCK_INTENSET_HFCLK192MSTARTED_Msk, /**< Interrupt on HFCLK192MSTARTED event. */
448 #endif
449 #if NRF_CLOCK_HAS_XO_TUNE
450 NRF_CLOCK_INT_XOTUNED_MASK = CLOCK_INTENSET_XOTUNED_Msk, /**< HFXO tuning is done. */
451 NRF_CLOCK_INT_XOTUNEERROR_MASK = CLOCK_INTENSET_XOTUNEERROR_Msk, /**< HFXO quality issue detected, XOTUNE is needed. */
452 NRF_CLOCK_INT_XOTUNEFAILED_MASK = CLOCK_INTENSET_XOTUNEFAILED_Msk, /**< HFXO tuning could not be completed. */
453 #endif
454 } nrf_clock_int_mask_t;
455
456 /**
457 * @brief Tasks.
458 *
459 * @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running.
460 * The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running.
461 */
462 typedef enum
463 {
464 #if NRF_CLOCK_HAS_HFDOMAIN
465 #if NRF_CLOCK_HAS_XO
466 NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_XOSTART), /**< Start HFCLK clock source. */
467 NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_XOSTOP), /**< Stop HFCLK clock source. */
468 #else
469 NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source. */
470 NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source. */
471 #endif
472 #endif
473 #if NRF_CLOCK_HAS_PLL
474 NRF_CLOCK_TASK_PLLSTART = offsetof(NRF_CLOCK_Type, TASKS_PLLSTART), /**< Start PLL and keep it running, regardless of the automatic clock requests. */
475 NRF_CLOCK_TASK_PLLSTOP = offsetof(NRF_CLOCK_Type, TASKS_PLLSTOP), /**< Stop PLL. */
476 #endif
477 NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source. */
478 NRF_CLOCK_TASK_LFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP), /**< Stop LFCLK clock source. */
479 #if NRF_CLOCK_HAS_CALIBRATION
480 NRF_CLOCK_TASK_CAL = offsetof(NRF_CLOCK_Type, TASKS_CAL), /**< Start calibration of LFCLK RC oscillator. */
481 #endif
482 #if NRF_CLOCK_HAS_CALIBRATION_TIMER
483 NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer. */
484 NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer. */
485 #endif
486 #if NRF_CLOCK_HAS_HFCLKAUDIO
487 NRF_CLOCK_TASK_HFCLKAUDIOSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKAUDIOSTART), /**< Start HFCLKAUDIO clock source. */
488 NRF_CLOCK_TASK_HFCLKAUDIOSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKAUDIOSTOP), /**< Stop HFCLKAUDIO clock source. */
489 #endif
490 #if NRF_CLOCK_HAS_HFCLK192M
491 NRF_CLOCK_TASK_HFCLK192MSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLK192MSTART), /**< Start HFCLK192M clock source. */
492 NRF_CLOCK_TASK_HFCLK192MSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLK192MSTOP), /**< Stop HFCLK192M clock source. */
493 #endif
494 #if NRF_CLOCK_HAS_XO_TUNE
495 NRF_CLOCK_TASK_XOTUNE = offsetof(NRF_CLOCK_Type, TASKS_XOTUNE), /**< Start tuning for HFXO. */
496 NRF_CLOCK_TASK_XOTUNEABORT = offsetof(NRF_CLOCK_Type, TASKS_XOTUNEABORT), /**< Stop tuning for HFXO. */
497 #endif
498 } nrf_clock_task_t;
499
500 /** @brief Events. */
501 typedef enum
502 {
503 #if NRF_CLOCK_HAS_HFDOMAIN
504 #if NRF_CLOCK_HAS_XO
505 NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_XOSTARTED), /**< HFCLK oscillator started. */
506 #else
507 NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started. */
508 #endif
509 #endif
510 #if NRF_CLOCK_HAS_PLL
511 NRF_CLOCK_EVENT_PLLSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_PLLSTARTED), /**< PLL started. */
512 #endif
513 NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started. */
514 #if NRF_CLOCK_HAS_LFCLK_SRC_CHANGED
515 NRF_CLOCK_EVENT_LFCLKSRCCHANGED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSRCCHANGED), /**< LFCLK source changed */
516 #endif
517 #if NRF_CLOCK_HAS_CALIBRATION
518 NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed. */
519 #endif
520 #if NRF_CLOCK_HAS_CALIBRATION_TIMER
521 NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO), /**< Calibration timer time-out. */
522 #endif
523 #if defined(CLOCK_INTENSET_CTSTARTED_Msk) || defined(__NRFX_DOXYGEN__)
524 NRF_CLOCK_EVENT_CTSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_CTSTARTED), /**< Calibration timer started. */
525 NRF_CLOCK_EVENT_CTSTOPPED = offsetof(NRF_CLOCK_Type, EVENTS_CTSTOPPED) /**< Calibration timer stopped. */
526 #endif
527 #if NRF_CLOCK_HAS_HFCLKAUDIO
528 NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKAUDIOSTARTED), /**< HFCLKAUDIO oscillator started. */
529 #endif
530 #if NRF_CLOCK_HAS_HFCLK192M
531 NRF_CLOCK_EVENT_HFCLK192MSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLK192MSTARTED), /**< HFCLK192M oscillator started. */
532 #endif
533 #if NRF_CLOCK_HAS_XO_TUNE
534 NRF_CLOCK_EVENT_XOTUNED = offsetof(NRF_CLOCK_Type, EVENTS_XOTUNED), /**< HFXO tuning is done. */
535 NRF_CLOCK_EVENT_XOTUNEERROR = offsetof(NRF_CLOCK_Type, EVENTS_XOTUNEERROR), /**< HFXO quality issue detected, XOTUNE is needed. */
536 NRF_CLOCK_EVENT_XOTUNEFAILED = offsetof(NRF_CLOCK_Type, EVENTS_XOTUNEFAILED), /**< HFXO tuning could not be completed. */
537 #endif
538 } nrf_clock_event_t;
539
540 /**
541 * @brief Function for enabling the specified interrupt.
542 *
543 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
544 * @param[in] mask Mask of interrupts to be enabled.
545 * Use @ref nrf_clock_int_mask_t values for bit masking.
546 */
547 NRF_STATIC_INLINE void nrf_clock_int_enable(NRF_CLOCK_Type * p_reg, uint32_t mask);
548
549 /**
550 * @brief Function for disabling the specified interrupt.
551 *
552 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
553 * @param[in] mask Mask of interrupts to be disabled.
554 * Use @ref nrf_clock_int_mask_t values for bit masking.
555 */
556 NRF_STATIC_INLINE void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask);
557
558 /**
559 * @brief Function for checking if the specified interrupts are enabled.
560 *
561 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
562 * @param[in] mask Mask of interrupts to be checked.
563 * Use @ref nrf_clock_int_mask_t values for bit masking.
564 *
565 * @return Mask of enabled interrupts.
566 */
567 NRF_STATIC_INLINE uint32_t nrf_clock_int_enable_check(NRF_CLOCK_Type const * p_reg, uint32_t mask);
568
569 #if NRF_CLOCK_HAS_INTPEND
570 /**
571 * @brief Function for retrieving the state of pending interrupts.
572 *
573 * @note States of pending interrupt are saved as a bitmask.
574 * One set at particular position means that interrupt for event is pending.
575 *
576 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
577 *
578 * @return Bitmask with information about pending interrupts.
579 * Use @ref nrf_clock_int_mask_t values for bit masking.
580 */
581 NRF_STATIC_INLINE uint32_t nrf_clock_int_pending_get(NRF_CLOCK_Type const * p_reg);
582 #endif
583
584 /**
585 * @brief Function for retrieving the address of the specified task.
586 * @details This function can be used by the PPI module.
587 *
588 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
589 * @param[in] task CLOCK Task.
590 *
591 * @return Address of the requested task register.
592 */
593 NRF_STATIC_INLINE uint32_t nrf_clock_task_address_get(NRF_CLOCK_Type const * p_reg,
594 nrf_clock_task_t task);
595
596 /**
597 * @brief Function for setting the specified task.
598 *
599 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
600 * @param[in] task Task to be activated.
601 */
602 NRF_STATIC_INLINE void nrf_clock_task_trigger(NRF_CLOCK_Type * p_reg, nrf_clock_task_t task);
603
604 /**
605 * @brief Function for retrieving the address of the specified event.
606 * @details This function can be used by the PPI module.
607 *
608 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
609 * @param[in] event CLOCK Event.
610 *
611 * @return Address of the specified event register.
612 */
613 NRF_STATIC_INLINE uint32_t nrf_clock_event_address_get(NRF_CLOCK_Type const * p_reg,
614 nrf_clock_event_t event);
615
616 /**
617 * @brief Function for clearing the specified event.
618 *
619 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
620 * @param[in] event Event to clear.
621 */
622 NRF_STATIC_INLINE void nrf_clock_event_clear(NRF_CLOCK_Type * p_reg, nrf_clock_event_t event);
623
624 /**
625 * @brief Function for retrieving the state of the specified event.
626 *
627 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
628 * @param[in] event Event to be checked.
629 *
630 * @retval true The event has been generated.
631 * @retval false The event has not been generated.
632 */
633 NRF_STATIC_INLINE bool nrf_clock_event_check(NRF_CLOCK_Type const * p_reg, nrf_clock_event_t event);
634
635 /**
636 * @brief Function for retrieving the trigger status of the task START for given domain.
637 *
638 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
639 * @param[in] domain Clock domain.
640 *
641 * @retval false The task START for the given domain has not been triggered.
642 * @retval true The task START for the given domain has been triggered.
643 */
644 NRF_STATIC_INLINE bool nrf_clock_start_task_check(NRF_CLOCK_Type const * p_reg,
645 nrf_clock_domain_t domain);
646
647 /**
648 * @brief Function for retrieving the state of the clock.
649 *
650 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
651 * @param[in] domain Clock domain.
652 * @param[out] p_clk_src Pointer to clock source that is running. Set to NULL if not needed.
653 * Ignored for HFCLKAUDIO domain. Variable pointed by @p p_clk_src
654 * must be of either @ref nrf_clock_lfclk_t type for LFCLK
655 * or @ref nrf_clock_hfclk_t type for HFCLK and HFCLK192M.
656 *
657 * @retval false The clock is not running.
658 * @retval true The clock is running.
659 */
660 NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg,
661 nrf_clock_domain_t domain,
662 void * p_clk_src);
663
664 /**
665 * @brief Function for changing the low-frequency clock source.
666 * @details Check in Product Specification if this function can be called when
667 * the low-frequency clock is running.
668 *
669 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
670 * @param[in] source New low-frequency clock source.
671 */
672 NRF_STATIC_INLINE void nrf_clock_lf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_lfclk_t source);
673
674 /**
675 * @brief Function for retrieving the selected source for the low-frequency clock.
676 *
677 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
678 *
679 * @retval NRF_CLOCK_LFCLK_RC The internal 32 kHz RC oscillator
680 * is the selected source for the low-frequency clock.
681 * @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator
682 * is the selected source for the low-frequency clock.
683 * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesized from
684 * the HFCLK is the selected source for the low-frequency clock.
685 */
686 NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(NRF_CLOCK_Type const * p_reg);
687
688 /**
689 * @brief Function for retrieving the active source of the low-frequency clock.
690 *
691 * @note This function is deprecated. Use @ref nrf_clock_is_running instead.
692 *
693 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
694 *
695 * @retval NRF_CLOCK_LFCLK_RC The internal 32 kHz RC oscillator
696 * is the active source of the low-frequency clock.
697 * @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator
698 * is the active source of the low-frequency clock.
699 * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesized from
700 * the HFCLK is the active source of the low-frequency clock.
701 */
702 NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(NRF_CLOCK_Type const * p_reg);
703
704 #if NRF_CLOCK_HAS_SRC_COPY
705 /**
706 * @brief Function for retrieving the clock source for the LFCLK clock when
707 * the task LKCLKSTART is triggered.
708 *
709 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
710 *
711 * @retval NRF_CLOCK_LFCLK_RC The internal 32 kHz RC oscillator
712 * is running and generating the LFCLK clock.
713 * @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator
714 * is running and generating the LFCLK clock.
715 * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesized from
716 * the HFCLK is running and generating the LFCLK clock.
717 */
718 NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg);
719 #endif
720
721 /**
722 * @brief Function for retrieving the state of the LFCLK clock.
723 *
724 * @note This function is deprecated. Use @ref nrf_clock_is_running instead.
725 *
726 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
727 *
728 * @retval false The LFCLK clock is not running.
729 * @retval true The LFCLK clock is running.
730 */
731 NRF_STATIC_INLINE bool nrf_clock_lf_is_running(NRF_CLOCK_Type const * p_reg);
732
733 /**
734 * @brief Function for retrieving the trigger status of the task LFCLKSTART.
735 *
736 * @note This function is deprecated. Use @ref nrf_clock_start_task_check instead.
737 *
738 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
739 *
740 * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED The task LFCLKSTART has not been triggered.
741 * @retval NRF_CLOCK_START_TASK_TRIGGERED The task LFCLKSTART has been triggered.
742 */
743 NRF_STATIC_INLINE
744 nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(NRF_CLOCK_Type const * p_reg);
745
746 #if NRF_CLOCK_HAS_HFDOMAIN
747 #if NRF_CLOCK_HAS_HFCLKSRC
748 /**
749 * @brief Function for changing the high-frequency clock source.
750 *
751 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
752 * @param[in] source New high-frequency clock source.
753 */
754 NRF_STATIC_INLINE void nrf_clock_hf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source);
755 #endif
756
757 /**
758 * @brief Function for retrieving the selected source of the high-frequency clock.
759 *
760 * For SoCs not featuring the HFCLKSRC register, this is always also the active source
761 * of the high-frequency clock.
762 *
763 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
764 *
765 * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY The internal RC oscillator is the selected
766 * source of the high-frequency clock.
767 * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY An external crystal oscillator is the selected
768 * source of the high-frequency clock.
769 */
770 NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(NRF_CLOCK_Type const * p_reg);
771
772 /**
773 * @brief Function for retrieving the state of the HFCLK clock.
774 *
775 * @note This function is deprecated. Use @ref nrf_clock_is_running instead.
776 *
777 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
778 * @param[in] clk_src Clock source to be checked.
779 *
780 * @retval false The HFCLK clock is not running.
781 * @retval true The HFCLK clock is running.
782 */
783 NRF_STATIC_INLINE bool nrf_clock_hf_is_running(NRF_CLOCK_Type const * p_reg,
784 nrf_clock_hfclk_t clk_src);
785
786 /**
787 * @brief Function for retrieving the trigger status of the task HFCLKSTART.
788 *
789 * @note This function is deprecated. Use @ref nrf_clock_start_task_check instead.
790 *
791 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
792 *
793 * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED The task HFCLKSTART has not been triggered.
794 * @retval NRF_CLOCK_START_TASK_TRIGGERED The task HFCLKSTART has been triggered.
795 */
796 NRF_STATIC_INLINE
797 nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(NRF_CLOCK_Type const * p_reg);
798
799 #if NRF_CLOCK_HAS_HFCLKAUDIO
800 /**
801 * @brief Function for changing the Audio clock FREQ_VALUE.
802 *
803 * The frequency of HFCLKAUDIO ranges from 10.666 MHz to 13.333 MHz in 40.7 Hz steps.
804 * To calculate @p freq_value corresponding to the chosen frequency, use the following equation:
805 * FREQ_VALUE = 2^16 * ((12 * f_out / 32M) - 4)
806 *
807 * @warning Chosen frequency must fit in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands.
808 *
809 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
810 * @param[in] freq_value New FREQ_VALUE
811 */
812 NRF_STATIC_INLINE
813 void nrf_clock_hfclkaudio_config_set(NRF_CLOCK_Type * p_reg, uint16_t freq_value);
814
815 /**
816 * @brief Function for retrieving the Audio clock FREQ_VALUE.
817 *
818 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
819 *
820 * The frequency of HFCLKAUDIO ranges from 10.666 MHz to 13.333 MHz in 40.7 Hz steps.
821 * To calculate frequency corresponding to the returned FREQ_VALUE, use the following equation:
822 * f_out = 32M * (4 + FREQ_VALUE * 2^(-16))/12
823
824 * @return FREQ_VALUE of the Audio clock.
825 */
826 NRF_STATIC_INLINE
827 uint16_t nrf_clock_hfclkaudio_config_get(NRF_CLOCK_Type const * p_reg);
828 #endif
829 #endif // NRF_CLOCK_HAS_HFDOMAIN
830
831 #if NRF_CLOCK_HAS_CALIBRATION_TIMER
832 /**
833 * @brief Function for changing the calibration timer interval.
834 *
835 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
836 * @param[in] interval New calibration timer interval in 0.25 s resolution
837 * (range: 0.25 seconds to 31.75 seconds).
838 */
839 NRF_STATIC_INLINE void nrf_clock_cal_timer_timeout_set(NRF_CLOCK_Type * p_reg, uint32_t interval);
840 #endif
841
842 #if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT)
843 /**
844 * @brief Function for changing the HFCLK frequency divider.
845 *
846 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
847 * @param[in] divider New HFCLK divider.
848 */
849 NRF_STATIC_INLINE void nrf_clock_hfclk_div_set(NRF_CLOCK_Type * p_reg,
850 nrf_clock_hfclk_div_t divider);
851
852 /**
853 * @brief Function for retrieving the HFCLK frequency divider.
854 *
855 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
856 *
857 * @return HFCLK frequency divider.
858 */
859 NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk_div_get(NRF_CLOCK_Type const * p_reg);
860 #endif
861
862 #if NRF_CLOCK_HAS_HFCLK192M
863 /**
864 * @brief Function for changing the HFCLK192M frequency divider.
865 *
866 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
867 * @param[in] divider New HFCLK192M divider.
868 */
869 NRF_STATIC_INLINE void nrf_clock_hfclk192m_div_set(NRF_CLOCK_Type * p_reg,
870 nrf_clock_hfclk_div_t divider);
871
872 /**
873 * @brief Function for retrieving the HFCLK192M frequency divider.
874 *
875 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
876 *
877 * @return HFCLK192M frequency divider.
878 */
879 NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk192m_div_get(NRF_CLOCK_Type const * p_reg);
880
881 /**
882 * @brief Function for changing the HFCLK192M source.
883 *
884 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
885 * @param[in] source New HFCLK192M source.
886 */
887 NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg,
888 nrf_clock_hfclk_t source);
889
890 /**
891 * @brief Function for retrieving the selected source of the HFCLK192M.
892 *
893 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
894 *
895 * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY The internal RC oscillator is the selected
896 * source of the HFCLK192M.
897 * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY An external crystal oscillator is the selected
898 * source of the HFCLK192M.
899 */
900 NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hfclk192m_src_get(NRF_CLOCK_Type const * p_reg);
901 #endif // NRF_CLOCK_HAS_HFCLK192M
902
903 #if (NRF_CLOCK_HAS_LFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK192M || \
904 NRF_CLOCK_HAS_HFCLKAUDIO || NRF_CLOCK_HAS_LFCLKCTRL)
905 /**
906 * @brief Function for setting the clock domain to always run.
907 *
908 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
909 * @param[in] domain Clock domain.
910 * @param[in] alwaysrun Ensure the clock is always running.
911 */
912 NRF_STATIC_INLINE void nrf_clock_alwaysrun_set(NRF_CLOCK_Type * p_reg,
913 nrf_clock_domain_t domain,
914 bool alwaysrun);
915 /**
916 * @brief Function for checking if the clock domain is configured to always run.
917 *
918 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
919 * @param[in] domain Clock domain.
920 *
921 * @retval true The clock domain is configured to always run.
922 * @retval false The clock domain is not configured to always run.
923 */
924 NRF_STATIC_INLINE bool nrf_clock_alwaysrun_get(NRF_CLOCK_Type const * p_reg,
925 nrf_clock_domain_t domain);
926
927 #if NRF_CLOCK_HAS_ALWAYSRUN_ACTIVE
928 /**
929 * @brief Function for checking if the clock domain always run setting is active.
930 *
931 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
932 * @param[in] domain Clock domain.
933 *
934 * @retval true The clock domain always run setting is active.
935 * @retval false The clock domain always run setting is not active.
936 */
937 NRF_STATIC_INLINE bool nrf_clock_alwaysrun_active_get(NRF_CLOCK_Type const * p_reg,
938 nrf_clock_domain_t domain);
939 #endif
940 #endif /* (NRF_CLOCK_HAS_LFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK_ALWAYSRUN ||
941 NRF_CLOCK_HAS_HFCLK192M || NRF_CLOCK_HAS_HFCLKAUDIO || NRF_CLOCK_HAS_LFCLKCTRL) */
942
943 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
944 /**
945 * @brief Function for setting the subscribe configuration for a given
946 * CLOCK task.
947 *
948 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
949 * @param[in] task Task for which to set the configuration.
950 * @param[in] channel Channel through which to subscribe events.
951 */
952 NRF_STATIC_INLINE void nrf_clock_subscribe_set(NRF_CLOCK_Type * p_reg,
953 nrf_clock_task_t task,
954 uint8_t channel);
955
956 /**
957 * @brief Function for clearing the subscribe configuration for a given
958 * CLOCK task.
959 *
960 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
961 * @param[in] task Task for which to clear the configuration.
962 */
963 NRF_STATIC_INLINE void nrf_clock_subscribe_clear(NRF_CLOCK_Type * p_reg, nrf_clock_task_t task);
964
965 /**
966 * @brief Function for setting the publish configuration for a given
967 * CLOCK event.
968 *
969 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
970 * @param[in] event Event for which to set the configuration.
971 * @param[in] channel Channel through which to publish the event.
972 */
973 NRF_STATIC_INLINE void nrf_clock_publish_set(NRF_CLOCK_Type * p_reg,
974 nrf_clock_event_t event,
975 uint8_t channel);
976
977 /**
978 * @brief Function for clearing the publish configuration for a given
979 * CLOCK event.
980 *
981 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
982 * @param[in] event Event for which to clear the configuration.
983 */
984 NRF_STATIC_INLINE void nrf_clock_publish_clear(NRF_CLOCK_Type * p_reg, nrf_clock_event_t event);
985 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
986
987 #if NRF_CLOCK_HAS_CONFIG
988 /**
989 * @brief Function controls reset to the LF CLOCK peripheral.
990 *
991 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
992 * @param[in] enable Enable reset.
993 */
994 NRF_STATIC_INLINE void nrf_clock_config_reset_enable_set(NRF_CLOCK_Type * p_reg, bool enable);
995
996 /**
997 * @brief Function for enabling bypass.
998 *
999 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1000 * @param[in] source Bypass source.
1001 * @param[in] enable Enable bypass.
1002 */
1003 NRF_STATIC_INLINE void nrf_clock_config_bypass_enable_set(NRF_CLOCK_Type * p_reg,
1004 nrf_clock_lfclk_t source,
1005 bool enable);
1006
1007 /**
1008 * @brief Function for setting the timeout value for the clock alignment procedure.
1009 *
1010 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1011 * @param[in] timeout Number of 32Ki clocks.
1012 */
1013 NRF_STATIC_INLINE void nrf_clock_config_timeout_set(NRF_CLOCK_Type * p_reg,
1014 uint8_t timeout);
1015
1016 /**
1017 * @brief Function for getting the timeout value for the clock alignment procedure.
1018 *
1019 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1020 *
1021 * @retval Number of 32Ki clocks.
1022 */
1023 NRF_STATIC_INLINE uint8_t nrf_clock_config_timeout_get(NRF_CLOCK_Type const * p_reg);
1024
1025 /**
1026 * @brief Function for setting threshold limit while clock switching.
1027 *
1028 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1029 * @param[in] thr_low Threshold low limit while clock switching.
1030 * @param[in] thr_high Threshold high limit while clock switching.
1031 * @param[in] thr_diff Threshold difference while clock switching.
1032 */
1033 NRF_STATIC_INLINE void nrf_clock_config_threshold_set(NRF_CLOCK_Type * p_reg,
1034 uint8_t thr_low,
1035 uint8_t thr_high,
1036 uint8_t thr_diff);
1037 #endif // NRF_CLOCK_HAS_CONFIG
1038
1039 #ifndef NRF_DECLARE_ONLY
1040
nrf_clock_int_enable(NRF_CLOCK_Type * p_reg,uint32_t mask)1041 NRF_STATIC_INLINE void nrf_clock_int_enable(NRF_CLOCK_Type * p_reg, uint32_t mask)
1042 {
1043 p_reg->INTENSET = mask;
1044 }
1045
nrf_clock_int_disable(NRF_CLOCK_Type * p_reg,uint32_t mask)1046 NRF_STATIC_INLINE void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask)
1047 {
1048 p_reg->INTENCLR = mask;
1049 }
1050
nrf_clock_int_enable_check(NRF_CLOCK_Type const * p_reg,uint32_t mask)1051 NRF_STATIC_INLINE uint32_t nrf_clock_int_enable_check(NRF_CLOCK_Type const * p_reg, uint32_t mask)
1052 {
1053 return p_reg->INTENSET & mask;
1054 }
1055
1056 #if NRF_CLOCK_HAS_INTPEND
nrf_clock_int_pending_get(NRF_CLOCK_Type const * p_reg)1057 NRF_STATIC_INLINE uint32_t nrf_clock_int_pending_get(NRF_CLOCK_Type const * p_reg)
1058 {
1059 return p_reg->INTPEND;
1060 }
1061 #endif
1062
nrf_clock_task_address_get(NRF_CLOCK_Type const * p_reg,nrf_clock_task_t task)1063 NRF_STATIC_INLINE uint32_t nrf_clock_task_address_get(NRF_CLOCK_Type const * p_reg,
1064 nrf_clock_task_t task)
1065 {
1066 return nrf_task_event_address_get(p_reg, task);
1067 }
1068
nrf_clock_task_trigger(NRF_CLOCK_Type * p_reg,nrf_clock_task_t task)1069 NRF_STATIC_INLINE void nrf_clock_task_trigger(NRF_CLOCK_Type * p_reg, nrf_clock_task_t task)
1070 {
1071 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
1072 }
1073
nrf_clock_event_address_get(NRF_CLOCK_Type const * p_reg,nrf_clock_event_t event)1074 NRF_STATIC_INLINE uint32_t nrf_clock_event_address_get(NRF_CLOCK_Type const * p_reg,
1075 nrf_clock_event_t event)
1076 {
1077 return nrf_task_event_address_get(p_reg, event);
1078 }
1079
nrf_clock_event_clear(NRF_CLOCK_Type * p_reg,nrf_clock_event_t event)1080 NRF_STATIC_INLINE void nrf_clock_event_clear(NRF_CLOCK_Type * p_reg, nrf_clock_event_t event)
1081 {
1082 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
1083 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
1084 }
1085
nrf_clock_event_check(NRF_CLOCK_Type const * p_reg,nrf_clock_event_t event)1086 NRF_STATIC_INLINE bool nrf_clock_event_check(NRF_CLOCK_Type const * p_reg, nrf_clock_event_t event)
1087 {
1088 return nrf_event_check(p_reg, event);
1089 }
1090
nrf_clock_start_task_check(NRF_CLOCK_Type const * p_reg,nrf_clock_domain_t domain)1091 NRF_STATIC_INLINE bool nrf_clock_start_task_check(NRF_CLOCK_Type const * p_reg,
1092 nrf_clock_domain_t domain)
1093 {
1094 switch (domain)
1095 {
1096 case NRF_CLOCK_DOMAIN_LFCLK:
1097 return ((p_reg->NRF_LFCLKRUN & NRF_CLOCK_LFCLKRUN_STATUS_Msk)
1098 >> NRF_CLOCK_LFCLKRUN_STATUS_Pos);
1099 #if NRF_CLOCK_HAS_HFDOMAIN
1100 case NRF_CLOCK_DOMAIN_HFCLK:
1101 return ((p_reg->NRF_HFCLKRUN & NRF_CLOCK_HFCLKRUN_STATUS_Msk)
1102 >> NRF_CLOCK_HFCLKRUN_STATUS_Pos);
1103 #endif
1104 #if NRF_CLOCK_HAS_HFCLK192M
1105 case NRF_CLOCK_DOMAIN_HFCLK192M:
1106 return ((p_reg->HFCLK192MRUN & CLOCK_HFCLK192MRUN_STATUS_Msk)
1107 >> CLOCK_HFCLK192MRUN_STATUS_Pos);
1108 #endif
1109 #if NRF_CLOCK_HAS_HFCLKAUDIO
1110 case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
1111 return ((p_reg->HFCLKAUDIORUN & CLOCK_HFCLKAUDIORUN_STATUS_Msk)
1112 >> CLOCK_HFCLKAUDIORUN_STATUS_Pos);
1113 #endif
1114 default:
1115 NRFX_ASSERT(0);
1116 return false;
1117 }
1118 }
1119
1120 /*
1121 * `-Warray-bounds` warning is disabled for the `nrf_clock_is_running`
1122 * function because GCC 12 and above may report a false positive due to the
1123 * size of the write access to the memory address pointed by the `p_clk_src`
1124 * argument being variable depending on the value of the `domain` argument.
1125 */
1126 #if defined(__GNUC__)
1127 #pragma GCC diagnostic push
1128 #pragma GCC diagnostic ignored "-Warray-bounds"
1129 #endif
1130
nrf_clock_is_running(NRF_CLOCK_Type const * p_reg,nrf_clock_domain_t domain,void * p_clk_src)1131 NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg,
1132 nrf_clock_domain_t domain,
1133 void * p_clk_src)
1134 {
1135 bool clock_running = false;
1136 switch (domain)
1137 {
1138 case NRF_CLOCK_DOMAIN_LFCLK:
1139 #if NRF_CLOCK_HAS_LFCLKSTAT
1140 clock_running = p_reg->LFCLKSTAT.SRC;
1141 if (p_clk_src != NULL)
1142 {
1143 (*(nrf_clock_lfclk_t *)p_clk_src) = (nrf_clock_lfclk_t)(p_reg->LFCLKSTAT.SRC);
1144 }
1145 break;
1146 #else
1147 clock_running = p_reg->NRF_LFCLKSTAT & NRF_CLOCK_LFCLKSTAT_STATE_Msk;
1148 if (p_clk_src != NULL)
1149 {
1150 (*(nrf_clock_lfclk_t *)p_clk_src) =
1151 (nrf_clock_lfclk_t)((p_reg->NRF_LFCLKSTAT & NRF_CLOCK_LFCLKSTAT_SRC_Msk)
1152 >> NRF_CLOCK_LFCLKSTAT_SRC_Pos);
1153 }
1154 break;
1155 #endif
1156 #if NRF_CLOCK_HAS_HFDOMAIN
1157 case NRF_CLOCK_DOMAIN_HFCLK:
1158 clock_running = p_reg->NRF_HFCLKSTAT & NRF_CLOCK_HFCLKSTAT_STATE_Msk;
1159 if (p_clk_src != NULL)
1160 {
1161 #if NRF_CLOCK_HAS_XO
1162 /* XO registers do not contain information about low accuracy source being active.
1163 * It has to be derived from HFCLK state. */
1164 (*(nrf_clock_hfclk_t *)p_clk_src) = clock_running ? NRF_CLOCK_HFCLK_HIGH_ACCURACY :
1165 NRF_CLOCK_HFCLK_LOW_ACCURACY;
1166 #else
1167 (*(nrf_clock_hfclk_t *)p_clk_src) =
1168 (nrf_clock_hfclk_t)((p_reg->NRF_HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
1169 >> CLOCK_HFCLKSTAT_SRC_Pos);
1170 #endif
1171 }
1172 break;
1173 #endif
1174 #if NRF_CLOCK_HAS_HFCLK192M
1175 case NRF_CLOCK_DOMAIN_HFCLK192M:
1176 clock_running = p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_STATE_Msk;
1177 if (p_clk_src != NULL)
1178 {
1179 (*(nrf_clock_hfclk_t *)p_clk_src) =
1180 (nrf_clock_hfclk_t)((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_SRC_Msk)
1181 >> CLOCK_HFCLK192MSTAT_SRC_Pos);
1182 }
1183 break;
1184 #endif
1185 #if NRF_CLOCK_HAS_HFCLKAUDIO
1186 case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
1187 clock_running = p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_STATE_Msk;
1188 break;
1189 #endif
1190 default:
1191 NRFX_ASSERT(0);
1192 return false;
1193 }
1194 return clock_running;
1195 }
1196
1197 #if defined(__GNUC__)
1198 #pragma GCC diagnostic pop
1199 #endif
1200
nrf_clock_lf_src_set(NRF_CLOCK_Type * p_reg,nrf_clock_lfclk_t source)1201 NRF_STATIC_INLINE void nrf_clock_lf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_lfclk_t source)
1202 {
1203 #if NRF_CLOCK_HAS_LFCLKCTRL
1204 p_reg->LFCLKCTRL.SRC = (uint32_t)(source);
1205 #else
1206 p_reg->NRF_LFCLKSRC = (uint32_t)(source);
1207 #endif
1208 }
1209
nrf_clock_lf_src_get(NRF_CLOCK_Type const * p_reg)1210 NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(NRF_CLOCK_Type const * p_reg)
1211 {
1212 #if NRF_CLOCK_HAS_LFCLKCTRL
1213 return (nrf_clock_lfclk_t)(p_reg->LFCLKCTRL.SRC);
1214 #else
1215 return (nrf_clock_lfclk_t)(p_reg->NRF_LFCLKSRC);
1216 #endif
1217 }
1218
nrf_clock_lf_actv_src_get(NRF_CLOCK_Type const * p_reg)1219 NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(NRF_CLOCK_Type const * p_reg)
1220 {
1221 nrf_clock_lfclk_t clk_src;
1222 (void)nrf_clock_is_running(p_reg, NRF_CLOCK_DOMAIN_LFCLK, &clk_src);
1223 return clk_src;
1224 }
1225
1226 #if NRF_CLOCK_HAS_SRC_COPY
nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)1227 NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg)
1228 {
1229 return (nrf_clock_lfclk_t)((p_reg->NRF_LFCLKSRCCOPY & NRF_CLOCK_LFCLKSRCCOPY_SRC_Msk)
1230 >> NRF_CLOCK_LFCLKSRCCOPY_SRC_Pos);
1231 }
1232 #endif
1233
nrf_clock_lf_is_running(NRF_CLOCK_Type const * p_reg)1234 NRF_STATIC_INLINE bool nrf_clock_lf_is_running(NRF_CLOCK_Type const * p_reg)
1235 {
1236 return nrf_clock_is_running(p_reg, NRF_CLOCK_DOMAIN_LFCLK, NULL);
1237 }
1238
1239 NRF_STATIC_INLINE
nrf_clock_lf_start_task_status_get(NRF_CLOCK_Type const * p_reg)1240 nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(NRF_CLOCK_Type const * p_reg)
1241 {
1242 return (nrf_clock_start_task_status_t)nrf_clock_start_task_check(p_reg,
1243 NRF_CLOCK_DOMAIN_LFCLK);
1244 }
1245
1246 #if NRF_CLOCK_HAS_HFDOMAIN
1247 #if NRF_CLOCK_HAS_HFCLKSRC
nrf_clock_hf_src_set(NRF_CLOCK_Type * p_reg,nrf_clock_hfclk_t source)1248 NRF_STATIC_INLINE void nrf_clock_hf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
1249 {
1250 p_reg->HFCLKSRC = (uint32_t)(source);
1251 }
1252 #endif
1253
nrf_clock_hf_src_get(NRF_CLOCK_Type const * p_reg)1254 NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(NRF_CLOCK_Type const * p_reg)
1255 {
1256 #if NRF_CLOCK_HAS_HFCLKSRC
1257 return (nrf_clock_hfclk_t)(p_reg->HFCLKSRC);
1258 #elif NRF_CLOCK_HAS_XO
1259 /* XO registers do not contain information about low accuracy source being active.
1260 * It has to be derived from HFCLK state. */
1261 return (p_reg->NRF_HFCLKSTAT & NRF_CLOCK_HFCLKSTAT_STATE_Msk) ? NRF_CLOCK_HFCLK_HIGH_ACCURACY :
1262 NRF_CLOCK_HFCLK_LOW_ACCURACY;
1263 #else
1264 return (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
1265 >> CLOCK_HFCLKSTAT_SRC_Pos);
1266 #endif
1267 }
1268
nrf_clock_hf_is_running(NRF_CLOCK_Type const * p_reg,nrf_clock_hfclk_t clk_src)1269 NRF_STATIC_INLINE bool nrf_clock_hf_is_running(NRF_CLOCK_Type const * p_reg,
1270 nrf_clock_hfclk_t clk_src)
1271 {
1272 nrf_clock_hfclk_t active_clk_src;
1273 bool ret = nrf_clock_is_running(p_reg, NRF_CLOCK_DOMAIN_HFCLK, &active_clk_src);
1274 return (ret && (active_clk_src == clk_src));
1275 }
1276
1277 NRF_STATIC_INLINE
nrf_clock_hf_start_task_status_get(NRF_CLOCK_Type const * p_reg)1278 nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(NRF_CLOCK_Type const * p_reg)
1279 {
1280 return (nrf_clock_start_task_status_t)nrf_clock_start_task_check(p_reg,
1281 NRF_CLOCK_DOMAIN_HFCLK);
1282 }
1283 #endif // NRF_CLOCK_HAS_HFDOMAIN
1284
1285 #if NRF_CLOCK_HAS_HFCLKAUDIO
1286 NRF_STATIC_INLINE
nrf_clock_hfclkaudio_config_set(NRF_CLOCK_Type * p_reg,uint16_t freq_value)1287 void nrf_clock_hfclkaudio_config_set(NRF_CLOCK_Type * p_reg, uint16_t freq_value)
1288 {
1289 p_reg->HFCLKAUDIO.FREQUENCY = freq_value;
1290 }
1291
1292 NRF_STATIC_INLINE
nrf_clock_hfclkaudio_config_get(NRF_CLOCK_Type const * p_reg)1293 uint16_t nrf_clock_hfclkaudio_config_get(NRF_CLOCK_Type const * p_reg)
1294 {
1295 return (uint16_t)(p_reg->HFCLKAUDIO.FREQUENCY);
1296 }
1297 #endif
1298
1299 #if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT)
1300 NRF_STATIC_INLINE
nrf_clock_hfclk_div_set(NRF_CLOCK_Type * p_reg,nrf_clock_hfclk_div_t divider)1301 void nrf_clock_hfclk_div_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_div_t divider)
1302 {
1303 p_reg->HFCLKCTRL = (((uint8_t)(divider) << CLOCK_HFCLKCTRL_HCLK_Pos) &
1304 CLOCK_HFCLKCTRL_HCLK_Msk);
1305 }
1306
nrf_clock_hfclk_div_get(NRF_CLOCK_Type const * p_reg)1307 NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk_div_get(NRF_CLOCK_Type const * p_reg)
1308 {
1309 return (nrf_clock_hfclk_div_t)((p_reg->HFCLKCTRL & CLOCK_HFCLKCTRL_HCLK_Msk)
1310 >> CLOCK_HFCLKCTRL_HCLK_Pos);
1311 }
1312 #endif
1313
1314 #if NRF_CLOCK_HAS_HFCLK192M
1315 NRF_STATIC_INLINE
nrf_clock_hfclk192m_div_set(NRF_CLOCK_Type * p_reg,nrf_clock_hfclk_div_t divider)1316 void nrf_clock_hfclk192m_div_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_div_t divider)
1317 {
1318 p_reg->HFCLK192MCTRL = (((uint8_t)(divider) << CLOCK_HFCLK192MCTRL_HCLK192M_Pos) &
1319 CLOCK_HFCLK192MCTRL_HCLK192M_Msk);
1320 }
1321
nrf_clock_hfclk192m_div_get(NRF_CLOCK_Type const * p_reg)1322 NRF_STATIC_INLINE nrf_clock_hfclk_div_t nrf_clock_hfclk192m_div_get(NRF_CLOCK_Type const * p_reg)
1323 {
1324 return (nrf_clock_hfclk_div_t)((p_reg->HFCLK192MCTRL & CLOCK_HFCLK192MCTRL_HCLK192M_Msk)
1325 >> CLOCK_HFCLK192MCTRL_HCLK192M_Pos);
1326 }
1327
nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg,nrf_clock_hfclk_t source)1328 NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_t source)
1329 {
1330 p_reg->HFCLK192MSRC = (uint32_t)(source);
1331 }
1332
nrf_clock_hfclk192m_src_get(NRF_CLOCK_Type const * p_reg)1333 NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hfclk192m_src_get(NRF_CLOCK_Type const * p_reg)
1334 {
1335 return (nrf_clock_hfclk_t)(p_reg->HFCLK192MSRC);
1336 }
1337 #endif
1338
1339 #if NRF_CLOCK_HAS_CALIBRATION_TIMER
nrf_clock_cal_timer_timeout_set(NRF_CLOCK_Type * p_reg,uint32_t interval)1340 NRF_STATIC_INLINE void nrf_clock_cal_timer_timeout_set(NRF_CLOCK_Type * p_reg, uint32_t interval)
1341 {
1342 p_reg->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk);
1343 }
1344 #endif
1345
1346 #if (NRF_CLOCK_HAS_LFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK192M || \
1347 NRF_CLOCK_HAS_HFCLKAUDIO || NRF_CLOCK_HAS_LFCLKCTRL)
nrf_clock_alwaysrun_set(NRF_CLOCK_Type * p_reg,nrf_clock_domain_t domain,bool alwaysrun)1348 NRF_STATIC_INLINE void nrf_clock_alwaysrun_set(NRF_CLOCK_Type * p_reg,
1349 nrf_clock_domain_t domain,
1350 bool alwaysrun)
1351 {
1352 switch (domain)
1353 {
1354 #if NRF_CLOCK_HAS_LFCLK_ALWAYSRUN || NRF_CLOCK_HAS_LFCLKCTRL
1355 case NRF_CLOCK_DOMAIN_LFCLK:
1356 p_reg->NRF_LFCLKALWAYSRUN =
1357 ((alwaysrun << NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos)
1358 & NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk);
1359 break;
1360 #endif
1361 #if NRF_CLOCK_HAS_HFCLK_ALWAYSRUN
1362 case NRF_CLOCK_DOMAIN_HFCLK:
1363 p_reg->HFCLKALWAYSRUN =
1364 ((alwaysrun << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos)
1365 & CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk);
1366 break;
1367 #endif
1368 #if NRF_CLOCK_HAS_HFCLK192M
1369 case NRF_CLOCK_DOMAIN_HFCLK192M:
1370 p_reg->HFCLK192MALWAYSRUN =
1371 ((alwaysrun << CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos)
1372 & CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk);
1373 break;
1374 #endif
1375 #if NRF_CLOCK_HAS_HFCLKAUDIO
1376 case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
1377 p_reg->HFCLKAUDIOALWAYSRUN =
1378 ((alwaysrun << CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos)
1379 & CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk);
1380 break;
1381 #endif
1382 default:
1383 NRFX_ASSERT(0);
1384 break;
1385 }
1386 }
1387
nrf_clock_alwaysrun_get(NRF_CLOCK_Type const * p_reg,nrf_clock_domain_t domain)1388 NRF_STATIC_INLINE bool nrf_clock_alwaysrun_get(NRF_CLOCK_Type const * p_reg,
1389 nrf_clock_domain_t domain)
1390 {
1391 switch (domain)
1392 {
1393 #if NRF_CLOCK_HAS_LFCLK_ALWAYSRUN || NRF_CLOCK_HAS_LFCLKCTRL
1394 case NRF_CLOCK_DOMAIN_LFCLK:
1395 return ((p_reg->NRF_LFCLKALWAYSRUN & NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk)
1396 >> NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos);
1397 #endif
1398 #if NRF_CLOCK_HAS_HFCLK_ALWAYSRUN
1399 case NRF_CLOCK_DOMAIN_HFCLK:
1400 return ((p_reg->HFCLKALWAYSRUN & CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk)
1401 >> CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos);
1402 #endif
1403 #if NRF_CLOCK_HAS_HFCLK192M
1404 case NRF_CLOCK_DOMAIN_HFCLK192M:
1405 return ((p_reg->HFCLK192MALWAYSRUN & CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk)
1406 >> CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos);
1407 #endif
1408 #if NRF_CLOCK_HAS_HFCLKAUDIO
1409 case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
1410 return ((p_reg->HFCLKAUDIOALWAYSRUN & CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk)
1411 >> CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos);
1412 #endif
1413 default:
1414 NRFX_ASSERT(0);
1415 return false;
1416 }
1417 }
1418
1419 #if NRF_CLOCK_HAS_ALWAYSRUN_ACTIVE
nrf_clock_alwaysrun_active_get(NRF_CLOCK_Type const * p_reg,nrf_clock_domain_t domain)1420 NRF_STATIC_INLINE bool nrf_clock_alwaysrun_active_get(NRF_CLOCK_Type const * p_reg,
1421 nrf_clock_domain_t domain)
1422 {
1423 switch (domain)
1424 {
1425 #if NRF_CLOCK_HAS_LFCLK_ALWAYSRUN
1426 case NRF_CLOCK_DOMAIN_LFCLK:
1427 return ((p_reg->NRF_LFCLKSTAT & NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk)
1428 >> NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos);
1429 #endif
1430 #if NRF_CLOCK_HAS_HFCLK_ALWAYSRUN
1431 case NRF_CLOCK_DOMAIN_HFCLK:
1432 return ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk)
1433 >> CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos);
1434 #endif
1435 #if NRF_CLOCK_HAS_HFCLK192M
1436 case NRF_CLOCK_DOMAIN_HFCLK192M:
1437 return ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk)
1438 >> CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos);
1439 #endif
1440 #if NRF_CLOCK_HAS_HFCLKAUDIO
1441 case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
1442 return ((p_reg->HFCLKAUDIOSTAT & CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Msk)
1443 >> CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos);
1444 #endif
1445 default:
1446 NRFX_ASSERT(0);
1447 return false;
1448 }
1449 }
1450 #endif
1451 #endif /* (NRF_CLOCK_HAS_LFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK_ALWAYSRUN ||
1452 NRF_CLOCK_HAS_HFCLK192M || NRF_CLOCK_HAS_HFCLKAUDIO || NRF_CLOCK_HAS_LFCLKCTRL) */
1453
1454 #if defined(DPPI_PRESENT)
nrf_clock_subscribe_set(NRF_CLOCK_Type * p_reg,nrf_clock_task_t task,uint8_t channel)1455 NRF_STATIC_INLINE void nrf_clock_subscribe_set(NRF_CLOCK_Type * p_reg,
1456 nrf_clock_task_t task,
1457 uint8_t channel)
1458 {
1459 *((volatile uint32_t *) ((uint8_t *)p_reg+ (uint32_t)task + 0x80uL)) =
1460 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1461 }
1462
nrf_clock_subscribe_clear(NRF_CLOCK_Type * p_reg,nrf_clock_task_t task)1463 NRF_STATIC_INLINE void nrf_clock_subscribe_clear(NRF_CLOCK_Type * p_reg, nrf_clock_task_t task)
1464 {
1465 *((volatile uint32_t *) ((uint8_t *)p_reg + (uint32_t)task + 0x80uL)) = 0;
1466 }
1467
nrf_clock_publish_set(NRF_CLOCK_Type * p_reg,nrf_clock_event_t event,uint8_t channel)1468 NRF_STATIC_INLINE void nrf_clock_publish_set(NRF_CLOCK_Type * p_reg,
1469 nrf_clock_event_t event,
1470 uint8_t channel)
1471 {
1472 *((volatile uint32_t *) ((uint8_t *)p_reg + (uint32_t)event + 0x80uL)) =
1473 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1474 }
1475
nrf_clock_publish_clear(NRF_CLOCK_Type * p_reg,nrf_clock_event_t event)1476 NRF_STATIC_INLINE void nrf_clock_publish_clear(NRF_CLOCK_Type * p_reg, nrf_clock_event_t event)
1477 {
1478 *((volatile uint32_t *) ((uint8_t *)p_reg + (uint32_t)event + 0x80uL)) = 0;
1479 }
1480 #endif // defined(DPPI_PRESENT)
1481
1482 #if NRF_CLOCK_HAS_CONFIG
nrf_clock_config_reset_enable_set(NRF_CLOCK_Type * p_reg,bool enable)1483 NRF_STATIC_INLINE void nrf_clock_config_reset_enable_set(NRF_CLOCK_Type * p_reg, bool enable)
1484 {
1485 p_reg->CONFIG.SETUP = (p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_RESET_Msk) |
1486 (enable ? CLOCK_CONFIG_SETUP_RESET_Enabled
1487 : CLOCK_CONFIG_SETUP_RESET_Disabled)
1488 << CLOCK_CONFIG_SETUP_RESET_Pos;
1489 }
1490
nrf_clock_config_bypass_enable_set(NRF_CLOCK_Type * p_reg,nrf_clock_lfclk_t source,bool enable)1491 NRF_STATIC_INLINE void nrf_clock_config_bypass_enable_set(NRF_CLOCK_Type * p_reg,
1492 nrf_clock_lfclk_t source,
1493 bool enable)
1494 {
1495 switch (source)
1496 {
1497 case NRF_CLOCK_LFCLK_LPRC:
1498 p_reg->CONFIG.SETUP = (p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_BYPASSLFLPRC_Msk) |
1499 (enable ? CLOCK_CONFIG_SETUP_BYPASSLFLPRC_Enabled
1500 : CLOCK_CONFIG_SETUP_BYPASSLFLPRC_Disabled)
1501 << CLOCK_CONFIG_SETUP_BYPASSLFLPRC_Pos;
1502 break;
1503 case NRF_CLOCK_LFCLK_RC:
1504 p_reg->CONFIG.SETUP = (p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_BYPASSLFRC_Msk) |
1505 (enable ? CLOCK_CONFIG_SETUP_BYPASSLFRC_Enabled
1506 : CLOCK_CONFIG_SETUP_BYPASSLFRC_Disabled)
1507 << CLOCK_CONFIG_SETUP_BYPASSLFRC_Pos;
1508 break;
1509 case NRF_CLOCK_LFCLK_XTAL:
1510 p_reg->CONFIG.SETUP = (p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_BYPASSLFXO_Msk) |
1511 (enable ? CLOCK_CONFIG_SETUP_BYPASSLFXO_Enabled
1512 : CLOCK_CONFIG_SETUP_BYPASSLFXO_Disabled)
1513 << CLOCK_CONFIG_SETUP_BYPASSLFXO_Pos;
1514 break;
1515 case NRF_CLOCK_LFCLK_SYNTH:
1516 p_reg->CONFIG.SETUP = (p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_BYPASSSYNTH_Msk) |
1517 (enable ? CLOCK_CONFIG_SETUP_BYPASSSYNTH_Enabled
1518 : CLOCK_CONFIG_SETUP_BYPASSSYNTH_Disabled)
1519 << CLOCK_CONFIG_SETUP_BYPASSSYNTH_Pos;
1520 break;
1521 default:
1522 NRFX_ASSERT(0);
1523 break;
1524 }
1525 }
1526
nrf_clock_config_timeout_set(NRF_CLOCK_Type * p_reg,uint8_t timeout)1527 NRF_STATIC_INLINE void nrf_clock_config_timeout_set(NRF_CLOCK_Type * p_reg,
1528 uint8_t timeout)
1529 {
1530 p_reg->CONFIG.SETUP = ((p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_TIMEOUT_Msk)
1531 | ((timeout << CLOCK_CONFIG_SETUP_TIMEOUT_Pos)
1532 & CLOCK_CONFIG_SETUP_TIMEOUT_Msk));
1533 }
1534
nrf_clock_config_timeout_get(NRF_CLOCK_Type const * p_reg)1535 NRF_STATIC_INLINE uint8_t nrf_clock_config_timeout_get(NRF_CLOCK_Type const * p_reg)
1536 {
1537 return (p_reg->CONFIG.SETUP & CLOCK_CONFIG_SETUP_TIMEOUT_Msk) >> CLOCK_CONFIG_SETUP_TIMEOUT_Pos;
1538 }
1539
nrf_clock_config_threshold_set(NRF_CLOCK_Type * p_reg,uint8_t thr_low,uint8_t thr_high,uint8_t thr_diff)1540 NRF_STATIC_INLINE void nrf_clock_config_threshold_set(NRF_CLOCK_Type * p_reg,
1541 uint8_t thr_low,
1542 uint8_t thr_high,
1543 uint8_t thr_diff)
1544 {
1545 p_reg->CONFIG.THRESHOLD = ((((uint32_t)thr_low) << CLOCK_CONFIG_THRESHOLD_LOW_Pos)
1546 & CLOCK_CONFIG_THRESHOLD_LOW_Msk) |
1547 ((((uint32_t)thr_high) << CLOCK_CONFIG_THRESHOLD_HIGH_Pos)
1548 & CLOCK_CONFIG_THRESHOLD_HIGH_Msk) |
1549 ((((uint32_t)thr_diff) << CLOCK_CONFIG_THRESHOLD_DIFF_Pos)
1550 & CLOCK_CONFIG_THRESHOLD_DIFF_Msk);
1551 }
1552 #endif // NRF_CLOCK_HAS_CONFIG
1553
1554 #endif // NRF_DECLARE_ONLY
1555
1556 /** @} */
1557
1558 #ifdef __cplusplus
1559 }
1560 #endif
1561
1562 #endif // NRF_CLOCK_H__
1563
