1 /* 2 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 3 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, this 10 list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its 17 contributors may be used to endorse or promote products derived from this 18 software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 * 32 * @file nrf52840.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 07. January 2025 36 * @note Generated by SVDConv V3.3.35 on Tuesday, 07.01.2025 15:34:16 37 * from File 'nrf52840.svd', 38 * last modified on Friday, 13.12.2024 08:41:10 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf52840 49 * @{ 50 */ 51 52 53 #ifndef NRF52840_H 54 #define NRF52840_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 82 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 83 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 84 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 85 /* ========================================== nrf52840 Specific Interrupt Numbers ========================================== */ 86 CLOCK_POWER_IRQn = 0, /*!< 0 CLOCK_POWER */ 87 RADIO_IRQn = 1, /*!< 1 RADIO */ 88 UART0_UARTE0_IRQn = 2, /*!< 2 UART0_UARTE0 */ 89 SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0_IRQn= 3, /*!< 3 SPI0_SPIM0_SPIS0_TWI0_TWIM0_TWIS0 */ 90 SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1_IRQn= 4, /*!< 4 SPI1_SPIM1_SPIS1_TWI1_TWIM1_TWIS1 */ 91 NFCT_IRQn = 5, /*!< 5 NFCT */ 92 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 93 SAADC_IRQn = 7, /*!< 7 SAADC */ 94 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 95 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 96 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 97 RTC0_IRQn = 11, /*!< 11 RTC0 */ 98 TEMP_IRQn = 12, /*!< 12 TEMP */ 99 RNG_IRQn = 13, /*!< 13 RNG */ 100 ECB_IRQn = 14, /*!< 14 ECB */ 101 AAR_CCM_IRQn = 15, /*!< 15 AAR_CCM */ 102 WDT_IRQn = 16, /*!< 16 WDT */ 103 RTC1_IRQn = 17, /*!< 17 RTC1 */ 104 QDEC_IRQn = 18, /*!< 18 QDEC */ 105 COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ 106 EGU0_SWI0_IRQn = 20, /*!< 20 EGU0_SWI0 */ 107 EGU1_SWI1_IRQn = 21, /*!< 21 EGU1_SWI1 */ 108 EGU2_SWI2_IRQn = 22, /*!< 22 EGU2_SWI2 */ 109 EGU3_SWI3_IRQn = 23, /*!< 23 EGU3_SWI3 */ 110 EGU4_SWI4_IRQn = 24, /*!< 24 EGU4_SWI4 */ 111 EGU5_SWI5_IRQn = 25, /*!< 25 EGU5_SWI5 */ 112 TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 113 TIMER4_IRQn = 27, /*!< 27 TIMER4 */ 114 PWM0_IRQn = 28, /*!< 28 PWM0 */ 115 PDM_IRQn = 29, /*!< 29 PDM */ 116 MWU_IRQn = 32, /*!< 32 MWU */ 117 PWM1_IRQn = 33, /*!< 33 PWM1 */ 118 PWM2_IRQn = 34, /*!< 34 PWM2 */ 119 SPI2_SPIM2_SPIS2_IRQn = 35, /*!< 35 SPI2_SPIM2_SPIS2 */ 120 RTC2_IRQn = 36, /*!< 36 RTC2 */ 121 I2S_IRQn = 37, /*!< 37 I2S */ 122 FPU_IRQn = 38, /*!< 38 FPU */ 123 USBD_IRQn = 39, /*!< 39 USBD */ 124 UARTE1_IRQn = 40, /*!< 40 UARTE1 */ 125 QSPI_IRQn = 41, /*!< 41 QSPI */ 126 CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ 127 PWM3_IRQn = 45, /*!< 45 PWM3 */ 128 SPIM3_IRQn = 47 /*!< 47 SPIM3 */ 129 } IRQn_Type; 130 131 132 133 /* =========================================================================================================================== */ 134 /* ================ Processor and Core Peripheral Section ================ */ 135 /* =========================================================================================================================== */ 136 137 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 138 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 139 #define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ 140 #define __DSP_PRESENT 1 /*!< DSP present or not */ 141 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 142 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 143 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 144 #define __MPU_PRESENT 1 /*!< MPU present */ 145 #define __FPU_PRESENT 1 /*!< FPU present */ 146 #define __SAUREGION_PRESENT 0 /*!< SAU region present */ 147 148 149 /** @} */ /* End of group Configuration_of_CMSIS */ 150 151 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 152 #include "system_nrf52840.h" /*!< nrf52840 System */ 153 154 #ifndef __IM /*!< Fallback for older CMSIS versions */ 155 #define __IM __I 156 #endif 157 #ifndef __OM /*!< Fallback for older CMSIS versions */ 158 #define __OM __O 159 #endif 160 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 161 #define __IOM __IO 162 #endif 163 164 165 /* =========================================================================================================================== */ 166 /* ================ Device Specific Cluster Section ================ */ 167 /* =========================================================================================================================== */ 168 169 170 /** @addtogroup Device_Peripheral_clusters 171 * @{ 172 */ 173 174 175 /** 176 * @brief FICR_INFO [INFO] (Device info) 177 */ 178 typedef struct { 179 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 180 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code, last two letters of Package Variant 181 and first two characters of Build Code, 182 encoded in ASCII. */ 183 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 184 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 185 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 186 } FICR_INFO_Type; /*!< Size = 20 (0x14) */ 187 188 189 /** 190 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 191 */ 192 typedef struct { 193 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 194 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 195 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 196 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 197 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 198 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 199 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 200 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 201 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 202 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 203 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 204 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 205 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 206 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 207 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 208 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 209 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 210 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 211 212 213 /** 214 * @brief FICR_NFC [NFC] (Unspecified) 215 */ 216 typedef struct { 217 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read 218 these values to populate NFCID1_3RD_LAST, 219 NFCID1_2ND_LAST, and NFCID1_LAST. */ 220 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read 221 these values to populate NFCID1_3RD_LAST, 222 NFCID1_2ND_LAST, and NFCID1_LAST. */ 223 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read 224 these values to populate NFCID1_3RD_LAST, 225 NFCID1_2ND_LAST, and NFCID1_LAST. */ 226 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read 227 these values to populate NFCID1_3RD_LAST, 228 NFCID1_2ND_LAST, and NFCID1_LAST. */ 229 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 230 231 232 /** 233 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 234 */ 235 typedef struct { 236 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 237 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 238 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 239 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 240 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 241 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 242 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 243 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 244 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 245 246 247 /** 248 * @brief POWER_RAM [RAM] (Unspecified) 249 */ 250 typedef struct { 251 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 252 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 253 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 254 register */ 255 __IM uint32_t RESERVED; 256 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 257 258 259 /** 260 * @brief UART_PSEL [PSEL] (Unspecified) 261 */ 262 typedef struct { 263 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 264 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 265 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 266 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 267 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 268 269 270 /** 271 * @brief UARTE_PSEL [PSEL] (Unspecified) 272 */ 273 typedef struct { 274 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 275 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 276 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 277 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 278 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 279 280 281 /** 282 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 283 */ 284 typedef struct { 285 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 286 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 287 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 288 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 289 290 291 /** 292 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 293 */ 294 typedef struct { 295 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 296 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 297 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 298 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 299 300 301 /** 302 * @brief SPI_PSEL [PSEL] (Unspecified) 303 */ 304 typedef struct { 305 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 306 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 307 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 308 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 309 310 311 /** 312 * @brief SPIM_PSEL [PSEL] (Unspecified) 313 */ 314 typedef struct { 315 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 316 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 317 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 318 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ 319 } SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ 320 321 322 /** 323 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 324 */ 325 typedef struct { 326 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 327 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 328 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 329 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 330 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 331 332 333 /** 334 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 335 */ 336 typedef struct { 337 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 338 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 339 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 340 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 341 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 342 343 344 /** 345 * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) 346 */ 347 typedef struct { 348 __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ 349 __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge 350 of SCK at the start and the end of a transaction, 351 and minimum duration CSN will stay high 352 between transactions if END-START shortcut 353 is used */ 354 } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ 355 356 357 /** 358 * @brief SPIS_PSEL [PSEL] (Unspecified) 359 */ 360 typedef struct { 361 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 362 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 363 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 364 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 365 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 366 367 368 /** 369 * @brief SPIS_RXD [RXD] (Unspecified) 370 */ 371 typedef struct { 372 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 373 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 374 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 375 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 376 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 377 378 379 /** 380 * @brief SPIS_TXD [TXD] (Unspecified) 381 */ 382 typedef struct { 383 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 384 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 385 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 386 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 387 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 388 389 390 /** 391 * @brief TWI_PSEL [PSEL] (Unspecified) 392 */ 393 typedef struct { 394 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 395 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 396 } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 397 398 399 /** 400 * @brief TWIM_PSEL [PSEL] (Unspecified) 401 */ 402 typedef struct { 403 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 404 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 405 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 406 407 408 /** 409 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 410 */ 411 typedef struct { 412 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 413 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 414 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 415 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 416 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 417 418 419 /** 420 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 421 */ 422 typedef struct { 423 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 424 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 425 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 426 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 427 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 428 429 430 /** 431 * @brief TWIS_PSEL [PSEL] (Unspecified) 432 */ 433 typedef struct { 434 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 435 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 436 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 437 438 439 /** 440 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 441 */ 442 typedef struct { 443 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 444 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 445 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 446 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 447 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 448 449 450 /** 451 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 452 */ 453 typedef struct { 454 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 455 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 456 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 457 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 458 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 459 460 461 /** 462 * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 463 */ 464 typedef struct { 465 __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ 466 } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 467 468 469 /** 470 * @brief NFCT_TXD [TXD] (Unspecified) 471 */ 472 typedef struct { 473 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 474 __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 475 } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 476 477 478 /** 479 * @brief NFCT_RXD [RXD] (Unspecified) 480 */ 481 typedef struct { 482 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 483 __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 484 } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 485 486 487 /** 488 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 489 */ 490 typedef struct { 491 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or 492 above CH[n].LIMIT.HIGH */ 493 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or 494 below CH[n].LIMIT.LOW */ 495 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 496 497 498 /** 499 * @brief SAADC_CH [CH] (Unspecified) 500 */ 501 typedef struct { 502 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 503 for CH[n] */ 504 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 505 for CH[n] */ 506 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 507 CH[n] */ 508 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 509 monitoring of a channel */ 510 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 511 512 513 /** 514 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 515 */ 516 typedef struct { 517 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 518 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written 519 to output RAM buffer */ 520 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM 521 buffer since the previous START task */ 522 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 523 524 525 /** 526 * @brief QDEC_PSEL [PSEL] (Unspecified) 527 */ 528 typedef struct { 529 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 530 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 531 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 532 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 533 534 535 /** 536 * @brief PWM_SEQ [SEQ] (Unspecified) 537 */ 538 typedef struct { 539 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 540 of this sequence */ 541 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 542 in this sequence */ 543 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 544 periods between samples loaded into compare 545 register */ 546 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 547 __IM uint32_t RESERVED[4]; 548 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 549 550 551 /** 552 * @brief PWM_PSEL [PSEL] (Unspecified) 553 */ 554 typedef struct { 555 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 556 PWM channel n */ 557 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 558 559 560 /** 561 * @brief PDM_PSEL [PSEL] (Unspecified) 562 */ 563 typedef struct { 564 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 565 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 566 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 567 568 569 /** 570 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 571 */ 572 typedef struct { 573 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 574 EasyDMA */ 575 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 576 mode */ 577 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 578 579 580 /** 581 * @brief ACL_ACL [ACL] (Unspecified) 582 */ 583 typedef struct { 584 __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region 585 to protect. The start address must be word-aligned. */ 586 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect 587 counting from address ACL[n].ADDR. Writing 588 a '0' has no effect. */ 589 __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region 590 n as defined by start address ACL[n].ADDR 591 and size ACL[n].SIZE */ 592 __IM uint32_t RESERVED; 593 } ACL_ACL_Type; /*!< Size = 16 (0x10) */ 594 595 596 /** 597 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 598 */ 599 typedef struct { 600 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 601 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 602 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 603 604 605 /** 606 * @brief PPI_CH [CH] (PPI Channel) 607 */ 608 typedef struct { 609 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ 610 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ 611 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 612 613 614 /** 615 * @brief PPI_FORK [FORK] (Fork) 616 */ 617 typedef struct { 618 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ 619 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 620 621 622 /** 623 * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.) 624 */ 625 typedef struct { 626 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n 627 detected */ 628 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n 629 detected */ 630 } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ 631 632 633 /** 634 * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.) 635 */ 636 typedef struct { 637 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral 638 region n detected */ 639 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral 640 region n detected */ 641 } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ 642 643 644 /** 645 * @brief MWU_PERREGION [PERREGION] (Unspecified) 646 */ 647 typedef struct { 648 __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt 649 in region n, write access detected while 650 corresponding subregion was enabled for 651 watching */ 652 __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt 653 in region n, read access detected while 654 corresponding subregion was enabled for 655 watching */ 656 } MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ 657 658 659 /** 660 * @brief MWU_REGION [REGION] (Unspecified) 661 */ 662 typedef struct { 663 __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region 664 n */ 665 __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */ 666 __IM uint32_t RESERVED[2]; 667 } MWU_REGION_Type; /*!< Size = 16 (0x10) */ 668 669 670 /** 671 * @brief MWU_PREGION [PREGION] (Unspecified) 672 */ 673 typedef struct { 674 __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */ 675 __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */ 676 __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */ 677 __IM uint32_t RESERVED; 678 } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ 679 680 681 /** 682 * @brief I2S_CONFIG [CONFIG] (Unspecified) 683 */ 684 typedef struct { 685 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 686 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 687 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 688 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 689 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 690 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 691 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 692 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 693 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 694 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 695 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 696 697 698 /** 699 * @brief I2S_RXD [RXD] (Unspecified) 700 */ 701 typedef struct { 702 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 703 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 704 705 706 /** 707 * @brief I2S_TXD [TXD] (Unspecified) 708 */ 709 typedef struct { 710 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 711 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 712 713 714 /** 715 * @brief I2S_RXTXD [RXTXD] (Unspecified) 716 */ 717 typedef struct { 718 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 719 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 720 721 722 /** 723 * @brief I2S_PSEL [PSEL] (Unspecified) 724 */ 725 typedef struct { 726 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 727 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 728 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 729 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 730 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 731 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 732 733 734 /** 735 * @brief USBD_HALTED [HALTED] (Unspecified) 736 */ 737 typedef struct { 738 __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. 739 Can be used as is as response to a GetStatus() 740 request to endpoint. */ 741 __IM uint32_t RESERVED; 742 __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. 743 Can be used as is as response to a GetStatus() 744 request to endpoint. */ 745 } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ 746 747 748 /** 749 * @brief USBD_SIZE [SIZE] (Unspecified) 750 */ 751 typedef struct { 752 __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received 753 last in the data stage of this OUT endpoint */ 754 __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT 755 data endpoint */ 756 } USBD_SIZE_Type; /*!< Size = 36 (0x24) */ 757 758 759 /** 760 * @brief USBD_EPIN [EPIN] (Unspecified) 761 */ 762 typedef struct { 763 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 764 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 765 to transfer */ 766 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 767 in the last transaction */ 768 __IM uint32_t RESERVED[2]; 769 } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ 770 771 772 /** 773 * @brief USBD_ISOIN [ISOIN] (Unspecified) 774 */ 775 typedef struct { 776 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 777 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 778 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 779 } USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ 780 781 782 /** 783 * @brief USBD_EPOUT [EPOUT] (Unspecified) 784 */ 785 typedef struct { 786 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 787 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 788 to transfer */ 789 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 790 in the last transaction */ 791 __IM uint32_t RESERVED[2]; 792 } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ 793 794 795 /** 796 * @brief USBD_ISOOUT [ISOOUT] (Unspecified) 797 */ 798 typedef struct { 799 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 800 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 801 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 802 } USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ 803 804 805 /** 806 * @brief QSPI_READ [READ] (Unspecified) 807 */ 808 typedef struct { 809 __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ 810 __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ 811 __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ 812 } QSPI_READ_Type; /*!< Size = 12 (0xc) */ 813 814 815 /** 816 * @brief QSPI_WRITE [WRITE] (Unspecified) 817 */ 818 typedef struct { 819 __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ 820 __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ 821 __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ 822 } QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ 823 824 825 /** 826 * @brief QSPI_ERASE [ERASE] (Unspecified) 827 */ 828 typedef struct { 829 __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ 830 __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ 831 } QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ 832 833 834 /** 835 * @brief QSPI_PSEL [PSEL] (Unspecified) 836 */ 837 typedef struct { 838 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ 839 __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ 840 __IM uint32_t RESERVED; 841 __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ 842 __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ 843 __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ 844 __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ 845 } QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ 846 847 848 /** @} */ /* End of group Device_Peripheral_clusters */ 849 850 851 /* =========================================================================================================================== */ 852 /* ================ Device Specific Peripheral Section ================ */ 853 /* =========================================================================================================================== */ 854 855 856 /** @addtogroup Device_Peripheral_peripherals 857 * @{ 858 */ 859 860 861 862 /* =========================================================================================================================== */ 863 /* ================ FICR ================ */ 864 /* =========================================================================================================================== */ 865 866 867 /** 868 * @brief Factory information configuration registers (FICR) 869 */ 870 871 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 872 __IM uint32_t RESERVED[4]; 873 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 874 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 875 __IM uint32_t RESERVED1[18]; 876 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ 877 __IM uint32_t RESERVED2[6]; 878 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word 879 n */ 880 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ 881 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 882 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ 883 __IM uint32_t RESERVED3[21]; 884 __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 885 __IM uint32_t RESERVED4[143]; 886 __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature 887 n */ 888 __IM uint32_t RESERVED5[42]; 889 __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 890 coefficients */ 891 __IM uint32_t RESERVED6[2]; 892 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 893 __IM uint32_t RESERVED7[488]; 894 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 895 } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 896 897 898 899 /* =========================================================================================================================== */ 900 /* ================ UICR ================ */ 901 /* =========================================================================================================================== */ 902 903 904 /** 905 * @brief User information configuration registers (UICR) 906 */ 907 908 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 909 __IM uint32_t RESERVED[5]; 910 __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware 911 design */ 912 __IM uint32_t RESERVED1[2]; 913 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware 914 design */ 915 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ 916 __IM uint32_t RESERVED2[64]; 917 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET 918 function (see POWER chapter for details) */ 919 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 920 __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: 921 NFC antenna or GPIO */ 922 __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ 923 __IM uint32_t RESERVED3[60]; 924 __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The 925 maximum output voltage from this stage is 926 given as VDDH - V_VDDH-VDD. */ 927 } NRF_UICR_Type; /*!< Size = 776 (0x308) */ 928 929 930 931 /* =========================================================================================================================== */ 932 /* ================ APPROTECT ================ */ 933 /* =========================================================================================================================== */ 934 935 936 /** 937 * @brief Access Port Protection (APPROTECT) 938 */ 939 940 typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ 941 __IM uint32_t RESERVED[340]; 942 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until 943 next reset. */ 944 __IM uint32_t RESERVED1; 945 __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ 946 } NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ 947 948 949 950 /* =========================================================================================================================== */ 951 /* ================ CLOCK ================ */ 952 /* =========================================================================================================================== */ 953 954 955 /** 956 * @brief Clock control (CLOCK) 957 */ 958 959 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 960 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ 961 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ 962 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ 963 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ 964 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ 965 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 966 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 967 __IM uint32_t RESERVED[57]; 968 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ 969 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 970 __IM uint32_t RESERVED1; 971 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ 972 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 973 __IM uint32_t RESERVED2[5]; 974 __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready 975 to process new tasks */ 976 __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready 977 to process new tasks */ 978 __IM uint32_t RESERVED3[117]; 979 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 980 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 981 __IM uint32_t RESERVED4[63]; 982 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 983 triggered */ 984 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 985 __IM uint32_t RESERVED5; 986 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 987 triggered */ 988 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 989 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 990 task was triggered */ 991 __IM uint32_t RESERVED6[62]; 992 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 993 __IM uint32_t RESERVED7[3]; 994 __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering 995 the TASKS_HFCLKSTART task. */ 996 __IM uint32_t RESERVED8[3]; 997 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 998 __IM uint32_t RESERVED9[8]; 999 __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ 1000 __IM uint32_t RESERVED10[21]; 1001 __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */ 1002 } NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */ 1003 1004 1005 1006 /* =========================================================================================================================== */ 1007 /* ================ POWER ================ */ 1008 /* =========================================================================================================================== */ 1009 1010 1011 /** 1012 * @brief Power control (POWER) 1013 */ 1014 1015 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 1016 __IM uint32_t RESERVED[30]; 1017 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 1018 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ 1019 __IM uint32_t RESERVED1[34]; 1020 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 1021 __IM uint32_t RESERVED2[2]; 1022 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1023 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1024 __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ 1025 __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ 1026 __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ 1027 __IM uint32_t RESERVED3[119]; 1028 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1029 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1030 __IM uint32_t RESERVED4[61]; 1031 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1032 __IM uint32_t RESERVED5[9]; 1033 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 1034 __IM uint32_t RESERVED6[3]; 1035 __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ 1036 __IM uint32_t RESERVED7[49]; 1037 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 1038 __IM uint32_t RESERVED8[3]; 1039 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 1040 __IM uint32_t RESERVED9[2]; 1041 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 1042 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 1043 __IM uint32_t RESERVED10[21]; 1044 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */ 1045 __IM uint32_t RESERVED11; 1046 __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage */ 1047 __IM uint32_t RESERVED12[47]; 1048 __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ 1049 __IM uint32_t RESERVED13[175]; 1050 __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ 1051 } NRF_POWER_Type; /*!< Size = 2448 (0x990) */ 1052 1053 1054 1055 /* =========================================================================================================================== */ 1056 /* ================ P0 ================ */ 1057 /* =========================================================================================================================== */ 1058 1059 1060 /** 1061 * @brief GPIO Port 0 (P0) 1062 */ 1063 1064 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 1065 __IM uint32_t RESERVED[321]; 1066 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 1067 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 1068 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 1069 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 1070 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 1071 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 1072 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 1073 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 1074 have met the criteria set in the PIN_CNF[n].SENSE 1075 registers */ 1076 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior 1077 and LDETECT mode */ 1078 __IM uint32_t RESERVED1[118]; 1079 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO 1080 pins */ 1081 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 1082 1083 1084 1085 /* =========================================================================================================================== */ 1086 /* ================ RADIO ================ */ 1087 /* =========================================================================================================================== */ 1088 1089 1090 /** 1091 * @brief 2.4 GHz radio (RADIO) 1092 */ 1093 1094 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 1095 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 1096 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 1097 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 1098 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 1099 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 1100 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 1101 the receive signal strength */ 1102 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 1103 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 1104 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 1105 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 1106 802.15.4 mode */ 1107 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 1108 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 1109 802.15.4 mode */ 1110 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 1111 __IM uint32_t RESERVED[51]; 1112 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 1113 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 1114 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 1115 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 1116 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 1117 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 1118 packet */ 1119 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 1120 received packet */ 1121 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 1122 __IM uint32_t RESERVED1[2]; 1123 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 1124 __IM uint32_t RESERVED2; 1125 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 1126 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 1127 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 1128 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 1129 ED sample is ready for readout from the 1130 RADIO.EDSAMPLE register. */ 1131 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 1132 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 1133 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 1134 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 1135 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 1136 from Ble_LR125Kbit to Ble_LR500Kbit. */ 1137 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 1138 TX path */ 1139 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 1140 RX path */ 1141 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 1142 __IM uint32_t RESERVED3[2]; 1143 __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator. */ 1144 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and 1145 Ieee802154_250Kbit modes when last bit is 1146 sent on air. */ 1147 __IM uint32_t RESERVED4[36]; 1148 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1149 __IM uint32_t RESERVED5[64]; 1150 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1151 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1152 __IM uint32_t RESERVED6[61]; 1153 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 1154 __IM uint32_t RESERVED7; 1155 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 1156 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 1157 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 1158 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 1159 __IM uint32_t RESERVED8[59]; 1160 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 1161 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 1162 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 1163 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 1164 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 1165 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 1166 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 1167 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 1168 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 1169 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 1170 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 1171 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 1172 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 1173 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 1174 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 1175 __IM uint32_t RESERVED9; 1176 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 1177 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 1178 __IM uint32_t RESERVED10; 1179 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 1180 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 1181 __IM uint32_t RESERVED11[2]; 1182 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 1183 __IM uint32_t RESERVED12[39]; 1184 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 1185 n */ 1186 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 1187 n */ 1188 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 1189 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 1190 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 1191 __IM uint32_t RESERVED13; 1192 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 1193 __IM uint32_t RESERVED14[3]; 1194 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 1195 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 1196 __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 1197 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 1198 __IM uint32_t RESERVED15[611]; 1199 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 1200 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 1201 1202 1203 1204 /* =========================================================================================================================== */ 1205 /* ================ UART0 ================ */ 1206 /* =========================================================================================================================== */ 1207 1208 1209 /** 1210 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 1211 */ 1212 1213 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 1214 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1215 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1216 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1217 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1218 __IM uint32_t RESERVED[3]; 1219 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 1220 __IM uint32_t RESERVED1[56]; 1221 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1222 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1223 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 1224 __IM uint32_t RESERVED2[4]; 1225 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1226 __IM uint32_t RESERVED3; 1227 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1228 __IM uint32_t RESERVED4[7]; 1229 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1230 __IM uint32_t RESERVED5[46]; 1231 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1232 __IM uint32_t RESERVED6[64]; 1233 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1234 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1235 __IM uint32_t RESERVED7[93]; 1236 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1237 __IM uint32_t RESERVED8[31]; 1238 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1239 __IM uint32_t RESERVED9; 1240 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1241 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register. Register is cleared on read and 1242 the double buffered byte will be moved to 1243 RXD if it exists. */ 1244 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1245 __IM uint32_t RESERVED10; 1246 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1247 selected. */ 1248 __IM uint32_t RESERVED11[17]; 1249 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1250 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 1251 1252 1253 1254 /* =========================================================================================================================== */ 1255 /* ================ UARTE0 ================ */ 1256 /* =========================================================================================================================== */ 1257 1258 1259 /** 1260 * @brief UART with EasyDMA 0 (UARTE0) 1261 */ 1262 1263 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 1264 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1265 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1266 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1267 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1268 __IM uint32_t RESERVED[7]; 1269 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1270 __IM uint32_t RESERVED1[52]; 1271 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1272 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1273 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1274 transferred to Data RAM) */ 1275 __IM uint32_t RESERVED2; 1276 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1277 __IM uint32_t RESERVED3[2]; 1278 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1279 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1280 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1281 __IM uint32_t RESERVED4[7]; 1282 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1283 __IM uint32_t RESERVED5; 1284 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1285 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1286 __IM uint32_t RESERVED6; 1287 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1288 __IM uint32_t RESERVED7[41]; 1289 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1290 __IM uint32_t RESERVED8[63]; 1291 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1292 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1293 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1294 __IM uint32_t RESERVED9[93]; 1295 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one 1296 to clear. */ 1297 __IM uint32_t RESERVED10[31]; 1298 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1299 __IM uint32_t RESERVED11; 1300 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1301 __IM uint32_t RESERVED12[3]; 1302 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1303 selected. */ 1304 __IM uint32_t RESERVED13[3]; 1305 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1306 __IM uint32_t RESERVED14; 1307 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1308 __IM uint32_t RESERVED15[7]; 1309 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1310 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1311 1312 1313 1314 /* =========================================================================================================================== */ 1315 /* ================ SPI0 ================ */ 1316 /* =========================================================================================================================== */ 1317 1318 1319 /** 1320 * @brief Serial Peripheral Interface 0 (SPI0) 1321 */ 1322 1323 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1324 __IM uint32_t RESERVED[66]; 1325 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1326 __IM uint32_t RESERVED1[126]; 1327 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1328 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1329 __IM uint32_t RESERVED2[125]; 1330 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1331 __IM uint32_t RESERVED3; 1332 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1333 __IM uint32_t RESERVED4; 1334 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register. Register is cleared on read and 1335 the buffer pointer will be modified if read. */ 1336 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1337 __IM uint32_t RESERVED5; 1338 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1339 source selected. */ 1340 __IM uint32_t RESERVED6[11]; 1341 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1342 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1343 1344 1345 1346 /* =========================================================================================================================== */ 1347 /* ================ SPIM0 ================ */ 1348 /* =========================================================================================================================== */ 1349 1350 1351 /** 1352 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1353 */ 1354 1355 typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1356 __IM uint32_t RESERVED[4]; 1357 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1358 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1359 __IM uint32_t RESERVED1; 1360 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1361 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1362 __IM uint32_t RESERVED2[56]; 1363 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1364 __IM uint32_t RESERVED3[2]; 1365 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1366 __IM uint32_t RESERVED4; 1367 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1368 __IM uint32_t RESERVED5; 1369 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1370 __IM uint32_t RESERVED6[10]; 1371 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1372 __IM uint32_t RESERVED7[44]; 1373 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1374 __IM uint32_t RESERVED8[64]; 1375 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1376 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1377 __IM uint32_t RESERVED9[61]; 1378 __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields 1379 in this register are set to STALL by hardware 1380 whenever a stall occurs and can be cleared 1381 (set to NOSTALL) by the CPU. */ 1382 __IM uint32_t RESERVED10[63]; 1383 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1384 __IM uint32_t RESERVED11; 1385 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1386 __IM uint32_t RESERVED12[3]; 1387 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1388 source selected. */ 1389 __IM uint32_t RESERVED13[3]; 1390 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1391 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1392 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1393 __IM uint32_t RESERVED14[2]; 1394 __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ 1395 __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ 1396 __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ 1397 __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ 1398 __IM uint32_t RESERVED15[19]; 1399 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1400 been transmitted in the case when RXD.MAXCNT 1401 is greater than TXD.MAXCNT */ 1402 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1403 1404 1405 1406 /* =========================================================================================================================== */ 1407 /* ================ SPIS0 ================ */ 1408 /* =========================================================================================================================== */ 1409 1410 1411 /** 1412 * @brief SPI Slave 0 (SPIS0) 1413 */ 1414 1415 typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1416 __IM uint32_t RESERVED[9]; 1417 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1418 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1419 to acquire it */ 1420 __IM uint32_t RESERVED1[54]; 1421 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1422 __IM uint32_t RESERVED2[2]; 1423 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1424 __IM uint32_t RESERVED3[5]; 1425 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1426 __IM uint32_t RESERVED4[53]; 1427 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1428 __IM uint32_t RESERVED5[64]; 1429 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1430 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1431 __IM uint32_t RESERVED6[61]; 1432 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1433 __IM uint32_t RESERVED7[15]; 1434 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1435 __IM uint32_t RESERVED8[47]; 1436 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1437 __IM uint32_t RESERVED9; 1438 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1439 __IM uint32_t RESERVED10[7]; 1440 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1441 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1442 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1443 __IM uint32_t RESERVED11; 1444 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1445 of an ignored transaction. */ 1446 __IM uint32_t RESERVED12[24]; 1447 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1448 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1449 1450 1451 1452 /* =========================================================================================================================== */ 1453 /* ================ TWI0 ================ */ 1454 /* =========================================================================================================================== */ 1455 1456 1457 /** 1458 * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1459 */ 1460 1461 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1462 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1463 __IM uint32_t RESERVED; 1464 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1465 __IM uint32_t RESERVED1[2]; 1466 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1467 __IM uint32_t RESERVED2; 1468 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1469 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1470 __IM uint32_t RESERVED3[56]; 1471 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1472 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1473 __IM uint32_t RESERVED4[4]; 1474 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1475 __IM uint32_t RESERVED5; 1476 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1477 __IM uint32_t RESERVED6[4]; 1478 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1479 that is sent or received */ 1480 __IM uint32_t RESERVED7[3]; 1481 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1482 __IM uint32_t RESERVED8[45]; 1483 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1484 __IM uint32_t RESERVED9[64]; 1485 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1486 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1487 __IM uint32_t RESERVED10[110]; 1488 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1489 __IM uint32_t RESERVED11[14]; 1490 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1491 __IM uint32_t RESERVED12; 1492 __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1493 __IM uint32_t RESERVED13[2]; 1494 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register. Register is cleared on read and 1495 the buffer pointer will be modified if read. */ 1496 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1497 __IM uint32_t RESERVED14; 1498 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1499 source selected. */ 1500 __IM uint32_t RESERVED15[24]; 1501 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1502 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1503 1504 1505 1506 /* =========================================================================================================================== */ 1507 /* ================ TWIM0 ================ */ 1508 /* =========================================================================================================================== */ 1509 1510 1511 /** 1512 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1513 */ 1514 1515 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1516 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1517 __IM uint32_t RESERVED; 1518 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1519 __IM uint32_t RESERVED1[2]; 1520 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1521 TWI master is not suspended. */ 1522 __IM uint32_t RESERVED2; 1523 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1524 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1525 __IM uint32_t RESERVED3[56]; 1526 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1527 __IM uint32_t RESERVED4[7]; 1528 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1529 __IM uint32_t RESERVED5[8]; 1530 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1531 now suspended. */ 1532 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1533 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1534 __IM uint32_t RESERVED6[2]; 1535 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1536 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1537 byte */ 1538 __IM uint32_t RESERVED7[39]; 1539 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1540 __IM uint32_t RESERVED8[63]; 1541 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1542 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1543 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1544 __IM uint32_t RESERVED9[110]; 1545 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1546 __IM uint32_t RESERVED10[14]; 1547 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1548 __IM uint32_t RESERVED11; 1549 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1550 __IM uint32_t RESERVED12[5]; 1551 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1552 source selected. */ 1553 __IM uint32_t RESERVED13[3]; 1554 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1555 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1556 __IM uint32_t RESERVED14[13]; 1557 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1558 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1559 1560 1561 1562 /* =========================================================================================================================== */ 1563 /* ================ TWIS0 ================ */ 1564 /* =========================================================================================================================== */ 1565 1566 1567 /** 1568 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1569 */ 1570 1571 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1572 __IM uint32_t RESERVED[5]; 1573 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1574 __IM uint32_t RESERVED1; 1575 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1576 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1577 __IM uint32_t RESERVED2[3]; 1578 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1579 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1580 __IM uint32_t RESERVED3[51]; 1581 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1582 __IM uint32_t RESERVED4[7]; 1583 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1584 __IM uint32_t RESERVED5[9]; 1585 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1586 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1587 __IM uint32_t RESERVED6[4]; 1588 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1589 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1590 __IM uint32_t RESERVED7[37]; 1591 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1592 __IM uint32_t RESERVED8[63]; 1593 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1594 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1595 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1596 __IM uint32_t RESERVED9[113]; 1597 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1598 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1599 a match */ 1600 __IM uint32_t RESERVED10[10]; 1601 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1602 __IM uint32_t RESERVED11; 1603 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1604 __IM uint32_t RESERVED12[9]; 1605 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1606 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1607 __IM uint32_t RESERVED13[13]; 1608 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1609 __IM uint32_t RESERVED14; 1610 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1611 mechanism */ 1612 __IM uint32_t RESERVED15[10]; 1613 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1614 of an over-read of the transmit buffer. */ 1615 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1616 1617 1618 1619 /* =========================================================================================================================== */ 1620 /* ================ NFCT ================ */ 1621 /* =========================================================================================================================== */ 1622 1623 1624 /** 1625 * @brief NFC-A compatible radio (NFCT) 1626 */ 1627 1628 typedef struct { /*!< (@ 0x40005000) NFCT Structure */ 1629 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing 1630 frames, change state to activated */ 1631 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ 1632 __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 1633 sense mode */ 1634 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change 1635 state to transmit */ 1636 __IM uint32_t RESERVED[3]; 1637 __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 1638 __IM uint32_t RESERVED1; 1639 __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 1640 __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 1641 __IM uint32_t RESERVED2[53]; 1642 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send 1643 frames */ 1644 __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 1645 __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 1646 __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 1647 frame */ 1648 __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 1649 symbol of a frame */ 1650 __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 1651 frame */ 1652 __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) 1653 and transferred to RAM, and EasyDMA has 1654 ended accessing the RX buffer */ 1655 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 1656 contains details on the source of the error. */ 1657 __IM uint32_t RESERVED3[2]; 1658 __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 1659 register contains details on the source 1660 of the error. */ 1661 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 1662 in Data RAM full. */ 1663 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 1664 has ended accessing the TX buffer */ 1665 __IM uint32_t RESERVED4; 1666 __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 1667 __IM uint32_t RESERVED5[3]; 1668 __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ 1669 __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ 1670 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 1671 __IM uint32_t RESERVED6[43]; 1672 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1673 __IM uint32_t RESERVED7[63]; 1674 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1675 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1676 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1677 __IM uint32_t RESERVED8[62]; 1678 __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 1679 __IM uint32_t RESERVED9; 1680 __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 1681 __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ 1682 __IM uint32_t RESERVED10[3]; 1683 __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ 1684 __IM uint32_t RESERVED11[6]; 1685 __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 1686 __IM uint32_t RESERVED12[49]; 1687 __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 1688 __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 1689 __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 1690 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 1691 Data RAM */ 1692 __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD 1693 data storage each */ 1694 __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 1695 __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 1696 __IM uint32_t RESERVED13[26]; 1697 __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 1698 __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 1699 __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 1700 __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. 1701 This setting must be done before the NFCT 1702 peripheral is activated. */ 1703 __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 1704 __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 1705 } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 1706 1707 1708 1709 /* =========================================================================================================================== */ 1710 /* ================ GPIOTE ================ */ 1711 /* =========================================================================================================================== */ 1712 1713 1714 /** 1715 * @brief GPIO Tasks and Events (GPIOTE) 1716 */ 1717 1718 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1719 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1720 specified in CONFIG[n].PSEL. Action on pin 1721 is configured in CONFIG[n].POLARITY. */ 1722 __IM uint32_t RESERVED[4]; 1723 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1724 specified in CONFIG[n].PSEL. Action on pin 1725 is to set it high. */ 1726 __IM uint32_t RESERVED1[4]; 1727 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1728 specified in CONFIG[n].PSEL. Action on pin 1729 is to set it low. */ 1730 __IM uint32_t RESERVED2[32]; 1731 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1732 pin specified in CONFIG[n].PSEL */ 1733 __IM uint32_t RESERVED3[23]; 1734 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1735 with SENSE mechanism enabled */ 1736 __IM uint32_t RESERVED4[97]; 1737 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1738 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1739 __IM uint32_t RESERVED5[129]; 1740 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1741 SET[n], and CLR[n] tasks and IN[n] event */ 1742 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1743 1744 1745 1746 /* =========================================================================================================================== */ 1747 /* ================ SAADC ================ */ 1748 /* =========================================================================================================================== */ 1749 1750 1751 /** 1752 * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) 1753 */ 1754 1755 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1756 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer 1757 in RAM */ 1758 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ 1759 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ 1760 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1761 __IM uint32_t RESERVED[60]; 1762 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ 1763 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ 1764 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1765 on the configuration, multiple conversions 1766 might be needed for a result to be transferred 1767 to RAM. */ 1768 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ 1769 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1770 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ 1771 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1772 __IM uint32_t RESERVED1[106]; 1773 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1774 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1775 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1776 __IM uint32_t RESERVED2[61]; 1777 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1778 __IM uint32_t RESERVED3[63]; 1779 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ 1780 __IM uint32_t RESERVED4[3]; 1781 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1782 __IM uint32_t RESERVED5[24]; 1783 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1784 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is 1785 applied before averaging, thus for high 1786 OVERSAMPLE a higher RESOLUTION should be 1787 used. */ 1788 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1789 __IM uint32_t RESERVED6[12]; 1790 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1791 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1792 1793 1794 1795 /* =========================================================================================================================== */ 1796 /* ================ TIMER0 ================ */ 1797 /* =========================================================================================================================== */ 1798 1799 1800 /** 1801 * @brief Timer/Counter 0 (TIMER0) 1802 */ 1803 1804 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1805 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1806 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1807 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1808 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1809 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1810 __IM uint32_t RESERVED[11]; 1811 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1812 CC[n] register */ 1813 __IM uint32_t RESERVED1[58]; 1814 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1815 match */ 1816 __IM uint32_t RESERVED2[42]; 1817 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1818 __IM uint32_t RESERVED3[64]; 1819 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1820 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1821 __IM uint32_t RESERVED4[126]; 1822 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1823 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1824 __IM uint32_t RESERVED5; 1825 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1826 __IM uint32_t RESERVED6[11]; 1827 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1828 n */ 1829 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1830 1831 1832 1833 /* =========================================================================================================================== */ 1834 /* ================ RTC0 ================ */ 1835 /* =========================================================================================================================== */ 1836 1837 1838 /** 1839 * @brief Real time counter 0 (RTC0) 1840 */ 1841 1842 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1843 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1844 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1845 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1846 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1847 __IM uint32_t RESERVED[60]; 1848 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1849 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1850 __IM uint32_t RESERVED1[14]; 1851 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1852 match */ 1853 __IM uint32_t RESERVED2[109]; 1854 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1855 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1856 __IM uint32_t RESERVED3[13]; 1857 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1858 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1859 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1860 __IM uint32_t RESERVED4[110]; 1861 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1862 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 1863 Must be written when RTC is stopped. */ 1864 __IM uint32_t RESERVED5[13]; 1865 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1866 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1867 1868 1869 1870 /* =========================================================================================================================== */ 1871 /* ================ TEMP ================ */ 1872 /* =========================================================================================================================== */ 1873 1874 1875 /** 1876 * @brief Temperature Sensor (TEMP) 1877 */ 1878 1879 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1880 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1881 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1882 __IM uint32_t RESERVED[62]; 1883 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1884 __IM uint32_t RESERVED1[128]; 1885 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1886 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1887 __IM uint32_t RESERVED2[127]; 1888 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1889 __IM uint32_t RESERVED3[5]; 1890 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ 1891 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ 1892 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ 1893 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ 1894 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ 1895 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ 1896 __IM uint32_t RESERVED4[2]; 1897 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ 1898 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ 1899 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ 1900 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ 1901 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ 1902 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ 1903 __IM uint32_t RESERVED5[2]; 1904 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ 1905 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ 1906 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ 1907 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ 1908 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ 1909 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1910 1911 1912 1913 /* =========================================================================================================================== */ 1914 /* ================ RNG ================ */ 1915 /* =========================================================================================================================== */ 1916 1917 1918 /** 1919 * @brief Random Number Generator (RNG) 1920 */ 1921 1922 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1923 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1924 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1925 __IM uint32_t RESERVED[62]; 1926 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1927 written to the VALUE register */ 1928 __IM uint32_t RESERVED1[63]; 1929 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1930 __IM uint32_t RESERVED2[64]; 1931 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1932 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1933 __IM uint32_t RESERVED3[126]; 1934 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1935 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1936 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1937 1938 1939 1940 /* =========================================================================================================================== */ 1941 /* ================ ECB ================ */ 1942 /* =========================================================================================================================== */ 1943 1944 1945 /** 1946 * @brief AES ECB Mode Encryption (ECB) 1947 */ 1948 1949 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1950 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1951 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1952 __IM uint32_t RESERVED[62]; 1953 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1954 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1955 task or due to an error */ 1956 __IM uint32_t RESERVED1[127]; 1957 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1958 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1959 __IM uint32_t RESERVED2[126]; 1960 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1961 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1962 1963 1964 1965 /* =========================================================================================================================== */ 1966 /* ================ AAR ================ */ 1967 /* =========================================================================================================================== */ 1968 1969 1970 /** 1971 * @brief Accelerated Address Resolver (AAR) 1972 */ 1973 1974 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1975 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1976 in the IRK data structure */ 1977 __IM uint32_t RESERVED; 1978 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1979 __IM uint32_t RESERVED1[61]; 1980 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1981 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1982 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1983 __IM uint32_t RESERVED2[126]; 1984 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1985 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1986 __IM uint32_t RESERVED3[61]; 1987 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1988 __IM uint32_t RESERVED4[63]; 1989 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1990 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1991 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1992 __IM uint32_t RESERVED5; 1993 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1994 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1995 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1996 1997 1998 1999 /* =========================================================================================================================== */ 2000 /* ================ CCM ================ */ 2001 /* =========================================================================================================================== */ 2002 2003 2004 /** 2005 * @brief AES CCM mode encryption (CCM) 2006 */ 2007 2008 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 2009 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 2010 will stop by itself when completed. */ 2011 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 2012 stop by itself when completed. */ 2013 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 2014 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 2015 the contents of the RATEOVERRIDE register 2016 for any ongoing encryption/decryption */ 2017 __IM uint32_t RESERVED[60]; 2018 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 2019 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 2020 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 2021 __IM uint32_t RESERVED1[61]; 2022 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2023 __IM uint32_t RESERVED2[64]; 2024 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2025 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2026 __IM uint32_t RESERVED3[61]; 2027 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 2028 __IM uint32_t RESERVED4[63]; 2029 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 2030 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 2031 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key 2032 and the NONCE vector */ 2033 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 2034 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 2035 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 2036 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 2037 = Extended */ 2038 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 2039 } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 2040 2041 2042 2043 /* =========================================================================================================================== */ 2044 /* ================ WDT ================ */ 2045 /* =========================================================================================================================== */ 2046 2047 2048 /** 2049 * @brief Watchdog Timer (WDT) 2050 */ 2051 2052 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 2053 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 2054 __IM uint32_t RESERVED[63]; 2055 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 2056 __IM uint32_t RESERVED1[128]; 2057 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2058 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2059 __IM uint32_t RESERVED2[61]; 2060 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 2061 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 2062 __IM uint32_t RESERVED3[63]; 2063 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 2064 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 2065 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 2066 __IM uint32_t RESERVED4[60]; 2067 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 2068 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 2069 2070 2071 2072 /* =========================================================================================================================== */ 2073 /* ================ QDEC ================ */ 2074 /* =========================================================================================================================== */ 2075 2076 2077 /** 2078 * @brief Quadrature Decoder (QDEC) 2079 */ 2080 2081 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 2082 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 2083 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 2084 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 2085 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 2086 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 2087 __IM uint32_t RESERVED[59]; 2088 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 2089 written to the SAMPLE register */ 2090 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 2091 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 2092 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 2093 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 2094 __IM uint32_t RESERVED1[59]; 2095 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2096 __IM uint32_t RESERVED2[64]; 2097 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2098 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2099 __IM uint32_t RESERVED3[125]; 2100 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 2101 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 2102 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 2103 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 2104 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 2105 and DBLRDY events can be generated */ 2106 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 2107 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 2108 READCLRACC or RDCLRACC task */ 2109 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 2110 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 2111 __IM uint32_t RESERVED4[5]; 2112 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 2113 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 2114 double transitions */ 2115 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 2116 or RDCLRDBL task */ 2117 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 2118 2119 2120 2121 /* =========================================================================================================================== */ 2122 /* ================ COMP ================ */ 2123 /* =========================================================================================================================== */ 2124 2125 2126 /** 2127 * @brief Comparator (COMP) 2128 */ 2129 2130 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 2131 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2132 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2133 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2134 __IM uint32_t RESERVED[61]; 2135 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 2136 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2137 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2138 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2139 __IM uint32_t RESERVED1[60]; 2140 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2141 __IM uint32_t RESERVED2[63]; 2142 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2143 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2144 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2145 __IM uint32_t RESERVED3[61]; 2146 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2147 __IM uint32_t RESERVED4[63]; 2148 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 2149 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 2150 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 2151 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2152 __IM uint32_t RESERVED5[8]; 2153 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 2154 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 2155 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2156 } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 2157 2158 2159 2160 /* =========================================================================================================================== */ 2161 /* ================ LPCOMP ================ */ 2162 /* =========================================================================================================================== */ 2163 2164 2165 /** 2166 * @brief Low-power comparator (LPCOMP) 2167 */ 2168 2169 typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 2170 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2171 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2172 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2173 __IM uint32_t RESERVED[61]; 2174 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 2175 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2176 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2177 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2178 __IM uint32_t RESERVED1[60]; 2179 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2180 __IM uint32_t RESERVED2[64]; 2181 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2182 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2183 __IM uint32_t RESERVED3[61]; 2184 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2185 __IM uint32_t RESERVED4[63]; 2186 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 2187 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 2188 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 2189 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2190 __IM uint32_t RESERVED5[4]; 2191 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 2192 __IM uint32_t RESERVED6[5]; 2193 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2194 } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 2195 2196 2197 2198 /* =========================================================================================================================== */ 2199 /* ================ EGU0 ================ */ 2200 /* =========================================================================================================================== */ 2201 2202 2203 /** 2204 * @brief Event generator unit 0 (EGU0) 2205 */ 2206 2207 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 2208 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 2209 the corresponding TRIGGERED[n] event */ 2210 __IM uint32_t RESERVED[48]; 2211 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 2212 by triggering the corresponding TRIGGER[n] 2213 task */ 2214 __IM uint32_t RESERVED1[112]; 2215 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2216 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2217 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2218 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 2219 2220 2221 2222 /* =========================================================================================================================== */ 2223 /* ================ SWI0 ================ */ 2224 /* =========================================================================================================================== */ 2225 2226 2227 /** 2228 * @brief Software interrupt 0 (SWI0) 2229 */ 2230 2231 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 2232 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2233 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 2234 2235 2236 2237 /* =========================================================================================================================== */ 2238 /* ================ PWM0 ================ */ 2239 /* =========================================================================================================================== */ 2240 2241 2242 /** 2243 * @brief Pulse width modulation unit 0 (PWM0) 2244 */ 2245 2246 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 2247 __IM uint32_t RESERVED; 2248 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2249 the end of current PWM period, and stops 2250 sequence playback */ 2251 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 2252 on all enabled channels from sequence n, 2253 and starts playing that sequence at the 2254 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2255 Causes PWM generation to start if not running. */ 2256 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2257 all enabled channels if DECODER.MODE=NextStep. 2258 Does not cause PWM generation to start if 2259 not running. */ 2260 __IM uint32_t RESERVED1[60]; 2261 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2262 are no longer generated */ 2263 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 2264 on sequence n */ 2265 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 2266 sequence n, when last value from RAM has 2267 been applied to wave counter */ 2268 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2269 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2270 of times defined in LOOP.CNT */ 2271 __IM uint32_t RESERVED2[56]; 2272 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2273 __IM uint32_t RESERVED3[63]; 2274 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2275 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2276 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2277 __IM uint32_t RESERVED4[125]; 2278 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2279 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2280 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2281 counts */ 2282 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2283 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2284 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 2285 __IM uint32_t RESERVED5[2]; 2286 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2287 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2288 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2289 2290 2291 2292 /* =========================================================================================================================== */ 2293 /* ================ PDM ================ */ 2294 /* =========================================================================================================================== */ 2295 2296 2297 /** 2298 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 2299 */ 2300 2301 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 2302 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2303 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2304 __IM uint32_t RESERVED[62]; 2305 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2306 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2307 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2308 by SAMPLE.MAXCNT (or the last sample after 2309 a STOP task has been received) to Data RAM */ 2310 __IM uint32_t RESERVED1[125]; 2311 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2312 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2313 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2314 __IM uint32_t RESERVED2[125]; 2315 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2316 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2317 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2318 signals */ 2319 __IM uint32_t RESERVED3[3]; 2320 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2321 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2322 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 2323 sample rate. Change PDMCLKCTRL accordingly. */ 2324 __IM uint32_t RESERVED4[7]; 2325 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2326 __IM uint32_t RESERVED5[6]; 2327 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2328 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2329 2330 2331 2332 /* =========================================================================================================================== */ 2333 /* ================ ACL ================ */ 2334 /* =========================================================================================================================== */ 2335 2336 2337 /** 2338 * @brief Access control lists (ACL) 2339 */ 2340 2341 typedef struct { /*!< (@ 0x4001E000) ACL Structure */ 2342 __IM uint32_t RESERVED[512]; 2343 __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ 2344 } NRF_ACL_Type; /*!< Size = 2176 (0x880) */ 2345 2346 2347 2348 /* =========================================================================================================================== */ 2349 /* ================ NVMC ================ */ 2350 /* =========================================================================================================================== */ 2351 2352 2353 /** 2354 * @brief Non Volatile Memory Controller (NVMC) 2355 */ 2356 2357 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 2358 __IM uint32_t RESERVED[256]; 2359 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2360 __IM uint32_t RESERVED1; 2361 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 2362 __IM uint32_t RESERVED2[62]; 2363 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2364 __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 2365 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2366 __IM uint32_t RESERVED3; 2367 __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 2368 registers */ 2369 __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 2370 area */ 2371 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 2372 __IM uint32_t RESERVED4[8]; 2373 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 2374 __IM uint32_t RESERVED5; 2375 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 2376 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 2377 } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 2378 2379 2380 2381 /* =========================================================================================================================== */ 2382 /* ================ PPI ================ */ 2383 /* =========================================================================================================================== */ 2384 2385 2386 /** 2387 * @brief Programmable Peripheral Interconnect (PPI) 2388 */ 2389 2390 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 2391 __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2392 __IM uint32_t RESERVED[308]; 2393 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2394 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2395 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2396 __IM uint32_t RESERVED1; 2397 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 2398 __IM uint32_t RESERVED2[148]; 2399 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ 2400 __IM uint32_t RESERVED3[62]; 2401 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 2402 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 2403 2404 2405 2406 /* =========================================================================================================================== */ 2407 /* ================ MWU ================ */ 2408 /* =========================================================================================================================== */ 2409 2410 2411 /** 2412 * @brief Memory Watch Unit (MWU) 2413 */ 2414 2415 typedef struct { /*!< (@ 0x40020000) MWU Structure */ 2416 __IM uint32_t RESERVED[64]; 2417 __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */ 2418 __IM uint32_t RESERVED1[16]; 2419 __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */ 2420 __IM uint32_t RESERVED2[100]; 2421 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2422 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2423 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2424 __IM uint32_t RESERVED3[5]; 2425 __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */ 2426 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ 2427 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ 2428 __IM uint32_t RESERVED4[53]; 2429 __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ 2430 __IM uint32_t RESERVED5[64]; 2431 __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ 2432 __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ 2433 __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ 2434 __IM uint32_t RESERVED6[57]; 2435 __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ 2436 __IM uint32_t RESERVED7[32]; 2437 __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ 2438 } NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ 2439 2440 2441 2442 /* =========================================================================================================================== */ 2443 /* ================ I2S ================ */ 2444 /* =========================================================================================================================== */ 2445 2446 2447 /** 2448 * @brief Inter-IC Sound (I2S) 2449 */ 2450 2451 typedef struct { /*!< (@ 0x40025000) I2S Structure */ 2452 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2453 generator when this is enabled. */ 2454 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2455 Triggering this task will cause the STOPPED 2456 event to be generated. */ 2457 __IM uint32_t RESERVED[63]; 2458 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2459 double-buffers. When the I2S module is started 2460 and RX is enabled, this event will be generated 2461 for every RXTXD.MAXCNT words that are received 2462 on the SDIN pin. */ 2463 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2464 __IM uint32_t RESERVED1[2]; 2465 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2466 double-buffers. When the I2S module is started 2467 and TX is enabled, this event will be generated 2468 for every RXTXD.MAXCNT words that are sent 2469 on the SDOUT pin. */ 2470 __IM uint32_t RESERVED2[122]; 2471 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2472 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2473 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2474 __IM uint32_t RESERVED3[125]; 2475 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2476 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2477 __IM uint32_t RESERVED4[3]; 2478 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2479 __IM uint32_t RESERVED5; 2480 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2481 __IM uint32_t RESERVED6[3]; 2482 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2483 __IM uint32_t RESERVED7[3]; 2484 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2485 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2486 2487 2488 2489 /* =========================================================================================================================== */ 2490 /* ================ FPU ================ */ 2491 /* =========================================================================================================================== */ 2492 2493 2494 /** 2495 * @brief FPU (FPU) 2496 */ 2497 2498 typedef struct { /*!< (@ 0x40026000) FPU Structure */ 2499 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2500 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2501 2502 2503 2504 /* =========================================================================================================================== */ 2505 /* ================ USBD ================ */ 2506 /* =========================================================================================================================== */ 2507 2508 2509 /** 2510 * @brief Universal serial bus device (USBD) 2511 */ 2512 2513 typedef struct { /*!< (@ 0x40027000) USBD Structure */ 2514 __IM uint32_t RESERVED; 2515 __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR 2516 and EPIN[n].MAXCNT registers values, and 2517 enables endpoint IN n to respond to traffic 2518 from host */ 2519 __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers 2520 values, and enables sending data on ISO 2521 endpoint */ 2522 __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR 2523 and EPOUT[n].MAXCNT registers values, and 2524 enables endpoint n to respond to traffic 2525 from host */ 2526 __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers 2527 values, and enables receiving of data on 2528 ISO endpoint */ 2529 __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ 2530 __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ 2531 __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint 2532 0 */ 2533 __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined 2534 in the DPDMVALUE register */ 2535 __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state 2536 (USB engine takes control) */ 2537 __IM uint32_t RESERVED1[40]; 2538 __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected 2539 on USB lines */ 2540 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, 2541 or EPOUT[n].PTR and EPOUT[n].MAXCNT registers 2542 have been captured on all endpoints reported 2543 in the EPSTATUS register */ 2544 __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer 2545 has been consumed. The buffer can be accessed 2546 safely by software. */ 2547 __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place 2548 on the control endpoint */ 2549 __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The 2550 buffer can be accessed safely by software. */ 2551 __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer 2552 has been consumed. The buffer can be accessed 2553 safely by software. */ 2554 __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The 2555 buffer can be accessed safely by software. */ 2556 __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition 2557 has been detected on USB lines */ 2558 __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific 2559 events has occurred. Check EVENTCAUSE register 2560 to find the cause. */ 2561 __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) 2562 on the control endpoint */ 2563 __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, 2564 indicated by the EPDATASTATUS register */ 2565 __IM uint32_t RESERVED2[39]; 2566 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2567 __IM uint32_t RESERVED3[63]; 2568 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2569 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2570 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2571 __IM uint32_t RESERVED4[61]; 2572 __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ 2573 __IM uint32_t RESERVED5[7]; 2574 __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ 2575 __IM uint32_t RESERVED6; 2576 __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA 2577 registers have been captured */ 2578 __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an 2579 acknowledged data transfer has occurred 2580 (EPDATA event) */ 2581 __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ 2582 __IM uint32_t RESERVED7[3]; 2583 __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ 2584 __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ 2585 __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ 2586 __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ 2587 __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ 2588 __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ 2589 __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ 2590 __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ 2591 __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ 2592 __IM uint32_t RESERVED8[15]; 2593 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ 2594 __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ 2595 __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by 2596 the DPDMDRIVE task. The DPDMNODRIVE task 2597 reverts the control of the lines to MAC 2598 IP (no forcing). */ 2599 __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ 2600 __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ 2601 __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ 2602 __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ 2603 __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ 2604 __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame 2605 counter */ 2606 __IM uint32_t RESERVED9[2]; 2607 __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during 2608 USB suspend */ 2609 __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint 2610 to an IN token when no data is ready to 2611 be sent */ 2612 __IM uint32_t RESERVED10[51]; 2613 __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ 2614 __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ 2615 __IM uint32_t RESERVED11[21]; 2616 __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ 2617 __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ 2618 } NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ 2619 2620 2621 2622 /* =========================================================================================================================== */ 2623 /* ================ QSPI ================ */ 2624 /* =========================================================================================================================== */ 2625 2626 2627 /** 2628 * @brief External flash interface (QSPI) 2629 */ 2630 2631 typedef struct { /*!< (@ 0x40029000) QSPI Structure */ 2632 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ 2633 __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to 2634 internal RAM */ 2635 __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external 2636 flash memory */ 2637 __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ 2638 __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ 2639 __IM uint32_t RESERVED[59]; 2640 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be 2641 generated as a response to any QSPI task. */ 2642 __IM uint32_t RESERVED1[127]; 2643 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2644 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2645 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2646 __IM uint32_t RESERVED2[125]; 2647 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected 2648 in PSELn registers */ 2649 __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ 2650 __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ 2651 __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ 2652 __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ 2653 __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute 2654 in Place operation. */ 2655 __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ 2656 __IM uint32_t RESERVED3[46]; 2657 __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ 2658 __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ 2659 __IM uint32_t RESERVED4[3]; 2660 __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep 2661 power-down mode (DPM). */ 2662 __IM uint32_t RESERVED5[3]; 2663 __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ 2664 __IM uint32_t RESERVED6[3]; 2665 __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ 2666 __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ 2667 __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ 2668 __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ 2669 } NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ 2670 2671 2672 2673 /* =========================================================================================================================== */ 2674 /* ================ CRYPTOCELL ================ */ 2675 /* =========================================================================================================================== */ 2676 2677 2678 /** 2679 * @brief CRYPTOCELL register interface (CRYPTOCELL) 2680 */ 2681 2682 typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL Structure */ 2683 __IM uint32_t RESERVED[320]; 2684 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem. */ 2685 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 2686 2687 2688 2689 /* =========================================================================================================================== */ 2690 /* ================ CC_AES ================ */ 2691 /* =========================================================================================================================== */ 2692 2693 2694 /** 2695 * @brief CRYPTOCELL AES engine (CC_AES) 2696 */ 2697 2698 typedef struct { /*!< (@ 0x5002B000) CC_AES Structure */ 2699 __IM uint32_t RESERVED[256]; 2700 __OM uint32_t AES_KEY_0[8]; /*!< (@ 0x00000400) Description collection: AES key value to use. 2701 The initial AES_KEY_0[0] register holds 2702 the least significant bits [31:0] of the 2703 key value. */ 2704 __IM uint32_t RESERVED1[8]; 2705 __IOM uint32_t AES_IV_0[4]; /*!< (@ 0x00000440) Description collection: AES Initialization Vector 2706 (IV) to use. The initial AES_IV_0[0] register 2707 holds the least significant bits [31:0] 2708 of the IV. */ 2709 __IM uint32_t RESERVED2[4]; 2710 __IOM uint32_t AES_CTR[4]; /*!< (@ 0x00000460) Description collection: AES counter (CTR) to 2711 use. The initial AES_CTR[0] register holds 2712 the least significant bits [31:0] of the 2713 CTR. */ 2714 __IM uint32_t AES_BUSY; /*!< (@ 0x00000470) Status register for AES engine activity. */ 2715 __IM uint32_t RESERVED3; 2716 __OM uint32_t AES_SK; /*!< (@ 0x00000478) Writing to this address trigger sampling of the 2717 HW key to the AES_KEY_0 register */ 2718 __OM uint32_t AES_CMAC_INIT; /*!< (@ 0x0000047C) Writing to this address triggers the AES engine 2719 to generate K1 and K2 for AES-CMAC operations. */ 2720 __IM uint32_t RESERVED4[15]; 2721 __IOM uint32_t AES_REMAINING_BYTES; /*!< (@ 0x000004BC) This register should be set with the amount of 2722 remaining bytes until the end of the current 2723 AES operation. */ 2724 __IOM uint32_t AES_CONTROL; /*!< (@ 0x000004C0) Control the AES engine behavior. */ 2725 __IM uint32_t RESERVED5; 2726 __IM uint32_t AES_HW_FLAGS; /*!< (@ 0x000004C8) Hardware configuration of the AES engine. Reset 2727 value holds the supported features. */ 2728 __IM uint32_t RESERVED6[3]; 2729 __IOM uint32_t AES_CTR_NO_INCREMENT; /*!< (@ 0x000004D8) This register enables the AES CTR no increment 2730 mode in which the counter mode is not incremented 2731 between two blocks */ 2732 __IM uint32_t RESERVED7[6]; 2733 __OM uint32_t AES_SW_RESET; /*!< (@ 0x000004F4) Reset the AES engine. */ 2734 __IM uint32_t RESERVED8[11]; 2735 __OM uint32_t AES_CMAC_SIZE0_KICK; /*!< (@ 0x00000524) Writing to this address triggers the AES engine 2736 to perform a CMAC operation with size 0. 2737 The CMAC result can be read from the AES_IV_0 2738 register. */ 2739 } NRF_CC_AES_Type; /*!< Size = 1320 (0x528) */ 2740 2741 2742 2743 /* =========================================================================================================================== */ 2744 /* ================ CC_CHACHA ================ */ 2745 /* =========================================================================================================================== */ 2746 2747 2748 /** 2749 * @brief CRYPTOCELL CHACHA engine (CC_CHACHA) 2750 */ 2751 2752 typedef struct { /*!< (@ 0x5002B000) CC_CHACHA Structure */ 2753 __IM uint32_t RESERVED[224]; 2754 __IOM uint32_t CHACHA_CONTROL; /*!< (@ 0x00000380) Control the CHACHA engine behavior. */ 2755 __IM uint32_t CHACHA_VERSION; /*!< (@ 0x00000384) CHACHA engine HW version */ 2756 __OM uint32_t CHACHA_KEY[8]; /*!< (@ 0x00000388) Description collection: CHACHA key value to use. 2757 The initial CHACHA_KEY[0] register holds 2758 the least significant bits [31:0] of the 2759 key value. */ 2760 __IOM uint32_t CHACHA_IV[2]; /*!< (@ 0x000003A8) Description collection: CHACHA Initialization 2761 Vector (IV) to use. The IV is also known 2762 as the nonce. */ 2763 __IM uint32_t CHACHA_BUSY; /*!< (@ 0x000003B0) Status register for CHACHA engine activity. */ 2764 __IM uint32_t CHACHA_HW_FLAGS; /*!< (@ 0x000003B4) Hardware configuration of the CHACHA engine. 2765 Reset value holds the supported features. */ 2766 __IOM uint32_t CHACHA_BLOCK_CNT_LSB; /*!< (@ 0x000003B8) Store the LSB value of the block counter, in 2767 order to support suspend/resume of operation */ 2768 __IOM uint32_t CHACHA_BLOCK_CNT_MSB; /*!< (@ 0x000003BC) Store the MSB value of the block counter, in 2769 order to support suspend/resume of operation */ 2770 __OM uint32_t CHACHA_SW_RESET; /*!< (@ 0x000003C0) Reset the CHACHA engine. */ 2771 __IM uint32_t CHACHA_POLY1305_KEY[8]; /*!< (@ 0x000003C4) Description collection: The auto-generated key 2772 to use in Poly1305 MAC calculation. The 2773 initial CHACHA_POLY1305_KEY[0] register 2774 holds the least significant bits [31:0] 2775 of the key value. */ 2776 __IOM uint32_t CHACHA_ENDIANNESS; /*!< (@ 0x000003E4) CHACHA engine data order configuration. */ 2777 __IM uint32_t CHACHA_DEBUG; /*!< (@ 0x000003E8) Debug register for the CHACHA engine */ 2778 } NRF_CC_CHACHA_Type; /*!< Size = 1004 (0x3ec) */ 2779 2780 2781 2782 /* =========================================================================================================================== */ 2783 /* ================ CC_CTL ================ */ 2784 /* =========================================================================================================================== */ 2785 2786 2787 /** 2788 * @brief CRYPTOCELL CTL interface (CC_CTL) 2789 */ 2790 2791 typedef struct { /*!< (@ 0x5002B000) CC_CTL Structure */ 2792 __IM uint32_t RESERVED[576]; 2793 __OM uint32_t CRYPTO_CTL; /*!< (@ 0x00000900) Defines the cryptographic flow. */ 2794 __IM uint32_t RESERVED1[3]; 2795 __IM uint32_t CRYPTO_BUSY; /*!< (@ 0x00000910) Status register for cryptographic cores engine 2796 activity. */ 2797 __IM uint32_t RESERVED2[2]; 2798 __IM uint32_t HASH_BUSY; /*!< (@ 0x0000091C) Status register for HASH engine activity. */ 2799 __IM uint32_t RESERVED3[4]; 2800 __IOM uint32_t CONTEXT_ID; /*!< (@ 0x00000930) A general-purpose read/write register. */ 2801 } NRF_CC_CTL_Type; /*!< Size = 2356 (0x934) */ 2802 2803 2804 2805 /* =========================================================================================================================== */ 2806 /* ================ CC_DIN ================ */ 2807 /* =========================================================================================================================== */ 2808 2809 2810 /** 2811 * @brief CRYPTOCELL Data IN interface (CC_DIN) 2812 */ 2813 2814 typedef struct { /*!< (@ 0x5002B000) CC_DIN Structure */ 2815 __IM uint32_t RESERVED[768]; 2816 __OM uint32_t DIN_BUFFER; /*!< (@ 0x00000C00) Used by CPU to write data directly to the DIN 2817 buffer, which is then sent to the cryptographic 2818 engines for processing. */ 2819 __IM uint32_t RESERVED1[7]; 2820 __IM uint32_t DIN_DMA_MEM_BUSY; /*!< (@ 0x00000C20) Status register for DIN DMA engine activity when 2821 accessing memory. */ 2822 __IM uint32_t RESERVED2; 2823 __OM uint32_t SRC_MEM_ADDR; /*!< (@ 0x00000C28) Data source address in memory. */ 2824 __OM uint32_t SRC_MEM_SIZE; /*!< (@ 0x00000C2C) The number of bytes to be read from memory. Writing 2825 to this register triggers the DMA operation. */ 2826 __IOM uint32_t SRC_SRAM_ADDR; /*!< (@ 0x00000C30) Data source address in RNG SRAM. */ 2827 __OM uint32_t SRC_SRAM_SIZE; /*!< (@ 0x00000C34) The number of bytes to be read from RNG SRAM. 2828 Writing to this register triggers the DMA 2829 operation. */ 2830 __IM uint32_t DIN_DMA_SRAM_BUSY; /*!< (@ 0x00000C38) Status register for DIN DMA engine activity when 2831 accessing RNG SRAM. */ 2832 __IOM uint32_t DIN_DMA_SRAM_ENDIANNESS; /*!< (@ 0x00000C3C) Configure the endianness of DIN DMA transactions 2833 towards RNG SRAM. */ 2834 __IM uint32_t RESERVED3; 2835 __OM uint32_t DIN_SW_RESET; /*!< (@ 0x00000C44) Reset the DIN DMA engine. */ 2836 __OM uint32_t DIN_CPU_DATA; /*!< (@ 0x00000C48) Specifies the number of bytes the CPU will write 2837 to the DIN_BUFFER, ensuring the cryptographic 2838 engine processes the correct amount of data. */ 2839 __OM uint32_t DIN_WRITE_ALIGN; /*!< (@ 0x00000C4C) Indicates that the next CPU write to the DIN_BUFFER 2840 is the last in the sequence. This is needed 2841 only when the data size is NOT modulo 4 2842 (e.g. HASH padding). */ 2843 __IM uint32_t DIN_FIFO_EMPTY; /*!< (@ 0x00000C50) Register indicating if DIN FIFO is empty and 2844 if more data can be accepted. */ 2845 __IM uint32_t RESERVED4; 2846 __OM uint32_t DIN_FIFO_RESET; /*!< (@ 0x00000C58) Reset the DIN FIFO, effectively clearing the 2847 FIFO for new data. */ 2848 } NRF_CC_DIN_Type; /*!< Size = 3164 (0xc5c) */ 2849 2850 2851 2852 /* =========================================================================================================================== */ 2853 /* ================ CC_DOUT ================ */ 2854 /* =========================================================================================================================== */ 2855 2856 2857 /** 2858 * @brief CRYPTOCELL Data OUT interface (CC_DOUT) 2859 */ 2860 2861 typedef struct { /*!< (@ 0x5002B000) CC_DOUT Structure */ 2862 __IM uint32_t RESERVED[768]; 2863 __IM uint32_t DOUT_BUFFER; /*!< (@ 0x00000C00) Cryptographic results directly accessible by 2864 the CPU. */ 2865 __IM uint32_t RESERVED1[71]; 2866 __IM uint32_t DOUT_DMA_MEM_BUSY; /*!< (@ 0x00000D20) Status register for DOUT DMA engine activity 2867 when accessing memory. */ 2868 __IM uint32_t RESERVED2; 2869 __OM uint32_t DST_MEM_ADDR; /*!< (@ 0x00000D28) Data destination address in memory. */ 2870 __OM uint32_t DST_MEM_SIZE; /*!< (@ 0x00000D2C) The number of bytes to be written to memory. */ 2871 __IOM uint32_t DST_SRAM_ADDR; /*!< (@ 0x00000D30) Data destination address in RNG SRAM. */ 2872 __OM uint32_t DST_SRAM_SIZE; /*!< (@ 0x00000D34) The number of bytes to be written to RNG SRAM. */ 2873 __IM uint32_t DOUT_DMA_SRAM_BUSY; /*!< (@ 0x00000D38) Status register for DOUT DMA engine activity 2874 when accessing RNG SRAM. */ 2875 __IOM uint32_t DOUT_DMA_SRAM_ENDIANNESS; /*!< (@ 0x00000D3C) Configure the endianness of DOUT DMA transactions 2876 towards RNG SRAM. */ 2877 __IM uint32_t RESERVED3; 2878 __OM uint32_t DOUT_READ_ALIGN; /*!< (@ 0x00000D44) Indication that the next CPU read from the DOUT_BUFFER 2879 is the last in the sequence. This is needed 2880 only when the data size is NOT modulo 4 2881 (e.g. HASH padding). */ 2882 __IM uint32_t RESERVED4[2]; 2883 __IM uint32_t DOUT_FIFO_EMPTY; /*!< (@ 0x00000D50) Register indicating if DOUT FIFO is empty or 2884 if more data will come. */ 2885 __IM uint32_t RESERVED5; 2886 __OM uint32_t DOUT_SW_RESET; /*!< (@ 0x00000D58) Reset the DOUT DMA engine. */ 2887 } NRF_CC_DOUT_Type; /*!< Size = 3420 (0xd5c) */ 2888 2889 2890 2891 /* =========================================================================================================================== */ 2892 /* ================ CC_HASH ================ */ 2893 /* =========================================================================================================================== */ 2894 2895 2896 /** 2897 * @brief CRYPTOCELL HASH engine (CC_HASH) 2898 */ 2899 2900 typedef struct { /*!< (@ 0x5002B000) CC_HASH Structure */ 2901 __IM uint32_t RESERVED[400]; 2902 __IOM uint32_t HASH_H[8]; /*!< (@ 0x00000640) Description collection: HASH_H value registers. 2903 The initial HASH_H[0] register holds the 2904 least significant bits [31:0] of the value. */ 2905 __IM uint32_t RESERVED1[9]; 2906 __OM uint32_t HASH_PAD_AUTO; /*!< (@ 0x00000684) Configure the HASH engine to automatically pad 2907 data at the end of the DMA transfer to complete 2908 the digest operation. */ 2909 __IM uint32_t RESERVED2[3]; 2910 __OM uint32_t HASH_INIT_STATE; /*!< (@ 0x00000694) Configure HASH engine initial state registers. */ 2911 __IM uint32_t RESERVED3[70]; 2912 __IM uint32_t HASH_VERSION; /*!< (@ 0x000007B0) HASH engine HW version */ 2913 __IM uint32_t RESERVED4[3]; 2914 __IOM uint32_t HASH_CONTROL; /*!< (@ 0x000007C0) Control the HASH engine behavior. */ 2915 __IOM uint32_t HASH_PAD; /*!< (@ 0x000007C4) Enable the hardware padding feature of the HASH 2916 engine. */ 2917 __IOM uint32_t HASH_PAD_FORCE; /*!< (@ 0x000007C8) Force the hardware padding operation to trigger 2918 if the input data length is zero bytes. */ 2919 __IOM uint32_t HASH_CUR_LEN_0; /*!< (@ 0x000007CC) Bits [31:0] of the number of bytes that have 2920 been digested so far. */ 2921 __IOM uint32_t HASH_CUR_LEN_1; /*!< (@ 0x000007D0) Bits [63:32] of the number of bytes that have 2922 been digested so far. */ 2923 __IM uint32_t RESERVED5[2]; 2924 __IM uint32_t HASH_HW_FLAGS; /*!< (@ 0x000007DC) Hardware configuration of the HASH engine. Reset 2925 value holds the supported features. */ 2926 __IM uint32_t RESERVED6; 2927 __OM uint32_t HASH_SW_RESET; /*!< (@ 0x000007E4) Reset the HASH engine. */ 2928 __IOM uint32_t HASH_ENDIANNESS; /*!< (@ 0x000007E8) Configure the endianness of HASH data and padding 2929 generation. */ 2930 } NRF_CC_HASH_Type; /*!< Size = 2028 (0x7ec) */ 2931 2932 2933 2934 /* =========================================================================================================================== */ 2935 /* ================ CC_HOST_RGF ================ */ 2936 /* =========================================================================================================================== */ 2937 2938 2939 /** 2940 * @brief CRYPTOCELL HOST register interface (CC_HOST_RGF) 2941 */ 2942 2943 typedef struct { /*!< (@ 0x5002B000) CC_HOST_RGF Structure */ 2944 __IM uint32_t RESERVED[640]; 2945 __IM uint32_t IRR; /*!< (@ 0x00000A00) Interrupt request register. Each bit of this 2946 register holds the interrupt status of a 2947 single interrupt source. If corresponding 2948 IMR bit is unmasked, an interrupt is generated. */ 2949 __IOM uint32_t IMR; /*!< (@ 0x00000A04) Interrupt mask register. Each bit of this register 2950 holds the mask of a single interrupt source. */ 2951 __OM uint32_t ICR; /*!< (@ 0x00000A08) Interrupt clear register. Writing a 1 bit into 2952 a field in this register will clear the 2953 corresponding bit in IRR. */ 2954 __IOM uint32_t ENDIANNESS; /*!< (@ 0x00000A0C) This register defines the endianness of the Host-accessible 2955 registers, and can only be written once. */ 2956 __IM uint32_t RESERVED1[5]; 2957 __IM uint32_t HOST_SIGNATURE; /*!< (@ 0x00000A24) This register holds the CRYPTOCELL subsystem 2958 signature. See reset value. */ 2959 __IM uint32_t HOST_BOOT; /*!< (@ 0x00000A28) Hardware configuration of the CRYPTOCELL subsystem. 2960 Reset value holds the supported features. */ 2961 __IM uint32_t RESERVED2[3]; 2962 __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00000A38) AES hardware key select. */ 2963 __IM uint32_t RESERVED3[4]; 2964 __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00000A4C) This write-once register is the K_PRTL lock register. 2965 When this register is set, K_PRTL cannot 2966 be used and a zeroed key will be used instead. 2967 The value of this register is saved in the 2968 CRYPTOCELL AO power domain. */ 2969 __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00000A50) This register holds bits 31:0 of K_DR. The value 2970 of this register is saved in the CRYPTOCELL 2971 AO power domain. Reading from this address 2972 returns the K_DR valid status indicating 2973 if K_DR is successfully retained. */ 2974 __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00000A54) This register holds bits 63:32 of K_DR. The value 2975 of this register is saved in the CRYPTOCELL 2976 AO power domain. */ 2977 __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00000A58) This register holds bits 95:64 of K_DR. The value 2978 of this register is saved in the CRYPTOCELL 2979 AO power domain. */ 2980 __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00000A5C) This register holds bits 127:96 of K_DR. The 2981 value of this register is saved in the CRYPTOCELL 2982 AO power domain. */ 2983 __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00000A60) Controls life-cycle state (LCS) for CRYPTOCELL 2984 subsystem */ 2985 } NRF_CC_HOST_RGF_Type; /*!< Size = 2660 (0xa64) */ 2986 2987 2988 2989 /* =========================================================================================================================== */ 2990 /* ================ CC_MISC ================ */ 2991 /* =========================================================================================================================== */ 2992 2993 2994 /** 2995 * @brief CRYPTOCELL MISC interface (CC_MISC) 2996 */ 2997 2998 typedef struct { /*!< (@ 0x5002B000) CC_MISC Structure */ 2999 __IM uint32_t RESERVED[516]; 3000 __OM uint32_t AES_CLK; /*!< (@ 0x00000810) Clock control for the AES engine. */ 3001 __IM uint32_t RESERVED1; 3002 __OM uint32_t HASH_CLK; /*!< (@ 0x00000818) Clock control for the HASH engine. */ 3003 __OM uint32_t PKA_CLK; /*!< (@ 0x0000081C) Clock control for the PKA engine. */ 3004 __OM uint32_t DMA_CLK; /*!< (@ 0x00000820) Clock control for the DMA engines. */ 3005 __IM uint32_t CLK_STATUS; /*!< (@ 0x00000824) CRYPTOCELL clocks status register. */ 3006 __IM uint32_t RESERVED2[12]; 3007 __OM uint32_t CHACHA_CLK; /*!< (@ 0x00000858) Clock control for the CHACHA engine. */ 3008 } NRF_CC_MISC_Type; /*!< Size = 2140 (0x85c) */ 3009 3010 3011 3012 /* =========================================================================================================================== */ 3013 /* ================ CC_PKA ================ */ 3014 /* =========================================================================================================================== */ 3015 3016 3017 /** 3018 * @brief CRYPTOCELL PKA engine (CC_PKA) 3019 */ 3020 3021 typedef struct { /*!< (@ 0x5002B000) CC_PKA Structure */ 3022 __IOM uint32_t MEMORY_MAP[32]; /*!< (@ 0x00000000) Description collection: Register for mapping 3023 the virtual register R[n] to a physical 3024 address in the PKA SRAM. */ 3025 __IOM uint32_t OPCODE; /*!< (@ 0x00000080) Operation code to be executed by the PKA engine. 3026 Writing to this register triggers the PKA 3027 operation. */ 3028 __IOM uint32_t N_NP_T0_T1_ADDR; /*!< (@ 0x00000084) This register defines the N, Np, T0, and T1 virtual 3029 register index. */ 3030 __IM uint32_t PKA_STATUS; /*!< (@ 0x00000088) This register holds the status for the PKA pipeline. */ 3031 __OM uint32_t PKA_SW_RESET; /*!< (@ 0x0000008C) Reset the PKA engine. */ 3032 __IOM uint32_t PKA_L[8]; /*!< (@ 0x00000090) Description collection: This register holds the 3033 operands bit size. */ 3034 __IM uint32_t PKA_PIPE; /*!< (@ 0x000000B0) Status register indicating if the PKA pipeline 3035 is ready to receive a new OPCODE. */ 3036 __IM uint32_t PKA_DONE; /*!< (@ 0x000000B4) Status register indicating if the PKA operation 3037 has been completed. */ 3038 __IM uint32_t RESERVED[3]; 3039 __IM uint32_t PKA_VERSION; /*!< (@ 0x000000C4) PKA engine HW version. Reset value holds the 3040 version. */ 3041 __IM uint32_t RESERVED1[3]; 3042 __OM uint32_t PKA_SRAM_WADDR; /*!< (@ 0x000000D4) Start address in PKA SRAM for subsequent write 3043 transactions. */ 3044 __OM uint32_t PKA_SRAM_WDATA; /*!< (@ 0x000000D8) Write data to PKA SRAM. Writing to this register 3045 triggers a DMA transaction writing data 3046 into PKA SRAM. The DMA address offset is 3047 automatically incremented during write. */ 3048 __IM uint32_t PKA_SRAM_RDATA; /*!< (@ 0x000000DC) Read data from PKA SRAM. Reading from this register 3049 triggers a DMA transaction read data from 3050 PKA SRAM. The DMA address offset is automatically 3051 incremented during read. */ 3052 __OM uint32_t PKA_SRAM_WCLEAR; /*!< (@ 0x000000E0) Register for clearing PKA SRAM write buffer. */ 3053 __OM uint32_t PKA_SRAM_RADDR; /*!< (@ 0x000000E4) Start address in PKA SRAM for subsequent read 3054 transactions. */ 3055 } NRF_CC_PKA_Type; /*!< Size = 232 (0xe8) */ 3056 3057 3058 3059 /* =========================================================================================================================== */ 3060 /* ================ CC_RNG ================ */ 3061 /* =========================================================================================================================== */ 3062 3063 3064 /** 3065 * @brief CRYPTOCELL RNG engine (CC_RNG) 3066 */ 3067 3068 typedef struct { /*!< (@ 0x5002B000) CC_RNG Structure */ 3069 __IM uint32_t RESERVED[64]; 3070 __IOM uint32_t RNG_IMR; /*!< (@ 0x00000100) Interrupt mask register. Each bit of this register 3071 holds the mask of a single interrupt source. */ 3072 __IM uint32_t RNG_ISR; /*!< (@ 0x00000104) Interrupt status register. Each bit of this register 3073 holds the interrupt status of a single interrupt 3074 source. If corresponding RNG_IMR bit is 3075 unmasked, an interrupt is generated. */ 3076 __OM uint32_t RNG_ICR; /*!< (@ 0x00000108) Interrupt clear register. Writing a 1 bit into 3077 a field in this register will clear the 3078 corresponding bit in RNG_ISR. */ 3079 __IOM uint32_t TRNG_CONFIG; /*!< (@ 0x0000010C) TRNG ring oscillator length configuration */ 3080 __IM uint32_t TRNG_VALID; /*!< (@ 0x00000110) This register indicates if TRNG entropy collection 3081 is valid. */ 3082 __IM uint32_t EHR_DATA[6]; /*!< (@ 0x00000114) Description collection: The entropy holding registers 3083 (EHR) hold 192-bits random data collected 3084 by the TRNG. The initial EHR_DATA[0] register 3085 holds the least significant bits [31:0] 3086 of the random data value. */ 3087 __IOM uint32_t NOISE_SOURCE; /*!< (@ 0x0000012C) This register controls the ring oscillator circuit 3088 used as a noise source. */ 3089 __IOM uint32_t SAMPLE_CNT; /*!< (@ 0x00000130) Sample count defining the number of CPU clock 3090 cycles between two consecutive noise source 3091 samples. */ 3092 __IOM uint32_t AUTOCORR_STATISTIC; /*!< (@ 0x00000134) Statistics counter for autocorrelation test activations. 3093 Statistics collection is stopped if one 3094 of the counters reach its limit of all ones. */ 3095 __IOM uint32_t TRNG_DEBUG; /*!< (@ 0x00000138) Debug register for the TRNG. This register is 3096 used to bypass TRNG tests in hardware. */ 3097 __IM uint32_t RESERVED1; 3098 __OM uint32_t RNG_SW_RESET; /*!< (@ 0x00000140) Reset the RNG engine. */ 3099 __IM uint32_t RESERVED2[29]; 3100 __IM uint32_t RNG_BUSY; /*!< (@ 0x000001B8) Status register for RNG engine activity. */ 3101 __OM uint32_t TRNG_RESET; /*!< (@ 0x000001BC) Reset the TRNG, including internal counter of 3102 collected bits and registers EHR_DATA and 3103 TRNG_VALID. */ 3104 __IM uint32_t RNG_HW_FLAGS; /*!< (@ 0x000001C0) Hardware configuration of RNG engine. Reset value 3105 holds the supported features. */ 3106 __OM uint32_t RNG_CLK; /*!< (@ 0x000001C4) Control clock for the RNG engine. */ 3107 __IOM uint32_t RNG_DMA; /*!< (@ 0x000001C8) Writing to this register enables the RNG DMA 3108 engine. */ 3109 __IOM uint32_t RNG_DMA_ROSC_LEN; /*!< (@ 0x000001CC) This register defines which ring oscillator length 3110 configuration should be used when using 3111 the RNG DMA engine. */ 3112 __IOM uint32_t RNG_DMA_SRAM_ADDR; /*!< (@ 0x000001D0) This register defines the start address in TRNG 3113 SRAM for the TRNG data to be collected by 3114 the RNG DMA engine. */ 3115 __IOM uint32_t RNG_DMA_SAMPLES_NUM; /*!< (@ 0x000001D4) This register defines the number of 192-bits 3116 samples that the RNG DMA engine collects 3117 per run. */ 3118 __IOM uint32_t RNG_WATCHDOG_VAL; /*!< (@ 0x000001D8) This register defines the maximum number of CPU 3119 clock cycles per TRNG collection of 192-bits 3120 samples. If the number of cycles for a collection 3121 exceeds this threshold the WATCHDOG interrupt 3122 is triggered. */ 3123 __IM uint32_t RNG_DMA_BUSY; /*!< (@ 0x000001DC) Status register for RNG DMA engine activity. */ 3124 } NRF_CC_RNG_Type; /*!< Size = 480 (0x1e0) */ 3125 3126 3127 3128 /* =========================================================================================================================== */ 3129 /* ================ CC_RNG_SRAM ================ */ 3130 /* =========================================================================================================================== */ 3131 3132 3133 /** 3134 * @brief CRYPTOCELL RNG SRAM interface (CC_RNG_SRAM) 3135 */ 3136 3137 typedef struct { /*!< (@ 0x5002B000) CC_RNG_SRAM Structure */ 3138 __IM uint32_t RESERVED[960]; 3139 __IOM uint32_t SRAM_DATA; /*!< (@ 0x00000F00) Read/Write data from RNG SRAM */ 3140 __OM uint32_t SRAM_ADDR; /*!< (@ 0x00000F04) First address given to RNG SRAM DMA for read/write 3141 transactions from/to RNG SRAM. */ 3142 __IM uint32_t SRAM_DATA_READY; /*!< (@ 0x00000F08) RNG SRAM DMA engine is ready to read/write from/to 3143 RNG SRAM. */ 3144 } NRF_CC_RNG_SRAM_Type; /*!< Size = 3852 (0xf0c) */ 3145 3146 3147 /** @} */ /* End of group Device_Peripheral_peripherals */ 3148 3149 3150 /* =========================================================================================================================== */ 3151 /* ================ Device Specific Peripheral Address Map ================ */ 3152 /* =========================================================================================================================== */ 3153 3154 3155 /** @addtogroup Device_Peripheral_peripheralAddr 3156 * @{ 3157 */ 3158 3159 #define NRF_FICR_BASE 0x10000000UL 3160 #define NRF_UICR_BASE 0x10001000UL 3161 #define NRF_APPROTECT_BASE 0x40000000UL 3162 #define NRF_CLOCK_BASE 0x40000000UL 3163 #define NRF_POWER_BASE 0x40000000UL 3164 #define NRF_P0_BASE 0x50000000UL 3165 #define NRF_P1_BASE 0x50000300UL 3166 #define NRF_RADIO_BASE 0x40001000UL 3167 #define NRF_UART0_BASE 0x40002000UL 3168 #define NRF_UARTE0_BASE 0x40002000UL 3169 #define NRF_SPI0_BASE 0x40003000UL 3170 #define NRF_SPIM0_BASE 0x40003000UL 3171 #define NRF_SPIS0_BASE 0x40003000UL 3172 #define NRF_TWI0_BASE 0x40003000UL 3173 #define NRF_TWIM0_BASE 0x40003000UL 3174 #define NRF_TWIS0_BASE 0x40003000UL 3175 #define NRF_SPI1_BASE 0x40004000UL 3176 #define NRF_SPIM1_BASE 0x40004000UL 3177 #define NRF_SPIS1_BASE 0x40004000UL 3178 #define NRF_TWI1_BASE 0x40004000UL 3179 #define NRF_TWIM1_BASE 0x40004000UL 3180 #define NRF_TWIS1_BASE 0x40004000UL 3181 #define NRF_NFCT_BASE 0x40005000UL 3182 #define NRF_GPIOTE_BASE 0x40006000UL 3183 #define NRF_SAADC_BASE 0x40007000UL 3184 #define NRF_TIMER0_BASE 0x40008000UL 3185 #define NRF_TIMER1_BASE 0x40009000UL 3186 #define NRF_TIMER2_BASE 0x4000A000UL 3187 #define NRF_RTC0_BASE 0x4000B000UL 3188 #define NRF_TEMP_BASE 0x4000C000UL 3189 #define NRF_RNG_BASE 0x4000D000UL 3190 #define NRF_ECB_BASE 0x4000E000UL 3191 #define NRF_AAR_BASE 0x4000F000UL 3192 #define NRF_CCM_BASE 0x4000F000UL 3193 #define NRF_WDT_BASE 0x40010000UL 3194 #define NRF_RTC1_BASE 0x40011000UL 3195 #define NRF_QDEC_BASE 0x40012000UL 3196 #define NRF_COMP_BASE 0x40013000UL 3197 #define NRF_LPCOMP_BASE 0x40013000UL 3198 #define NRF_EGU0_BASE 0x40014000UL 3199 #define NRF_SWI0_BASE 0x40014000UL 3200 #define NRF_EGU1_BASE 0x40015000UL 3201 #define NRF_SWI1_BASE 0x40015000UL 3202 #define NRF_EGU2_BASE 0x40016000UL 3203 #define NRF_SWI2_BASE 0x40016000UL 3204 #define NRF_EGU3_BASE 0x40017000UL 3205 #define NRF_SWI3_BASE 0x40017000UL 3206 #define NRF_EGU4_BASE 0x40018000UL 3207 #define NRF_SWI4_BASE 0x40018000UL 3208 #define NRF_EGU5_BASE 0x40019000UL 3209 #define NRF_SWI5_BASE 0x40019000UL 3210 #define NRF_TIMER3_BASE 0x4001A000UL 3211 #define NRF_TIMER4_BASE 0x4001B000UL 3212 #define NRF_PWM0_BASE 0x4001C000UL 3213 #define NRF_PDM_BASE 0x4001D000UL 3214 #define NRF_ACL_BASE 0x4001E000UL 3215 #define NRF_NVMC_BASE 0x4001E000UL 3216 #define NRF_PPI_BASE 0x4001F000UL 3217 #define NRF_MWU_BASE 0x40020000UL 3218 #define NRF_PWM1_BASE 0x40021000UL 3219 #define NRF_PWM2_BASE 0x40022000UL 3220 #define NRF_SPI2_BASE 0x40023000UL 3221 #define NRF_SPIM2_BASE 0x40023000UL 3222 #define NRF_SPIS2_BASE 0x40023000UL 3223 #define NRF_RTC2_BASE 0x40024000UL 3224 #define NRF_I2S_BASE 0x40025000UL 3225 #define NRF_FPU_BASE 0x40026000UL 3226 #define NRF_USBD_BASE 0x40027000UL 3227 #define NRF_UARTE1_BASE 0x40028000UL 3228 #define NRF_QSPI_BASE 0x40029000UL 3229 #define NRF_CRYPTOCELL_BASE 0x5002A000UL 3230 #define NRF_CC_AES_BASE 0x5002B000UL 3231 #define NRF_CC_CHACHA_BASE 0x5002B000UL 3232 #define NRF_CC_CTL_BASE 0x5002B000UL 3233 #define NRF_CC_DIN_BASE 0x5002B000UL 3234 #define NRF_CC_DOUT_BASE 0x5002B000UL 3235 #define NRF_CC_HASH_BASE 0x5002B000UL 3236 #define NRF_CC_HOST_RGF_BASE 0x5002B000UL 3237 #define NRF_CC_MISC_BASE 0x5002B000UL 3238 #define NRF_CC_PKA_BASE 0x5002B000UL 3239 #define NRF_CC_RNG_BASE 0x5002B000UL 3240 #define NRF_CC_RNG_SRAM_BASE 0x5002B000UL 3241 #define NRF_PWM3_BASE 0x4002D000UL 3242 #define NRF_SPIM3_BASE 0x4002F000UL 3243 3244 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 3245 3246 3247 /* =========================================================================================================================== */ 3248 /* ================ Peripheral declaration ================ */ 3249 /* =========================================================================================================================== */ 3250 3251 3252 /** @addtogroup Device_Peripheral_declaration 3253 * @{ 3254 */ 3255 3256 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 3257 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 3258 #define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) 3259 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 3260 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 3261 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 3262 #define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) 3263 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 3264 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 3265 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 3266 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 3267 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 3268 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 3269 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 3270 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 3271 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 3272 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 3273 #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 3274 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 3275 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 3276 #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 3277 #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 3278 #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) 3279 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 3280 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 3281 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 3282 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 3283 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 3284 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 3285 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 3286 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 3287 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 3288 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 3289 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 3290 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 3291 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 3292 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 3293 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 3294 #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 3295 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 3296 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 3297 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 3298 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 3299 #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 3300 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 3301 #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 3302 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 3303 #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 3304 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 3305 #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 3306 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 3307 #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 3308 #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) 3309 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 3310 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 3311 #define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) 3312 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 3313 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 3314 #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) 3315 #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) 3316 #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) 3317 #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) 3318 #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) 3319 #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) 3320 #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) 3321 #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) 3322 #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) 3323 #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) 3324 #define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) 3325 #define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) 3326 #define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) 3327 #define NRF_CC_AES ((NRF_CC_AES_Type*) NRF_CC_AES_BASE) 3328 #define NRF_CC_CHACHA ((NRF_CC_CHACHA_Type*) NRF_CC_CHACHA_BASE) 3329 #define NRF_CC_CTL ((NRF_CC_CTL_Type*) NRF_CC_CTL_BASE) 3330 #define NRF_CC_DIN ((NRF_CC_DIN_Type*) NRF_CC_DIN_BASE) 3331 #define NRF_CC_DOUT ((NRF_CC_DOUT_Type*) NRF_CC_DOUT_BASE) 3332 #define NRF_CC_HASH ((NRF_CC_HASH_Type*) NRF_CC_HASH_BASE) 3333 #define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) 3334 #define NRF_CC_MISC ((NRF_CC_MISC_Type*) NRF_CC_MISC_BASE) 3335 #define NRF_CC_PKA ((NRF_CC_PKA_Type*) NRF_CC_PKA_BASE) 3336 #define NRF_CC_RNG ((NRF_CC_RNG_Type*) NRF_CC_RNG_BASE) 3337 #define NRF_CC_RNG_SRAM ((NRF_CC_RNG_SRAM_Type*) NRF_CC_RNG_SRAM_BASE) 3338 #define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) 3339 #define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) 3340 3341 /** @} */ /* End of group Device_Peripheral_declaration */ 3342 3343 3344 #ifdef __cplusplus 3345 } 3346 #endif 3347 3348 #endif /* NRF52840_H */ 3349 3350 3351 /** @} */ /* End of group nrf52840 */ 3352 3353 /** @} */ /* End of group Nordic Semiconductor */ 3354
