Searched refs:NRFX_BIT_MASK (Results 1 – 17 of 17) sorted by relevance
43 NRFX_BIT_MASK(DPPI020_CH_NUM))49 NRFX_BIT_MASK(DPPI030_CH_NUM))
232 (power_mask & (NRFX_BIT_MASK(VMC_RAM_SECTION_COUNT) << VMC_RAM_POWER_S0POWER_Pos)) | in nrf_vmc_ram_block_config()233 (retention_mask & (NRFX_BIT_MASK(VMC_RAM_SECTION_COUNT) << in nrf_vmc_ram_block_config()283 return p_reg->RAM[ram_block_num].POWER & (NRFX_BIT_MASK(VMC_RAM_SECTION_COUNT) << in nrf_vmc_ram_block_power_mask_get()326 return p_reg->RAM[ram_block_num].POWER & (NRFX_BIT_MASK(VMC_RAM_SECTION_COUNT) << in nrf_vmc_ram_block_retention_mask_get()
58 #define GPIOTE0_AVAILABLE_GPIO_PORTS NRFX_BIT_MASK(GPIO_COUNT)62 #define GPIOTE1_AVAILABLE_GPIO_PORTS NRFX_BIT_MASK(GPIO_COUNT)
59 ((uint32_t)(NRFX_BIT_MASK(SAADC_CH_NUM * NRF_SAADC_LIMITS_PER_CHANNEL) \
235 #define NRF_GRTC_INTEN_MASK NRFX_BIT_MASK(GRTC_CC_MaxCount)
118 #define NRFX_GPPI_ALL_APP_GROUPS_MASK (NRFX_BIT_MASK(NRF_DPPI_GROUP_NUM_MAX) & \120 #define NRFX_GPPI_ALL_APP_CHANNELS_MASK (NRFX_BIT_MASK(NRF_DPPI_CH_NUM_MAX) & \124 #define NRFX_GPPI_PROG_APP_CHANNELS_MASK NRFX_BIT_MASK(NRFX_GPPI_PROG_APP_CHANNELS_NUM)
344 NRFX_BIT_MASK(nrf_ppib_channel_number_get(path.ppib->ppib.left.p_reg)); in gppi_dppi_connection_setup()421 possible_mask &= NRFX_BIT_MASK( in gppi_dppi_connection_setup()423 possible_mask &= NRFX_BIT_MASK( in gppi_dppi_connection_setup()476 possible_mask &= NRFX_BIT_MASK( in gppi_dppi_connection_setup()478 possible_mask &= NRFX_BIT_MASK( in gppi_dppi_connection_setup()
307 resetreas = mask & NRFX_BIT_MASK(NRFX_RESET_REASON_LOCAL_OFFSET); in nrfx_reset_reason_clear()
43 NRFX_BIT_MASK(LOCAL_IPCT_NUM))
57 .channels_mask = NRFX_BIT_MASK(NRFX_CONCAT(DPPIC, idx, _CH_NUM))
118 NRFX_BIT_MASK(NRFX_MIN(PPIB_CHANNELS_NUM(left), PPIB_CHANNELS_NUM(right))
291 #define DPPI_CHANNELS_NUM(idx) NRFX_BIT_MASK(NRFX_CONCAT(DPPIC, idx, _CH_NUM)296 #define DPPI_GROUPS_NUM(idx) NRFX_BIT_MASK(NRFX_CONCAT(DPPIC, idx, _GROUP_NUM)
118 (NRFX_BIT_MASK(PIN_FLAG_TRIG_MODE_BITS) << PIN_FLAG_TRIG_MODE_OFFSET)135 #define PIN_HANDLER_ID_MASK (NRFX_BIT_MASK(PIN_HANDLER_ID_BITS) << PIN_HANDLER_ID_SHIFT)151 #define PIN_HANDLER_MAX_COUNT NRFX_BIT_MASK(PIN_HANDLER_ID_BITS)156 #define PIN_TE_ID_MASK (NRFX_BIT_MASK(PIN_TE_ID_BITS) << PIN_TE_ID_SHIFT)832 p_cb->available_evt_handlers = NRFX_BIT_MASK(NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS); in gpiote_init()
88 #define UARTE_RX_FLAGS (NRFX_BIT_MASK(UARTE_FLAG_RX_CNT) << UARTE_FLAG_RX_OFFSET)
171 #define NRFX_BIT_MASK(x) (((x) == 32) ? UINT32_MAX : ((1UL << (x)) - 1)) macro
173 (NRFX_BIT_MASK(NRFX_CONCAT_3(GPIOTE, idx, _CH_NUM)) & \
