Searched refs:FICR_TEMP_B5_B_Pos (Results 1 – 7 of 7) sorted by relevance
1579 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ macro1580 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
1862 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ macro1863 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
1664 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ macro1665 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
2356 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ macro2357 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
3427 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ macro3428 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
1691 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ macro1692 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
