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Searched refs:ETM_TRCVDCTLR_EVENT1_Pos (Results 1 – 9 of 9) sorted by relevance

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Dnrf54l09_enga_types.h8543 …#define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. … macro
8544 …#define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field…
Dnrf54l15_types.h8246 …#define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. … macro
8247 …#define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field…
Dnrf54l05_types.h8246 …#define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. … macro
8247 …#define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field…
Dnrf54l10_types.h8246 …#define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. … macro
8247 …#define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field…
Dnrf54l20_enga_types.h8713 …#define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. … macro
8714 …#define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field…
Dnrf7120_enga_types.h10186 …#define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. … macro
10187 …#define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field…
Dnrf9230_engb_types.h15043 …#define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. … macro
15044 …#define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field…
Dnrf54h20_types.h15435 …#define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. … macro
15436 …#define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field…
Dnrf9230_enga_types.h14517 …#define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. … macro
14518 …#define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field…