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Searched refs:CONFIG (Results 1 – 25 of 53) sorted by relevance

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/hal_nordic-latest/nrfx/hal/
Dnrf_glitchdet.h97 return ((p_reg->CONFIG & GLITCHDET_CONFIG_ENABLE_Msk) in nrf_glitchdet_enable_check()
103 p_reg->CONFIG = (p_reg->CONFIG & ~GLITCHDET_CONFIG_ENABLE_Msk) | in nrf_glitchdet_enable_set()
110 return (nrf_glitchdet_mode_t)((p_reg->CONFIG & GLITCHDET_CONFIG_MODE_Msk) >> in nrf_glitchdet_mode_get()
117 p_reg->CONFIG = (p_reg->CONFIG & ~GLITCHDET_CONFIG_MODE_Msk) | in nrf_glitchdet_mode_set()
Dnrf_spis.h1025 p_reg->CONFIG = config; in nrf_spis_configure()
1073 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_spis_rx_pattern_match_enable_set()
1081 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_spis_rx_pattern_match_enable_set()
1089 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_spis_rx_pattern_match_enable_set()
1097 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_spis_rx_pattern_match_enable_set()
1117 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk) in nrf_spis_rx_pattern_match_enable_check()
1121 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk) in nrf_spis_rx_pattern_match_enable_check()
1125 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk) in nrf_spis_rx_pattern_match_enable_check()
1129 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk) in nrf_spis_rx_pattern_match_enable_check()
1145 p_reg->DMA.RX.MATCH.CONFIG |= SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk; in nrf_spis_rx_pattern_match_one_shot_enable()
[all …]
Dnrf_twim.h1047 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_twim_rx_pattern_match_enable_set()
1055 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_twim_rx_pattern_match_enable_set()
1063 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_twim_rx_pattern_match_enable_set()
1071 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_twim_rx_pattern_match_enable_set()
1091 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk) in nrf_twim_rx_pattern_match_enable_check()
1095 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk) in nrf_twim_rx_pattern_match_enable_check()
1099 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk) in nrf_twim_rx_pattern_match_enable_check()
1103 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk) in nrf_twim_rx_pattern_match_enable_check()
1119 p_reg->DMA.RX.MATCH.CONFIG |= TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk; in nrf_twim_rx_pattern_match_one_shot_enable()
1122 p_reg->DMA.RX.MATCH.CONFIG |= TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk; in nrf_twim_rx_pattern_match_one_shot_enable()
[all …]
Dnrf_tdm.h768 p_reg->CONFIG.MODE = p_config->mode; in nrf_tdm_configure()
769 p_reg->CONFIG.ALIGN = p_config->alignment; in nrf_tdm_configure()
770 p_reg->CONFIG.SWIDTH = p_config->sample_width; in nrf_tdm_configure()
771 p_reg->CONFIG.CHANNEL.MASK = p_config->channels; in nrf_tdm_configure()
772 p_reg->CONFIG.CHANNEL.NUM = p_config->num_of_channels; in nrf_tdm_configure()
773 p_reg->CONFIG.CHANNEL.DELAY = p_config->channel_delay; in nrf_tdm_configure()
774 p_reg->CONFIG.SCK.DIV = p_config->sck_setup; in nrf_tdm_configure()
775 p_reg->CONFIG.FSYNC.DURATION = p_config->fsync_duration; in nrf_tdm_configure()
776 p_reg->CONFIG.MCK.DIV = p_config->mck_setup; in nrf_tdm_configure()
777 p_reg->CONFIG.SCK.POLARITY = (p_config->sck_polarity == NRF_TDM_POLARITY_POSEDGE) ? in nrf_tdm_configure()
[all …]
Dnrf_gpiote.h825 p_reg->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event; in nrf_gpiote_event_enable()
830 p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk; in nrf_gpiote_event_disable()
838 p_reg->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk); in nrf_gpiote_event_configure()
839 p_reg->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) | in nrf_gpiote_event_configure()
845 return ((p_reg->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos); in nrf_gpiote_event_pin_get()
851 return (nrf_gpiote_polarity_t)((p_reg->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >> in nrf_gpiote_event_polarity_get()
857 uint32_t final_config = p_reg->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task; in nrf_gpiote_task_enable()
864 p_reg->CONFIG[idx] = final_config | in nrf_gpiote_task_enable()
870 p_reg->CONFIG[idx] = final_config; in nrf_gpiote_task_enable()
875 p_reg->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Msk; in nrf_gpiote_task_disable()
[all …]
Dnrf_spim.h1523 p_reg->CONFIG = config; in nrf_spim_configure()
1563 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_spim_rx_pattern_match_enable_set()
1571 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_spim_rx_pattern_match_enable_set()
1579 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_spim_rx_pattern_match_enable_set()
1587 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG & in nrf_spim_rx_pattern_match_enable_set()
1607 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk) in nrf_spim_rx_pattern_match_enable_check()
1611 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk) in nrf_spim_rx_pattern_match_enable_check()
1615 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk) in nrf_spim_rx_pattern_match_enable_check()
1619 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk) in nrf_spim_rx_pattern_match_enable_check()
1635 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk; in nrf_spim_rx_pattern_match_one_shot_enable()
[all …]
Dnrf_i2s.h739 p_reg->CONFIG.MODE = p_config->mode; in nrf_i2s_configure()
740 p_reg->CONFIG.FORMAT = p_config->format; in nrf_i2s_configure()
741 p_reg->CONFIG.ALIGN = p_config->alignment; in nrf_i2s_configure()
742 p_reg->CONFIG.SWIDTH = p_config->sample_width; in nrf_i2s_configure()
743 p_reg->CONFIG.CHANNELS = p_config->channels; in nrf_i2s_configure()
744 p_reg->CONFIG.RATIO = p_config->ratio; in nrf_i2s_configure()
748 p_reg->CONFIG.MCKEN = in nrf_i2s_configure()
753 p_reg->CONFIG.MCKFREQ = p_config->mck_setup; in nrf_i2s_configure()
754 p_reg->CONFIG.MCKEN = in nrf_i2s_configure()
771 p_reg->CONFIG.RXEN = (p_buffer_rx != NULL) ? 1 : 0; in nrf_i2s_transfer_set()
[all …]
Dnrf_rramc.h636 p_config->mode_write = (bool)((p_reg->CONFIG & RRAMC_CONFIG_WEN_Msk) >> in nrf_rramc_config_get()
638 p_config->write_buff_size = (uint32_t)((p_reg->CONFIG & RRAMC_CONFIG_WRITEBUFSIZE_Msk) >> in nrf_rramc_config_get()
647 p_reg->CONFIG = ((uint32_t)p_config->mode_write << RRAMC_CONFIG_WEN_Pos) | in nrf_rramc_config_set()
675 p_config->access_timeout = (uint16_t)((p_reg->POWER.CONFIG & in nrf_rramc_power_config_get()
678 p_config->abort_on_pof = ((p_reg->POWER.CONFIG & in nrf_rramc_power_config_get()
687 p_reg->POWER.CONFIG = in nrf_rramc_power_config_set()
709 p_reg->REGION[region].CONFIG = (((p_config->permissions in nrf_rramc_region_config_set()
725 uint32_t reg = p_reg->REGION[region].CONFIG; in nrf_rramc_region_config_get()
739 return p_reg->REGION[region].CONFIG; in nrf_rramc_region_config_raw_get()
Dnrf_uicr.h498 config.permissions = (p_reg->MEM[index].CONFIG & in nrf_uicr_mem_config_get()
503 config.owner = (nrf_owner_t)((p_reg->MEM[index].CONFIG & UICR_MEM_CONFIG_OWNERID_Msk) >> in nrf_uicr_mem_config_get()
507 config.address = (p_reg->MEM[index].CONFIG & UICR_MEM_CONFIG_ADDRESS_Msk); in nrf_uicr_mem_config_get()
526 config.secattr = (p_reg->PERIPH[index].CONFIG & UICR_PERIPH_CONFIG_SECURE_Msk) >> in nrf_uicr_periph_config_get()
529 config.dmasec = (p_reg->PERIPH[index].CONFIG & UICR_PERIPH_CONFIG_DMASEC_Msk) >> in nrf_uicr_periph_config_get()
532 …config.processor = (nrf_processor_t)((p_reg->PERIPH[index].CONFIG & UICR_PERIPH_CONFIG_PROCESSOR_M… in nrf_uicr_periph_config_get()
536 config.address = (p_reg->PERIPH[index].CONFIG & UICR_PERIPH_CONFIG_ADDRESS_Msk); in nrf_uicr_periph_config_get()
714 config.size = (p_reg->MAILBOX[index].CONFIG & UICR_MAILBOX_CONFIG_SIZE_Msk) in nrf_uicr_mailbox_config_get()
717 config.owner = (nrf_owner_t)((p_reg->MAILBOX[index].CONFIG & UICR_MAILBOX_CONFIG_OWNERID_Msk) in nrf_uicr_mailbox_config_get()
720 config.secure = (p_reg->MAILBOX[index].CONFIG & UICR_MAILBOX_CONFIG_SECURE_Msk) in nrf_uicr_mailbox_config_get()
Dnrf_mpc.h781 p_reg->REGION[index].CONFIG = (((p_config->slave_number << in nrf_mpc_region_config_set()
806 ret.slave_number = (p_reg->REGION[index].CONFIG & MPC_REGION_CONFIG_SLAVENUMBER_Msk) in nrf_mpc_region_config_get()
809 ret.lock = ((p_reg->REGION[index].CONFIG & MPC_REGION_CONFIG_LOCK_Msk) in nrf_mpc_region_config_get()
812 ret.enable = ((p_reg->REGION[index].CONFIG & MPC_REGION_CONFIG_ENABLE_Msk) in nrf_mpc_region_config_get()
815 ret.permissions = (p_reg->REGION[index].CONFIG & in nrf_mpc_region_config_get()
820 ret.owner = (nrf_owner_t)((p_reg->REGION[index].CONFIG & MPC_REGION_CONFIG_OWNERID_Msk) in nrf_mpc_region_config_get()
884 p_reg->OVERRIDE[index].CONFIG = (((p_config->lock ? MPC_OVERRIDE_CONFIG_LOCK_Locked : in nrf_mpc_override_config_set()
911 ret.slave_number = (p_reg->OVERRIDE[index].CONFIG & MPC_OVERRIDE_CONFIG_SLAVENUMBER_Msk) in nrf_mpc_override_config_get()
915 ret.lock = ((p_reg->OVERRIDE[index].CONFIG & MPC_OVERRIDE_CONFIG_LOCK_Msk) in nrf_mpc_override_config_get()
918 ret.enable = ((p_reg->OVERRIDE[index].CONFIG & MPC_OVERRIDE_CONFIG_ENABLE_Msk) in nrf_mpc_override_config_get()
[all …]
Dnrf_clock.h1485 p_reg->CONFIG.SETUP = (p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_RESET_Msk) | in nrf_clock_config_reset_enable_set()
1498 p_reg->CONFIG.SETUP = (p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_BYPASSLFLPRC_Msk) | in nrf_clock_config_bypass_enable_set()
1504 p_reg->CONFIG.SETUP = (p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_BYPASSLFRC_Msk) | in nrf_clock_config_bypass_enable_set()
1510 p_reg->CONFIG.SETUP = (p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_BYPASSLFXO_Msk) | in nrf_clock_config_bypass_enable_set()
1516 p_reg->CONFIG.SETUP = (p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_BYPASSSYNTH_Msk) | in nrf_clock_config_bypass_enable_set()
1530 p_reg->CONFIG.SETUP = ((p_reg->CONFIG.SETUP & ~CLOCK_CONFIG_SETUP_TIMEOUT_Msk) in nrf_clock_config_timeout_set()
1537 return (p_reg->CONFIG.SETUP & CLOCK_CONFIG_SETUP_TIMEOUT_Msk) >> CLOCK_CONFIG_SETUP_TIMEOUT_Pos; in nrf_clock_config_timeout_get()
1545 p_reg->CONFIG.THRESHOLD = ((((uint32_t)thr_low) << CLOCK_CONFIG_THRESHOLD_LOW_Pos) in nrf_clock_config_threshold_set()
Dnrf_cracen_cm.h203 p_reg->CRYPTMSTRDMA.CONFIG = (uint32_t)mask; in nrf_cracen_cm_config_indirect_set()
208 p_reg->CRYPTMSTRDMA.CONFIG = CRACENCORE_CRYPTMSTRDMA_CONFIG_SOFTRST_Msk; in nrf_cracen_cm_softreset()
209 p_reg->CRYPTMSTRDMA.CONFIG = 0; in nrf_cracen_cm_softreset()
Dnrf_mvdma.h581 p_reg->CONFIG.MODE = ((uint32_t)mode << MVDMA_CONFIG_MODE_MODE_Pos); in nrf_mvdma_mode_set()
587 p_reg->CONFIG.AXIMODE = ((uint32_t)aximode << MVDMA_CONFIG_AXIMODE_AXIMODE_Pos); in nrf_mvdma_aximode_set()
597 p_reg->CONFIG.SOURCELISTPTR = (uint32_t)p_job; in nrf_mvdma_source_list_ptr_set()
606 return (nrf_vdma_job_t *)(p_reg->CONFIG.SOURCELISTPTR); in nrf_mvdma_source_list_ptr_get()
616 p_reg->CONFIG.SINKLISTPTR = (uint32_t)p_job; in nrf_mvdma_sink_list_ptr_set()
625 return (nrf_vdma_job_t *)(p_reg->CONFIG.SINKLISTPTR); in nrf_mvdma_sink_list_ptr_get()
Dnrf_rng.h306 p_reg->CONFIG |= RNG_CONFIG_DERCEN_Msk; in nrf_rng_error_correction_enable()
311 p_reg->CONFIG &= ~RNG_CONFIG_DERCEN_Msk; in nrf_rng_error_correction_disable()
Dnrf_auxpll.h482 uint32_t reg = p_reg->CONFIG.CFGSTATIC; in nrf_auxpll_config_get()
505 p_reg->CONFIG.CFGSTATIC = in nrf_auxpll_config_set()
605 return ((p_reg->CONFIG.CFGSTATIC & AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Msk) >> in nrf_auxpll_static_ratio_get()
/hal_nordic-latest/nrfx/mdk/
Dsystem_nrf54l_approtect.h76 NRF_WDT30->CONFIG = 9; in nrf54l_handle_approtect_signal()
116 NRF_WDT30->CONFIG = 9; in nrf54l_handle_secureapprotect_signal()
Dsystem_nrf7120_enga_approtect.h76 NRF_WDT30->CONFIG = 9; in nrf7120_handle_approtect_signal()
116 NRF_WDT30->CONFIG = 9; in nrf7120_handle_secureapprotect_signal()
Dsystem_nrf7120_enga.c183 …NRF_GLITCHDET_S->GLITCHDETECTOR.CONFIG = (GLITCHDET_GLITCHDETECTOR_CONFIG_ENABLE_Disable << GLITCH… in SystemInit()
185 … NRF_GLITCHDET_S->CONFIG = (GLITCHDET_CONFIG_ENABLE_Disable << GLITCHDET_CONFIG_ENABLE_Pos); in SystemInit()
Dsystem_nrf54l.c225 …NRF_GLITCHDET_S->GLITCHDETECTOR.CONFIG = (GLITCHDET_GLITCHDETECTOR_CONFIG_ENABLE_Disable << GLITCH… in SystemInit()
227 … NRF_GLITCHDET_S->CONFIG = (GLITCHDET_CONFIG_ENABLE_Disable << GLITCHDET_CONFIG_ENABLE_Pos); in SystemInit()
Dnrf52805.h440 …__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input confi… member
850 …__IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hard… member
910 …__IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hard… member
1072 …__IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the a… member
1107 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register … member
1153 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register … member
1197 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register … member
1238 …__IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configur… member
1434 …__IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register … member
1565 …__IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register … member
[all …]
Dnrf51.h454 …__IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hard… member
489 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. … member
595 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. … member
625 …__IOM uint32_t CONFIG[4]; /*!< (@ 0x00000510) Channel configuration registers.… member
653 …__IOM uint32_t CONFIG; /*!< (@ 0x00000504) ADC configuration register. … member
789 …__IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. … member
933 …__IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register. … member
1057 …__IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. … member
Dnrf52810.h443 …__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input confi… member
889 …__IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hard… member
949 …__IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hard… member
1112 …__IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the a… member
1147 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register … member
1193 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register … member
1237 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register … member
1278 …__IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configur… member
1474 …__IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register … member
1605 …__IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register … member
[all …]
Dsystem_nrf5340_application.c216 NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; in SystemInit()
222 NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; in SystemInit()
Dnrf52811.h462 …__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input confi… member
959 …__IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hard… member
1019 …__IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hard… member
1050 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register … member
1096 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register … member
1140 …__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register … member
1308 …__IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the a… member
1348 …__IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configur… member
1544 …__IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register … member
1675 …__IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register … member
[all …]
Dsystem_nrf91.c156 NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; in SystemInit()
186 NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren; in SystemInit()

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