1 /*
2 
3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef __NRF52840_BITS_H
36 #define __NRF52840_BITS_H
37 
38 /*lint ++flb "Enter library region" */
39 
40 /* Peripheral: AAR */
41 /* Description: Accelerated Address Resolver */
42 
43 /* Register: AAR_TASKS_START */
44 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
45 
46 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
47 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
48 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
49 #define AAR_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
50 
51 /* Register: AAR_TASKS_STOP */
52 /* Description: Stop resolving addresses */
53 
54 /* Bit 0 : Stop resolving addresses */
55 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
56 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
57 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
58 
59 /* Register: AAR_EVENTS_END */
60 /* Description: Address resolution procedure complete */
61 
62 /* Bit 0 : Address resolution procedure complete */
63 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
64 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
65 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
66 #define AAR_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */
67 
68 /* Register: AAR_EVENTS_RESOLVED */
69 /* Description: Address resolved */
70 
71 /* Bit 0 : Address resolved */
72 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
73 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
74 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0x0UL) /*!< Event not generated */
75 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (0x1UL) /*!< Event generated */
76 
77 /* Register: AAR_EVENTS_NOTRESOLVED */
78 /* Description: Address not resolved */
79 
80 /* Bit 0 : Address not resolved */
81 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
82 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
83 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0x0UL) /*!< Event not generated */
84 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (0x1UL) /*!< Event generated */
85 
86 /* Register: AAR_INTENSET */
87 /* Description: Enable interrupt */
88 
89 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
90 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
91 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
92 #define AAR_INTENSET_NOTRESOLVED_Disabled (0x0UL) /*!< Read: Disabled */
93 #define AAR_INTENSET_NOTRESOLVED_Enabled (0x1UL) /*!< Read: Enabled */
94 #define AAR_INTENSET_NOTRESOLVED_Set (0x1UL) /*!< Enable */
95 
96 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
97 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
98 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
99 #define AAR_INTENSET_RESOLVED_Disabled (0x0UL) /*!< Read: Disabled */
100 #define AAR_INTENSET_RESOLVED_Enabled (0x1UL) /*!< Read: Enabled */
101 #define AAR_INTENSET_RESOLVED_Set (0x1UL) /*!< Enable */
102 
103 /* Bit 0 : Write '1' to enable interrupt for event END */
104 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
105 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
106 #define AAR_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
107 #define AAR_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
108 #define AAR_INTENSET_END_Set (0x1UL) /*!< Enable */
109 
110 /* Register: AAR_INTENCLR */
111 /* Description: Disable interrupt */
112 
113 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
114 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
115 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
116 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0x0UL) /*!< Read: Disabled */
117 #define AAR_INTENCLR_NOTRESOLVED_Enabled (0x1UL) /*!< Read: Enabled */
118 #define AAR_INTENCLR_NOTRESOLVED_Clear (0x1UL) /*!< Disable */
119 
120 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
121 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
122 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
123 #define AAR_INTENCLR_RESOLVED_Disabled (0x0UL) /*!< Read: Disabled */
124 #define AAR_INTENCLR_RESOLVED_Enabled (0x1UL) /*!< Read: Enabled */
125 #define AAR_INTENCLR_RESOLVED_Clear (0x1UL) /*!< Disable */
126 
127 /* Bit 0 : Write '1' to disable interrupt for event END */
128 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
129 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
130 #define AAR_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
131 #define AAR_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
132 #define AAR_INTENCLR_END_Clear (0x1UL) /*!< Disable */
133 
134 /* Register: AAR_STATUS */
135 /* Description: Resolution status */
136 
137 /* Bits 3..0 : The IRK that was used last time an address was resolved */
138 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
139 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
140 
141 /* Register: AAR_ENABLE */
142 /* Description: Enable AAR */
143 
144 /* Bits 1..0 : Enable or disable AAR */
145 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
146 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
147 #define AAR_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
148 #define AAR_ENABLE_ENABLE_Enabled (0x3UL) /*!< Enable */
149 
150 /* Register: AAR_NIRK */
151 /* Description: Number of IRKs */
152 
153 /* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */
154 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
155 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
156 
157 /* Register: AAR_IRKPTR */
158 /* Description: Pointer to IRK data structure */
159 
160 /* Bits 31..0 : Pointer to the IRK data structure */
161 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
162 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
163 
164 /* Register: AAR_ADDRPTR */
165 /* Description: Pointer to the resolvable address */
166 
167 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
168 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
169 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
170 
171 /* Register: AAR_SCRATCHPTR */
172 /* Description: Pointer to data area used for temporary storage */
173 
174 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */
175 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
176 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
177 
178 
179 /* Peripheral: ACL */
180 /* Description: Access control lists */
181 
182 /* Register: ACL_ACL_ADDR */
183 /* Description: Description cluster: Start address of region to protect. The start address must be word-aligned. */
184 
185 /* Bits 31..0 : Start address of flash region n. The start address must point to a flash page boundary. */
186 #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
187 #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
188 
189 /* Register: ACL_ACL_SIZE */
190 /* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */
191 
192 /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */
193 #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
194 #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
195 
196 /* Register: ACL_ACL_PERM */
197 /* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */
198 
199 /* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */
200 #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
201 #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
202 #define ACL_ACL_PERM_READ_Enable (0x0UL) /*!< Allow read instructions to region n. */
203 #define ACL_ACL_PERM_READ_Disable (0x1UL) /*!< Block read instructions to region n. */
204 
205 /* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */
206 #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
207 #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
208 #define ACL_ACL_PERM_WRITE_Enable (0x0UL) /*!< Allow write and erase instructions to region n. */
209 #define ACL_ACL_PERM_WRITE_Disable (0x1UL) /*!< Block write and erase instructions to region n. */
210 
211 
212 /* Peripheral: APPROTECT */
213 /* Description: Access Port Protection */
214 
215 /* Register: APPROTECT_FORCEPROTECT */
216 /* Description: Software force enable APPROTECT mechanism until next reset. */
217 
218 /* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */
219 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */
220 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */
221 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x00UL) /*!< Software force enable APPROTECT mechanism */
222 
223 /* Register: APPROTECT_DISABLE */
224 /* Description: Software disable APPROTECT mechanism */
225 
226 /* Bits 7..0 : Software disable APPROTECT mechanism */
227 #define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */
228 #define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */
229 #define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */
230 
231 
232 /* Peripheral: CCM */
233 /* Description: AES CCM mode encryption */
234 
235 /* Register: CCM_TASKS_KSGEN */
236 /* Description: Start generation of keystream. This operation will stop by itself when completed. */
237 
238 /* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */
239 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
240 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
241 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (0x1UL) /*!< Trigger task */
242 
243 /* Register: CCM_TASKS_CRYPT */
244 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */
245 
246 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
247 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
248 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
249 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (0x1UL) /*!< Trigger task */
250 
251 /* Register: CCM_TASKS_STOP */
252 /* Description: Stop encryption/decryption */
253 
254 /* Bit 0 : Stop encryption/decryption */
255 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
256 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
257 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
258 
259 /* Register: CCM_TASKS_RATEOVERRIDE */
260 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
261 
262 /* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
263 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */
264 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */
265 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (0x1UL) /*!< Trigger task */
266 
267 /* Register: CCM_EVENTS_ENDKSGEN */
268 /* Description: Keystream generation complete */
269 
270 /* Bit 0 : Keystream generation complete */
271 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
272 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
273 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0x0UL) /*!< Event not generated */
274 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (0x1UL) /*!< Event generated */
275 
276 /* Register: CCM_EVENTS_ENDCRYPT */
277 /* Description: Encrypt/decrypt complete */
278 
279 /* Bit 0 : Encrypt/decrypt complete */
280 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
281 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
282 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0x0UL) /*!< Event not generated */
283 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (0x1UL) /*!< Event generated */
284 
285 /* Register: CCM_EVENTS_ERROR */
286 /* Description: Deprecated register - CCM error event */
287 
288 /* Bit 0 : Deprecated field -  CCM error event */
289 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
290 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
291 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
292 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */
293 
294 /* Register: CCM_SHORTS */
295 /* Description: Shortcuts between local events and tasks */
296 
297 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
298 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
299 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
300 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0x0UL) /*!< Disable shortcut */
301 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (0x1UL) /*!< Enable shortcut */
302 
303 /* Register: CCM_INTENSET */
304 /* Description: Enable interrupt */
305 
306 /* Bit 2 : Deprecated intsetfield -  Write '1' to enable interrupt for event ERROR */
307 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
308 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
309 #define CCM_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
310 #define CCM_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
311 #define CCM_INTENSET_ERROR_Set (0x1UL) /*!< Enable */
312 
313 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
314 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
315 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
316 #define CCM_INTENSET_ENDCRYPT_Disabled (0x0UL) /*!< Read: Disabled */
317 #define CCM_INTENSET_ENDCRYPT_Enabled (0x1UL) /*!< Read: Enabled */
318 #define CCM_INTENSET_ENDCRYPT_Set (0x1UL) /*!< Enable */
319 
320 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
321 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
322 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
323 #define CCM_INTENSET_ENDKSGEN_Disabled (0x0UL) /*!< Read: Disabled */
324 #define CCM_INTENSET_ENDKSGEN_Enabled (0x1UL) /*!< Read: Enabled */
325 #define CCM_INTENSET_ENDKSGEN_Set (0x1UL) /*!< Enable */
326 
327 /* Register: CCM_INTENCLR */
328 /* Description: Disable interrupt */
329 
330 /* Bit 2 : Deprecated intclrfield -  Write '1' to disable interrupt for event ERROR */
331 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
332 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
333 #define CCM_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
334 #define CCM_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
335 #define CCM_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */
336 
337 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
338 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
339 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
340 #define CCM_INTENCLR_ENDCRYPT_Disabled (0x0UL) /*!< Read: Disabled */
341 #define CCM_INTENCLR_ENDCRYPT_Enabled (0x1UL) /*!< Read: Enabled */
342 #define CCM_INTENCLR_ENDCRYPT_Clear (0x1UL) /*!< Disable */
343 
344 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
345 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
346 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
347 #define CCM_INTENCLR_ENDKSGEN_Disabled (0x0UL) /*!< Read: Disabled */
348 #define CCM_INTENCLR_ENDKSGEN_Enabled (0x1UL) /*!< Read: Enabled */
349 #define CCM_INTENCLR_ENDKSGEN_Clear (0x1UL) /*!< Disable */
350 
351 /* Register: CCM_MICSTATUS */
352 /* Description: MIC check result */
353 
354 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
355 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
356 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
357 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0x0UL) /*!< MIC check failed */
358 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (0x1UL) /*!< MIC check passed */
359 
360 /* Register: CCM_ENABLE */
361 /* Description: Enable */
362 
363 /* Bits 1..0 : Enable or disable CCM */
364 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
365 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
366 #define CCM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
367 #define CCM_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable */
368 
369 /* Register: CCM_MODE */
370 /* Description: Operation mode */
371 
372 /* Bit 24 : Packet length configuration */
373 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
374 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
375 #define CCM_MODE_LENGTH_Default (0x0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */
376 #define CCM_MODE_LENGTH_Extended (0x1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */
377 
378 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
379 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
380 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
381 #define CCM_MODE_DATARATE_1Mbit (0x0UL) /*!< 1 Mbps */
382 #define CCM_MODE_DATARATE_2Mbit (0x1UL) /*!< 2 Mbps */
383 #define CCM_MODE_DATARATE_125Kbps (0x2UL) /*!< 125 kbps */
384 #define CCM_MODE_DATARATE_500Kbps (0x3UL) /*!< 500 kbps */
385 
386 /* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */
387 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
388 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
389 #define CCM_MODE_MODE_Encryption (0x0UL) /*!< AES CCM packet encryption mode */
390 #define CCM_MODE_MODE_Decryption (0x1UL) /*!< AES CCM packet decryption mode */
391 
392 /* Register: CCM_CNFPTR */
393 /* Description: Pointer to data structure holding the AES key and the NONCE vector */
394 
395 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */
396 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
397 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
398 
399 /* Register: CCM_INPTR */
400 /* Description: Input pointer */
401 
402 /* Bits 31..0 : Input pointer */
403 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
404 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
405 
406 /* Register: CCM_OUTPTR */
407 /* Description: Output pointer */
408 
409 /* Bits 31..0 : Output pointer */
410 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
411 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
412 
413 /* Register: CCM_SCRATCHPTR */
414 /* Description: Pointer to data area used for temporary storage */
415 
416 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation,
417         MIC generation and encryption/decryption. */
418 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
419 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
420 
421 /* Register: CCM_MAXPACKETSIZE */
422 /* Description: Length of keystream generated when MODE.LENGTH = Extended */
423 
424 /* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */
425 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
426 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
427 
428 /* Register: CCM_RATEOVERRIDE */
429 /* Description: Data rate override setting. */
430 
431 /* Bits 1..0 : Data rate override setting */
432 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
433 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
434 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0x0UL) /*!< 1 Mbps */
435 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (0x1UL) /*!< 2 Mbps */
436 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (0x2UL) /*!< 125 kbps */
437 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (0x3UL) /*!< 500 kbps */
438 
439 
440 /* Peripheral: CC_AES */
441 /* Description: CRYPTOCELL AES engine */
442 
443 /* Register: CC_AES_AES_KEY_0 */
444 /* Description: Description collection: AES key value to use.
445         The initial AES_KEY_0[0] register holds the least significant bits [31:0] of the key value. */
446 
447 /* Bits 31..0 : AES key value. */
448 #define CC_AES_AES_KEY_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */
449 #define CC_AES_AES_KEY_0_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_KEY_0_VALUE_Pos) /*!< Bit mask of VALUE field. */
450 
451 /* Register: CC_AES_AES_IV_0 */
452 /* Description: Description collection: AES Initialization Vector (IV) to use.
453         The initial AES_IV_0[0] register holds the least significant bits [31:0] of the IV. */
454 
455 /* Bits 31..0 : AES non-tunneling or first tunnel stage IV value. */
456 #define CC_AES_AES_IV_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */
457 #define CC_AES_AES_IV_0_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_IV_0_VALUE_Pos) /*!< Bit mask of VALUE field. */
458 
459 /* Register: CC_AES_AES_CTR */
460 /* Description: Description collection: AES counter (CTR) to use.
461         The initial AES_CTR[0] register holds the least significant bits [31:0] of the CTR. */
462 
463 /* Bits 31..0 : AES CTR value. */
464 #define CC_AES_AES_CTR_VALUE_Pos (0UL) /*!< Position of VALUE field. */
465 #define CC_AES_AES_CTR_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_CTR_VALUE_Pos) /*!< Bit mask of VALUE field. */
466 
467 /* Register: CC_AES_AES_BUSY */
468 /* Description: Status register for AES engine activity. */
469 
470 /* Bit 0 : AES engine status. */
471 #define CC_AES_AES_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
472 #define CC_AES_AES_BUSY_STATUS_Msk (0x1UL << CC_AES_AES_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
473 #define CC_AES_AES_BUSY_STATUS_Idle (0x0UL) /*!< AES engine is idle */
474 #define CC_AES_AES_BUSY_STATUS_Busy (0x1UL) /*!< AES engine is busy */
475 
476 /* Register: CC_AES_AES_SK */
477 /* Description: Writing to this address trigger sampling of the HW key to the AES_KEY_0 register */
478 
479 /* Bit 0 : Sample HW key to AES_KEY_0 registers. */
480 #define CC_AES_AES_SK_AES_SK_Pos (0UL) /*!< Position of AES_SK field. */
481 #define CC_AES_AES_SK_AES_SK_Msk (0x1UL << CC_AES_AES_SK_AES_SK_Pos) /*!< Bit mask of AES_SK field. */
482 
483 /* Register: CC_AES_AES_CMAC_INIT */
484 /* Description: Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations. */
485 
486 /* Bit 0 : Generate K1 and K2 for the AES-CMAC operations. */
487 #define CC_AES_AES_CMAC_INIT_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
488 #define CC_AES_AES_CMAC_INIT_ENABLE_Msk (0x1UL << CC_AES_AES_CMAC_INIT_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
489 #define CC_AES_AES_CMAC_INIT_ENABLE_Enable (0x1UL) /*!< Initialize AES-CMAC operations. */
490 
491 /* Register: CC_AES_AES_REMAINING_BYTES */
492 /* Description: This register should be set with the amount of remaining bytes until the end of the current AES operation. */
493 
494 /* Bits 31..0 : Remaining bytes util the end of the current AES operation. */
495 #define CC_AES_AES_REMAINING_BYTES_VALUE_Pos (0UL) /*!< Position of VALUE field. */
496 #define CC_AES_AES_REMAINING_BYTES_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_REMAINING_BYTES_VALUE_Pos) /*!< Bit mask of VALUE field. */
497 
498 /* Register: CC_AES_AES_CONTROL */
499 /* Description: Control the AES engine behavior. */
500 
501 /* Bit 31 : Using direct access and not the DIN-DOUT DMA interface */
502 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Pos (31UL) /*!< Position of DIRECT_ACCESS field. */
503 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Msk (0x1UL << CC_AES_AES_CONTROL_DIRECT_ACCESS_Pos) /*!< Bit mask of DIRECT_ACCESS field. */
504 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Disable (0x0UL) /*!< Access using the DIN-DOUT DMA interface */
505 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Enable (0x1UL) /*!< Access using direct access */
506 
507 /* Bit 29 : This field determines the value that is written to AES_KEY_0, when AES_SK is kicked. */
508 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Pos (29UL) /*!< Position of AES_XOR_CRYPTOKEY field. */
509 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Msk (0x1UL << CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Pos) /*!< Bit mask of AES_XOR_CRYPTOKEY field. */
510 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Disable (0x0UL) /*!< The value that is written to AES_KEY_0 is the value of the HW cryptokey as is. */
511 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Enable (0x1UL) /*!< The value that is written to AES_KEY_0 is the value of the HW cryptokey XOR with the current value of AES_KEY_0. */
512 
513 /* Bits 13..12 : Set the AES key length. */
514 #define CC_AES_AES_CONTROL_NK_KEY0_Pos (12UL) /*!< Position of NK_KEY0 field. */
515 #define CC_AES_AES_CONTROL_NK_KEY0_Msk (0x3UL << CC_AES_AES_CONTROL_NK_KEY0_Pos) /*!< Bit mask of NK_KEY0 field. */
516 #define CC_AES_AES_CONTROL_NK_KEY0_128Bits (0x0UL) /*!< 128 bits key length */
517 
518 /* Bits 4..2 : Set the AES mode. */
519 #define CC_AES_AES_CONTROL_MODE_KEY0_Pos (2UL) /*!< Position of MODE_KEY0 field. */
520 #define CC_AES_AES_CONTROL_MODE_KEY0_Msk (0x7UL << CC_AES_AES_CONTROL_MODE_KEY0_Pos) /*!< Bit mask of MODE_KEY0 field. */
521 #define CC_AES_AES_CONTROL_MODE_KEY0_ECB (0x0UL) /*!< Electronic codebook mode */
522 #define CC_AES_AES_CONTROL_MODE_KEY0_CBC (0x1UL) /*!< Cipher block chaining mode */
523 #define CC_AES_AES_CONTROL_MODE_KEY0_CTR (0x2UL) /*!< Counter mode */
524 #define CC_AES_AES_CONTROL_MODE_KEY0_CBC_MAC (0x3UL) /*!< Cipher Block Chaining Message Authentication Code */
525 #define CC_AES_AES_CONTROL_MODE_KEY0_CMAC (0x7UL) /*!< Cipher-based Message Authentication Code */
526 
527 /* Bit 0 : Set AES encrypt or decrypt mode in non-tunneling operations. */
528 #define CC_AES_AES_CONTROL_DEC_KEY0_Pos (0UL) /*!< Position of DEC_KEY0 field. */
529 #define CC_AES_AES_CONTROL_DEC_KEY0_Msk (0x1UL << CC_AES_AES_CONTROL_DEC_KEY0_Pos) /*!< Bit mask of DEC_KEY0 field. */
530 #define CC_AES_AES_CONTROL_DEC_KEY0_Encrypt (0x0UL) /*!< Perform AES encryption */
531 #define CC_AES_AES_CONTROL_DEC_KEY0_Decrypt (0x1UL) /*!< Perform AES decryption */
532 
533 /* Register: CC_AES_AES_HW_FLAGS */
534 /* Description: Hardware configuration of the AES engine. Reset value holds the supported features. */
535 
536 /* Bit 12 : If this flag is set, the engine support DFA countermeasures. */
537 #define CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Pos (12UL) /*!< Position of DFA_CNTRMSR_EXIST field. */
538 #define CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Pos) /*!< Bit mask of DFA_CNTRMSR_EXIST field. */
539 
540 /* Bit 11 : If this flag is set, the engine support a second register set for tunneling operations. */
541 #define CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Pos (11UL) /*!< Position of SECOND_REGS_SET_EXIST field. */
542 #define CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Pos) /*!< Bit mask of SECOND_REGS_SET_EXIST field. */
543 
544 /* Bit 10 : If this flag is set, the engine support tunneling operations. */
545 #define CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Pos (10UL) /*!< Position of AES_TUNNEL_EXIST field. */
546 #define CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Pos) /*!< Bit mask of AES_TUNNEL_EXIST field. */
547 
548 /* Bit 9 : If this flag is set, the engine contains the PREV_IV register for faster AES XCBC MAC calculation. */
549 #define CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Pos (9UL) /*!< Position of AES_SUPPORT_PREV_IV field. */
550 #define CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Pos) /*!< Bit mask of AES_SUPPORT_PREV_IV field. */
551 
552 /* Bit 8 : If this flag is set, the engine uses 5 SBOX where each AES round takes 4 cycles. */
553 #define CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Pos (8UL) /*!< Position of USE_5_SBOXES field. */
554 #define CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Msk (0x1UL << CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Pos) /*!< Bit mask of USE_5_SBOXES field. */
555 
556 /* Bit 5 : If this flag is set, the engine uses SBOX tables. */
557 #define CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Pos (5UL) /*!< Position of USE_SBOX_TABLE field. */
558 #define CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Msk (0x1UL << CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Pos) /*!< Bit mask of USE_SBOX_TABLE field. */
559 
560 /* Bit 4 : If this flag is set, the engine only support encrypt operations. */
561 #define CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Pos (4UL) /*!< Position of ONLY_ENCRYPT field. */
562 #define CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Msk (0x1UL << CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Pos) /*!< Bit mask of ONLY_ENCRYPT field. */
563 
564 /* Bit 3 : If this flag is set, the engine support AES CTR mode. */
565 #define CC_AES_AES_HW_FLAGS_CTR_EXIST_Pos (3UL) /*!< Position of CTR_EXIST field. */
566 #define CC_AES_AES_HW_FLAGS_CTR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_CTR_EXIST_Pos) /*!< Bit mask of CTR_EXIST field. */
567 
568 /* Bit 2 : If this flag is set, the engine support DPA countermeasures. */
569 #define CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Pos (2UL) /*!< Position of DPA_CNTRMSR_EXIST field. */
570 #define CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Pos) /*!< Bit mask of DPA_CNTRMSR_EXIST field. */
571 
572 /* Bit 1 : If this flag is set, the engine support AES_LARGE_RKEK. */
573 #define CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Pos (1UL) /*!< Position of AES_LARGE_RKEK field. */
574 #define CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Pos) /*!< Bit mask of AES_LARGE_RKEK field. */
575 
576 /* Bit 0 : If this flag is set, the engine support 192 bits and 256 bits key size. */
577 #define CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Pos (0UL) /*!< Position of SUPPORT_256_192_KEY field. */
578 #define CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Msk (0x1UL << CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Pos) /*!< Bit mask of SUPPORT_256_192_KEY field. */
579 
580 /* Register: CC_AES_AES_CTR_NO_INCREMENT */
581 /* Description: This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks */
582 
583 /* Bit 0 : This field enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks */
584 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
585 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Msk (0x1UL << CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
586 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Disable (0x0UL) /*!< Counter always incremented between blocks */
587 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Enable (0x1UL) /*!< Do not increment counter between blocks */
588 
589 /* Register: CC_AES_AES_SW_RESET */
590 /* Description: Reset the AES engine. */
591 
592 /* Bit 0 : Writing any value to this address resets the AES engine. The reset takes 4 CPU clock cycles to complete. */
593 #define CC_AES_AES_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
594 #define CC_AES_AES_SW_RESET_RESET_Msk (0x1UL << CC_AES_AES_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
595 #define CC_AES_AES_SW_RESET_RESET_Enable (0x1UL) /*!< Reset AES engine. */
596 
597 /* Register: CC_AES_AES_CMAC_SIZE0_KICK */
598 /* Description: Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register. */
599 
600 /* Bit 0 : Force AES CMAC operation with size 0. */
601 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
602 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Msk (0x1UL << CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
603 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Disable (0x0UL) /*!< Normal AES CMAC operation */
604 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Enable (0x1UL) /*!< Force CMAC operation with size 0 */
605 
606 
607 /* Peripheral: CC_CHACHA */
608 /* Description: CRYPTOCELL CHACHA engine */
609 
610 /* Register: CC_CHACHA_CHACHA_CONTROL */
611 /* Description: Control the CHACHA engine behavior. */
612 
613 /* Bit 10 : Use 96 bits Initialization Vector (IV) */
614 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Pos (10UL) /*!< Position of USE_IV_96BIT field. */
615 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Pos) /*!< Bit mask of USE_IV_96BIT field. */
616 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Disable (0x0UL) /*!< Use default size IV of 64 bit */
617 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Enable (0x1UL) /*!< The IV is 96 bits */
618 
619 /* Bit 9 : Reset block counter for new messages */
620 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Pos (9UL) /*!< Position of RESET_BLOCK_CNT field. */
621 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Pos) /*!< Bit mask of RESET_BLOCK_CNT field. */
622 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Disable (0x0UL) /*!< Use current block counter value */
623 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Enable (0x1UL) /*!< Reset block counter value to zero */
624 
625 /* Bits 5..4 : Set number of permutation rounds, default value is 20. */
626 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Pos (4UL) /*!< Position of NUM_OF_ROUNDS field. */
627 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Msk (0x3UL << CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Pos) /*!< Bit mask of NUM_OF_ROUNDS field. */
628 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Default (0x0UL) /*!< Use 20 rounds of rotation (default) */
629 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_12Rounds (0x1UL) /*!< Use 12 rounds of rotation */
630 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_8Rounds (0x2UL) /*!< Use 8 rounds of rotation */
631 
632 /* Bit 3 : Key length selection. */
633 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Pos (3UL) /*!< Position of KEY_LEN field. */
634 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Pos) /*!< Bit mask of KEY_LEN field. */
635 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_256Bits (0x0UL) /*!< Use 256 bits key length */
636 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_128Bits (0x1UL) /*!< Use 128 bits key length */
637 
638 /* Bit 2 : Generate the key to use in Poly1305 message authentication code calculation. */
639 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Pos (2UL) /*!< Position of GEN_KEY_POLY1305 field. */
640 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Pos) /*!< Bit mask of GEN_KEY_POLY1305 field. */
641 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Disable (0x0UL) /*!< Do not generate Poly1305 key */
642 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Enable (0x1UL) /*!< Generate Poly1305 key */
643 
644 /* Bit 1 : Perform initialization for a new message */
645 #define CC_CHACHA_CHACHA_CONTROL_INIT_Pos (1UL) /*!< Position of INIT field. */
646 #define CC_CHACHA_CHACHA_CONTROL_INIT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_INIT_Pos) /*!< Bit mask of INIT field. */
647 #define CC_CHACHA_CHACHA_CONTROL_INIT_Disable (0x0UL) /*!< Message already initialized */
648 #define CC_CHACHA_CHACHA_CONTROL_INIT_Enable (0x1UL) /*!< Initialize new message */
649 
650 /* Bit 0 : Run engine in ChaCha or Salsa mode */
651 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Pos (0UL) /*!< Position of CHACHA_OR_SALSA field. */
652 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Pos) /*!< Bit mask of CHACHA_OR_SALSA field. */
653 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_ChaCha (0x0UL) /*!< Run engine in ChaCha mode */
654 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Salsa (0x1UL) /*!< Run engine in Salsa mode */
655 
656 /* Register: CC_CHACHA_CHACHA_VERSION */
657 /* Description: CHACHA engine HW version */
658 
659 /* Bits 31..0 :   */
660 #define CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Pos (0UL) /*!< Position of CHACHA_VERSION field. */
661 #define CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Pos) /*!< Bit mask of CHACHA_VERSION field. */
662 
663 /* Register: CC_CHACHA_CHACHA_KEY */
664 /* Description: Description collection: CHACHA key value to use. The initial CHACHA_KEY[0] register holds the least significant bits [31:0] of the key value. */
665 
666 /* Bits 31..0 : CHACHA key value. */
667 #define CC_CHACHA_CHACHA_KEY_VALUE_Pos (0UL) /*!< Position of VALUE field. */
668 #define CC_CHACHA_CHACHA_KEY_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_KEY_VALUE_Pos) /*!< Bit mask of VALUE field. */
669 
670 /* Register: CC_CHACHA_CHACHA_IV */
671 /* Description: Description collection: CHACHA Initialization Vector (IV) to use. The IV is also known as the nonce. */
672 
673 /* Bits 31..0 : CHACHA IV value. */
674 #define CC_CHACHA_CHACHA_IV_VALUE_Pos (0UL) /*!< Position of VALUE field. */
675 #define CC_CHACHA_CHACHA_IV_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_IV_VALUE_Pos) /*!< Bit mask of VALUE field. */
676 
677 /* Register: CC_CHACHA_CHACHA_BUSY */
678 /* Description: Status register for CHACHA engine activity. */
679 
680 /* Bit 0 : CHACHA engine status. */
681 #define CC_CHACHA_CHACHA_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
682 #define CC_CHACHA_CHACHA_BUSY_STATUS_Msk (0x1UL << CC_CHACHA_CHACHA_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
683 #define CC_CHACHA_CHACHA_BUSY_STATUS_Idle (0x0UL) /*!< CHACHA engine is idle */
684 #define CC_CHACHA_CHACHA_BUSY_STATUS_Busy (0x1UL) /*!< CHACHA engine is busy */
685 
686 /* Register: CC_CHACHA_CHACHA_HW_FLAGS */
687 /* Description: Hardware configuration of the CHACHA engine. Reset value holds the supported features. */
688 
689 /* Bit 2 : If this flag is set, the next matrix calculated when the current one is written to data output path. */
690 #define CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Pos (2UL) /*!< Position of FAST_CHACHA field. */
691 #define CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Pos) /*!< Bit mask of FAST_CHACHA field. */
692 
693 /* Bit 1 : If this flag is set, the engine include Salsa support */
694 #define CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Pos (1UL) /*!< Position of SALSA_EXISTS field. */
695 #define CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Pos) /*!< Bit mask of SALSA_EXISTS field. */
696 
697 /* Bit 0 : If this flag is set, the engine include ChaCha support */
698 #define CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Pos (0UL) /*!< Position of CHACHA_EXISTS field. */
699 #define CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Pos) /*!< Bit mask of CHACHA_EXISTS field. */
700 
701 /* Register: CC_CHACHA_CHACHA_BLOCK_CNT_LSB */
702 /* Description: Store the LSB value of the block counter, in order to support suspend/resume of operation */
703 
704 /* Bits 31..0 : This register holds the ChaCha block counter bits [31:0] and must be read and written during respectively suspend and resume operations. */
705 #define CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Pos (0UL) /*!< Position of VALUE field. */
706 #define CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Pos) /*!< Bit mask of VALUE field. */
707 
708 /* Register: CC_CHACHA_CHACHA_BLOCK_CNT_MSB */
709 /* Description: Store the MSB value of the block counter, in order to support suspend/resume of operation */
710 
711 /* Bits 31..0 : This register holds the ChaCha block counter bits [63:32] and must be read and written during respectively suspend and resume operations. */
712 #define CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Pos (0UL) /*!< Position of VALUE field. */
713 #define CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Pos) /*!< Bit mask of VALUE field. */
714 
715 /* Register: CC_CHACHA_CHACHA_SW_RESET */
716 /* Description: Reset the CHACHA engine. */
717 
718 /* Bit 0 : Writing any value to this address resets the CHACHA engine. The reset takes 4 CPU clock cycles to complete. */
719 #define CC_CHACHA_CHACHA_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
720 #define CC_CHACHA_CHACHA_SW_RESET_RESET_Msk (0x1UL << CC_CHACHA_CHACHA_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
721 #define CC_CHACHA_CHACHA_SW_RESET_RESET_Enable (0x1UL) /*!< Reset CHACHA engine. */
722 
723 /* Register: CC_CHACHA_CHACHA_POLY1305_KEY */
724 /* Description: Description collection: The auto-generated key to use in Poly1305 MAC calculation. The initial CHACHA_POLY1305_KEY[0] register holds the least significant bits [31:0] of the key value. */
725 
726 /* Bits 31..0 : Poly1305 key value. */
727 #define CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Pos (0UL) /*!< Position of VALUE field. */
728 #define CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Pos) /*!< Bit mask of VALUE field. */
729 
730 /* Register: CC_CHACHA_CHACHA_ENDIANNESS */
731 /* Description: CHACHA engine data order configuration. */
732 
733 /* Bit 4 : Change the byte order of the output data. */
734 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Pos (4UL) /*!< Position of CHACHA_DOUT_BYTE_ORDER field. */
735 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Pos) /*!< Bit mask of CHACHA_DOUT_BYTE_ORDER field. */
736 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Default (0x0UL) /*!< Use default byte order within each output word, where bytes are ordered as follows: B0, B1, B2, B3. */
737 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Reverse (0x1UL) /*!< Reverse the byte order within each output word, where bytes are re-ordered as follows: B3, B2, B1, B0. */
738 
739 /* Bit 3 : Change the word order of the output data. */
740 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Pos (3UL) /*!< Position of CHACHA_DOUT_WORD_ORDER field. */
741 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Pos) /*!< Bit mask of CHACHA_DOUT_WORD_ORDER field. */
742 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Default (0x0UL) /*!< Uses default word order for 128-bits output, where words are ordered as follows: w0, w1, w2, w3. */
743 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Reverse (0x1UL) /*!< Reverse the word order for 128-bits output, where words are re-ordered as follows: w3, w2, w1, w0. */
744 
745 /* Bit 2 : Change the quarter of a matrix order in the engine. */
746 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Pos (2UL) /*!< Position of CHACHA_CORE_MATRIX_LBE_ORDER field. */
747 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Pos) /*!< Bit mask of CHACHA_CORE_MATRIX_LBE_ORDER field. */
748 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Default (0x0UL) /*!< Use default quarter of matrix order, where quarters are ordered as follows: q0, q1, q2, q3. Each quarter represents a 128-bits section of the matrix. */
749 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Reverse (0x1UL) /*!< Reverse the order of matrix quarters, where quarters are re-ordered as follows: q3, q2, q1, q0. Each quarter represents a 128-bits section of the matrix. */
750 
751 /* Bit 1 : Change the byte order of the input data. */
752 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Pos (1UL) /*!< Position of CHACHA_DIN_BYTE_ORDER field. */
753 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Pos) /*!< Bit mask of CHACHA_DIN_BYTE_ORDER field. */
754 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Default (0x0UL) /*!< Use default byte order within each input word, where bytes are ordered as follows: B0, B1, B2, B3. */
755 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Reverse (0x1UL) /*!< Reverse the byte order within each input word, where bytes are re-ordered as follows: B3, B2, B1, B0. */
756 
757 /* Bit 0 : Change the word order of the input data. */
758 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Pos (0UL) /*!< Position of CHACHA_DIN_WORD_ORDER field. */
759 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Pos) /*!< Bit mask of CHACHA_DIN_WORD_ORDER field. */
760 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Default (0x0UL) /*!< Use default word order for 128-bits input, where words are ordered as follows: w0, w1, w2, w3. */
761 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Reverse (0x1UL) /*!< Reverses the word order for 128-bits input, where words are re-ordered as follows: w3, w2, w1, w0. */
762 
763 /* Register: CC_CHACHA_CHACHA_DEBUG */
764 /* Description: Debug register for the CHACHA engine */
765 
766 /* Bits 1..0 : Reflects the debug state of the CHACHA FSM. */
767 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Pos (0UL) /*!< Position of FSM_STATE field. */
768 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Msk (0x3UL << CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Pos) /*!< Bit mask of FSM_STATE field. */
769 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_IDLE_STATE (0x0UL) /*!< CHACHA FSM is in idle state */
770 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_INIT_STATE (0x1UL) /*!< CHACHA FSM is in init state */
771 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_ROUNDS_STATE (0x2UL) /*!< CHACHA FSM is in rounds state */
772 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_FINAL_STATE (0x3UL) /*!< CHACHA FSM is in final state */
773 
774 
775 /* Peripheral: CC_CTL */
776 /* Description: CRYPTOCELL CTL interface */
777 
778 /* Register: CC_CTL_CRYPTO_CTL */
779 /* Description: Defines the cryptographic flow. */
780 
781 /* Bits 4..0 : Configure the cryptographic engine mode. */
782 #define CC_CTL_CRYPTO_CTL_MODE_Pos (0UL) /*!< Position of MODE field. */
783 #define CC_CTL_CRYPTO_CTL_MODE_Msk (0x1FUL << CC_CTL_CRYPTO_CTL_MODE_Pos) /*!< Bit mask of MODE field. */
784 #define CC_CTL_CRYPTO_CTL_MODE_Bypass (0x00UL) /*!< Bypass cryptographic engine */
785 #define CC_CTL_CRYPTO_CTL_MODE_AESActive (0x01UL) /*!< Use AES engine */
786 #define CC_CTL_CRYPTO_CTL_MODE_AESToHashActive (0x02UL) /*!< Pipe AES engine output to HASH engine input */
787 #define CC_CTL_CRYPTO_CTL_MODE_AESAndHashActive (0x03UL) /*!< Process input using both AES and HASH engine in parallell */
788 #define CC_CTL_CRYPTO_CTL_MODE_HashActive (0x07UL) /*!< Use HASH engine */
789 #define CC_CTL_CRYPTO_CTL_MODE_AESMACAndBypassActive (0x09UL) /*!< Calculate AES MAC and bypass */
790 #define CC_CTL_CRYPTO_CTL_MODE_AESToHashAndDOUTActive (0x0AUL) /*!< Pipe AES engine output to HASH engine input. The resulting digest output is piped to DOUT buffer. */
791 #define CC_CTL_CRYPTO_CTL_MODE_ChaChaActive (0x10UL) /*!< Use CHACHA engine */
792 
793 /* Register: CC_CTL_CRYPTO_BUSY */
794 /* Description: Status register for cryptographic cores engine activity. */
795 
796 /* Bit 0 : Cryptographic core engines status. */
797 #define CC_CTL_CRYPTO_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
798 #define CC_CTL_CRYPTO_BUSY_STATUS_Msk (0x1UL << CC_CTL_CRYPTO_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
799 #define CC_CTL_CRYPTO_BUSY_STATUS_Idle (0x0UL) /*!< Cryptographic core engines are idle */
800 #define CC_CTL_CRYPTO_BUSY_STATUS_Busy (0x1UL) /*!< Cryptographic core engines are busy */
801 
802 /* Register: CC_CTL_HASH_BUSY */
803 /* Description: Status register for HASH engine activity. */
804 
805 /* Bit 0 : Hash engine status. */
806 #define CC_CTL_HASH_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
807 #define CC_CTL_HASH_BUSY_STATUS_Msk (0x1UL << CC_CTL_HASH_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
808 #define CC_CTL_HASH_BUSY_STATUS_Idle (0x0UL) /*!< HASH engine is idle */
809 #define CC_CTL_HASH_BUSY_STATUS_Busy (0x1UL) /*!< HASH engine is busy */
810 
811 /* Register: CC_CTL_CONTEXT_ID */
812 /* Description: A general-purpose read/write register. */
813 
814 /* Bits 7..0 : Context ID */
815 #define CC_CTL_CONTEXT_ID_CONTEXT_ID_Pos (0UL) /*!< Position of CONTEXT_ID field. */
816 #define CC_CTL_CONTEXT_ID_CONTEXT_ID_Msk (0xFFUL << CC_CTL_CONTEXT_ID_CONTEXT_ID_Pos) /*!< Bit mask of CONTEXT_ID field. */
817 
818 
819 /* Peripheral: CC_DIN */
820 /* Description: CRYPTOCELL Data IN interface */
821 
822 /* Register: CC_DIN_DIN_BUFFER */
823 /* Description: Used by CPU to write data directly to the DIN buffer, which is then sent to the cryptographic engines for processing. */
824 
825 /* Bits 31..0 : This register is mapped into 8 addresses in order to enable a CPU burst. */
826 #define CC_DIN_DIN_BUFFER_DATA_Pos (0UL) /*!< Position of DATA field. */
827 #define CC_DIN_DIN_BUFFER_DATA_Msk (0xFFFFFFFFUL << CC_DIN_DIN_BUFFER_DATA_Pos) /*!< Bit mask of DATA field. */
828 
829 /* Register: CC_DIN_DIN_DMA_MEM_BUSY */
830 /* Description: Status register for DIN DMA engine activity when accessing memory. */
831 
832 /* Bit 0 : DIN memory DMA engine status. */
833 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
834 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Msk (0x1UL << CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
835 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Idle (0x0UL) /*!< DIN memory DMA engine is idle */
836 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Busy (0x1UL) /*!< DIN memory DMA engine is busy */
837 
838 /* Register: CC_DIN_SRC_MEM_ADDR */
839 /* Description: Data source address in memory. */
840 
841 /* Bits 31..0 : Source address in memory. */
842 #define CC_DIN_SRC_MEM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
843 #define CC_DIN_SRC_MEM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DIN_SRC_MEM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
844 
845 /* Register: CC_DIN_SRC_MEM_SIZE */
846 /* Description: The number of bytes to be read from memory. Writing to this register triggers the DMA operation. */
847 
848 /* Bit 31 : This field is reserved */
849 #define CC_DIN_SRC_MEM_SIZE_LAST_Pos (31UL) /*!< Position of LAST field. */
850 #define CC_DIN_SRC_MEM_SIZE_LAST_Msk (0x1UL << CC_DIN_SRC_MEM_SIZE_LAST_Pos) /*!< Bit mask of LAST field. */
851 
852 /* Bit 30 : This field is reserved */
853 #define CC_DIN_SRC_MEM_SIZE_FIRST_Pos (30UL) /*!< Position of FIRST field. */
854 #define CC_DIN_SRC_MEM_SIZE_FIRST_Msk (0x1UL << CC_DIN_SRC_MEM_SIZE_FIRST_Pos) /*!< Bit mask of FIRST field. */
855 
856 /* Bits 29..0 : Total number of bytes to read from memory. */
857 #define CC_DIN_SRC_MEM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
858 #define CC_DIN_SRC_MEM_SIZE_SIZE_Msk (0x3FFFFFFFUL << CC_DIN_SRC_MEM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
859 
860 /* Register: CC_DIN_SRC_SRAM_ADDR */
861 /* Description: Data source address in RNG SRAM. */
862 
863 /* Bits 31..0 : Source address in RNG SRAM. */
864 #define CC_DIN_SRC_SRAM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
865 #define CC_DIN_SRC_SRAM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DIN_SRC_SRAM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
866 
867 /* Register: CC_DIN_SRC_SRAM_SIZE */
868 /* Description: The number of bytes to be read from RNG SRAM. Writing to this register triggers the DMA operation. */
869 
870 /* Bits 31..0 : Total number of bytes to read from RNG SRAM. */
871 #define CC_DIN_SRC_SRAM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
872 #define CC_DIN_SRC_SRAM_SIZE_SIZE_Msk (0xFFFFFFFFUL << CC_DIN_SRC_SRAM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
873 
874 /* Register: CC_DIN_DIN_DMA_SRAM_BUSY */
875 /* Description: Status register for DIN DMA engine activity when accessing RNG SRAM. */
876 
877 /* Bit 0 : DIN RNG SRAM DMA engine status. */
878 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
879 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Msk (0x1UL << CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
880 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Idle (0x0UL) /*!< DIN RNG SRAM DMA engine is idle */
881 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Busy (0x1UL) /*!< DIN RNG SRAM DMA engine is busy */
882 
883 /* Register: CC_DIN_DIN_DMA_SRAM_ENDIANNESS */
884 /* Description: Configure the endianness of DIN DMA transactions towards RNG SRAM. */
885 
886 /* Bit 0 : Endianness of DIN DMA transactions towards RNG SRAM. The default value is little-endian. */
887 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */
888 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
889 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for RNG SRAM DMA transactions */
890 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for RNG SRAM DMA transactions */
891 
892 /* Register: CC_DIN_DIN_SW_RESET */
893 /* Description: Reset the DIN DMA engine. */
894 
895 /* Bit 0 : Writing any value to this address resets the DIN DMA engine. The reset takes 4 CPU clock cycles to complete. */
896 #define CC_DIN_DIN_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
897 #define CC_DIN_DIN_SW_RESET_RESET_Msk (0x1UL << CC_DIN_DIN_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
898 #define CC_DIN_DIN_SW_RESET_RESET_Enable (0x1UL) /*!< Reset DIN DMA engine. */
899 
900 /* Register: CC_DIN_DIN_CPU_DATA */
901 /* Description: Specifies the number of bytes the CPU will write to the DIN_BUFFER, ensuring the cryptographic engine processes the correct amount of data. */
902 
903 /* Bits 15..0 : When using CPU direct write to the DIN_BUFFER, the size of input data in bytes should be written to this register. */
904 #define CC_DIN_DIN_CPU_DATA_SIZE_Pos (0UL) /*!< Position of SIZE field. */
905 #define CC_DIN_DIN_CPU_DATA_SIZE_Msk (0xFFFFUL << CC_DIN_DIN_CPU_DATA_SIZE_Pos) /*!< Bit mask of SIZE field. */
906 
907 /* Register: CC_DIN_DIN_WRITE_ALIGN */
908 /* Description: Indicates that the next CPU write to the DIN_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). */
909 
910 /* Bit 0 : Next CPU write to the DIN_BUFFER is the last word. */
911 #define CC_DIN_DIN_WRITE_ALIGN_LAST_Pos (0UL) /*!< Position of LAST field. */
912 #define CC_DIN_DIN_WRITE_ALIGN_LAST_Msk (0x1UL << CC_DIN_DIN_WRITE_ALIGN_LAST_Pos) /*!< Bit mask of LAST field. */
913 #define CC_DIN_DIN_WRITE_ALIGN_LAST_Confirm (0x1UL) /*!< The next CPU write is the last in the sequence. */
914 
915 /* Register: CC_DIN_DIN_FIFO_EMPTY */
916 /* Description: Register indicating if DIN FIFO is empty and if more data can be accepted. */
917 
918 /* Bit 0 : DIN FIFO status */
919 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
920 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_Msk (0x1UL << CC_DIN_DIN_FIFO_EMPTY_STATUS_Pos) /*!< Bit mask of STATUS field. */
921 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_NotEmpty (0x0UL) /*!< DIN FIFO is not empty */
922 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_Empty (0x1UL) /*!< DIN FIFO is empty, and more data can be accepted */
923 
924 /* Register: CC_DIN_DIN_FIFO_RESET */
925 /* Description: Reset the DIN FIFO, effectively clearing the FIFO for new data. */
926 
927 /* Bit 0 : Writing any value to this address resets the DIN FIFO. */
928 #define CC_DIN_DIN_FIFO_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
929 #define CC_DIN_DIN_FIFO_RESET_RESET_Msk (0x1UL << CC_DIN_DIN_FIFO_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
930 #define CC_DIN_DIN_FIFO_RESET_RESET_Enable (0x1UL) /*!< Reset DIN FIFO. */
931 
932 
933 /* Peripheral: CC_DOUT */
934 /* Description: CRYPTOCELL Data OUT interface */
935 
936 /* Register: CC_DOUT_DOUT_BUFFER */
937 /* Description: Cryptographic results directly accessible by the CPU. */
938 
939 /* Bits 31..0 : This address can be used by the CPU to read data directly from the DOUT buffer. */
940 #define CC_DOUT_DOUT_BUFFER_DATA_Pos (0UL) /*!< Position of DATA field. */
941 #define CC_DOUT_DOUT_BUFFER_DATA_Msk (0xFFFFFFFFUL << CC_DOUT_DOUT_BUFFER_DATA_Pos) /*!< Bit mask of DATA field. */
942 
943 /* Register: CC_DOUT_DOUT_DMA_MEM_BUSY */
944 /* Description: Status register for DOUT DMA engine activity when accessing memory. */
945 
946 /* Bit 0 : DOUT memory DMA engine status. */
947 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
948 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
949 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Idle (0x0UL) /*!< DOUT memory DMA engine is idle */
950 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Busy (0x1UL) /*!< DOUT memory DMA engine is busy */
951 
952 /* Register: CC_DOUT_DST_MEM_ADDR */
953 /* Description: Data destination address in memory. */
954 
955 /* Bits 31..0 : Destination address in memory. */
956 #define CC_DOUT_DST_MEM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
957 #define CC_DOUT_DST_MEM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DOUT_DST_MEM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
958 
959 /* Register: CC_DOUT_DST_MEM_SIZE */
960 /* Description: The number of bytes to be written to memory. */
961 
962 /* Bit 31 : This field is reserved */
963 #define CC_DOUT_DST_MEM_SIZE_LAST_Pos (31UL) /*!< Position of LAST field. */
964 #define CC_DOUT_DST_MEM_SIZE_LAST_Msk (0x1UL << CC_DOUT_DST_MEM_SIZE_LAST_Pos) /*!< Bit mask of LAST field. */
965 
966 /* Bit 30 : This field is reserved */
967 #define CC_DOUT_DST_MEM_SIZE_FIRST_Pos (30UL) /*!< Position of FIRST field. */
968 #define CC_DOUT_DST_MEM_SIZE_FIRST_Msk (0x1UL << CC_DOUT_DST_MEM_SIZE_FIRST_Pos) /*!< Bit mask of FIRST field. */
969 
970 /* Bits 29..0 : Total number of bytes to write to memory. */
971 #define CC_DOUT_DST_MEM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
972 #define CC_DOUT_DST_MEM_SIZE_SIZE_Msk (0x3FFFFFFFUL << CC_DOUT_DST_MEM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
973 
974 /* Register: CC_DOUT_DST_SRAM_ADDR */
975 /* Description: Data destination address in RNG SRAM. */
976 
977 /* Bits 31..0 : Destination address in RNG SRAM. */
978 #define CC_DOUT_DST_SRAM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
979 #define CC_DOUT_DST_SRAM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DOUT_DST_SRAM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
980 
981 /* Register: CC_DOUT_DST_SRAM_SIZE */
982 /* Description: The number of bytes to be written to RNG SRAM. */
983 
984 /* Bits 31..0 : Total number of bytes to write to RNG SRAM. */
985 #define CC_DOUT_DST_SRAM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
986 #define CC_DOUT_DST_SRAM_SIZE_SIZE_Msk (0xFFFFFFFFUL << CC_DOUT_DST_SRAM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
987 
988 /* Register: CC_DOUT_DOUT_DMA_SRAM_BUSY */
989 /* Description: Status register for DOUT DMA engine activity when accessing RNG SRAM. */
990 
991 /* Bit 0 : DOUT RNG SRAM DMA engine status. */
992 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
993 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
994 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Idle (0x0UL) /*!< DOUT RNG SRAM DMA engine is idle */
995 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Busy (0x1UL) /*!< DOUT RNG SRAM DMA engine is busy */
996 
997 /* Register: CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS */
998 /* Description: Configure the endianness of DOUT DMA transactions towards RNG SRAM. */
999 
1000 /* Bit 0 : Endianness of DOUT DMA transactions towards RNG SRAM. The default value is little-endian. */
1001 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */
1002 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
1003 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for RNG SRAM DMA transactions */
1004 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for RNG SRAM DMA transactions */
1005 
1006 /* Register: CC_DOUT_DOUT_READ_ALIGN */
1007 /* Description: Indication that the next CPU read from the DOUT_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). */
1008 
1009 /* Bit 0 : Next CPU read from the DOUT_BUFFER is the last word, and the remaining read aligned content can be flushed. */
1010 #define CC_DOUT_DOUT_READ_ALIGN_LAST_Pos (0UL) /*!< Position of LAST field. */
1011 #define CC_DOUT_DOUT_READ_ALIGN_LAST_Msk (0x1UL << CC_DOUT_DOUT_READ_ALIGN_LAST_Pos) /*!< Bit mask of LAST field. */
1012 #define CC_DOUT_DOUT_READ_ALIGN_LAST_Flush (0x1UL) /*!< Flush the remaining read aligned content. */
1013 
1014 /* Register: CC_DOUT_DOUT_FIFO_EMPTY */
1015 /* Description: Register indicating if DOUT FIFO is empty or if more data will come. */
1016 
1017 /* Bit 0 : DOUT FIFO status */
1018 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1019 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Pos) /*!< Bit mask of STATUS field. */
1020 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_NotEmpty (0x0UL) /*!< DOUT FIFO is not empty, and more data will come */
1021 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Empty (0x1UL) /*!< DOUT FIFO is empty */
1022 
1023 /* Register: CC_DOUT_DOUT_SW_RESET */
1024 /* Description: Reset the DOUT DMA engine. */
1025 
1026 /* Bit 0 : Writing any value to this address resets the DOUT DMA engine. The reset takes 4 CPU clock cycles to complete. */
1027 #define CC_DOUT_DOUT_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
1028 #define CC_DOUT_DOUT_SW_RESET_RESET_Msk (0x1UL << CC_DOUT_DOUT_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
1029 #define CC_DOUT_DOUT_SW_RESET_RESET_Enable (0x1UL) /*!< Reset DOUT DMA engine. */
1030 
1031 
1032 /* Peripheral: CC_HASH */
1033 /* Description: CRYPTOCELL HASH engine */
1034 
1035 /* Register: CC_HASH_HASH_H */
1036 /* Description: Description collection: HASH_H value registers. The initial HASH_H[0] register holds the least significant bits [31:0] of the value. */
1037 
1038 /* Bits 31..0 : Write the initial hash value before start of digest operation, and read the final hash value result after
1039           the digest operation has been completed. */
1040 #define CC_HASH_HASH_H_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1041 #define CC_HASH_HASH_H_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_H_VALUE_Pos) /*!< Bit mask of VALUE field. */
1042 
1043 /* Register: CC_HASH_HASH_PAD_AUTO */
1044 /* Description: Configure the HASH engine to automatically pad data at the end of the DMA transfer to complete the digest operation. */
1045 
1046 /* Bit 0 : Enable automatic padding in hardware. */
1047 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Pos (0UL) /*!< Position of HWPAD field. */
1048 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Msk (0x1UL << CC_HASH_HASH_PAD_AUTO_HWPAD_Pos) /*!< Bit mask of HWPAD field. */
1049 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Disable (0x0UL) /*!< Do not enable automatic hardware padding. */
1050 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Enable (0x1UL) /*!< Enable automatic hardware padding. */
1051 
1052 /* Register: CC_HASH_HASH_INIT_STATE */
1053 /* Description: Configure HASH engine initial state registers. */
1054 
1055 /* Bit 0 : Enable loading of data to initial state registers. Digest/IV for HASH/AES_MAC. */
1056 #define CC_HASH_HASH_INIT_STATE_LOAD_Pos (0UL) /*!< Position of LOAD field. */
1057 #define CC_HASH_HASH_INIT_STATE_LOAD_Msk (0x1UL << CC_HASH_HASH_INIT_STATE_LOAD_Pos) /*!< Bit mask of LOAD field. */
1058 #define CC_HASH_HASH_INIT_STATE_LOAD_Disable (0x0UL) /*!< Disable loading of data to initial state registers. */
1059 #define CC_HASH_HASH_INIT_STATE_LOAD_Enable (0x1UL) /*!< Enable loading of data to initial state registers. */
1060 
1061 /* Register: CC_HASH_HASH_VERSION */
1062 /* Description: HASH engine HW version */
1063 
1064 /* Bits 15..12 : Major version number */
1065 #define CC_HASH_HASH_VERSION_MAJOR_VERSION_NUMBER_Pos (12UL) /*!< Position of MAJOR_VERSION_NUMBER field. */
1066 #define CC_HASH_HASH_VERSION_MAJOR_VERSION_NUMBER_Msk (0xFUL << CC_HASH_HASH_VERSION_MAJOR_VERSION_NUMBER_Pos) /*!< Bit mask of MAJOR_VERSION_NUMBER field. */
1067 
1068 /* Bits 11..8 : Minor version number */
1069 #define CC_HASH_HASH_VERSION_MINOR_VERSION_NUMBER_Pos (8UL) /*!< Position of MINOR_VERSION_NUMBER field. */
1070 #define CC_HASH_HASH_VERSION_MINOR_VERSION_NUMBER_Msk (0xFUL << CC_HASH_HASH_VERSION_MINOR_VERSION_NUMBER_Pos) /*!< Bit mask of MINOR_VERSION_NUMBER field. */
1071 
1072 /* Bits 7..0 :   */
1073 #define CC_HASH_HASH_VERSION_PATCH_Pos (0UL) /*!< Position of PATCH field. */
1074 #define CC_HASH_HASH_VERSION_PATCH_Msk (0xFFUL << CC_HASH_HASH_VERSION_PATCH_Pos) /*!< Bit mask of PATCH field. */
1075 
1076 /* Register: CC_HASH_HASH_CONTROL */
1077 /* Description: Control the HASH engine behavior. */
1078 
1079 /* Bits 3..0 : Select HASH mode to execute */
1080 #define CC_HASH_HASH_CONTROL_MODE_Pos (0UL) /*!< Position of MODE field. */
1081 #define CC_HASH_HASH_CONTROL_MODE_Msk (0xFUL << CC_HASH_HASH_CONTROL_MODE_Pos) /*!< Bit mask of MODE field. */
1082 #define CC_HASH_HASH_CONTROL_MODE_SHA1 (0x1UL) /*!< Select SHA1 mode */
1083 #define CC_HASH_HASH_CONTROL_MODE_SHA256 (0x2UL) /*!< Select SHA256 mode */
1084 #define CC_HASH_HASH_CONTROL_MODE_SHA224 (0xAUL) /*!< Select SHA224 mode */
1085 
1086 /* Register: CC_HASH_HASH_PAD */
1087 /* Description: Enable the hardware padding feature of the HASH engine. */
1088 
1089 /* Bit 0 : Configure hardware padding feature. */
1090 #define CC_HASH_HASH_PAD_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1091 #define CC_HASH_HASH_PAD_ENABLE_Msk (0x1UL << CC_HASH_HASH_PAD_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1092 #define CC_HASH_HASH_PAD_ENABLE_Disable (0x0UL) /*!< Disable hardware padding feature. */
1093 #define CC_HASH_HASH_PAD_ENABLE_Enable (0x1UL) /*!< Enable hardware padding feature. */
1094 
1095 /* Register: CC_HASH_HASH_PAD_FORCE */
1096 /* Description: Force the hardware padding operation to trigger if the input data length is zero bytes. */
1097 
1098 /* Bit 2 : Trigger hardware padding operation. */
1099 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Pos (2UL) /*!< Position of ENABLE field. */
1100 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Msk (0x1UL << CC_HASH_HASH_PAD_FORCE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1101 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Disable (0x0UL) /*!< Do not force hardware padding to trigger. */
1102 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Enable (0x1UL) /*!< Force hardware padding to trigger. */
1103 
1104 /* Register: CC_HASH_HASH_CUR_LEN_0 */
1105 /* Description: Bits [31:0] of the number of bytes that have been digested so far. */
1106 
1107 /* Bits 31..0 : Bits [31:0] of current length of digested data in bytes. */
1108 #define CC_HASH_HASH_CUR_LEN_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1109 #define CC_HASH_HASH_CUR_LEN_0_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_CUR_LEN_0_VALUE_Pos) /*!< Bit mask of VALUE field. */
1110 
1111 /* Register: CC_HASH_HASH_CUR_LEN_1 */
1112 /* Description: Bits [63:32] of the number of bytes that have been digested so far. */
1113 
1114 /* Bits 31..0 : Bits [63:32] of current length of digested data in bytes. */
1115 #define CC_HASH_HASH_CUR_LEN_1_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1116 #define CC_HASH_HASH_CUR_LEN_1_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_CUR_LEN_1_VALUE_Pos) /*!< Bit mask of VALUE field. */
1117 
1118 /* Register: CC_HASH_HASH_HW_FLAGS */
1119 /* Description: Hardware configuration of the HASH engine. Reset value holds the supported features. */
1120 
1121 /* Bit 18 : If this flag is set, the engine include HASH to DOUT support. */
1122 #define CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Pos (18UL) /*!< Position of DUMP_HASH_TO_DOUT_EXISTS field. */
1123 #define CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Pos) /*!< Bit mask of DUMP_HASH_TO_DOUT_EXISTS field. */
1124 
1125 /* Bit 17 : If this flag is set, the engine include compare digest logic. */
1126 #define CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Pos (17UL) /*!< Position of HASH_COMPARE_EXISTS field. */
1127 #define CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Pos) /*!< Bit mask of HASH_COMPARE_EXISTS field. */
1128 
1129 /* Bit 16 : If this flag is set, the engine include SHA-256 support. */
1130 #define CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Pos (16UL) /*!< Position of SHA_256_EXISTS field. */
1131 #define CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Pos) /*!< Bit mask of SHA_256_EXISTS field. */
1132 
1133 /* Bit 15 : If this flag is set, the engine include HMAC support. */
1134 #define CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Pos (15UL) /*!< Position of HMAC_EXISTS field. */
1135 #define CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Pos) /*!< Bit mask of HMAC_EXISTS field. */
1136 
1137 /* Bit 14 : If this flag is set, the engine include MD5 support. */
1138 #define CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Pos (14UL) /*!< Position of MD5_EXISTS field. */
1139 #define CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Pos) /*!< Bit mask of MD5_EXISTS field. */
1140 
1141 /* Bit 13 : If this flag is set, the engine include pad block support. */
1142 #define CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Pos (13UL) /*!< Position of PAD_EXISTS field. */
1143 #define CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Pos) /*!< Bit mask of PAD_EXISTS field. */
1144 
1145 /* Bit 12 : If this flag is set, the engine include SHA-512 support. */
1146 #define CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Pos (12UL) /*!< Position of SHA_512_EXISTS field. */
1147 #define CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Pos) /*!< Bit mask of SHA_512_EXISTS field. */
1148 
1149 /* Bits 11..8 : Determine the granularity of word size. */
1150 #define CC_HASH_HASH_HW_FLAGS_DW_Pos (8UL) /*!< Position of DW field. */
1151 #define CC_HASH_HASH_HW_FLAGS_DW_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_DW_Pos) /*!< Bit mask of DW field. */
1152 #define CC_HASH_HASH_HW_FLAGS_DW_32Bits (0x0UL) /*!< 32 bits word data. */
1153 #define CC_HASH_HASH_HW_FLAGS_DW_64Bits (0x1UL) /*!< 64 bits word data. */
1154 
1155 /* Bits 7..4 : Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi. */
1156 #define CC_HASH_HASH_HW_FLAGS_CH_Pos (4UL) /*!< Position of CH field. */
1157 #define CC_HASH_HASH_HW_FLAGS_CH_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_CH_Pos) /*!< Bit mask of CH field. */
1158 #define CC_HASH_HASH_HW_FLAGS_CH_One (0x0UL) /*!< One Hi value is updated at a time. */
1159 #define CC_HASH_HASH_HW_FLAGS_CH_All (0x1UL) /*!< All Hi values are updated at the same time. */
1160 
1161 /* Bits 3..0 : Indicates the number of concurrent words the hash is using to compute signature. */
1162 #define CC_HASH_HASH_HW_FLAGS_CW_Pos (0UL) /*!< Position of CW field. */
1163 #define CC_HASH_HASH_HW_FLAGS_CW_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_CW_Pos) /*!< Bit mask of CW field. */
1164 #define CC_HASH_HASH_HW_FLAGS_CW_One (0x1UL) /*!< One concurrent word used by hash during signature generation */
1165 #define CC_HASH_HASH_HW_FLAGS_CW_Two (0x2UL) /*!< Two concurrent words used by hash during signature generation */
1166 
1167 /* Register: CC_HASH_HASH_SW_RESET */
1168 /* Description: Reset the HASH engine. */
1169 
1170 /* Bit 0 : Writing any value to this address resets the HASH engine. The reset takes 4 CPU clock cycles to complete. */
1171 #define CC_HASH_HASH_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
1172 #define CC_HASH_HASH_SW_RESET_RESET_Msk (0x1UL << CC_HASH_HASH_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
1173 #define CC_HASH_HASH_SW_RESET_RESET_Enable (0x1UL) /*!< Reset HASH engine. */
1174 
1175 /* Register: CC_HASH_HASH_ENDIANNESS */
1176 /* Description: Configure the endianness of HASH data and padding generation. */
1177 
1178 /* Bit 0 : Endianness of HASH data and padding generation. The default value is little-endian. */
1179 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */
1180 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_HASH_HASH_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
1181 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for data and padding */
1182 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for data and padding */
1183 
1184 
1185 /* Peripheral: CC_HOST_RGF */
1186 /* Description: CRYPTOCELL HOST register interface */
1187 
1188 /* Register: CC_HOST_RGF_IRR */
1189 /* Description: Interrupt request register. Each bit of this register holds the interrupt
1190         status of a single interrupt source. If corresponding IMR bit is
1191         unmasked, an interrupt is generated. */
1192 
1193 /* Bit 10 : The RNG interrupt status. */
1194 #define CC_HOST_RGF_IRR_RNG_INT_Pos (10UL) /*!< Position of RNG_INT field. */
1195 #define CC_HOST_RGF_IRR_RNG_INT_Msk (0x1UL << CC_HOST_RGF_IRR_RNG_INT_Pos) /*!< Bit mask of RNG_INT field. */
1196 
1197 /* Bit 9 : The PKA end of operation interrupt status. */
1198 #define CC_HOST_RGF_IRR_PKA_INT_Pos (9UL) /*!< Position of PKA_INT field. */
1199 #define CC_HOST_RGF_IRR_PKA_INT_Msk (0x1UL << CC_HOST_RGF_IRR_PKA_INT_Pos) /*!< Bit mask of PKA_INT field. */
1200 
1201 /* Bit 8 : The AHB error interrupt status. */
1202 #define CC_HOST_RGF_IRR_AHB_ERR_INT_Pos (8UL) /*!< Position of AHB_ERR_INT field. */
1203 #define CC_HOST_RGF_IRR_AHB_ERR_INT_Msk (0x1UL << CC_HOST_RGF_IRR_AHB_ERR_INT_Pos) /*!< Bit mask of AHB_ERR_INT field. */
1204 
1205 /* Bit 7 : The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to memory. */
1206 #define CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Pos (7UL) /*!< Position of DOUT_TO_MEM_INT field. */
1207 #define CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Msk (0x1UL << CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Pos) /*!< Bit mask of DOUT_TO_MEM_INT field. */
1208 
1209 /* Bit 6 : The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from memory to DIN buffer. */
1210 #define CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Pos (6UL) /*!< Position of MEM_TO_DIN_INT field. */
1211 #define CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Msk (0x1UL << CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Pos) /*!< Bit mask of MEM_TO_DIN_INT field. */
1212 
1213 /* Bit 5 : The DOUT to RNG SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to RNG SRAM. */
1214 #define CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Pos (5UL) /*!< Position of DOUT_TO_SRAM_INT field. */
1215 #define CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Msk (0x1UL << CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Pos) /*!< Bit mask of DOUT_TO_SRAM_INT field. */
1216 
1217 /* Bit 4 : The RNG SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from RNG SRAM to DIN buffer. */
1218 #define CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Pos (4UL) /*!< Position of SRAM_TO_DIN_INT field. */
1219 #define CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Msk (0x1UL << CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Pos) /*!< Bit mask of SRAM_TO_DIN_INT field. */
1220 
1221 /* Register: CC_HOST_RGF_IMR */
1222 /* Description: Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. */
1223 
1224 /* Bit 10 : The RNG interrupt mask. */
1225 #define CC_HOST_RGF_IMR_RNG_MASK_Pos (10UL) /*!< Position of RNG_MASK field. */
1226 #define CC_HOST_RGF_IMR_RNG_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_RNG_MASK_Pos) /*!< Bit mask of RNG_MASK field. */
1227 #define CC_HOST_RGF_IMR_RNG_MASK_IRQEnable (0x0UL) /*!< Do not mask RNG interrupt i.e. interrupt is generated */
1228 #define CC_HOST_RGF_IMR_RNG_MASK_IRQDisable (0x1UL) /*!< Mask RNG interrupt i.e. no interrupt is generated */
1229 
1230 /* Bit 9 : The PKA end of operation interrupt mask. */
1231 #define CC_HOST_RGF_IMR_PKA_MASK_Pos (9UL) /*!< Position of PKA_MASK field. */
1232 #define CC_HOST_RGF_IMR_PKA_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_PKA_MASK_Pos) /*!< Bit mask of PKA_MASK field. */
1233 #define CC_HOST_RGF_IMR_PKA_MASK_IRQEnable (0x0UL) /*!< Do not mask PKA end of operation interrupt i.e. interrupt is generated */
1234 #define CC_HOST_RGF_IMR_PKA_MASK_IRQDisable (0x1UL) /*!< Mask PKA end of operation interrupt i.e. no interrupt is generated */
1235 
1236 /* Bit 8 : The AHB error interrupt mask. */
1237 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_Pos (8UL) /*!< Position of AHB_ERR_MASK field. */
1238 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_AHB_ERR_MASK_Pos) /*!< Bit mask of AHB_ERR_MASK field. */
1239 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask AHB error interrupt i.e. interrupt is generated */
1240 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_IRQDisable (0x1UL) /*!< Mask AHB error interrupt i.e. no interrupt is generated */
1241 
1242 /* Bit 7 : The DOUT to memory DMA done interrupt mask. */
1243 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Pos (7UL) /*!< Position of DOUT_TO_MEM_MASK field. */
1244 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Pos) /*!< Bit mask of DOUT_TO_MEM_MASK field. */
1245 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_IRQEnable (0x0UL) /*!< Do not mask DOUT to memory DMA done interrupt i.e. interrupt is generated */
1246 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_IRQDisable (0x1UL) /*!< Mask DOUT to memory DMA done interrupt i.e. no interrupt is generated */
1247 
1248 /* Bit 6 : The memory to DIN DMA done interrupt mask. */
1249 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Pos (6UL) /*!< Position of MEM_TO_DIN_MASK field. */
1250 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Pos) /*!< Bit mask of MEM_TO_DIN_MASK field. */
1251 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_IRQEnable (0x0UL) /*!< Do not mask memory to DIN DMA done interrupt i.e. interrupt is generated */
1252 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_IRQDisable (0x1UL) /*!< Mask memory to DIN DMA done interrupt i.e. no interrupt is generated */
1253 
1254 /* Bit 5 : The DOUT to RNG SRAM DMA done interrupt mask. */
1255 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Pos (5UL) /*!< Position of DOUT_TO_SRAM_MASK field. */
1256 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Pos) /*!< Bit mask of DOUT_TO_SRAM_MASK field. */
1257 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_IRQEnable (0x0UL) /*!< Do not mask DOUT to RNG SRAM DMA done interrupt i.e. interrupt is generated */
1258 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_IRQDisable (0x1UL) /*!< Mask DOUT to RNG SRAM DMA done interrupt i.e. no interrupt is generated */
1259 
1260 /* Bit 4 : The RNG SRAM to DIN DMA done interrupt mask. */
1261 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Pos (4UL) /*!< Position of SRAM_TO_DIN_MASK field. */
1262 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Pos) /*!< Bit mask of SRAM_TO_DIN_MASK field. */
1263 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_IRQEnable (0x0UL) /*!< Do not mask RNG SRAM to DIN DMA done interrupt i.e. interrupt is generated */
1264 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_IRQDisable (0x1UL) /*!< Mask RNG SRAM to DIN DMA done interrupt i.e. no interrupt is generated */
1265 
1266 /* Register: CC_HOST_RGF_ICR */
1267 /* Description: Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR. */
1268 
1269 /* Bit 10 : The RNG interrupt clear. Register RNG_ISR in the RNG engine must be cleared before this interrupt can be cleared. */
1270 #define CC_HOST_RGF_ICR_RNG_CLEAR_Pos (10UL) /*!< Position of RNG_CLEAR field. */
1271 #define CC_HOST_RGF_ICR_RNG_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_RNG_CLEAR_Pos) /*!< Bit mask of RNG_CLEAR field. */
1272 
1273 /* Bit 9 : The PKA end of operation interrupt clear. */
1274 #define CC_HOST_RGF_ICR_PKA_CLEAR_Pos (9UL) /*!< Position of PKA_CLEAR field. */
1275 #define CC_HOST_RGF_ICR_PKA_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_PKA_CLEAR_Pos) /*!< Bit mask of PKA_CLEAR field. */
1276 
1277 /* Bit 8 : The AHB error interrupt clear. */
1278 #define CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Pos (8UL) /*!< Position of AHB_ERR_CLEAR field. */
1279 #define CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Pos) /*!< Bit mask of AHB_ERR_CLEAR field. */
1280 
1281 /* Bit 7 : The DOUT to memory DMA done interrupt clear. */
1282 #define CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Pos (7UL) /*!< Position of DOUT_TO_MEM_CLEAR field. */
1283 #define CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Pos) /*!< Bit mask of DOUT_TO_MEM_CLEAR field. */
1284 
1285 /* Bit 6 : The memory to DIN DMA done interrupt clear. */
1286 #define CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Pos (6UL) /*!< Position of MEM_TO_DIN_CLEAR field. */
1287 #define CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Pos) /*!< Bit mask of MEM_TO_DIN_CLEAR field. */
1288 
1289 /* Bit 5 : The DOUT to RNG SRAM DMA done interrupt clear. */
1290 #define CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Pos (5UL) /*!< Position of DOUT_TO_SRAM_CLEAR field. */
1291 #define CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Pos) /*!< Bit mask of DOUT_TO_SRAM_CLEAR field. */
1292 
1293 /* Bit 4 : The RNG SRAM to DIN DMA done interrupt clear. */
1294 #define CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Pos (4UL) /*!< Position of SRAM_TO_DIN_CLEAR field. */
1295 #define CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Pos) /*!< Bit mask of SRAM_TO_DIN_CLEAR field. */
1296 
1297 /* Register: CC_HOST_RGF_ENDIANNESS */
1298 /* Description: This register defines the endianness of the Host-accessible registers, and can only be written once. */
1299 
1300 /* Bit 15 : DIN read word endianness. */
1301 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Pos (15UL) /*!< Position of DIN_RD_WBG field. */
1302 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Pos) /*!< Bit mask of DIN_RD_WBG field. */
1303 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_LittleEndian (0x0UL) /*!< Configure DIN read word as little-endian */
1304 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_BigEndian (0x1UL) /*!< Configure DIN read word as big-endian */
1305 
1306 /* Bit 11 : DOUT write word endianness. */
1307 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Pos (11UL) /*!< Position of DOUT_WR_WBG field. */
1308 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Pos) /*!< Bit mask of DOUT_WR_WBG field. */
1309 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_LittleEndian (0x0UL) /*!< Configure DOUT write word as little-endian */
1310 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_BigEndian (0x1UL) /*!< Configure DOUT write word as big-endian */
1311 
1312 /* Bit 7 : DIN read endianness. */
1313 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Pos (7UL) /*!< Position of DIN_RD_BG field. */
1314 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Pos) /*!< Bit mask of DIN_RD_BG field. */
1315 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_LittleEndian (0x0UL) /*!< Configure DIN read as little-endian */
1316 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_BigEndian (0x1UL) /*!< Configure DIN read as big-endian */
1317 
1318 /* Bit 3 : DOUT write endianness. */
1319 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Pos (3UL) /*!< Position of DOUT_WR_BG field. */
1320 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Pos) /*!< Bit mask of DOUT_WR_BG field. */
1321 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_LittleEndian (0x0UL) /*!< Configure DOUT write as little-endian */
1322 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_BigEndian (0x1UL) /*!< Configure DOUT write as big-endian */
1323 
1324 /* Register: CC_HOST_RGF_HOST_SIGNATURE */
1325 /* Description: This register holds the CRYPTOCELL subsystem signature. See reset value. */
1326 
1327 /* Bits 31..0 : Fixed-value identification signature used by host driver to verify CRYPTOCELL presence at this address. */
1328 #define CC_HOST_RGF_HOST_SIGNATURE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1329 #define CC_HOST_RGF_HOST_SIGNATURE_VALUE_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_SIGNATURE_VALUE_Pos) /*!< Bit mask of VALUE field. */
1330 
1331 /* Register: CC_HOST_RGF_HOST_BOOT */
1332 /* Description: Hardware configuration of the CRYPTOCELL subsystem. Reset value holds the supported features. */
1333 
1334 /* Bit 30 : If this flag is set, the AES engine is present */
1335 #define CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Pos (30UL) /*!< Position of AES_EXISTS_LOCAL field. */
1336 #define CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_EXISTS_LOCAL field. */
1337 
1338 /* Bit 29 : If this flag is set, the AES engine only support encryption */
1339 #define CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Pos (29UL) /*!< Position of ONLY_ENCRYPT_LOCAL field. */
1340 #define CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Pos) /*!< Bit mask of ONLY_ENCRYPT_LOCAL field. */
1341 
1342 /* Bit 28 : If this flag is set, the AES engine supports 192/256 bits key sizes */
1343 #define CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Pos (28UL) /*!< Position of SUPPORT_256_192_KEY_LOCAL field. */
1344 #define CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Pos) /*!< Bit mask of SUPPORT_256_192_KEY_LOCAL field. */
1345 
1346 /* Bit 27 : If this flag is set, the AES engine supports tunneling operations */
1347 #define CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Pos (27UL) /*!< Position of TUNNELING_ENB_LOCAL field. */
1348 #define CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Pos) /*!< Bit mask of TUNNELING_ENB_LOCAL field. */
1349 
1350 /* Bit 26 : If this flag is set, the AES engine data input support byte size resolution */
1351 #define CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Pos (26UL) /*!< Position of AES_DIN_BYTE_RESOLUTION_LOCAL field. */
1352 #define CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Pos) /*!< Bit mask of AES_DIN_BYTE_RESOLUTION_LOCAL field. */
1353 
1354 /* Bit 25 : If this flag is set, AES CTR mode is supported */
1355 #define CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Pos (25UL) /*!< Position of CTR_EXISTS_LOCAL field. */
1356 #define CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Pos) /*!< Bit mask of CTR_EXISTS_LOCAL field. */
1357 
1358 /* Bit 24 : If this flag is set, AES XEX mode is supported */
1359 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Pos (24UL) /*!< Position of AES_XEX_EXISTS_LOCAL field. */
1360 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_XEX_EXISTS_LOCAL field. */
1361 
1362 /* Bit 23 : If this flag is set, AES XEX mode T-value calculation in HW is supported */
1363 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Pos (23UL) /*!< Position of AES_XEX_HW_T_CALC_LOCAL field. */
1364 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Pos) /*!< Bit mask of AES_XEX_HW_T_CALC_LOCAL field. */
1365 
1366 /* Bit 22 : If this flag is set, AES CCM mode is supported */
1367 #define CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Pos (22UL) /*!< Position of AES_CCM_EXISTS_LOCAL field. */
1368 #define CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_CCM_EXISTS_LOCAL field. */
1369 
1370 /* Bit 21 : If this flag is set, AES CMAC mode is supported */
1371 #define CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Pos (21UL) /*!< Position of AES_CMAC_EXISTS_LOCAL field. */
1372 #define CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_CMAC_EXISTS_LOCAL field. */
1373 
1374 /* Bit 20 : If this flag is set, AES XCBC-MAC mode is supported */
1375 #define CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Pos (20UL) /*!< Position of AES_XCBC_MAC_EXISTS_LOCAL field. */
1376 #define CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_XCBC_MAC_EXISTS_LOCAL field. */
1377 
1378 /* Bit 19 : If this flag is set, the DES engine is present */
1379 #define CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Pos (19UL) /*!< Position of DES_EXISTS_LOCAL field. */
1380 #define CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Pos) /*!< Bit mask of DES_EXISTS_LOCAL field. */
1381 
1382 /* Bit 18 : If this flag is set, the C2 engine is present */
1383 #define CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Pos (18UL) /*!< Position of C2_EXISTS_LOCAL field. */
1384 #define CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Pos) /*!< Bit mask of C2_EXISTS_LOCAL field. */
1385 
1386 /* Bit 17 : If this flag is set, the HASH engine is present */
1387 #define CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Pos (17UL) /*!< Position of HASH_EXISTS_LOCAL field. */
1388 #define CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Pos) /*!< Bit mask of HASH_EXISTS_LOCAL field. */
1389 
1390 /* Bit 16 : If this flag is set, the HASH engine supports MD5 */
1391 #define CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Pos (16UL) /*!< Position of MD5_PRSNT_LOCAL field. */
1392 #define CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Pos) /*!< Bit mask of MD5_PRSNT_LOCAL field. */
1393 
1394 /* Bit 15 : If this flag is set, the HASH engine supports SHA256 */
1395 #define CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Pos (15UL) /*!< Position of SHA_256_PRSNT_LOCAL field. */
1396 #define CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Pos) /*!< Bit mask of SHA_256_PRSNT_LOCAL field. */
1397 
1398 /* Bit 14 : If this flag is set, the HASH engine supports SHA512 */
1399 #define CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Pos (14UL) /*!< Position of SHA_512_PRSNT_LOCAL field. */
1400 #define CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Pos) /*!< Bit mask of SHA_512_PRSNT_LOCAL field. */
1401 
1402 /* Bit 13 : If this flag is set, the RC4 engine is present */
1403 #define CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Pos (13UL) /*!< Position of RC4_EXISTS_LOCAL field. */
1404 #define CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Pos) /*!< Bit mask of RC4_EXISTS_LOCAL field. */
1405 
1406 /* Bit 12 : If this flag is set, the PKA engine is present */
1407 #define CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Pos (12UL) /*!< Position of PKA_EXISTS_LOCAL field. */
1408 #define CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Pos) /*!< Bit mask of PKA_EXISTS_LOCAL field. */
1409 
1410 /* Bit 11 : If this flag is set, the RNG engine is present */
1411 #define CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Pos (11UL) /*!< Position of RNG_EXISTS_LOCAL field. */
1412 #define CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Pos) /*!< Bit mask of RNG_EXISTS_LOCAL field. */
1413 
1414 /* Bit 10 : If this flag is set, PAU is supported */
1415 #define CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Pos (10UL) /*!< Position of PAU_EXISTS_LOCAL field. */
1416 #define CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Pos) /*!< Bit mask of PAU_EXISTS_LOCAL field. */
1417 
1418 /* Bit 9 : If this flag is set, Descriptors are supported */
1419 #define CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Pos (9UL) /*!< Position of DSCRPTR_EXISTS_LOCAL field. */
1420 #define CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Pos) /*!< Bit mask of DSCRPTR_EXISTS_LOCAL field. */
1421 
1422 /* Bits 8..6 : SRAM size */
1423 #define CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Pos (6UL) /*!< Position of SRAM_SIZE_LOCAL field. */
1424 #define CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Msk (0x7UL << CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Pos) /*!< Bit mask of SRAM_SIZE_LOCAL field. */
1425 
1426 /* Bit 5 : If this flag is set, RKEK ECC is supported */
1427 #define CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Pos (5UL) /*!< Position of RKEK_ECC_EXISTS_LOCAL_N field. */
1428 #define CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Pos) /*!< Bit mask of RKEK_ECC_EXISTS_LOCAL_N field. */
1429 
1430 /* Bit 3 : If this flag is set, external secure memory is supported */
1431 #define CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Pos (3UL) /*!< Position of EXT_MEM_SECURED_LOCAL field. */
1432 #define CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Pos) /*!< Bit mask of EXT_MEM_SECURED_LOCAL field. */
1433 
1434 /* Bit 2 : If this flag is set, HASH in fuses is supported */
1435 #define CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Pos (2UL) /*!< Position of HASH_IN_FUSES_LOCAL field. */
1436 #define CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Pos) /*!< Bit mask of HASH_IN_FUSES_LOCAL field. */
1437 
1438 /* Bit 1 : If this flag is set, large RKEK is supported */
1439 #define CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Pos (1UL) /*!< Position of LARGE_RKEK_LOCAL field. */
1440 #define CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Pos) /*!< Bit mask of LARGE_RKEK_LOCAL field. */
1441 
1442 /* Bit 0 : If this flag is set, full power gating is implemented */
1443 #define CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Pos (0UL) /*!< Position of POWER_GATING_EXISTS_LOCAL field. */
1444 #define CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Pos) /*!< Bit mask of POWER_GATING_EXISTS_LOCAL field. */
1445 
1446 /* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */
1447 /* Description: AES hardware key select. */
1448 
1449 /* Bits 1..0 : Select the source of the HW key that is used by the AES engine */
1450 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */
1451 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */
1452 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0x0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */
1453 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (0x1UL) /*!< Use hard-coded RTL key K_PRTL */
1454 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (0x2UL) /*!< Use provided session key */
1455 
1456 /* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */
1457 /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
1458 
1459 /* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
1460 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */
1461 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */
1462 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0x0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */
1463 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (0x1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */
1464 
1465 /* Register: CC_HOST_RGF_HOST_IOT_KDR0 */
1466 /* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */
1467 
1468 /* Bits 31..0 : This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. Write: K_DR bits 31:0. */
1469 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */
1470 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */
1471 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_NotRetained (0x00000000UL) /*!< Read: 128 bits K_DR key value is not yet retained in the CRYPTOCELL AO power domain. */
1472 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Retained (0x00000001UL) /*!< Read: 128 bits K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */
1473 
1474 /* Register: CC_HOST_RGF_HOST_IOT_KDR1 */
1475 /* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
1476 
1477 /* Bits 31..0 : K_DR bits 63:32 */
1478 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */
1479 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */
1480 
1481 /* Register: CC_HOST_RGF_HOST_IOT_KDR2 */
1482 /* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
1483 
1484 /* Bits 31..0 : K_DR bits 95:64 */
1485 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */
1486 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */
1487 
1488 /* Register: CC_HOST_RGF_HOST_IOT_KDR3 */
1489 /* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
1490 
1491 /* Bits 31..0 : K_DR bits 127:96 */
1492 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */
1493 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */
1494 
1495 /* Register: CC_HOST_RGF_HOST_IOT_LCS */
1496 /* Description: Controls life-cycle state (LCS) for CRYPTOCELL subsystem */
1497 
1498 /* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */
1499 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */
1500 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */
1501 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0x0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */
1502 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (0x1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */
1503 
1504 /* Bits 2..0 : Life-cycle state value. This field is write-once per reset. */
1505 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */
1506 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */
1507 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_DebugEnable (0x0UL) /*!< CC310 operates in debug mode */
1508 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (0x2UL) /*!< CC310 operates in secure mode */
1509 
1510 
1511 /* Peripheral: CC_MISC */
1512 /* Description: CRYPTOCELL MISC interface */
1513 
1514 /* Register: CC_MISC_AES_CLK */
1515 /* Description: Clock control for the AES engine. */
1516 
1517 /* Bit 0 : Enables clock for the AES engine. */
1518 #define CC_MISC_AES_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1519 #define CC_MISC_AES_CLK_ENABLE_Msk (0x1UL << CC_MISC_AES_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1520 #define CC_MISC_AES_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the AES engine. */
1521 #define CC_MISC_AES_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the AES engine. */
1522 
1523 /* Register: CC_MISC_HASH_CLK */
1524 /* Description: Clock control for the HASH engine. */
1525 
1526 /* Bit 0 : Enables clock for the HASH engine. */
1527 #define CC_MISC_HASH_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1528 #define CC_MISC_HASH_CLK_ENABLE_Msk (0x1UL << CC_MISC_HASH_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1529 #define CC_MISC_HASH_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the HASH engine. */
1530 #define CC_MISC_HASH_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the HASH engine. */
1531 
1532 /* Register: CC_MISC_PKA_CLK */
1533 /* Description: Clock control for the PKA engine. */
1534 
1535 /* Bit 0 : Enables clock for the PKA engine. */
1536 #define CC_MISC_PKA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1537 #define CC_MISC_PKA_CLK_ENABLE_Msk (0x1UL << CC_MISC_PKA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1538 #define CC_MISC_PKA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the PKA engine. */
1539 #define CC_MISC_PKA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the PKA engine. */
1540 
1541 /* Register: CC_MISC_DMA_CLK */
1542 /* Description: Clock control for the DMA engines. */
1543 
1544 /* Bit 0 : Enables clock for the DMA engines. */
1545 #define CC_MISC_DMA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1546 #define CC_MISC_DMA_CLK_ENABLE_Msk (0x1UL << CC_MISC_DMA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1547 #define CC_MISC_DMA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the DMA engines. */
1548 #define CC_MISC_DMA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the DMA engines. */
1549 
1550 /* Register: CC_MISC_CLK_STATUS */
1551 /* Description: CRYPTOCELL clocks status register. */
1552 
1553 /* Bit 8 : Status of DMA engines clock. */
1554 #define CC_MISC_CLK_STATUS_DMA_CLK_Pos (8UL) /*!< Position of DMA_CLK field. */
1555 #define CC_MISC_CLK_STATUS_DMA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_DMA_CLK_Pos) /*!< Bit mask of DMA_CLK field. */
1556 #define CC_MISC_CLK_STATUS_DMA_CLK_Disabled (0x0UL) /*!< Clocks for DMA engines are disabled */
1557 #define CC_MISC_CLK_STATUS_DMA_CLK_Enabled (0x1UL) /*!< Clocks for DMA engines are enabled */
1558 
1559 /* Bit 7 : Status of CHACHA engine clock. */
1560 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Pos (7UL) /*!< Position of CHACHA_CLK field. */
1561 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_CHACHA_CLK_Pos) /*!< Bit mask of CHACHA_CLK field. */
1562 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Disabled (0x0UL) /*!< Clock for CHACHA engine is disabled */
1563 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Enabled (0x1UL) /*!< Clock for CHACHA engine is enabled */
1564 
1565 /* Bit 3 : Status of PKA engine clock. */
1566 #define CC_MISC_CLK_STATUS_PKA_CLK_Pos (3UL) /*!< Position of PKA_CLK field. */
1567 #define CC_MISC_CLK_STATUS_PKA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_PKA_CLK_Pos) /*!< Bit mask of PKA_CLK field. */
1568 #define CC_MISC_CLK_STATUS_PKA_CLK_Disabled (0x0UL) /*!< Clock for PKA engine is disabled */
1569 #define CC_MISC_CLK_STATUS_PKA_CLK_Enabled (0x1UL) /*!< Clock for PKA engine is enabled */
1570 
1571 /* Bit 2 : Status of HASH engine clock. */
1572 #define CC_MISC_CLK_STATUS_HASH_CLK_Pos (2UL) /*!< Position of HASH_CLK field. */
1573 #define CC_MISC_CLK_STATUS_HASH_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_HASH_CLK_Pos) /*!< Bit mask of HASH_CLK field. */
1574 #define CC_MISC_CLK_STATUS_HASH_CLK_Disabled (0x0UL) /*!< Clock for HASH engine is disabled */
1575 #define CC_MISC_CLK_STATUS_HASH_CLK_Enabled (0x1UL) /*!< Clock for HASH engine is enabled */
1576 
1577 /* Bit 0 : Status of AES engine clock. */
1578 #define CC_MISC_CLK_STATUS_AES_CLK_Pos (0UL) /*!< Position of AES_CLK field. */
1579 #define CC_MISC_CLK_STATUS_AES_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_AES_CLK_Pos) /*!< Bit mask of AES_CLK field. */
1580 #define CC_MISC_CLK_STATUS_AES_CLK_Disabled (0x0UL) /*!< Clock for AES engine is disabled */
1581 #define CC_MISC_CLK_STATUS_AES_CLK_Enabled (0x1UL) /*!< Clock for AES engine is enabled */
1582 
1583 /* Register: CC_MISC_CHACHA_CLK */
1584 /* Description: Clock control for the CHACHA engine. */
1585 
1586 /* Bit 0 : Enables clock for the CHACHA engine. */
1587 #define CC_MISC_CHACHA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1588 #define CC_MISC_CHACHA_CLK_ENABLE_Msk (0x1UL << CC_MISC_CHACHA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1589 #define CC_MISC_CHACHA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the CHACHA engine. */
1590 #define CC_MISC_CHACHA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the CHACHA engine. */
1591 
1592 
1593 /* Peripheral: CC_PKA */
1594 /* Description: CRYPTOCELL PKA engine */
1595 
1596 /* Register: CC_PKA_MEMORY_MAP */
1597 /* Description: Description collection: Register for mapping the virtual register R[n] to a physical address in the PKA SRAM. */
1598 
1599 /* Bits 9..1 : The physical word address used for the virtual register. */
1600 #define CC_PKA_MEMORY_MAP_ADDR_Pos (1UL) /*!< Position of ADDR field. */
1601 #define CC_PKA_MEMORY_MAP_ADDR_Msk (0x1FFUL << CC_PKA_MEMORY_MAP_ADDR_Pos) /*!< Bit mask of ADDR field. */
1602 
1603 /* Register: CC_PKA_OPCODE */
1604 /* Description: Operation code to be executed by the PKA engine. Writing to this register triggers the PKA operation. */
1605 
1606 /* Bits 31..27 : Operation code to be executed by the PKA engine */
1607 #define CC_PKA_OPCODE_OPCODE_Pos (27UL) /*!< Position of OPCODE field. */
1608 #define CC_PKA_OPCODE_OPCODE_Msk (0x1FUL << CC_PKA_OPCODE_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
1609 #define CC_PKA_OPCODE_OPCODE_Terminate (0x00UL) /*!< Terminate operation */
1610 #define CC_PKA_OPCODE_OPCODE_AddInc (0x04UL) /*!< Add or Increment */
1611 #define CC_PKA_OPCODE_OPCODE_SubDecNeg (0x05UL) /*!< Subtract, Decrement, or Negate */
1612 #define CC_PKA_OPCODE_OPCODE_ModAddInc (0x06UL) /*!< Modular Add or Modular Increment */
1613 #define CC_PKA_OPCODE_OPCODE_ModSubDecNeg (0x07UL) /*!< Modular Subtract, Modular Decrement, or Modular Negate */
1614 #define CC_PKA_OPCODE_OPCODE_ANDTST0CLR0 (0x08UL) /*!< Perform AND, test, or clear */
1615 #define CC_PKA_OPCODE_OPCODE_ORCOPYSET0 (0x09UL) /*!< Perform OR, copy, or set bits */
1616 #define CC_PKA_OPCODE_OPCODE_XORFLP0INVCMP (0x0AUL) /*!< Perform XOR, flip bits, invert, or compare */
1617 #define CC_PKA_OPCODE_OPCODE_SHR0 (0x0CUL) /*!< Shift right 0 operation */
1618 #define CC_PKA_OPCODE_OPCODE_SHR1 (0x0DUL) /*!< Shift right 1 operation */
1619 #define CC_PKA_OPCODE_OPCODE_SHL0 (0x0EUL) /*!< Shift left 0 operation */
1620 #define CC_PKA_OPCODE_OPCODE_SHL1 (0x0FUL) /*!< Shift left 1 operation */
1621 #define CC_PKA_OPCODE_OPCODE_MulLow (0x10UL) /*!< Multiply low operation */
1622 #define CC_PKA_OPCODE_OPCODE_ModMul (0x11UL) /*!< Modular multiply operation */
1623 #define CC_PKA_OPCODE_OPCODE_ModMulN (0x12UL) /*!< Modular multiply N operation */
1624 #define CC_PKA_OPCODE_OPCODE_ModExp (0x13UL) /*!< Modular exponentiation operation */
1625 #define CC_PKA_OPCODE_OPCODE_Division (0x14UL) /*!< Division operation */
1626 #define CC_PKA_OPCODE_OPCODE_ModInv (0x15UL) /*!< Modular inversion operation */
1627 #define CC_PKA_OPCODE_OPCODE_ModDiv (0x16UL) /*!< Modular division operation */
1628 #define CC_PKA_OPCODE_OPCODE_MulHigh (0x17UL) /*!< Multiply high operation */
1629 #define CC_PKA_OPCODE_OPCODE_ModMLAC (0x18UL) /*!< Modular multiplication acceleration */
1630 #define CC_PKA_OPCODE_OPCODE_ModMLACNR (0x19UL) /*!< Modular multiplication acceleration where final reduction is omitted */
1631 #define CC_PKA_OPCODE_OPCODE_Reduction (0x1BUL) /*!< Reduction operation */
1632 
1633 /* Bits 26..24 : The length of the operands. This value serves as an PKA length register index. E.g.: if LEN field value is set to 0, PKA_L[0] holds the size of the operands. */
1634 #define CC_PKA_OPCODE_LEN_Pos (24UL) /*!< Position of LEN field. */
1635 #define CC_PKA_OPCODE_LEN_Msk (0x7UL << CC_PKA_OPCODE_LEN_Pos) /*!< Bit mask of LEN field. */
1636 
1637 /* Bit 23 : This field controls the interpretation of REG_A. */
1638 #define CC_PKA_OPCODE_CONST_A_Pos (23UL) /*!< Position of CONST_A field. */
1639 #define CC_PKA_OPCODE_CONST_A_Msk (0x1UL << CC_PKA_OPCODE_CONST_A_Pos) /*!< Bit mask of CONST_A field. */
1640 #define CC_PKA_OPCODE_CONST_A_Register (0x0UL) /*!< REG_A is intepreted as a register index. */
1641 #define CC_PKA_OPCODE_CONST_A_Constant (0x1UL) /*!< REG_A is intepreted as a constant. */
1642 
1643 /* Bits 22..18 : Operand A virtual register index. */
1644 #define CC_PKA_OPCODE_REG_A_Pos (18UL) /*!< Position of REG_A field. */
1645 #define CC_PKA_OPCODE_REG_A_Msk (0x1FUL << CC_PKA_OPCODE_REG_A_Pos) /*!< Bit mask of REG_A field. */
1646 
1647 /* Bit 17 : This field controls the interpretation of REG_B. */
1648 #define CC_PKA_OPCODE_CONST_B_Pos (17UL) /*!< Position of CONST_B field. */
1649 #define CC_PKA_OPCODE_CONST_B_Msk (0x1UL << CC_PKA_OPCODE_CONST_B_Pos) /*!< Bit mask of CONST_B field. */
1650 #define CC_PKA_OPCODE_CONST_B_Register (0x0UL) /*!< REG_B is intepreted as a register index. */
1651 #define CC_PKA_OPCODE_CONST_B_Constant (0x1UL) /*!< REG_B is intepreted as a constant. */
1652 
1653 /* Bits 16..12 : Operand B virtual register index. */
1654 #define CC_PKA_OPCODE_REG_B_Pos (12UL) /*!< Position of REG_B field. */
1655 #define CC_PKA_OPCODE_REG_B_Msk (0x1FUL << CC_PKA_OPCODE_REG_B_Pos) /*!< Bit mask of REG_B field. */
1656 
1657 /* Bit 11 : This field controls the interpretation of REG_R. */
1658 #define CC_PKA_OPCODE_DISCARD_R_Pos (11UL) /*!< Position of DISCARD_R field. */
1659 #define CC_PKA_OPCODE_DISCARD_R_Msk (0x1UL << CC_PKA_OPCODE_DISCARD_R_Pos) /*!< Bit mask of DISCARD_R field. */
1660 #define CC_PKA_OPCODE_DISCARD_R_Register (0x0UL) /*!< REG_R is intepreted as a register index. */
1661 #define CC_PKA_OPCODE_DISCARD_R_Discard (0x1UL) /*!< Result is discarded. */
1662 
1663 /* Bits 10..6 : Result register virtual register index. */
1664 #define CC_PKA_OPCODE_REG_R_Pos (6UL) /*!< Position of REG_R field. */
1665 #define CC_PKA_OPCODE_REG_R_Msk (0x1FUL << CC_PKA_OPCODE_REG_R_Pos) /*!< Bit mask of REG_R field. */
1666 
1667 /* Bits 5..0 : Holds the operation tag or the operand C virtual register index. */
1668 #define CC_PKA_OPCODE_TAG_Pos (0UL) /*!< Position of TAG field. */
1669 #define CC_PKA_OPCODE_TAG_Msk (0x3FUL << CC_PKA_OPCODE_TAG_Pos) /*!< Bit mask of TAG field. */
1670 
1671 /* Register: CC_PKA_N_NP_T0_T1_ADDR */
1672 /* Description: This register defines the N, Np, T0, and T1 virtual register index. */
1673 
1674 /* Bits 19..15 : Temporary register 1 virtual register index. Default is R31. */
1675 #define CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Pos (15UL) /*!< Position of T1_VIRTUAL_ADDR field. */
1676 #define CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Pos) /*!< Bit mask of T1_VIRTUAL_ADDR field. */
1677 
1678 /* Bits 14..10 : Temporary register 0 virtual register index. Default is R30. */
1679 #define CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Pos (10UL) /*!< Position of T0_VIRTUAL_ADDR field. */
1680 #define CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Pos) /*!< Bit mask of T0_VIRTUAL_ADDR field. */
1681 
1682 /* Bits 9..5 : Register Np virtual register index. Default is R1. */
1683 #define CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Pos (5UL) /*!< Position of NP_VIRTUAL_ADDR field. */
1684 #define CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Pos) /*!< Bit mask of NP_VIRTUAL_ADDR field. */
1685 
1686 /* Bits 4..0 : Register N virtual register index. Default is R0. */
1687 #define CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Pos (0UL) /*!< Position of N_VIRTUAL_ADDR field. */
1688 #define CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Pos) /*!< Bit mask of N_VIRTUAL_ADDR field. */
1689 
1690 /* Register: CC_PKA_PKA_STATUS */
1691 /* Description: This register holds the status for the PKA pipeline. */
1692 
1693 /* Bits 20..16 : Opcode of the last operation */
1694 #define CC_PKA_PKA_STATUS_OPCODE_Pos (16UL) /*!< Position of OPCODE field. */
1695 #define CC_PKA_PKA_STATUS_OPCODE_Msk (0x1FUL << CC_PKA_PKA_STATUS_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
1696 
1697 /* Bit 15 : Indicates the modular inverse of zero. */
1698 #define CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Pos (15UL) /*!< Position of MODINV_OF_ZERO field. */
1699 #define CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Pos) /*!< Bit mask of MODINV_OF_ZERO field. */
1700 
1701 /* Bit 14 : Indication if the division is done by zero. */
1702 #define CC_PKA_PKA_STATUS_DIV_BY_ZERO_Pos (14UL) /*!< Position of DIV_BY_ZERO field. */
1703 #define CC_PKA_PKA_STATUS_DIV_BY_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_DIV_BY_ZERO_Pos) /*!< Bit mask of DIV_BY_ZERO field. */
1704 
1705 /* Bit 13 : Modular overflow flag. */
1706 #define CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Pos (13UL) /*!< Position of ALU_MODOVRFLW field. */
1707 #define CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Pos) /*!< Bit mask of ALU_MODOVRFLW field. */
1708 
1709 /* Bit 12 : Indicates if the result of ALU OUT is zero. */
1710 #define CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Pos (12UL) /*!< Position of ALU_OUT_ZERO field. */
1711 #define CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Pos) /*!< Bit mask of ALU_OUT_ZERO field. */
1712 
1713 /* Bit 11 : Indicates the last subtraction operation sign. */
1714 #define CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Pos (11UL) /*!< Position of ALU_SUB_IS_ZERO field. */
1715 #define CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Pos) /*!< Bit mask of ALU_SUB_IS_ZERO field. */
1716 
1717 /* Bit 10 : Holds the carry of the last modular operation. */
1718 #define CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Pos (10UL) /*!< Position of ALU_CARRY_MOD field. */
1719 #define CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Pos) /*!< Bit mask of ALU_CARRY_MOD field. */
1720 
1721 /* Bit 9 : Holds the carry of the last ALU operation. */
1722 #define CC_PKA_PKA_STATUS_ALU_CARRY_Pos (9UL) /*!< Position of ALU_CARRY field. */
1723 #define CC_PKA_PKA_STATUS_ALU_CARRY_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_CARRY_Pos) /*!< Bit mask of ALU_CARRY field. */
1724 
1725 /* Bit 8 : Indicates the MSB sign of the last operation. */
1726 #define CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Pos (8UL) /*!< Position of ALU_SIGN_OUT field. */
1727 #define CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Pos) /*!< Bit mask of ALU_SIGN_OUT field. */
1728 
1729 /* Bits 7..4 : The least significant 4-bits of the operand updated in shift operation. */
1730 #define CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Pos (4UL) /*!< Position of ALU_LSB_4BITS field. */
1731 #define CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Msk (0xFUL << CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Pos) /*!< Bit mask of ALU_LSB_4BITS field. */
1732 
1733 /* Bits 3..0 : The most significant 4-bits of the operand updated in shift operation. */
1734 #define CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Pos (0UL) /*!< Position of ALU_MSB_4BITS field. */
1735 #define CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Msk (0xFUL << CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Pos) /*!< Bit mask of ALU_MSB_4BITS field. */
1736 
1737 /* Register: CC_PKA_PKA_SW_RESET */
1738 /* Description: Reset the PKA engine. */
1739 
1740 /* Bit 0 : Writing any value to this address resets the PKA engine. The reset takes 4 CPU clock cycles to complete. */
1741 #define CC_PKA_PKA_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
1742 #define CC_PKA_PKA_SW_RESET_RESET_Msk (0x1UL << CC_PKA_PKA_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
1743 #define CC_PKA_PKA_SW_RESET_RESET_Enable (0x1UL) /*!< Reset PKA engine. */
1744 
1745 /* Register: CC_PKA_PKA_L */
1746 /* Description: Description collection: This register holds the operands bit size. */
1747 
1748 /* Bits 12..0 : Operand bit size. */
1749 #define CC_PKA_PKA_L_OpSize_Pos (0UL) /*!< Position of OpSize field. */
1750 #define CC_PKA_PKA_L_OpSize_Msk (0x1FFFUL << CC_PKA_PKA_L_OpSize_Pos) /*!< Bit mask of OpSize field. */
1751 
1752 /* Register: CC_PKA_PKA_PIPE */
1753 /* Description: Status register indicating if the PKA pipeline is ready to receive a new OPCODE. */
1754 
1755 /* Bit 0 : PKA pipeline status. */
1756 #define CC_PKA_PKA_PIPE_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1757 #define CC_PKA_PKA_PIPE_STATUS_Msk (0x1UL << CC_PKA_PKA_PIPE_STATUS_Pos) /*!< Bit mask of STATUS field. */
1758 #define CC_PKA_PKA_PIPE_STATUS_NotReady (0x0UL) /*!< PKA pipeline is not ready for a new OPCODE */
1759 #define CC_PKA_PKA_PIPE_STATUS_Ready (0x1UL) /*!< PKA pipeline is ready for a new OPCODE */
1760 
1761 /* Register: CC_PKA_PKA_DONE */
1762 /* Description: Status register indicating if the PKA operation has been completed. */
1763 
1764 /* Bit 0 : PKA operation status. */
1765 #define CC_PKA_PKA_DONE_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1766 #define CC_PKA_PKA_DONE_STATUS_Msk (0x1UL << CC_PKA_PKA_DONE_STATUS_Pos) /*!< Bit mask of STATUS field. */
1767 #define CC_PKA_PKA_DONE_STATUS_Processing (0x0UL) /*!< PKA operation is processing */
1768 #define CC_PKA_PKA_DONE_STATUS_Completed (0x1UL) /*!< PKA operation is completed and pipeline is empty */
1769 
1770 /* Register: CC_PKA_PKA_VERSION */
1771 /* Description: PKA engine HW version. Reset value holds the version. */
1772 
1773 /* Bits 31..0 :   */
1774 #define CC_PKA_PKA_VERSION_PKA_VERSION_Pos (0UL) /*!< Position of PKA_VERSION field. */
1775 #define CC_PKA_PKA_VERSION_PKA_VERSION_Msk (0xFFFFFFFFUL << CC_PKA_PKA_VERSION_PKA_VERSION_Pos) /*!< Bit mask of PKA_VERSION field. */
1776 
1777 /* Register: CC_PKA_PKA_SRAM_WADDR */
1778 /* Description: Start address in PKA SRAM for subsequent write transactions. */
1779 
1780 /* Bits 31..0 : PKA SRAM start address for write transaction */
1781 #define CC_PKA_PKA_SRAM_WADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
1782 #define CC_PKA_PKA_SRAM_WADDR_ADDR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
1783 
1784 /* Register: CC_PKA_PKA_SRAM_WDATA */
1785 /* Description: Write data to PKA SRAM. Writing to this register triggers a DMA transaction writing data into PKA SRAM. The DMA address offset is automatically incremented during write. */
1786 
1787 /* Bits 31..0 : Data to write to PKA SRAM. */
1788 #define CC_PKA_PKA_SRAM_WDATA_DATA_Pos (0UL) /*!< Position of DATA field. */
1789 #define CC_PKA_PKA_SRAM_WDATA_DATA_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WDATA_DATA_Pos) /*!< Bit mask of DATA field. */
1790 
1791 /* Register: CC_PKA_PKA_SRAM_RDATA */
1792 /* Description: Read data from PKA SRAM. Reading from this register triggers a DMA transaction read data from PKA SRAM. The DMA address offset is automatically incremented during read. */
1793 
1794 /* Bits 31..0 : Data to read from PKA SRAM */
1795 #define CC_PKA_PKA_SRAM_RDATA_DATA_Pos (0UL) /*!< Position of DATA field. */
1796 #define CC_PKA_PKA_SRAM_RDATA_DATA_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_RDATA_DATA_Pos) /*!< Bit mask of DATA field. */
1797 
1798 /* Register: CC_PKA_PKA_SRAM_WCLEAR */
1799 /* Description: Register for clearing PKA SRAM write buffer. */
1800 
1801 /* Bits 31..0 : Clear the PKA SRAM write buffer. */
1802 #define CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */
1803 #define CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Pos) /*!< Bit mask of CLEAR field. */
1804 
1805 /* Register: CC_PKA_PKA_SRAM_RADDR */
1806 /* Description: Start address in PKA SRAM for subsequent read transactions. */
1807 
1808 /* Bits 31..0 : PKA SRAM start address for read transaction */
1809 #define CC_PKA_PKA_SRAM_RADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
1810 #define CC_PKA_PKA_SRAM_RADDR_ADDR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_RADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
1811 
1812 
1813 /* Peripheral: CC_RNG */
1814 /* Description: CRYPTOCELL RNG engine */
1815 
1816 /* Register: CC_RNG_RNG_IMR */
1817 /* Description: Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. */
1818 
1819 /* Bit 5 : See RNG_ISR for explanation on this interrupt. */
1820 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_Pos (5UL) /*!< Position of DMA_DONE_MASK field. */
1821 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_DMA_DONE_MASK_Pos) /*!< Bit mask of DMA_DONE_MASK field. */
1822 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_IRQEnable (0x0UL) /*!< Do not mask the RNG DMA completion interrupt i.e. interrupt is generated */
1823 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_IRQDisable (0x1UL) /*!< Mask the RNG DMA completion interrupt i.e. no interrupt is generated */
1824 
1825 /* Bit 4 : See RNG_ISR for explanation on this interrupt. */
1826 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_Pos (4UL) /*!< Position of WATCHDOG_MASK field. */
1827 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_WATCHDOG_MASK_Pos) /*!< Bit mask of WATCHDOG_MASK field. */
1828 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_IRQEnable (0x0UL) /*!< Do not mask the watchdog interrupt i.e. interrupt is generated */
1829 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_IRQDisable (0x1UL) /*!< Mask the watchdog interrupt i.e. no interrupt is generated */
1830 
1831 /* Bit 3 : See RNG_ISR for explanation on this interrupt. */
1832 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_Pos (3UL) /*!< Position of VNC_ERR_MASK field. */
1833 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_VNC_ERR_MASK_Pos) /*!< Bit mask of VNC_ERR_MASK field. */
1834 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask the von Neumann corrector error interrupt i.e. interrupt is generated */
1835 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_IRQDisable (0x1UL) /*!< Mask the von Neumann corrector error interrupt i.e. no interrupt is generated */
1836 
1837 /* Bit 2 : See RNG_ISR for explanation on this interrupt. */
1838 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Pos (2UL) /*!< Position of CRNGT_ERR_MASK field. */
1839 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Pos) /*!< Bit mask of CRNGT_ERR_MASK field. */
1840 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask the CRNGT error interrupt i.e. interrupt is generated */
1841 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_IRQDisable (0x1UL) /*!< Mask the CRNGT error interrupt i.e. no interrupt is generated */
1842 
1843 /* Bit 1 : See RNG_ISR for explanation on this interrupt. */
1844 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Pos (1UL) /*!< Position of AUTOCORR_ERR_MASK field. */
1845 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Pos) /*!< Bit mask of AUTOCORR_ERR_MASK field. */
1846 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask autocorrelation interrupt i.e. interrupt is generated */
1847 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_IRQDisable (0x1UL) /*!< Mask autocorrelation interrupt i.e. no interrupt is generated */
1848 
1849 /* Bit 0 : See RNG_ISR for explanation on this interrupt. */
1850 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_Pos (0UL) /*!< Position of EHR_VALID_MASK field. */
1851 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_EHR_VALID_MASK_Pos) /*!< Bit mask of EHR_VALID_MASK field. */
1852 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_IRQEnable (0x0UL) /*!< Do not mask EHR interrupt i.e. interrupt is generated */
1853 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_IRQDisable (0x1UL) /*!< Mask EHR interrupt i.e. no interrupt is generated */
1854 
1855 /* Register: CC_RNG_RNG_ISR */
1856 /* Description: Interrupt status register. Each bit of this register holds the interrupt
1857         status of a single interrupt source. If corresponding RNG_IMR bit is
1858         unmasked, an interrupt is generated. */
1859 
1860 /* Bit 5 : RNG DMA to SRAM is completed. */
1861 #define CC_RNG_RNG_ISR_DMA_DONE_INT_Pos (5UL) /*!< Position of DMA_DONE_INT field. */
1862 #define CC_RNG_RNG_ISR_DMA_DONE_INT_Msk (0x1UL << CC_RNG_RNG_ISR_DMA_DONE_INT_Pos) /*!< Bit mask of DMA_DONE_INT field. */
1863 
1864 /* Bit 4 : Maximum number of CPU clock cycles per sample have been exceeded. See RNG_WATCHDOG_VAL for more information. */
1865 #define CC_RNG_RNG_ISR_WATCHDOG_INT_Pos (4UL) /*!< Position of WATCHDOG_INT field. */
1866 #define CC_RNG_RNG_ISR_WATCHDOG_INT_Msk (0x1UL << CC_RNG_RNG_ISR_WATCHDOG_INT_Pos) /*!< Bit mask of WATCHDOG_INT field. */
1867 
1868 /* Bit 3 : von Neumann corrector error. Failure occurs if 32 consecutive collected bits are identical, ZERO, or ONE. */
1869 #define CC_RNG_RNG_ISR_VNC_ERR_INT_Pos (3UL) /*!< Position of VNC_ERR_INT field. */
1870 #define CC_RNG_RNG_ISR_VNC_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_VNC_ERR_INT_Pos) /*!< Bit mask of VNC_ERR_INT field. */
1871 
1872 /* Bit 2 : Continuous random number generator test error. Failure occurs when two consecutive blocks of 16 collected bits are equal. */
1873 #define CC_RNG_RNG_ISR_CRNGT_ERR_INT_Pos (2UL) /*!< Position of CRNGT_ERR_INT field. */
1874 #define CC_RNG_RNG_ISR_CRNGT_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_CRNGT_ERR_INT_Pos) /*!< Bit mask of CRNGT_ERR_INT field. */
1875 
1876 /* Bit 1 : Autocorrelation error. Failure occurs when autocorrelation test has failed four times in a row. Once set, the TRNG ceases to function until next reset. */
1877 #define CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Pos (1UL) /*!< Position of AUTOCORR_ERR_INT field. */
1878 #define CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Pos) /*!< Bit mask of AUTOCORR_ERR_INT field. */
1879 
1880 /* Bit 0 : 192-bits have been collected and are ready to be read. */
1881 #define CC_RNG_RNG_ISR_EHR_VALID_INT_Pos (0UL) /*!< Position of EHR_VALID_INT field. */
1882 #define CC_RNG_RNG_ISR_EHR_VALID_INT_Msk (0x1UL << CC_RNG_RNG_ISR_EHR_VALID_INT_Pos) /*!< Bit mask of EHR_VALID_INT field. */
1883 
1884 /* Register: CC_RNG_RNG_ICR */
1885 /* Description: Interrupt clear register. Writing a 1 bit into a field in this register
1886         will clear the corresponding bit in RNG_ISR. */
1887 
1888 /* Bit 5 : Writing value '1' clears corresponding bit in RNG_ISR */
1889 #define CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Pos (5UL) /*!< Position of DMA_DONE_CLEAR field. */
1890 #define CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Pos) /*!< Bit mask of DMA_DONE_CLEAR field. */
1891 
1892 /* Bit 4 : Writing value '1' clears corresponding bit in RNG_ISR */
1893 #define CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Pos (4UL) /*!< Position of WATCHDOG_CLEAR field. */
1894 #define CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Pos) /*!< Bit mask of WATCHDOG_CLEAR field. */
1895 
1896 /* Bit 3 : Writing value '1' clears corresponding bit in RNG_ISR */
1897 #define CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Pos (3UL) /*!< Position of VNC_ERR_CLEAR field. */
1898 #define CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Pos) /*!< Bit mask of VNC_ERR_CLEAR field. */
1899 
1900 /* Bit 2 : Writing value '1' clears corresponding bit in RNG_ISR */
1901 #define CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Pos (2UL) /*!< Position of CRNGT_ERR_CLEAR field. */
1902 #define CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Pos) /*!< Bit mask of CRNGT_ERR_CLEAR field. */
1903 
1904 /* Bit 1 : Cannot be cleared by software! Only RNG reset clears this bit. */
1905 #define CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Pos (1UL) /*!< Position of AUTOCORR_ERR_CLEAR field. */
1906 #define CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Pos) /*!< Bit mask of AUTOCORR_ERR_CLEAR field. */
1907 
1908 /* Bit 0 : Writing value '1' clears corresponding bit in RNG_ISR */
1909 #define CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Pos (0UL) /*!< Position of EHR_VALID_CLEAR field. */
1910 #define CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Pos) /*!< Bit mask of EHR_VALID_CLEAR field. */
1911 
1912 /* Register: CC_RNG_TRNG_CONFIG */
1913 /* Description: TRNG ring oscillator length configuration */
1914 
1915 /* Bits 1..0 : Set the length of the oscillator ring (= the number of inverters) out of four possible configurations. */
1916 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_Pos (0UL) /*!< Position of ROSC_LEN field. */
1917 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_Msk (0x3UL << CC_RNG_TRNG_CONFIG_ROSC_LEN_Pos) /*!< Bit mask of ROSC_LEN field. */
1918 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC1 (0x0UL) /*!< Use shortest ROSC1 ring oscillator configuration. */
1919 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC2 (0x1UL) /*!< Use ROSC2 ring oscillator configuration. */
1920 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC3 (0x2UL) /*!< Use ROSC3 ring oscillator configuration. */
1921 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC4 (0x3UL) /*!< Use longest ROSC4 ring oscillator configuration. */
1922 
1923 /* Register: CC_RNG_TRNG_VALID */
1924 /* Description: This register indicates if TRNG entropy collection is valid. */
1925 
1926 /* Bit 0 : A value of 1 indicates that collection of bits in the TRNG is completed, and data can be read from EHR_DATA registers. */
1927 #define CC_RNG_TRNG_VALID_EHR_DATA_Pos (0UL) /*!< Position of EHR_DATA field. */
1928 #define CC_RNG_TRNG_VALID_EHR_DATA_Msk (0x1UL << CC_RNG_TRNG_VALID_EHR_DATA_Pos) /*!< Bit mask of EHR_DATA field. */
1929 #define CC_RNG_TRNG_VALID_EHR_DATA_NotValid (0x0UL) /*!< Collection of bits not valid. */
1930 #define CC_RNG_TRNG_VALID_EHR_DATA_Valid (0x1UL) /*!< Collection of bits valid. */
1931 
1932 /* Register: CC_RNG_EHR_DATA */
1933 /* Description: Description collection: The entropy holding registers (EHR) hold 192-bits random data collected by the TRNG. The initial EHR_DATA[0] register holds the least significant bits [31:0] of the random data value. */
1934 
1935 /* Bits 31..0 : Random data value. */
1936 #define CC_RNG_EHR_DATA_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1937 #define CC_RNG_EHR_DATA_VALUE_Msk (0xFFFFFFFFUL << CC_RNG_EHR_DATA_VALUE_Pos) /*!< Bit mask of VALUE field. */
1938 
1939 /* Register: CC_RNG_NOISE_SOURCE */
1940 /* Description: This register controls the ring oscillator circuit used as a noise source. */
1941 
1942 /* Bit 0 : Enable or disable the noise source. */
1943 #define CC_RNG_NOISE_SOURCE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1944 #define CC_RNG_NOISE_SOURCE_ENABLE_Msk (0x1UL << CC_RNG_NOISE_SOURCE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1945 #define CC_RNG_NOISE_SOURCE_ENABLE_Disabled (0x0UL) /*!< Noise source is disabled */
1946 #define CC_RNG_NOISE_SOURCE_ENABLE_Enabled (0x1UL) /*!< Noise source is enabled */
1947 
1948 /* Register: CC_RNG_SAMPLE_CNT */
1949 /* Description: Sample count defining the number of CPU clock cycles between two consecutive noise source samples. */
1950 
1951 /* Bits 31..0 : Number of CPU clock cycles between two consecutive noise source samples. */
1952 #define CC_RNG_SAMPLE_CNT_VALUE_Pos (0UL) /*!< Position of VALUE field. */
1953 #define CC_RNG_SAMPLE_CNT_VALUE_Msk (0xFFFFFFFFUL << CC_RNG_SAMPLE_CNT_VALUE_Pos) /*!< Bit mask of VALUE field. */
1954 
1955 /* Register: CC_RNG_AUTOCORR_STATISTIC */
1956 /* Description: Statistics counter for autocorrelation test activations. Statistics collection is stopped if one of the counters reach its limit of all ones. */
1957 
1958 /* Bits 21..14 : Count each time an autocorrelation test fails. Any write to the field resets the counter. */
1959 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Pos (14UL) /*!< Position of AUTOCORR_FAILS field. */
1960 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Msk (0xFFUL << CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Pos) /*!< Bit mask of AUTOCORR_FAILS field. */
1961 
1962 /* Bits 13..0 : Count each time an autocorrelation test starts. Any write to the field resets the counter. */
1963 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Pos (0UL) /*!< Position of AUTOCORR_TRYS field. */
1964 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Msk (0x3FFFUL << CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Pos) /*!< Bit mask of AUTOCORR_TRYS field. */
1965 
1966 /* Register: CC_RNG_TRNG_DEBUG */
1967 /* Description: Debug register for the TRNG. This register is used to bypass TRNG tests in hardware. */
1968 
1969 /* Bit 3 : Bypass the autocorrelation test. */
1970 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Pos (3UL) /*!< Position of AUTOCORR_BYPASS field. */
1971 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Pos) /*!< Bit mask of AUTOCORR_BYPASS field. */
1972 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Disabled (0x0UL) /*!< Autocorrelation test is active */
1973 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Enabled (0x1UL) /*!< Bypass the autocorrelation test */
1974 
1975 /* Bit 2 : Bypass the Continuous Random Number Generator Test (CRNGT). */
1976 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Pos (2UL) /*!< Position of CRNGT_BYPASS field. */
1977 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Pos) /*!< Bit mask of CRNGT_BYPASS field. */
1978 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Disabled (0x0UL) /*!< CRNGT is active */
1979 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Enabled (0x1UL) /*!< Bypass CRNGT */
1980 
1981 /* Bit 1 : Bypass the von Neumann corrector post-processing test, including the 32 consecutive bits test. */
1982 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Pos (1UL) /*!< Position of VNC_BYPASS field. */
1983 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_VNC_BYPASS_Pos) /*!< Bit mask of VNC_BYPASS field. */
1984 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Disabled (0x0UL) /*!< von Neumann corrector post-processing is active */
1985 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Enabled (0x1UL) /*!< Bypass the von Neumann corrector */
1986 
1987 /* Register: CC_RNG_RNG_SW_RESET */
1988 /* Description: Reset the RNG engine. */
1989 
1990 /* Bit 0 : Writing any value to this address resets the RNG engine. The reset takes 4 CPU clock cycles to complete. */
1991 #define CC_RNG_RNG_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
1992 #define CC_RNG_RNG_SW_RESET_RESET_Msk (0x1UL << CC_RNG_RNG_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
1993 #define CC_RNG_RNG_SW_RESET_RESET_Enable (0x1UL) /*!< Reset RNG engine. */
1994 
1995 /* Register: CC_RNG_RNG_BUSY */
1996 /* Description: Status register for RNG engine activity. */
1997 
1998 /* Bit 1 : TRNG status. */
1999 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Pos (1UL) /*!< Position of TRNG_STATUS field. */
2000 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Msk (0x1UL << CC_RNG_RNG_BUSY_TRNG_STATUS_Pos) /*!< Bit mask of TRNG_STATUS field. */
2001 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Idle (0x0UL) /*!< TRNG is idle */
2002 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Busy (0x1UL) /*!< TRNG is busy */
2003 
2004 /* Bit 0 : RNG engine status. */
2005 #define CC_RNG_RNG_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
2006 #define CC_RNG_RNG_BUSY_STATUS_Msk (0x1UL << CC_RNG_RNG_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
2007 #define CC_RNG_RNG_BUSY_STATUS_Idle (0x0UL) /*!< RNG engine is idle */
2008 #define CC_RNG_RNG_BUSY_STATUS_Busy (0x1UL) /*!< RNG engine is busy */
2009 
2010 /* Register: CC_RNG_TRNG_RESET */
2011 /* Description: Reset the TRNG, including internal counter of collected bits and registers EHR_DATA and TRNG_VALID. */
2012 
2013 /* Bit 0 : Writing any value to this address resets the internal bits counter and registers EHR_DATA and TRNG_VALID. Register NOISE_SOURCE must be disabled in order for the reset to take place. */
2014 #define CC_RNG_TRNG_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
2015 #define CC_RNG_TRNG_RESET_RESET_Msk (0x1UL << CC_RNG_TRNG_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
2016 #define CC_RNG_TRNG_RESET_RESET_Enable (0x1UL) /*!< Reset TRNG. */
2017 
2018 /* Register: CC_RNG_RNG_HW_FLAGS */
2019 /* Description: Hardware configuration of RNG engine. Reset value holds the supported features. */
2020 
2021 /* Bit 7 :   */
2022 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Pos (7UL) /*!< Position of RNG_USE_5_SBOXES field. */
2023 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Pos) /*!< Bit mask of RNG_USE_5_SBOXES field. */
2024 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Disable (0x0UL) /*!< 20 SBOX AES */
2025 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Enable (0x1UL) /*!< 5 SBOX AES */
2026 
2027 /* Bit 6 : If this flag is set, the engine include support for automatic reseeding. */
2028 #define CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Pos (6UL) /*!< Position of RESEEDING_EXISTS field. */
2029 #define CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Pos) /*!< Bit mask of RESEEDING_EXISTS field. */
2030 
2031 /* Bit 5 : If this flag is set, the engine include support for known answer tests. */
2032 #define CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Pos (5UL) /*!< Position of KAT_EXISTS field. */
2033 #define CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Pos) /*!< Bit mask of KAT_EXISTS field. */
2034 
2035 /* Bit 4 : If this flag is set, the engine include a pseudo-random number generator. */
2036 #define CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Pos (4UL) /*!< Position of PRNG_EXISTS field. */
2037 #define CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Pos) /*!< Bit mask of PRNG_EXISTS field. */
2038 
2039 /* Bit 3 : If this flag is set, the engine include support for bypassing TRNG tests. */
2040 #define CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Pos (3UL) /*!< Position of BYPASS_EXISTS field. */
2041 #define CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Pos) /*!< Bit mask of BYPASS_EXISTS field. */
2042 
2043 /* Bit 2 : If this flag is set, the engine include support for autocorrelation test. */
2044 #define CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Pos (2UL) /*!< Position of AUTOCORR_EXISTS field. */
2045 #define CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Pos) /*!< Bit mask of AUTOCORR_EXISTS field. */
2046 
2047 /* Bit 1 : If this flag is set, the engine include support for continuous random number generator test. */
2048 #define CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Pos (1UL) /*!< Position of CRNGT_EXISTS field. */
2049 #define CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Pos) /*!< Bit mask of CRNGT_EXISTS field. */
2050 
2051 /* Bit 0 : Data width supported by the entropy collector */
2052 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Pos (0UL) /*!< Position of EHR_WIDTH field. */
2053 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Pos) /*!< Bit mask of EHR_WIDTH field. */
2054 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_128Bits (0x0UL) /*!< 128 bits EHR width */
2055 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_192Bits (0x1UL) /*!< 192 bits EHR width */
2056 
2057 /* Register: CC_RNG_RNG_CLK */
2058 /* Description: Control clock for the RNG engine. */
2059 
2060 /* Bit 0 : Enables clock for the RNG engine. */
2061 #define CC_RNG_RNG_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2062 #define CC_RNG_RNG_CLK_ENABLE_Msk (0x1UL << CC_RNG_RNG_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2063 #define CC_RNG_RNG_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for RNG engine. */
2064 #define CC_RNG_RNG_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for RNG engine. */
2065 
2066 /* Register: CC_RNG_RNG_DMA */
2067 /* Description: Writing to this register enables the RNG DMA engine. */
2068 
2069 /* Bit 0 :   */
2070 #define CC_RNG_RNG_DMA_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2071 #define CC_RNG_RNG_DMA_ENABLE_Msk (0x1UL << CC_RNG_RNG_DMA_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2072 #define CC_RNG_RNG_DMA_ENABLE_Disable (0x0UL) /*!< Disable RNG DMA engine */
2073 #define CC_RNG_RNG_DMA_ENABLE_Enable (0x1UL) /*!< Enable RNG DMA engine This value is cleared when the RNG DMA engine completes its operation. */
2074 
2075 /* Register: CC_RNG_RNG_DMA_ROSC_LEN */
2076 /* Description: This register defines which ring oscillator length configuration should be used when using the RNG DMA engine. */
2077 
2078 /* Bit 3 : Use longest ROSC4 ring oscillator configuration. */
2079 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Pos (3UL) /*!< Position of ROSC4 field. */
2080 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */
2081 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Disable (0x0UL) /*!< Disable ROSC4 */
2082 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Enable (0x1UL) /*!< Enable ROSC4 */
2083 
2084 /* Bit 2 : Use ROSC3 ring oscillator configuration. */
2085 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Pos (2UL) /*!< Position of ROSC3 field. */
2086 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */
2087 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Disable (0x0UL) /*!< Disable ROSC3 */
2088 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Enable (0x1UL) /*!< Enable ROSC3 */
2089 
2090 /* Bit 1 : Use ROSC2 ring oscillator configuration. */
2091 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Pos (1UL) /*!< Position of ROSC2 field. */
2092 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */
2093 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Disable (0x0UL) /*!< Disable ROSC2 */
2094 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Enable (0x1UL) /*!< Enable ROSC2 */
2095 
2096 /* Bit 0 : Use shortest ROSC1 ring oscillator configuration. */
2097 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
2098 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */
2099 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Disable (0x0UL) /*!< Disable ROSC1 */
2100 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Enable (0x1UL) /*!< Enable ROSC1 */
2101 
2102 /* Register: CC_RNG_RNG_DMA_SRAM_ADDR */
2103 /* Description: This register defines the start address in TRNG SRAM for the TRNG data to be collected by the RNG DMA engine. */
2104 
2105 /* Bits 10..0 : Start address of the TRNG data in TRNG SRAM. */
2106 #define CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Pos (0UL) /*!< Position of RNG_SRAM_DMA_ADDR field. */
2107 #define CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Msk (0x7FFUL << CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Pos) /*!< Bit mask of RNG_SRAM_DMA_ADDR field. */
2108 
2109 /* Register: CC_RNG_RNG_DMA_SAMPLES_NUM */
2110 /* Description: This register defines the number of 192-bits samples that the RNG DMA engine collects per run. */
2111 
2112 /* Bits 7..0 : Defines the number of 192-bits samples that the DMA engine collects per run. */
2113 #define CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Pos (0UL) /*!< Position of RNG_SAMPLES_NUM field. */
2114 #define CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Msk (0xFFUL << CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Pos) /*!< Bit mask of RNG_SAMPLES_NUM field. */
2115 
2116 /* Register: CC_RNG_RNG_WATCHDOG_VAL */
2117 /* Description: This register defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. */
2118 
2119 /* Bits 31..0 : Defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. */
2120 #define CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Pos (0UL) /*!< Position of RNG_WATCHDOG_VAL field. */
2121 #define CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Msk (0xFFFFFFFFUL << CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Pos) /*!< Bit mask of RNG_WATCHDOG_VAL field. */
2122 
2123 /* Register: CC_RNG_RNG_DMA_BUSY */
2124 /* Description: Status register for RNG DMA engine activity. */
2125 
2126 /* Bits 10..3 : Number of samples already collected using the current ring oscillator configuration. */
2127 #define CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Pos (3UL) /*!< Position of NUM_OF_SAMPLES field. */
2128 #define CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Msk (0xFFUL << CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Pos) /*!< Bit mask of NUM_OF_SAMPLES field. */
2129 
2130 /* Bits 2..1 : The active ring oscillator length configuration used by the RNG DMA engine. */
2131 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Pos (1UL) /*!< Position of ROSC_LEN field. */
2132 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Msk (0x3UL << CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Pos) /*!< Bit mask of ROSC_LEN field. */
2133 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC1 (0x0UL) /*!< Shortest ROSC1 ring oscillator configuration used. */
2134 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC2 (0x1UL) /*!< ROSC2 ring oscillator configuration used. */
2135 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC3 (0x2UL) /*!< ROSC3 ring oscillator configuration used. */
2136 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC4 (0x3UL) /*!< Longest ROSC4 ring oscillator configuration used. */
2137 
2138 /* Bit 0 : RNG DMA engine status. */
2139 #define CC_RNG_RNG_DMA_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
2140 #define CC_RNG_RNG_DMA_BUSY_STATUS_Msk (0x1UL << CC_RNG_RNG_DMA_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
2141 #define CC_RNG_RNG_DMA_BUSY_STATUS_Idle (0x0UL) /*!< RNG DMA engine is idle */
2142 #define CC_RNG_RNG_DMA_BUSY_STATUS_Busy (0x1UL) /*!< RNG DMA engine is busy */
2143 
2144 
2145 /* Peripheral: CC_RNG_SRAM */
2146 /* Description: CRYPTOCELL RNG SRAM interface */
2147 
2148 /* Register: CC_RNG_SRAM_SRAM_DATA */
2149 /* Description: Read/Write data from RNG SRAM */
2150 
2151 /* Bits 31..0 : 32 bits DMA read/write from/to RNG SRAM. A 'read' or 'write' operation to this register will trigger the DMA address to be automatically incremented. */
2152 #define CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Pos (0UL) /*!< Position of SRAM_DATA field. */
2153 #define CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Msk (0xFFFFFFFFUL << CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Pos) /*!< Bit mask of SRAM_DATA field. */
2154 
2155 /* Register: CC_RNG_SRAM_SRAM_ADDR */
2156 /* Description: First address given to RNG SRAM DMA for read/write transactions from/to RNG SRAM. */
2157 
2158 /* Bits 14..0 : RNG SRAM starting address */
2159 #define CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Pos (0UL) /*!< Position of SRAM_ADDR field. */
2160 #define CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Msk (0x7FFFUL << CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Pos) /*!< Bit mask of SRAM_ADDR field. */
2161 
2162 /* Register: CC_RNG_SRAM_SRAM_DATA_READY */
2163 /* Description: RNG SRAM DMA engine is ready to read/write from/to RNG SRAM. */
2164 
2165 /* Bit 0 : RNG SRAM DMA status. */
2166 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Pos (0UL) /*!< Position of SRAM_READY field. */
2167 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Msk (0x1UL << CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Pos) /*!< Bit mask of SRAM_READY field. */
2168 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Busy (0x0UL) /*!< DMA is busy */
2169 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Idle (0x1UL) /*!< DMA is idle */
2170 
2171 
2172 /* Peripheral: CLOCK */
2173 /* Description: Clock control */
2174 
2175 /* Register: CLOCK_TASKS_HFCLKSTART */
2176 /* Description: Start HFXO crystal oscillator */
2177 
2178 /* Bit 0 : Start HFXO crystal oscillator */
2179 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
2180 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
2181 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (0x1UL) /*!< Trigger task */
2182 
2183 /* Register: CLOCK_TASKS_HFCLKSTOP */
2184 /* Description: Stop HFXO crystal oscillator */
2185 
2186 /* Bit 0 : Stop HFXO crystal oscillator */
2187 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
2188 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
2189 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */
2190 
2191 /* Register: CLOCK_TASKS_LFCLKSTART */
2192 /* Description: Start LFCLK */
2193 
2194 /* Bit 0 : Start LFCLK */
2195 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
2196 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
2197 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (0x1UL) /*!< Trigger task */
2198 
2199 /* Register: CLOCK_TASKS_LFCLKSTOP */
2200 /* Description: Stop LFCLK */
2201 
2202 /* Bit 0 : Stop LFCLK */
2203 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
2204 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
2205 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */
2206 
2207 /* Register: CLOCK_TASKS_CAL */
2208 /* Description: Start calibration of LFRC */
2209 
2210 /* Bit 0 : Start calibration of LFRC */
2211 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
2212 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
2213 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (0x1UL) /*!< Trigger task */
2214 
2215 /* Register: CLOCK_TASKS_CTSTART */
2216 /* Description: Start calibration timer */
2217 
2218 /* Bit 0 : Start calibration timer */
2219 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */
2220 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */
2221 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (0x1UL) /*!< Trigger task */
2222 
2223 /* Register: CLOCK_TASKS_CTSTOP */
2224 /* Description: Stop calibration timer */
2225 
2226 /* Bit 0 : Stop calibration timer */
2227 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */
2228 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */
2229 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (0x1UL) /*!< Trigger task */
2230 
2231 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
2232 /* Description: HFXO crystal oscillator started */
2233 
2234 /* Bit 0 : HFXO crystal oscillator started */
2235 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
2236 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
2237 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
2238 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (0x1UL) /*!< Event generated */
2239 
2240 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
2241 /* Description: LFCLK started */
2242 
2243 /* Bit 0 : LFCLK started */
2244 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
2245 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
2246 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
2247 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (0x1UL) /*!< Event generated */
2248 
2249 /* Register: CLOCK_EVENTS_DONE */
2250 /* Description: Calibration of LFRC completed */
2251 
2252 /* Bit 0 : Calibration of LFRC completed */
2253 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
2254 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
2255 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */
2256 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */
2257 
2258 /* Register: CLOCK_EVENTS_CTTO */
2259 /* Description: Calibration timer timeout */
2260 
2261 /* Bit 0 : Calibration timer timeout */
2262 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */
2263 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */
2264 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0x0UL) /*!< Event not generated */
2265 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (0x1UL) /*!< Event generated */
2266 
2267 /* Register: CLOCK_EVENTS_CTSTARTED */
2268 /* Description: Calibration timer has been started and is ready to process new tasks */
2269 
2270 /* Bit 0 : Calibration timer has been started and is ready to process new tasks */
2271 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */
2272 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */
2273 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
2274 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (0x1UL) /*!< Event generated */
2275 
2276 /* Register: CLOCK_EVENTS_CTSTOPPED */
2277 /* Description: Calibration timer has been stopped and is ready to process new tasks */
2278 
2279 /* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */
2280 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */
2281 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */
2282 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */
2283 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (0x1UL) /*!< Event generated */
2284 
2285 /* Register: CLOCK_INTENSET */
2286 /* Description: Enable interrupt */
2287 
2288 /* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */
2289 #define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
2290 #define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
2291 #define CLOCK_INTENSET_CTSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
2292 #define CLOCK_INTENSET_CTSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
2293 #define CLOCK_INTENSET_CTSTOPPED_Set (0x1UL) /*!< Enable */
2294 
2295 /* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */
2296 #define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
2297 #define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
2298 #define CLOCK_INTENSET_CTSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
2299 #define CLOCK_INTENSET_CTSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
2300 #define CLOCK_INTENSET_CTSTARTED_Set (0x1UL) /*!< Enable */
2301 
2302 /* Bit 4 : Write '1' to enable interrupt for event CTTO */
2303 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
2304 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
2305 #define CLOCK_INTENSET_CTTO_Disabled (0x0UL) /*!< Read: Disabled */
2306 #define CLOCK_INTENSET_CTTO_Enabled (0x1UL) /*!< Read: Enabled */
2307 #define CLOCK_INTENSET_CTTO_Set (0x1UL) /*!< Enable */
2308 
2309 /* Bit 3 : Write '1' to enable interrupt for event DONE */
2310 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
2311 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
2312 #define CLOCK_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */
2313 #define CLOCK_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */
2314 #define CLOCK_INTENSET_DONE_Set (0x1UL) /*!< Enable */
2315 
2316 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
2317 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
2318 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
2319 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
2320 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
2321 #define CLOCK_INTENSET_LFCLKSTARTED_Set (0x1UL) /*!< Enable */
2322 
2323 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
2324 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
2325 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
2326 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
2327 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
2328 #define CLOCK_INTENSET_HFCLKSTARTED_Set (0x1UL) /*!< Enable */
2329 
2330 /* Register: CLOCK_INTENCLR */
2331 /* Description: Disable interrupt */
2332 
2333 /* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */
2334 #define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
2335 #define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
2336 #define CLOCK_INTENCLR_CTSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
2337 #define CLOCK_INTENCLR_CTSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
2338 #define CLOCK_INTENCLR_CTSTOPPED_Clear (0x1UL) /*!< Disable */
2339 
2340 /* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */
2341 #define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
2342 #define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
2343 #define CLOCK_INTENCLR_CTSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
2344 #define CLOCK_INTENCLR_CTSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
2345 #define CLOCK_INTENCLR_CTSTARTED_Clear (0x1UL) /*!< Disable */
2346 
2347 /* Bit 4 : Write '1' to disable interrupt for event CTTO */
2348 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
2349 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
2350 #define CLOCK_INTENCLR_CTTO_Disabled (0x0UL) /*!< Read: Disabled */
2351 #define CLOCK_INTENCLR_CTTO_Enabled (0x1UL) /*!< Read: Enabled */
2352 #define CLOCK_INTENCLR_CTTO_Clear (0x1UL) /*!< Disable */
2353 
2354 /* Bit 3 : Write '1' to disable interrupt for event DONE */
2355 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
2356 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
2357 #define CLOCK_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */
2358 #define CLOCK_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */
2359 #define CLOCK_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */
2360 
2361 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
2362 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
2363 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
2364 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
2365 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
2366 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (0x1UL) /*!< Disable */
2367 
2368 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
2369 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
2370 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
2371 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
2372 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
2373 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (0x1UL) /*!< Disable */
2374 
2375 /* Register: CLOCK_HFCLKRUN */
2376 /* Description: Status indicating that HFCLKSTART task has been triggered */
2377 
2378 /* Bit 0 : HFCLKSTART task triggered or not */
2379 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
2380 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
2381 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */
2382 #define CLOCK_HFCLKRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */
2383 
2384 /* Register: CLOCK_HFCLKSTAT */
2385 /* Description: HFCLK status */
2386 
2387 /* Bit 16 : HFCLK state */
2388 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
2389 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
2390 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0x0UL) /*!< HFCLK not running */
2391 #define CLOCK_HFCLKSTAT_STATE_Running (0x1UL) /*!< HFCLK running */
2392 
2393 /* Bit 0 : Source of HFCLK */
2394 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
2395 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
2396 #define CLOCK_HFCLKSTAT_SRC_RC (0x0UL) /*!< 64 MHz internal oscillator (HFINT) */
2397 #define CLOCK_HFCLKSTAT_SRC_Xtal (0x1UL) /*!< 64 MHz crystal oscillator (HFXO) */
2398 
2399 /* Register: CLOCK_LFCLKRUN */
2400 /* Description: Status indicating that LFCLKSTART task has been triggered */
2401 
2402 /* Bit 0 : LFCLKSTART task triggered or not */
2403 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
2404 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
2405 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */
2406 #define CLOCK_LFCLKRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */
2407 
2408 /* Register: CLOCK_LFCLKSTAT */
2409 /* Description: LFCLK status */
2410 
2411 /* Bit 16 : LFCLK state */
2412 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
2413 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
2414 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0x0UL) /*!< LFCLK not running */
2415 #define CLOCK_LFCLKSTAT_STATE_Running (0x1UL) /*!< LFCLK running */
2416 
2417 /* Bits 1..0 : Source of LFCLK */
2418 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
2419 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
2420 #define CLOCK_LFCLKSTAT_SRC_RC (0x0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
2421 #define CLOCK_LFCLKSTAT_SRC_Xtal (0x1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
2422 #define CLOCK_LFCLKSTAT_SRC_Synth (0x2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
2423 
2424 /* Register: CLOCK_LFCLKSRCCOPY */
2425 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
2426 
2427 /* Bits 1..0 : Clock source */
2428 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
2429 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
2430 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0x0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
2431 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (0x1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
2432 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (0x2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
2433 
2434 /* Register: CLOCK_LFCLKSRC */
2435 /* Description: Clock source for the LFCLK */
2436 
2437 /* Bit 17 : Enable or disable external source for LFCLK */
2438 #define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
2439 #define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
2440 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0x0UL) /*!< Disable external source (use with Xtal) */
2441 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (0x1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
2442 
2443 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
2444 #define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
2445 #define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
2446 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0x0UL) /*!< Disable (use with Xtal or low-swing external source) */
2447 #define CLOCK_LFCLKSRC_BYPASS_Enabled (0x1UL) /*!< Enable (use with rail-to-rail external source) */
2448 
2449 /* Bits 1..0 : Clock source */
2450 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
2451 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
2452 #define CLOCK_LFCLKSRC_SRC_RC (0x0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
2453 #define CLOCK_LFCLKSRC_SRC_Xtal (0x1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
2454 #define CLOCK_LFCLKSRC_SRC_Synth (0x2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
2455 
2456 /* Register: CLOCK_HFXODEBOUNCE */
2457 /* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */
2458 
2459 /* Bits 7..0 : HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. */
2460 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos (0UL) /*!< Position of HFXODEBOUNCE field. */
2461 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Msk (0xFFUL << CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos) /*!< Bit mask of HFXODEBOUNCE field. */
2462 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. */
2463 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db1024us (0x40UL) /*!< 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. */
2464 
2465 /* Register: CLOCK_CTIV */
2466 /* Description: Calibration timer interval */
2467 
2468 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
2469 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
2470 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
2471 
2472 /* Register: CLOCK_TRACECONFIG */
2473 /* Description: Clocking options for the trace port debug interface */
2474 
2475 /* Bits 17..16 : Pin multiplexing of trace signals. See pin assignment chapter for more details. */
2476 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
2477 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
2478 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0x0UL) /*!< No trace signals routed to pins. All pins can be used as regular GPIOs. */
2479 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (0x1UL) /*!< SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. */
2480 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (0x2UL) /*!< All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. */
2481 
2482 /* Bits 1..0 : Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. */
2483 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
2484 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
2485 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0x0UL) /*!< 32 MHz trace port clock (TRACECLK = 16 MHz) */
2486 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (0x1UL) /*!< 16 MHz trace port clock (TRACECLK = 8 MHz) */
2487 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (0x2UL) /*!< 8 MHz trace port clock (TRACECLK = 4 MHz) */
2488 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (0x3UL) /*!< 4 MHz trace port clock (TRACECLK = 2 MHz) */
2489 
2490 /* Register: CLOCK_LFRCMODE */
2491 /* Description: LFRC mode configuration */
2492 
2493 /* Bit 16 : Active LFRC mode. This field is read only. */
2494 #define CLOCK_LFRCMODE_STATUS_Pos (16UL) /*!< Position of STATUS field. */
2495 #define CLOCK_LFRCMODE_STATUS_Msk (0x1UL << CLOCK_LFRCMODE_STATUS_Pos) /*!< Bit mask of STATUS field. */
2496 #define CLOCK_LFRCMODE_STATUS_Normal (0x0UL) /*!< Normal mode */
2497 #define CLOCK_LFRCMODE_STATUS_ULP (0x1UL) /*!< Ultra-low power mode (ULP) */
2498 
2499 /* Bit 0 : Set LFRC mode */
2500 #define CLOCK_LFRCMODE_MODE_Pos (0UL) /*!< Position of MODE field. */
2501 #define CLOCK_LFRCMODE_MODE_Msk (0x1UL << CLOCK_LFRCMODE_MODE_Pos) /*!< Bit mask of MODE field. */
2502 #define CLOCK_LFRCMODE_MODE_Normal (0x0UL) /*!< Normal mode */
2503 #define CLOCK_LFRCMODE_MODE_ULP (0x1UL) /*!< Ultra-low power mode (ULP) */
2504 
2505 
2506 /* Peripheral: COMP */
2507 /* Description: Comparator */
2508 
2509 /* Register: COMP_TASKS_START */
2510 /* Description: Start comparator */
2511 
2512 /* Bit 0 : Start comparator */
2513 #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
2514 #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
2515 #define COMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
2516 
2517 /* Register: COMP_TASKS_STOP */
2518 /* Description: Stop comparator */
2519 
2520 /* Bit 0 : Stop comparator */
2521 #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
2522 #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
2523 #define COMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
2524 
2525 /* Register: COMP_TASKS_SAMPLE */
2526 /* Description: Sample comparator value */
2527 
2528 /* Bit 0 : Sample comparator value */
2529 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
2530 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
2531 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */
2532 
2533 /* Register: COMP_EVENTS_READY */
2534 /* Description: COMP is ready and output is valid */
2535 
2536 /* Bit 0 : COMP is ready and output is valid */
2537 #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
2538 #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
2539 #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */
2540 #define COMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */
2541 
2542 /* Register: COMP_EVENTS_DOWN */
2543 /* Description: Downward crossing */
2544 
2545 /* Bit 0 : Downward crossing */
2546 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
2547 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
2548 #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated */
2549 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated */
2550 
2551 /* Register: COMP_EVENTS_UP */
2552 /* Description: Upward crossing */
2553 
2554 /* Bit 0 : Upward crossing */
2555 #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
2556 #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
2557 #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated */
2558 #define COMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated */
2559 
2560 /* Register: COMP_EVENTS_CROSS */
2561 /* Description: Downward or upward crossing */
2562 
2563 /* Bit 0 : Downward or upward crossing */
2564 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
2565 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
2566 #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated */
2567 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated */
2568 
2569 /* Register: COMP_SHORTS */
2570 /* Description: Shortcuts between local events and tasks */
2571 
2572 /* Bit 4 : Shortcut between event CROSS and task STOP */
2573 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
2574 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
2575 #define COMP_SHORTS_CROSS_STOP_Disabled (0x0UL) /*!< Disable shortcut */
2576 #define COMP_SHORTS_CROSS_STOP_Enabled (0x1UL) /*!< Enable shortcut */
2577 
2578 /* Bit 3 : Shortcut between event UP and task STOP */
2579 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
2580 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
2581 #define COMP_SHORTS_UP_STOP_Disabled (0x0UL) /*!< Disable shortcut */
2582 #define COMP_SHORTS_UP_STOP_Enabled (0x1UL) /*!< Enable shortcut */
2583 
2584 /* Bit 2 : Shortcut between event DOWN and task STOP */
2585 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
2586 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
2587 #define COMP_SHORTS_DOWN_STOP_Disabled (0x0UL) /*!< Disable shortcut */
2588 #define COMP_SHORTS_DOWN_STOP_Enabled (0x1UL) /*!< Enable shortcut */
2589 
2590 /* Bit 1 : Shortcut between event READY and task STOP */
2591 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
2592 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
2593 #define COMP_SHORTS_READY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
2594 #define COMP_SHORTS_READY_STOP_Enabled (0x1UL) /*!< Enable shortcut */
2595 
2596 /* Bit 0 : Shortcut between event READY and task SAMPLE */
2597 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
2598 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
2599 #define COMP_SHORTS_READY_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut */
2600 #define COMP_SHORTS_READY_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut */
2601 
2602 /* Register: COMP_INTEN */
2603 /* Description: Enable or disable interrupt */
2604 
2605 /* Bit 3 : Enable or disable interrupt for event CROSS */
2606 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2607 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
2608 #define COMP_INTEN_CROSS_Disabled (0x0UL) /*!< Disable */
2609 #define COMP_INTEN_CROSS_Enabled (0x1UL) /*!< Enable */
2610 
2611 /* Bit 2 : Enable or disable interrupt for event UP */
2612 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
2613 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
2614 #define COMP_INTEN_UP_Disabled (0x0UL) /*!< Disable */
2615 #define COMP_INTEN_UP_Enabled (0x1UL) /*!< Enable */
2616 
2617 /* Bit 1 : Enable or disable interrupt for event DOWN */
2618 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2619 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
2620 #define COMP_INTEN_DOWN_Disabled (0x0UL) /*!< Disable */
2621 #define COMP_INTEN_DOWN_Enabled (0x1UL) /*!< Enable */
2622 
2623 /* Bit 0 : Enable or disable interrupt for event READY */
2624 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
2625 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
2626 #define COMP_INTEN_READY_Disabled (0x0UL) /*!< Disable */
2627 #define COMP_INTEN_READY_Enabled (0x1UL) /*!< Enable */
2628 
2629 /* Register: COMP_INTENSET */
2630 /* Description: Enable interrupt */
2631 
2632 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
2633 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2634 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
2635 #define COMP_INTENSET_CROSS_Disabled (0x0UL) /*!< Read: Disabled */
2636 #define COMP_INTENSET_CROSS_Enabled (0x1UL) /*!< Read: Enabled */
2637 #define COMP_INTENSET_CROSS_Set (0x1UL) /*!< Enable */
2638 
2639 /* Bit 2 : Write '1' to enable interrupt for event UP */
2640 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
2641 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
2642 #define COMP_INTENSET_UP_Disabled (0x0UL) /*!< Read: Disabled */
2643 #define COMP_INTENSET_UP_Enabled (0x1UL) /*!< Read: Enabled */
2644 #define COMP_INTENSET_UP_Set (0x1UL) /*!< Enable */
2645 
2646 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
2647 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2648 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
2649 #define COMP_INTENSET_DOWN_Disabled (0x0UL) /*!< Read: Disabled */
2650 #define COMP_INTENSET_DOWN_Enabled (0x1UL) /*!< Read: Enabled */
2651 #define COMP_INTENSET_DOWN_Set (0x1UL) /*!< Enable */
2652 
2653 /* Bit 0 : Write '1' to enable interrupt for event READY */
2654 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
2655 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
2656 #define COMP_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */
2657 #define COMP_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */
2658 #define COMP_INTENSET_READY_Set (0x1UL) /*!< Enable */
2659 
2660 /* Register: COMP_INTENCLR */
2661 /* Description: Disable interrupt */
2662 
2663 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
2664 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2665 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
2666 #define COMP_INTENCLR_CROSS_Disabled (0x0UL) /*!< Read: Disabled */
2667 #define COMP_INTENCLR_CROSS_Enabled (0x1UL) /*!< Read: Enabled */
2668 #define COMP_INTENCLR_CROSS_Clear (0x1UL) /*!< Disable */
2669 
2670 /* Bit 2 : Write '1' to disable interrupt for event UP */
2671 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
2672 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
2673 #define COMP_INTENCLR_UP_Disabled (0x0UL) /*!< Read: Disabled */
2674 #define COMP_INTENCLR_UP_Enabled (0x1UL) /*!< Read: Enabled */
2675 #define COMP_INTENCLR_UP_Clear (0x1UL) /*!< Disable */
2676 
2677 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
2678 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2679 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
2680 #define COMP_INTENCLR_DOWN_Disabled (0x0UL) /*!< Read: Disabled */
2681 #define COMP_INTENCLR_DOWN_Enabled (0x1UL) /*!< Read: Enabled */
2682 #define COMP_INTENCLR_DOWN_Clear (0x1UL) /*!< Disable */
2683 
2684 /* Bit 0 : Write '1' to disable interrupt for event READY */
2685 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
2686 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
2687 #define COMP_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */
2688 #define COMP_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */
2689 #define COMP_INTENCLR_READY_Clear (0x1UL) /*!< Disable */
2690 
2691 /* Register: COMP_RESULT */
2692 /* Description: Compare result */
2693 
2694 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
2695 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
2696 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
2697 #define COMP_RESULT_RESULT_Below (0x0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
2698 #define COMP_RESULT_RESULT_Above (0x1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
2699 
2700 /* Register: COMP_ENABLE */
2701 /* Description: COMP enable */
2702 
2703 /* Bits 1..0 : Enable or disable COMP */
2704 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2705 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2706 #define COMP_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
2707 #define COMP_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable */
2708 
2709 /* Register: COMP_PSEL */
2710 /* Description: Pin select */
2711 
2712 /* Bits 2..0 : Analog pin select */
2713 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
2714 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
2715 #define COMP_PSEL_PSEL_AnalogInput0 (0x0UL) /*!< AIN0 selected as analog input */
2716 #define COMP_PSEL_PSEL_AnalogInput1 (0x1UL) /*!< AIN1 selected as analog input */
2717 #define COMP_PSEL_PSEL_AnalogInput2 (0x2UL) /*!< AIN2 selected as analog input */
2718 #define COMP_PSEL_PSEL_AnalogInput3 (0x3UL) /*!< AIN3 selected as analog input */
2719 #define COMP_PSEL_PSEL_AnalogInput4 (0x4UL) /*!< AIN4 selected as analog input */
2720 #define COMP_PSEL_PSEL_AnalogInput5 (0x5UL) /*!< AIN5 selected as analog input */
2721 #define COMP_PSEL_PSEL_AnalogInput6 (0x6UL) /*!< AIN6 selected as analog input */
2722 #define COMP_PSEL_PSEL_AnalogInput7 (0x7UL) /*!< AIN7 selected as analog input */
2723 
2724 /* Register: COMP_REFSEL */
2725 /* Description: Reference source select for single-ended mode */
2726 
2727 /* Bits 2..0 : Reference select */
2728 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
2729 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
2730 #define COMP_REFSEL_REFSEL_Int1V2 (0x0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
2731 #define COMP_REFSEL_REFSEL_Int1V8 (0x1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
2732 #define COMP_REFSEL_REFSEL_Int2V4 (0x2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
2733 #define COMP_REFSEL_REFSEL_VDD (0x4UL) /*!< VREF = VDD */
2734 #define COMP_REFSEL_REFSEL_ARef (0x5UL) /*!< VREF = AREF */
2735 
2736 /* Register: COMP_EXTREFSEL */
2737 /* Description: External reference select */
2738 
2739 /* Bits 2..0 : External analog reference select */
2740 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
2741 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
2742 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0x0UL) /*!< Use AIN0 as external analog reference */
2743 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (0x1UL) /*!< Use AIN1 as external analog reference */
2744 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (0x2UL) /*!< Use AIN2 as external analog reference */
2745 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (0x3UL) /*!< Use AIN3 as external analog reference */
2746 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (0x4UL) /*!< Use AIN4 as external analog reference */
2747 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (0x5UL) /*!< Use AIN5 as external analog reference */
2748 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (0x6UL) /*!< Use AIN6 as external analog reference */
2749 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (0x7UL) /*!< Use AIN7 as external analog reference */
2750 
2751 /* Register: COMP_TH */
2752 /* Description: Threshold configuration for hysteresis unit */
2753 
2754 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
2755 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
2756 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
2757 
2758 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
2759 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
2760 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
2761 
2762 /* Register: COMP_MODE */
2763 /* Description: Mode configuration */
2764 
2765 /* Bit 8 : Main operation modes */
2766 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
2767 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
2768 #define COMP_MODE_MAIN_SE (0x0UL) /*!< Single-ended mode */
2769 #define COMP_MODE_MAIN_Diff (0x1UL) /*!< Differential mode */
2770 
2771 /* Bits 1..0 : Speed and power modes */
2772 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
2773 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
2774 #define COMP_MODE_SP_Low (0x0UL) /*!< Low-power mode */
2775 #define COMP_MODE_SP_Normal (0x1UL) /*!< Normal mode */
2776 #define COMP_MODE_SP_High (0x2UL) /*!< High-speed mode */
2777 
2778 /* Register: COMP_HYST */
2779 /* Description: Comparator hysteresis enable */
2780 
2781 /* Bit 0 : Comparator hysteresis */
2782 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
2783 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
2784 #define COMP_HYST_HYST_NoHyst (0x0UL) /*!< Comparator hysteresis disabled */
2785 #define COMP_HYST_HYST_Hyst50mV (0x1UL) /*!< Comparator hysteresis enabled */
2786 
2787 
2788 /* Peripheral: CRYPTOCELL */
2789 /* Description: CRYPTOCELL register interface */
2790 
2791 /* Register: CRYPTOCELL_ENABLE */
2792 /* Description: Enable CRYPTOCELL subsystem. */
2793 
2794 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem. */
2795 #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2796 #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2797 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0x0UL) /*!< CRYPTOCELL subsystem disabled. */
2798 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (0x1UL) /*!< CRYPTOCELL subsystem enabled. */
2799 
2800 
2801 /* Peripheral: ECB */
2802 /* Description: AES ECB Mode Encryption */
2803 
2804 /* Register: ECB_TASKS_STARTECB */
2805 /* Description: Start ECB block encrypt */
2806 
2807 /* Bit 0 : Start ECB block encrypt */
2808 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
2809 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
2810 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (0x1UL) /*!< Trigger task */
2811 
2812 /* Register: ECB_TASKS_STOPECB */
2813 /* Description: Abort a possible executing ECB operation */
2814 
2815 /* Bit 0 : Abort a possible executing ECB operation */
2816 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
2817 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
2818 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (0x1UL) /*!< Trigger task */
2819 
2820 /* Register: ECB_EVENTS_ENDECB */
2821 /* Description: ECB block encrypt complete */
2822 
2823 /* Bit 0 : ECB block encrypt complete */
2824 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
2825 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
2826 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0x0UL) /*!< Event not generated */
2827 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (0x1UL) /*!< Event generated */
2828 
2829 /* Register: ECB_EVENTS_ERRORECB */
2830 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
2831 
2832 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
2833 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
2834 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
2835 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0x0UL) /*!< Event not generated */
2836 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (0x1UL) /*!< Event generated */
2837 
2838 /* Register: ECB_INTENSET */
2839 /* Description: Enable interrupt */
2840 
2841 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
2842 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
2843 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
2844 #define ECB_INTENSET_ERRORECB_Disabled (0x0UL) /*!< Read: Disabled */
2845 #define ECB_INTENSET_ERRORECB_Enabled (0x1UL) /*!< Read: Enabled */
2846 #define ECB_INTENSET_ERRORECB_Set (0x1UL) /*!< Enable */
2847 
2848 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */
2849 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
2850 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
2851 #define ECB_INTENSET_ENDECB_Disabled (0x0UL) /*!< Read: Disabled */
2852 #define ECB_INTENSET_ENDECB_Enabled (0x1UL) /*!< Read: Enabled */
2853 #define ECB_INTENSET_ENDECB_Set (0x1UL) /*!< Enable */
2854 
2855 /* Register: ECB_INTENCLR */
2856 /* Description: Disable interrupt */
2857 
2858 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
2859 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
2860 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
2861 #define ECB_INTENCLR_ERRORECB_Disabled (0x0UL) /*!< Read: Disabled */
2862 #define ECB_INTENCLR_ERRORECB_Enabled (0x1UL) /*!< Read: Enabled */
2863 #define ECB_INTENCLR_ERRORECB_Clear (0x1UL) /*!< Disable */
2864 
2865 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */
2866 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
2867 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
2868 #define ECB_INTENCLR_ENDECB_Disabled (0x0UL) /*!< Read: Disabled */
2869 #define ECB_INTENCLR_ENDECB_Enabled (0x1UL) /*!< Read: Enabled */
2870 #define ECB_INTENCLR_ENDECB_Clear (0x1UL) /*!< Disable */
2871 
2872 /* Register: ECB_ECBDATAPTR */
2873 /* Description: ECB block encrypt memory pointers */
2874 
2875 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
2876 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
2877 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
2878 
2879 
2880 /* Peripheral: EGU */
2881 /* Description: Event generator unit 0 */
2882 
2883 /* Register: EGU_TASKS_TRIGGER */
2884 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
2885 
2886 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
2887 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
2888 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
2889 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */
2890 
2891 /* Register: EGU_EVENTS_TRIGGERED */
2892 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
2893 
2894 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
2895 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
2896 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
2897 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated */
2898 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated */
2899 
2900 /* Register: EGU_INTEN */
2901 /* Description: Enable or disable interrupt */
2902 
2903 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
2904 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
2905 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
2906 #define EGU_INTEN_TRIGGERED15_Disabled (0x0UL) /*!< Disable */
2907 #define EGU_INTEN_TRIGGERED15_Enabled (0x1UL) /*!< Enable */
2908 
2909 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
2910 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
2911 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
2912 #define EGU_INTEN_TRIGGERED14_Disabled (0x0UL) /*!< Disable */
2913 #define EGU_INTEN_TRIGGERED14_Enabled (0x1UL) /*!< Enable */
2914 
2915 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
2916 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
2917 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
2918 #define EGU_INTEN_TRIGGERED13_Disabled (0x0UL) /*!< Disable */
2919 #define EGU_INTEN_TRIGGERED13_Enabled (0x1UL) /*!< Enable */
2920 
2921 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
2922 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
2923 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
2924 #define EGU_INTEN_TRIGGERED12_Disabled (0x0UL) /*!< Disable */
2925 #define EGU_INTEN_TRIGGERED12_Enabled (0x1UL) /*!< Enable */
2926 
2927 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
2928 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
2929 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
2930 #define EGU_INTEN_TRIGGERED11_Disabled (0x0UL) /*!< Disable */
2931 #define EGU_INTEN_TRIGGERED11_Enabled (0x1UL) /*!< Enable */
2932 
2933 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
2934 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
2935 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
2936 #define EGU_INTEN_TRIGGERED10_Disabled (0x0UL) /*!< Disable */
2937 #define EGU_INTEN_TRIGGERED10_Enabled (0x1UL) /*!< Enable */
2938 
2939 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
2940 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
2941 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
2942 #define EGU_INTEN_TRIGGERED9_Disabled (0x0UL) /*!< Disable */
2943 #define EGU_INTEN_TRIGGERED9_Enabled (0x1UL) /*!< Enable */
2944 
2945 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
2946 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
2947 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
2948 #define EGU_INTEN_TRIGGERED8_Disabled (0x0UL) /*!< Disable */
2949 #define EGU_INTEN_TRIGGERED8_Enabled (0x1UL) /*!< Enable */
2950 
2951 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
2952 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
2953 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
2954 #define EGU_INTEN_TRIGGERED7_Disabled (0x0UL) /*!< Disable */
2955 #define EGU_INTEN_TRIGGERED7_Enabled (0x1UL) /*!< Enable */
2956 
2957 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
2958 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
2959 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
2960 #define EGU_INTEN_TRIGGERED6_Disabled (0x0UL) /*!< Disable */
2961 #define EGU_INTEN_TRIGGERED6_Enabled (0x1UL) /*!< Enable */
2962 
2963 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
2964 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
2965 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
2966 #define EGU_INTEN_TRIGGERED5_Disabled (0x0UL) /*!< Disable */
2967 #define EGU_INTEN_TRIGGERED5_Enabled (0x1UL) /*!< Enable */
2968 
2969 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
2970 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
2971 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
2972 #define EGU_INTEN_TRIGGERED4_Disabled (0x0UL) /*!< Disable */
2973 #define EGU_INTEN_TRIGGERED4_Enabled (0x1UL) /*!< Enable */
2974 
2975 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
2976 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
2977 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
2978 #define EGU_INTEN_TRIGGERED3_Disabled (0x0UL) /*!< Disable */
2979 #define EGU_INTEN_TRIGGERED3_Enabled (0x1UL) /*!< Enable */
2980 
2981 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
2982 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
2983 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
2984 #define EGU_INTEN_TRIGGERED2_Disabled (0x0UL) /*!< Disable */
2985 #define EGU_INTEN_TRIGGERED2_Enabled (0x1UL) /*!< Enable */
2986 
2987 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
2988 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
2989 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
2990 #define EGU_INTEN_TRIGGERED1_Disabled (0x0UL) /*!< Disable */
2991 #define EGU_INTEN_TRIGGERED1_Enabled (0x1UL) /*!< Enable */
2992 
2993 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
2994 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
2995 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
2996 #define EGU_INTEN_TRIGGERED0_Disabled (0x0UL) /*!< Disable */
2997 #define EGU_INTEN_TRIGGERED0_Enabled (0x1UL) /*!< Enable */
2998 
2999 /* Register: EGU_INTENSET */
3000 /* Description: Enable interrupt */
3001 
3002 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
3003 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
3004 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
3005 #define EGU_INTENSET_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */
3006 #define EGU_INTENSET_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */
3007 #define EGU_INTENSET_TRIGGERED15_Set (0x1UL) /*!< Enable */
3008 
3009 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
3010 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
3011 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
3012 #define EGU_INTENSET_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */
3013 #define EGU_INTENSET_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */
3014 #define EGU_INTENSET_TRIGGERED14_Set (0x1UL) /*!< Enable */
3015 
3016 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
3017 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
3018 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
3019 #define EGU_INTENSET_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */
3020 #define EGU_INTENSET_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */
3021 #define EGU_INTENSET_TRIGGERED13_Set (0x1UL) /*!< Enable */
3022 
3023 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
3024 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
3025 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
3026 #define EGU_INTENSET_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */
3027 #define EGU_INTENSET_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */
3028 #define EGU_INTENSET_TRIGGERED12_Set (0x1UL) /*!< Enable */
3029 
3030 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
3031 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
3032 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
3033 #define EGU_INTENSET_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */
3034 #define EGU_INTENSET_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */
3035 #define EGU_INTENSET_TRIGGERED11_Set (0x1UL) /*!< Enable */
3036 
3037 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
3038 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
3039 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
3040 #define EGU_INTENSET_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */
3041 #define EGU_INTENSET_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */
3042 #define EGU_INTENSET_TRIGGERED10_Set (0x1UL) /*!< Enable */
3043 
3044 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
3045 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
3046 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
3047 #define EGU_INTENSET_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */
3048 #define EGU_INTENSET_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */
3049 #define EGU_INTENSET_TRIGGERED9_Set (0x1UL) /*!< Enable */
3050 
3051 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
3052 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
3053 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
3054 #define EGU_INTENSET_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */
3055 #define EGU_INTENSET_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */
3056 #define EGU_INTENSET_TRIGGERED8_Set (0x1UL) /*!< Enable */
3057 
3058 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
3059 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
3060 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
3061 #define EGU_INTENSET_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */
3062 #define EGU_INTENSET_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */
3063 #define EGU_INTENSET_TRIGGERED7_Set (0x1UL) /*!< Enable */
3064 
3065 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
3066 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
3067 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
3068 #define EGU_INTENSET_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */
3069 #define EGU_INTENSET_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */
3070 #define EGU_INTENSET_TRIGGERED6_Set (0x1UL) /*!< Enable */
3071 
3072 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
3073 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
3074 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
3075 #define EGU_INTENSET_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */
3076 #define EGU_INTENSET_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */
3077 #define EGU_INTENSET_TRIGGERED5_Set (0x1UL) /*!< Enable */
3078 
3079 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
3080 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
3081 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
3082 #define EGU_INTENSET_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */
3083 #define EGU_INTENSET_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */
3084 #define EGU_INTENSET_TRIGGERED4_Set (0x1UL) /*!< Enable */
3085 
3086 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
3087 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
3088 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
3089 #define EGU_INTENSET_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */
3090 #define EGU_INTENSET_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */
3091 #define EGU_INTENSET_TRIGGERED3_Set (0x1UL) /*!< Enable */
3092 
3093 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
3094 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
3095 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
3096 #define EGU_INTENSET_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */
3097 #define EGU_INTENSET_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */
3098 #define EGU_INTENSET_TRIGGERED2_Set (0x1UL) /*!< Enable */
3099 
3100 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
3101 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
3102 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
3103 #define EGU_INTENSET_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */
3104 #define EGU_INTENSET_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */
3105 #define EGU_INTENSET_TRIGGERED1_Set (0x1UL) /*!< Enable */
3106 
3107 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
3108 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
3109 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
3110 #define EGU_INTENSET_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */
3111 #define EGU_INTENSET_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */
3112 #define EGU_INTENSET_TRIGGERED0_Set (0x1UL) /*!< Enable */
3113 
3114 /* Register: EGU_INTENCLR */
3115 /* Description: Disable interrupt */
3116 
3117 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
3118 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
3119 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
3120 #define EGU_INTENCLR_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */
3121 #define EGU_INTENCLR_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */
3122 #define EGU_INTENCLR_TRIGGERED15_Clear (0x1UL) /*!< Disable */
3123 
3124 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
3125 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
3126 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
3127 #define EGU_INTENCLR_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */
3128 #define EGU_INTENCLR_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */
3129 #define EGU_INTENCLR_TRIGGERED14_Clear (0x1UL) /*!< Disable */
3130 
3131 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
3132 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
3133 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
3134 #define EGU_INTENCLR_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */
3135 #define EGU_INTENCLR_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */
3136 #define EGU_INTENCLR_TRIGGERED13_Clear (0x1UL) /*!< Disable */
3137 
3138 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
3139 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
3140 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
3141 #define EGU_INTENCLR_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */
3142 #define EGU_INTENCLR_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */
3143 #define EGU_INTENCLR_TRIGGERED12_Clear (0x1UL) /*!< Disable */
3144 
3145 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
3146 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
3147 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
3148 #define EGU_INTENCLR_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */
3149 #define EGU_INTENCLR_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */
3150 #define EGU_INTENCLR_TRIGGERED11_Clear (0x1UL) /*!< Disable */
3151 
3152 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
3153 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
3154 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
3155 #define EGU_INTENCLR_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */
3156 #define EGU_INTENCLR_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */
3157 #define EGU_INTENCLR_TRIGGERED10_Clear (0x1UL) /*!< Disable */
3158 
3159 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
3160 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
3161 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
3162 #define EGU_INTENCLR_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */
3163 #define EGU_INTENCLR_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */
3164 #define EGU_INTENCLR_TRIGGERED9_Clear (0x1UL) /*!< Disable */
3165 
3166 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
3167 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
3168 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
3169 #define EGU_INTENCLR_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */
3170 #define EGU_INTENCLR_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */
3171 #define EGU_INTENCLR_TRIGGERED8_Clear (0x1UL) /*!< Disable */
3172 
3173 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
3174 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
3175 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
3176 #define EGU_INTENCLR_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */
3177 #define EGU_INTENCLR_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */
3178 #define EGU_INTENCLR_TRIGGERED7_Clear (0x1UL) /*!< Disable */
3179 
3180 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
3181 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
3182 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
3183 #define EGU_INTENCLR_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */
3184 #define EGU_INTENCLR_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */
3185 #define EGU_INTENCLR_TRIGGERED6_Clear (0x1UL) /*!< Disable */
3186 
3187 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
3188 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
3189 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
3190 #define EGU_INTENCLR_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */
3191 #define EGU_INTENCLR_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */
3192 #define EGU_INTENCLR_TRIGGERED5_Clear (0x1UL) /*!< Disable */
3193 
3194 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
3195 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
3196 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
3197 #define EGU_INTENCLR_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */
3198 #define EGU_INTENCLR_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */
3199 #define EGU_INTENCLR_TRIGGERED4_Clear (0x1UL) /*!< Disable */
3200 
3201 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
3202 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
3203 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
3204 #define EGU_INTENCLR_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */
3205 #define EGU_INTENCLR_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */
3206 #define EGU_INTENCLR_TRIGGERED3_Clear (0x1UL) /*!< Disable */
3207 
3208 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
3209 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
3210 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
3211 #define EGU_INTENCLR_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */
3212 #define EGU_INTENCLR_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */
3213 #define EGU_INTENCLR_TRIGGERED2_Clear (0x1UL) /*!< Disable */
3214 
3215 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
3216 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
3217 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
3218 #define EGU_INTENCLR_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */
3219 #define EGU_INTENCLR_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */
3220 #define EGU_INTENCLR_TRIGGERED1_Clear (0x1UL) /*!< Disable */
3221 
3222 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
3223 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
3224 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
3225 #define EGU_INTENCLR_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */
3226 #define EGU_INTENCLR_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */
3227 #define EGU_INTENCLR_TRIGGERED0_Clear (0x1UL) /*!< Disable */
3228 
3229 
3230 /* Peripheral: FICR */
3231 /* Description: Factory information configuration registers */
3232 
3233 /* Register: FICR_CODEPAGESIZE */
3234 /* Description: Code memory page size */
3235 
3236 /* Bits 31..0 : Code memory page size */
3237 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
3238 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
3239 
3240 /* Register: FICR_CODESIZE */
3241 /* Description: Code memory size */
3242 
3243 /* Bits 31..0 : Code memory size in number of pages */
3244 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
3245 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
3246 
3247 /* Register: FICR_DEVICEID */
3248 /* Description: Description collection: Device identifier */
3249 
3250 /* Bits 31..0 : 64 bit unique device identifier */
3251 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
3252 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
3253 
3254 /* Register: FICR_ER */
3255 /* Description: Description collection: Encryption root, word n */
3256 
3257 /* Bits 31..0 : Encryption root, word n */
3258 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
3259 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
3260 
3261 /* Register: FICR_IR */
3262 /* Description: Description collection: Identity Root, word n */
3263 
3264 /* Bits 31..0 : Identity Root, word n */
3265 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
3266 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
3267 
3268 /* Register: FICR_DEVICEADDRTYPE */
3269 /* Description: Device address type */
3270 
3271 /* Bit 0 : Device address type */
3272 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
3273 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
3274 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0x0UL) /*!< Public address */
3275 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (0x1UL) /*!< Random address */
3276 
3277 /* Register: FICR_DEVICEADDR */
3278 /* Description: Description collection: Device address n */
3279 
3280 /* Bits 31..0 : 48 bit device address */
3281 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
3282 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
3283 
3284 /* Register: FICR_INFO_PART */
3285 /* Description: Part code */
3286 
3287 /* Bits 31..0 : Part code */
3288 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
3289 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
3290 #define FICR_INFO_PART_PART_N52840 (0x00052840UL) /*!< nRF52840 */
3291 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3292 
3293 /* Register: FICR_INFO_VARIANT */
3294 /* Description: Build code, last two letters of Package Variant and first two characters of Build Code, encoded in ASCII. */
3295 
3296 /* Bits 31..0 : For valid values see SoC revisions and variants. */
3297 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
3298 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
3299 
3300 /* Register: FICR_INFO_PACKAGE */
3301 /* Description: Package option */
3302 
3303 /* Bits 31..0 : Package option */
3304 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
3305 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
3306 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x00002000UL) /*!< QFxx - 6x6 48-pin QFN */
3307 #define FICR_INFO_PACKAGE_PACKAGE_QI (0x00002004UL) /*!< QIxx - 7x7 73-pin aQFN */
3308 #define FICR_INFO_PACKAGE_PACKAGE_CK (0x00002005UL) /*!< CKxx - 3.544 x 3.607 WLCSP */
3309 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3310 
3311 /* Register: FICR_INFO_RAM */
3312 /* Description: RAM variant */
3313 
3314 /* Bits 31..0 : RAM variant */
3315 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
3316 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
3317 #define FICR_INFO_RAM_RAM_K16 (0x00000010UL) /*!< 16 kB RAM */
3318 #define FICR_INFO_RAM_RAM_K32 (0x00000020UL) /*!< 32 kB RAM */
3319 #define FICR_INFO_RAM_RAM_K64 (0x00000040UL) /*!< 64 kB RAM */
3320 #define FICR_INFO_RAM_RAM_K128 (0x00000080UL) /*!< 128 kB RAM */
3321 #define FICR_INFO_RAM_RAM_K256 (0x00000100UL) /*!< 256 kB RAM */
3322 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3323 
3324 /* Register: FICR_INFO_FLASH */
3325 /* Description: Flash variant */
3326 
3327 /* Bits 31..0 : Flash variant */
3328 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
3329 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
3330 #define FICR_INFO_FLASH_FLASH_K128 (0x00000080UL) /*!< 128 kB FLASH */
3331 #define FICR_INFO_FLASH_FLASH_K256 (0x00000100UL) /*!< 256 kB FLASH */
3332 #define FICR_INFO_FLASH_FLASH_K512 (0x00000200UL) /*!< 512 kB FLASH */
3333 #define FICR_INFO_FLASH_FLASH_K1024 (0x00000400UL) /*!< 1 MB FLASH */
3334 #define FICR_INFO_FLASH_FLASH_K2048 (0x00000800UL) /*!< 2 MB FLASH */
3335 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3336 
3337 /* Register: FICR_PRODTEST */
3338 /* Description: Description collection: Production test signature n */
3339 
3340 /* Bits 31..0 : Production test signature n */
3341 #define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */
3342 #define FICR_PRODTEST_PRODTEST_Msk (0xFFFFFFFFUL << FICR_PRODTEST_PRODTEST_Pos) /*!< Bit mask of PRODTEST field. */
3343 #define FICR_PRODTEST_PRODTEST_Done (0xBB42319FUL) /*!< Production tests done */
3344 #define FICR_PRODTEST_PRODTEST_NotDone (0xFFFFFFFFUL) /*!< Production tests not done */
3345 
3346 /* Register: FICR_TEMP_A0 */
3347 /* Description: Slope definition A0 */
3348 
3349 /* Bits 11..0 : A (slope definition) register. */
3350 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
3351 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
3352 
3353 /* Register: FICR_TEMP_A1 */
3354 /* Description: Slope definition A1 */
3355 
3356 /* Bits 11..0 : A (slope definition) register. */
3357 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
3358 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
3359 
3360 /* Register: FICR_TEMP_A2 */
3361 /* Description: Slope definition A2 */
3362 
3363 /* Bits 11..0 : A (slope definition) register. */
3364 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
3365 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
3366 
3367 /* Register: FICR_TEMP_A3 */
3368 /* Description: Slope definition A3 */
3369 
3370 /* Bits 11..0 : A (slope definition) register. */
3371 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
3372 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
3373 
3374 /* Register: FICR_TEMP_A4 */
3375 /* Description: Slope definition A4 */
3376 
3377 /* Bits 11..0 : A (slope definition) register. */
3378 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
3379 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
3380 
3381 /* Register: FICR_TEMP_A5 */
3382 /* Description: Slope definition A5 */
3383 
3384 /* Bits 11..0 : A (slope definition) register. */
3385 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
3386 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
3387 
3388 /* Register: FICR_TEMP_B0 */
3389 /* Description: Y-intercept B0 */
3390 
3391 /* Bits 13..0 : B (y-intercept) */
3392 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
3393 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
3394 
3395 /* Register: FICR_TEMP_B1 */
3396 /* Description: Y-intercept B1 */
3397 
3398 /* Bits 13..0 : B (y-intercept) */
3399 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
3400 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
3401 
3402 /* Register: FICR_TEMP_B2 */
3403 /* Description: Y-intercept B2 */
3404 
3405 /* Bits 13..0 : B (y-intercept) */
3406 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
3407 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
3408 
3409 /* Register: FICR_TEMP_B3 */
3410 /* Description: Y-intercept B3 */
3411 
3412 /* Bits 13..0 : B (y-intercept) */
3413 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
3414 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
3415 
3416 /* Register: FICR_TEMP_B4 */
3417 /* Description: Y-intercept B4 */
3418 
3419 /* Bits 13..0 : B (y-intercept) */
3420 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
3421 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
3422 
3423 /* Register: FICR_TEMP_B5 */
3424 /* Description: Y-intercept B5 */
3425 
3426 /* Bits 13..0 : B (y-intercept) */
3427 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
3428 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
3429 
3430 /* Register: FICR_TEMP_T0 */
3431 /* Description: Segment end T0 */
3432 
3433 /* Bits 7..0 : T (segment end) register */
3434 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
3435 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
3436 
3437 /* Register: FICR_TEMP_T1 */
3438 /* Description: Segment end T1 */
3439 
3440 /* Bits 7..0 : T (segment end) register */
3441 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
3442 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
3443 
3444 /* Register: FICR_TEMP_T2 */
3445 /* Description: Segment end T2 */
3446 
3447 /* Bits 7..0 : T (segment end) register */
3448 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
3449 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
3450 
3451 /* Register: FICR_TEMP_T3 */
3452 /* Description: Segment end T3 */
3453 
3454 /* Bits 7..0 : T (segment end) register */
3455 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
3456 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
3457 
3458 /* Register: FICR_TEMP_T4 */
3459 /* Description: Segment end T4 */
3460 
3461 /* Bits 7..0 : T (segment end) register */
3462 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
3463 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
3464 
3465 /* Register: FICR_NFC_TAGHEADER0 */
3466 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
3467 
3468 /* Bits 31..24 : Unique identifier byte 3 */
3469 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
3470 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
3471 
3472 /* Bits 23..16 : Unique identifier byte 2 */
3473 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
3474 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
3475 
3476 /* Bits 15..8 : Unique identifier byte 1 */
3477 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
3478 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
3479 
3480 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
3481 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
3482 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
3483 
3484 /* Register: FICR_NFC_TAGHEADER1 */
3485 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
3486 
3487 /* Bits 31..24 : Unique identifier byte 7 */
3488 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
3489 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
3490 
3491 /* Bits 23..16 : Unique identifier byte 6 */
3492 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
3493 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
3494 
3495 /* Bits 15..8 : Unique identifier byte 5 */
3496 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
3497 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
3498 
3499 /* Bits 7..0 : Unique identifier byte 4 */
3500 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
3501 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
3502 
3503 /* Register: FICR_NFC_TAGHEADER2 */
3504 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
3505 
3506 /* Bits 31..24 : Unique identifier byte 11 */
3507 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
3508 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
3509 
3510 /* Bits 23..16 : Unique identifier byte 10 */
3511 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
3512 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
3513 
3514 /* Bits 15..8 : Unique identifier byte 9 */
3515 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
3516 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
3517 
3518 /* Bits 7..0 : Unique identifier byte 8 */
3519 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
3520 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
3521 
3522 /* Register: FICR_NFC_TAGHEADER3 */
3523 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
3524 
3525 /* Bits 31..24 : Unique identifier byte 15 */
3526 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
3527 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
3528 
3529 /* Bits 23..16 : Unique identifier byte 14 */
3530 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
3531 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
3532 
3533 /* Bits 15..8 : Unique identifier byte 13 */
3534 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
3535 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
3536 
3537 /* Bits 7..0 : Unique identifier byte 12 */
3538 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
3539 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
3540 
3541 /* Register: FICR_TRNG90B_BYTES */
3542 /* Description: Amount of bytes for the required entropy bits */
3543 
3544 /* Bits 31..0 : Amount of bytes for the required entropy bits */
3545 #define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */
3546 #define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */
3547 
3548 /* Register: FICR_TRNG90B_RCCUTOFF */
3549 /* Description: Repetition counter cutoff */
3550 
3551 /* Bits 31..0 : Repetition counter cutoff */
3552 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */
3553 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */
3554 
3555 /* Register: FICR_TRNG90B_APCUTOFF */
3556 /* Description: Adaptive proportion cutoff */
3557 
3558 /* Bits 31..0 : Adaptive proportion cutoff */
3559 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */
3560 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */
3561 
3562 /* Register: FICR_TRNG90B_STARTUP */
3563 /* Description: Amount of bytes for the startup tests */
3564 
3565 /* Bits 31..0 : Amount of bytes for the startup tests */
3566 #define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */
3567 #define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */
3568 
3569 /* Register: FICR_TRNG90B_ROSC1 */
3570 /* Description: Sample count for ring oscillator 1 */
3571 
3572 /* Bits 31..0 : Sample count for ring oscillator 1 */
3573 #define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
3574 #define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */
3575 
3576 /* Register: FICR_TRNG90B_ROSC2 */
3577 /* Description: Sample count for ring oscillator 2 */
3578 
3579 /* Bits 31..0 : Sample count for ring oscillator 2 */
3580 #define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */
3581 #define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */
3582 
3583 /* Register: FICR_TRNG90B_ROSC3 */
3584 /* Description: Sample count for ring oscillator 3 */
3585 
3586 /* Bits 31..0 : Sample count for ring oscillator 3 */
3587 #define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */
3588 #define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */
3589 
3590 /* Register: FICR_TRNG90B_ROSC4 */
3591 /* Description: Sample count for ring oscillator 4 */
3592 
3593 /* Bits 31..0 : Sample count for ring oscillator 4 */
3594 #define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */
3595 #define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */
3596 
3597 
3598 /* Peripheral: GPIOTE */
3599 /* Description: GPIO Tasks and Events */
3600 
3601 /* Register: GPIOTE_TASKS_OUT */
3602 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
3603 
3604 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
3605 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
3606 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
3607 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (0x1UL) /*!< Trigger task */
3608 
3609 /* Register: GPIOTE_TASKS_SET */
3610 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
3611 
3612 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
3613 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
3614 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
3615 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (0x1UL) /*!< Trigger task */
3616 
3617 /* Register: GPIOTE_TASKS_CLR */
3618 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
3619 
3620 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
3621 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
3622 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
3623 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (0x1UL) /*!< Trigger task */
3624 
3625 /* Register: GPIOTE_EVENTS_IN */
3626 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
3627 
3628 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
3629 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
3630 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
3631 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0x0UL) /*!< Event not generated */
3632 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (0x1UL) /*!< Event generated */
3633 
3634 /* Register: GPIOTE_EVENTS_PORT */
3635 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
3636 
3637 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
3638 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
3639 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
3640 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0x0UL) /*!< Event not generated */
3641 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (0x1UL) /*!< Event generated */
3642 
3643 /* Register: GPIOTE_INTENSET */
3644 /* Description: Enable interrupt */
3645 
3646 /* Bit 31 : Write '1' to enable interrupt for event PORT */
3647 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
3648 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
3649 #define GPIOTE_INTENSET_PORT_Disabled (0x0UL) /*!< Read: Disabled */
3650 #define GPIOTE_INTENSET_PORT_Enabled (0x1UL) /*!< Read: Enabled */
3651 #define GPIOTE_INTENSET_PORT_Set (0x1UL) /*!< Enable */
3652 
3653 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
3654 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
3655 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
3656 #define GPIOTE_INTENSET_IN7_Disabled (0x0UL) /*!< Read: Disabled */
3657 #define GPIOTE_INTENSET_IN7_Enabled (0x1UL) /*!< Read: Enabled */
3658 #define GPIOTE_INTENSET_IN7_Set (0x1UL) /*!< Enable */
3659 
3660 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
3661 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
3662 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
3663 #define GPIOTE_INTENSET_IN6_Disabled (0x0UL) /*!< Read: Disabled */
3664 #define GPIOTE_INTENSET_IN6_Enabled (0x1UL) /*!< Read: Enabled */
3665 #define GPIOTE_INTENSET_IN6_Set (0x1UL) /*!< Enable */
3666 
3667 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
3668 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
3669 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
3670 #define GPIOTE_INTENSET_IN5_Disabled (0x0UL) /*!< Read: Disabled */
3671 #define GPIOTE_INTENSET_IN5_Enabled (0x1UL) /*!< Read: Enabled */
3672 #define GPIOTE_INTENSET_IN5_Set (0x1UL) /*!< Enable */
3673 
3674 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
3675 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
3676 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
3677 #define GPIOTE_INTENSET_IN4_Disabled (0x0UL) /*!< Read: Disabled */
3678 #define GPIOTE_INTENSET_IN4_Enabled (0x1UL) /*!< Read: Enabled */
3679 #define GPIOTE_INTENSET_IN4_Set (0x1UL) /*!< Enable */
3680 
3681 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
3682 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
3683 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
3684 #define GPIOTE_INTENSET_IN3_Disabled (0x0UL) /*!< Read: Disabled */
3685 #define GPIOTE_INTENSET_IN3_Enabled (0x1UL) /*!< Read: Enabled */
3686 #define GPIOTE_INTENSET_IN3_Set (0x1UL) /*!< Enable */
3687 
3688 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
3689 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
3690 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
3691 #define GPIOTE_INTENSET_IN2_Disabled (0x0UL) /*!< Read: Disabled */
3692 #define GPIOTE_INTENSET_IN2_Enabled (0x1UL) /*!< Read: Enabled */
3693 #define GPIOTE_INTENSET_IN2_Set (0x1UL) /*!< Enable */
3694 
3695 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
3696 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
3697 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
3698 #define GPIOTE_INTENSET_IN1_Disabled (0x0UL) /*!< Read: Disabled */
3699 #define GPIOTE_INTENSET_IN1_Enabled (0x1UL) /*!< Read: Enabled */
3700 #define GPIOTE_INTENSET_IN1_Set (0x1UL) /*!< Enable */
3701 
3702 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
3703 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
3704 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
3705 #define GPIOTE_INTENSET_IN0_Disabled (0x0UL) /*!< Read: Disabled */
3706 #define GPIOTE_INTENSET_IN0_Enabled (0x1UL) /*!< Read: Enabled */
3707 #define GPIOTE_INTENSET_IN0_Set (0x1UL) /*!< Enable */
3708 
3709 /* Register: GPIOTE_INTENCLR */
3710 /* Description: Disable interrupt */
3711 
3712 /* Bit 31 : Write '1' to disable interrupt for event PORT */
3713 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
3714 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
3715 #define GPIOTE_INTENCLR_PORT_Disabled (0x0UL) /*!< Read: Disabled */
3716 #define GPIOTE_INTENCLR_PORT_Enabled (0x1UL) /*!< Read: Enabled */
3717 #define GPIOTE_INTENCLR_PORT_Clear (0x1UL) /*!< Disable */
3718 
3719 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
3720 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
3721 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
3722 #define GPIOTE_INTENCLR_IN7_Disabled (0x0UL) /*!< Read: Disabled */
3723 #define GPIOTE_INTENCLR_IN7_Enabled (0x1UL) /*!< Read: Enabled */
3724 #define GPIOTE_INTENCLR_IN7_Clear (0x1UL) /*!< Disable */
3725 
3726 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
3727 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
3728 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
3729 #define GPIOTE_INTENCLR_IN6_Disabled (0x0UL) /*!< Read: Disabled */
3730 #define GPIOTE_INTENCLR_IN6_Enabled (0x1UL) /*!< Read: Enabled */
3731 #define GPIOTE_INTENCLR_IN6_Clear (0x1UL) /*!< Disable */
3732 
3733 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
3734 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
3735 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
3736 #define GPIOTE_INTENCLR_IN5_Disabled (0x0UL) /*!< Read: Disabled */
3737 #define GPIOTE_INTENCLR_IN5_Enabled (0x1UL) /*!< Read: Enabled */
3738 #define GPIOTE_INTENCLR_IN5_Clear (0x1UL) /*!< Disable */
3739 
3740 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
3741 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
3742 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
3743 #define GPIOTE_INTENCLR_IN4_Disabled (0x0UL) /*!< Read: Disabled */
3744 #define GPIOTE_INTENCLR_IN4_Enabled (0x1UL) /*!< Read: Enabled */
3745 #define GPIOTE_INTENCLR_IN4_Clear (0x1UL) /*!< Disable */
3746 
3747 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
3748 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
3749 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
3750 #define GPIOTE_INTENCLR_IN3_Disabled (0x0UL) /*!< Read: Disabled */
3751 #define GPIOTE_INTENCLR_IN3_Enabled (0x1UL) /*!< Read: Enabled */
3752 #define GPIOTE_INTENCLR_IN3_Clear (0x1UL) /*!< Disable */
3753 
3754 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
3755 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
3756 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
3757 #define GPIOTE_INTENCLR_IN2_Disabled (0x0UL) /*!< Read: Disabled */
3758 #define GPIOTE_INTENCLR_IN2_Enabled (0x1UL) /*!< Read: Enabled */
3759 #define GPIOTE_INTENCLR_IN2_Clear (0x1UL) /*!< Disable */
3760 
3761 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
3762 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
3763 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
3764 #define GPIOTE_INTENCLR_IN1_Disabled (0x0UL) /*!< Read: Disabled */
3765 #define GPIOTE_INTENCLR_IN1_Enabled (0x1UL) /*!< Read: Enabled */
3766 #define GPIOTE_INTENCLR_IN1_Clear (0x1UL) /*!< Disable */
3767 
3768 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
3769 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
3770 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
3771 #define GPIOTE_INTENCLR_IN0_Disabled (0x0UL) /*!< Read: Disabled */
3772 #define GPIOTE_INTENCLR_IN0_Enabled (0x1UL) /*!< Read: Enabled */
3773 #define GPIOTE_INTENCLR_IN0_Clear (0x1UL) /*!< Disable */
3774 
3775 /* Register: GPIOTE_CONFIG */
3776 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
3777 
3778 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
3779 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
3780 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
3781 #define GPIOTE_CONFIG_OUTINIT_Low (0x0UL) /*!< Task mode: Initial value of pin before task triggering is low */
3782 #define GPIOTE_CONFIG_OUTINIT_High (0x1UL) /*!< Task mode: Initial value of pin before task triggering is high */
3783 
3784 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
3785 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
3786 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
3787 #define GPIOTE_CONFIG_POLARITY_None (0x0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
3788 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
3789 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
3790 #define GPIOTE_CONFIG_POLARITY_Toggle (0x3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
3791 
3792 /* Bit 13 : Port number */
3793 #define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */
3794 #define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */
3795 
3796 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
3797 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
3798 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
3799 
3800 /* Bits 1..0 : Mode */
3801 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
3802 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
3803 #define GPIOTE_CONFIG_MODE_Disabled (0x0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
3804 #define GPIOTE_CONFIG_MODE_Event (0x1UL) /*!< Event mode */
3805 #define GPIOTE_CONFIG_MODE_Task (0x3UL) /*!< Task mode */
3806 
3807 
3808 /* Peripheral: I2S */
3809 /* Description: Inter-IC Sound */
3810 
3811 /* Register: I2S_TASKS_START */
3812 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
3813 
3814 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
3815 #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
3816 #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
3817 #define I2S_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
3818 
3819 /* Register: I2S_TASKS_STOP */
3820 /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
3821 
3822 /* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
3823 #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
3824 #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
3825 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
3826 
3827 /* Register: I2S_EVENTS_RXPTRUPD */
3828 /* Description: The RXD.PTR register has been copied to internal double-buffers.
3829       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
3830 
3831 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
3832       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
3833 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
3834 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
3835 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */
3836 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (0x1UL) /*!< Event generated */
3837 
3838 /* Register: I2S_EVENTS_STOPPED */
3839 /* Description: I2S transfer stopped. */
3840 
3841 /* Bit 0 : I2S transfer stopped. */
3842 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
3843 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
3844 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
3845 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
3846 
3847 /* Register: I2S_EVENTS_TXPTRUPD */
3848 /* Description: The TDX.PTR register has been copied to internal double-buffers.
3849       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
3850 
3851 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
3852       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
3853 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
3854 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
3855 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */
3856 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (0x1UL) /*!< Event generated */
3857 
3858 /* Register: I2S_INTEN */
3859 /* Description: Enable or disable interrupt */
3860 
3861 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
3862 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
3863 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
3864 #define I2S_INTEN_TXPTRUPD_Disabled (0x0UL) /*!< Disable */
3865 #define I2S_INTEN_TXPTRUPD_Enabled (0x1UL) /*!< Enable */
3866 
3867 /* Bit 2 : Enable or disable interrupt for event STOPPED */
3868 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
3869 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
3870 #define I2S_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
3871 #define I2S_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
3872 
3873 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
3874 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
3875 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
3876 #define I2S_INTEN_RXPTRUPD_Disabled (0x0UL) /*!< Disable */
3877 #define I2S_INTEN_RXPTRUPD_Enabled (0x1UL) /*!< Enable */
3878 
3879 /* Register: I2S_INTENSET */
3880 /* Description: Enable interrupt */
3881 
3882 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
3883 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
3884 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
3885 #define I2S_INTENSET_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
3886 #define I2S_INTENSET_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
3887 #define I2S_INTENSET_TXPTRUPD_Set (0x1UL) /*!< Enable */
3888 
3889 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
3890 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
3891 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
3892 #define I2S_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
3893 #define I2S_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
3894 #define I2S_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
3895 
3896 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
3897 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
3898 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
3899 #define I2S_INTENSET_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
3900 #define I2S_INTENSET_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
3901 #define I2S_INTENSET_RXPTRUPD_Set (0x1UL) /*!< Enable */
3902 
3903 /* Register: I2S_INTENCLR */
3904 /* Description: Disable interrupt */
3905 
3906 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
3907 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
3908 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
3909 #define I2S_INTENCLR_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
3910 #define I2S_INTENCLR_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
3911 #define I2S_INTENCLR_TXPTRUPD_Clear (0x1UL) /*!< Disable */
3912 
3913 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
3914 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
3915 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
3916 #define I2S_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
3917 #define I2S_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
3918 #define I2S_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
3919 
3920 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
3921 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
3922 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
3923 #define I2S_INTENCLR_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
3924 #define I2S_INTENCLR_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
3925 #define I2S_INTENCLR_RXPTRUPD_Clear (0x1UL) /*!< Disable */
3926 
3927 /* Register: I2S_ENABLE */
3928 /* Description: Enable I2S module. */
3929 
3930 /* Bit 0 : Enable I2S module. */
3931 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
3932 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
3933 #define I2S_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
3934 #define I2S_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */
3935 
3936 /* Register: I2S_CONFIG_MODE */
3937 /* Description: I2S mode. */
3938 
3939 /* Bit 0 : I2S mode. */
3940 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
3941 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
3942 #define I2S_CONFIG_MODE_MODE_Master (0x0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
3943 #define I2S_CONFIG_MODE_MODE_Slave (0x1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
3944 
3945 /* Register: I2S_CONFIG_RXEN */
3946 /* Description: Reception (RX) enable. */
3947 
3948 /* Bit 0 : Reception (RX) enable. */
3949 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
3950 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
3951 #define I2S_CONFIG_RXEN_RXEN_Disabled (0x0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
3952 #define I2S_CONFIG_RXEN_RXEN_Enabled (0x1UL) /*!< Reception enabled. */
3953 
3954 /* Register: I2S_CONFIG_TXEN */
3955 /* Description: Transmission (TX) enable. */
3956 
3957 /* Bit 0 : Transmission (TX) enable. */
3958 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
3959 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
3960 #define I2S_CONFIG_TXEN_TXEN_Disabled (0x0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
3961 #define I2S_CONFIG_TXEN_TXEN_Enabled (0x1UL) /*!< Transmission enabled. */
3962 
3963 /* Register: I2S_CONFIG_MCKEN */
3964 /* Description: Master clock generator enable. */
3965 
3966 /* Bit 0 : Master clock generator enable. */
3967 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
3968 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
3969 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0x0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
3970 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (0x1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
3971 
3972 /* Register: I2S_CONFIG_MCKFREQ */
3973 /* Description: Master clock generator frequency. */
3974 
3975 /* Bits 31..0 : Master clock generator frequency. */
3976 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
3977 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
3978 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
3979 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
3980 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
3981 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
3982 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
3983 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
3984 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
3985 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
3986 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
3987 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
3988 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
3989 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
3990 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
3991 
3992 /* Register: I2S_CONFIG_RATIO */
3993 /* Description: MCK / LRCK ratio. */
3994 
3995 /* Bits 3..0 : MCK / LRCK ratio. */
3996 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
3997 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
3998 #define I2S_CONFIG_RATIO_RATIO_32X (0x0UL) /*!< LRCK = MCK / 32 */
3999 #define I2S_CONFIG_RATIO_RATIO_48X (0x1UL) /*!< LRCK = MCK / 48 */
4000 #define I2S_CONFIG_RATIO_RATIO_64X (0x2UL) /*!< LRCK = MCK / 64 */
4001 #define I2S_CONFIG_RATIO_RATIO_96X (0x3UL) /*!< LRCK = MCK / 96 */
4002 #define I2S_CONFIG_RATIO_RATIO_128X (0x4UL) /*!< LRCK = MCK / 128 */
4003 #define I2S_CONFIG_RATIO_RATIO_192X (0x5UL) /*!< LRCK = MCK / 192 */
4004 #define I2S_CONFIG_RATIO_RATIO_256X (0x6UL) /*!< LRCK = MCK / 256 */
4005 #define I2S_CONFIG_RATIO_RATIO_384X (0x7UL) /*!< LRCK = MCK / 384 */
4006 #define I2S_CONFIG_RATIO_RATIO_512X (0x8UL) /*!< LRCK = MCK / 512 */
4007 
4008 /* Register: I2S_CONFIG_SWIDTH */
4009 /* Description: Sample width. */
4010 
4011 /* Bits 1..0 : Sample width. */
4012 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
4013 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
4014 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0x0UL) /*!< 8 bit. */
4015 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (0x1UL) /*!< 16 bit. */
4016 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (0x2UL) /*!< 24 bit. */
4017 
4018 /* Register: I2S_CONFIG_ALIGN */
4019 /* Description: Alignment of sample within a frame. */
4020 
4021 /* Bit 0 : Alignment of sample within a frame. */
4022 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
4023 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
4024 #define I2S_CONFIG_ALIGN_ALIGN_Left (0x0UL) /*!< Left-aligned. */
4025 #define I2S_CONFIG_ALIGN_ALIGN_Right (0x1UL) /*!< Right-aligned. */
4026 
4027 /* Register: I2S_CONFIG_FORMAT */
4028 /* Description: Frame format. */
4029 
4030 /* Bit 0 : Frame format. */
4031 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
4032 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
4033 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0x0UL) /*!< Original I2S format. */
4034 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (0x1UL) /*!< Alternate (left- or right-aligned) format. */
4035 
4036 /* Register: I2S_CONFIG_CHANNELS */
4037 /* Description: Enable channels. */
4038 
4039 /* Bits 1..0 : Enable channels. */
4040 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
4041 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
4042 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0x0UL) /*!< Stereo. */
4043 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (0x1UL) /*!< Left only. */
4044 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (0x2UL) /*!< Right only. */
4045 
4046 /* Register: I2S_RXD_PTR */
4047 /* Description: Receive buffer RAM start address. */
4048 
4049 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
4050 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
4051 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
4052 
4053 /* Register: I2S_TXD_PTR */
4054 /* Description: Transmit buffer RAM start address. */
4055 
4056 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
4057 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
4058 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
4059 
4060 /* Register: I2S_RXTXD_MAXCNT */
4061 /* Description: Size of RXD and TXD buffers. */
4062 
4063 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
4064 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
4065 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
4066 
4067 /* Register: I2S_PSEL_MCK */
4068 /* Description: Pin select for MCK signal. */
4069 
4070 /* Bit 31 : Connection */
4071 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4072 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4073 #define I2S_PSEL_MCK_CONNECT_Connected (0x0UL) /*!< Connect */
4074 #define I2S_PSEL_MCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
4075 
4076 /* Bit 5 : Port number */
4077 #define I2S_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */
4078 #define I2S_PSEL_MCK_PORT_Msk (0x1UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */
4079 
4080 /* Bits 4..0 : Pin number */
4081 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
4082 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
4083 
4084 /* Register: I2S_PSEL_SCK */
4085 /* Description: Pin select for SCK signal. */
4086 
4087 /* Bit 31 : Connection */
4088 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4089 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4090 #define I2S_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
4091 #define I2S_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
4092 
4093 /* Bit 5 : Port number */
4094 #define I2S_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
4095 #define I2S_PSEL_SCK_PORT_Msk (0x1UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
4096 
4097 /* Bits 4..0 : Pin number */
4098 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
4099 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
4100 
4101 /* Register: I2S_PSEL_LRCK */
4102 /* Description: Pin select for LRCK signal. */
4103 
4104 /* Bit 31 : Connection */
4105 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4106 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4107 #define I2S_PSEL_LRCK_CONNECT_Connected (0x0UL) /*!< Connect */
4108 #define I2S_PSEL_LRCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
4109 
4110 /* Bit 5 : Port number */
4111 #define I2S_PSEL_LRCK_PORT_Pos (5UL) /*!< Position of PORT field. */
4112 #define I2S_PSEL_LRCK_PORT_Msk (0x1UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */
4113 
4114 /* Bits 4..0 : Pin number */
4115 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
4116 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
4117 
4118 /* Register: I2S_PSEL_SDIN */
4119 /* Description: Pin select for SDIN signal. */
4120 
4121 /* Bit 31 : Connection */
4122 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4123 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4124 #define I2S_PSEL_SDIN_CONNECT_Connected (0x0UL) /*!< Connect */
4125 #define I2S_PSEL_SDIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
4126 
4127 /* Bit 5 : Port number */
4128 #define I2S_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */
4129 #define I2S_PSEL_SDIN_PORT_Msk (0x1UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */
4130 
4131 /* Bits 4..0 : Pin number */
4132 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
4133 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
4134 
4135 /* Register: I2S_PSEL_SDOUT */
4136 /* Description: Pin select for SDOUT signal. */
4137 
4138 /* Bit 31 : Connection */
4139 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4140 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4141 #define I2S_PSEL_SDOUT_CONNECT_Connected (0x0UL) /*!< Connect */
4142 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
4143 
4144 /* Bit 5 : Port number */
4145 #define I2S_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */
4146 #define I2S_PSEL_SDOUT_PORT_Msk (0x1UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */
4147 
4148 /* Bits 4..0 : Pin number */
4149 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
4150 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
4151 
4152 
4153 /* Peripheral: LPCOMP */
4154 /* Description: Low-power comparator */
4155 
4156 /* Register: LPCOMP_TASKS_START */
4157 /* Description: Start comparator */
4158 
4159 /* Bit 0 : Start comparator */
4160 #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
4161 #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
4162 #define LPCOMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
4163 
4164 /* Register: LPCOMP_TASKS_STOP */
4165 /* Description: Stop comparator */
4166 
4167 /* Bit 0 : Stop comparator */
4168 #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
4169 #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
4170 #define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
4171 
4172 /* Register: LPCOMP_TASKS_SAMPLE */
4173 /* Description: Sample comparator value */
4174 
4175 /* Bit 0 : Sample comparator value */
4176 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
4177 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
4178 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */
4179 
4180 /* Register: LPCOMP_EVENTS_READY */
4181 /* Description: LPCOMP is ready and output is valid */
4182 
4183 /* Bit 0 : LPCOMP is ready and output is valid */
4184 #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
4185 #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
4186 #define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */
4187 #define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */
4188 
4189 /* Register: LPCOMP_EVENTS_DOWN */
4190 /* Description: Downward crossing */
4191 
4192 /* Bit 0 : Downward crossing */
4193 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
4194 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
4195 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated */
4196 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated */
4197 
4198 /* Register: LPCOMP_EVENTS_UP */
4199 /* Description: Upward crossing */
4200 
4201 /* Bit 0 : Upward crossing */
4202 #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
4203 #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
4204 #define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated */
4205 #define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated */
4206 
4207 /* Register: LPCOMP_EVENTS_CROSS */
4208 /* Description: Downward or upward crossing */
4209 
4210 /* Bit 0 : Downward or upward crossing */
4211 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
4212 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
4213 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated */
4214 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated */
4215 
4216 /* Register: LPCOMP_SHORTS */
4217 /* Description: Shortcuts between local events and tasks */
4218 
4219 /* Bit 4 : Shortcut between event CROSS and task STOP */
4220 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
4221 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
4222 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0x0UL) /*!< Disable shortcut */
4223 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (0x1UL) /*!< Enable shortcut */
4224 
4225 /* Bit 3 : Shortcut between event UP and task STOP */
4226 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
4227 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
4228 #define LPCOMP_SHORTS_UP_STOP_Disabled (0x0UL) /*!< Disable shortcut */
4229 #define LPCOMP_SHORTS_UP_STOP_Enabled (0x1UL) /*!< Enable shortcut */
4230 
4231 /* Bit 2 : Shortcut between event DOWN and task STOP */
4232 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
4233 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
4234 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0x0UL) /*!< Disable shortcut */
4235 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (0x1UL) /*!< Enable shortcut */
4236 
4237 /* Bit 1 : Shortcut between event READY and task STOP */
4238 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
4239 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
4240 #define LPCOMP_SHORTS_READY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
4241 #define LPCOMP_SHORTS_READY_STOP_Enabled (0x1UL) /*!< Enable shortcut */
4242 
4243 /* Bit 0 : Shortcut between event READY and task SAMPLE */
4244 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
4245 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
4246 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut */
4247 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut */
4248 
4249 /* Register: LPCOMP_INTENSET */
4250 /* Description: Enable interrupt */
4251 
4252 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
4253 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
4254 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
4255 #define LPCOMP_INTENSET_CROSS_Disabled (0x0UL) /*!< Read: Disabled */
4256 #define LPCOMP_INTENSET_CROSS_Enabled (0x1UL) /*!< Read: Enabled */
4257 #define LPCOMP_INTENSET_CROSS_Set (0x1UL) /*!< Enable */
4258 
4259 /* Bit 2 : Write '1' to enable interrupt for event UP */
4260 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
4261 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
4262 #define LPCOMP_INTENSET_UP_Disabled (0x0UL) /*!< Read: Disabled */
4263 #define LPCOMP_INTENSET_UP_Enabled (0x1UL) /*!< Read: Enabled */
4264 #define LPCOMP_INTENSET_UP_Set (0x1UL) /*!< Enable */
4265 
4266 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
4267 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
4268 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
4269 #define LPCOMP_INTENSET_DOWN_Disabled (0x0UL) /*!< Read: Disabled */
4270 #define LPCOMP_INTENSET_DOWN_Enabled (0x1UL) /*!< Read: Enabled */
4271 #define LPCOMP_INTENSET_DOWN_Set (0x1UL) /*!< Enable */
4272 
4273 /* Bit 0 : Write '1' to enable interrupt for event READY */
4274 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
4275 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
4276 #define LPCOMP_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */
4277 #define LPCOMP_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */
4278 #define LPCOMP_INTENSET_READY_Set (0x1UL) /*!< Enable */
4279 
4280 /* Register: LPCOMP_INTENCLR */
4281 /* Description: Disable interrupt */
4282 
4283 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
4284 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
4285 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
4286 #define LPCOMP_INTENCLR_CROSS_Disabled (0x0UL) /*!< Read: Disabled */
4287 #define LPCOMP_INTENCLR_CROSS_Enabled (0x1UL) /*!< Read: Enabled */
4288 #define LPCOMP_INTENCLR_CROSS_Clear (0x1UL) /*!< Disable */
4289 
4290 /* Bit 2 : Write '1' to disable interrupt for event UP */
4291 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
4292 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
4293 #define LPCOMP_INTENCLR_UP_Disabled (0x0UL) /*!< Read: Disabled */
4294 #define LPCOMP_INTENCLR_UP_Enabled (0x1UL) /*!< Read: Enabled */
4295 #define LPCOMP_INTENCLR_UP_Clear (0x1UL) /*!< Disable */
4296 
4297 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
4298 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
4299 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
4300 #define LPCOMP_INTENCLR_DOWN_Disabled (0x0UL) /*!< Read: Disabled */
4301 #define LPCOMP_INTENCLR_DOWN_Enabled (0x1UL) /*!< Read: Enabled */
4302 #define LPCOMP_INTENCLR_DOWN_Clear (0x1UL) /*!< Disable */
4303 
4304 /* Bit 0 : Write '1' to disable interrupt for event READY */
4305 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
4306 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
4307 #define LPCOMP_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */
4308 #define LPCOMP_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */
4309 #define LPCOMP_INTENCLR_READY_Clear (0x1UL) /*!< Disable */
4310 
4311 /* Register: LPCOMP_RESULT */
4312 /* Description: Compare result */
4313 
4314 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
4315 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
4316 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
4317 #define LPCOMP_RESULT_RESULT_Below (0x0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-) */
4318 #define LPCOMP_RESULT_RESULT_Above (0x1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-) */
4319 
4320 /* Register: LPCOMP_ENABLE */
4321 /* Description: Enable LPCOMP */
4322 
4323 /* Bits 1..0 : Enable or disable LPCOMP */
4324 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
4325 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
4326 #define LPCOMP_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
4327 #define LPCOMP_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */
4328 
4329 /* Register: LPCOMP_PSEL */
4330 /* Description: Input pin select */
4331 
4332 /* Bits 2..0 : Analog pin select */
4333 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
4334 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
4335 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0x0UL) /*!< AIN0 selected as analog input */
4336 #define LPCOMP_PSEL_PSEL_AnalogInput1 (0x1UL) /*!< AIN1 selected as analog input */
4337 #define LPCOMP_PSEL_PSEL_AnalogInput2 (0x2UL) /*!< AIN2 selected as analog input */
4338 #define LPCOMP_PSEL_PSEL_AnalogInput3 (0x3UL) /*!< AIN3 selected as analog input */
4339 #define LPCOMP_PSEL_PSEL_AnalogInput4 (0x4UL) /*!< AIN4 selected as analog input */
4340 #define LPCOMP_PSEL_PSEL_AnalogInput5 (0x5UL) /*!< AIN5 selected as analog input */
4341 #define LPCOMP_PSEL_PSEL_AnalogInput6 (0x6UL) /*!< AIN6 selected as analog input */
4342 #define LPCOMP_PSEL_PSEL_AnalogInput7 (0x7UL) /*!< AIN7 selected as analog input */
4343 
4344 /* Register: LPCOMP_REFSEL */
4345 /* Description: Reference select */
4346 
4347 /* Bits 3..0 : Reference select */
4348 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
4349 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
4350 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0x0UL) /*!< VDD * 1/8 selected as reference */
4351 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (0x1UL) /*!< VDD * 2/8 selected as reference */
4352 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (0x2UL) /*!< VDD * 3/8 selected as reference */
4353 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (0x3UL) /*!< VDD * 4/8 selected as reference */
4354 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (0x4UL) /*!< VDD * 5/8 selected as reference */
4355 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (0x5UL) /*!< VDD * 6/8 selected as reference */
4356 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (0x6UL) /*!< VDD * 7/8 selected as reference */
4357 #define LPCOMP_REFSEL_REFSEL_ARef (0x7UL) /*!< External analog reference selected */
4358 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (0x8UL) /*!< VDD * 1/16 selected as reference */
4359 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (0x9UL) /*!< VDD * 3/16 selected as reference */
4360 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (0xAUL) /*!< VDD * 5/16 selected as reference */
4361 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (0xBUL) /*!< VDD * 7/16 selected as reference */
4362 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (0xCUL) /*!< VDD * 9/16 selected as reference */
4363 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (0xDUL) /*!< VDD * 11/16 selected as reference */
4364 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (0xEUL) /*!< VDD * 13/16 selected as reference */
4365 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (0xFUL) /*!< VDD * 15/16 selected as reference */
4366 
4367 /* Register: LPCOMP_EXTREFSEL */
4368 /* Description: External reference select */
4369 
4370 /* Bit 0 : External analog reference select */
4371 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
4372 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
4373 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0x0UL) /*!< Use AIN0 as external analog reference */
4374 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (0x1UL) /*!< Use AIN1 as external analog reference */
4375 
4376 /* Register: LPCOMP_ANADETECT */
4377 /* Description: Analog detect configuration */
4378 
4379 /* Bits 1..0 : Analog detect configuration */
4380 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
4381 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
4382 #define LPCOMP_ANADETECT_ANADETECT_Cross (0x0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
4383 #define LPCOMP_ANADETECT_ANADETECT_Up (0x1UL) /*!< Generate ANADETECT on upward crossing only */
4384 #define LPCOMP_ANADETECT_ANADETECT_Down (0x2UL) /*!< Generate ANADETECT on downward crossing only */
4385 
4386 /* Register: LPCOMP_HYST */
4387 /* Description: Comparator hysteresis enable */
4388 
4389 /* Bit 0 : Comparator hysteresis enable */
4390 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
4391 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
4392 #define LPCOMP_HYST_HYST_Disabled (0x0UL) /*!< Comparator hysteresis disabled */
4393 #define LPCOMP_HYST_HYST_Enabled (0x1UL) /*!< Comparator hysteresis enabled */
4394 
4395 
4396 /* Peripheral: MWU */
4397 /* Description: Memory Watch Unit */
4398 
4399 /* Register: MWU_EVENTS_REGION_WA */
4400 /* Description: Description cluster: Write access to region n detected */
4401 
4402 /* Bit 0 : Write access to region n detected */
4403 #define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
4404 #define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */
4405 #define MWU_EVENTS_REGION_WA_WA_NotGenerated (0x0UL) /*!< Event not generated */
4406 #define MWU_EVENTS_REGION_WA_WA_Generated (0x1UL) /*!< Event generated */
4407 
4408 /* Register: MWU_EVENTS_REGION_RA */
4409 /* Description: Description cluster: Read access to region n detected */
4410 
4411 /* Bit 0 : Read access to region n detected */
4412 #define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
4413 #define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */
4414 #define MWU_EVENTS_REGION_RA_RA_NotGenerated (0x0UL) /*!< Event not generated */
4415 #define MWU_EVENTS_REGION_RA_RA_Generated (0x1UL) /*!< Event generated */
4416 
4417 /* Register: MWU_EVENTS_PREGION_WA */
4418 /* Description: Description cluster: Write access to peripheral region n detected */
4419 
4420 /* Bit 0 : Write access to peripheral region n detected */
4421 #define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
4422 #define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */
4423 #define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0x0UL) /*!< Event not generated */
4424 #define MWU_EVENTS_PREGION_WA_WA_Generated (0x1UL) /*!< Event generated */
4425 
4426 /* Register: MWU_EVENTS_PREGION_RA */
4427 /* Description: Description cluster: Read access to peripheral region n detected */
4428 
4429 /* Bit 0 : Read access to peripheral region n detected */
4430 #define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
4431 #define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */
4432 #define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0x0UL) /*!< Event not generated */
4433 #define MWU_EVENTS_PREGION_RA_RA_Generated (0x1UL) /*!< Event generated */
4434 
4435 /* Register: MWU_INTEN */
4436 /* Description: Enable or disable interrupt */
4437 
4438 /* Bit 27 : Enable or disable interrupt for event PREGION1RA */
4439 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
4440 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
4441 #define MWU_INTEN_PREGION1RA_Disabled (0x0UL) /*!< Disable */
4442 #define MWU_INTEN_PREGION1RA_Enabled (0x1UL) /*!< Enable */
4443 
4444 /* Bit 26 : Enable or disable interrupt for event PREGION1WA */
4445 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
4446 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
4447 #define MWU_INTEN_PREGION1WA_Disabled (0x0UL) /*!< Disable */
4448 #define MWU_INTEN_PREGION1WA_Enabled (0x1UL) /*!< Enable */
4449 
4450 /* Bit 25 : Enable or disable interrupt for event PREGION0RA */
4451 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
4452 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
4453 #define MWU_INTEN_PREGION0RA_Disabled (0x0UL) /*!< Disable */
4454 #define MWU_INTEN_PREGION0RA_Enabled (0x1UL) /*!< Enable */
4455 
4456 /* Bit 24 : Enable or disable interrupt for event PREGION0WA */
4457 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
4458 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
4459 #define MWU_INTEN_PREGION0WA_Disabled (0x0UL) /*!< Disable */
4460 #define MWU_INTEN_PREGION0WA_Enabled (0x1UL) /*!< Enable */
4461 
4462 /* Bit 7 : Enable or disable interrupt for event REGION3RA */
4463 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
4464 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
4465 #define MWU_INTEN_REGION3RA_Disabled (0x0UL) /*!< Disable */
4466 #define MWU_INTEN_REGION3RA_Enabled (0x1UL) /*!< Enable */
4467 
4468 /* Bit 6 : Enable or disable interrupt for event REGION3WA */
4469 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
4470 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
4471 #define MWU_INTEN_REGION3WA_Disabled (0x0UL) /*!< Disable */
4472 #define MWU_INTEN_REGION3WA_Enabled (0x1UL) /*!< Enable */
4473 
4474 /* Bit 5 : Enable or disable interrupt for event REGION2RA */
4475 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
4476 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
4477 #define MWU_INTEN_REGION2RA_Disabled (0x0UL) /*!< Disable */
4478 #define MWU_INTEN_REGION2RA_Enabled (0x1UL) /*!< Enable */
4479 
4480 /* Bit 4 : Enable or disable interrupt for event REGION2WA */
4481 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
4482 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
4483 #define MWU_INTEN_REGION2WA_Disabled (0x0UL) /*!< Disable */
4484 #define MWU_INTEN_REGION2WA_Enabled (0x1UL) /*!< Enable */
4485 
4486 /* Bit 3 : Enable or disable interrupt for event REGION1RA */
4487 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
4488 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
4489 #define MWU_INTEN_REGION1RA_Disabled (0x0UL) /*!< Disable */
4490 #define MWU_INTEN_REGION1RA_Enabled (0x1UL) /*!< Enable */
4491 
4492 /* Bit 2 : Enable or disable interrupt for event REGION1WA */
4493 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
4494 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
4495 #define MWU_INTEN_REGION1WA_Disabled (0x0UL) /*!< Disable */
4496 #define MWU_INTEN_REGION1WA_Enabled (0x1UL) /*!< Enable */
4497 
4498 /* Bit 1 : Enable or disable interrupt for event REGION0RA */
4499 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
4500 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
4501 #define MWU_INTEN_REGION0RA_Disabled (0x0UL) /*!< Disable */
4502 #define MWU_INTEN_REGION0RA_Enabled (0x1UL) /*!< Enable */
4503 
4504 /* Bit 0 : Enable or disable interrupt for event REGION0WA */
4505 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
4506 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
4507 #define MWU_INTEN_REGION0WA_Disabled (0x0UL) /*!< Disable */
4508 #define MWU_INTEN_REGION0WA_Enabled (0x1UL) /*!< Enable */
4509 
4510 /* Register: MWU_INTENSET */
4511 /* Description: Enable interrupt */
4512 
4513 /* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
4514 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
4515 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
4516 #define MWU_INTENSET_PREGION1RA_Disabled (0x0UL) /*!< Read: Disabled */
4517 #define MWU_INTENSET_PREGION1RA_Enabled (0x1UL) /*!< Read: Enabled */
4518 #define MWU_INTENSET_PREGION1RA_Set (0x1UL) /*!< Enable */
4519 
4520 /* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
4521 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
4522 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
4523 #define MWU_INTENSET_PREGION1WA_Disabled (0x0UL) /*!< Read: Disabled */
4524 #define MWU_INTENSET_PREGION1WA_Enabled (0x1UL) /*!< Read: Enabled */
4525 #define MWU_INTENSET_PREGION1WA_Set (0x1UL) /*!< Enable */
4526 
4527 /* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
4528 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
4529 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
4530 #define MWU_INTENSET_PREGION0RA_Disabled (0x0UL) /*!< Read: Disabled */
4531 #define MWU_INTENSET_PREGION0RA_Enabled (0x1UL) /*!< Read: Enabled */
4532 #define MWU_INTENSET_PREGION0RA_Set (0x1UL) /*!< Enable */
4533 
4534 /* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
4535 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
4536 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
4537 #define MWU_INTENSET_PREGION0WA_Disabled (0x0UL) /*!< Read: Disabled */
4538 #define MWU_INTENSET_PREGION0WA_Enabled (0x1UL) /*!< Read: Enabled */
4539 #define MWU_INTENSET_PREGION0WA_Set (0x1UL) /*!< Enable */
4540 
4541 /* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
4542 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
4543 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
4544 #define MWU_INTENSET_REGION3RA_Disabled (0x0UL) /*!< Read: Disabled */
4545 #define MWU_INTENSET_REGION3RA_Enabled (0x1UL) /*!< Read: Enabled */
4546 #define MWU_INTENSET_REGION3RA_Set (0x1UL) /*!< Enable */
4547 
4548 /* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
4549 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
4550 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
4551 #define MWU_INTENSET_REGION3WA_Disabled (0x0UL) /*!< Read: Disabled */
4552 #define MWU_INTENSET_REGION3WA_Enabled (0x1UL) /*!< Read: Enabled */
4553 #define MWU_INTENSET_REGION3WA_Set (0x1UL) /*!< Enable */
4554 
4555 /* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
4556 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
4557 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
4558 #define MWU_INTENSET_REGION2RA_Disabled (0x0UL) /*!< Read: Disabled */
4559 #define MWU_INTENSET_REGION2RA_Enabled (0x1UL) /*!< Read: Enabled */
4560 #define MWU_INTENSET_REGION2RA_Set (0x1UL) /*!< Enable */
4561 
4562 /* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
4563 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
4564 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
4565 #define MWU_INTENSET_REGION2WA_Disabled (0x0UL) /*!< Read: Disabled */
4566 #define MWU_INTENSET_REGION2WA_Enabled (0x1UL) /*!< Read: Enabled */
4567 #define MWU_INTENSET_REGION2WA_Set (0x1UL) /*!< Enable */
4568 
4569 /* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
4570 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
4571 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
4572 #define MWU_INTENSET_REGION1RA_Disabled (0x0UL) /*!< Read: Disabled */
4573 #define MWU_INTENSET_REGION1RA_Enabled (0x1UL) /*!< Read: Enabled */
4574 #define MWU_INTENSET_REGION1RA_Set (0x1UL) /*!< Enable */
4575 
4576 /* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
4577 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
4578 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
4579 #define MWU_INTENSET_REGION1WA_Disabled (0x0UL) /*!< Read: Disabled */
4580 #define MWU_INTENSET_REGION1WA_Enabled (0x1UL) /*!< Read: Enabled */
4581 #define MWU_INTENSET_REGION1WA_Set (0x1UL) /*!< Enable */
4582 
4583 /* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
4584 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
4585 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
4586 #define MWU_INTENSET_REGION0RA_Disabled (0x0UL) /*!< Read: Disabled */
4587 #define MWU_INTENSET_REGION0RA_Enabled (0x1UL) /*!< Read: Enabled */
4588 #define MWU_INTENSET_REGION0RA_Set (0x1UL) /*!< Enable */
4589 
4590 /* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
4591 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
4592 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
4593 #define MWU_INTENSET_REGION0WA_Disabled (0x0UL) /*!< Read: Disabled */
4594 #define MWU_INTENSET_REGION0WA_Enabled (0x1UL) /*!< Read: Enabled */
4595 #define MWU_INTENSET_REGION0WA_Set (0x1UL) /*!< Enable */
4596 
4597 /* Register: MWU_INTENCLR */
4598 /* Description: Disable interrupt */
4599 
4600 /* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
4601 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
4602 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
4603 #define MWU_INTENCLR_PREGION1RA_Disabled (0x0UL) /*!< Read: Disabled */
4604 #define MWU_INTENCLR_PREGION1RA_Enabled (0x1UL) /*!< Read: Enabled */
4605 #define MWU_INTENCLR_PREGION1RA_Clear (0x1UL) /*!< Disable */
4606 
4607 /* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
4608 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
4609 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
4610 #define MWU_INTENCLR_PREGION1WA_Disabled (0x0UL) /*!< Read: Disabled */
4611 #define MWU_INTENCLR_PREGION1WA_Enabled (0x1UL) /*!< Read: Enabled */
4612 #define MWU_INTENCLR_PREGION1WA_Clear (0x1UL) /*!< Disable */
4613 
4614 /* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
4615 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
4616 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
4617 #define MWU_INTENCLR_PREGION0RA_Disabled (0x0UL) /*!< Read: Disabled */
4618 #define MWU_INTENCLR_PREGION0RA_Enabled (0x1UL) /*!< Read: Enabled */
4619 #define MWU_INTENCLR_PREGION0RA_Clear (0x1UL) /*!< Disable */
4620 
4621 /* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
4622 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
4623 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
4624 #define MWU_INTENCLR_PREGION0WA_Disabled (0x0UL) /*!< Read: Disabled */
4625 #define MWU_INTENCLR_PREGION0WA_Enabled (0x1UL) /*!< Read: Enabled */
4626 #define MWU_INTENCLR_PREGION0WA_Clear (0x1UL) /*!< Disable */
4627 
4628 /* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
4629 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
4630 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
4631 #define MWU_INTENCLR_REGION3RA_Disabled (0x0UL) /*!< Read: Disabled */
4632 #define MWU_INTENCLR_REGION3RA_Enabled (0x1UL) /*!< Read: Enabled */
4633 #define MWU_INTENCLR_REGION3RA_Clear (0x1UL) /*!< Disable */
4634 
4635 /* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
4636 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
4637 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
4638 #define MWU_INTENCLR_REGION3WA_Disabled (0x0UL) /*!< Read: Disabled */
4639 #define MWU_INTENCLR_REGION3WA_Enabled (0x1UL) /*!< Read: Enabled */
4640 #define MWU_INTENCLR_REGION3WA_Clear (0x1UL) /*!< Disable */
4641 
4642 /* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
4643 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
4644 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
4645 #define MWU_INTENCLR_REGION2RA_Disabled (0x0UL) /*!< Read: Disabled */
4646 #define MWU_INTENCLR_REGION2RA_Enabled (0x1UL) /*!< Read: Enabled */
4647 #define MWU_INTENCLR_REGION2RA_Clear (0x1UL) /*!< Disable */
4648 
4649 /* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
4650 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
4651 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
4652 #define MWU_INTENCLR_REGION2WA_Disabled (0x0UL) /*!< Read: Disabled */
4653 #define MWU_INTENCLR_REGION2WA_Enabled (0x1UL) /*!< Read: Enabled */
4654 #define MWU_INTENCLR_REGION2WA_Clear (0x1UL) /*!< Disable */
4655 
4656 /* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
4657 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
4658 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
4659 #define MWU_INTENCLR_REGION1RA_Disabled (0x0UL) /*!< Read: Disabled */
4660 #define MWU_INTENCLR_REGION1RA_Enabled (0x1UL) /*!< Read: Enabled */
4661 #define MWU_INTENCLR_REGION1RA_Clear (0x1UL) /*!< Disable */
4662 
4663 /* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
4664 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
4665 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
4666 #define MWU_INTENCLR_REGION1WA_Disabled (0x0UL) /*!< Read: Disabled */
4667 #define MWU_INTENCLR_REGION1WA_Enabled (0x1UL) /*!< Read: Enabled */
4668 #define MWU_INTENCLR_REGION1WA_Clear (0x1UL) /*!< Disable */
4669 
4670 /* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
4671 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
4672 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
4673 #define MWU_INTENCLR_REGION0RA_Disabled (0x0UL) /*!< Read: Disabled */
4674 #define MWU_INTENCLR_REGION0RA_Enabled (0x1UL) /*!< Read: Enabled */
4675 #define MWU_INTENCLR_REGION0RA_Clear (0x1UL) /*!< Disable */
4676 
4677 /* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
4678 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
4679 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
4680 #define MWU_INTENCLR_REGION0WA_Disabled (0x0UL) /*!< Read: Disabled */
4681 #define MWU_INTENCLR_REGION0WA_Enabled (0x1UL) /*!< Read: Enabled */
4682 #define MWU_INTENCLR_REGION0WA_Clear (0x1UL) /*!< Disable */
4683 
4684 /* Register: MWU_NMIEN */
4685 /* Description: Enable or disable interrupt */
4686 
4687 /* Bit 27 : Enable or disable interrupt for event PREGION1RA */
4688 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
4689 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
4690 #define MWU_NMIEN_PREGION1RA_Disabled (0x0UL) /*!< Disable */
4691 #define MWU_NMIEN_PREGION1RA_Enabled (0x1UL) /*!< Enable */
4692 
4693 /* Bit 26 : Enable or disable interrupt for event PREGION1WA */
4694 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
4695 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
4696 #define MWU_NMIEN_PREGION1WA_Disabled (0x0UL) /*!< Disable */
4697 #define MWU_NMIEN_PREGION1WA_Enabled (0x1UL) /*!< Enable */
4698 
4699 /* Bit 25 : Enable or disable interrupt for event PREGION0RA */
4700 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
4701 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
4702 #define MWU_NMIEN_PREGION0RA_Disabled (0x0UL) /*!< Disable */
4703 #define MWU_NMIEN_PREGION0RA_Enabled (0x1UL) /*!< Enable */
4704 
4705 /* Bit 24 : Enable or disable interrupt for event PREGION0WA */
4706 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
4707 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
4708 #define MWU_NMIEN_PREGION0WA_Disabled (0x0UL) /*!< Disable */
4709 #define MWU_NMIEN_PREGION0WA_Enabled (0x1UL) /*!< Enable */
4710 
4711 /* Bit 7 : Enable or disable interrupt for event REGION3RA */
4712 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
4713 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
4714 #define MWU_NMIEN_REGION3RA_Disabled (0x0UL) /*!< Disable */
4715 #define MWU_NMIEN_REGION3RA_Enabled (0x1UL) /*!< Enable */
4716 
4717 /* Bit 6 : Enable or disable interrupt for event REGION3WA */
4718 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
4719 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
4720 #define MWU_NMIEN_REGION3WA_Disabled (0x0UL) /*!< Disable */
4721 #define MWU_NMIEN_REGION3WA_Enabled (0x1UL) /*!< Enable */
4722 
4723 /* Bit 5 : Enable or disable interrupt for event REGION2RA */
4724 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
4725 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
4726 #define MWU_NMIEN_REGION2RA_Disabled (0x0UL) /*!< Disable */
4727 #define MWU_NMIEN_REGION2RA_Enabled (0x1UL) /*!< Enable */
4728 
4729 /* Bit 4 : Enable or disable interrupt for event REGION2WA */
4730 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
4731 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
4732 #define MWU_NMIEN_REGION2WA_Disabled (0x0UL) /*!< Disable */
4733 #define MWU_NMIEN_REGION2WA_Enabled (0x1UL) /*!< Enable */
4734 
4735 /* Bit 3 : Enable or disable interrupt for event REGION1RA */
4736 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
4737 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
4738 #define MWU_NMIEN_REGION1RA_Disabled (0x0UL) /*!< Disable */
4739 #define MWU_NMIEN_REGION1RA_Enabled (0x1UL) /*!< Enable */
4740 
4741 /* Bit 2 : Enable or disable interrupt for event REGION1WA */
4742 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
4743 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
4744 #define MWU_NMIEN_REGION1WA_Disabled (0x0UL) /*!< Disable */
4745 #define MWU_NMIEN_REGION1WA_Enabled (0x1UL) /*!< Enable */
4746 
4747 /* Bit 1 : Enable or disable interrupt for event REGION0RA */
4748 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
4749 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
4750 #define MWU_NMIEN_REGION0RA_Disabled (0x0UL) /*!< Disable */
4751 #define MWU_NMIEN_REGION0RA_Enabled (0x1UL) /*!< Enable */
4752 
4753 /* Bit 0 : Enable or disable interrupt for event REGION0WA */
4754 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
4755 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
4756 #define MWU_NMIEN_REGION0WA_Disabled (0x0UL) /*!< Disable */
4757 #define MWU_NMIEN_REGION0WA_Enabled (0x1UL) /*!< Enable */
4758 
4759 /* Register: MWU_NMIENSET */
4760 /* Description: Enable interrupt */
4761 
4762 /* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
4763 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
4764 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
4765 #define MWU_NMIENSET_PREGION1RA_Disabled (0x0UL) /*!< Read: Disabled */
4766 #define MWU_NMIENSET_PREGION1RA_Enabled (0x1UL) /*!< Read: Enabled */
4767 #define MWU_NMIENSET_PREGION1RA_Set (0x1UL) /*!< Enable */
4768 
4769 /* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
4770 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
4771 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
4772 #define MWU_NMIENSET_PREGION1WA_Disabled (0x0UL) /*!< Read: Disabled */
4773 #define MWU_NMIENSET_PREGION1WA_Enabled (0x1UL) /*!< Read: Enabled */
4774 #define MWU_NMIENSET_PREGION1WA_Set (0x1UL) /*!< Enable */
4775 
4776 /* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
4777 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
4778 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
4779 #define MWU_NMIENSET_PREGION0RA_Disabled (0x0UL) /*!< Read: Disabled */
4780 #define MWU_NMIENSET_PREGION0RA_Enabled (0x1UL) /*!< Read: Enabled */
4781 #define MWU_NMIENSET_PREGION0RA_Set (0x1UL) /*!< Enable */
4782 
4783 /* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
4784 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
4785 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
4786 #define MWU_NMIENSET_PREGION0WA_Disabled (0x0UL) /*!< Read: Disabled */
4787 #define MWU_NMIENSET_PREGION0WA_Enabled (0x1UL) /*!< Read: Enabled */
4788 #define MWU_NMIENSET_PREGION0WA_Set (0x1UL) /*!< Enable */
4789 
4790 /* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
4791 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
4792 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
4793 #define MWU_NMIENSET_REGION3RA_Disabled (0x0UL) /*!< Read: Disabled */
4794 #define MWU_NMIENSET_REGION3RA_Enabled (0x1UL) /*!< Read: Enabled */
4795 #define MWU_NMIENSET_REGION3RA_Set (0x1UL) /*!< Enable */
4796 
4797 /* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
4798 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
4799 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
4800 #define MWU_NMIENSET_REGION3WA_Disabled (0x0UL) /*!< Read: Disabled */
4801 #define MWU_NMIENSET_REGION3WA_Enabled (0x1UL) /*!< Read: Enabled */
4802 #define MWU_NMIENSET_REGION3WA_Set (0x1UL) /*!< Enable */
4803 
4804 /* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
4805 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
4806 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
4807 #define MWU_NMIENSET_REGION2RA_Disabled (0x0UL) /*!< Read: Disabled */
4808 #define MWU_NMIENSET_REGION2RA_Enabled (0x1UL) /*!< Read: Enabled */
4809 #define MWU_NMIENSET_REGION2RA_Set (0x1UL) /*!< Enable */
4810 
4811 /* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
4812 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
4813 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
4814 #define MWU_NMIENSET_REGION2WA_Disabled (0x0UL) /*!< Read: Disabled */
4815 #define MWU_NMIENSET_REGION2WA_Enabled (0x1UL) /*!< Read: Enabled */
4816 #define MWU_NMIENSET_REGION2WA_Set (0x1UL) /*!< Enable */
4817 
4818 /* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
4819 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
4820 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
4821 #define MWU_NMIENSET_REGION1RA_Disabled (0x0UL) /*!< Read: Disabled */
4822 #define MWU_NMIENSET_REGION1RA_Enabled (0x1UL) /*!< Read: Enabled */
4823 #define MWU_NMIENSET_REGION1RA_Set (0x1UL) /*!< Enable */
4824 
4825 /* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
4826 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
4827 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
4828 #define MWU_NMIENSET_REGION1WA_Disabled (0x0UL) /*!< Read: Disabled */
4829 #define MWU_NMIENSET_REGION1WA_Enabled (0x1UL) /*!< Read: Enabled */
4830 #define MWU_NMIENSET_REGION1WA_Set (0x1UL) /*!< Enable */
4831 
4832 /* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
4833 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
4834 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
4835 #define MWU_NMIENSET_REGION0RA_Disabled (0x0UL) /*!< Read: Disabled */
4836 #define MWU_NMIENSET_REGION0RA_Enabled (0x1UL) /*!< Read: Enabled */
4837 #define MWU_NMIENSET_REGION0RA_Set (0x1UL) /*!< Enable */
4838 
4839 /* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
4840 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
4841 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
4842 #define MWU_NMIENSET_REGION0WA_Disabled (0x0UL) /*!< Read: Disabled */
4843 #define MWU_NMIENSET_REGION0WA_Enabled (0x1UL) /*!< Read: Enabled */
4844 #define MWU_NMIENSET_REGION0WA_Set (0x1UL) /*!< Enable */
4845 
4846 /* Register: MWU_NMIENCLR */
4847 /* Description: Disable interrupt */
4848 
4849 /* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
4850 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
4851 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
4852 #define MWU_NMIENCLR_PREGION1RA_Disabled (0x0UL) /*!< Read: Disabled */
4853 #define MWU_NMIENCLR_PREGION1RA_Enabled (0x1UL) /*!< Read: Enabled */
4854 #define MWU_NMIENCLR_PREGION1RA_Clear (0x1UL) /*!< Disable */
4855 
4856 /* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
4857 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
4858 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
4859 #define MWU_NMIENCLR_PREGION1WA_Disabled (0x0UL) /*!< Read: Disabled */
4860 #define MWU_NMIENCLR_PREGION1WA_Enabled (0x1UL) /*!< Read: Enabled */
4861 #define MWU_NMIENCLR_PREGION1WA_Clear (0x1UL) /*!< Disable */
4862 
4863 /* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
4864 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
4865 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
4866 #define MWU_NMIENCLR_PREGION0RA_Disabled (0x0UL) /*!< Read: Disabled */
4867 #define MWU_NMIENCLR_PREGION0RA_Enabled (0x1UL) /*!< Read: Enabled */
4868 #define MWU_NMIENCLR_PREGION0RA_Clear (0x1UL) /*!< Disable */
4869 
4870 /* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
4871 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
4872 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
4873 #define MWU_NMIENCLR_PREGION0WA_Disabled (0x0UL) /*!< Read: Disabled */
4874 #define MWU_NMIENCLR_PREGION0WA_Enabled (0x1UL) /*!< Read: Enabled */
4875 #define MWU_NMIENCLR_PREGION0WA_Clear (0x1UL) /*!< Disable */
4876 
4877 /* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
4878 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
4879 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
4880 #define MWU_NMIENCLR_REGION3RA_Disabled (0x0UL) /*!< Read: Disabled */
4881 #define MWU_NMIENCLR_REGION3RA_Enabled (0x1UL) /*!< Read: Enabled */
4882 #define MWU_NMIENCLR_REGION3RA_Clear (0x1UL) /*!< Disable */
4883 
4884 /* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
4885 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
4886 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
4887 #define MWU_NMIENCLR_REGION3WA_Disabled (0x0UL) /*!< Read: Disabled */
4888 #define MWU_NMIENCLR_REGION3WA_Enabled (0x1UL) /*!< Read: Enabled */
4889 #define MWU_NMIENCLR_REGION3WA_Clear (0x1UL) /*!< Disable */
4890 
4891 /* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
4892 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
4893 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
4894 #define MWU_NMIENCLR_REGION2RA_Disabled (0x0UL) /*!< Read: Disabled */
4895 #define MWU_NMIENCLR_REGION2RA_Enabled (0x1UL) /*!< Read: Enabled */
4896 #define MWU_NMIENCLR_REGION2RA_Clear (0x1UL) /*!< Disable */
4897 
4898 /* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
4899 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
4900 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
4901 #define MWU_NMIENCLR_REGION2WA_Disabled (0x0UL) /*!< Read: Disabled */
4902 #define MWU_NMIENCLR_REGION2WA_Enabled (0x1UL) /*!< Read: Enabled */
4903 #define MWU_NMIENCLR_REGION2WA_Clear (0x1UL) /*!< Disable */
4904 
4905 /* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
4906 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
4907 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
4908 #define MWU_NMIENCLR_REGION1RA_Disabled (0x0UL) /*!< Read: Disabled */
4909 #define MWU_NMIENCLR_REGION1RA_Enabled (0x1UL) /*!< Read: Enabled */
4910 #define MWU_NMIENCLR_REGION1RA_Clear (0x1UL) /*!< Disable */
4911 
4912 /* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
4913 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
4914 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
4915 #define MWU_NMIENCLR_REGION1WA_Disabled (0x0UL) /*!< Read: Disabled */
4916 #define MWU_NMIENCLR_REGION1WA_Enabled (0x1UL) /*!< Read: Enabled */
4917 #define MWU_NMIENCLR_REGION1WA_Clear (0x1UL) /*!< Disable */
4918 
4919 /* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
4920 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
4921 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
4922 #define MWU_NMIENCLR_REGION0RA_Disabled (0x0UL) /*!< Read: Disabled */
4923 #define MWU_NMIENCLR_REGION0RA_Enabled (0x1UL) /*!< Read: Enabled */
4924 #define MWU_NMIENCLR_REGION0RA_Clear (0x1UL) /*!< Disable */
4925 
4926 /* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
4927 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
4928 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
4929 #define MWU_NMIENCLR_REGION0WA_Disabled (0x0UL) /*!< Read: Disabled */
4930 #define MWU_NMIENCLR_REGION0WA_Enabled (0x1UL) /*!< Read: Enabled */
4931 #define MWU_NMIENCLR_REGION0WA_Clear (0x1UL) /*!< Disable */
4932 
4933 /* Register: MWU_PERREGION_SUBSTATWA */
4934 /* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */
4935 
4936 /* Bit 31 : Subregion 31 in region n (write '1' to clear) */
4937 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
4938 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
4939 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
4940 #define MWU_PERREGION_SUBSTATWA_SR31_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
4941 
4942 /* Bit 30 : Subregion 30 in region n (write '1' to clear) */
4943 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
4944 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
4945 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
4946 #define MWU_PERREGION_SUBSTATWA_SR30_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
4947 
4948 /* Bit 29 : Subregion 29 in region n (write '1' to clear) */
4949 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
4950 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
4951 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
4952 #define MWU_PERREGION_SUBSTATWA_SR29_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
4953 
4954 /* Bit 28 : Subregion 28 in region n (write '1' to clear) */
4955 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
4956 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
4957 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
4958 #define MWU_PERREGION_SUBSTATWA_SR28_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
4959 
4960 /* Bit 27 : Subregion 27 in region n (write '1' to clear) */
4961 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
4962 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
4963 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
4964 #define MWU_PERREGION_SUBSTATWA_SR27_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
4965 
4966 /* Bit 26 : Subregion 26 in region n (write '1' to clear) */
4967 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
4968 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
4969 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
4970 #define MWU_PERREGION_SUBSTATWA_SR26_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
4971 
4972 /* Bit 25 : Subregion 25 in region n (write '1' to clear) */
4973 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
4974 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
4975 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
4976 #define MWU_PERREGION_SUBSTATWA_SR25_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
4977 
4978 /* Bit 24 : Subregion 24 in region n (write '1' to clear) */
4979 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
4980 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
4981 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
4982 #define MWU_PERREGION_SUBSTATWA_SR24_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
4983 
4984 /* Bit 23 : Subregion 23 in region n (write '1' to clear) */
4985 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
4986 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
4987 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
4988 #define MWU_PERREGION_SUBSTATWA_SR23_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
4989 
4990 /* Bit 22 : Subregion 22 in region n (write '1' to clear) */
4991 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
4992 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
4993 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
4994 #define MWU_PERREGION_SUBSTATWA_SR22_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
4995 
4996 /* Bit 21 : Subregion 21 in region n (write '1' to clear) */
4997 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
4998 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
4999 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5000 #define MWU_PERREGION_SUBSTATWA_SR21_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5001 
5002 /* Bit 20 : Subregion 20 in region n (write '1' to clear) */
5003 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
5004 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
5005 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5006 #define MWU_PERREGION_SUBSTATWA_SR20_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5007 
5008 /* Bit 19 : Subregion 19 in region n (write '1' to clear) */
5009 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
5010 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
5011 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5012 #define MWU_PERREGION_SUBSTATWA_SR19_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5013 
5014 /* Bit 18 : Subregion 18 in region n (write '1' to clear) */
5015 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
5016 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
5017 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5018 #define MWU_PERREGION_SUBSTATWA_SR18_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5019 
5020 /* Bit 17 : Subregion 17 in region n (write '1' to clear) */
5021 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
5022 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
5023 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5024 #define MWU_PERREGION_SUBSTATWA_SR17_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5025 
5026 /* Bit 16 : Subregion 16 in region n (write '1' to clear) */
5027 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
5028 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
5029 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5030 #define MWU_PERREGION_SUBSTATWA_SR16_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5031 
5032 /* Bit 15 : Subregion 15 in region n (write '1' to clear) */
5033 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
5034 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
5035 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5036 #define MWU_PERREGION_SUBSTATWA_SR15_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5037 
5038 /* Bit 14 : Subregion 14 in region n (write '1' to clear) */
5039 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
5040 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
5041 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5042 #define MWU_PERREGION_SUBSTATWA_SR14_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5043 
5044 /* Bit 13 : Subregion 13 in region n (write '1' to clear) */
5045 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
5046 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
5047 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5048 #define MWU_PERREGION_SUBSTATWA_SR13_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5049 
5050 /* Bit 12 : Subregion 12 in region n (write '1' to clear) */
5051 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
5052 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
5053 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5054 #define MWU_PERREGION_SUBSTATWA_SR12_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5055 
5056 /* Bit 11 : Subregion 11 in region n (write '1' to clear) */
5057 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
5058 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
5059 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5060 #define MWU_PERREGION_SUBSTATWA_SR11_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5061 
5062 /* Bit 10 : Subregion 10 in region n (write '1' to clear) */
5063 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
5064 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
5065 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5066 #define MWU_PERREGION_SUBSTATWA_SR10_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5067 
5068 /* Bit 9 : Subregion 9 in region n (write '1' to clear) */
5069 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
5070 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
5071 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5072 #define MWU_PERREGION_SUBSTATWA_SR9_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5073 
5074 /* Bit 8 : Subregion 8 in region n (write '1' to clear) */
5075 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
5076 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
5077 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5078 #define MWU_PERREGION_SUBSTATWA_SR8_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5079 
5080 /* Bit 7 : Subregion 7 in region n (write '1' to clear) */
5081 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
5082 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
5083 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5084 #define MWU_PERREGION_SUBSTATWA_SR7_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5085 
5086 /* Bit 6 : Subregion 6 in region n (write '1' to clear) */
5087 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
5088 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
5089 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5090 #define MWU_PERREGION_SUBSTATWA_SR6_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5091 
5092 /* Bit 5 : Subregion 5 in region n (write '1' to clear) */
5093 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
5094 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
5095 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5096 #define MWU_PERREGION_SUBSTATWA_SR5_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5097 
5098 /* Bit 4 : Subregion 4 in region n (write '1' to clear) */
5099 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
5100 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
5101 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5102 #define MWU_PERREGION_SUBSTATWA_SR4_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5103 
5104 /* Bit 3 : Subregion 3 in region n (write '1' to clear) */
5105 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
5106 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
5107 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5108 #define MWU_PERREGION_SUBSTATWA_SR3_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5109 
5110 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
5111 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
5112 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
5113 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5114 #define MWU_PERREGION_SUBSTATWA_SR2_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5115 
5116 /* Bit 1 : Subregion 1 in region n (write '1' to clear) */
5117 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
5118 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
5119 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5120 #define MWU_PERREGION_SUBSTATWA_SR1_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5121 
5122 /* Bit 0 : Subregion 0 in region n (write '1' to clear) */
5123 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
5124 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
5125 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0x0UL) /*!< No write access occurred in this subregion */
5126 #define MWU_PERREGION_SUBSTATWA_SR0_Access (0x1UL) /*!< Write access(es) occurred in this subregion */
5127 
5128 /* Register: MWU_PERREGION_SUBSTATRA */
5129 /* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */
5130 
5131 /* Bit 31 : Subregion 31 in region n (write '1' to clear) */
5132 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
5133 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
5134 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5135 #define MWU_PERREGION_SUBSTATRA_SR31_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5136 
5137 /* Bit 30 : Subregion 30 in region n (write '1' to clear) */
5138 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
5139 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
5140 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5141 #define MWU_PERREGION_SUBSTATRA_SR30_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5142 
5143 /* Bit 29 : Subregion 29 in region n (write '1' to clear) */
5144 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
5145 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
5146 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5147 #define MWU_PERREGION_SUBSTATRA_SR29_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5148 
5149 /* Bit 28 : Subregion 28 in region n (write '1' to clear) */
5150 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
5151 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
5152 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5153 #define MWU_PERREGION_SUBSTATRA_SR28_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5154 
5155 /* Bit 27 : Subregion 27 in region n (write '1' to clear) */
5156 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
5157 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
5158 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5159 #define MWU_PERREGION_SUBSTATRA_SR27_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5160 
5161 /* Bit 26 : Subregion 26 in region n (write '1' to clear) */
5162 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
5163 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
5164 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5165 #define MWU_PERREGION_SUBSTATRA_SR26_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5166 
5167 /* Bit 25 : Subregion 25 in region n (write '1' to clear) */
5168 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
5169 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
5170 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5171 #define MWU_PERREGION_SUBSTATRA_SR25_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5172 
5173 /* Bit 24 : Subregion 24 in region n (write '1' to clear) */
5174 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
5175 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
5176 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5177 #define MWU_PERREGION_SUBSTATRA_SR24_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5178 
5179 /* Bit 23 : Subregion 23 in region n (write '1' to clear) */
5180 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
5181 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
5182 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5183 #define MWU_PERREGION_SUBSTATRA_SR23_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5184 
5185 /* Bit 22 : Subregion 22 in region n (write '1' to clear) */
5186 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
5187 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
5188 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5189 #define MWU_PERREGION_SUBSTATRA_SR22_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5190 
5191 /* Bit 21 : Subregion 21 in region n (write '1' to clear) */
5192 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
5193 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
5194 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5195 #define MWU_PERREGION_SUBSTATRA_SR21_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5196 
5197 /* Bit 20 : Subregion 20 in region n (write '1' to clear) */
5198 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
5199 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
5200 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5201 #define MWU_PERREGION_SUBSTATRA_SR20_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5202 
5203 /* Bit 19 : Subregion 19 in region n (write '1' to clear) */
5204 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
5205 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
5206 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5207 #define MWU_PERREGION_SUBSTATRA_SR19_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5208 
5209 /* Bit 18 : Subregion 18 in region n (write '1' to clear) */
5210 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
5211 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
5212 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5213 #define MWU_PERREGION_SUBSTATRA_SR18_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5214 
5215 /* Bit 17 : Subregion 17 in region n (write '1' to clear) */
5216 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
5217 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
5218 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5219 #define MWU_PERREGION_SUBSTATRA_SR17_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5220 
5221 /* Bit 16 : Subregion 16 in region n (write '1' to clear) */
5222 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
5223 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
5224 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5225 #define MWU_PERREGION_SUBSTATRA_SR16_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5226 
5227 /* Bit 15 : Subregion 15 in region n (write '1' to clear) */
5228 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
5229 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
5230 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5231 #define MWU_PERREGION_SUBSTATRA_SR15_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5232 
5233 /* Bit 14 : Subregion 14 in region n (write '1' to clear) */
5234 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
5235 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
5236 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5237 #define MWU_PERREGION_SUBSTATRA_SR14_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5238 
5239 /* Bit 13 : Subregion 13 in region n (write '1' to clear) */
5240 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
5241 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
5242 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5243 #define MWU_PERREGION_SUBSTATRA_SR13_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5244 
5245 /* Bit 12 : Subregion 12 in region n (write '1' to clear) */
5246 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
5247 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
5248 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5249 #define MWU_PERREGION_SUBSTATRA_SR12_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5250 
5251 /* Bit 11 : Subregion 11 in region n (write '1' to clear) */
5252 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
5253 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
5254 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5255 #define MWU_PERREGION_SUBSTATRA_SR11_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5256 
5257 /* Bit 10 : Subregion 10 in region n (write '1' to clear) */
5258 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
5259 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
5260 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5261 #define MWU_PERREGION_SUBSTATRA_SR10_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5262 
5263 /* Bit 9 : Subregion 9 in region n (write '1' to clear) */
5264 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
5265 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
5266 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5267 #define MWU_PERREGION_SUBSTATRA_SR9_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5268 
5269 /* Bit 8 : Subregion 8 in region n (write '1' to clear) */
5270 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
5271 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
5272 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5273 #define MWU_PERREGION_SUBSTATRA_SR8_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5274 
5275 /* Bit 7 : Subregion 7 in region n (write '1' to clear) */
5276 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
5277 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
5278 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5279 #define MWU_PERREGION_SUBSTATRA_SR7_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5280 
5281 /* Bit 6 : Subregion 6 in region n (write '1' to clear) */
5282 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
5283 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
5284 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5285 #define MWU_PERREGION_SUBSTATRA_SR6_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5286 
5287 /* Bit 5 : Subregion 5 in region n (write '1' to clear) */
5288 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
5289 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
5290 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5291 #define MWU_PERREGION_SUBSTATRA_SR5_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5292 
5293 /* Bit 4 : Subregion 4 in region n (write '1' to clear) */
5294 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
5295 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
5296 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5297 #define MWU_PERREGION_SUBSTATRA_SR4_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5298 
5299 /* Bit 3 : Subregion 3 in region n (write '1' to clear) */
5300 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
5301 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
5302 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5303 #define MWU_PERREGION_SUBSTATRA_SR3_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5304 
5305 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
5306 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
5307 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
5308 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5309 #define MWU_PERREGION_SUBSTATRA_SR2_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5310 
5311 /* Bit 1 : Subregion 1 in region n (write '1' to clear) */
5312 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
5313 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
5314 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5315 #define MWU_PERREGION_SUBSTATRA_SR1_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5316 
5317 /* Bit 0 : Subregion 0 in region n (write '1' to clear) */
5318 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
5319 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
5320 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0x0UL) /*!< No read access occurred in this subregion */
5321 #define MWU_PERREGION_SUBSTATRA_SR0_Access (0x1UL) /*!< Read access(es) occurred in this subregion */
5322 
5323 /* Register: MWU_REGIONEN */
5324 /* Description: Enable/disable regions watch */
5325 
5326 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
5327 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
5328 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
5329 #define MWU_REGIONEN_PRGN1RA_Disable (0x0UL) /*!< Disable read access watch in this PREGION */
5330 #define MWU_REGIONEN_PRGN1RA_Enable (0x1UL) /*!< Enable read access watch in this PREGION */
5331 
5332 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
5333 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
5334 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
5335 #define MWU_REGIONEN_PRGN1WA_Disable (0x0UL) /*!< Disable write access watch in this PREGION */
5336 #define MWU_REGIONEN_PRGN1WA_Enable (0x1UL) /*!< Enable write access watch in this PREGION */
5337 
5338 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
5339 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
5340 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
5341 #define MWU_REGIONEN_PRGN0RA_Disable (0x0UL) /*!< Disable read access watch in this PREGION */
5342 #define MWU_REGIONEN_PRGN0RA_Enable (0x1UL) /*!< Enable read access watch in this PREGION */
5343 
5344 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
5345 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
5346 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
5347 #define MWU_REGIONEN_PRGN0WA_Disable (0x0UL) /*!< Disable write access watch in this PREGION */
5348 #define MWU_REGIONEN_PRGN0WA_Enable (0x1UL) /*!< Enable write access watch in this PREGION */
5349 
5350 /* Bit 7 : Enable/disable read access watch in region[3] */
5351 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
5352 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
5353 #define MWU_REGIONEN_RGN3RA_Disable (0x0UL) /*!< Disable read access watch in this region */
5354 #define MWU_REGIONEN_RGN3RA_Enable (0x1UL) /*!< Enable read access watch in this region */
5355 
5356 /* Bit 6 : Enable/disable write access watch in region[3] */
5357 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
5358 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
5359 #define MWU_REGIONEN_RGN3WA_Disable (0x0UL) /*!< Disable write access watch in this region */
5360 #define MWU_REGIONEN_RGN3WA_Enable (0x1UL) /*!< Enable write access watch in this region */
5361 
5362 /* Bit 5 : Enable/disable read access watch in region[2] */
5363 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
5364 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
5365 #define MWU_REGIONEN_RGN2RA_Disable (0x0UL) /*!< Disable read access watch in this region */
5366 #define MWU_REGIONEN_RGN2RA_Enable (0x1UL) /*!< Enable read access watch in this region */
5367 
5368 /* Bit 4 : Enable/disable write access watch in region[2] */
5369 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
5370 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
5371 #define MWU_REGIONEN_RGN2WA_Disable (0x0UL) /*!< Disable write access watch in this region */
5372 #define MWU_REGIONEN_RGN2WA_Enable (0x1UL) /*!< Enable write access watch in this region */
5373 
5374 /* Bit 3 : Enable/disable read access watch in region[1] */
5375 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
5376 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
5377 #define MWU_REGIONEN_RGN1RA_Disable (0x0UL) /*!< Disable read access watch in this region */
5378 #define MWU_REGIONEN_RGN1RA_Enable (0x1UL) /*!< Enable read access watch in this region */
5379 
5380 /* Bit 2 : Enable/disable write access watch in region[1] */
5381 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
5382 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
5383 #define MWU_REGIONEN_RGN1WA_Disable (0x0UL) /*!< Disable write access watch in this region */
5384 #define MWU_REGIONEN_RGN1WA_Enable (0x1UL) /*!< Enable write access watch in this region */
5385 
5386 /* Bit 1 : Enable/disable read access watch in region[0] */
5387 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
5388 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
5389 #define MWU_REGIONEN_RGN0RA_Disable (0x0UL) /*!< Disable read access watch in this region */
5390 #define MWU_REGIONEN_RGN0RA_Enable (0x1UL) /*!< Enable read access watch in this region */
5391 
5392 /* Bit 0 : Enable/disable write access watch in region[0] */
5393 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
5394 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
5395 #define MWU_REGIONEN_RGN0WA_Disable (0x0UL) /*!< Disable write access watch in this region */
5396 #define MWU_REGIONEN_RGN0WA_Enable (0x1UL) /*!< Enable write access watch in this region */
5397 
5398 /* Register: MWU_REGIONENSET */
5399 /* Description: Enable regions watch */
5400 
5401 /* Bit 27 : Enable read access watch in PREGION[1] */
5402 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
5403 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
5404 #define MWU_REGIONENSET_PRGN1RA_Disabled (0x0UL) /*!< Read access watch in this PREGION is disabled */
5405 #define MWU_REGIONENSET_PRGN1RA_Enabled (0x1UL) /*!< Read access watch in this PREGION is enabled */
5406 #define MWU_REGIONENSET_PRGN1RA_Set (0x1UL) /*!< Enable read access watch in this PREGION */
5407 
5408 /* Bit 26 : Enable write access watch in PREGION[1] */
5409 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
5410 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
5411 #define MWU_REGIONENSET_PRGN1WA_Disabled (0x0UL) /*!< Write access watch in this PREGION is disabled */
5412 #define MWU_REGIONENSET_PRGN1WA_Enabled (0x1UL) /*!< Write access watch in this PREGION is enabled */
5413 #define MWU_REGIONENSET_PRGN1WA_Set (0x1UL) /*!< Enable write access watch in this PREGION */
5414 
5415 /* Bit 25 : Enable read access watch in PREGION[0] */
5416 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
5417 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
5418 #define MWU_REGIONENSET_PRGN0RA_Disabled (0x0UL) /*!< Read access watch in this PREGION is disabled */
5419 #define MWU_REGIONENSET_PRGN0RA_Enabled (0x1UL) /*!< Read access watch in this PREGION is enabled */
5420 #define MWU_REGIONENSET_PRGN0RA_Set (0x1UL) /*!< Enable read access watch in this PREGION */
5421 
5422 /* Bit 24 : Enable write access watch in PREGION[0] */
5423 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
5424 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
5425 #define MWU_REGIONENSET_PRGN0WA_Disabled (0x0UL) /*!< Write access watch in this PREGION is disabled */
5426 #define MWU_REGIONENSET_PRGN0WA_Enabled (0x1UL) /*!< Write access watch in this PREGION is enabled */
5427 #define MWU_REGIONENSET_PRGN0WA_Set (0x1UL) /*!< Enable write access watch in this PREGION */
5428 
5429 /* Bit 7 : Enable read access watch in region[3] */
5430 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
5431 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
5432 #define MWU_REGIONENSET_RGN3RA_Disabled (0x0UL) /*!< Read access watch in this region is disabled */
5433 #define MWU_REGIONENSET_RGN3RA_Enabled (0x1UL) /*!< Read access watch in this region is enabled */
5434 #define MWU_REGIONENSET_RGN3RA_Set (0x1UL) /*!< Enable read access watch in this region */
5435 
5436 /* Bit 6 : Enable write access watch in region[3] */
5437 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
5438 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
5439 #define MWU_REGIONENSET_RGN3WA_Disabled (0x0UL) /*!< Write access watch in this region is disabled */
5440 #define MWU_REGIONENSET_RGN3WA_Enabled (0x1UL) /*!< Write access watch in this region is enabled */
5441 #define MWU_REGIONENSET_RGN3WA_Set (0x1UL) /*!< Enable write access watch in this region */
5442 
5443 /* Bit 5 : Enable read access watch in region[2] */
5444 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
5445 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
5446 #define MWU_REGIONENSET_RGN2RA_Disabled (0x0UL) /*!< Read access watch in this region is disabled */
5447 #define MWU_REGIONENSET_RGN2RA_Enabled (0x1UL) /*!< Read access watch in this region is enabled */
5448 #define MWU_REGIONENSET_RGN2RA_Set (0x1UL) /*!< Enable read access watch in this region */
5449 
5450 /* Bit 4 : Enable write access watch in region[2] */
5451 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
5452 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
5453 #define MWU_REGIONENSET_RGN2WA_Disabled (0x0UL) /*!< Write access watch in this region is disabled */
5454 #define MWU_REGIONENSET_RGN2WA_Enabled (0x1UL) /*!< Write access watch in this region is enabled */
5455 #define MWU_REGIONENSET_RGN2WA_Set (0x1UL) /*!< Enable write access watch in this region */
5456 
5457 /* Bit 3 : Enable read access watch in region[1] */
5458 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
5459 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
5460 #define MWU_REGIONENSET_RGN1RA_Disabled (0x0UL) /*!< Read access watch in this region is disabled */
5461 #define MWU_REGIONENSET_RGN1RA_Enabled (0x1UL) /*!< Read access watch in this region is enabled */
5462 #define MWU_REGIONENSET_RGN1RA_Set (0x1UL) /*!< Enable read access watch in this region */
5463 
5464 /* Bit 2 : Enable write access watch in region[1] */
5465 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
5466 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
5467 #define MWU_REGIONENSET_RGN1WA_Disabled (0x0UL) /*!< Write access watch in this region is disabled */
5468 #define MWU_REGIONENSET_RGN1WA_Enabled (0x1UL) /*!< Write access watch in this region is enabled */
5469 #define MWU_REGIONENSET_RGN1WA_Set (0x1UL) /*!< Enable write access watch in this region */
5470 
5471 /* Bit 1 : Enable read access watch in region[0] */
5472 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
5473 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
5474 #define MWU_REGIONENSET_RGN0RA_Disabled (0x0UL) /*!< Read access watch in this region is disabled */
5475 #define MWU_REGIONENSET_RGN0RA_Enabled (0x1UL) /*!< Read access watch in this region is enabled */
5476 #define MWU_REGIONENSET_RGN0RA_Set (0x1UL) /*!< Enable read access watch in this region */
5477 
5478 /* Bit 0 : Enable write access watch in region[0] */
5479 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
5480 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
5481 #define MWU_REGIONENSET_RGN0WA_Disabled (0x0UL) /*!< Write access watch in this region is disabled */
5482 #define MWU_REGIONENSET_RGN0WA_Enabled (0x1UL) /*!< Write access watch in this region is enabled */
5483 #define MWU_REGIONENSET_RGN0WA_Set (0x1UL) /*!< Enable write access watch in this region */
5484 
5485 /* Register: MWU_REGIONENCLR */
5486 /* Description: Disable regions watch */
5487 
5488 /* Bit 27 : Disable read access watch in PREGION[1] */
5489 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
5490 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
5491 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0x0UL) /*!< Read access watch in this PREGION is disabled */
5492 #define MWU_REGIONENCLR_PRGN1RA_Enabled (0x1UL) /*!< Read access watch in this PREGION is enabled */
5493 #define MWU_REGIONENCLR_PRGN1RA_Clear (0x1UL) /*!< Disable read access watch in this PREGION */
5494 
5495 /* Bit 26 : Disable write access watch in PREGION[1] */
5496 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
5497 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
5498 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0x0UL) /*!< Write access watch in this PREGION is disabled */
5499 #define MWU_REGIONENCLR_PRGN1WA_Enabled (0x1UL) /*!< Write access watch in this PREGION is enabled */
5500 #define MWU_REGIONENCLR_PRGN1WA_Clear (0x1UL) /*!< Disable write access watch in this PREGION */
5501 
5502 /* Bit 25 : Disable read access watch in PREGION[0] */
5503 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
5504 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
5505 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0x0UL) /*!< Read access watch in this PREGION is disabled */
5506 #define MWU_REGIONENCLR_PRGN0RA_Enabled (0x1UL) /*!< Read access watch in this PREGION is enabled */
5507 #define MWU_REGIONENCLR_PRGN0RA_Clear (0x1UL) /*!< Disable read access watch in this PREGION */
5508 
5509 /* Bit 24 : Disable write access watch in PREGION[0] */
5510 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
5511 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
5512 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0x0UL) /*!< Write access watch in this PREGION is disabled */
5513 #define MWU_REGIONENCLR_PRGN0WA_Enabled (0x1UL) /*!< Write access watch in this PREGION is enabled */
5514 #define MWU_REGIONENCLR_PRGN0WA_Clear (0x1UL) /*!< Disable write access watch in this PREGION */
5515 
5516 /* Bit 7 : Disable read access watch in region[3] */
5517 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
5518 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
5519 #define MWU_REGIONENCLR_RGN3RA_Disabled (0x0UL) /*!< Read access watch in this region is disabled */
5520 #define MWU_REGIONENCLR_RGN3RA_Enabled (0x1UL) /*!< Read access watch in this region is enabled */
5521 #define MWU_REGIONENCLR_RGN3RA_Clear (0x1UL) /*!< Disable read access watch in this region */
5522 
5523 /* Bit 6 : Disable write access watch in region[3] */
5524 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
5525 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
5526 #define MWU_REGIONENCLR_RGN3WA_Disabled (0x0UL) /*!< Write access watch in this region is disabled */
5527 #define MWU_REGIONENCLR_RGN3WA_Enabled (0x1UL) /*!< Write access watch in this region is enabled */
5528 #define MWU_REGIONENCLR_RGN3WA_Clear (0x1UL) /*!< Disable write access watch in this region */
5529 
5530 /* Bit 5 : Disable read access watch in region[2] */
5531 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
5532 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
5533 #define MWU_REGIONENCLR_RGN2RA_Disabled (0x0UL) /*!< Read access watch in this region is disabled */
5534 #define MWU_REGIONENCLR_RGN2RA_Enabled (0x1UL) /*!< Read access watch in this region is enabled */
5535 #define MWU_REGIONENCLR_RGN2RA_Clear (0x1UL) /*!< Disable read access watch in this region */
5536 
5537 /* Bit 4 : Disable write access watch in region[2] */
5538 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
5539 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
5540 #define MWU_REGIONENCLR_RGN2WA_Disabled (0x0UL) /*!< Write access watch in this region is disabled */
5541 #define MWU_REGIONENCLR_RGN2WA_Enabled (0x1UL) /*!< Write access watch in this region is enabled */
5542 #define MWU_REGIONENCLR_RGN2WA_Clear (0x1UL) /*!< Disable write access watch in this region */
5543 
5544 /* Bit 3 : Disable read access watch in region[1] */
5545 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
5546 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
5547 #define MWU_REGIONENCLR_RGN1RA_Disabled (0x0UL) /*!< Read access watch in this region is disabled */
5548 #define MWU_REGIONENCLR_RGN1RA_Enabled (0x1UL) /*!< Read access watch in this region is enabled */
5549 #define MWU_REGIONENCLR_RGN1RA_Clear (0x1UL) /*!< Disable read access watch in this region */
5550 
5551 /* Bit 2 : Disable write access watch in region[1] */
5552 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
5553 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
5554 #define MWU_REGIONENCLR_RGN1WA_Disabled (0x0UL) /*!< Write access watch in this region is disabled */
5555 #define MWU_REGIONENCLR_RGN1WA_Enabled (0x1UL) /*!< Write access watch in this region is enabled */
5556 #define MWU_REGIONENCLR_RGN1WA_Clear (0x1UL) /*!< Disable write access watch in this region */
5557 
5558 /* Bit 1 : Disable read access watch in region[0] */
5559 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
5560 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
5561 #define MWU_REGIONENCLR_RGN0RA_Disabled (0x0UL) /*!< Read access watch in this region is disabled */
5562 #define MWU_REGIONENCLR_RGN0RA_Enabled (0x1UL) /*!< Read access watch in this region is enabled */
5563 #define MWU_REGIONENCLR_RGN0RA_Clear (0x1UL) /*!< Disable read access watch in this region */
5564 
5565 /* Bit 0 : Disable write access watch in region[0] */
5566 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
5567 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
5568 #define MWU_REGIONENCLR_RGN0WA_Disabled (0x0UL) /*!< Write access watch in this region is disabled */
5569 #define MWU_REGIONENCLR_RGN0WA_Enabled (0x1UL) /*!< Write access watch in this region is enabled */
5570 #define MWU_REGIONENCLR_RGN0WA_Clear (0x1UL) /*!< Disable write access watch in this region */
5571 
5572 /* Register: MWU_REGION_START */
5573 /* Description: Description cluster: Start address for region n */
5574 
5575 /* Bits 31..0 : Start address for region */
5576 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
5577 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
5578 
5579 /* Register: MWU_REGION_END */
5580 /* Description: Description cluster: End address of region n */
5581 
5582 /* Bits 31..0 : End address of region. */
5583 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
5584 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
5585 
5586 /* Register: MWU_PREGION_START */
5587 /* Description: Description cluster: Reserved for future use */
5588 
5589 /* Bits 31..0 : Reserved for future use */
5590 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
5591 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
5592 
5593 /* Register: MWU_PREGION_END */
5594 /* Description: Description cluster: Reserved for future use */
5595 
5596 /* Bits 31..0 : Reserved for future use */
5597 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
5598 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
5599 
5600 /* Register: MWU_PREGION_SUBS */
5601 /* Description: Description cluster: Subregions of region n */
5602 
5603 /* Bit 31 : Include or exclude subregion 31 in region */
5604 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
5605 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
5606 #define MWU_PREGION_SUBS_SR31_Exclude (0x0UL) /*!< Exclude */
5607 #define MWU_PREGION_SUBS_SR31_Include (0x1UL) /*!< Include */
5608 
5609 /* Bit 30 : Include or exclude subregion 30 in region */
5610 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
5611 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
5612 #define MWU_PREGION_SUBS_SR30_Exclude (0x0UL) /*!< Exclude */
5613 #define MWU_PREGION_SUBS_SR30_Include (0x1UL) /*!< Include */
5614 
5615 /* Bit 29 : Include or exclude subregion 29 in region */
5616 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
5617 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
5618 #define MWU_PREGION_SUBS_SR29_Exclude (0x0UL) /*!< Exclude */
5619 #define MWU_PREGION_SUBS_SR29_Include (0x1UL) /*!< Include */
5620 
5621 /* Bit 28 : Include or exclude subregion 28 in region */
5622 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
5623 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
5624 #define MWU_PREGION_SUBS_SR28_Exclude (0x0UL) /*!< Exclude */
5625 #define MWU_PREGION_SUBS_SR28_Include (0x1UL) /*!< Include */
5626 
5627 /* Bit 27 : Include or exclude subregion 27 in region */
5628 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
5629 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
5630 #define MWU_PREGION_SUBS_SR27_Exclude (0x0UL) /*!< Exclude */
5631 #define MWU_PREGION_SUBS_SR27_Include (0x1UL) /*!< Include */
5632 
5633 /* Bit 26 : Include or exclude subregion 26 in region */
5634 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
5635 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
5636 #define MWU_PREGION_SUBS_SR26_Exclude (0x0UL) /*!< Exclude */
5637 #define MWU_PREGION_SUBS_SR26_Include (0x1UL) /*!< Include */
5638 
5639 /* Bit 25 : Include or exclude subregion 25 in region */
5640 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
5641 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
5642 #define MWU_PREGION_SUBS_SR25_Exclude (0x0UL) /*!< Exclude */
5643 #define MWU_PREGION_SUBS_SR25_Include (0x1UL) /*!< Include */
5644 
5645 /* Bit 24 : Include or exclude subregion 24 in region */
5646 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
5647 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
5648 #define MWU_PREGION_SUBS_SR24_Exclude (0x0UL) /*!< Exclude */
5649 #define MWU_PREGION_SUBS_SR24_Include (0x1UL) /*!< Include */
5650 
5651 /* Bit 23 : Include or exclude subregion 23 in region */
5652 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
5653 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
5654 #define MWU_PREGION_SUBS_SR23_Exclude (0x0UL) /*!< Exclude */
5655 #define MWU_PREGION_SUBS_SR23_Include (0x1UL) /*!< Include */
5656 
5657 /* Bit 22 : Include or exclude subregion 22 in region */
5658 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
5659 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
5660 #define MWU_PREGION_SUBS_SR22_Exclude (0x0UL) /*!< Exclude */
5661 #define MWU_PREGION_SUBS_SR22_Include (0x1UL) /*!< Include */
5662 
5663 /* Bit 21 : Include or exclude subregion 21 in region */
5664 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
5665 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
5666 #define MWU_PREGION_SUBS_SR21_Exclude (0x0UL) /*!< Exclude */
5667 #define MWU_PREGION_SUBS_SR21_Include (0x1UL) /*!< Include */
5668 
5669 /* Bit 20 : Include or exclude subregion 20 in region */
5670 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
5671 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
5672 #define MWU_PREGION_SUBS_SR20_Exclude (0x0UL) /*!< Exclude */
5673 #define MWU_PREGION_SUBS_SR20_Include (0x1UL) /*!< Include */
5674 
5675 /* Bit 19 : Include or exclude subregion 19 in region */
5676 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
5677 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
5678 #define MWU_PREGION_SUBS_SR19_Exclude (0x0UL) /*!< Exclude */
5679 #define MWU_PREGION_SUBS_SR19_Include (0x1UL) /*!< Include */
5680 
5681 /* Bit 18 : Include or exclude subregion 18 in region */
5682 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
5683 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
5684 #define MWU_PREGION_SUBS_SR18_Exclude (0x0UL) /*!< Exclude */
5685 #define MWU_PREGION_SUBS_SR18_Include (0x1UL) /*!< Include */
5686 
5687 /* Bit 17 : Include or exclude subregion 17 in region */
5688 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
5689 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
5690 #define MWU_PREGION_SUBS_SR17_Exclude (0x0UL) /*!< Exclude */
5691 #define MWU_PREGION_SUBS_SR17_Include (0x1UL) /*!< Include */
5692 
5693 /* Bit 16 : Include or exclude subregion 16 in region */
5694 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
5695 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
5696 #define MWU_PREGION_SUBS_SR16_Exclude (0x0UL) /*!< Exclude */
5697 #define MWU_PREGION_SUBS_SR16_Include (0x1UL) /*!< Include */
5698 
5699 /* Bit 15 : Include or exclude subregion 15 in region */
5700 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
5701 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
5702 #define MWU_PREGION_SUBS_SR15_Exclude (0x0UL) /*!< Exclude */
5703 #define MWU_PREGION_SUBS_SR15_Include (0x1UL) /*!< Include */
5704 
5705 /* Bit 14 : Include or exclude subregion 14 in region */
5706 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
5707 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
5708 #define MWU_PREGION_SUBS_SR14_Exclude (0x0UL) /*!< Exclude */
5709 #define MWU_PREGION_SUBS_SR14_Include (0x1UL) /*!< Include */
5710 
5711 /* Bit 13 : Include or exclude subregion 13 in region */
5712 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
5713 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
5714 #define MWU_PREGION_SUBS_SR13_Exclude (0x0UL) /*!< Exclude */
5715 #define MWU_PREGION_SUBS_SR13_Include (0x1UL) /*!< Include */
5716 
5717 /* Bit 12 : Include or exclude subregion 12 in region */
5718 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
5719 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
5720 #define MWU_PREGION_SUBS_SR12_Exclude (0x0UL) /*!< Exclude */
5721 #define MWU_PREGION_SUBS_SR12_Include (0x1UL) /*!< Include */
5722 
5723 /* Bit 11 : Include or exclude subregion 11 in region */
5724 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
5725 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
5726 #define MWU_PREGION_SUBS_SR11_Exclude (0x0UL) /*!< Exclude */
5727 #define MWU_PREGION_SUBS_SR11_Include (0x1UL) /*!< Include */
5728 
5729 /* Bit 10 : Include or exclude subregion 10 in region */
5730 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
5731 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
5732 #define MWU_PREGION_SUBS_SR10_Exclude (0x0UL) /*!< Exclude */
5733 #define MWU_PREGION_SUBS_SR10_Include (0x1UL) /*!< Include */
5734 
5735 /* Bit 9 : Include or exclude subregion 9 in region */
5736 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
5737 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
5738 #define MWU_PREGION_SUBS_SR9_Exclude (0x0UL) /*!< Exclude */
5739 #define MWU_PREGION_SUBS_SR9_Include (0x1UL) /*!< Include */
5740 
5741 /* Bit 8 : Include or exclude subregion 8 in region */
5742 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
5743 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
5744 #define MWU_PREGION_SUBS_SR8_Exclude (0x0UL) /*!< Exclude */
5745 #define MWU_PREGION_SUBS_SR8_Include (0x1UL) /*!< Include */
5746 
5747 /* Bit 7 : Include or exclude subregion 7 in region */
5748 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
5749 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
5750 #define MWU_PREGION_SUBS_SR7_Exclude (0x0UL) /*!< Exclude */
5751 #define MWU_PREGION_SUBS_SR7_Include (0x1UL) /*!< Include */
5752 
5753 /* Bit 6 : Include or exclude subregion 6 in region */
5754 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
5755 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
5756 #define MWU_PREGION_SUBS_SR6_Exclude (0x0UL) /*!< Exclude */
5757 #define MWU_PREGION_SUBS_SR6_Include (0x1UL) /*!< Include */
5758 
5759 /* Bit 5 : Include or exclude subregion 5 in region */
5760 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
5761 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
5762 #define MWU_PREGION_SUBS_SR5_Exclude (0x0UL) /*!< Exclude */
5763 #define MWU_PREGION_SUBS_SR5_Include (0x1UL) /*!< Include */
5764 
5765 /* Bit 4 : Include or exclude subregion 4 in region */
5766 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
5767 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
5768 #define MWU_PREGION_SUBS_SR4_Exclude (0x0UL) /*!< Exclude */
5769 #define MWU_PREGION_SUBS_SR4_Include (0x1UL) /*!< Include */
5770 
5771 /* Bit 3 : Include or exclude subregion 3 in region */
5772 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
5773 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
5774 #define MWU_PREGION_SUBS_SR3_Exclude (0x0UL) /*!< Exclude */
5775 #define MWU_PREGION_SUBS_SR3_Include (0x1UL) /*!< Include */
5776 
5777 /* Bit 2 : Include or exclude subregion 2 in region */
5778 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
5779 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
5780 #define MWU_PREGION_SUBS_SR2_Exclude (0x0UL) /*!< Exclude */
5781 #define MWU_PREGION_SUBS_SR2_Include (0x1UL) /*!< Include */
5782 
5783 /* Bit 1 : Include or exclude subregion 1 in region */
5784 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
5785 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
5786 #define MWU_PREGION_SUBS_SR1_Exclude (0x0UL) /*!< Exclude */
5787 #define MWU_PREGION_SUBS_SR1_Include (0x1UL) /*!< Include */
5788 
5789 /* Bit 0 : Include or exclude subregion 0 in region */
5790 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
5791 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
5792 #define MWU_PREGION_SUBS_SR0_Exclude (0x0UL) /*!< Exclude */
5793 #define MWU_PREGION_SUBS_SR0_Include (0x1UL) /*!< Include */
5794 
5795 
5796 /* Peripheral: NFCT */
5797 /* Description: NFC-A compatible radio */
5798 
5799 /* Register: NFCT_TASKS_ACTIVATE */
5800 /* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
5801 
5802 /* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
5803 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
5804 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
5805 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (0x1UL) /*!< Trigger task */
5806 
5807 /* Register: NFCT_TASKS_DISABLE */
5808 /* Description: Disable NFCT peripheral */
5809 
5810 /* Bit 0 : Disable NFCT peripheral */
5811 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
5812 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
5813 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (0x1UL) /*!< Trigger task */
5814 
5815 /* Register: NFCT_TASKS_SENSE */
5816 /* Description: Enable NFC sense field mode, change state to sense mode */
5817 
5818 /* Bit 0 : Enable NFC sense field mode, change state to sense mode */
5819 #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */
5820 #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */
5821 #define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (0x1UL) /*!< Trigger task */
5822 
5823 /* Register: NFCT_TASKS_STARTTX */
5824 /* Description: Start transmission of an outgoing frame, change state to transmit */
5825 
5826 /* Bit 0 : Start transmission of an outgoing frame, change state to transmit */
5827 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
5828 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
5829 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */
5830 
5831 /* Register: NFCT_TASKS_ENABLERXDATA */
5832 /* Description: Initializes the EasyDMA for receive. */
5833 
5834 /* Bit 0 : Initializes the EasyDMA for receive. */
5835 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */
5836 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */
5837 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (0x1UL) /*!< Trigger task */
5838 
5839 /* Register: NFCT_TASKS_GOIDLE */
5840 /* Description: Force state machine to IDLE state */
5841 
5842 /* Bit 0 : Force state machine to IDLE state */
5843 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */
5844 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */
5845 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (0x1UL) /*!< Trigger task */
5846 
5847 /* Register: NFCT_TASKS_GOSLEEP */
5848 /* Description: Force state machine to SLEEP_A state */
5849 
5850 /* Bit 0 : Force state machine to SLEEP_A state */
5851 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */
5852 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */
5853 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (0x1UL) /*!< Trigger task */
5854 
5855 /* Register: NFCT_EVENTS_READY */
5856 /* Description: The NFCT peripheral is ready to receive and send frames */
5857 
5858 /* Bit 0 : The NFCT peripheral is ready to receive and send frames */
5859 #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
5860 #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
5861 #define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */
5862 #define NFCT_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */
5863 
5864 /* Register: NFCT_EVENTS_FIELDDETECTED */
5865 /* Description: Remote NFC field detected */
5866 
5867 /* Bit 0 : Remote NFC field detected */
5868 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */
5869 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */
5870 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0x0UL) /*!< Event not generated */
5871 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (0x1UL) /*!< Event generated */
5872 
5873 /* Register: NFCT_EVENTS_FIELDLOST */
5874 /* Description: Remote NFC field lost */
5875 
5876 /* Bit 0 : Remote NFC field lost */
5877 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */
5878 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */
5879 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0x0UL) /*!< Event not generated */
5880 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (0x1UL) /*!< Event generated */
5881 
5882 /* Register: NFCT_EVENTS_TXFRAMESTART */
5883 /* Description: Marks the start of the first symbol of a transmitted frame */
5884 
5885 /* Bit 0 : Marks the start of the first symbol of a transmitted frame */
5886 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */
5887 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */
5888 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */
5889 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (0x1UL) /*!< Event generated */
5890 
5891 /* Register: NFCT_EVENTS_TXFRAMEEND */
5892 /* Description: Marks the end of the last transmitted on-air symbol of a frame */
5893 
5894 /* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */
5895 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */
5896 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */
5897 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0x0UL) /*!< Event not generated */
5898 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (0x1UL) /*!< Event generated */
5899 
5900 /* Register: NFCT_EVENTS_RXFRAMESTART */
5901 /* Description: Marks the end of the first symbol of a received frame */
5902 
5903 /* Bit 0 : Marks the end of the first symbol of a received frame */
5904 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */
5905 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */
5906 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */
5907 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (0x1UL) /*!< Event generated */
5908 
5909 /* Register: NFCT_EVENTS_RXFRAMEEND */
5910 /* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
5911 
5912 /* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
5913 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */
5914 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */
5915 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0x0UL) /*!< Event not generated */
5916 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (0x1UL) /*!< Event generated */
5917 
5918 /* Register: NFCT_EVENTS_ERROR */
5919 /* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
5920 
5921 /* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
5922 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
5923 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
5924 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
5925 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */
5926 
5927 /* Register: NFCT_EVENTS_RXERROR */
5928 /* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
5929 
5930 /* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
5931 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */
5932 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */
5933 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0x0UL) /*!< Event not generated */
5934 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (0x1UL) /*!< Event generated */
5935 
5936 /* Register: NFCT_EVENTS_ENDRX */
5937 /* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
5938 
5939 /* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
5940 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
5941 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
5942 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
5943 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */
5944 
5945 /* Register: NFCT_EVENTS_ENDTX */
5946 /* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
5947 
5948 /* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
5949 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
5950 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
5951 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */
5952 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */
5953 
5954 /* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */
5955 /* Description: Auto collision resolution process has started */
5956 
5957 /* Bit 0 : Auto collision resolution process has started */
5958 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */
5959 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */
5960 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
5961 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (0x1UL) /*!< Event generated */
5962 
5963 /* Register: NFCT_EVENTS_COLLISION */
5964 /* Description: NFC auto collision resolution error reported. */
5965 
5966 /* Bit 0 : NFC auto collision resolution error reported. */
5967 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */
5968 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */
5969 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0x0UL) /*!< Event not generated */
5970 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (0x1UL) /*!< Event generated */
5971 
5972 /* Register: NFCT_EVENTS_SELECTED */
5973 /* Description: NFC auto collision resolution successfully completed */
5974 
5975 /* Bit 0 : NFC auto collision resolution successfully completed */
5976 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */
5977 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */
5978 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0x0UL) /*!< Event not generated */
5979 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (0x1UL) /*!< Event generated */
5980 
5981 /* Register: NFCT_EVENTS_STARTED */
5982 /* Description: EasyDMA is ready to receive or send frames. */
5983 
5984 /* Bit 0 : EasyDMA is ready to receive or send frames. */
5985 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
5986 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
5987 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
5988 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */
5989 
5990 /* Register: NFCT_SHORTS */
5991 /* Description: Shortcuts between local events and tasks */
5992 
5993 /* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */
5994 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */
5995 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */
5996 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0x0UL) /*!< Disable shortcut */
5997 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (0x1UL) /*!< Enable shortcut */
5998 
5999 /* Bit 1 : Shortcut between event FIELDLOST and task SENSE */
6000 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
6001 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
6002 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0x0UL) /*!< Disable shortcut */
6003 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (0x1UL) /*!< Enable shortcut */
6004 
6005 /* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */
6006 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
6007 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
6008 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0x0UL) /*!< Disable shortcut */
6009 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (0x1UL) /*!< Enable shortcut */
6010 
6011 /* Register: NFCT_INTEN */
6012 /* Description: Enable or disable interrupt */
6013 
6014 /* Bit 20 : Enable or disable interrupt for event STARTED */
6015 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
6016 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
6017 #define NFCT_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */
6018 #define NFCT_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */
6019 
6020 /* Bit 19 : Enable or disable interrupt for event SELECTED */
6021 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
6022 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
6023 #define NFCT_INTEN_SELECTED_Disabled (0x0UL) /*!< Disable */
6024 #define NFCT_INTEN_SELECTED_Enabled (0x1UL) /*!< Enable */
6025 
6026 /* Bit 18 : Enable or disable interrupt for event COLLISION */
6027 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
6028 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
6029 #define NFCT_INTEN_COLLISION_Disabled (0x0UL) /*!< Disable */
6030 #define NFCT_INTEN_COLLISION_Enabled (0x1UL) /*!< Enable */
6031 
6032 /* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */
6033 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
6034 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
6035 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Disable */
6036 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Enable */
6037 
6038 /* Bit 12 : Enable or disable interrupt for event ENDTX */
6039 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
6040 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
6041 #define NFCT_INTEN_ENDTX_Disabled (0x0UL) /*!< Disable */
6042 #define NFCT_INTEN_ENDTX_Enabled (0x1UL) /*!< Enable */
6043 
6044 /* Bit 11 : Enable or disable interrupt for event ENDRX */
6045 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
6046 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
6047 #define NFCT_INTEN_ENDRX_Disabled (0x0UL) /*!< Disable */
6048 #define NFCT_INTEN_ENDRX_Enabled (0x1UL) /*!< Enable */
6049 
6050 /* Bit 10 : Enable or disable interrupt for event RXERROR */
6051 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
6052 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
6053 #define NFCT_INTEN_RXERROR_Disabled (0x0UL) /*!< Disable */
6054 #define NFCT_INTEN_RXERROR_Enabled (0x1UL) /*!< Enable */
6055 
6056 /* Bit 7 : Enable or disable interrupt for event ERROR */
6057 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
6058 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
6059 #define NFCT_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
6060 #define NFCT_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */
6061 
6062 /* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */
6063 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
6064 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
6065 #define NFCT_INTEN_RXFRAMEEND_Disabled (0x0UL) /*!< Disable */
6066 #define NFCT_INTEN_RXFRAMEEND_Enabled (0x1UL) /*!< Enable */
6067 
6068 /* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */
6069 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
6070 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
6071 #define NFCT_INTEN_RXFRAMESTART_Disabled (0x0UL) /*!< Disable */
6072 #define NFCT_INTEN_RXFRAMESTART_Enabled (0x1UL) /*!< Enable */
6073 
6074 /* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */
6075 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
6076 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
6077 #define NFCT_INTEN_TXFRAMEEND_Disabled (0x0UL) /*!< Disable */
6078 #define NFCT_INTEN_TXFRAMEEND_Enabled (0x1UL) /*!< Enable */
6079 
6080 /* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */
6081 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
6082 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
6083 #define NFCT_INTEN_TXFRAMESTART_Disabled (0x0UL) /*!< Disable */
6084 #define NFCT_INTEN_TXFRAMESTART_Enabled (0x1UL) /*!< Enable */
6085 
6086 /* Bit 2 : Enable or disable interrupt for event FIELDLOST */
6087 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
6088 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
6089 #define NFCT_INTEN_FIELDLOST_Disabled (0x0UL) /*!< Disable */
6090 #define NFCT_INTEN_FIELDLOST_Enabled (0x1UL) /*!< Enable */
6091 
6092 /* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */
6093 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
6094 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
6095 #define NFCT_INTEN_FIELDDETECTED_Disabled (0x0UL) /*!< Disable */
6096 #define NFCT_INTEN_FIELDDETECTED_Enabled (0x1UL) /*!< Enable */
6097 
6098 /* Bit 0 : Enable or disable interrupt for event READY */
6099 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
6100 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
6101 #define NFCT_INTEN_READY_Disabled (0x0UL) /*!< Disable */
6102 #define NFCT_INTEN_READY_Enabled (0x1UL) /*!< Enable */
6103 
6104 /* Register: NFCT_INTENSET */
6105 /* Description: Enable interrupt */
6106 
6107 /* Bit 20 : Write '1' to enable interrupt for event STARTED */
6108 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
6109 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
6110 #define NFCT_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
6111 #define NFCT_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
6112 #define NFCT_INTENSET_STARTED_Set (0x1UL) /*!< Enable */
6113 
6114 /* Bit 19 : Write '1' to enable interrupt for event SELECTED */
6115 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
6116 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
6117 #define NFCT_INTENSET_SELECTED_Disabled (0x0UL) /*!< Read: Disabled */
6118 #define NFCT_INTENSET_SELECTED_Enabled (0x1UL) /*!< Read: Enabled */
6119 #define NFCT_INTENSET_SELECTED_Set (0x1UL) /*!< Enable */
6120 
6121 /* Bit 18 : Write '1' to enable interrupt for event COLLISION */
6122 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
6123 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
6124 #define NFCT_INTENSET_COLLISION_Disabled (0x0UL) /*!< Read: Disabled */
6125 #define NFCT_INTENSET_COLLISION_Enabled (0x1UL) /*!< Read: Enabled */
6126 #define NFCT_INTENSET_COLLISION_Set (0x1UL) /*!< Enable */
6127 
6128 /* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */
6129 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
6130 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
6131 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
6132 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
6133 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (0x1UL) /*!< Enable */
6134 
6135 /* Bit 12 : Write '1' to enable interrupt for event ENDTX */
6136 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
6137 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
6138 #define NFCT_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
6139 #define NFCT_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
6140 #define NFCT_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */
6141 
6142 /* Bit 11 : Write '1' to enable interrupt for event ENDRX */
6143 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
6144 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
6145 #define NFCT_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
6146 #define NFCT_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
6147 #define NFCT_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */
6148 
6149 /* Bit 10 : Write '1' to enable interrupt for event RXERROR */
6150 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
6151 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
6152 #define NFCT_INTENSET_RXERROR_Disabled (0x0UL) /*!< Read: Disabled */
6153 #define NFCT_INTENSET_RXERROR_Enabled (0x1UL) /*!< Read: Enabled */
6154 #define NFCT_INTENSET_RXERROR_Set (0x1UL) /*!< Enable */
6155 
6156 /* Bit 7 : Write '1' to enable interrupt for event ERROR */
6157 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
6158 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
6159 #define NFCT_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
6160 #define NFCT_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
6161 #define NFCT_INTENSET_ERROR_Set (0x1UL) /*!< Enable */
6162 
6163 /* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */
6164 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
6165 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
6166 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */
6167 #define NFCT_INTENSET_RXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */
6168 #define NFCT_INTENSET_RXFRAMEEND_Set (0x1UL) /*!< Enable */
6169 
6170 /* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */
6171 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
6172 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
6173 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
6174 #define NFCT_INTENSET_RXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
6175 #define NFCT_INTENSET_RXFRAMESTART_Set (0x1UL) /*!< Enable */
6176 
6177 /* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */
6178 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
6179 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
6180 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */
6181 #define NFCT_INTENSET_TXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */
6182 #define NFCT_INTENSET_TXFRAMEEND_Set (0x1UL) /*!< Enable */
6183 
6184 /* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */
6185 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
6186 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
6187 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
6188 #define NFCT_INTENSET_TXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
6189 #define NFCT_INTENSET_TXFRAMESTART_Set (0x1UL) /*!< Enable */
6190 
6191 /* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */
6192 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
6193 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
6194 #define NFCT_INTENSET_FIELDLOST_Disabled (0x0UL) /*!< Read: Disabled */
6195 #define NFCT_INTENSET_FIELDLOST_Enabled (0x1UL) /*!< Read: Enabled */
6196 #define NFCT_INTENSET_FIELDLOST_Set (0x1UL) /*!< Enable */
6197 
6198 /* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */
6199 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
6200 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
6201 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0x0UL) /*!< Read: Disabled */
6202 #define NFCT_INTENSET_FIELDDETECTED_Enabled (0x1UL) /*!< Read: Enabled */
6203 #define NFCT_INTENSET_FIELDDETECTED_Set (0x1UL) /*!< Enable */
6204 
6205 /* Bit 0 : Write '1' to enable interrupt for event READY */
6206 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
6207 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
6208 #define NFCT_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */
6209 #define NFCT_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */
6210 #define NFCT_INTENSET_READY_Set (0x1UL) /*!< Enable */
6211 
6212 /* Register: NFCT_INTENCLR */
6213 /* Description: Disable interrupt */
6214 
6215 /* Bit 20 : Write '1' to disable interrupt for event STARTED */
6216 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
6217 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
6218 #define NFCT_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
6219 #define NFCT_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
6220 #define NFCT_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */
6221 
6222 /* Bit 19 : Write '1' to disable interrupt for event SELECTED */
6223 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
6224 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
6225 #define NFCT_INTENCLR_SELECTED_Disabled (0x0UL) /*!< Read: Disabled */
6226 #define NFCT_INTENCLR_SELECTED_Enabled (0x1UL) /*!< Read: Enabled */
6227 #define NFCT_INTENCLR_SELECTED_Clear (0x1UL) /*!< Disable */
6228 
6229 /* Bit 18 : Write '1' to disable interrupt for event COLLISION */
6230 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
6231 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
6232 #define NFCT_INTENCLR_COLLISION_Disabled (0x0UL) /*!< Read: Disabled */
6233 #define NFCT_INTENCLR_COLLISION_Enabled (0x1UL) /*!< Read: Enabled */
6234 #define NFCT_INTENCLR_COLLISION_Clear (0x1UL) /*!< Disable */
6235 
6236 /* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */
6237 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
6238 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
6239 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
6240 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
6241 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (0x1UL) /*!< Disable */
6242 
6243 /* Bit 12 : Write '1' to disable interrupt for event ENDTX */
6244 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
6245 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
6246 #define NFCT_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
6247 #define NFCT_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
6248 #define NFCT_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */
6249 
6250 /* Bit 11 : Write '1' to disable interrupt for event ENDRX */
6251 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
6252 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
6253 #define NFCT_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
6254 #define NFCT_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
6255 #define NFCT_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */
6256 
6257 /* Bit 10 : Write '1' to disable interrupt for event RXERROR */
6258 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
6259 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
6260 #define NFCT_INTENCLR_RXERROR_Disabled (0x0UL) /*!< Read: Disabled */
6261 #define NFCT_INTENCLR_RXERROR_Enabled (0x1UL) /*!< Read: Enabled */
6262 #define NFCT_INTENCLR_RXERROR_Clear (0x1UL) /*!< Disable */
6263 
6264 /* Bit 7 : Write '1' to disable interrupt for event ERROR */
6265 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
6266 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
6267 #define NFCT_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
6268 #define NFCT_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
6269 #define NFCT_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */
6270 
6271 /* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */
6272 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
6273 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
6274 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */
6275 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */
6276 #define NFCT_INTENCLR_RXFRAMEEND_Clear (0x1UL) /*!< Disable */
6277 
6278 /* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */
6279 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
6280 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
6281 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
6282 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
6283 #define NFCT_INTENCLR_RXFRAMESTART_Clear (0x1UL) /*!< Disable */
6284 
6285 /* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */
6286 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
6287 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
6288 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */
6289 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */
6290 #define NFCT_INTENCLR_TXFRAMEEND_Clear (0x1UL) /*!< Disable */
6291 
6292 /* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */
6293 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
6294 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
6295 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
6296 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
6297 #define NFCT_INTENCLR_TXFRAMESTART_Clear (0x1UL) /*!< Disable */
6298 
6299 /* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */
6300 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
6301 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
6302 #define NFCT_INTENCLR_FIELDLOST_Disabled (0x0UL) /*!< Read: Disabled */
6303 #define NFCT_INTENCLR_FIELDLOST_Enabled (0x1UL) /*!< Read: Enabled */
6304 #define NFCT_INTENCLR_FIELDLOST_Clear (0x1UL) /*!< Disable */
6305 
6306 /* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */
6307 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
6308 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
6309 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0x0UL) /*!< Read: Disabled */
6310 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (0x1UL) /*!< Read: Enabled */
6311 #define NFCT_INTENCLR_FIELDDETECTED_Clear (0x1UL) /*!< Disable */
6312 
6313 /* Bit 0 : Write '1' to disable interrupt for event READY */
6314 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
6315 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
6316 #define NFCT_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */
6317 #define NFCT_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */
6318 #define NFCT_INTENCLR_READY_Clear (0x1UL) /*!< Disable */
6319 
6320 /* Register: NFCT_ERRORSTATUS */
6321 /* Description: NFC Error Status register */
6322 
6323 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
6324 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
6325 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
6326 
6327 /* Register: NFCT_FRAMESTATUS_RX */
6328 /* Description: Result of last incoming frame */
6329 
6330 /* Bit 3 : Overrun detected */
6331 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
6332 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
6333 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0x0UL) /*!< No overrun detected */
6334 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (0x1UL) /*!< Overrun error */
6335 
6336 /* Bit 2 : Parity status of received frame */
6337 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
6338 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
6339 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0x0UL) /*!< Frame received with parity OK */
6340 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (0x1UL) /*!< Frame received with parity error */
6341 
6342 /* Bit 0 : No valid end of frame (EoF) detected */
6343 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
6344 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
6345 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0x0UL) /*!< Valid CRC detected */
6346 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (0x1UL) /*!< CRC received does not match local check */
6347 
6348 /* Register: NFCT_NFCTAGSTATE */
6349 /* Description: NfcTag state register */
6350 
6351 /* Bits 2..0 : NfcTag state */
6352 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */
6353 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */
6354 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0x0UL) /*!< Disabled or sense */
6355 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (0x2UL) /*!< RampUp */
6356 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (0x3UL) /*!< Idle */
6357 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (0x4UL) /*!< Receive */
6358 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (0x5UL) /*!< FrameDelay */
6359 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (0x6UL) /*!< Transmit */
6360 
6361 /* Register: NFCT_SLEEPSTATE */
6362 /* Description: Sleep state during automatic collision resolution */
6363 
6364 /* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE
6365         by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a
6366         GOSLEEP task. */
6367 #define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */
6368 #define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */
6369 #define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0x0UL) /*!< State is IDLE. */
6370 #define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (0x1UL) /*!< State is SLEEP_A. */
6371 
6372 /* Register: NFCT_FIELDPRESENT */
6373 /* Description: Indicates the presence or not of a valid field */
6374 
6375 /* Bit 1 : Indicates if the low level has locked to the field */
6376 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
6377 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
6378 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0x0UL) /*!< Not locked to field */
6379 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (0x1UL) /*!< Locked to field */
6380 
6381 /* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */
6382 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
6383 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
6384 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0x0UL) /*!< No valid field detected */
6385 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (0x1UL) /*!< Valid field detected */
6386 
6387 /* Register: NFCT_FRAMEDELAYMIN */
6388 /* Description: Minimum frame delay */
6389 
6390 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
6391 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
6392 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
6393 
6394 /* Register: NFCT_FRAMEDELAYMAX */
6395 /* Description: Maximum frame delay */
6396 
6397 /* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clocks */
6398 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
6399 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
6400 
6401 /* Register: NFCT_FRAMEDELAYMODE */
6402 /* Description: Configuration register for the Frame Delay Timer */
6403 
6404 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
6405 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
6406 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
6407 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0x0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
6408 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (0x1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
6409 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (0x2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
6410 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (0x3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
6411 
6412 /* Register: NFCT_PACKETPTR */
6413 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
6414 
6415 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */
6416 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
6417 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
6418 
6419 /* Register: NFCT_MAXLEN */
6420 /* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */
6421 
6422 /* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */
6423 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
6424 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
6425 
6426 /* Register: NFCT_TXD_FRAMECONFIG */
6427 /* Description: Configuration of outgoing frames */
6428 
6429 /* Bit 4 : CRC mode for outgoing frames */
6430 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
6431 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
6432 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0x0UL) /*!< CRC is not added to the frame */
6433 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (0x1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
6434 
6435 /* Bit 2 : Adding SoF or not in TX frames */
6436 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
6437 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
6438 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0x0UL) /*!< SoF symbol not added */
6439 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (0x1UL) /*!< SoF symbol added */
6440 
6441 /* Bit 1 : Discarding unused bits at start or end of a frame */
6442 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
6443 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
6444 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0x0UL) /*!< Unused bits are discarded at end of frame (EoF) */
6445 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (0x1UL) /*!< Unused bits are discarded at start of frame (SoF) */
6446 
6447 /* Bit 0 : Indicates if parity is added to the frame */
6448 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
6449 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
6450 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0x0UL) /*!< Parity is not added to TX frames */
6451 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (0x1UL) /*!< Parity is added to TX frames */
6452 
6453 /* Register: NFCT_TXD_AMOUNT */
6454 /* Description: Size of outgoing frame */
6455 
6456 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
6457 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
6458 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
6459 
6460 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
6461 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
6462 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
6463 
6464 /* Register: NFCT_RXD_FRAMECONFIG */
6465 /* Description: Configuration of incoming frames */
6466 
6467 /* Bit 4 : CRC mode for incoming frames */
6468 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
6469 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
6470 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0x0UL) /*!< CRC is not expected in RX frames */
6471 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (0x1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
6472 
6473 /* Bit 2 : SoF expected or not in RX frames */
6474 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
6475 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
6476 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0x0UL) /*!< SoF symbol is not expected in RX frames */
6477 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (0x1UL) /*!< SoF symbol is expected in RX frames */
6478 
6479 /* Bit 0 : Indicates if parity expected in RX frame */
6480 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
6481 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
6482 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0x0UL) /*!< Parity is not expected in RX frames */
6483 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (0x1UL) /*!< Parity is expected in RX frames */
6484 
6485 /* Register: NFCT_RXD_AMOUNT */
6486 /* Description: Size of last incoming frame */
6487 
6488 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
6489 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
6490 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
6491 
6492 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
6493 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
6494 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
6495 
6496 /* Register: NFCT_NFCID1_LAST */
6497 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
6498 
6499 /* Bits 31..24 : NFCID1 byte W */
6500 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
6501 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
6502 
6503 /* Bits 23..16 : NFCID1 byte X */
6504 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
6505 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
6506 
6507 /* Bits 15..8 : NFCID1 byte Y */
6508 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
6509 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
6510 
6511 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
6512 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
6513 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
6514 
6515 /* Register: NFCT_NFCID1_2ND_LAST */
6516 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
6517 
6518 /* Bits 23..16 : NFCID1 byte T */
6519 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
6520 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
6521 
6522 /* Bits 15..8 : NFCID1 byte U */
6523 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
6524 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
6525 
6526 /* Bits 7..0 : NFCID1 byte V */
6527 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
6528 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
6529 
6530 /* Register: NFCT_NFCID1_3RD_LAST */
6531 /* Description: Third last NFCID1 part (10 bytes ID) */
6532 
6533 /* Bits 23..16 : NFCID1 byte Q */
6534 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
6535 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
6536 
6537 /* Bits 15..8 : NFCID1 byte R */
6538 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
6539 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
6540 
6541 /* Bits 7..0 : NFCID1 byte S */
6542 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
6543 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
6544 
6545 /* Register: NFCT_AUTOCOLRESCONFIG */
6546 /* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. */
6547 
6548 /* Bit 0 : Enables/disables auto collision resolution */
6549 #define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
6550 #define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
6551 #define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0x0UL) /*!< Auto collision resolution enabled */
6552 #define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (0x1UL) /*!< Auto collision resolution disabled */
6553 
6554 /* Register: NFCT_SENSRES */
6555 /* Description: NFC-A SENS_RES auto-response settings */
6556 
6557 /* Bits 15..12 : Reserved for future use. Shall be 0. */
6558 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
6559 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
6560 
6561 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
6562 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
6563 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
6564 
6565 /* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */
6566 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
6567 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
6568 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0x0UL) /*!< NFCID1 size: single (4 bytes) */
6569 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (0x1UL) /*!< NFCID1 size: double (7 bytes) */
6570 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (0x2UL) /*!< NFCID1 size: triple (10 bytes) */
6571 
6572 /* Bit 5 : Reserved for future use. Shall be 0. */
6573 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
6574 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
6575 
6576 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
6577 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
6578 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
6579 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0x00UL) /*!< SDD pattern 00000 */
6580 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (0x01UL) /*!< SDD pattern 00001 */
6581 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (0x02UL) /*!< SDD pattern 00010 */
6582 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (0x04UL) /*!< SDD pattern 00100 */
6583 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (0x08UL) /*!< SDD pattern 01000 */
6584 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (0x10UL) /*!< SDD pattern 10000 */
6585 
6586 /* Register: NFCT_SELRES */
6587 /* Description: NFC-A SEL_RES auto-response settings */
6588 
6589 /* Bit 7 : Reserved for future use. Shall be 0. */
6590 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
6591 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
6592 
6593 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
6594 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
6595 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
6596 
6597 /* Bits 4..3 : Reserved for future use. Shall be 0. */
6598 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
6599 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
6600 
6601 /* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */
6602 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
6603 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
6604 
6605 /* Bits 1..0 : Reserved for future use. Shall be 0. */
6606 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
6607 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
6608 
6609 
6610 /* Peripheral: NVMC */
6611 /* Description: Non Volatile Memory Controller */
6612 
6613 /* Register: NVMC_READY */
6614 /* Description: Ready flag */
6615 
6616 /* Bit 0 : NVMC is ready or busy */
6617 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
6618 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
6619 #define NVMC_READY_READY_Busy (0x0UL) /*!< NVMC is busy (on-going write or erase operation) */
6620 #define NVMC_READY_READY_Ready (0x1UL) /*!< NVMC is ready */
6621 
6622 /* Register: NVMC_READYNEXT */
6623 /* Description: Ready flag */
6624 
6625 /* Bit 0 : NVMC can accept a new write operation */
6626 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
6627 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
6628 #define NVMC_READYNEXT_READYNEXT_Busy (0x0UL) /*!< NVMC cannot accept any write operation */
6629 #define NVMC_READYNEXT_READYNEXT_Ready (0x1UL) /*!< NVMC is ready */
6630 
6631 /* Register: NVMC_CONFIG */
6632 /* Description: Configuration register */
6633 
6634 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
6635 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
6636 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
6637 #define NVMC_CONFIG_WEN_Ren (0x0UL) /*!< Read only access */
6638 #define NVMC_CONFIG_WEN_Wen (0x1UL) /*!< Write enabled */
6639 #define NVMC_CONFIG_WEN_Een (0x2UL) /*!< Erase enabled */
6640 
6641 /* Register: NVMC_ERASEPAGE */
6642 /* Description: Register for erasing a page in code area */
6643 
6644 /* Bits 31..0 : Register for starting erase of a page in code area */
6645 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
6646 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
6647 
6648 /* Register: NVMC_ERASEALL */
6649 /* Description: Register for erasing all non-volatile user memory */
6650 
6651 /* Bit 0 : Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */
6652 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
6653 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
6654 #define NVMC_ERASEALL_ERASEALL_NoOperation (0x0UL) /*!< No operation */
6655 #define NVMC_ERASEALL_ERASEALL_Erase (0x1UL) /*!< Start chip erase */
6656 
6657 /* Register: NVMC_ERASEUICR */
6658 /* Description: Register for erasing user information configuration registers */
6659 
6660 /* Bit 0 : Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. */
6661 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
6662 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
6663 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0x0UL) /*!< No operation */
6664 #define NVMC_ERASEUICR_ERASEUICR_Erase (0x1UL) /*!< Start erase of UICR */
6665 
6666 /* Register: NVMC_ERASEPAGEPARTIAL */
6667 /* Description: Register for partial erase of a page in code area */
6668 
6669 /* Bits 31..0 : Register for starting partial erase of a page in code area */
6670 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */
6671 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */
6672 
6673 /* Register: NVMC_ERASEPAGEPARTIALCFG */
6674 /* Description: Register for partial erase configuration */
6675 
6676 /* Bits 6..0 : Duration of the partial erase in milliseconds */
6677 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
6678 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
6679 
6680 /* Register: NVMC_ICACHECNF */
6681 /* Description: I-code cache configuration register */
6682 
6683 /* Bit 8 : Cache profiling enable */
6684 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
6685 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
6686 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0x0UL) /*!< Disable cache profiling */
6687 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (0x1UL) /*!< Enable cache profiling */
6688 
6689 /* Bit 0 : Cache enable */
6690 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
6691 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
6692 #define NVMC_ICACHECNF_CACHEEN_Disabled (0x0UL) /*!< Disable cache. Invalidates all cache entries. */
6693 #define NVMC_ICACHECNF_CACHEEN_Enabled (0x1UL) /*!< Enable cache */
6694 
6695 /* Register: NVMC_IHIT */
6696 /* Description: I-code cache hit counter */
6697 
6698 /* Bits 31..0 : Number of cache hits. Register is writable, but only to '0'. */
6699 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
6700 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
6701 
6702 /* Register: NVMC_IMISS */
6703 /* Description: I-code cache miss counter */
6704 
6705 /* Bits 31..0 : Number of cache misses. Register is writable, but only to '0'. */
6706 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
6707 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
6708 
6709 
6710 /* Peripheral: GPIO */
6711 /* Description: GPIO Port 0 */
6712 
6713 /* Register: GPIO_OUT */
6714 /* Description: Write GPIO port */
6715 
6716 /* Bit 31 : Pin 31 */
6717 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6718 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6719 #define GPIO_OUT_PIN31_Low (0x0UL) /*!< Pin driver is low */
6720 #define GPIO_OUT_PIN31_High (0x1UL) /*!< Pin driver is high */
6721 
6722 /* Bit 30 : Pin 30 */
6723 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6724 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6725 #define GPIO_OUT_PIN30_Low (0x0UL) /*!< Pin driver is low */
6726 #define GPIO_OUT_PIN30_High (0x1UL) /*!< Pin driver is high */
6727 
6728 /* Bit 29 : Pin 29 */
6729 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6730 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6731 #define GPIO_OUT_PIN29_Low (0x0UL) /*!< Pin driver is low */
6732 #define GPIO_OUT_PIN29_High (0x1UL) /*!< Pin driver is high */
6733 
6734 /* Bit 28 : Pin 28 */
6735 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6736 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6737 #define GPIO_OUT_PIN28_Low (0x0UL) /*!< Pin driver is low */
6738 #define GPIO_OUT_PIN28_High (0x1UL) /*!< Pin driver is high */
6739 
6740 /* Bit 27 : Pin 27 */
6741 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6742 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6743 #define GPIO_OUT_PIN27_Low (0x0UL) /*!< Pin driver is low */
6744 #define GPIO_OUT_PIN27_High (0x1UL) /*!< Pin driver is high */
6745 
6746 /* Bit 26 : Pin 26 */
6747 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6748 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6749 #define GPIO_OUT_PIN26_Low (0x0UL) /*!< Pin driver is low */
6750 #define GPIO_OUT_PIN26_High (0x1UL) /*!< Pin driver is high */
6751 
6752 /* Bit 25 : Pin 25 */
6753 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6754 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6755 #define GPIO_OUT_PIN25_Low (0x0UL) /*!< Pin driver is low */
6756 #define GPIO_OUT_PIN25_High (0x1UL) /*!< Pin driver is high */
6757 
6758 /* Bit 24 : Pin 24 */
6759 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6760 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6761 #define GPIO_OUT_PIN24_Low (0x0UL) /*!< Pin driver is low */
6762 #define GPIO_OUT_PIN24_High (0x1UL) /*!< Pin driver is high */
6763 
6764 /* Bit 23 : Pin 23 */
6765 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6766 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6767 #define GPIO_OUT_PIN23_Low (0x0UL) /*!< Pin driver is low */
6768 #define GPIO_OUT_PIN23_High (0x1UL) /*!< Pin driver is high */
6769 
6770 /* Bit 22 : Pin 22 */
6771 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6772 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6773 #define GPIO_OUT_PIN22_Low (0x0UL) /*!< Pin driver is low */
6774 #define GPIO_OUT_PIN22_High (0x1UL) /*!< Pin driver is high */
6775 
6776 /* Bit 21 : Pin 21 */
6777 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6778 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6779 #define GPIO_OUT_PIN21_Low (0x0UL) /*!< Pin driver is low */
6780 #define GPIO_OUT_PIN21_High (0x1UL) /*!< Pin driver is high */
6781 
6782 /* Bit 20 : Pin 20 */
6783 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6784 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6785 #define GPIO_OUT_PIN20_Low (0x0UL) /*!< Pin driver is low */
6786 #define GPIO_OUT_PIN20_High (0x1UL) /*!< Pin driver is high */
6787 
6788 /* Bit 19 : Pin 19 */
6789 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6790 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6791 #define GPIO_OUT_PIN19_Low (0x0UL) /*!< Pin driver is low */
6792 #define GPIO_OUT_PIN19_High (0x1UL) /*!< Pin driver is high */
6793 
6794 /* Bit 18 : Pin 18 */
6795 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6796 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6797 #define GPIO_OUT_PIN18_Low (0x0UL) /*!< Pin driver is low */
6798 #define GPIO_OUT_PIN18_High (0x1UL) /*!< Pin driver is high */
6799 
6800 /* Bit 17 : Pin 17 */
6801 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6802 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6803 #define GPIO_OUT_PIN17_Low (0x0UL) /*!< Pin driver is low */
6804 #define GPIO_OUT_PIN17_High (0x1UL) /*!< Pin driver is high */
6805 
6806 /* Bit 16 : Pin 16 */
6807 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6808 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6809 #define GPIO_OUT_PIN16_Low (0x0UL) /*!< Pin driver is low */
6810 #define GPIO_OUT_PIN16_High (0x1UL) /*!< Pin driver is high */
6811 
6812 /* Bit 15 : Pin 15 */
6813 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6814 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6815 #define GPIO_OUT_PIN15_Low (0x0UL) /*!< Pin driver is low */
6816 #define GPIO_OUT_PIN15_High (0x1UL) /*!< Pin driver is high */
6817 
6818 /* Bit 14 : Pin 14 */
6819 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6820 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6821 #define GPIO_OUT_PIN14_Low (0x0UL) /*!< Pin driver is low */
6822 #define GPIO_OUT_PIN14_High (0x1UL) /*!< Pin driver is high */
6823 
6824 /* Bit 13 : Pin 13 */
6825 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6826 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6827 #define GPIO_OUT_PIN13_Low (0x0UL) /*!< Pin driver is low */
6828 #define GPIO_OUT_PIN13_High (0x1UL) /*!< Pin driver is high */
6829 
6830 /* Bit 12 : Pin 12 */
6831 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6832 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6833 #define GPIO_OUT_PIN12_Low (0x0UL) /*!< Pin driver is low */
6834 #define GPIO_OUT_PIN12_High (0x1UL) /*!< Pin driver is high */
6835 
6836 /* Bit 11 : Pin 11 */
6837 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6838 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6839 #define GPIO_OUT_PIN11_Low (0x0UL) /*!< Pin driver is low */
6840 #define GPIO_OUT_PIN11_High (0x1UL) /*!< Pin driver is high */
6841 
6842 /* Bit 10 : Pin 10 */
6843 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6844 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6845 #define GPIO_OUT_PIN10_Low (0x0UL) /*!< Pin driver is low */
6846 #define GPIO_OUT_PIN10_High (0x1UL) /*!< Pin driver is high */
6847 
6848 /* Bit 9 : Pin 9 */
6849 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6850 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6851 #define GPIO_OUT_PIN9_Low (0x0UL) /*!< Pin driver is low */
6852 #define GPIO_OUT_PIN9_High (0x1UL) /*!< Pin driver is high */
6853 
6854 /* Bit 8 : Pin 8 */
6855 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6856 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6857 #define GPIO_OUT_PIN8_Low (0x0UL) /*!< Pin driver is low */
6858 #define GPIO_OUT_PIN8_High (0x1UL) /*!< Pin driver is high */
6859 
6860 /* Bit 7 : Pin 7 */
6861 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6862 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6863 #define GPIO_OUT_PIN7_Low (0x0UL) /*!< Pin driver is low */
6864 #define GPIO_OUT_PIN7_High (0x1UL) /*!< Pin driver is high */
6865 
6866 /* Bit 6 : Pin 6 */
6867 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6868 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6869 #define GPIO_OUT_PIN6_Low (0x0UL) /*!< Pin driver is low */
6870 #define GPIO_OUT_PIN6_High (0x1UL) /*!< Pin driver is high */
6871 
6872 /* Bit 5 : Pin 5 */
6873 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6874 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6875 #define GPIO_OUT_PIN5_Low (0x0UL) /*!< Pin driver is low */
6876 #define GPIO_OUT_PIN5_High (0x1UL) /*!< Pin driver is high */
6877 
6878 /* Bit 4 : Pin 4 */
6879 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6880 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6881 #define GPIO_OUT_PIN4_Low (0x0UL) /*!< Pin driver is low */
6882 #define GPIO_OUT_PIN4_High (0x1UL) /*!< Pin driver is high */
6883 
6884 /* Bit 3 : Pin 3 */
6885 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6886 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6887 #define GPIO_OUT_PIN3_Low (0x0UL) /*!< Pin driver is low */
6888 #define GPIO_OUT_PIN3_High (0x1UL) /*!< Pin driver is high */
6889 
6890 /* Bit 2 : Pin 2 */
6891 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6892 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6893 #define GPIO_OUT_PIN2_Low (0x0UL) /*!< Pin driver is low */
6894 #define GPIO_OUT_PIN2_High (0x1UL) /*!< Pin driver is high */
6895 
6896 /* Bit 1 : Pin 1 */
6897 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6898 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6899 #define GPIO_OUT_PIN1_Low (0x0UL) /*!< Pin driver is low */
6900 #define GPIO_OUT_PIN1_High (0x1UL) /*!< Pin driver is high */
6901 
6902 /* Bit 0 : Pin 0 */
6903 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6904 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6905 #define GPIO_OUT_PIN0_Low (0x0UL) /*!< Pin driver is low */
6906 #define GPIO_OUT_PIN0_High (0x1UL) /*!< Pin driver is high */
6907 
6908 /* Register: GPIO_OUTSET */
6909 /* Description: Set individual bits in GPIO port */
6910 
6911 /* Bit 31 : Pin 31 */
6912 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6913 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6914 #define GPIO_OUTSET_PIN31_Low (0x0UL) /*!< Read: pin driver is low */
6915 #define GPIO_OUTSET_PIN31_High (0x1UL) /*!< Read: pin driver is high */
6916 #define GPIO_OUTSET_PIN31_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6917 
6918 /* Bit 30 : Pin 30 */
6919 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6920 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6921 #define GPIO_OUTSET_PIN30_Low (0x0UL) /*!< Read: pin driver is low */
6922 #define GPIO_OUTSET_PIN30_High (0x1UL) /*!< Read: pin driver is high */
6923 #define GPIO_OUTSET_PIN30_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6924 
6925 /* Bit 29 : Pin 29 */
6926 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6927 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6928 #define GPIO_OUTSET_PIN29_Low (0x0UL) /*!< Read: pin driver is low */
6929 #define GPIO_OUTSET_PIN29_High (0x1UL) /*!< Read: pin driver is high */
6930 #define GPIO_OUTSET_PIN29_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6931 
6932 /* Bit 28 : Pin 28 */
6933 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6934 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6935 #define GPIO_OUTSET_PIN28_Low (0x0UL) /*!< Read: pin driver is low */
6936 #define GPIO_OUTSET_PIN28_High (0x1UL) /*!< Read: pin driver is high */
6937 #define GPIO_OUTSET_PIN28_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6938 
6939 /* Bit 27 : Pin 27 */
6940 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6941 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6942 #define GPIO_OUTSET_PIN27_Low (0x0UL) /*!< Read: pin driver is low */
6943 #define GPIO_OUTSET_PIN27_High (0x1UL) /*!< Read: pin driver is high */
6944 #define GPIO_OUTSET_PIN27_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6945 
6946 /* Bit 26 : Pin 26 */
6947 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6948 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6949 #define GPIO_OUTSET_PIN26_Low (0x0UL) /*!< Read: pin driver is low */
6950 #define GPIO_OUTSET_PIN26_High (0x1UL) /*!< Read: pin driver is high */
6951 #define GPIO_OUTSET_PIN26_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6952 
6953 /* Bit 25 : Pin 25 */
6954 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6955 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6956 #define GPIO_OUTSET_PIN25_Low (0x0UL) /*!< Read: pin driver is low */
6957 #define GPIO_OUTSET_PIN25_High (0x1UL) /*!< Read: pin driver is high */
6958 #define GPIO_OUTSET_PIN25_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6959 
6960 /* Bit 24 : Pin 24 */
6961 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6962 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6963 #define GPIO_OUTSET_PIN24_Low (0x0UL) /*!< Read: pin driver is low */
6964 #define GPIO_OUTSET_PIN24_High (0x1UL) /*!< Read: pin driver is high */
6965 #define GPIO_OUTSET_PIN24_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6966 
6967 /* Bit 23 : Pin 23 */
6968 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6969 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6970 #define GPIO_OUTSET_PIN23_Low (0x0UL) /*!< Read: pin driver is low */
6971 #define GPIO_OUTSET_PIN23_High (0x1UL) /*!< Read: pin driver is high */
6972 #define GPIO_OUTSET_PIN23_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6973 
6974 /* Bit 22 : Pin 22 */
6975 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6976 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6977 #define GPIO_OUTSET_PIN22_Low (0x0UL) /*!< Read: pin driver is low */
6978 #define GPIO_OUTSET_PIN22_High (0x1UL) /*!< Read: pin driver is high */
6979 #define GPIO_OUTSET_PIN22_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6980 
6981 /* Bit 21 : Pin 21 */
6982 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6983 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6984 #define GPIO_OUTSET_PIN21_Low (0x0UL) /*!< Read: pin driver is low */
6985 #define GPIO_OUTSET_PIN21_High (0x1UL) /*!< Read: pin driver is high */
6986 #define GPIO_OUTSET_PIN21_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6987 
6988 /* Bit 20 : Pin 20 */
6989 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6990 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6991 #define GPIO_OUTSET_PIN20_Low (0x0UL) /*!< Read: pin driver is low */
6992 #define GPIO_OUTSET_PIN20_High (0x1UL) /*!< Read: pin driver is high */
6993 #define GPIO_OUTSET_PIN20_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
6994 
6995 /* Bit 19 : Pin 19 */
6996 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6997 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6998 #define GPIO_OUTSET_PIN19_Low (0x0UL) /*!< Read: pin driver is low */
6999 #define GPIO_OUTSET_PIN19_High (0x1UL) /*!< Read: pin driver is high */
7000 #define GPIO_OUTSET_PIN19_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7001 
7002 /* Bit 18 : Pin 18 */
7003 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7004 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7005 #define GPIO_OUTSET_PIN18_Low (0x0UL) /*!< Read: pin driver is low */
7006 #define GPIO_OUTSET_PIN18_High (0x1UL) /*!< Read: pin driver is high */
7007 #define GPIO_OUTSET_PIN18_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7008 
7009 /* Bit 17 : Pin 17 */
7010 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7011 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7012 #define GPIO_OUTSET_PIN17_Low (0x0UL) /*!< Read: pin driver is low */
7013 #define GPIO_OUTSET_PIN17_High (0x1UL) /*!< Read: pin driver is high */
7014 #define GPIO_OUTSET_PIN17_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7015 
7016 /* Bit 16 : Pin 16 */
7017 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7018 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7019 #define GPIO_OUTSET_PIN16_Low (0x0UL) /*!< Read: pin driver is low */
7020 #define GPIO_OUTSET_PIN16_High (0x1UL) /*!< Read: pin driver is high */
7021 #define GPIO_OUTSET_PIN16_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7022 
7023 /* Bit 15 : Pin 15 */
7024 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7025 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7026 #define GPIO_OUTSET_PIN15_Low (0x0UL) /*!< Read: pin driver is low */
7027 #define GPIO_OUTSET_PIN15_High (0x1UL) /*!< Read: pin driver is high */
7028 #define GPIO_OUTSET_PIN15_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7029 
7030 /* Bit 14 : Pin 14 */
7031 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7032 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7033 #define GPIO_OUTSET_PIN14_Low (0x0UL) /*!< Read: pin driver is low */
7034 #define GPIO_OUTSET_PIN14_High (0x1UL) /*!< Read: pin driver is high */
7035 #define GPIO_OUTSET_PIN14_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7036 
7037 /* Bit 13 : Pin 13 */
7038 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7039 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7040 #define GPIO_OUTSET_PIN13_Low (0x0UL) /*!< Read: pin driver is low */
7041 #define GPIO_OUTSET_PIN13_High (0x1UL) /*!< Read: pin driver is high */
7042 #define GPIO_OUTSET_PIN13_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7043 
7044 /* Bit 12 : Pin 12 */
7045 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7046 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7047 #define GPIO_OUTSET_PIN12_Low (0x0UL) /*!< Read: pin driver is low */
7048 #define GPIO_OUTSET_PIN12_High (0x1UL) /*!< Read: pin driver is high */
7049 #define GPIO_OUTSET_PIN12_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7050 
7051 /* Bit 11 : Pin 11 */
7052 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7053 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7054 #define GPIO_OUTSET_PIN11_Low (0x0UL) /*!< Read: pin driver is low */
7055 #define GPIO_OUTSET_PIN11_High (0x1UL) /*!< Read: pin driver is high */
7056 #define GPIO_OUTSET_PIN11_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7057 
7058 /* Bit 10 : Pin 10 */
7059 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7060 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7061 #define GPIO_OUTSET_PIN10_Low (0x0UL) /*!< Read: pin driver is low */
7062 #define GPIO_OUTSET_PIN10_High (0x1UL) /*!< Read: pin driver is high */
7063 #define GPIO_OUTSET_PIN10_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7064 
7065 /* Bit 9 : Pin 9 */
7066 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7067 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7068 #define GPIO_OUTSET_PIN9_Low (0x0UL) /*!< Read: pin driver is low */
7069 #define GPIO_OUTSET_PIN9_High (0x1UL) /*!< Read: pin driver is high */
7070 #define GPIO_OUTSET_PIN9_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7071 
7072 /* Bit 8 : Pin 8 */
7073 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7074 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7075 #define GPIO_OUTSET_PIN8_Low (0x0UL) /*!< Read: pin driver is low */
7076 #define GPIO_OUTSET_PIN8_High (0x1UL) /*!< Read: pin driver is high */
7077 #define GPIO_OUTSET_PIN8_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7078 
7079 /* Bit 7 : Pin 7 */
7080 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7081 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7082 #define GPIO_OUTSET_PIN7_Low (0x0UL) /*!< Read: pin driver is low */
7083 #define GPIO_OUTSET_PIN7_High (0x1UL) /*!< Read: pin driver is high */
7084 #define GPIO_OUTSET_PIN7_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7085 
7086 /* Bit 6 : Pin 6 */
7087 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7088 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7089 #define GPIO_OUTSET_PIN6_Low (0x0UL) /*!< Read: pin driver is low */
7090 #define GPIO_OUTSET_PIN6_High (0x1UL) /*!< Read: pin driver is high */
7091 #define GPIO_OUTSET_PIN6_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7092 
7093 /* Bit 5 : Pin 5 */
7094 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7095 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7096 #define GPIO_OUTSET_PIN5_Low (0x0UL) /*!< Read: pin driver is low */
7097 #define GPIO_OUTSET_PIN5_High (0x1UL) /*!< Read: pin driver is high */
7098 #define GPIO_OUTSET_PIN5_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7099 
7100 /* Bit 4 : Pin 4 */
7101 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7102 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7103 #define GPIO_OUTSET_PIN4_Low (0x0UL) /*!< Read: pin driver is low */
7104 #define GPIO_OUTSET_PIN4_High (0x1UL) /*!< Read: pin driver is high */
7105 #define GPIO_OUTSET_PIN4_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7106 
7107 /* Bit 3 : Pin 3 */
7108 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7109 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7110 #define GPIO_OUTSET_PIN3_Low (0x0UL) /*!< Read: pin driver is low */
7111 #define GPIO_OUTSET_PIN3_High (0x1UL) /*!< Read: pin driver is high */
7112 #define GPIO_OUTSET_PIN3_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7113 
7114 /* Bit 2 : Pin 2 */
7115 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7116 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7117 #define GPIO_OUTSET_PIN2_Low (0x0UL) /*!< Read: pin driver is low */
7118 #define GPIO_OUTSET_PIN2_High (0x1UL) /*!< Read: pin driver is high */
7119 #define GPIO_OUTSET_PIN2_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7120 
7121 /* Bit 1 : Pin 1 */
7122 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7123 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7124 #define GPIO_OUTSET_PIN1_Low (0x0UL) /*!< Read: pin driver is low */
7125 #define GPIO_OUTSET_PIN1_High (0x1UL) /*!< Read: pin driver is high */
7126 #define GPIO_OUTSET_PIN1_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7127 
7128 /* Bit 0 : Pin 0 */
7129 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7130 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7131 #define GPIO_OUTSET_PIN0_Low (0x0UL) /*!< Read: pin driver is low */
7132 #define GPIO_OUTSET_PIN0_High (0x1UL) /*!< Read: pin driver is high */
7133 #define GPIO_OUTSET_PIN0_Set (0x1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
7134 
7135 /* Register: GPIO_OUTCLR */
7136 /* Description: Clear individual bits in GPIO port */
7137 
7138 /* Bit 31 : Pin 31 */
7139 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7140 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7141 #define GPIO_OUTCLR_PIN31_Low (0x0UL) /*!< Read: pin driver is low */
7142 #define GPIO_OUTCLR_PIN31_High (0x1UL) /*!< Read: pin driver is high */
7143 #define GPIO_OUTCLR_PIN31_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7144 
7145 /* Bit 30 : Pin 30 */
7146 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7147 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7148 #define GPIO_OUTCLR_PIN30_Low (0x0UL) /*!< Read: pin driver is low */
7149 #define GPIO_OUTCLR_PIN30_High (0x1UL) /*!< Read: pin driver is high */
7150 #define GPIO_OUTCLR_PIN30_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7151 
7152 /* Bit 29 : Pin 29 */
7153 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7154 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7155 #define GPIO_OUTCLR_PIN29_Low (0x0UL) /*!< Read: pin driver is low */
7156 #define GPIO_OUTCLR_PIN29_High (0x1UL) /*!< Read: pin driver is high */
7157 #define GPIO_OUTCLR_PIN29_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7158 
7159 /* Bit 28 : Pin 28 */
7160 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7161 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7162 #define GPIO_OUTCLR_PIN28_Low (0x0UL) /*!< Read: pin driver is low */
7163 #define GPIO_OUTCLR_PIN28_High (0x1UL) /*!< Read: pin driver is high */
7164 #define GPIO_OUTCLR_PIN28_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7165 
7166 /* Bit 27 : Pin 27 */
7167 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7168 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7169 #define GPIO_OUTCLR_PIN27_Low (0x0UL) /*!< Read: pin driver is low */
7170 #define GPIO_OUTCLR_PIN27_High (0x1UL) /*!< Read: pin driver is high */
7171 #define GPIO_OUTCLR_PIN27_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7172 
7173 /* Bit 26 : Pin 26 */
7174 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7175 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7176 #define GPIO_OUTCLR_PIN26_Low (0x0UL) /*!< Read: pin driver is low */
7177 #define GPIO_OUTCLR_PIN26_High (0x1UL) /*!< Read: pin driver is high */
7178 #define GPIO_OUTCLR_PIN26_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7179 
7180 /* Bit 25 : Pin 25 */
7181 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7182 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7183 #define GPIO_OUTCLR_PIN25_Low (0x0UL) /*!< Read: pin driver is low */
7184 #define GPIO_OUTCLR_PIN25_High (0x1UL) /*!< Read: pin driver is high */
7185 #define GPIO_OUTCLR_PIN25_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7186 
7187 /* Bit 24 : Pin 24 */
7188 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7189 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7190 #define GPIO_OUTCLR_PIN24_Low (0x0UL) /*!< Read: pin driver is low */
7191 #define GPIO_OUTCLR_PIN24_High (0x1UL) /*!< Read: pin driver is high */
7192 #define GPIO_OUTCLR_PIN24_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7193 
7194 /* Bit 23 : Pin 23 */
7195 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7196 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7197 #define GPIO_OUTCLR_PIN23_Low (0x0UL) /*!< Read: pin driver is low */
7198 #define GPIO_OUTCLR_PIN23_High (0x1UL) /*!< Read: pin driver is high */
7199 #define GPIO_OUTCLR_PIN23_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7200 
7201 /* Bit 22 : Pin 22 */
7202 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7203 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7204 #define GPIO_OUTCLR_PIN22_Low (0x0UL) /*!< Read: pin driver is low */
7205 #define GPIO_OUTCLR_PIN22_High (0x1UL) /*!< Read: pin driver is high */
7206 #define GPIO_OUTCLR_PIN22_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7207 
7208 /* Bit 21 : Pin 21 */
7209 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7210 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7211 #define GPIO_OUTCLR_PIN21_Low (0x0UL) /*!< Read: pin driver is low */
7212 #define GPIO_OUTCLR_PIN21_High (0x1UL) /*!< Read: pin driver is high */
7213 #define GPIO_OUTCLR_PIN21_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7214 
7215 /* Bit 20 : Pin 20 */
7216 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7217 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7218 #define GPIO_OUTCLR_PIN20_Low (0x0UL) /*!< Read: pin driver is low */
7219 #define GPIO_OUTCLR_PIN20_High (0x1UL) /*!< Read: pin driver is high */
7220 #define GPIO_OUTCLR_PIN20_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7221 
7222 /* Bit 19 : Pin 19 */
7223 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7224 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7225 #define GPIO_OUTCLR_PIN19_Low (0x0UL) /*!< Read: pin driver is low */
7226 #define GPIO_OUTCLR_PIN19_High (0x1UL) /*!< Read: pin driver is high */
7227 #define GPIO_OUTCLR_PIN19_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7228 
7229 /* Bit 18 : Pin 18 */
7230 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7231 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7232 #define GPIO_OUTCLR_PIN18_Low (0x0UL) /*!< Read: pin driver is low */
7233 #define GPIO_OUTCLR_PIN18_High (0x1UL) /*!< Read: pin driver is high */
7234 #define GPIO_OUTCLR_PIN18_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7235 
7236 /* Bit 17 : Pin 17 */
7237 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7238 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7239 #define GPIO_OUTCLR_PIN17_Low (0x0UL) /*!< Read: pin driver is low */
7240 #define GPIO_OUTCLR_PIN17_High (0x1UL) /*!< Read: pin driver is high */
7241 #define GPIO_OUTCLR_PIN17_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7242 
7243 /* Bit 16 : Pin 16 */
7244 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7245 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7246 #define GPIO_OUTCLR_PIN16_Low (0x0UL) /*!< Read: pin driver is low */
7247 #define GPIO_OUTCLR_PIN16_High (0x1UL) /*!< Read: pin driver is high */
7248 #define GPIO_OUTCLR_PIN16_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7249 
7250 /* Bit 15 : Pin 15 */
7251 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7252 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7253 #define GPIO_OUTCLR_PIN15_Low (0x0UL) /*!< Read: pin driver is low */
7254 #define GPIO_OUTCLR_PIN15_High (0x1UL) /*!< Read: pin driver is high */
7255 #define GPIO_OUTCLR_PIN15_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7256 
7257 /* Bit 14 : Pin 14 */
7258 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7259 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7260 #define GPIO_OUTCLR_PIN14_Low (0x0UL) /*!< Read: pin driver is low */
7261 #define GPIO_OUTCLR_PIN14_High (0x1UL) /*!< Read: pin driver is high */
7262 #define GPIO_OUTCLR_PIN14_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7263 
7264 /* Bit 13 : Pin 13 */
7265 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7266 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7267 #define GPIO_OUTCLR_PIN13_Low (0x0UL) /*!< Read: pin driver is low */
7268 #define GPIO_OUTCLR_PIN13_High (0x1UL) /*!< Read: pin driver is high */
7269 #define GPIO_OUTCLR_PIN13_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7270 
7271 /* Bit 12 : Pin 12 */
7272 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7273 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7274 #define GPIO_OUTCLR_PIN12_Low (0x0UL) /*!< Read: pin driver is low */
7275 #define GPIO_OUTCLR_PIN12_High (0x1UL) /*!< Read: pin driver is high */
7276 #define GPIO_OUTCLR_PIN12_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7277 
7278 /* Bit 11 : Pin 11 */
7279 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7280 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7281 #define GPIO_OUTCLR_PIN11_Low (0x0UL) /*!< Read: pin driver is low */
7282 #define GPIO_OUTCLR_PIN11_High (0x1UL) /*!< Read: pin driver is high */
7283 #define GPIO_OUTCLR_PIN11_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7284 
7285 /* Bit 10 : Pin 10 */
7286 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7287 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7288 #define GPIO_OUTCLR_PIN10_Low (0x0UL) /*!< Read: pin driver is low */
7289 #define GPIO_OUTCLR_PIN10_High (0x1UL) /*!< Read: pin driver is high */
7290 #define GPIO_OUTCLR_PIN10_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7291 
7292 /* Bit 9 : Pin 9 */
7293 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7294 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7295 #define GPIO_OUTCLR_PIN9_Low (0x0UL) /*!< Read: pin driver is low */
7296 #define GPIO_OUTCLR_PIN9_High (0x1UL) /*!< Read: pin driver is high */
7297 #define GPIO_OUTCLR_PIN9_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7298 
7299 /* Bit 8 : Pin 8 */
7300 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7301 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7302 #define GPIO_OUTCLR_PIN8_Low (0x0UL) /*!< Read: pin driver is low */
7303 #define GPIO_OUTCLR_PIN8_High (0x1UL) /*!< Read: pin driver is high */
7304 #define GPIO_OUTCLR_PIN8_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7305 
7306 /* Bit 7 : Pin 7 */
7307 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7308 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7309 #define GPIO_OUTCLR_PIN7_Low (0x0UL) /*!< Read: pin driver is low */
7310 #define GPIO_OUTCLR_PIN7_High (0x1UL) /*!< Read: pin driver is high */
7311 #define GPIO_OUTCLR_PIN7_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7312 
7313 /* Bit 6 : Pin 6 */
7314 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7315 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7316 #define GPIO_OUTCLR_PIN6_Low (0x0UL) /*!< Read: pin driver is low */
7317 #define GPIO_OUTCLR_PIN6_High (0x1UL) /*!< Read: pin driver is high */
7318 #define GPIO_OUTCLR_PIN6_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7319 
7320 /* Bit 5 : Pin 5 */
7321 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7322 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7323 #define GPIO_OUTCLR_PIN5_Low (0x0UL) /*!< Read: pin driver is low */
7324 #define GPIO_OUTCLR_PIN5_High (0x1UL) /*!< Read: pin driver is high */
7325 #define GPIO_OUTCLR_PIN5_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7326 
7327 /* Bit 4 : Pin 4 */
7328 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7329 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7330 #define GPIO_OUTCLR_PIN4_Low (0x0UL) /*!< Read: pin driver is low */
7331 #define GPIO_OUTCLR_PIN4_High (0x1UL) /*!< Read: pin driver is high */
7332 #define GPIO_OUTCLR_PIN4_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7333 
7334 /* Bit 3 : Pin 3 */
7335 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7336 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7337 #define GPIO_OUTCLR_PIN3_Low (0x0UL) /*!< Read: pin driver is low */
7338 #define GPIO_OUTCLR_PIN3_High (0x1UL) /*!< Read: pin driver is high */
7339 #define GPIO_OUTCLR_PIN3_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7340 
7341 /* Bit 2 : Pin 2 */
7342 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7343 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7344 #define GPIO_OUTCLR_PIN2_Low (0x0UL) /*!< Read: pin driver is low */
7345 #define GPIO_OUTCLR_PIN2_High (0x1UL) /*!< Read: pin driver is high */
7346 #define GPIO_OUTCLR_PIN2_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7347 
7348 /* Bit 1 : Pin 1 */
7349 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7350 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7351 #define GPIO_OUTCLR_PIN1_Low (0x0UL) /*!< Read: pin driver is low */
7352 #define GPIO_OUTCLR_PIN1_High (0x1UL) /*!< Read: pin driver is high */
7353 #define GPIO_OUTCLR_PIN1_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7354 
7355 /* Bit 0 : Pin 0 */
7356 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7357 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7358 #define GPIO_OUTCLR_PIN0_Low (0x0UL) /*!< Read: pin driver is low */
7359 #define GPIO_OUTCLR_PIN0_High (0x1UL) /*!< Read: pin driver is high */
7360 #define GPIO_OUTCLR_PIN0_Clear (0x1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
7361 
7362 /* Register: GPIO_IN */
7363 /* Description: Read GPIO port */
7364 
7365 /* Bit 31 : Pin 31 */
7366 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7367 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7368 #define GPIO_IN_PIN31_Low (0x0UL) /*!< Pin input is low */
7369 #define GPIO_IN_PIN31_High (0x1UL) /*!< Pin input is high */
7370 
7371 /* Bit 30 : Pin 30 */
7372 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7373 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7374 #define GPIO_IN_PIN30_Low (0x0UL) /*!< Pin input is low */
7375 #define GPIO_IN_PIN30_High (0x1UL) /*!< Pin input is high */
7376 
7377 /* Bit 29 : Pin 29 */
7378 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7379 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7380 #define GPIO_IN_PIN29_Low (0x0UL) /*!< Pin input is low */
7381 #define GPIO_IN_PIN29_High (0x1UL) /*!< Pin input is high */
7382 
7383 /* Bit 28 : Pin 28 */
7384 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7385 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7386 #define GPIO_IN_PIN28_Low (0x0UL) /*!< Pin input is low */
7387 #define GPIO_IN_PIN28_High (0x1UL) /*!< Pin input is high */
7388 
7389 /* Bit 27 : Pin 27 */
7390 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7391 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7392 #define GPIO_IN_PIN27_Low (0x0UL) /*!< Pin input is low */
7393 #define GPIO_IN_PIN27_High (0x1UL) /*!< Pin input is high */
7394 
7395 /* Bit 26 : Pin 26 */
7396 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7397 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7398 #define GPIO_IN_PIN26_Low (0x0UL) /*!< Pin input is low */
7399 #define GPIO_IN_PIN26_High (0x1UL) /*!< Pin input is high */
7400 
7401 /* Bit 25 : Pin 25 */
7402 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7403 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7404 #define GPIO_IN_PIN25_Low (0x0UL) /*!< Pin input is low */
7405 #define GPIO_IN_PIN25_High (0x1UL) /*!< Pin input is high */
7406 
7407 /* Bit 24 : Pin 24 */
7408 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7409 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7410 #define GPIO_IN_PIN24_Low (0x0UL) /*!< Pin input is low */
7411 #define GPIO_IN_PIN24_High (0x1UL) /*!< Pin input is high */
7412 
7413 /* Bit 23 : Pin 23 */
7414 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7415 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7416 #define GPIO_IN_PIN23_Low (0x0UL) /*!< Pin input is low */
7417 #define GPIO_IN_PIN23_High (0x1UL) /*!< Pin input is high */
7418 
7419 /* Bit 22 : Pin 22 */
7420 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7421 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7422 #define GPIO_IN_PIN22_Low (0x0UL) /*!< Pin input is low */
7423 #define GPIO_IN_PIN22_High (0x1UL) /*!< Pin input is high */
7424 
7425 /* Bit 21 : Pin 21 */
7426 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7427 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7428 #define GPIO_IN_PIN21_Low (0x0UL) /*!< Pin input is low */
7429 #define GPIO_IN_PIN21_High (0x1UL) /*!< Pin input is high */
7430 
7431 /* Bit 20 : Pin 20 */
7432 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7433 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7434 #define GPIO_IN_PIN20_Low (0x0UL) /*!< Pin input is low */
7435 #define GPIO_IN_PIN20_High (0x1UL) /*!< Pin input is high */
7436 
7437 /* Bit 19 : Pin 19 */
7438 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7439 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7440 #define GPIO_IN_PIN19_Low (0x0UL) /*!< Pin input is low */
7441 #define GPIO_IN_PIN19_High (0x1UL) /*!< Pin input is high */
7442 
7443 /* Bit 18 : Pin 18 */
7444 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7445 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7446 #define GPIO_IN_PIN18_Low (0x0UL) /*!< Pin input is low */
7447 #define GPIO_IN_PIN18_High (0x1UL) /*!< Pin input is high */
7448 
7449 /* Bit 17 : Pin 17 */
7450 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7451 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7452 #define GPIO_IN_PIN17_Low (0x0UL) /*!< Pin input is low */
7453 #define GPIO_IN_PIN17_High (0x1UL) /*!< Pin input is high */
7454 
7455 /* Bit 16 : Pin 16 */
7456 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7457 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7458 #define GPIO_IN_PIN16_Low (0x0UL) /*!< Pin input is low */
7459 #define GPIO_IN_PIN16_High (0x1UL) /*!< Pin input is high */
7460 
7461 /* Bit 15 : Pin 15 */
7462 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7463 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7464 #define GPIO_IN_PIN15_Low (0x0UL) /*!< Pin input is low */
7465 #define GPIO_IN_PIN15_High (0x1UL) /*!< Pin input is high */
7466 
7467 /* Bit 14 : Pin 14 */
7468 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7469 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7470 #define GPIO_IN_PIN14_Low (0x0UL) /*!< Pin input is low */
7471 #define GPIO_IN_PIN14_High (0x1UL) /*!< Pin input is high */
7472 
7473 /* Bit 13 : Pin 13 */
7474 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7475 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7476 #define GPIO_IN_PIN13_Low (0x0UL) /*!< Pin input is low */
7477 #define GPIO_IN_PIN13_High (0x1UL) /*!< Pin input is high */
7478 
7479 /* Bit 12 : Pin 12 */
7480 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7481 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7482 #define GPIO_IN_PIN12_Low (0x0UL) /*!< Pin input is low */
7483 #define GPIO_IN_PIN12_High (0x1UL) /*!< Pin input is high */
7484 
7485 /* Bit 11 : Pin 11 */
7486 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7487 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7488 #define GPIO_IN_PIN11_Low (0x0UL) /*!< Pin input is low */
7489 #define GPIO_IN_PIN11_High (0x1UL) /*!< Pin input is high */
7490 
7491 /* Bit 10 : Pin 10 */
7492 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7493 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7494 #define GPIO_IN_PIN10_Low (0x0UL) /*!< Pin input is low */
7495 #define GPIO_IN_PIN10_High (0x1UL) /*!< Pin input is high */
7496 
7497 /* Bit 9 : Pin 9 */
7498 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7499 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7500 #define GPIO_IN_PIN9_Low (0x0UL) /*!< Pin input is low */
7501 #define GPIO_IN_PIN9_High (0x1UL) /*!< Pin input is high */
7502 
7503 /* Bit 8 : Pin 8 */
7504 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7505 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7506 #define GPIO_IN_PIN8_Low (0x0UL) /*!< Pin input is low */
7507 #define GPIO_IN_PIN8_High (0x1UL) /*!< Pin input is high */
7508 
7509 /* Bit 7 : Pin 7 */
7510 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7511 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7512 #define GPIO_IN_PIN7_Low (0x0UL) /*!< Pin input is low */
7513 #define GPIO_IN_PIN7_High (0x1UL) /*!< Pin input is high */
7514 
7515 /* Bit 6 : Pin 6 */
7516 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7517 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7518 #define GPIO_IN_PIN6_Low (0x0UL) /*!< Pin input is low */
7519 #define GPIO_IN_PIN6_High (0x1UL) /*!< Pin input is high */
7520 
7521 /* Bit 5 : Pin 5 */
7522 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7523 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7524 #define GPIO_IN_PIN5_Low (0x0UL) /*!< Pin input is low */
7525 #define GPIO_IN_PIN5_High (0x1UL) /*!< Pin input is high */
7526 
7527 /* Bit 4 : Pin 4 */
7528 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7529 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7530 #define GPIO_IN_PIN4_Low (0x0UL) /*!< Pin input is low */
7531 #define GPIO_IN_PIN4_High (0x1UL) /*!< Pin input is high */
7532 
7533 /* Bit 3 : Pin 3 */
7534 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7535 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7536 #define GPIO_IN_PIN3_Low (0x0UL) /*!< Pin input is low */
7537 #define GPIO_IN_PIN3_High (0x1UL) /*!< Pin input is high */
7538 
7539 /* Bit 2 : Pin 2 */
7540 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7541 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7542 #define GPIO_IN_PIN2_Low (0x0UL) /*!< Pin input is low */
7543 #define GPIO_IN_PIN2_High (0x1UL) /*!< Pin input is high */
7544 
7545 /* Bit 1 : Pin 1 */
7546 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7547 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7548 #define GPIO_IN_PIN1_Low (0x0UL) /*!< Pin input is low */
7549 #define GPIO_IN_PIN1_High (0x1UL) /*!< Pin input is high */
7550 
7551 /* Bit 0 : Pin 0 */
7552 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7553 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7554 #define GPIO_IN_PIN0_Low (0x0UL) /*!< Pin input is low */
7555 #define GPIO_IN_PIN0_High (0x1UL) /*!< Pin input is high */
7556 
7557 /* Register: GPIO_DIR */
7558 /* Description: Direction of GPIO pins */
7559 
7560 /* Bit 31 : Pin 31 */
7561 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7562 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7563 #define GPIO_DIR_PIN31_Input (0x0UL) /*!< Pin set as input */
7564 #define GPIO_DIR_PIN31_Output (0x1UL) /*!< Pin set as output */
7565 
7566 /* Bit 30 : Pin 30 */
7567 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7568 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7569 #define GPIO_DIR_PIN30_Input (0x0UL) /*!< Pin set as input */
7570 #define GPIO_DIR_PIN30_Output (0x1UL) /*!< Pin set as output */
7571 
7572 /* Bit 29 : Pin 29 */
7573 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7574 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7575 #define GPIO_DIR_PIN29_Input (0x0UL) /*!< Pin set as input */
7576 #define GPIO_DIR_PIN29_Output (0x1UL) /*!< Pin set as output */
7577 
7578 /* Bit 28 : Pin 28 */
7579 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7580 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7581 #define GPIO_DIR_PIN28_Input (0x0UL) /*!< Pin set as input */
7582 #define GPIO_DIR_PIN28_Output (0x1UL) /*!< Pin set as output */
7583 
7584 /* Bit 27 : Pin 27 */
7585 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7586 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7587 #define GPIO_DIR_PIN27_Input (0x0UL) /*!< Pin set as input */
7588 #define GPIO_DIR_PIN27_Output (0x1UL) /*!< Pin set as output */
7589 
7590 /* Bit 26 : Pin 26 */
7591 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7592 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7593 #define GPIO_DIR_PIN26_Input (0x0UL) /*!< Pin set as input */
7594 #define GPIO_DIR_PIN26_Output (0x1UL) /*!< Pin set as output */
7595 
7596 /* Bit 25 : Pin 25 */
7597 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7598 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7599 #define GPIO_DIR_PIN25_Input (0x0UL) /*!< Pin set as input */
7600 #define GPIO_DIR_PIN25_Output (0x1UL) /*!< Pin set as output */
7601 
7602 /* Bit 24 : Pin 24 */
7603 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7604 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7605 #define GPIO_DIR_PIN24_Input (0x0UL) /*!< Pin set as input */
7606 #define GPIO_DIR_PIN24_Output (0x1UL) /*!< Pin set as output */
7607 
7608 /* Bit 23 : Pin 23 */
7609 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7610 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7611 #define GPIO_DIR_PIN23_Input (0x0UL) /*!< Pin set as input */
7612 #define GPIO_DIR_PIN23_Output (0x1UL) /*!< Pin set as output */
7613 
7614 /* Bit 22 : Pin 22 */
7615 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7616 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7617 #define GPIO_DIR_PIN22_Input (0x0UL) /*!< Pin set as input */
7618 #define GPIO_DIR_PIN22_Output (0x1UL) /*!< Pin set as output */
7619 
7620 /* Bit 21 : Pin 21 */
7621 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7622 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7623 #define GPIO_DIR_PIN21_Input (0x0UL) /*!< Pin set as input */
7624 #define GPIO_DIR_PIN21_Output (0x1UL) /*!< Pin set as output */
7625 
7626 /* Bit 20 : Pin 20 */
7627 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7628 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7629 #define GPIO_DIR_PIN20_Input (0x0UL) /*!< Pin set as input */
7630 #define GPIO_DIR_PIN20_Output (0x1UL) /*!< Pin set as output */
7631 
7632 /* Bit 19 : Pin 19 */
7633 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7634 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7635 #define GPIO_DIR_PIN19_Input (0x0UL) /*!< Pin set as input */
7636 #define GPIO_DIR_PIN19_Output (0x1UL) /*!< Pin set as output */
7637 
7638 /* Bit 18 : Pin 18 */
7639 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7640 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7641 #define GPIO_DIR_PIN18_Input (0x0UL) /*!< Pin set as input */
7642 #define GPIO_DIR_PIN18_Output (0x1UL) /*!< Pin set as output */
7643 
7644 /* Bit 17 : Pin 17 */
7645 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7646 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7647 #define GPIO_DIR_PIN17_Input (0x0UL) /*!< Pin set as input */
7648 #define GPIO_DIR_PIN17_Output (0x1UL) /*!< Pin set as output */
7649 
7650 /* Bit 16 : Pin 16 */
7651 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7652 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7653 #define GPIO_DIR_PIN16_Input (0x0UL) /*!< Pin set as input */
7654 #define GPIO_DIR_PIN16_Output (0x1UL) /*!< Pin set as output */
7655 
7656 /* Bit 15 : Pin 15 */
7657 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7658 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7659 #define GPIO_DIR_PIN15_Input (0x0UL) /*!< Pin set as input */
7660 #define GPIO_DIR_PIN15_Output (0x1UL) /*!< Pin set as output */
7661 
7662 /* Bit 14 : Pin 14 */
7663 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7664 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7665 #define GPIO_DIR_PIN14_Input (0x0UL) /*!< Pin set as input */
7666 #define GPIO_DIR_PIN14_Output (0x1UL) /*!< Pin set as output */
7667 
7668 /* Bit 13 : Pin 13 */
7669 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7670 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7671 #define GPIO_DIR_PIN13_Input (0x0UL) /*!< Pin set as input */
7672 #define GPIO_DIR_PIN13_Output (0x1UL) /*!< Pin set as output */
7673 
7674 /* Bit 12 : Pin 12 */
7675 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7676 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7677 #define GPIO_DIR_PIN12_Input (0x0UL) /*!< Pin set as input */
7678 #define GPIO_DIR_PIN12_Output (0x1UL) /*!< Pin set as output */
7679 
7680 /* Bit 11 : Pin 11 */
7681 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7682 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7683 #define GPIO_DIR_PIN11_Input (0x0UL) /*!< Pin set as input */
7684 #define GPIO_DIR_PIN11_Output (0x1UL) /*!< Pin set as output */
7685 
7686 /* Bit 10 : Pin 10 */
7687 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7688 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7689 #define GPIO_DIR_PIN10_Input (0x0UL) /*!< Pin set as input */
7690 #define GPIO_DIR_PIN10_Output (0x1UL) /*!< Pin set as output */
7691 
7692 /* Bit 9 : Pin 9 */
7693 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7694 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7695 #define GPIO_DIR_PIN9_Input (0x0UL) /*!< Pin set as input */
7696 #define GPIO_DIR_PIN9_Output (0x1UL) /*!< Pin set as output */
7697 
7698 /* Bit 8 : Pin 8 */
7699 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7700 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7701 #define GPIO_DIR_PIN8_Input (0x0UL) /*!< Pin set as input */
7702 #define GPIO_DIR_PIN8_Output (0x1UL) /*!< Pin set as output */
7703 
7704 /* Bit 7 : Pin 7 */
7705 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7706 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7707 #define GPIO_DIR_PIN7_Input (0x0UL) /*!< Pin set as input */
7708 #define GPIO_DIR_PIN7_Output (0x1UL) /*!< Pin set as output */
7709 
7710 /* Bit 6 : Pin 6 */
7711 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7712 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7713 #define GPIO_DIR_PIN6_Input (0x0UL) /*!< Pin set as input */
7714 #define GPIO_DIR_PIN6_Output (0x1UL) /*!< Pin set as output */
7715 
7716 /* Bit 5 : Pin 5 */
7717 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7718 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7719 #define GPIO_DIR_PIN5_Input (0x0UL) /*!< Pin set as input */
7720 #define GPIO_DIR_PIN5_Output (0x1UL) /*!< Pin set as output */
7721 
7722 /* Bit 4 : Pin 4 */
7723 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7724 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7725 #define GPIO_DIR_PIN4_Input (0x0UL) /*!< Pin set as input */
7726 #define GPIO_DIR_PIN4_Output (0x1UL) /*!< Pin set as output */
7727 
7728 /* Bit 3 : Pin 3 */
7729 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7730 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7731 #define GPIO_DIR_PIN3_Input (0x0UL) /*!< Pin set as input */
7732 #define GPIO_DIR_PIN3_Output (0x1UL) /*!< Pin set as output */
7733 
7734 /* Bit 2 : Pin 2 */
7735 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7736 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7737 #define GPIO_DIR_PIN2_Input (0x0UL) /*!< Pin set as input */
7738 #define GPIO_DIR_PIN2_Output (0x1UL) /*!< Pin set as output */
7739 
7740 /* Bit 1 : Pin 1 */
7741 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7742 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7743 #define GPIO_DIR_PIN1_Input (0x0UL) /*!< Pin set as input */
7744 #define GPIO_DIR_PIN1_Output (0x1UL) /*!< Pin set as output */
7745 
7746 /* Bit 0 : Pin 0 */
7747 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7748 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7749 #define GPIO_DIR_PIN0_Input (0x0UL) /*!< Pin set as input */
7750 #define GPIO_DIR_PIN0_Output (0x1UL) /*!< Pin set as output */
7751 
7752 /* Register: GPIO_DIRSET */
7753 /* Description: DIR set register */
7754 
7755 /* Bit 31 : Set as output pin 31 */
7756 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7757 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7758 #define GPIO_DIRSET_PIN31_Input (0x0UL) /*!< Read: pin set as input */
7759 #define GPIO_DIRSET_PIN31_Output (0x1UL) /*!< Read: pin set as output */
7760 #define GPIO_DIRSET_PIN31_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7761 
7762 /* Bit 30 : Set as output pin 30 */
7763 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7764 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7765 #define GPIO_DIRSET_PIN30_Input (0x0UL) /*!< Read: pin set as input */
7766 #define GPIO_DIRSET_PIN30_Output (0x1UL) /*!< Read: pin set as output */
7767 #define GPIO_DIRSET_PIN30_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7768 
7769 /* Bit 29 : Set as output pin 29 */
7770 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7771 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7772 #define GPIO_DIRSET_PIN29_Input (0x0UL) /*!< Read: pin set as input */
7773 #define GPIO_DIRSET_PIN29_Output (0x1UL) /*!< Read: pin set as output */
7774 #define GPIO_DIRSET_PIN29_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7775 
7776 /* Bit 28 : Set as output pin 28 */
7777 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7778 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7779 #define GPIO_DIRSET_PIN28_Input (0x0UL) /*!< Read: pin set as input */
7780 #define GPIO_DIRSET_PIN28_Output (0x1UL) /*!< Read: pin set as output */
7781 #define GPIO_DIRSET_PIN28_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7782 
7783 /* Bit 27 : Set as output pin 27 */
7784 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7785 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7786 #define GPIO_DIRSET_PIN27_Input (0x0UL) /*!< Read: pin set as input */
7787 #define GPIO_DIRSET_PIN27_Output (0x1UL) /*!< Read: pin set as output */
7788 #define GPIO_DIRSET_PIN27_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7789 
7790 /* Bit 26 : Set as output pin 26 */
7791 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7792 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7793 #define GPIO_DIRSET_PIN26_Input (0x0UL) /*!< Read: pin set as input */
7794 #define GPIO_DIRSET_PIN26_Output (0x1UL) /*!< Read: pin set as output */
7795 #define GPIO_DIRSET_PIN26_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7796 
7797 /* Bit 25 : Set as output pin 25 */
7798 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7799 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7800 #define GPIO_DIRSET_PIN25_Input (0x0UL) /*!< Read: pin set as input */
7801 #define GPIO_DIRSET_PIN25_Output (0x1UL) /*!< Read: pin set as output */
7802 #define GPIO_DIRSET_PIN25_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7803 
7804 /* Bit 24 : Set as output pin 24 */
7805 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7806 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7807 #define GPIO_DIRSET_PIN24_Input (0x0UL) /*!< Read: pin set as input */
7808 #define GPIO_DIRSET_PIN24_Output (0x1UL) /*!< Read: pin set as output */
7809 #define GPIO_DIRSET_PIN24_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7810 
7811 /* Bit 23 : Set as output pin 23 */
7812 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7813 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7814 #define GPIO_DIRSET_PIN23_Input (0x0UL) /*!< Read: pin set as input */
7815 #define GPIO_DIRSET_PIN23_Output (0x1UL) /*!< Read: pin set as output */
7816 #define GPIO_DIRSET_PIN23_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7817 
7818 /* Bit 22 : Set as output pin 22 */
7819 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7820 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7821 #define GPIO_DIRSET_PIN22_Input (0x0UL) /*!< Read: pin set as input */
7822 #define GPIO_DIRSET_PIN22_Output (0x1UL) /*!< Read: pin set as output */
7823 #define GPIO_DIRSET_PIN22_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7824 
7825 /* Bit 21 : Set as output pin 21 */
7826 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7827 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7828 #define GPIO_DIRSET_PIN21_Input (0x0UL) /*!< Read: pin set as input */
7829 #define GPIO_DIRSET_PIN21_Output (0x1UL) /*!< Read: pin set as output */
7830 #define GPIO_DIRSET_PIN21_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7831 
7832 /* Bit 20 : Set as output pin 20 */
7833 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7834 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7835 #define GPIO_DIRSET_PIN20_Input (0x0UL) /*!< Read: pin set as input */
7836 #define GPIO_DIRSET_PIN20_Output (0x1UL) /*!< Read: pin set as output */
7837 #define GPIO_DIRSET_PIN20_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7838 
7839 /* Bit 19 : Set as output pin 19 */
7840 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7841 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7842 #define GPIO_DIRSET_PIN19_Input (0x0UL) /*!< Read: pin set as input */
7843 #define GPIO_DIRSET_PIN19_Output (0x1UL) /*!< Read: pin set as output */
7844 #define GPIO_DIRSET_PIN19_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7845 
7846 /* Bit 18 : Set as output pin 18 */
7847 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7848 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7849 #define GPIO_DIRSET_PIN18_Input (0x0UL) /*!< Read: pin set as input */
7850 #define GPIO_DIRSET_PIN18_Output (0x1UL) /*!< Read: pin set as output */
7851 #define GPIO_DIRSET_PIN18_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7852 
7853 /* Bit 17 : Set as output pin 17 */
7854 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7855 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7856 #define GPIO_DIRSET_PIN17_Input (0x0UL) /*!< Read: pin set as input */
7857 #define GPIO_DIRSET_PIN17_Output (0x1UL) /*!< Read: pin set as output */
7858 #define GPIO_DIRSET_PIN17_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7859 
7860 /* Bit 16 : Set as output pin 16 */
7861 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7862 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7863 #define GPIO_DIRSET_PIN16_Input (0x0UL) /*!< Read: pin set as input */
7864 #define GPIO_DIRSET_PIN16_Output (0x1UL) /*!< Read: pin set as output */
7865 #define GPIO_DIRSET_PIN16_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7866 
7867 /* Bit 15 : Set as output pin 15 */
7868 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7869 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7870 #define GPIO_DIRSET_PIN15_Input (0x0UL) /*!< Read: pin set as input */
7871 #define GPIO_DIRSET_PIN15_Output (0x1UL) /*!< Read: pin set as output */
7872 #define GPIO_DIRSET_PIN15_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7873 
7874 /* Bit 14 : Set as output pin 14 */
7875 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7876 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7877 #define GPIO_DIRSET_PIN14_Input (0x0UL) /*!< Read: pin set as input */
7878 #define GPIO_DIRSET_PIN14_Output (0x1UL) /*!< Read: pin set as output */
7879 #define GPIO_DIRSET_PIN14_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7880 
7881 /* Bit 13 : Set as output pin 13 */
7882 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7883 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7884 #define GPIO_DIRSET_PIN13_Input (0x0UL) /*!< Read: pin set as input */
7885 #define GPIO_DIRSET_PIN13_Output (0x1UL) /*!< Read: pin set as output */
7886 #define GPIO_DIRSET_PIN13_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7887 
7888 /* Bit 12 : Set as output pin 12 */
7889 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7890 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7891 #define GPIO_DIRSET_PIN12_Input (0x0UL) /*!< Read: pin set as input */
7892 #define GPIO_DIRSET_PIN12_Output (0x1UL) /*!< Read: pin set as output */
7893 #define GPIO_DIRSET_PIN12_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7894 
7895 /* Bit 11 : Set as output pin 11 */
7896 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7897 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7898 #define GPIO_DIRSET_PIN11_Input (0x0UL) /*!< Read: pin set as input */
7899 #define GPIO_DIRSET_PIN11_Output (0x1UL) /*!< Read: pin set as output */
7900 #define GPIO_DIRSET_PIN11_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7901 
7902 /* Bit 10 : Set as output pin 10 */
7903 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7904 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7905 #define GPIO_DIRSET_PIN10_Input (0x0UL) /*!< Read: pin set as input */
7906 #define GPIO_DIRSET_PIN10_Output (0x1UL) /*!< Read: pin set as output */
7907 #define GPIO_DIRSET_PIN10_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7908 
7909 /* Bit 9 : Set as output pin 9 */
7910 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7911 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7912 #define GPIO_DIRSET_PIN9_Input (0x0UL) /*!< Read: pin set as input */
7913 #define GPIO_DIRSET_PIN9_Output (0x1UL) /*!< Read: pin set as output */
7914 #define GPIO_DIRSET_PIN9_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7915 
7916 /* Bit 8 : Set as output pin 8 */
7917 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7918 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7919 #define GPIO_DIRSET_PIN8_Input (0x0UL) /*!< Read: pin set as input */
7920 #define GPIO_DIRSET_PIN8_Output (0x1UL) /*!< Read: pin set as output */
7921 #define GPIO_DIRSET_PIN8_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7922 
7923 /* Bit 7 : Set as output pin 7 */
7924 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7925 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7926 #define GPIO_DIRSET_PIN7_Input (0x0UL) /*!< Read: pin set as input */
7927 #define GPIO_DIRSET_PIN7_Output (0x1UL) /*!< Read: pin set as output */
7928 #define GPIO_DIRSET_PIN7_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7929 
7930 /* Bit 6 : Set as output pin 6 */
7931 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7932 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7933 #define GPIO_DIRSET_PIN6_Input (0x0UL) /*!< Read: pin set as input */
7934 #define GPIO_DIRSET_PIN6_Output (0x1UL) /*!< Read: pin set as output */
7935 #define GPIO_DIRSET_PIN6_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7936 
7937 /* Bit 5 : Set as output pin 5 */
7938 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7939 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7940 #define GPIO_DIRSET_PIN5_Input (0x0UL) /*!< Read: pin set as input */
7941 #define GPIO_DIRSET_PIN5_Output (0x1UL) /*!< Read: pin set as output */
7942 #define GPIO_DIRSET_PIN5_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7943 
7944 /* Bit 4 : Set as output pin 4 */
7945 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7946 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7947 #define GPIO_DIRSET_PIN4_Input (0x0UL) /*!< Read: pin set as input */
7948 #define GPIO_DIRSET_PIN4_Output (0x1UL) /*!< Read: pin set as output */
7949 #define GPIO_DIRSET_PIN4_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7950 
7951 /* Bit 3 : Set as output pin 3 */
7952 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7953 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7954 #define GPIO_DIRSET_PIN3_Input (0x0UL) /*!< Read: pin set as input */
7955 #define GPIO_DIRSET_PIN3_Output (0x1UL) /*!< Read: pin set as output */
7956 #define GPIO_DIRSET_PIN3_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7957 
7958 /* Bit 2 : Set as output pin 2 */
7959 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7960 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7961 #define GPIO_DIRSET_PIN2_Input (0x0UL) /*!< Read: pin set as input */
7962 #define GPIO_DIRSET_PIN2_Output (0x1UL) /*!< Read: pin set as output */
7963 #define GPIO_DIRSET_PIN2_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7964 
7965 /* Bit 1 : Set as output pin 1 */
7966 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7967 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7968 #define GPIO_DIRSET_PIN1_Input (0x0UL) /*!< Read: pin set as input */
7969 #define GPIO_DIRSET_PIN1_Output (0x1UL) /*!< Read: pin set as output */
7970 #define GPIO_DIRSET_PIN1_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7971 
7972 /* Bit 0 : Set as output pin 0 */
7973 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7974 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7975 #define GPIO_DIRSET_PIN0_Input (0x0UL) /*!< Read: pin set as input */
7976 #define GPIO_DIRSET_PIN0_Output (0x1UL) /*!< Read: pin set as output */
7977 #define GPIO_DIRSET_PIN0_Set (0x1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
7978 
7979 /* Register: GPIO_DIRCLR */
7980 /* Description: DIR clear register */
7981 
7982 /* Bit 31 : Set as input pin 31 */
7983 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7984 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7985 #define GPIO_DIRCLR_PIN31_Input (0x0UL) /*!< Read: pin set as input */
7986 #define GPIO_DIRCLR_PIN31_Output (0x1UL) /*!< Read: pin set as output */
7987 #define GPIO_DIRCLR_PIN31_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
7988 
7989 /* Bit 30 : Set as input pin 30 */
7990 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7991 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7992 #define GPIO_DIRCLR_PIN30_Input (0x0UL) /*!< Read: pin set as input */
7993 #define GPIO_DIRCLR_PIN30_Output (0x1UL) /*!< Read: pin set as output */
7994 #define GPIO_DIRCLR_PIN30_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
7995 
7996 /* Bit 29 : Set as input pin 29 */
7997 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7998 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7999 #define GPIO_DIRCLR_PIN29_Input (0x0UL) /*!< Read: pin set as input */
8000 #define GPIO_DIRCLR_PIN29_Output (0x1UL) /*!< Read: pin set as output */
8001 #define GPIO_DIRCLR_PIN29_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8002 
8003 /* Bit 28 : Set as input pin 28 */
8004 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
8005 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
8006 #define GPIO_DIRCLR_PIN28_Input (0x0UL) /*!< Read: pin set as input */
8007 #define GPIO_DIRCLR_PIN28_Output (0x1UL) /*!< Read: pin set as output */
8008 #define GPIO_DIRCLR_PIN28_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8009 
8010 /* Bit 27 : Set as input pin 27 */
8011 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
8012 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
8013 #define GPIO_DIRCLR_PIN27_Input (0x0UL) /*!< Read: pin set as input */
8014 #define GPIO_DIRCLR_PIN27_Output (0x1UL) /*!< Read: pin set as output */
8015 #define GPIO_DIRCLR_PIN27_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8016 
8017 /* Bit 26 : Set as input pin 26 */
8018 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
8019 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
8020 #define GPIO_DIRCLR_PIN26_Input (0x0UL) /*!< Read: pin set as input */
8021 #define GPIO_DIRCLR_PIN26_Output (0x1UL) /*!< Read: pin set as output */
8022 #define GPIO_DIRCLR_PIN26_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8023 
8024 /* Bit 25 : Set as input pin 25 */
8025 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
8026 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
8027 #define GPIO_DIRCLR_PIN25_Input (0x0UL) /*!< Read: pin set as input */
8028 #define GPIO_DIRCLR_PIN25_Output (0x1UL) /*!< Read: pin set as output */
8029 #define GPIO_DIRCLR_PIN25_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8030 
8031 /* Bit 24 : Set as input pin 24 */
8032 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
8033 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
8034 #define GPIO_DIRCLR_PIN24_Input (0x0UL) /*!< Read: pin set as input */
8035 #define GPIO_DIRCLR_PIN24_Output (0x1UL) /*!< Read: pin set as output */
8036 #define GPIO_DIRCLR_PIN24_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8037 
8038 /* Bit 23 : Set as input pin 23 */
8039 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
8040 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
8041 #define GPIO_DIRCLR_PIN23_Input (0x0UL) /*!< Read: pin set as input */
8042 #define GPIO_DIRCLR_PIN23_Output (0x1UL) /*!< Read: pin set as output */
8043 #define GPIO_DIRCLR_PIN23_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8044 
8045 /* Bit 22 : Set as input pin 22 */
8046 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
8047 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
8048 #define GPIO_DIRCLR_PIN22_Input (0x0UL) /*!< Read: pin set as input */
8049 #define GPIO_DIRCLR_PIN22_Output (0x1UL) /*!< Read: pin set as output */
8050 #define GPIO_DIRCLR_PIN22_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8051 
8052 /* Bit 21 : Set as input pin 21 */
8053 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
8054 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
8055 #define GPIO_DIRCLR_PIN21_Input (0x0UL) /*!< Read: pin set as input */
8056 #define GPIO_DIRCLR_PIN21_Output (0x1UL) /*!< Read: pin set as output */
8057 #define GPIO_DIRCLR_PIN21_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8058 
8059 /* Bit 20 : Set as input pin 20 */
8060 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
8061 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
8062 #define GPIO_DIRCLR_PIN20_Input (0x0UL) /*!< Read: pin set as input */
8063 #define GPIO_DIRCLR_PIN20_Output (0x1UL) /*!< Read: pin set as output */
8064 #define GPIO_DIRCLR_PIN20_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8065 
8066 /* Bit 19 : Set as input pin 19 */
8067 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
8068 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
8069 #define GPIO_DIRCLR_PIN19_Input (0x0UL) /*!< Read: pin set as input */
8070 #define GPIO_DIRCLR_PIN19_Output (0x1UL) /*!< Read: pin set as output */
8071 #define GPIO_DIRCLR_PIN19_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8072 
8073 /* Bit 18 : Set as input pin 18 */
8074 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
8075 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
8076 #define GPIO_DIRCLR_PIN18_Input (0x0UL) /*!< Read: pin set as input */
8077 #define GPIO_DIRCLR_PIN18_Output (0x1UL) /*!< Read: pin set as output */
8078 #define GPIO_DIRCLR_PIN18_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8079 
8080 /* Bit 17 : Set as input pin 17 */
8081 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
8082 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
8083 #define GPIO_DIRCLR_PIN17_Input (0x0UL) /*!< Read: pin set as input */
8084 #define GPIO_DIRCLR_PIN17_Output (0x1UL) /*!< Read: pin set as output */
8085 #define GPIO_DIRCLR_PIN17_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8086 
8087 /* Bit 16 : Set as input pin 16 */
8088 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
8089 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
8090 #define GPIO_DIRCLR_PIN16_Input (0x0UL) /*!< Read: pin set as input */
8091 #define GPIO_DIRCLR_PIN16_Output (0x1UL) /*!< Read: pin set as output */
8092 #define GPIO_DIRCLR_PIN16_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8093 
8094 /* Bit 15 : Set as input pin 15 */
8095 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
8096 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
8097 #define GPIO_DIRCLR_PIN15_Input (0x0UL) /*!< Read: pin set as input */
8098 #define GPIO_DIRCLR_PIN15_Output (0x1UL) /*!< Read: pin set as output */
8099 #define GPIO_DIRCLR_PIN15_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8100 
8101 /* Bit 14 : Set as input pin 14 */
8102 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
8103 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
8104 #define GPIO_DIRCLR_PIN14_Input (0x0UL) /*!< Read: pin set as input */
8105 #define GPIO_DIRCLR_PIN14_Output (0x1UL) /*!< Read: pin set as output */
8106 #define GPIO_DIRCLR_PIN14_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8107 
8108 /* Bit 13 : Set as input pin 13 */
8109 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
8110 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
8111 #define GPIO_DIRCLR_PIN13_Input (0x0UL) /*!< Read: pin set as input */
8112 #define GPIO_DIRCLR_PIN13_Output (0x1UL) /*!< Read: pin set as output */
8113 #define GPIO_DIRCLR_PIN13_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8114 
8115 /* Bit 12 : Set as input pin 12 */
8116 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
8117 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
8118 #define GPIO_DIRCLR_PIN12_Input (0x0UL) /*!< Read: pin set as input */
8119 #define GPIO_DIRCLR_PIN12_Output (0x1UL) /*!< Read: pin set as output */
8120 #define GPIO_DIRCLR_PIN12_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8121 
8122 /* Bit 11 : Set as input pin 11 */
8123 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
8124 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
8125 #define GPIO_DIRCLR_PIN11_Input (0x0UL) /*!< Read: pin set as input */
8126 #define GPIO_DIRCLR_PIN11_Output (0x1UL) /*!< Read: pin set as output */
8127 #define GPIO_DIRCLR_PIN11_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8128 
8129 /* Bit 10 : Set as input pin 10 */
8130 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
8131 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
8132 #define GPIO_DIRCLR_PIN10_Input (0x0UL) /*!< Read: pin set as input */
8133 #define GPIO_DIRCLR_PIN10_Output (0x1UL) /*!< Read: pin set as output */
8134 #define GPIO_DIRCLR_PIN10_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8135 
8136 /* Bit 9 : Set as input pin 9 */
8137 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
8138 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
8139 #define GPIO_DIRCLR_PIN9_Input (0x0UL) /*!< Read: pin set as input */
8140 #define GPIO_DIRCLR_PIN9_Output (0x1UL) /*!< Read: pin set as output */
8141 #define GPIO_DIRCLR_PIN9_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8142 
8143 /* Bit 8 : Set as input pin 8 */
8144 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
8145 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
8146 #define GPIO_DIRCLR_PIN8_Input (0x0UL) /*!< Read: pin set as input */
8147 #define GPIO_DIRCLR_PIN8_Output (0x1UL) /*!< Read: pin set as output */
8148 #define GPIO_DIRCLR_PIN8_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8149 
8150 /* Bit 7 : Set as input pin 7 */
8151 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
8152 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
8153 #define GPIO_DIRCLR_PIN7_Input (0x0UL) /*!< Read: pin set as input */
8154 #define GPIO_DIRCLR_PIN7_Output (0x1UL) /*!< Read: pin set as output */
8155 #define GPIO_DIRCLR_PIN7_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8156 
8157 /* Bit 6 : Set as input pin 6 */
8158 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
8159 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
8160 #define GPIO_DIRCLR_PIN6_Input (0x0UL) /*!< Read: pin set as input */
8161 #define GPIO_DIRCLR_PIN6_Output (0x1UL) /*!< Read: pin set as output */
8162 #define GPIO_DIRCLR_PIN6_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8163 
8164 /* Bit 5 : Set as input pin 5 */
8165 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
8166 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
8167 #define GPIO_DIRCLR_PIN5_Input (0x0UL) /*!< Read: pin set as input */
8168 #define GPIO_DIRCLR_PIN5_Output (0x1UL) /*!< Read: pin set as output */
8169 #define GPIO_DIRCLR_PIN5_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8170 
8171 /* Bit 4 : Set as input pin 4 */
8172 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
8173 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
8174 #define GPIO_DIRCLR_PIN4_Input (0x0UL) /*!< Read: pin set as input */
8175 #define GPIO_DIRCLR_PIN4_Output (0x1UL) /*!< Read: pin set as output */
8176 #define GPIO_DIRCLR_PIN4_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8177 
8178 /* Bit 3 : Set as input pin 3 */
8179 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
8180 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
8181 #define GPIO_DIRCLR_PIN3_Input (0x0UL) /*!< Read: pin set as input */
8182 #define GPIO_DIRCLR_PIN3_Output (0x1UL) /*!< Read: pin set as output */
8183 #define GPIO_DIRCLR_PIN3_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8184 
8185 /* Bit 2 : Set as input pin 2 */
8186 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
8187 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
8188 #define GPIO_DIRCLR_PIN2_Input (0x0UL) /*!< Read: pin set as input */
8189 #define GPIO_DIRCLR_PIN2_Output (0x1UL) /*!< Read: pin set as output */
8190 #define GPIO_DIRCLR_PIN2_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8191 
8192 /* Bit 1 : Set as input pin 1 */
8193 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
8194 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
8195 #define GPIO_DIRCLR_PIN1_Input (0x0UL) /*!< Read: pin set as input */
8196 #define GPIO_DIRCLR_PIN1_Output (0x1UL) /*!< Read: pin set as output */
8197 #define GPIO_DIRCLR_PIN1_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8198 
8199 /* Bit 0 : Set as input pin 0 */
8200 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
8201 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
8202 #define GPIO_DIRCLR_PIN0_Input (0x0UL) /*!< Read: pin set as input */
8203 #define GPIO_DIRCLR_PIN0_Output (0x1UL) /*!< Read: pin set as output */
8204 #define GPIO_DIRCLR_PIN0_Clear (0x1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
8205 
8206 /* Register: GPIO_LATCH */
8207 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
8208 
8209 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
8210 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
8211 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
8212 #define GPIO_LATCH_PIN31_NotLatched (0x0UL) /*!< Criteria has not been met */
8213 #define GPIO_LATCH_PIN31_Latched (0x1UL) /*!< Criteria has been met */
8214 
8215 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
8216 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
8217 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
8218 #define GPIO_LATCH_PIN30_NotLatched (0x0UL) /*!< Criteria has not been met */
8219 #define GPIO_LATCH_PIN30_Latched (0x1UL) /*!< Criteria has been met */
8220 
8221 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
8222 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
8223 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
8224 #define GPIO_LATCH_PIN29_NotLatched (0x0UL) /*!< Criteria has not been met */
8225 #define GPIO_LATCH_PIN29_Latched (0x1UL) /*!< Criteria has been met */
8226 
8227 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
8228 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
8229 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
8230 #define GPIO_LATCH_PIN28_NotLatched (0x0UL) /*!< Criteria has not been met */
8231 #define GPIO_LATCH_PIN28_Latched (0x1UL) /*!< Criteria has been met */
8232 
8233 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
8234 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
8235 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
8236 #define GPIO_LATCH_PIN27_NotLatched (0x0UL) /*!< Criteria has not been met */
8237 #define GPIO_LATCH_PIN27_Latched (0x1UL) /*!< Criteria has been met */
8238 
8239 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
8240 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
8241 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
8242 #define GPIO_LATCH_PIN26_NotLatched (0x0UL) /*!< Criteria has not been met */
8243 #define GPIO_LATCH_PIN26_Latched (0x1UL) /*!< Criteria has been met */
8244 
8245 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
8246 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
8247 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
8248 #define GPIO_LATCH_PIN25_NotLatched (0x0UL) /*!< Criteria has not been met */
8249 #define GPIO_LATCH_PIN25_Latched (0x1UL) /*!< Criteria has been met */
8250 
8251 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
8252 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
8253 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
8254 #define GPIO_LATCH_PIN24_NotLatched (0x0UL) /*!< Criteria has not been met */
8255 #define GPIO_LATCH_PIN24_Latched (0x1UL) /*!< Criteria has been met */
8256 
8257 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
8258 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
8259 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
8260 #define GPIO_LATCH_PIN23_NotLatched (0x0UL) /*!< Criteria has not been met */
8261 #define GPIO_LATCH_PIN23_Latched (0x1UL) /*!< Criteria has been met */
8262 
8263 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
8264 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
8265 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
8266 #define GPIO_LATCH_PIN22_NotLatched (0x0UL) /*!< Criteria has not been met */
8267 #define GPIO_LATCH_PIN22_Latched (0x1UL) /*!< Criteria has been met */
8268 
8269 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
8270 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
8271 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
8272 #define GPIO_LATCH_PIN21_NotLatched (0x0UL) /*!< Criteria has not been met */
8273 #define GPIO_LATCH_PIN21_Latched (0x1UL) /*!< Criteria has been met */
8274 
8275 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
8276 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
8277 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
8278 #define GPIO_LATCH_PIN20_NotLatched (0x0UL) /*!< Criteria has not been met */
8279 #define GPIO_LATCH_PIN20_Latched (0x1UL) /*!< Criteria has been met */
8280 
8281 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
8282 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
8283 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
8284 #define GPIO_LATCH_PIN19_NotLatched (0x0UL) /*!< Criteria has not been met */
8285 #define GPIO_LATCH_PIN19_Latched (0x1UL) /*!< Criteria has been met */
8286 
8287 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
8288 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
8289 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
8290 #define GPIO_LATCH_PIN18_NotLatched (0x0UL) /*!< Criteria has not been met */
8291 #define GPIO_LATCH_PIN18_Latched (0x1UL) /*!< Criteria has been met */
8292 
8293 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
8294 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
8295 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
8296 #define GPIO_LATCH_PIN17_NotLatched (0x0UL) /*!< Criteria has not been met */
8297 #define GPIO_LATCH_PIN17_Latched (0x1UL) /*!< Criteria has been met */
8298 
8299 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
8300 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
8301 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
8302 #define GPIO_LATCH_PIN16_NotLatched (0x0UL) /*!< Criteria has not been met */
8303 #define GPIO_LATCH_PIN16_Latched (0x1UL) /*!< Criteria has been met */
8304 
8305 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
8306 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
8307 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
8308 #define GPIO_LATCH_PIN15_NotLatched (0x0UL) /*!< Criteria has not been met */
8309 #define GPIO_LATCH_PIN15_Latched (0x1UL) /*!< Criteria has been met */
8310 
8311 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
8312 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
8313 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
8314 #define GPIO_LATCH_PIN14_NotLatched (0x0UL) /*!< Criteria has not been met */
8315 #define GPIO_LATCH_PIN14_Latched (0x1UL) /*!< Criteria has been met */
8316 
8317 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
8318 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
8319 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
8320 #define GPIO_LATCH_PIN13_NotLatched (0x0UL) /*!< Criteria has not been met */
8321 #define GPIO_LATCH_PIN13_Latched (0x1UL) /*!< Criteria has been met */
8322 
8323 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
8324 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
8325 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
8326 #define GPIO_LATCH_PIN12_NotLatched (0x0UL) /*!< Criteria has not been met */
8327 #define GPIO_LATCH_PIN12_Latched (0x1UL) /*!< Criteria has been met */
8328 
8329 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
8330 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
8331 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
8332 #define GPIO_LATCH_PIN11_NotLatched (0x0UL) /*!< Criteria has not been met */
8333 #define GPIO_LATCH_PIN11_Latched (0x1UL) /*!< Criteria has been met */
8334 
8335 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
8336 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
8337 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
8338 #define GPIO_LATCH_PIN10_NotLatched (0x0UL) /*!< Criteria has not been met */
8339 #define GPIO_LATCH_PIN10_Latched (0x1UL) /*!< Criteria has been met */
8340 
8341 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
8342 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
8343 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
8344 #define GPIO_LATCH_PIN9_NotLatched (0x0UL) /*!< Criteria has not been met */
8345 #define GPIO_LATCH_PIN9_Latched (0x1UL) /*!< Criteria has been met */
8346 
8347 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
8348 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
8349 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
8350 #define GPIO_LATCH_PIN8_NotLatched (0x0UL) /*!< Criteria has not been met */
8351 #define GPIO_LATCH_PIN8_Latched (0x1UL) /*!< Criteria has been met */
8352 
8353 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
8354 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
8355 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
8356 #define GPIO_LATCH_PIN7_NotLatched (0x0UL) /*!< Criteria has not been met */
8357 #define GPIO_LATCH_PIN7_Latched (0x1UL) /*!< Criteria has been met */
8358 
8359 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
8360 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
8361 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
8362 #define GPIO_LATCH_PIN6_NotLatched (0x0UL) /*!< Criteria has not been met */
8363 #define GPIO_LATCH_PIN6_Latched (0x1UL) /*!< Criteria has been met */
8364 
8365 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
8366 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
8367 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
8368 #define GPIO_LATCH_PIN5_NotLatched (0x0UL) /*!< Criteria has not been met */
8369 #define GPIO_LATCH_PIN5_Latched (0x1UL) /*!< Criteria has been met */
8370 
8371 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
8372 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
8373 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
8374 #define GPIO_LATCH_PIN4_NotLatched (0x0UL) /*!< Criteria has not been met */
8375 #define GPIO_LATCH_PIN4_Latched (0x1UL) /*!< Criteria has been met */
8376 
8377 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
8378 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
8379 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
8380 #define GPIO_LATCH_PIN3_NotLatched (0x0UL) /*!< Criteria has not been met */
8381 #define GPIO_LATCH_PIN3_Latched (0x1UL) /*!< Criteria has been met */
8382 
8383 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
8384 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
8385 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
8386 #define GPIO_LATCH_PIN2_NotLatched (0x0UL) /*!< Criteria has not been met */
8387 #define GPIO_LATCH_PIN2_Latched (0x1UL) /*!< Criteria has been met */
8388 
8389 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
8390 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
8391 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
8392 #define GPIO_LATCH_PIN1_NotLatched (0x0UL) /*!< Criteria has not been met */
8393 #define GPIO_LATCH_PIN1_Latched (0x1UL) /*!< Criteria has been met */
8394 
8395 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
8396 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
8397 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
8398 #define GPIO_LATCH_PIN0_NotLatched (0x0UL) /*!< Criteria has not been met */
8399 #define GPIO_LATCH_PIN0_Latched (0x1UL) /*!< Criteria has been met */
8400 
8401 /* Register: GPIO_DETECTMODE */
8402 /* Description: Select between default DETECT signal behavior and LDETECT mode */
8403 
8404 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
8405 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
8406 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
8407 #define GPIO_DETECTMODE_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */
8408 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */
8409 
8410 /* Register: GPIO_PIN_CNF */
8411 /* Description: Description collection: Configuration of GPIO pins */
8412 
8413 /* Bits 17..16 : Pin sensing mechanism */
8414 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
8415 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
8416 #define GPIO_PIN_CNF_SENSE_Disabled (0x0UL) /*!< Disabled */
8417 #define GPIO_PIN_CNF_SENSE_High (0x2UL) /*!< Sense for high level */
8418 #define GPIO_PIN_CNF_SENSE_Low (0x3UL) /*!< Sense for low level */
8419 
8420 /* Bits 10..8 : Drive configuration */
8421 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
8422 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
8423 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x0UL) /*!< Standard '0', standard '1' */
8424 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x1UL) /*!< High drive '0', standard '1' */
8425 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x2UL) /*!< Standard '0', high drive '1' */
8426 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x3UL) /*!< High drive '0', high 'drive '1'' */
8427 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
8428 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
8429 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
8430 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
8431 
8432 /* Bits 3..2 : Pull configuration */
8433 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
8434 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
8435 #define GPIO_PIN_CNF_PULL_Disabled (0x0UL) /*!< No pull */
8436 #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull down on pin */
8437 #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull up on pin */
8438 
8439 /* Bit 1 : Connect or disconnect input buffer */
8440 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
8441 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
8442 #define GPIO_PIN_CNF_INPUT_Connect (0x0UL) /*!< Connect input buffer */
8443 #define GPIO_PIN_CNF_INPUT_Disconnect (0x1UL) /*!< Disconnect input buffer */
8444 
8445 /* Bit 0 : Pin direction. Same physical register as DIR register */
8446 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
8447 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
8448 #define GPIO_PIN_CNF_DIR_Input (0x0UL) /*!< Configure pin as an input pin */
8449 #define GPIO_PIN_CNF_DIR_Output (0x1UL) /*!< Configure pin as an output pin */
8450 
8451 
8452 /* Peripheral: PDM */
8453 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
8454 
8455 /* Register: PDM_TASKS_START */
8456 /* Description: Starts continuous PDM transfer */
8457 
8458 /* Bit 0 : Starts continuous PDM transfer */
8459 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8460 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8461 #define PDM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
8462 
8463 /* Register: PDM_TASKS_STOP */
8464 /* Description: Stops PDM transfer */
8465 
8466 /* Bit 0 : Stops PDM transfer */
8467 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8468 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8469 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
8470 
8471 /* Register: PDM_EVENTS_STARTED */
8472 /* Description: PDM transfer has started */
8473 
8474 /* Bit 0 : PDM transfer has started */
8475 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
8476 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
8477 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
8478 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */
8479 
8480 /* Register: PDM_EVENTS_STOPPED */
8481 /* Description: PDM transfer has finished */
8482 
8483 /* Bit 0 : PDM transfer has finished */
8484 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8485 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8486 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
8487 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
8488 
8489 /* Register: PDM_EVENTS_END */
8490 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
8491 
8492 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
8493 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
8494 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
8495 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
8496 #define PDM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */
8497 
8498 /* Register: PDM_INTEN */
8499 /* Description: Enable or disable interrupt */
8500 
8501 /* Bit 2 : Enable or disable interrupt for event END */
8502 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
8503 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
8504 #define PDM_INTEN_END_Disabled (0x0UL) /*!< Disable */
8505 #define PDM_INTEN_END_Enabled (0x1UL) /*!< Enable */
8506 
8507 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8508 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8509 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8510 #define PDM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
8511 #define PDM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
8512 
8513 /* Bit 0 : Enable or disable interrupt for event STARTED */
8514 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
8515 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
8516 #define PDM_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */
8517 #define PDM_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */
8518 
8519 /* Register: PDM_INTENSET */
8520 /* Description: Enable interrupt */
8521 
8522 /* Bit 2 : Write '1' to enable interrupt for event END */
8523 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
8524 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
8525 #define PDM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
8526 #define PDM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
8527 #define PDM_INTENSET_END_Set (0x1UL) /*!< Enable */
8528 
8529 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
8530 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8531 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8532 #define PDM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
8533 #define PDM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
8534 #define PDM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
8535 
8536 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
8537 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
8538 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
8539 #define PDM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
8540 #define PDM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
8541 #define PDM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */
8542 
8543 /* Register: PDM_INTENCLR */
8544 /* Description: Disable interrupt */
8545 
8546 /* Bit 2 : Write '1' to disable interrupt for event END */
8547 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
8548 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
8549 #define PDM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
8550 #define PDM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
8551 #define PDM_INTENCLR_END_Clear (0x1UL) /*!< Disable */
8552 
8553 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
8554 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8555 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8556 #define PDM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
8557 #define PDM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
8558 #define PDM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
8559 
8560 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
8561 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
8562 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
8563 #define PDM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
8564 #define PDM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
8565 #define PDM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */
8566 
8567 /* Register: PDM_ENABLE */
8568 /* Description: PDM module enable register */
8569 
8570 /* Bit 0 : Enable or disable PDM module */
8571 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8572 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8573 #define PDM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
8574 #define PDM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */
8575 
8576 /* Register: PDM_PDMCLKCTRL */
8577 /* Description: PDM clock generator control */
8578 
8579 /* Bits 31..0 : PDM_CLK frequency configuration */
8580 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
8581 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
8582 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
8583 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
8584 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
8585 #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
8586 #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
8587 #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
8588 
8589 /* Register: PDM_MODE */
8590 /* Description: Defines the routing of the connected PDM microphones' signals */
8591 
8592 /* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */
8593 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
8594 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
8595 #define PDM_MODE_EDGE_LeftFalling (0x0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
8596 #define PDM_MODE_EDGE_LeftRising (0x1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
8597 
8598 /* Bit 0 : Mono or stereo operation */
8599 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
8600 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
8601 #define PDM_MODE_OPERATION_Stereo (0x0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */
8602 #define PDM_MODE_OPERATION_Mono (0x1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */
8603 
8604 /* Register: PDM_GAINL */
8605 /* Description: Left output gain adjustment */
8606 
8607 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
8608 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
8609 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
8610 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
8611 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
8612 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
8613 
8614 /* Register: PDM_GAINR */
8615 /* Description: Right output gain adjustment */
8616 
8617 /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
8618 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
8619 #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
8620 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
8621 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
8622 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
8623 
8624 /* Register: PDM_RATIO */
8625 /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
8626 
8627 /* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
8628 #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
8629 #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
8630 #define PDM_RATIO_RATIO_Ratio64 (0x0UL) /*!< Ratio of 64 */
8631 #define PDM_RATIO_RATIO_Ratio80 (0x1UL) /*!< Ratio of 80 */
8632 
8633 /* Register: PDM_PSEL_CLK */
8634 /* Description: Pin number configuration for PDM CLK signal */
8635 
8636 /* Bit 31 : Connection */
8637 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8638 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8639 #define PDM_PSEL_CLK_CONNECT_Connected (0x0UL) /*!< Connect */
8640 #define PDM_PSEL_CLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
8641 
8642 /* Bit 5 : Port number */
8643 #define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */
8644 #define PDM_PSEL_CLK_PORT_Msk (0x1UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */
8645 
8646 /* Bits 4..0 : Pin number */
8647 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
8648 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
8649 
8650 /* Register: PDM_PSEL_DIN */
8651 /* Description: Pin number configuration for PDM DIN signal */
8652 
8653 /* Bit 31 : Connection */
8654 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8655 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8656 #define PDM_PSEL_DIN_CONNECT_Connected (0x0UL) /*!< Connect */
8657 #define PDM_PSEL_DIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
8658 
8659 /* Bit 5 : Port number */
8660 #define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */
8661 #define PDM_PSEL_DIN_PORT_Msk (0x1UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */
8662 
8663 /* Bits 4..0 : Pin number */
8664 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
8665 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
8666 
8667 /* Register: PDM_SAMPLE_PTR */
8668 /* Description: RAM address pointer to write samples to with EasyDMA */
8669 
8670 /* Bits 31..0 : Address to write PDM samples to over DMA */
8671 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
8672 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
8673 
8674 /* Register: PDM_SAMPLE_MAXCNT */
8675 /* Description: Number of samples to allocate memory for in EasyDMA mode */
8676 
8677 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
8678 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
8679 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
8680 
8681 
8682 /* Peripheral: POWER */
8683 /* Description: Power control */
8684 
8685 /* Register: POWER_TASKS_CONSTLAT */
8686 /* Description: Enable Constant Latency mode */
8687 
8688 /* Bit 0 : Enable Constant Latency mode */
8689 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
8690 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
8691 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (0x1UL) /*!< Trigger task */
8692 
8693 /* Register: POWER_TASKS_LOWPWR */
8694 /* Description: Enable Low-power mode (variable latency) */
8695 
8696 /* Bit 0 : Enable Low-power mode (variable latency) */
8697 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
8698 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
8699 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (0x1UL) /*!< Trigger task */
8700 
8701 /* Register: POWER_EVENTS_POFWARN */
8702 /* Description: Power failure warning */
8703 
8704 /* Bit 0 : Power failure warning */
8705 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
8706 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
8707 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0x0UL) /*!< Event not generated */
8708 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (0x1UL) /*!< Event generated */
8709 
8710 /* Register: POWER_EVENTS_SLEEPENTER */
8711 /* Description: CPU entered WFI/WFE sleep */
8712 
8713 /* Bit 0 : CPU entered WFI/WFE sleep */
8714 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
8715 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
8716 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0x0UL) /*!< Event not generated */
8717 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (0x1UL) /*!< Event generated */
8718 
8719 /* Register: POWER_EVENTS_SLEEPEXIT */
8720 /* Description: CPU exited WFI/WFE sleep */
8721 
8722 /* Bit 0 : CPU exited WFI/WFE sleep */
8723 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
8724 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
8725 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0x0UL) /*!< Event not generated */
8726 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (0x1UL) /*!< Event generated */
8727 
8728 /* Register: POWER_EVENTS_USBDETECTED */
8729 /* Description: Voltage supply detected on VBUS */
8730 
8731 /* Bit 0 : Voltage supply detected on VBUS */
8732 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */
8733 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */
8734 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0x0UL) /*!< Event not generated */
8735 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (0x1UL) /*!< Event generated */
8736 
8737 /* Register: POWER_EVENTS_USBREMOVED */
8738 /* Description: Voltage supply removed from VBUS */
8739 
8740 /* Bit 0 : Voltage supply removed from VBUS */
8741 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */
8742 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */
8743 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0x0UL) /*!< Event not generated */
8744 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (0x1UL) /*!< Event generated */
8745 
8746 /* Register: POWER_EVENTS_USBPWRRDY */
8747 /* Description: USB 3.3 V supply ready */
8748 
8749 /* Bit 0 : USB 3.3 V supply ready */
8750 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */
8751 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */
8752 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0x0UL) /*!< Event not generated */
8753 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (0x1UL) /*!< Event generated */
8754 
8755 /* Register: POWER_INTENSET */
8756 /* Description: Enable interrupt */
8757 
8758 /* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */
8759 #define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
8760 #define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
8761 #define POWER_INTENSET_USBPWRRDY_Disabled (0x0UL) /*!< Read: Disabled */
8762 #define POWER_INTENSET_USBPWRRDY_Enabled (0x1UL) /*!< Read: Enabled */
8763 #define POWER_INTENSET_USBPWRRDY_Set (0x1UL) /*!< Enable */
8764 
8765 /* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */
8766 #define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
8767 #define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
8768 #define POWER_INTENSET_USBREMOVED_Disabled (0x0UL) /*!< Read: Disabled */
8769 #define POWER_INTENSET_USBREMOVED_Enabled (0x1UL) /*!< Read: Enabled */
8770 #define POWER_INTENSET_USBREMOVED_Set (0x1UL) /*!< Enable */
8771 
8772 /* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */
8773 #define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
8774 #define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
8775 #define POWER_INTENSET_USBDETECTED_Disabled (0x0UL) /*!< Read: Disabled */
8776 #define POWER_INTENSET_USBDETECTED_Enabled (0x1UL) /*!< Read: Enabled */
8777 #define POWER_INTENSET_USBDETECTED_Set (0x1UL) /*!< Enable */
8778 
8779 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
8780 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
8781 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
8782 #define POWER_INTENSET_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */
8783 #define POWER_INTENSET_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */
8784 #define POWER_INTENSET_SLEEPEXIT_Set (0x1UL) /*!< Enable */
8785 
8786 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
8787 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
8788 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
8789 #define POWER_INTENSET_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */
8790 #define POWER_INTENSET_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */
8791 #define POWER_INTENSET_SLEEPENTER_Set (0x1UL) /*!< Enable */
8792 
8793 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
8794 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
8795 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
8796 #define POWER_INTENSET_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */
8797 #define POWER_INTENSET_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */
8798 #define POWER_INTENSET_POFWARN_Set (0x1UL) /*!< Enable */
8799 
8800 /* Register: POWER_INTENCLR */
8801 /* Description: Disable interrupt */
8802 
8803 /* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */
8804 #define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
8805 #define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
8806 #define POWER_INTENCLR_USBPWRRDY_Disabled (0x0UL) /*!< Read: Disabled */
8807 #define POWER_INTENCLR_USBPWRRDY_Enabled (0x1UL) /*!< Read: Enabled */
8808 #define POWER_INTENCLR_USBPWRRDY_Clear (0x1UL) /*!< Disable */
8809 
8810 /* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */
8811 #define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
8812 #define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
8813 #define POWER_INTENCLR_USBREMOVED_Disabled (0x0UL) /*!< Read: Disabled */
8814 #define POWER_INTENCLR_USBREMOVED_Enabled (0x1UL) /*!< Read: Enabled */
8815 #define POWER_INTENCLR_USBREMOVED_Clear (0x1UL) /*!< Disable */
8816 
8817 /* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */
8818 #define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
8819 #define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
8820 #define POWER_INTENCLR_USBDETECTED_Disabled (0x0UL) /*!< Read: Disabled */
8821 #define POWER_INTENCLR_USBDETECTED_Enabled (0x1UL) /*!< Read: Enabled */
8822 #define POWER_INTENCLR_USBDETECTED_Clear (0x1UL) /*!< Disable */
8823 
8824 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
8825 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
8826 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
8827 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */
8828 #define POWER_INTENCLR_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */
8829 #define POWER_INTENCLR_SLEEPEXIT_Clear (0x1UL) /*!< Disable */
8830 
8831 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
8832 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
8833 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
8834 #define POWER_INTENCLR_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */
8835 #define POWER_INTENCLR_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */
8836 #define POWER_INTENCLR_SLEEPENTER_Clear (0x1UL) /*!< Disable */
8837 
8838 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
8839 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
8840 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
8841 #define POWER_INTENCLR_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */
8842 #define POWER_INTENCLR_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */
8843 #define POWER_INTENCLR_POFWARN_Clear (0x1UL) /*!< Disable */
8844 
8845 /* Register: POWER_RESETREAS */
8846 /* Description: Reset reason */
8847 
8848 /* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */
8849 #define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */
8850 #define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */
8851 #define POWER_RESETREAS_VBUS_NotDetected (0x0UL) /*!< Not detected */
8852 #define POWER_RESETREAS_VBUS_Detected (0x1UL) /*!< Detected */
8853 
8854 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
8855 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
8856 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
8857 #define POWER_RESETREAS_NFC_NotDetected (0x0UL) /*!< Not detected */
8858 #define POWER_RESETREAS_NFC_Detected (0x1UL) /*!< Detected */
8859 
8860 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
8861 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
8862 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
8863 #define POWER_RESETREAS_DIF_NotDetected (0x0UL) /*!< Not detected */
8864 #define POWER_RESETREAS_DIF_Detected (0x1UL) /*!< Detected */
8865 
8866 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
8867 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
8868 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
8869 #define POWER_RESETREAS_LPCOMP_NotDetected (0x0UL) /*!< Not detected */
8870 #define POWER_RESETREAS_LPCOMP_Detected (0x1UL) /*!< Detected */
8871 
8872 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
8873 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
8874 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
8875 #define POWER_RESETREAS_OFF_NotDetected (0x0UL) /*!< Not detected */
8876 #define POWER_RESETREAS_OFF_Detected (0x1UL) /*!< Detected */
8877 
8878 /* Bit 3 : Reset from CPU lock-up detected */
8879 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
8880 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
8881 #define POWER_RESETREAS_LOCKUP_NotDetected (0x0UL) /*!< Not detected */
8882 #define POWER_RESETREAS_LOCKUP_Detected (0x1UL) /*!< Detected */
8883 
8884 /* Bit 2 : Reset from soft reset detected */
8885 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
8886 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
8887 #define POWER_RESETREAS_SREQ_NotDetected (0x0UL) /*!< Not detected */
8888 #define POWER_RESETREAS_SREQ_Detected (0x1UL) /*!< Detected */
8889 
8890 /* Bit 1 : Reset from watchdog detected */
8891 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
8892 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
8893 #define POWER_RESETREAS_DOG_NotDetected (0x0UL) /*!< Not detected */
8894 #define POWER_RESETREAS_DOG_Detected (0x1UL) /*!< Detected */
8895 
8896 /* Bit 0 : Reset from pin-reset detected */
8897 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
8898 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
8899 #define POWER_RESETREAS_RESETPIN_NotDetected (0x0UL) /*!< Not detected */
8900 #define POWER_RESETREAS_RESETPIN_Detected (0x1UL) /*!< Detected */
8901 
8902 /* Register: POWER_RAMSTATUS */
8903 /* Description: Deprecated register - RAM status register */
8904 
8905 /* Bit 3 : RAM block 3 is on or off/powering up */
8906 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
8907 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
8908 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0x0UL) /*!< Off */
8909 #define POWER_RAMSTATUS_RAMBLOCK3_On (0x1UL) /*!< On */
8910 
8911 /* Bit 2 : RAM block 2 is on or off/powering up */
8912 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
8913 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
8914 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0x0UL) /*!< Off */
8915 #define POWER_RAMSTATUS_RAMBLOCK2_On (0x1UL) /*!< On */
8916 
8917 /* Bit 1 : RAM block 1 is on or off/powering up */
8918 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
8919 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
8920 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0x0UL) /*!< Off */
8921 #define POWER_RAMSTATUS_RAMBLOCK1_On (0x1UL) /*!< On */
8922 
8923 /* Bit 0 : RAM block 0 is on or off/powering up */
8924 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
8925 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
8926 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0x0UL) /*!< Off */
8927 #define POWER_RAMSTATUS_RAMBLOCK0_On (0x1UL) /*!< On */
8928 
8929 /* Register: POWER_USBREGSTATUS */
8930 /* Description: USB supply status */
8931 
8932 /* Bit 1 : USB supply output settling time elapsed */
8933 #define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */
8934 #define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */
8935 #define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0x0UL) /*!< USBREG output settling time not elapsed */
8936 #define POWER_USBREGSTATUS_OUTPUTRDY_Ready (0x1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */
8937 
8938 /* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */
8939 #define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */
8940 #define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */
8941 #define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0x0UL) /*!< VBUS voltage below valid threshold */
8942 #define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (0x1UL) /*!< VBUS voltage above valid threshold */
8943 
8944 /* Register: POWER_SYSTEMOFF */
8945 /* Description: System OFF register */
8946 
8947 /* Bit 0 : Enable System OFF mode */
8948 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
8949 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
8950 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (0x1UL) /*!< Enable System OFF mode */
8951 
8952 /* Register: POWER_POFCON */
8953 /* Description: Power-fail comparator configuration */
8954 
8955 /* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */
8956 #define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */
8957 #define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */
8958 #define POWER_POFCON_THRESHOLDVDDH_V27 (0x0UL) /*!< Set threshold to 2.7 V */
8959 #define POWER_POFCON_THRESHOLDVDDH_V28 (0x1UL) /*!< Set threshold to 2.8 V */
8960 #define POWER_POFCON_THRESHOLDVDDH_V29 (0x2UL) /*!< Set threshold to 2.9 V */
8961 #define POWER_POFCON_THRESHOLDVDDH_V30 (0x3UL) /*!< Set threshold to 3.0 V */
8962 #define POWER_POFCON_THRESHOLDVDDH_V31 (0x4UL) /*!< Set threshold to 3.1 V */
8963 #define POWER_POFCON_THRESHOLDVDDH_V32 (0x5UL) /*!< Set threshold to 3.2 V */
8964 #define POWER_POFCON_THRESHOLDVDDH_V33 (0x6UL) /*!< Set threshold to 3.3 V */
8965 #define POWER_POFCON_THRESHOLDVDDH_V34 (0x7UL) /*!< Set threshold to 3.4 V */
8966 #define POWER_POFCON_THRESHOLDVDDH_V35 (0x8UL) /*!< Set threshold to 3.5 V */
8967 #define POWER_POFCON_THRESHOLDVDDH_V36 (0x9UL) /*!< Set threshold to 3.6 V */
8968 #define POWER_POFCON_THRESHOLDVDDH_V37 (0xAUL) /*!< Set threshold to 3.7 V */
8969 #define POWER_POFCON_THRESHOLDVDDH_V38 (0xBUL) /*!< Set threshold to 3.8 V */
8970 #define POWER_POFCON_THRESHOLDVDDH_V39 (0xCUL) /*!< Set threshold to 3.9 V */
8971 #define POWER_POFCON_THRESHOLDVDDH_V40 (0xDUL) /*!< Set threshold to 4.0 V */
8972 #define POWER_POFCON_THRESHOLDVDDH_V41 (0xEUL) /*!< Set threshold to 4.1 V */
8973 #define POWER_POFCON_THRESHOLDVDDH_V42 (0xFUL) /*!< Set threshold to 4.2 V */
8974 
8975 /* Bits 4..1 : Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. */
8976 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
8977 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
8978 #define POWER_POFCON_THRESHOLD_V17 (0x4UL) /*!< Set threshold to 1.7 V */
8979 #define POWER_POFCON_THRESHOLD_V18 (0x5UL) /*!< Set threshold to 1.8 V */
8980 #define POWER_POFCON_THRESHOLD_V19 (0x6UL) /*!< Set threshold to 1.9 V */
8981 #define POWER_POFCON_THRESHOLD_V20 (0x7UL) /*!< Set threshold to 2.0 V */
8982 #define POWER_POFCON_THRESHOLD_V21 (0x8UL) /*!< Set threshold to 2.1 V */
8983 #define POWER_POFCON_THRESHOLD_V22 (0x9UL) /*!< Set threshold to 2.2 V */
8984 #define POWER_POFCON_THRESHOLD_V23 (0xAUL) /*!< Set threshold to 2.3 V */
8985 #define POWER_POFCON_THRESHOLD_V24 (0xBUL) /*!< Set threshold to 2.4 V */
8986 #define POWER_POFCON_THRESHOLD_V25 (0xCUL) /*!< Set threshold to 2.5 V */
8987 #define POWER_POFCON_THRESHOLD_V26 (0xDUL) /*!< Set threshold to 2.6 V */
8988 #define POWER_POFCON_THRESHOLD_V27 (0xEUL) /*!< Set threshold to 2.7 V */
8989 #define POWER_POFCON_THRESHOLD_V28 (0xFUL) /*!< Set threshold to 2.8 V */
8990 
8991 /* Bit 0 : Enable or disable power failure warning */
8992 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
8993 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
8994 #define POWER_POFCON_POF_Disabled (0x0UL) /*!< Disable */
8995 #define POWER_POFCON_POF_Enabled (0x1UL) /*!< Enable */
8996 
8997 /* Register: POWER_GPREGRET */
8998 /* Description: General purpose retention register */
8999 
9000 /* Bits 7..0 : General purpose retention register */
9001 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
9002 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
9003 
9004 /* Register: POWER_GPREGRET2 */
9005 /* Description: General purpose retention register */
9006 
9007 /* Bits 7..0 : General purpose retention register */
9008 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
9009 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
9010 
9011 /* Register: POWER_DCDCEN */
9012 /* Description: Enable DC/DC converter for REG1 stage */
9013 
9014 /* Bit 0 : Enable DC/DC converter for REG1 stage. */
9015 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
9016 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
9017 #define POWER_DCDCEN_DCDCEN_Disabled (0x0UL) /*!< Disable */
9018 #define POWER_DCDCEN_DCDCEN_Enabled (0x1UL) /*!< Enable */
9019 
9020 /* Register: POWER_DCDCEN0 */
9021 /* Description: Enable DC/DC converter for REG0 stage */
9022 
9023 /* Bit 0 : Enable DC/DC converter for REG0 stage. */
9024 #define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
9025 #define POWER_DCDCEN0_DCDCEN_Msk (0x1UL << POWER_DCDCEN0_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
9026 #define POWER_DCDCEN0_DCDCEN_Disabled (0x0UL) /*!< Disable */
9027 #define POWER_DCDCEN0_DCDCEN_Enabled (0x1UL) /*!< Enable */
9028 
9029 /* Register: POWER_MAINREGSTATUS */
9030 /* Description: Main supply status */
9031 
9032 /* Bit 0 : Main supply status */
9033 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */
9034 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */
9035 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0x0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */
9036 #define POWER_MAINREGSTATUS_MAINREGSTATUS_High (0x1UL) /*!< High voltage mode. Voltage supplied on VDDH. */
9037 
9038 /* Register: POWER_RAM_POWER */
9039 /* Description: Description cluster: RAMn power control register */
9040 
9041 /* Bit 31 : Keep retention on RAM section S15 when RAM section is off */
9042 #define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
9043 #define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
9044 #define POWER_RAM_POWER_S15RETENTION_Off (0x0UL) /*!< Off */
9045 #define POWER_RAM_POWER_S15RETENTION_On (0x1UL) /*!< On */
9046 
9047 /* Bit 30 : Keep retention on RAM section S14 when RAM section is off */
9048 #define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
9049 #define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
9050 #define POWER_RAM_POWER_S14RETENTION_Off (0x0UL) /*!< Off */
9051 #define POWER_RAM_POWER_S14RETENTION_On (0x1UL) /*!< On */
9052 
9053 /* Bit 29 : Keep retention on RAM section S13 when RAM section is off */
9054 #define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
9055 #define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
9056 #define POWER_RAM_POWER_S13RETENTION_Off (0x0UL) /*!< Off */
9057 #define POWER_RAM_POWER_S13RETENTION_On (0x1UL) /*!< On */
9058 
9059 /* Bit 28 : Keep retention on RAM section S12 when RAM section is off */
9060 #define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
9061 #define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
9062 #define POWER_RAM_POWER_S12RETENTION_Off (0x0UL) /*!< Off */
9063 #define POWER_RAM_POWER_S12RETENTION_On (0x1UL) /*!< On */
9064 
9065 /* Bit 27 : Keep retention on RAM section S11 when RAM section is off */
9066 #define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
9067 #define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
9068 #define POWER_RAM_POWER_S11RETENTION_Off (0x0UL) /*!< Off */
9069 #define POWER_RAM_POWER_S11RETENTION_On (0x1UL) /*!< On */
9070 
9071 /* Bit 26 : Keep retention on RAM section S10 when RAM section is off */
9072 #define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
9073 #define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
9074 #define POWER_RAM_POWER_S10RETENTION_Off (0x0UL) /*!< Off */
9075 #define POWER_RAM_POWER_S10RETENTION_On (0x1UL) /*!< On */
9076 
9077 /* Bit 25 : Keep retention on RAM section S9 when RAM section is off */
9078 #define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
9079 #define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
9080 #define POWER_RAM_POWER_S9RETENTION_Off (0x0UL) /*!< Off */
9081 #define POWER_RAM_POWER_S9RETENTION_On (0x1UL) /*!< On */
9082 
9083 /* Bit 24 : Keep retention on RAM section S8 when RAM section is off */
9084 #define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
9085 #define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
9086 #define POWER_RAM_POWER_S8RETENTION_Off (0x0UL) /*!< Off */
9087 #define POWER_RAM_POWER_S8RETENTION_On (0x1UL) /*!< On */
9088 
9089 /* Bit 23 : Keep retention on RAM section S7 when RAM section is off */
9090 #define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
9091 #define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
9092 #define POWER_RAM_POWER_S7RETENTION_Off (0x0UL) /*!< Off */
9093 #define POWER_RAM_POWER_S7RETENTION_On (0x1UL) /*!< On */
9094 
9095 /* Bit 22 : Keep retention on RAM section S6 when RAM section is off */
9096 #define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
9097 #define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
9098 #define POWER_RAM_POWER_S6RETENTION_Off (0x0UL) /*!< Off */
9099 #define POWER_RAM_POWER_S6RETENTION_On (0x1UL) /*!< On */
9100 
9101 /* Bit 21 : Keep retention on RAM section S5 when RAM section is off */
9102 #define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
9103 #define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
9104 #define POWER_RAM_POWER_S5RETENTION_Off (0x0UL) /*!< Off */
9105 #define POWER_RAM_POWER_S5RETENTION_On (0x1UL) /*!< On */
9106 
9107 /* Bit 20 : Keep retention on RAM section S4 when RAM section is off */
9108 #define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
9109 #define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
9110 #define POWER_RAM_POWER_S4RETENTION_Off (0x0UL) /*!< Off */
9111 #define POWER_RAM_POWER_S4RETENTION_On (0x1UL) /*!< On */
9112 
9113 /* Bit 19 : Keep retention on RAM section S3 when RAM section is off */
9114 #define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
9115 #define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
9116 #define POWER_RAM_POWER_S3RETENTION_Off (0x0UL) /*!< Off */
9117 #define POWER_RAM_POWER_S3RETENTION_On (0x1UL) /*!< On */
9118 
9119 /* Bit 18 : Keep retention on RAM section S2 when RAM section is off */
9120 #define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
9121 #define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
9122 #define POWER_RAM_POWER_S2RETENTION_Off (0x0UL) /*!< Off */
9123 #define POWER_RAM_POWER_S2RETENTION_On (0x1UL) /*!< On */
9124 
9125 /* Bit 17 : Keep retention on RAM section S1 when RAM section is off */
9126 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
9127 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
9128 #define POWER_RAM_POWER_S1RETENTION_Off (0x0UL) /*!< Off */
9129 #define POWER_RAM_POWER_S1RETENTION_On (0x1UL) /*!< On */
9130 
9131 /* Bit 16 : Keep retention on RAM section S0 when RAM section is off */
9132 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
9133 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
9134 #define POWER_RAM_POWER_S0RETENTION_Off (0x0UL) /*!< Off */
9135 #define POWER_RAM_POWER_S0RETENTION_On (0x1UL) /*!< On */
9136 
9137 /* Bit 15 : Keep RAM section S15 on or off in System ON mode. */
9138 #define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
9139 #define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
9140 #define POWER_RAM_POWER_S15POWER_Off (0x0UL) /*!< Off */
9141 #define POWER_RAM_POWER_S15POWER_On (0x1UL) /*!< On */
9142 
9143 /* Bit 14 : Keep RAM section S14 on or off in System ON mode. */
9144 #define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
9145 #define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
9146 #define POWER_RAM_POWER_S14POWER_Off (0x0UL) /*!< Off */
9147 #define POWER_RAM_POWER_S14POWER_On (0x1UL) /*!< On */
9148 
9149 /* Bit 13 : Keep RAM section S13 on or off in System ON mode. */
9150 #define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
9151 #define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
9152 #define POWER_RAM_POWER_S13POWER_Off (0x0UL) /*!< Off */
9153 #define POWER_RAM_POWER_S13POWER_On (0x1UL) /*!< On */
9154 
9155 /* Bit 12 : Keep RAM section S12 on or off in System ON mode. */
9156 #define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
9157 #define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
9158 #define POWER_RAM_POWER_S12POWER_Off (0x0UL) /*!< Off */
9159 #define POWER_RAM_POWER_S12POWER_On (0x1UL) /*!< On */
9160 
9161 /* Bit 11 : Keep RAM section S11 on or off in System ON mode. */
9162 #define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
9163 #define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
9164 #define POWER_RAM_POWER_S11POWER_Off (0x0UL) /*!< Off */
9165 #define POWER_RAM_POWER_S11POWER_On (0x1UL) /*!< On */
9166 
9167 /* Bit 10 : Keep RAM section S10 on or off in System ON mode. */
9168 #define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
9169 #define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
9170 #define POWER_RAM_POWER_S10POWER_Off (0x0UL) /*!< Off */
9171 #define POWER_RAM_POWER_S10POWER_On (0x1UL) /*!< On */
9172 
9173 /* Bit 9 : Keep RAM section S9 on or off in System ON mode. */
9174 #define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
9175 #define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
9176 #define POWER_RAM_POWER_S9POWER_Off (0x0UL) /*!< Off */
9177 #define POWER_RAM_POWER_S9POWER_On (0x1UL) /*!< On */
9178 
9179 /* Bit 8 : Keep RAM section S8 on or off in System ON mode. */
9180 #define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
9181 #define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
9182 #define POWER_RAM_POWER_S8POWER_Off (0x0UL) /*!< Off */
9183 #define POWER_RAM_POWER_S8POWER_On (0x1UL) /*!< On */
9184 
9185 /* Bit 7 : Keep RAM section S7 on or off in System ON mode. */
9186 #define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
9187 #define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
9188 #define POWER_RAM_POWER_S7POWER_Off (0x0UL) /*!< Off */
9189 #define POWER_RAM_POWER_S7POWER_On (0x1UL) /*!< On */
9190 
9191 /* Bit 6 : Keep RAM section S6 on or off in System ON mode. */
9192 #define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
9193 #define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
9194 #define POWER_RAM_POWER_S6POWER_Off (0x0UL) /*!< Off */
9195 #define POWER_RAM_POWER_S6POWER_On (0x1UL) /*!< On */
9196 
9197 /* Bit 5 : Keep RAM section S5 on or off in System ON mode. */
9198 #define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
9199 #define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
9200 #define POWER_RAM_POWER_S5POWER_Off (0x0UL) /*!< Off */
9201 #define POWER_RAM_POWER_S5POWER_On (0x1UL) /*!< On */
9202 
9203 /* Bit 4 : Keep RAM section S4 on or off in System ON mode. */
9204 #define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
9205 #define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
9206 #define POWER_RAM_POWER_S4POWER_Off (0x0UL) /*!< Off */
9207 #define POWER_RAM_POWER_S4POWER_On (0x1UL) /*!< On */
9208 
9209 /* Bit 3 : Keep RAM section S3 on or off in System ON mode. */
9210 #define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
9211 #define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
9212 #define POWER_RAM_POWER_S3POWER_Off (0x0UL) /*!< Off */
9213 #define POWER_RAM_POWER_S3POWER_On (0x1UL) /*!< On */
9214 
9215 /* Bit 2 : Keep RAM section S2 on or off in System ON mode. */
9216 #define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
9217 #define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
9218 #define POWER_RAM_POWER_S2POWER_Off (0x0UL) /*!< Off */
9219 #define POWER_RAM_POWER_S2POWER_On (0x1UL) /*!< On */
9220 
9221 /* Bit 1 : Keep RAM section S1 on or off in System ON mode. */
9222 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
9223 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
9224 #define POWER_RAM_POWER_S1POWER_Off (0x0UL) /*!< Off */
9225 #define POWER_RAM_POWER_S1POWER_On (0x1UL) /*!< On */
9226 
9227 /* Bit 0 : Keep RAM section S0 on or off in System ON mode. */
9228 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
9229 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
9230 #define POWER_RAM_POWER_S0POWER_Off (0x0UL) /*!< Off */
9231 #define POWER_RAM_POWER_S0POWER_On (0x1UL) /*!< On */
9232 
9233 /* Register: POWER_RAM_POWERSET */
9234 /* Description: Description cluster: RAMn power control set register */
9235 
9236 /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
9237 #define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
9238 #define POWER_RAM_POWERSET_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
9239 #define POWER_RAM_POWERSET_S15RETENTION_On (0x1UL) /*!< On */
9240 
9241 /* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
9242 #define POWER_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
9243 #define POWER_RAM_POWERSET_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
9244 #define POWER_RAM_POWERSET_S14RETENTION_On (0x1UL) /*!< On */
9245 
9246 /* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
9247 #define POWER_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
9248 #define POWER_RAM_POWERSET_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
9249 #define POWER_RAM_POWERSET_S13RETENTION_On (0x1UL) /*!< On */
9250 
9251 /* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
9252 #define POWER_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
9253 #define POWER_RAM_POWERSET_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
9254 #define POWER_RAM_POWERSET_S12RETENTION_On (0x1UL) /*!< On */
9255 
9256 /* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
9257 #define POWER_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
9258 #define POWER_RAM_POWERSET_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
9259 #define POWER_RAM_POWERSET_S11RETENTION_On (0x1UL) /*!< On */
9260 
9261 /* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
9262 #define POWER_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
9263 #define POWER_RAM_POWERSET_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
9264 #define POWER_RAM_POWERSET_S10RETENTION_On (0x1UL) /*!< On */
9265 
9266 /* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
9267 #define POWER_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
9268 #define POWER_RAM_POWERSET_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
9269 #define POWER_RAM_POWERSET_S9RETENTION_On (0x1UL) /*!< On */
9270 
9271 /* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
9272 #define POWER_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
9273 #define POWER_RAM_POWERSET_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
9274 #define POWER_RAM_POWERSET_S8RETENTION_On (0x1UL) /*!< On */
9275 
9276 /* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
9277 #define POWER_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
9278 #define POWER_RAM_POWERSET_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
9279 #define POWER_RAM_POWERSET_S7RETENTION_On (0x1UL) /*!< On */
9280 
9281 /* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
9282 #define POWER_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
9283 #define POWER_RAM_POWERSET_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
9284 #define POWER_RAM_POWERSET_S6RETENTION_On (0x1UL) /*!< On */
9285 
9286 /* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
9287 #define POWER_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
9288 #define POWER_RAM_POWERSET_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
9289 #define POWER_RAM_POWERSET_S5RETENTION_On (0x1UL) /*!< On */
9290 
9291 /* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
9292 #define POWER_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
9293 #define POWER_RAM_POWERSET_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
9294 #define POWER_RAM_POWERSET_S4RETENTION_On (0x1UL) /*!< On */
9295 
9296 /* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
9297 #define POWER_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
9298 #define POWER_RAM_POWERSET_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
9299 #define POWER_RAM_POWERSET_S3RETENTION_On (0x1UL) /*!< On */
9300 
9301 /* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
9302 #define POWER_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
9303 #define POWER_RAM_POWERSET_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
9304 #define POWER_RAM_POWERSET_S2RETENTION_On (0x1UL) /*!< On */
9305 
9306 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
9307 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
9308 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
9309 #define POWER_RAM_POWERSET_S1RETENTION_On (0x1UL) /*!< On */
9310 
9311 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
9312 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
9313 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
9314 #define POWER_RAM_POWERSET_S0RETENTION_On (0x1UL) /*!< On */
9315 
9316 /* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */
9317 #define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
9318 #define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
9319 #define POWER_RAM_POWERSET_S15POWER_On (0x1UL) /*!< On */
9320 
9321 /* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */
9322 #define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
9323 #define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
9324 #define POWER_RAM_POWERSET_S14POWER_On (0x1UL) /*!< On */
9325 
9326 /* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */
9327 #define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
9328 #define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
9329 #define POWER_RAM_POWERSET_S13POWER_On (0x1UL) /*!< On */
9330 
9331 /* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */
9332 #define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
9333 #define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
9334 #define POWER_RAM_POWERSET_S12POWER_On (0x1UL) /*!< On */
9335 
9336 /* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */
9337 #define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
9338 #define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
9339 #define POWER_RAM_POWERSET_S11POWER_On (0x1UL) /*!< On */
9340 
9341 /* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */
9342 #define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
9343 #define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
9344 #define POWER_RAM_POWERSET_S10POWER_On (0x1UL) /*!< On */
9345 
9346 /* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */
9347 #define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
9348 #define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
9349 #define POWER_RAM_POWERSET_S9POWER_On (0x1UL) /*!< On */
9350 
9351 /* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */
9352 #define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
9353 #define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
9354 #define POWER_RAM_POWERSET_S8POWER_On (0x1UL) /*!< On */
9355 
9356 /* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */
9357 #define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
9358 #define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
9359 #define POWER_RAM_POWERSET_S7POWER_On (0x1UL) /*!< On */
9360 
9361 /* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */
9362 #define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
9363 #define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
9364 #define POWER_RAM_POWERSET_S6POWER_On (0x1UL) /*!< On */
9365 
9366 /* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */
9367 #define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
9368 #define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
9369 #define POWER_RAM_POWERSET_S5POWER_On (0x1UL) /*!< On */
9370 
9371 /* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */
9372 #define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
9373 #define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
9374 #define POWER_RAM_POWERSET_S4POWER_On (0x1UL) /*!< On */
9375 
9376 /* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */
9377 #define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
9378 #define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
9379 #define POWER_RAM_POWERSET_S3POWER_On (0x1UL) /*!< On */
9380 
9381 /* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
9382 #define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
9383 #define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
9384 #define POWER_RAM_POWERSET_S2POWER_On (0x1UL) /*!< On */
9385 
9386 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
9387 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
9388 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
9389 #define POWER_RAM_POWERSET_S1POWER_On (0x1UL) /*!< On */
9390 
9391 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
9392 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
9393 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
9394 #define POWER_RAM_POWERSET_S0POWER_On (0x1UL) /*!< On */
9395 
9396 /* Register: POWER_RAM_POWERCLR */
9397 /* Description: Description cluster: RAMn power control clear register */
9398 
9399 /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
9400 #define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
9401 #define POWER_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
9402 #define POWER_RAM_POWERCLR_S15RETENTION_Off (0x1UL) /*!< Off */
9403 
9404 /* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
9405 #define POWER_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
9406 #define POWER_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
9407 #define POWER_RAM_POWERCLR_S14RETENTION_Off (0x1UL) /*!< Off */
9408 
9409 /* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
9410 #define POWER_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
9411 #define POWER_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
9412 #define POWER_RAM_POWERCLR_S13RETENTION_Off (0x1UL) /*!< Off */
9413 
9414 /* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
9415 #define POWER_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
9416 #define POWER_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
9417 #define POWER_RAM_POWERCLR_S12RETENTION_Off (0x1UL) /*!< Off */
9418 
9419 /* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
9420 #define POWER_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
9421 #define POWER_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
9422 #define POWER_RAM_POWERCLR_S11RETENTION_Off (0x1UL) /*!< Off */
9423 
9424 /* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
9425 #define POWER_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
9426 #define POWER_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
9427 #define POWER_RAM_POWERCLR_S10RETENTION_Off (0x1UL) /*!< Off */
9428 
9429 /* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
9430 #define POWER_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
9431 #define POWER_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
9432 #define POWER_RAM_POWERCLR_S9RETENTION_Off (0x1UL) /*!< Off */
9433 
9434 /* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
9435 #define POWER_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
9436 #define POWER_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
9437 #define POWER_RAM_POWERCLR_S8RETENTION_Off (0x1UL) /*!< Off */
9438 
9439 /* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
9440 #define POWER_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
9441 #define POWER_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
9442 #define POWER_RAM_POWERCLR_S7RETENTION_Off (0x1UL) /*!< Off */
9443 
9444 /* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
9445 #define POWER_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
9446 #define POWER_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
9447 #define POWER_RAM_POWERCLR_S6RETENTION_Off (0x1UL) /*!< Off */
9448 
9449 /* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
9450 #define POWER_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
9451 #define POWER_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
9452 #define POWER_RAM_POWERCLR_S5RETENTION_Off (0x1UL) /*!< Off */
9453 
9454 /* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
9455 #define POWER_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
9456 #define POWER_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
9457 #define POWER_RAM_POWERCLR_S4RETENTION_Off (0x1UL) /*!< Off */
9458 
9459 /* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
9460 #define POWER_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
9461 #define POWER_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
9462 #define POWER_RAM_POWERCLR_S3RETENTION_Off (0x1UL) /*!< Off */
9463 
9464 /* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
9465 #define POWER_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
9466 #define POWER_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
9467 #define POWER_RAM_POWERCLR_S2RETENTION_Off (0x1UL) /*!< Off */
9468 
9469 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
9470 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
9471 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
9472 #define POWER_RAM_POWERCLR_S1RETENTION_Off (0x1UL) /*!< Off */
9473 
9474 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
9475 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
9476 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
9477 #define POWER_RAM_POWERCLR_S0RETENTION_Off (0x1UL) /*!< Off */
9478 
9479 /* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */
9480 #define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
9481 #define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
9482 #define POWER_RAM_POWERCLR_S15POWER_Off (0x1UL) /*!< Off */
9483 
9484 /* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */
9485 #define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
9486 #define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
9487 #define POWER_RAM_POWERCLR_S14POWER_Off (0x1UL) /*!< Off */
9488 
9489 /* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */
9490 #define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
9491 #define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
9492 #define POWER_RAM_POWERCLR_S13POWER_Off (0x1UL) /*!< Off */
9493 
9494 /* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */
9495 #define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
9496 #define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
9497 #define POWER_RAM_POWERCLR_S12POWER_Off (0x1UL) /*!< Off */
9498 
9499 /* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */
9500 #define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
9501 #define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
9502 #define POWER_RAM_POWERCLR_S11POWER_Off (0x1UL) /*!< Off */
9503 
9504 /* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */
9505 #define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
9506 #define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
9507 #define POWER_RAM_POWERCLR_S10POWER_Off (0x1UL) /*!< Off */
9508 
9509 /* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */
9510 #define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
9511 #define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
9512 #define POWER_RAM_POWERCLR_S9POWER_Off (0x1UL) /*!< Off */
9513 
9514 /* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */
9515 #define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
9516 #define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
9517 #define POWER_RAM_POWERCLR_S8POWER_Off (0x1UL) /*!< Off */
9518 
9519 /* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */
9520 #define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
9521 #define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
9522 #define POWER_RAM_POWERCLR_S7POWER_Off (0x1UL) /*!< Off */
9523 
9524 /* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */
9525 #define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
9526 #define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
9527 #define POWER_RAM_POWERCLR_S6POWER_Off (0x1UL) /*!< Off */
9528 
9529 /* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */
9530 #define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
9531 #define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
9532 #define POWER_RAM_POWERCLR_S5POWER_Off (0x1UL) /*!< Off */
9533 
9534 /* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */
9535 #define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
9536 #define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
9537 #define POWER_RAM_POWERCLR_S4POWER_Off (0x1UL) /*!< Off */
9538 
9539 /* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */
9540 #define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
9541 #define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
9542 #define POWER_RAM_POWERCLR_S3POWER_Off (0x1UL) /*!< Off */
9543 
9544 /* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
9545 #define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
9546 #define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
9547 #define POWER_RAM_POWERCLR_S2POWER_Off (0x1UL) /*!< Off */
9548 
9549 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
9550 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
9551 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
9552 #define POWER_RAM_POWERCLR_S1POWER_Off (0x1UL) /*!< Off */
9553 
9554 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
9555 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
9556 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
9557 #define POWER_RAM_POWERCLR_S0POWER_Off (0x1UL) /*!< Off */
9558 
9559 
9560 /* Peripheral: PPI */
9561 /* Description: Programmable Peripheral Interconnect */
9562 
9563 /* Register: PPI_TASKS_CHG_EN */
9564 /* Description: Description cluster: Enable channel group n */
9565 
9566 /* Bit 0 : Enable channel group n */
9567 #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
9568 #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
9569 #define PPI_TASKS_CHG_EN_EN_Trigger (0x1UL) /*!< Trigger task */
9570 
9571 /* Register: PPI_TASKS_CHG_DIS */
9572 /* Description: Description cluster: Disable channel group n */
9573 
9574 /* Bit 0 : Disable channel group n */
9575 #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
9576 #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
9577 #define PPI_TASKS_CHG_DIS_DIS_Trigger (0x1UL) /*!< Trigger task */
9578 
9579 /* Register: PPI_CHEN */
9580 /* Description: Channel enable register */
9581 
9582 /* Bit 31 : Enable or disable channel 31 */
9583 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
9584 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
9585 #define PPI_CHEN_CH31_Disabled (0x0UL) /*!< Disable channel */
9586 #define PPI_CHEN_CH31_Enabled (0x1UL) /*!< Enable channel */
9587 
9588 /* Bit 30 : Enable or disable channel 30 */
9589 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
9590 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
9591 #define PPI_CHEN_CH30_Disabled (0x0UL) /*!< Disable channel */
9592 #define PPI_CHEN_CH30_Enabled (0x1UL) /*!< Enable channel */
9593 
9594 /* Bit 29 : Enable or disable channel 29 */
9595 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
9596 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
9597 #define PPI_CHEN_CH29_Disabled (0x0UL) /*!< Disable channel */
9598 #define PPI_CHEN_CH29_Enabled (0x1UL) /*!< Enable channel */
9599 
9600 /* Bit 28 : Enable or disable channel 28 */
9601 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
9602 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
9603 #define PPI_CHEN_CH28_Disabled (0x0UL) /*!< Disable channel */
9604 #define PPI_CHEN_CH28_Enabled (0x1UL) /*!< Enable channel */
9605 
9606 /* Bit 27 : Enable or disable channel 27 */
9607 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
9608 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
9609 #define PPI_CHEN_CH27_Disabled (0x0UL) /*!< Disable channel */
9610 #define PPI_CHEN_CH27_Enabled (0x1UL) /*!< Enable channel */
9611 
9612 /* Bit 26 : Enable or disable channel 26 */
9613 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
9614 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
9615 #define PPI_CHEN_CH26_Disabled (0x0UL) /*!< Disable channel */
9616 #define PPI_CHEN_CH26_Enabled (0x1UL) /*!< Enable channel */
9617 
9618 /* Bit 25 : Enable or disable channel 25 */
9619 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
9620 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
9621 #define PPI_CHEN_CH25_Disabled (0x0UL) /*!< Disable channel */
9622 #define PPI_CHEN_CH25_Enabled (0x1UL) /*!< Enable channel */
9623 
9624 /* Bit 24 : Enable or disable channel 24 */
9625 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
9626 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
9627 #define PPI_CHEN_CH24_Disabled (0x0UL) /*!< Disable channel */
9628 #define PPI_CHEN_CH24_Enabled (0x1UL) /*!< Enable channel */
9629 
9630 /* Bit 23 : Enable or disable channel 23 */
9631 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
9632 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
9633 #define PPI_CHEN_CH23_Disabled (0x0UL) /*!< Disable channel */
9634 #define PPI_CHEN_CH23_Enabled (0x1UL) /*!< Enable channel */
9635 
9636 /* Bit 22 : Enable or disable channel 22 */
9637 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
9638 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
9639 #define PPI_CHEN_CH22_Disabled (0x0UL) /*!< Disable channel */
9640 #define PPI_CHEN_CH22_Enabled (0x1UL) /*!< Enable channel */
9641 
9642 /* Bit 21 : Enable or disable channel 21 */
9643 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
9644 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
9645 #define PPI_CHEN_CH21_Disabled (0x0UL) /*!< Disable channel */
9646 #define PPI_CHEN_CH21_Enabled (0x1UL) /*!< Enable channel */
9647 
9648 /* Bit 20 : Enable or disable channel 20 */
9649 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
9650 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
9651 #define PPI_CHEN_CH20_Disabled (0x0UL) /*!< Disable channel */
9652 #define PPI_CHEN_CH20_Enabled (0x1UL) /*!< Enable channel */
9653 
9654 /* Bit 19 : Enable or disable channel 19 */
9655 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
9656 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
9657 #define PPI_CHEN_CH19_Disabled (0x0UL) /*!< Disable channel */
9658 #define PPI_CHEN_CH19_Enabled (0x1UL) /*!< Enable channel */
9659 
9660 /* Bit 18 : Enable or disable channel 18 */
9661 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
9662 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
9663 #define PPI_CHEN_CH18_Disabled (0x0UL) /*!< Disable channel */
9664 #define PPI_CHEN_CH18_Enabled (0x1UL) /*!< Enable channel */
9665 
9666 /* Bit 17 : Enable or disable channel 17 */
9667 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
9668 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
9669 #define PPI_CHEN_CH17_Disabled (0x0UL) /*!< Disable channel */
9670 #define PPI_CHEN_CH17_Enabled (0x1UL) /*!< Enable channel */
9671 
9672 /* Bit 16 : Enable or disable channel 16 */
9673 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
9674 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
9675 #define PPI_CHEN_CH16_Disabled (0x0UL) /*!< Disable channel */
9676 #define PPI_CHEN_CH16_Enabled (0x1UL) /*!< Enable channel */
9677 
9678 /* Bit 15 : Enable or disable channel 15 */
9679 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
9680 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
9681 #define PPI_CHEN_CH15_Disabled (0x0UL) /*!< Disable channel */
9682 #define PPI_CHEN_CH15_Enabled (0x1UL) /*!< Enable channel */
9683 
9684 /* Bit 14 : Enable or disable channel 14 */
9685 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
9686 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
9687 #define PPI_CHEN_CH14_Disabled (0x0UL) /*!< Disable channel */
9688 #define PPI_CHEN_CH14_Enabled (0x1UL) /*!< Enable channel */
9689 
9690 /* Bit 13 : Enable or disable channel 13 */
9691 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
9692 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
9693 #define PPI_CHEN_CH13_Disabled (0x0UL) /*!< Disable channel */
9694 #define PPI_CHEN_CH13_Enabled (0x1UL) /*!< Enable channel */
9695 
9696 /* Bit 12 : Enable or disable channel 12 */
9697 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
9698 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
9699 #define PPI_CHEN_CH12_Disabled (0x0UL) /*!< Disable channel */
9700 #define PPI_CHEN_CH12_Enabled (0x1UL) /*!< Enable channel */
9701 
9702 /* Bit 11 : Enable or disable channel 11 */
9703 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
9704 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
9705 #define PPI_CHEN_CH11_Disabled (0x0UL) /*!< Disable channel */
9706 #define PPI_CHEN_CH11_Enabled (0x1UL) /*!< Enable channel */
9707 
9708 /* Bit 10 : Enable or disable channel 10 */
9709 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
9710 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
9711 #define PPI_CHEN_CH10_Disabled (0x0UL) /*!< Disable channel */
9712 #define PPI_CHEN_CH10_Enabled (0x1UL) /*!< Enable channel */
9713 
9714 /* Bit 9 : Enable or disable channel 9 */
9715 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
9716 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
9717 #define PPI_CHEN_CH9_Disabled (0x0UL) /*!< Disable channel */
9718 #define PPI_CHEN_CH9_Enabled (0x1UL) /*!< Enable channel */
9719 
9720 /* Bit 8 : Enable or disable channel 8 */
9721 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
9722 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
9723 #define PPI_CHEN_CH8_Disabled (0x0UL) /*!< Disable channel */
9724 #define PPI_CHEN_CH8_Enabled (0x1UL) /*!< Enable channel */
9725 
9726 /* Bit 7 : Enable or disable channel 7 */
9727 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
9728 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
9729 #define PPI_CHEN_CH7_Disabled (0x0UL) /*!< Disable channel */
9730 #define PPI_CHEN_CH7_Enabled (0x1UL) /*!< Enable channel */
9731 
9732 /* Bit 6 : Enable or disable channel 6 */
9733 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
9734 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
9735 #define PPI_CHEN_CH6_Disabled (0x0UL) /*!< Disable channel */
9736 #define PPI_CHEN_CH6_Enabled (0x1UL) /*!< Enable channel */
9737 
9738 /* Bit 5 : Enable or disable channel 5 */
9739 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
9740 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
9741 #define PPI_CHEN_CH5_Disabled (0x0UL) /*!< Disable channel */
9742 #define PPI_CHEN_CH5_Enabled (0x1UL) /*!< Enable channel */
9743 
9744 /* Bit 4 : Enable or disable channel 4 */
9745 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
9746 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
9747 #define PPI_CHEN_CH4_Disabled (0x0UL) /*!< Disable channel */
9748 #define PPI_CHEN_CH4_Enabled (0x1UL) /*!< Enable channel */
9749 
9750 /* Bit 3 : Enable or disable channel 3 */
9751 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
9752 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
9753 #define PPI_CHEN_CH3_Disabled (0x0UL) /*!< Disable channel */
9754 #define PPI_CHEN_CH3_Enabled (0x1UL) /*!< Enable channel */
9755 
9756 /* Bit 2 : Enable or disable channel 2 */
9757 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
9758 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
9759 #define PPI_CHEN_CH2_Disabled (0x0UL) /*!< Disable channel */
9760 #define PPI_CHEN_CH2_Enabled (0x1UL) /*!< Enable channel */
9761 
9762 /* Bit 1 : Enable or disable channel 1 */
9763 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
9764 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
9765 #define PPI_CHEN_CH1_Disabled (0x0UL) /*!< Disable channel */
9766 #define PPI_CHEN_CH1_Enabled (0x1UL) /*!< Enable channel */
9767 
9768 /* Bit 0 : Enable or disable channel 0 */
9769 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
9770 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
9771 #define PPI_CHEN_CH0_Disabled (0x0UL) /*!< Disable channel */
9772 #define PPI_CHEN_CH0_Enabled (0x1UL) /*!< Enable channel */
9773 
9774 /* Register: PPI_CHENSET */
9775 /* Description: Channel enable set register */
9776 
9777 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect. */
9778 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
9779 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
9780 #define PPI_CHENSET_CH31_Disabled (0x0UL) /*!< Read: channel disabled */
9781 #define PPI_CHENSET_CH31_Enabled (0x1UL) /*!< Read: channel enabled */
9782 #define PPI_CHENSET_CH31_Set (0x1UL) /*!< Write: Enable channel */
9783 
9784 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect. */
9785 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
9786 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
9787 #define PPI_CHENSET_CH30_Disabled (0x0UL) /*!< Read: channel disabled */
9788 #define PPI_CHENSET_CH30_Enabled (0x1UL) /*!< Read: channel enabled */
9789 #define PPI_CHENSET_CH30_Set (0x1UL) /*!< Write: Enable channel */
9790 
9791 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect. */
9792 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
9793 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
9794 #define PPI_CHENSET_CH29_Disabled (0x0UL) /*!< Read: channel disabled */
9795 #define PPI_CHENSET_CH29_Enabled (0x1UL) /*!< Read: channel enabled */
9796 #define PPI_CHENSET_CH29_Set (0x1UL) /*!< Write: Enable channel */
9797 
9798 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect. */
9799 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
9800 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
9801 #define PPI_CHENSET_CH28_Disabled (0x0UL) /*!< Read: channel disabled */
9802 #define PPI_CHENSET_CH28_Enabled (0x1UL) /*!< Read: channel enabled */
9803 #define PPI_CHENSET_CH28_Set (0x1UL) /*!< Write: Enable channel */
9804 
9805 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect. */
9806 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
9807 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
9808 #define PPI_CHENSET_CH27_Disabled (0x0UL) /*!< Read: channel disabled */
9809 #define PPI_CHENSET_CH27_Enabled (0x1UL) /*!< Read: channel enabled */
9810 #define PPI_CHENSET_CH27_Set (0x1UL) /*!< Write: Enable channel */
9811 
9812 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect. */
9813 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
9814 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
9815 #define PPI_CHENSET_CH26_Disabled (0x0UL) /*!< Read: channel disabled */
9816 #define PPI_CHENSET_CH26_Enabled (0x1UL) /*!< Read: channel enabled */
9817 #define PPI_CHENSET_CH26_Set (0x1UL) /*!< Write: Enable channel */
9818 
9819 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect. */
9820 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
9821 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
9822 #define PPI_CHENSET_CH25_Disabled (0x0UL) /*!< Read: channel disabled */
9823 #define PPI_CHENSET_CH25_Enabled (0x1UL) /*!< Read: channel enabled */
9824 #define PPI_CHENSET_CH25_Set (0x1UL) /*!< Write: Enable channel */
9825 
9826 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect. */
9827 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
9828 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
9829 #define PPI_CHENSET_CH24_Disabled (0x0UL) /*!< Read: channel disabled */
9830 #define PPI_CHENSET_CH24_Enabled (0x1UL) /*!< Read: channel enabled */
9831 #define PPI_CHENSET_CH24_Set (0x1UL) /*!< Write: Enable channel */
9832 
9833 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect. */
9834 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
9835 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
9836 #define PPI_CHENSET_CH23_Disabled (0x0UL) /*!< Read: channel disabled */
9837 #define PPI_CHENSET_CH23_Enabled (0x1UL) /*!< Read: channel enabled */
9838 #define PPI_CHENSET_CH23_Set (0x1UL) /*!< Write: Enable channel */
9839 
9840 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect. */
9841 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
9842 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
9843 #define PPI_CHENSET_CH22_Disabled (0x0UL) /*!< Read: channel disabled */
9844 #define PPI_CHENSET_CH22_Enabled (0x1UL) /*!< Read: channel enabled */
9845 #define PPI_CHENSET_CH22_Set (0x1UL) /*!< Write: Enable channel */
9846 
9847 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect. */
9848 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
9849 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
9850 #define PPI_CHENSET_CH21_Disabled (0x0UL) /*!< Read: channel disabled */
9851 #define PPI_CHENSET_CH21_Enabled (0x1UL) /*!< Read: channel enabled */
9852 #define PPI_CHENSET_CH21_Set (0x1UL) /*!< Write: Enable channel */
9853 
9854 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect. */
9855 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
9856 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
9857 #define PPI_CHENSET_CH20_Disabled (0x0UL) /*!< Read: channel disabled */
9858 #define PPI_CHENSET_CH20_Enabled (0x1UL) /*!< Read: channel enabled */
9859 #define PPI_CHENSET_CH20_Set (0x1UL) /*!< Write: Enable channel */
9860 
9861 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect. */
9862 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
9863 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
9864 #define PPI_CHENSET_CH19_Disabled (0x0UL) /*!< Read: channel disabled */
9865 #define PPI_CHENSET_CH19_Enabled (0x1UL) /*!< Read: channel enabled */
9866 #define PPI_CHENSET_CH19_Set (0x1UL) /*!< Write: Enable channel */
9867 
9868 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect. */
9869 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
9870 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
9871 #define PPI_CHENSET_CH18_Disabled (0x0UL) /*!< Read: channel disabled */
9872 #define PPI_CHENSET_CH18_Enabled (0x1UL) /*!< Read: channel enabled */
9873 #define PPI_CHENSET_CH18_Set (0x1UL) /*!< Write: Enable channel */
9874 
9875 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect. */
9876 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
9877 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
9878 #define PPI_CHENSET_CH17_Disabled (0x0UL) /*!< Read: channel disabled */
9879 #define PPI_CHENSET_CH17_Enabled (0x1UL) /*!< Read: channel enabled */
9880 #define PPI_CHENSET_CH17_Set (0x1UL) /*!< Write: Enable channel */
9881 
9882 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect. */
9883 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
9884 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
9885 #define PPI_CHENSET_CH16_Disabled (0x0UL) /*!< Read: channel disabled */
9886 #define PPI_CHENSET_CH16_Enabled (0x1UL) /*!< Read: channel enabled */
9887 #define PPI_CHENSET_CH16_Set (0x1UL) /*!< Write: Enable channel */
9888 
9889 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect. */
9890 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
9891 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
9892 #define PPI_CHENSET_CH15_Disabled (0x0UL) /*!< Read: channel disabled */
9893 #define PPI_CHENSET_CH15_Enabled (0x1UL) /*!< Read: channel enabled */
9894 #define PPI_CHENSET_CH15_Set (0x1UL) /*!< Write: Enable channel */
9895 
9896 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect. */
9897 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
9898 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
9899 #define PPI_CHENSET_CH14_Disabled (0x0UL) /*!< Read: channel disabled */
9900 #define PPI_CHENSET_CH14_Enabled (0x1UL) /*!< Read: channel enabled */
9901 #define PPI_CHENSET_CH14_Set (0x1UL) /*!< Write: Enable channel */
9902 
9903 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect. */
9904 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
9905 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
9906 #define PPI_CHENSET_CH13_Disabled (0x0UL) /*!< Read: channel disabled */
9907 #define PPI_CHENSET_CH13_Enabled (0x1UL) /*!< Read: channel enabled */
9908 #define PPI_CHENSET_CH13_Set (0x1UL) /*!< Write: Enable channel */
9909 
9910 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect. */
9911 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
9912 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
9913 #define PPI_CHENSET_CH12_Disabled (0x0UL) /*!< Read: channel disabled */
9914 #define PPI_CHENSET_CH12_Enabled (0x1UL) /*!< Read: channel enabled */
9915 #define PPI_CHENSET_CH12_Set (0x1UL) /*!< Write: Enable channel */
9916 
9917 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect. */
9918 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
9919 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
9920 #define PPI_CHENSET_CH11_Disabled (0x0UL) /*!< Read: channel disabled */
9921 #define PPI_CHENSET_CH11_Enabled (0x1UL) /*!< Read: channel enabled */
9922 #define PPI_CHENSET_CH11_Set (0x1UL) /*!< Write: Enable channel */
9923 
9924 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect. */
9925 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
9926 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
9927 #define PPI_CHENSET_CH10_Disabled (0x0UL) /*!< Read: channel disabled */
9928 #define PPI_CHENSET_CH10_Enabled (0x1UL) /*!< Read: channel enabled */
9929 #define PPI_CHENSET_CH10_Set (0x1UL) /*!< Write: Enable channel */
9930 
9931 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect. */
9932 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
9933 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
9934 #define PPI_CHENSET_CH9_Disabled (0x0UL) /*!< Read: channel disabled */
9935 #define PPI_CHENSET_CH9_Enabled (0x1UL) /*!< Read: channel enabled */
9936 #define PPI_CHENSET_CH9_Set (0x1UL) /*!< Write: Enable channel */
9937 
9938 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect. */
9939 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
9940 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
9941 #define PPI_CHENSET_CH8_Disabled (0x0UL) /*!< Read: channel disabled */
9942 #define PPI_CHENSET_CH8_Enabled (0x1UL) /*!< Read: channel enabled */
9943 #define PPI_CHENSET_CH8_Set (0x1UL) /*!< Write: Enable channel */
9944 
9945 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect. */
9946 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
9947 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
9948 #define PPI_CHENSET_CH7_Disabled (0x0UL) /*!< Read: channel disabled */
9949 #define PPI_CHENSET_CH7_Enabled (0x1UL) /*!< Read: channel enabled */
9950 #define PPI_CHENSET_CH7_Set (0x1UL) /*!< Write: Enable channel */
9951 
9952 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect. */
9953 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
9954 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
9955 #define PPI_CHENSET_CH6_Disabled (0x0UL) /*!< Read: channel disabled */
9956 #define PPI_CHENSET_CH6_Enabled (0x1UL) /*!< Read: channel enabled */
9957 #define PPI_CHENSET_CH6_Set (0x1UL) /*!< Write: Enable channel */
9958 
9959 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect. */
9960 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
9961 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
9962 #define PPI_CHENSET_CH5_Disabled (0x0UL) /*!< Read: channel disabled */
9963 #define PPI_CHENSET_CH5_Enabled (0x1UL) /*!< Read: channel enabled */
9964 #define PPI_CHENSET_CH5_Set (0x1UL) /*!< Write: Enable channel */
9965 
9966 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect. */
9967 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
9968 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
9969 #define PPI_CHENSET_CH4_Disabled (0x0UL) /*!< Read: channel disabled */
9970 #define PPI_CHENSET_CH4_Enabled (0x1UL) /*!< Read: channel enabled */
9971 #define PPI_CHENSET_CH4_Set (0x1UL) /*!< Write: Enable channel */
9972 
9973 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect. */
9974 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
9975 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
9976 #define PPI_CHENSET_CH3_Disabled (0x0UL) /*!< Read: channel disabled */
9977 #define PPI_CHENSET_CH3_Enabled (0x1UL) /*!< Read: channel enabled */
9978 #define PPI_CHENSET_CH3_Set (0x1UL) /*!< Write: Enable channel */
9979 
9980 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect. */
9981 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
9982 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
9983 #define PPI_CHENSET_CH2_Disabled (0x0UL) /*!< Read: channel disabled */
9984 #define PPI_CHENSET_CH2_Enabled (0x1UL) /*!< Read: channel enabled */
9985 #define PPI_CHENSET_CH2_Set (0x1UL) /*!< Write: Enable channel */
9986 
9987 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect. */
9988 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
9989 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
9990 #define PPI_CHENSET_CH1_Disabled (0x0UL) /*!< Read: channel disabled */
9991 #define PPI_CHENSET_CH1_Enabled (0x1UL) /*!< Read: channel enabled */
9992 #define PPI_CHENSET_CH1_Set (0x1UL) /*!< Write: Enable channel */
9993 
9994 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect. */
9995 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
9996 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
9997 #define PPI_CHENSET_CH0_Disabled (0x0UL) /*!< Read: channel disabled */
9998 #define PPI_CHENSET_CH0_Enabled (0x1UL) /*!< Read: channel enabled */
9999 #define PPI_CHENSET_CH0_Set (0x1UL) /*!< Write: Enable channel */
10000 
10001 /* Register: PPI_CHENCLR */
10002 /* Description: Channel enable clear register */
10003 
10004 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect. */
10005 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
10006 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
10007 #define PPI_CHENCLR_CH31_Disabled (0x0UL) /*!< Read: channel disabled */
10008 #define PPI_CHENCLR_CH31_Enabled (0x1UL) /*!< Read: channel enabled */
10009 #define PPI_CHENCLR_CH31_Clear (0x1UL) /*!< Write: disable channel */
10010 
10011 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect. */
10012 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
10013 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
10014 #define PPI_CHENCLR_CH30_Disabled (0x0UL) /*!< Read: channel disabled */
10015 #define PPI_CHENCLR_CH30_Enabled (0x1UL) /*!< Read: channel enabled */
10016 #define PPI_CHENCLR_CH30_Clear (0x1UL) /*!< Write: disable channel */
10017 
10018 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect. */
10019 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
10020 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
10021 #define PPI_CHENCLR_CH29_Disabled (0x0UL) /*!< Read: channel disabled */
10022 #define PPI_CHENCLR_CH29_Enabled (0x1UL) /*!< Read: channel enabled */
10023 #define PPI_CHENCLR_CH29_Clear (0x1UL) /*!< Write: disable channel */
10024 
10025 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect. */
10026 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
10027 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
10028 #define PPI_CHENCLR_CH28_Disabled (0x0UL) /*!< Read: channel disabled */
10029 #define PPI_CHENCLR_CH28_Enabled (0x1UL) /*!< Read: channel enabled */
10030 #define PPI_CHENCLR_CH28_Clear (0x1UL) /*!< Write: disable channel */
10031 
10032 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect. */
10033 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
10034 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
10035 #define PPI_CHENCLR_CH27_Disabled (0x0UL) /*!< Read: channel disabled */
10036 #define PPI_CHENCLR_CH27_Enabled (0x1UL) /*!< Read: channel enabled */
10037 #define PPI_CHENCLR_CH27_Clear (0x1UL) /*!< Write: disable channel */
10038 
10039 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect. */
10040 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
10041 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
10042 #define PPI_CHENCLR_CH26_Disabled (0x0UL) /*!< Read: channel disabled */
10043 #define PPI_CHENCLR_CH26_Enabled (0x1UL) /*!< Read: channel enabled */
10044 #define PPI_CHENCLR_CH26_Clear (0x1UL) /*!< Write: disable channel */
10045 
10046 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect. */
10047 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
10048 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
10049 #define PPI_CHENCLR_CH25_Disabled (0x0UL) /*!< Read: channel disabled */
10050 #define PPI_CHENCLR_CH25_Enabled (0x1UL) /*!< Read: channel enabled */
10051 #define PPI_CHENCLR_CH25_Clear (0x1UL) /*!< Write: disable channel */
10052 
10053 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect. */
10054 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
10055 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
10056 #define PPI_CHENCLR_CH24_Disabled (0x0UL) /*!< Read: channel disabled */
10057 #define PPI_CHENCLR_CH24_Enabled (0x1UL) /*!< Read: channel enabled */
10058 #define PPI_CHENCLR_CH24_Clear (0x1UL) /*!< Write: disable channel */
10059 
10060 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect. */
10061 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
10062 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
10063 #define PPI_CHENCLR_CH23_Disabled (0x0UL) /*!< Read: channel disabled */
10064 #define PPI_CHENCLR_CH23_Enabled (0x1UL) /*!< Read: channel enabled */
10065 #define PPI_CHENCLR_CH23_Clear (0x1UL) /*!< Write: disable channel */
10066 
10067 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect. */
10068 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
10069 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
10070 #define PPI_CHENCLR_CH22_Disabled (0x0UL) /*!< Read: channel disabled */
10071 #define PPI_CHENCLR_CH22_Enabled (0x1UL) /*!< Read: channel enabled */
10072 #define PPI_CHENCLR_CH22_Clear (0x1UL) /*!< Write: disable channel */
10073 
10074 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect. */
10075 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
10076 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
10077 #define PPI_CHENCLR_CH21_Disabled (0x0UL) /*!< Read: channel disabled */
10078 #define PPI_CHENCLR_CH21_Enabled (0x1UL) /*!< Read: channel enabled */
10079 #define PPI_CHENCLR_CH21_Clear (0x1UL) /*!< Write: disable channel */
10080 
10081 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect. */
10082 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
10083 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
10084 #define PPI_CHENCLR_CH20_Disabled (0x0UL) /*!< Read: channel disabled */
10085 #define PPI_CHENCLR_CH20_Enabled (0x1UL) /*!< Read: channel enabled */
10086 #define PPI_CHENCLR_CH20_Clear (0x1UL) /*!< Write: disable channel */
10087 
10088 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect. */
10089 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
10090 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
10091 #define PPI_CHENCLR_CH19_Disabled (0x0UL) /*!< Read: channel disabled */
10092 #define PPI_CHENCLR_CH19_Enabled (0x1UL) /*!< Read: channel enabled */
10093 #define PPI_CHENCLR_CH19_Clear (0x1UL) /*!< Write: disable channel */
10094 
10095 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect. */
10096 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
10097 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
10098 #define PPI_CHENCLR_CH18_Disabled (0x0UL) /*!< Read: channel disabled */
10099 #define PPI_CHENCLR_CH18_Enabled (0x1UL) /*!< Read: channel enabled */
10100 #define PPI_CHENCLR_CH18_Clear (0x1UL) /*!< Write: disable channel */
10101 
10102 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect. */
10103 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
10104 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
10105 #define PPI_CHENCLR_CH17_Disabled (0x0UL) /*!< Read: channel disabled */
10106 #define PPI_CHENCLR_CH17_Enabled (0x1UL) /*!< Read: channel enabled */
10107 #define PPI_CHENCLR_CH17_Clear (0x1UL) /*!< Write: disable channel */
10108 
10109 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect. */
10110 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
10111 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
10112 #define PPI_CHENCLR_CH16_Disabled (0x0UL) /*!< Read: channel disabled */
10113 #define PPI_CHENCLR_CH16_Enabled (0x1UL) /*!< Read: channel enabled */
10114 #define PPI_CHENCLR_CH16_Clear (0x1UL) /*!< Write: disable channel */
10115 
10116 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect. */
10117 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
10118 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
10119 #define PPI_CHENCLR_CH15_Disabled (0x0UL) /*!< Read: channel disabled */
10120 #define PPI_CHENCLR_CH15_Enabled (0x1UL) /*!< Read: channel enabled */
10121 #define PPI_CHENCLR_CH15_Clear (0x1UL) /*!< Write: disable channel */
10122 
10123 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect. */
10124 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
10125 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
10126 #define PPI_CHENCLR_CH14_Disabled (0x0UL) /*!< Read: channel disabled */
10127 #define PPI_CHENCLR_CH14_Enabled (0x1UL) /*!< Read: channel enabled */
10128 #define PPI_CHENCLR_CH14_Clear (0x1UL) /*!< Write: disable channel */
10129 
10130 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect. */
10131 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
10132 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
10133 #define PPI_CHENCLR_CH13_Disabled (0x0UL) /*!< Read: channel disabled */
10134 #define PPI_CHENCLR_CH13_Enabled (0x1UL) /*!< Read: channel enabled */
10135 #define PPI_CHENCLR_CH13_Clear (0x1UL) /*!< Write: disable channel */
10136 
10137 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect. */
10138 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
10139 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
10140 #define PPI_CHENCLR_CH12_Disabled (0x0UL) /*!< Read: channel disabled */
10141 #define PPI_CHENCLR_CH12_Enabled (0x1UL) /*!< Read: channel enabled */
10142 #define PPI_CHENCLR_CH12_Clear (0x1UL) /*!< Write: disable channel */
10143 
10144 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect. */
10145 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
10146 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
10147 #define PPI_CHENCLR_CH11_Disabled (0x0UL) /*!< Read: channel disabled */
10148 #define PPI_CHENCLR_CH11_Enabled (0x1UL) /*!< Read: channel enabled */
10149 #define PPI_CHENCLR_CH11_Clear (0x1UL) /*!< Write: disable channel */
10150 
10151 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect. */
10152 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
10153 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
10154 #define PPI_CHENCLR_CH10_Disabled (0x0UL) /*!< Read: channel disabled */
10155 #define PPI_CHENCLR_CH10_Enabled (0x1UL) /*!< Read: channel enabled */
10156 #define PPI_CHENCLR_CH10_Clear (0x1UL) /*!< Write: disable channel */
10157 
10158 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect. */
10159 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
10160 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
10161 #define PPI_CHENCLR_CH9_Disabled (0x0UL) /*!< Read: channel disabled */
10162 #define PPI_CHENCLR_CH9_Enabled (0x1UL) /*!< Read: channel enabled */
10163 #define PPI_CHENCLR_CH9_Clear (0x1UL) /*!< Write: disable channel */
10164 
10165 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect. */
10166 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
10167 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
10168 #define PPI_CHENCLR_CH8_Disabled (0x0UL) /*!< Read: channel disabled */
10169 #define PPI_CHENCLR_CH8_Enabled (0x1UL) /*!< Read: channel enabled */
10170 #define PPI_CHENCLR_CH8_Clear (0x1UL) /*!< Write: disable channel */
10171 
10172 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect. */
10173 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
10174 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
10175 #define PPI_CHENCLR_CH7_Disabled (0x0UL) /*!< Read: channel disabled */
10176 #define PPI_CHENCLR_CH7_Enabled (0x1UL) /*!< Read: channel enabled */
10177 #define PPI_CHENCLR_CH7_Clear (0x1UL) /*!< Write: disable channel */
10178 
10179 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect. */
10180 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
10181 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
10182 #define PPI_CHENCLR_CH6_Disabled (0x0UL) /*!< Read: channel disabled */
10183 #define PPI_CHENCLR_CH6_Enabled (0x1UL) /*!< Read: channel enabled */
10184 #define PPI_CHENCLR_CH6_Clear (0x1UL) /*!< Write: disable channel */
10185 
10186 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect. */
10187 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
10188 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
10189 #define PPI_CHENCLR_CH5_Disabled (0x0UL) /*!< Read: channel disabled */
10190 #define PPI_CHENCLR_CH5_Enabled (0x1UL) /*!< Read: channel enabled */
10191 #define PPI_CHENCLR_CH5_Clear (0x1UL) /*!< Write: disable channel */
10192 
10193 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect. */
10194 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
10195 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
10196 #define PPI_CHENCLR_CH4_Disabled (0x0UL) /*!< Read: channel disabled */
10197 #define PPI_CHENCLR_CH4_Enabled (0x1UL) /*!< Read: channel enabled */
10198 #define PPI_CHENCLR_CH4_Clear (0x1UL) /*!< Write: disable channel */
10199 
10200 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect. */
10201 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
10202 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
10203 #define PPI_CHENCLR_CH3_Disabled (0x0UL) /*!< Read: channel disabled */
10204 #define PPI_CHENCLR_CH3_Enabled (0x1UL) /*!< Read: channel enabled */
10205 #define PPI_CHENCLR_CH3_Clear (0x1UL) /*!< Write: disable channel */
10206 
10207 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect. */
10208 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
10209 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
10210 #define PPI_CHENCLR_CH2_Disabled (0x0UL) /*!< Read: channel disabled */
10211 #define PPI_CHENCLR_CH2_Enabled (0x1UL) /*!< Read: channel enabled */
10212 #define PPI_CHENCLR_CH2_Clear (0x1UL) /*!< Write: disable channel */
10213 
10214 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect. */
10215 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
10216 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
10217 #define PPI_CHENCLR_CH1_Disabled (0x0UL) /*!< Read: channel disabled */
10218 #define PPI_CHENCLR_CH1_Enabled (0x1UL) /*!< Read: channel enabled */
10219 #define PPI_CHENCLR_CH1_Clear (0x1UL) /*!< Write: disable channel */
10220 
10221 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect. */
10222 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
10223 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
10224 #define PPI_CHENCLR_CH0_Disabled (0x0UL) /*!< Read: channel disabled */
10225 #define PPI_CHENCLR_CH0_Enabled (0x1UL) /*!< Read: channel enabled */
10226 #define PPI_CHENCLR_CH0_Clear (0x1UL) /*!< Write: disable channel */
10227 
10228 /* Register: PPI_CH_EEP */
10229 /* Description: Description cluster: Channel n event endpoint */
10230 
10231 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
10232 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
10233 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
10234 
10235 /* Register: PPI_CH_TEP */
10236 /* Description: Description cluster: Channel n task endpoint */
10237 
10238 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
10239 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
10240 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
10241 
10242 /* Register: PPI_CHG */
10243 /* Description: Description collection: Channel group n */
10244 
10245 /* Bit 31 : Include or exclude channel 31 */
10246 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
10247 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
10248 #define PPI_CHG_CH31_Excluded (0x0UL) /*!< Exclude */
10249 #define PPI_CHG_CH31_Included (0x1UL) /*!< Include */
10250 
10251 /* Bit 30 : Include or exclude channel 30 */
10252 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
10253 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
10254 #define PPI_CHG_CH30_Excluded (0x0UL) /*!< Exclude */
10255 #define PPI_CHG_CH30_Included (0x1UL) /*!< Include */
10256 
10257 /* Bit 29 : Include or exclude channel 29 */
10258 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
10259 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
10260 #define PPI_CHG_CH29_Excluded (0x0UL) /*!< Exclude */
10261 #define PPI_CHG_CH29_Included (0x1UL) /*!< Include */
10262 
10263 /* Bit 28 : Include or exclude channel 28 */
10264 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
10265 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
10266 #define PPI_CHG_CH28_Excluded (0x0UL) /*!< Exclude */
10267 #define PPI_CHG_CH28_Included (0x1UL) /*!< Include */
10268 
10269 /* Bit 27 : Include or exclude channel 27 */
10270 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
10271 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
10272 #define PPI_CHG_CH27_Excluded (0x0UL) /*!< Exclude */
10273 #define PPI_CHG_CH27_Included (0x1UL) /*!< Include */
10274 
10275 /* Bit 26 : Include or exclude channel 26 */
10276 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
10277 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
10278 #define PPI_CHG_CH26_Excluded (0x0UL) /*!< Exclude */
10279 #define PPI_CHG_CH26_Included (0x1UL) /*!< Include */
10280 
10281 /* Bit 25 : Include or exclude channel 25 */
10282 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
10283 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
10284 #define PPI_CHG_CH25_Excluded (0x0UL) /*!< Exclude */
10285 #define PPI_CHG_CH25_Included (0x1UL) /*!< Include */
10286 
10287 /* Bit 24 : Include or exclude channel 24 */
10288 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
10289 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
10290 #define PPI_CHG_CH24_Excluded (0x0UL) /*!< Exclude */
10291 #define PPI_CHG_CH24_Included (0x1UL) /*!< Include */
10292 
10293 /* Bit 23 : Include or exclude channel 23 */
10294 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
10295 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
10296 #define PPI_CHG_CH23_Excluded (0x0UL) /*!< Exclude */
10297 #define PPI_CHG_CH23_Included (0x1UL) /*!< Include */
10298 
10299 /* Bit 22 : Include or exclude channel 22 */
10300 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
10301 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
10302 #define PPI_CHG_CH22_Excluded (0x0UL) /*!< Exclude */
10303 #define PPI_CHG_CH22_Included (0x1UL) /*!< Include */
10304 
10305 /* Bit 21 : Include or exclude channel 21 */
10306 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
10307 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
10308 #define PPI_CHG_CH21_Excluded (0x0UL) /*!< Exclude */
10309 #define PPI_CHG_CH21_Included (0x1UL) /*!< Include */
10310 
10311 /* Bit 20 : Include or exclude channel 20 */
10312 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
10313 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
10314 #define PPI_CHG_CH20_Excluded (0x0UL) /*!< Exclude */
10315 #define PPI_CHG_CH20_Included (0x1UL) /*!< Include */
10316 
10317 /* Bit 19 : Include or exclude channel 19 */
10318 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
10319 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
10320 #define PPI_CHG_CH19_Excluded (0x0UL) /*!< Exclude */
10321 #define PPI_CHG_CH19_Included (0x1UL) /*!< Include */
10322 
10323 /* Bit 18 : Include or exclude channel 18 */
10324 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
10325 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
10326 #define PPI_CHG_CH18_Excluded (0x0UL) /*!< Exclude */
10327 #define PPI_CHG_CH18_Included (0x1UL) /*!< Include */
10328 
10329 /* Bit 17 : Include or exclude channel 17 */
10330 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
10331 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
10332 #define PPI_CHG_CH17_Excluded (0x0UL) /*!< Exclude */
10333 #define PPI_CHG_CH17_Included (0x1UL) /*!< Include */
10334 
10335 /* Bit 16 : Include or exclude channel 16 */
10336 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
10337 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
10338 #define PPI_CHG_CH16_Excluded (0x0UL) /*!< Exclude */
10339 #define PPI_CHG_CH16_Included (0x1UL) /*!< Include */
10340 
10341 /* Bit 15 : Include or exclude channel 15 */
10342 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
10343 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
10344 #define PPI_CHG_CH15_Excluded (0x0UL) /*!< Exclude */
10345 #define PPI_CHG_CH15_Included (0x1UL) /*!< Include */
10346 
10347 /* Bit 14 : Include or exclude channel 14 */
10348 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
10349 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
10350 #define PPI_CHG_CH14_Excluded (0x0UL) /*!< Exclude */
10351 #define PPI_CHG_CH14_Included (0x1UL) /*!< Include */
10352 
10353 /* Bit 13 : Include or exclude channel 13 */
10354 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
10355 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
10356 #define PPI_CHG_CH13_Excluded (0x0UL) /*!< Exclude */
10357 #define PPI_CHG_CH13_Included (0x1UL) /*!< Include */
10358 
10359 /* Bit 12 : Include or exclude channel 12 */
10360 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
10361 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
10362 #define PPI_CHG_CH12_Excluded (0x0UL) /*!< Exclude */
10363 #define PPI_CHG_CH12_Included (0x1UL) /*!< Include */
10364 
10365 /* Bit 11 : Include or exclude channel 11 */
10366 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
10367 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
10368 #define PPI_CHG_CH11_Excluded (0x0UL) /*!< Exclude */
10369 #define PPI_CHG_CH11_Included (0x1UL) /*!< Include */
10370 
10371 /* Bit 10 : Include or exclude channel 10 */
10372 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
10373 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
10374 #define PPI_CHG_CH10_Excluded (0x0UL) /*!< Exclude */
10375 #define PPI_CHG_CH10_Included (0x1UL) /*!< Include */
10376 
10377 /* Bit 9 : Include or exclude channel 9 */
10378 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
10379 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
10380 #define PPI_CHG_CH9_Excluded (0x0UL) /*!< Exclude */
10381 #define PPI_CHG_CH9_Included (0x1UL) /*!< Include */
10382 
10383 /* Bit 8 : Include or exclude channel 8 */
10384 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
10385 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
10386 #define PPI_CHG_CH8_Excluded (0x0UL) /*!< Exclude */
10387 #define PPI_CHG_CH8_Included (0x1UL) /*!< Include */
10388 
10389 /* Bit 7 : Include or exclude channel 7 */
10390 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
10391 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
10392 #define PPI_CHG_CH7_Excluded (0x0UL) /*!< Exclude */
10393 #define PPI_CHG_CH7_Included (0x1UL) /*!< Include */
10394 
10395 /* Bit 6 : Include or exclude channel 6 */
10396 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
10397 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
10398 #define PPI_CHG_CH6_Excluded (0x0UL) /*!< Exclude */
10399 #define PPI_CHG_CH6_Included (0x1UL) /*!< Include */
10400 
10401 /* Bit 5 : Include or exclude channel 5 */
10402 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
10403 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
10404 #define PPI_CHG_CH5_Excluded (0x0UL) /*!< Exclude */
10405 #define PPI_CHG_CH5_Included (0x1UL) /*!< Include */
10406 
10407 /* Bit 4 : Include or exclude channel 4 */
10408 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
10409 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
10410 #define PPI_CHG_CH4_Excluded (0x0UL) /*!< Exclude */
10411 #define PPI_CHG_CH4_Included (0x1UL) /*!< Include */
10412 
10413 /* Bit 3 : Include or exclude channel 3 */
10414 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
10415 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
10416 #define PPI_CHG_CH3_Excluded (0x0UL) /*!< Exclude */
10417 #define PPI_CHG_CH3_Included (0x1UL) /*!< Include */
10418 
10419 /* Bit 2 : Include or exclude channel 2 */
10420 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
10421 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
10422 #define PPI_CHG_CH2_Excluded (0x0UL) /*!< Exclude */
10423 #define PPI_CHG_CH2_Included (0x1UL) /*!< Include */
10424 
10425 /* Bit 1 : Include or exclude channel 1 */
10426 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
10427 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
10428 #define PPI_CHG_CH1_Excluded (0x0UL) /*!< Exclude */
10429 #define PPI_CHG_CH1_Included (0x1UL) /*!< Include */
10430 
10431 /* Bit 0 : Include or exclude channel 0 */
10432 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
10433 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
10434 #define PPI_CHG_CH0_Excluded (0x0UL) /*!< Exclude */
10435 #define PPI_CHG_CH0_Included (0x1UL) /*!< Include */
10436 
10437 /* Register: PPI_FORK_TEP */
10438 /* Description: Description cluster: Channel n task endpoint */
10439 
10440 /* Bits 31..0 : Pointer to task register */
10441 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
10442 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
10443 
10444 
10445 /* Peripheral: PWM */
10446 /* Description: Pulse width modulation unit 0 */
10447 
10448 /* Register: PWM_TASKS_STOP */
10449 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
10450 
10451 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
10452 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10453 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10454 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
10455 
10456 /* Register: PWM_TASKS_SEQSTART */
10457 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
10458 
10459 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
10460 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
10461 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
10462 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (0x1UL) /*!< Trigger task */
10463 
10464 /* Register: PWM_TASKS_NEXTSTEP */
10465 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
10466 
10467 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
10468 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
10469 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
10470 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (0x1UL) /*!< Trigger task */
10471 
10472 /* Register: PWM_EVENTS_STOPPED */
10473 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
10474 
10475 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
10476 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
10477 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
10478 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
10479 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
10480 
10481 /* Register: PWM_EVENTS_SEQSTARTED */
10482 /* Description: Description collection: First PWM period started on sequence n */
10483 
10484 /* Bit 0 : First PWM period started on sequence n */
10485 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
10486 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
10487 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
10488 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (0x1UL) /*!< Event generated */
10489 
10490 /* Register: PWM_EVENTS_SEQEND */
10491 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
10492 
10493 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
10494 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
10495 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
10496 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0x0UL) /*!< Event not generated */
10497 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (0x1UL) /*!< Event generated */
10498 
10499 /* Register: PWM_EVENTS_PWMPERIODEND */
10500 /* Description: Emitted at the end of each PWM period */
10501 
10502 /* Bit 0 : Emitted at the end of each PWM period */
10503 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
10504 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
10505 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated */
10506 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated */
10507 
10508 /* Register: PWM_EVENTS_LOOPSDONE */
10509 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
10510 
10511 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
10512 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
10513 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
10514 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0x0UL) /*!< Event not generated */
10515 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (0x1UL) /*!< Event generated */
10516 
10517 /* Register: PWM_SHORTS */
10518 /* Description: Shortcuts between local events and tasks */
10519 
10520 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
10521 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
10522 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
10523 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0x0UL) /*!< Disable shortcut */
10524 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (0x1UL) /*!< Enable shortcut */
10525 
10526 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
10527 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
10528 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
10529 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0x0UL) /*!< Disable shortcut */
10530 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (0x1UL) /*!< Enable shortcut */
10531 
10532 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
10533 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
10534 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
10535 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0x0UL) /*!< Disable shortcut */
10536 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (0x1UL) /*!< Enable shortcut */
10537 
10538 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
10539 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
10540 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
10541 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL) /*!< Disable shortcut */
10542 #define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL) /*!< Enable shortcut */
10543 
10544 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
10545 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
10546 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
10547 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0x0UL) /*!< Disable shortcut */
10548 #define PWM_SHORTS_SEQEND0_STOP_Enabled (0x1UL) /*!< Enable shortcut */
10549 
10550 /* Register: PWM_INTEN */
10551 /* Description: Enable or disable interrupt */
10552 
10553 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
10554 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
10555 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
10556 #define PWM_INTEN_LOOPSDONE_Disabled (0x0UL) /*!< Disable */
10557 #define PWM_INTEN_LOOPSDONE_Enabled (0x1UL) /*!< Enable */
10558 
10559 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
10560 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
10561 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
10562 #define PWM_INTEN_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */
10563 #define PWM_INTEN_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */
10564 
10565 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
10566 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
10567 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
10568 #define PWM_INTEN_SEQEND1_Disabled (0x0UL) /*!< Disable */
10569 #define PWM_INTEN_SEQEND1_Enabled (0x1UL) /*!< Enable */
10570 
10571 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
10572 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
10573 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
10574 #define PWM_INTEN_SEQEND0_Disabled (0x0UL) /*!< Disable */
10575 #define PWM_INTEN_SEQEND0_Enabled (0x1UL) /*!< Enable */
10576 
10577 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
10578 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
10579 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
10580 #define PWM_INTEN_SEQSTARTED1_Disabled (0x0UL) /*!< Disable */
10581 #define PWM_INTEN_SEQSTARTED1_Enabled (0x1UL) /*!< Enable */
10582 
10583 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
10584 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
10585 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
10586 #define PWM_INTEN_SEQSTARTED0_Disabled (0x0UL) /*!< Disable */
10587 #define PWM_INTEN_SEQSTARTED0_Enabled (0x1UL) /*!< Enable */
10588 
10589 /* Bit 1 : Enable or disable interrupt for event STOPPED */
10590 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10591 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10592 #define PWM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
10593 #define PWM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
10594 
10595 /* Register: PWM_INTENSET */
10596 /* Description: Enable interrupt */
10597 
10598 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
10599 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
10600 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
10601 #define PWM_INTENSET_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */
10602 #define PWM_INTENSET_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */
10603 #define PWM_INTENSET_LOOPSDONE_Set (0x1UL) /*!< Enable */
10604 
10605 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
10606 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
10607 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
10608 #define PWM_INTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */
10609 #define PWM_INTENSET_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */
10610 #define PWM_INTENSET_PWMPERIODEND_Set (0x1UL) /*!< Enable */
10611 
10612 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
10613 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
10614 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
10615 #define PWM_INTENSET_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */
10616 #define PWM_INTENSET_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */
10617 #define PWM_INTENSET_SEQEND1_Set (0x1UL) /*!< Enable */
10618 
10619 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
10620 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
10621 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
10622 #define PWM_INTENSET_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */
10623 #define PWM_INTENSET_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */
10624 #define PWM_INTENSET_SEQEND0_Set (0x1UL) /*!< Enable */
10625 
10626 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
10627 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
10628 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
10629 #define PWM_INTENSET_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */
10630 #define PWM_INTENSET_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */
10631 #define PWM_INTENSET_SEQSTARTED1_Set (0x1UL) /*!< Enable */
10632 
10633 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
10634 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
10635 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
10636 #define PWM_INTENSET_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */
10637 #define PWM_INTENSET_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */
10638 #define PWM_INTENSET_SEQSTARTED0_Set (0x1UL) /*!< Enable */
10639 
10640 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
10641 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10642 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10643 #define PWM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
10644 #define PWM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
10645 #define PWM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
10646 
10647 /* Register: PWM_INTENCLR */
10648 /* Description: Disable interrupt */
10649 
10650 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
10651 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
10652 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
10653 #define PWM_INTENCLR_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */
10654 #define PWM_INTENCLR_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */
10655 #define PWM_INTENCLR_LOOPSDONE_Clear (0x1UL) /*!< Disable */
10656 
10657 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
10658 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
10659 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
10660 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */
10661 #define PWM_INTENCLR_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */
10662 #define PWM_INTENCLR_PWMPERIODEND_Clear (0x1UL) /*!< Disable */
10663 
10664 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
10665 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
10666 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
10667 #define PWM_INTENCLR_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */
10668 #define PWM_INTENCLR_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */
10669 #define PWM_INTENCLR_SEQEND1_Clear (0x1UL) /*!< Disable */
10670 
10671 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
10672 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
10673 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
10674 #define PWM_INTENCLR_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */
10675 #define PWM_INTENCLR_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */
10676 #define PWM_INTENCLR_SEQEND0_Clear (0x1UL) /*!< Disable */
10677 
10678 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
10679 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
10680 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
10681 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */
10682 #define PWM_INTENCLR_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */
10683 #define PWM_INTENCLR_SEQSTARTED1_Clear (0x1UL) /*!< Disable */
10684 
10685 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
10686 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
10687 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
10688 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */
10689 #define PWM_INTENCLR_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */
10690 #define PWM_INTENCLR_SEQSTARTED0_Clear (0x1UL) /*!< Disable */
10691 
10692 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
10693 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10694 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10695 #define PWM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
10696 #define PWM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
10697 #define PWM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
10698 
10699 /* Register: PWM_ENABLE */
10700 /* Description: PWM module enable register */
10701 
10702 /* Bit 0 : Enable or disable PWM module */
10703 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10704 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10705 #define PWM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disabled */
10706 #define PWM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */
10707 
10708 /* Register: PWM_MODE */
10709 /* Description: Selects operating mode of the wave counter */
10710 
10711 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
10712 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
10713 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
10714 #define PWM_MODE_UPDOWN_Up (0x0UL) /*!< Up counter, edge-aligned PWM duty cycle */
10715 #define PWM_MODE_UPDOWN_UpAndDown (0x1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
10716 
10717 /* Register: PWM_COUNTERTOP */
10718 /* Description: Value up to which the pulse generator counter counts */
10719 
10720 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
10721 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
10722 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
10723 
10724 /* Register: PWM_PRESCALER */
10725 /* Description: Configuration for PWM_CLK */
10726 
10727 /* Bits 2..0 : Prescaler of PWM_CLK */
10728 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
10729 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
10730 #define PWM_PRESCALER_PRESCALER_DIV_1 (0x0UL) /*!< Divide by 1 (16 MHz) */
10731 #define PWM_PRESCALER_PRESCALER_DIV_2 (0x1UL) /*!< Divide by 2 (8 MHz) */
10732 #define PWM_PRESCALER_PRESCALER_DIV_4 (0x2UL) /*!< Divide by 4 (4 MHz) */
10733 #define PWM_PRESCALER_PRESCALER_DIV_8 (0x3UL) /*!< Divide by 8 (2 MHz) */
10734 #define PWM_PRESCALER_PRESCALER_DIV_16 (0x4UL) /*!< Divide by 16 (1 MHz) */
10735 #define PWM_PRESCALER_PRESCALER_DIV_32 (0x5UL) /*!< Divide by 32 (500 kHz) */
10736 #define PWM_PRESCALER_PRESCALER_DIV_64 (0x6UL) /*!< Divide by 64 (250 kHz) */
10737 #define PWM_PRESCALER_PRESCALER_DIV_128 (0x7UL) /*!< Divide by 128 (125 kHz) */
10738 
10739 /* Register: PWM_DECODER */
10740 /* Description: Configuration of the decoder */
10741 
10742 /* Bit 8 : Selects source for advancing the active sequence */
10743 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
10744 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
10745 #define PWM_DECODER_MODE_RefreshCount (0x0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
10746 #define PWM_DECODER_MODE_NextStep (0x1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
10747 
10748 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
10749 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
10750 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
10751 #define PWM_DECODER_LOAD_Common (0x0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
10752 #define PWM_DECODER_LOAD_Grouped (0x1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
10753 #define PWM_DECODER_LOAD_Individual (0x2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
10754 #define PWM_DECODER_LOAD_WaveForm (0x3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
10755 
10756 /* Register: PWM_LOOP */
10757 /* Description: Number of playbacks of a loop */
10758 
10759 /* Bits 15..0 : Number of playbacks of pattern cycles */
10760 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
10761 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
10762 #define PWM_LOOP_CNT_Disabled (0x0000UL) /*!< Looping disabled (stop at the end of the sequence) */
10763 
10764 /* Register: PWM_SEQ_PTR */
10765 /* Description: Description cluster: Beginning address in RAM of this sequence */
10766 
10767 /* Bits 31..0 : Beginning address in RAM of this sequence */
10768 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10769 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10770 
10771 /* Register: PWM_SEQ_CNT */
10772 /* Description: Description cluster: Number of values (duty cycles) in this sequence */
10773 
10774 /* Bits 14..0 : Number of values (duty cycles) in this sequence */
10775 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
10776 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
10777 #define PWM_SEQ_CNT_CNT_Disabled (0x0000UL) /*!< Sequence is disabled, and shall not be started as it is empty */
10778 
10779 /* Register: PWM_SEQ_REFRESH */
10780 /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */
10781 
10782 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
10783 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
10784 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
10785 #define PWM_SEQ_REFRESH_CNT_Continuous (0x000000UL) /*!< Update every PWM period */
10786 
10787 /* Register: PWM_SEQ_ENDDELAY */
10788 /* Description: Description cluster: Time added after the sequence */
10789 
10790 /* Bits 23..0 : Time added after the sequence in PWM periods */
10791 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
10792 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
10793 
10794 /* Register: PWM_PSEL_OUT */
10795 /* Description: Description collection: Output pin select for PWM channel n */
10796 
10797 /* Bit 31 : Connection */
10798 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10799 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10800 #define PWM_PSEL_OUT_CONNECT_Connected (0x0UL) /*!< Connect */
10801 #define PWM_PSEL_OUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
10802 
10803 /* Bit 5 : Port number */
10804 #define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */
10805 #define PWM_PSEL_OUT_PORT_Msk (0x1UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */
10806 
10807 /* Bits 4..0 : Pin number */
10808 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
10809 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
10810 
10811 
10812 /* Peripheral: QDEC */
10813 /* Description: Quadrature Decoder */
10814 
10815 /* Register: QDEC_TASKS_START */
10816 /* Description: Task starting the quadrature decoder */
10817 
10818 /* Bit 0 : Task starting the quadrature decoder */
10819 #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
10820 #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
10821 #define QDEC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
10822 
10823 /* Register: QDEC_TASKS_STOP */
10824 /* Description: Task stopping the quadrature decoder */
10825 
10826 /* Bit 0 : Task stopping the quadrature decoder */
10827 #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10828 #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10829 #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
10830 
10831 /* Register: QDEC_TASKS_READCLRACC */
10832 /* Description: Read and clear ACC and ACCDBL */
10833 
10834 /* Bit 0 : Read and clear ACC and ACCDBL */
10835 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */
10836 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */
10837 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (0x1UL) /*!< Trigger task */
10838 
10839 /* Register: QDEC_TASKS_RDCLRACC */
10840 /* Description: Read and clear ACC */
10841 
10842 /* Bit 0 : Read and clear ACC */
10843 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */
10844 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */
10845 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (0x1UL) /*!< Trigger task */
10846 
10847 /* Register: QDEC_TASKS_RDCLRDBL */
10848 /* Description: Read and clear ACCDBL */
10849 
10850 /* Bit 0 : Read and clear ACCDBL */
10851 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */
10852 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */
10853 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (0x1UL) /*!< Trigger task */
10854 
10855 /* Register: QDEC_EVENTS_SAMPLERDY */
10856 /* Description: Event being generated for every new sample value written to the SAMPLE register */
10857 
10858 /* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
10859 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */
10860 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */
10861 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0x0UL) /*!< Event not generated */
10862 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (0x1UL) /*!< Event generated */
10863 
10864 /* Register: QDEC_EVENTS_REPORTRDY */
10865 /* Description: Non-null report ready */
10866 
10867 /* Bit 0 : Non-null report ready */
10868 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */
10869 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */
10870 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0x0UL) /*!< Event not generated */
10871 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (0x1UL) /*!< Event generated */
10872 
10873 /* Register: QDEC_EVENTS_ACCOF */
10874 /* Description: ACC or ACCDBL register overflow */
10875 
10876 /* Bit 0 : ACC or ACCDBL register overflow */
10877 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */
10878 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */
10879 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0x0UL) /*!< Event not generated */
10880 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (0x1UL) /*!< Event generated */
10881 
10882 /* Register: QDEC_EVENTS_DBLRDY */
10883 /* Description: Double displacement(s) detected */
10884 
10885 /* Bit 0 : Double displacement(s) detected */
10886 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */
10887 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */
10888 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0x0UL) /*!< Event not generated */
10889 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (0x1UL) /*!< Event generated */
10890 
10891 /* Register: QDEC_EVENTS_STOPPED */
10892 /* Description: QDEC has been stopped */
10893 
10894 /* Bit 0 : QDEC has been stopped */
10895 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
10896 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
10897 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
10898 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
10899 
10900 /* Register: QDEC_SHORTS */
10901 /* Description: Shortcuts between local events and tasks */
10902 
10903 /* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
10904 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
10905 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
10906 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut */
10907 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut */
10908 
10909 /* Bit 5 : Shortcut between event DBLRDY and task STOP */
10910 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
10911 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
10912 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
10913 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */
10914 
10915 /* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
10916 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
10917 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
10918 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0x0UL) /*!< Disable shortcut */
10919 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (0x1UL) /*!< Enable shortcut */
10920 
10921 /* Bit 3 : Shortcut between event REPORTRDY and task STOP */
10922 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
10923 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
10924 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
10925 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */
10926 
10927 /* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
10928 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
10929 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
10930 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0x0UL) /*!< Disable shortcut */
10931 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (0x1UL) /*!< Enable shortcut */
10932 
10933 /* Bit 1 : Shortcut between event SAMPLERDY and task STOP */
10934 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
10935 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
10936 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
10937 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */
10938 
10939 /* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
10940 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
10941 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
10942 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut */
10943 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut */
10944 
10945 /* Register: QDEC_INTENSET */
10946 /* Description: Enable interrupt */
10947 
10948 /* Bit 4 : Write '1' to enable interrupt for event STOPPED */
10949 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
10950 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10951 #define QDEC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
10952 #define QDEC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
10953 #define QDEC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
10954 
10955 /* Bit 3 : Write '1' to enable interrupt for event DBLRDY */
10956 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
10957 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
10958 #define QDEC_INTENSET_DBLRDY_Disabled (0x0UL) /*!< Read: Disabled */
10959 #define QDEC_INTENSET_DBLRDY_Enabled (0x1UL) /*!< Read: Enabled */
10960 #define QDEC_INTENSET_DBLRDY_Set (0x1UL) /*!< Enable */
10961 
10962 /* Bit 2 : Write '1' to enable interrupt for event ACCOF */
10963 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
10964 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
10965 #define QDEC_INTENSET_ACCOF_Disabled (0x0UL) /*!< Read: Disabled */
10966 #define QDEC_INTENSET_ACCOF_Enabled (0x1UL) /*!< Read: Enabled */
10967 #define QDEC_INTENSET_ACCOF_Set (0x1UL) /*!< Enable */
10968 
10969 /* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
10970 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
10971 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
10972 #define QDEC_INTENSET_REPORTRDY_Disabled (0x0UL) /*!< Read: Disabled */
10973 #define QDEC_INTENSET_REPORTRDY_Enabled (0x1UL) /*!< Read: Enabled */
10974 #define QDEC_INTENSET_REPORTRDY_Set (0x1UL) /*!< Enable */
10975 
10976 /* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
10977 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
10978 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
10979 #define QDEC_INTENSET_SAMPLERDY_Disabled (0x0UL) /*!< Read: Disabled */
10980 #define QDEC_INTENSET_SAMPLERDY_Enabled (0x1UL) /*!< Read: Enabled */
10981 #define QDEC_INTENSET_SAMPLERDY_Set (0x1UL) /*!< Enable */
10982 
10983 /* Register: QDEC_INTENCLR */
10984 /* Description: Disable interrupt */
10985 
10986 /* Bit 4 : Write '1' to disable interrupt for event STOPPED */
10987 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
10988 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10989 #define QDEC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
10990 #define QDEC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
10991 #define QDEC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
10992 
10993 /* Bit 3 : Write '1' to disable interrupt for event DBLRDY */
10994 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
10995 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
10996 #define QDEC_INTENCLR_DBLRDY_Disabled (0x0UL) /*!< Read: Disabled */
10997 #define QDEC_INTENCLR_DBLRDY_Enabled (0x1UL) /*!< Read: Enabled */
10998 #define QDEC_INTENCLR_DBLRDY_Clear (0x1UL) /*!< Disable */
10999 
11000 /* Bit 2 : Write '1' to disable interrupt for event ACCOF */
11001 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
11002 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
11003 #define QDEC_INTENCLR_ACCOF_Disabled (0x0UL) /*!< Read: Disabled */
11004 #define QDEC_INTENCLR_ACCOF_Enabled (0x1UL) /*!< Read: Enabled */
11005 #define QDEC_INTENCLR_ACCOF_Clear (0x1UL) /*!< Disable */
11006 
11007 /* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
11008 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
11009 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
11010 #define QDEC_INTENCLR_REPORTRDY_Disabled (0x0UL) /*!< Read: Disabled */
11011 #define QDEC_INTENCLR_REPORTRDY_Enabled (0x1UL) /*!< Read: Enabled */
11012 #define QDEC_INTENCLR_REPORTRDY_Clear (0x1UL) /*!< Disable */
11013 
11014 /* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
11015 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
11016 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
11017 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0x0UL) /*!< Read: Disabled */
11018 #define QDEC_INTENCLR_SAMPLERDY_Enabled (0x1UL) /*!< Read: Enabled */
11019 #define QDEC_INTENCLR_SAMPLERDY_Clear (0x1UL) /*!< Disable */
11020 
11021 /* Register: QDEC_ENABLE */
11022 /* Description: Enable the quadrature decoder */
11023 
11024 /* Bit 0 : Enable or disable the quadrature decoder */
11025 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11026 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11027 #define QDEC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
11028 #define QDEC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */
11029 
11030 /* Register: QDEC_LEDPOL */
11031 /* Description: LED output pin polarity */
11032 
11033 /* Bit 0 : LED output pin polarity */
11034 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
11035 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
11036 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0x0UL) /*!< Led active on output pin low */
11037 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (0x1UL) /*!< Led active on output pin high */
11038 
11039 /* Register: QDEC_SAMPLEPER */
11040 /* Description: Sample period */
11041 
11042 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
11043 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
11044 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
11045 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x0UL) /*!< 128 us */
11046 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x1UL) /*!< 256 us */
11047 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x2UL) /*!< 512 us */
11048 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x3UL) /*!< 1024 us */
11049 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x4UL) /*!< 2048 us */
11050 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x5UL) /*!< 4096 us */
11051 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x6UL) /*!< 8192 us */
11052 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x7UL) /*!< 16384 us */
11053 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (0x8UL) /*!< 32768 us */
11054 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (0x9UL) /*!< 65536 us */
11055 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (0xAUL) /*!< 131072 us */
11056 
11057 /* Register: QDEC_SAMPLE */
11058 /* Description: Motion sample value */
11059 
11060 /* Bits 31..0 : Last motion sample */
11061 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
11062 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
11063 
11064 /* Register: QDEC_REPORTPER */
11065 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
11066 
11067 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */
11068 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
11069 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
11070 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x0UL) /*!< 10 samples/report */
11071 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x1UL) /*!< 40 samples/report */
11072 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x2UL) /*!< 80 samples/report */
11073 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x3UL) /*!< 120 samples/report */
11074 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x4UL) /*!< 160 samples/report */
11075 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x5UL) /*!< 200 samples/report */
11076 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x6UL) /*!< 240 samples/report */
11077 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x7UL) /*!< 280 samples/report */
11078 #define QDEC_REPORTPER_REPORTPER_1Smpl (0x8UL) /*!< 1 sample/report */
11079 
11080 /* Register: QDEC_ACC */
11081 /* Description: Register accumulating the valid transitions */
11082 
11083 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */
11084 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
11085 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
11086 
11087 /* Register: QDEC_ACCREAD */
11088 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
11089 
11090 /* Bits 31..0 : Snapshot of the ACC register. */
11091 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
11092 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
11093 
11094 /* Register: QDEC_PSEL_LED */
11095 /* Description: Pin select for LED signal */
11096 
11097 /* Bit 31 : Connection */
11098 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11099 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11100 #define QDEC_PSEL_LED_CONNECT_Connected (0x0UL) /*!< Connect */
11101 #define QDEC_PSEL_LED_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11102 
11103 /* Bit 5 : Port number */
11104 #define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */
11105 #define QDEC_PSEL_LED_PORT_Msk (0x1UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */
11106 
11107 /* Bits 4..0 : Pin number */
11108 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
11109 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
11110 
11111 /* Register: QDEC_PSEL_A */
11112 /* Description: Pin select for A signal */
11113 
11114 /* Bit 31 : Connection */
11115 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11116 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11117 #define QDEC_PSEL_A_CONNECT_Connected (0x0UL) /*!< Connect */
11118 #define QDEC_PSEL_A_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11119 
11120 /* Bit 5 : Port number */
11121 #define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */
11122 #define QDEC_PSEL_A_PORT_Msk (0x1UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */
11123 
11124 /* Bits 4..0 : Pin number */
11125 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
11126 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
11127 
11128 /* Register: QDEC_PSEL_B */
11129 /* Description: Pin select for B signal */
11130 
11131 /* Bit 31 : Connection */
11132 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11133 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11134 #define QDEC_PSEL_B_CONNECT_Connected (0x0UL) /*!< Connect */
11135 #define QDEC_PSEL_B_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11136 
11137 /* Bit 5 : Port number */
11138 #define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */
11139 #define QDEC_PSEL_B_PORT_Msk (0x1UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */
11140 
11141 /* Bits 4..0 : Pin number */
11142 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
11143 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
11144 
11145 /* Register: QDEC_DBFEN */
11146 /* Description: Enable input debounce filters */
11147 
11148 /* Bit 0 : Enable input debounce filters */
11149 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
11150 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
11151 #define QDEC_DBFEN_DBFEN_Disabled (0x0UL) /*!< Debounce input filters disabled */
11152 #define QDEC_DBFEN_DBFEN_Enabled (0x1UL) /*!< Debounce input filters enabled */
11153 
11154 /* Register: QDEC_LEDPRE */
11155 /* Description: Time period the LED is switched ON prior to sampling */
11156 
11157 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
11158 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
11159 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
11160 
11161 /* Register: QDEC_ACCDBL */
11162 /* Description: Register accumulating the number of detected double transitions */
11163 
11164 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
11165 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
11166 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
11167 
11168 /* Register: QDEC_ACCDBLREAD */
11169 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
11170 
11171 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
11172 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
11173 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
11174 
11175 
11176 /* Peripheral: QSPI */
11177 /* Description: External flash interface */
11178 
11179 /* Register: QSPI_TASKS_ACTIVATE */
11180 /* Description: Activate QSPI interface */
11181 
11182 /* Bit 0 : Activate QSPI interface */
11183 #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
11184 #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
11185 #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (0x1UL) /*!< Trigger task */
11186 
11187 /* Register: QSPI_TASKS_READSTART */
11188 /* Description: Start transfer from external flash memory to internal RAM */
11189 
11190 /* Bit 0 : Start transfer from external flash memory to internal RAM */
11191 #define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL) /*!< Position of TASKS_READSTART field. */
11192 #define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos) /*!< Bit mask of TASKS_READSTART field. */
11193 #define QSPI_TASKS_READSTART_TASKS_READSTART_Trigger (0x1UL) /*!< Trigger task */
11194 
11195 /* Register: QSPI_TASKS_WRITESTART */
11196 /* Description: Start transfer from internal RAM to external flash memory */
11197 
11198 /* Bit 0 : Start transfer from internal RAM to external flash memory */
11199 #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL) /*!< Position of TASKS_WRITESTART field. */
11200 #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos) /*!< Bit mask of TASKS_WRITESTART field. */
11201 #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Trigger (0x1UL) /*!< Trigger task */
11202 
11203 /* Register: QSPI_TASKS_ERASESTART */
11204 /* Description: Start external flash memory erase operation */
11205 
11206 /* Bit 0 : Start external flash memory erase operation */
11207 #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL) /*!< Position of TASKS_ERASESTART field. */
11208 #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos) /*!< Bit mask of TASKS_ERASESTART field. */
11209 #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Trigger (0x1UL) /*!< Trigger task */
11210 
11211 /* Register: QSPI_TASKS_DEACTIVATE */
11212 /* Description: Deactivate QSPI interface */
11213 
11214 /* Bit 0 : Deactivate QSPI interface */
11215 #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL) /*!< Position of TASKS_DEACTIVATE field. */
11216 #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos) /*!< Bit mask of TASKS_DEACTIVATE field. */
11217 #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Trigger (0x1UL) /*!< Trigger task */
11218 
11219 /* Register: QSPI_EVENTS_READY */
11220 /* Description: QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */
11221 
11222 /* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */
11223 #define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
11224 #define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
11225 #define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */
11226 #define QSPI_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */
11227 
11228 /* Register: QSPI_INTEN */
11229 /* Description: Enable or disable interrupt */
11230 
11231 /* Bit 0 : Enable or disable interrupt for event READY */
11232 #define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
11233 #define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */
11234 #define QSPI_INTEN_READY_Disabled (0x0UL) /*!< Disable */
11235 #define QSPI_INTEN_READY_Enabled (0x1UL) /*!< Enable */
11236 
11237 /* Register: QSPI_INTENSET */
11238 /* Description: Enable interrupt */
11239 
11240 /* Bit 0 : Write '1' to enable interrupt for event READY */
11241 #define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
11242 #define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
11243 #define QSPI_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */
11244 #define QSPI_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */
11245 #define QSPI_INTENSET_READY_Set (0x1UL) /*!< Enable */
11246 
11247 /* Register: QSPI_INTENCLR */
11248 /* Description: Disable interrupt */
11249 
11250 /* Bit 0 : Write '1' to disable interrupt for event READY */
11251 #define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
11252 #define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
11253 #define QSPI_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */
11254 #define QSPI_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */
11255 #define QSPI_INTENCLR_READY_Clear (0x1UL) /*!< Disable */
11256 
11257 /* Register: QSPI_ENABLE */
11258 /* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */
11259 
11260 /* Bit 0 : Enable or disable QSPI */
11261 #define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11262 #define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11263 #define QSPI_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable QSPI */
11264 #define QSPI_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable QSPI */
11265 
11266 /* Register: QSPI_READ_SRC */
11267 /* Description: Flash memory source address */
11268 
11269 /* Bits 31..0 : Word-aligned flash memory source address. */
11270 #define QSPI_READ_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
11271 #define QSPI_READ_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_READ_SRC_SRC_Pos) /*!< Bit mask of SRC field. */
11272 
11273 /* Register: QSPI_READ_DST */
11274 /* Description: RAM destination address */
11275 
11276 /* Bits 31..0 : Word-aligned RAM destination address. */
11277 #define QSPI_READ_DST_DST_Pos (0UL) /*!< Position of DST field. */
11278 #define QSPI_READ_DST_DST_Msk (0xFFFFFFFFUL << QSPI_READ_DST_DST_Pos) /*!< Bit mask of DST field. */
11279 
11280 /* Register: QSPI_READ_CNT */
11281 /* Description: Read transfer length */
11282 
11283 /* Bits 17..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */
11284 #define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
11285 #define QSPI_READ_CNT_CNT_Msk (0x3FFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
11286 
11287 /* Register: QSPI_WRITE_DST */
11288 /* Description: Flash destination address */
11289 
11290 /* Bits 31..0 : Word-aligned flash destination address. */
11291 #define QSPI_WRITE_DST_DST_Pos (0UL) /*!< Position of DST field. */
11292 #define QSPI_WRITE_DST_DST_Msk (0xFFFFFFFFUL << QSPI_WRITE_DST_DST_Pos) /*!< Bit mask of DST field. */
11293 
11294 /* Register: QSPI_WRITE_SRC */
11295 /* Description: RAM source address */
11296 
11297 /* Bits 31..0 : Word-aligned RAM source address. */
11298 #define QSPI_WRITE_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
11299 #define QSPI_WRITE_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_WRITE_SRC_SRC_Pos) /*!< Bit mask of SRC field. */
11300 
11301 /* Register: QSPI_WRITE_CNT */
11302 /* Description: Write transfer length */
11303 
11304 /* Bits 17..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */
11305 #define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
11306 #define QSPI_WRITE_CNT_CNT_Msk (0x3FFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
11307 
11308 /* Register: QSPI_ERASE_PTR */
11309 /* Description: Start address of flash block to be erased */
11310 
11311 /* Bits 31..0 : Word-aligned start address of block to be erased. */
11312 #define QSPI_ERASE_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11313 #define QSPI_ERASE_PTR_PTR_Msk (0xFFFFFFFFUL << QSPI_ERASE_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11314 
11315 /* Register: QSPI_ERASE_LEN */
11316 /* Description: Size of block to be erased. */
11317 
11318 /* Bits 1..0 : LEN */
11319 #define QSPI_ERASE_LEN_LEN_Pos (0UL) /*!< Position of LEN field. */
11320 #define QSPI_ERASE_LEN_LEN_Msk (0x3UL << QSPI_ERASE_LEN_LEN_Pos) /*!< Bit mask of LEN field. */
11321 #define QSPI_ERASE_LEN_LEN_4KB (0x0UL) /*!< Erase 4 kB block (flash command 0x20) */
11322 #define QSPI_ERASE_LEN_LEN_64KB (0x1UL) /*!< Erase 64 kB block (flash command 0xD8) */
11323 #define QSPI_ERASE_LEN_LEN_All (0x2UL) /*!< Erase all (flash command 0xC7) */
11324 
11325 /* Register: QSPI_PSEL_SCK */
11326 /* Description: Pin select for serial clock SCK */
11327 
11328 /* Bit 31 : Connection */
11329 #define QSPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11330 #define QSPI_PSEL_SCK_CONNECT_Msk (0x1UL << QSPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11331 #define QSPI_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
11332 #define QSPI_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11333 
11334 /* Bit 5 : Port number */
11335 #define QSPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
11336 #define QSPI_PSEL_SCK_PORT_Msk (0x1UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
11337 
11338 /* Bits 4..0 : Pin number */
11339 #define QSPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
11340 #define QSPI_PSEL_SCK_PIN_Msk (0x1FUL << QSPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
11341 
11342 /* Register: QSPI_PSEL_CSN */
11343 /* Description: Pin select for chip select signal CSN. */
11344 
11345 /* Bit 31 : Connection */
11346 #define QSPI_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11347 #define QSPI_PSEL_CSN_CONNECT_Msk (0x1UL << QSPI_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11348 #define QSPI_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */
11349 #define QSPI_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11350 
11351 /* Bit 5 : Port number */
11352 #define QSPI_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
11353 #define QSPI_PSEL_CSN_PORT_Msk (0x1UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
11354 
11355 /* Bits 4..0 : Pin number */
11356 #define QSPI_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
11357 #define QSPI_PSEL_CSN_PIN_Msk (0x1FUL << QSPI_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
11358 
11359 /* Register: QSPI_PSEL_IO0 */
11360 /* Description: Pin select for serial data MOSI/IO0. */
11361 
11362 /* Bit 31 : Connection */
11363 #define QSPI_PSEL_IO0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11364 #define QSPI_PSEL_IO0_CONNECT_Msk (0x1UL << QSPI_PSEL_IO0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11365 #define QSPI_PSEL_IO0_CONNECT_Connected (0x0UL) /*!< Connect */
11366 #define QSPI_PSEL_IO0_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11367 
11368 /* Bit 5 : Port number */
11369 #define QSPI_PSEL_IO0_PORT_Pos (5UL) /*!< Position of PORT field. */
11370 #define QSPI_PSEL_IO0_PORT_Msk (0x1UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */
11371 
11372 /* Bits 4..0 : Pin number */
11373 #define QSPI_PSEL_IO0_PIN_Pos (0UL) /*!< Position of PIN field. */
11374 #define QSPI_PSEL_IO0_PIN_Msk (0x1FUL << QSPI_PSEL_IO0_PIN_Pos) /*!< Bit mask of PIN field. */
11375 
11376 /* Register: QSPI_PSEL_IO1 */
11377 /* Description: Pin select for serial data MISO/IO1. */
11378 
11379 /* Bit 31 : Connection */
11380 #define QSPI_PSEL_IO1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11381 #define QSPI_PSEL_IO1_CONNECT_Msk (0x1UL << QSPI_PSEL_IO1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11382 #define QSPI_PSEL_IO1_CONNECT_Connected (0x0UL) /*!< Connect */
11383 #define QSPI_PSEL_IO1_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11384 
11385 /* Bit 5 : Port number */
11386 #define QSPI_PSEL_IO1_PORT_Pos (5UL) /*!< Position of PORT field. */
11387 #define QSPI_PSEL_IO1_PORT_Msk (0x1UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */
11388 
11389 /* Bits 4..0 : Pin number */
11390 #define QSPI_PSEL_IO1_PIN_Pos (0UL) /*!< Position of PIN field. */
11391 #define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos) /*!< Bit mask of PIN field. */
11392 
11393 /* Register: QSPI_PSEL_IO2 */
11394 /* Description: Pin select for serial data IO2. */
11395 
11396 /* Bit 31 : Connection */
11397 #define QSPI_PSEL_IO2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11398 #define QSPI_PSEL_IO2_CONNECT_Msk (0x1UL << QSPI_PSEL_IO2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11399 #define QSPI_PSEL_IO2_CONNECT_Connected (0x0UL) /*!< Connect */
11400 #define QSPI_PSEL_IO2_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11401 
11402 /* Bit 5 : Port number */
11403 #define QSPI_PSEL_IO2_PORT_Pos (5UL) /*!< Position of PORT field. */
11404 #define QSPI_PSEL_IO2_PORT_Msk (0x1UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */
11405 
11406 /* Bits 4..0 : Pin number */
11407 #define QSPI_PSEL_IO2_PIN_Pos (0UL) /*!< Position of PIN field. */
11408 #define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos) /*!< Bit mask of PIN field. */
11409 
11410 /* Register: QSPI_PSEL_IO3 */
11411 /* Description: Pin select for serial data IO3. */
11412 
11413 /* Bit 31 : Connection */
11414 #define QSPI_PSEL_IO3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11415 #define QSPI_PSEL_IO3_CONNECT_Msk (0x1UL << QSPI_PSEL_IO3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11416 #define QSPI_PSEL_IO3_CONNECT_Connected (0x0UL) /*!< Connect */
11417 #define QSPI_PSEL_IO3_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
11418 
11419 /* Bit 5 : Port number */
11420 #define QSPI_PSEL_IO3_PORT_Pos (5UL) /*!< Position of PORT field. */
11421 #define QSPI_PSEL_IO3_PORT_Msk (0x1UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */
11422 
11423 /* Bits 4..0 : Pin number */
11424 #define QSPI_PSEL_IO3_PIN_Pos (0UL) /*!< Position of PIN field. */
11425 #define QSPI_PSEL_IO3_PIN_Msk (0x1FUL << QSPI_PSEL_IO3_PIN_Pos) /*!< Bit mask of PIN field. */
11426 
11427 /* Register: QSPI_XIPOFFSET */
11428 /* Description: Address offset into the external memory for Execute in Place operation. */
11429 
11430 /* Bits 31..0 : Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. */
11431 #define QSPI_XIPOFFSET_XIPOFFSET_Pos (0UL) /*!< Position of XIPOFFSET field. */
11432 #define QSPI_XIPOFFSET_XIPOFFSET_Msk (0xFFFFFFFFUL << QSPI_XIPOFFSET_XIPOFFSET_Pos) /*!< Bit mask of XIPOFFSET field. */
11433 
11434 /* Register: QSPI_IFCONFIG0 */
11435 /* Description: Interface configuration. */
11436 
11437 /* Bit 12 : Page size for commands PP, PP2O, PP4O and PP4IO. */
11438 #define QSPI_IFCONFIG0_PPSIZE_Pos (12UL) /*!< Position of PPSIZE field. */
11439 #define QSPI_IFCONFIG0_PPSIZE_Msk (0x1UL << QSPI_IFCONFIG0_PPSIZE_Pos) /*!< Bit mask of PPSIZE field. */
11440 #define QSPI_IFCONFIG0_PPSIZE_256Bytes (0x0UL) /*!< 256 bytes. */
11441 #define QSPI_IFCONFIG0_PPSIZE_512Bytes (0x1UL) /*!< 512 bytes. */
11442 
11443 /* Bit 7 : Enable deep power-down mode (DPM) feature. */
11444 #define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL) /*!< Position of DPMENABLE field. */
11445 #define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos) /*!< Bit mask of DPMENABLE field. */
11446 #define QSPI_IFCONFIG0_DPMENABLE_Disable (0x0UL) /*!< Disable DPM feature. */
11447 #define QSPI_IFCONFIG0_DPMENABLE_Enable (0x1UL) /*!< Enable DPM feature. */
11448 
11449 /* Bit 6 : Addressing mode. */
11450 #define QSPI_IFCONFIG0_ADDRMODE_Pos (6UL) /*!< Position of ADDRMODE field. */
11451 #define QSPI_IFCONFIG0_ADDRMODE_Msk (0x1UL << QSPI_IFCONFIG0_ADDRMODE_Pos) /*!< Bit mask of ADDRMODE field. */
11452 #define QSPI_IFCONFIG0_ADDRMODE_24BIT (0x0UL) /*!< 24-bit addressing. */
11453 #define QSPI_IFCONFIG0_ADDRMODE_32BIT (0x1UL) /*!< 32-bit addressing. */
11454 
11455 /* Bits 5..3 : Configure number of data lines and opcode used for writing. */
11456 #define QSPI_IFCONFIG0_WRITEOC_Pos (3UL) /*!< Position of WRITEOC field. */
11457 #define QSPI_IFCONFIG0_WRITEOC_Msk (0x7UL << QSPI_IFCONFIG0_WRITEOC_Pos) /*!< Bit mask of WRITEOC field. */
11458 #define QSPI_IFCONFIG0_WRITEOC_PP (0x0UL) /*!< Single data line SPI. PP (opcode 0x02). */
11459 #define QSPI_IFCONFIG0_WRITEOC_PP2O (0x1UL) /*!< Dual data line SPI. PP2O (opcode 0xA2). */
11460 #define QSPI_IFCONFIG0_WRITEOC_PP4O (0x2UL) /*!< Quad data line SPI. PP4O (opcode 0x32). */
11461 #define QSPI_IFCONFIG0_WRITEOC_PP4IO (0x3UL) /*!< Quad data line SPI. PP4IO (opcode 0x38). */
11462 
11463 /* Bits 2..0 : Configure number of data lines and opcode used for reading. */
11464 #define QSPI_IFCONFIG0_READOC_Pos (0UL) /*!< Position of READOC field. */
11465 #define QSPI_IFCONFIG0_READOC_Msk (0x7UL << QSPI_IFCONFIG0_READOC_Pos) /*!< Bit mask of READOC field. */
11466 #define QSPI_IFCONFIG0_READOC_FASTREAD (0x0UL) /*!< Single data line SPI. FAST_READ (opcode 0x0B). */
11467 #define QSPI_IFCONFIG0_READOC_READ2O (0x1UL) /*!< Dual data line SPI. READ2O (opcode 0x3B). */
11468 #define QSPI_IFCONFIG0_READOC_READ2IO (0x2UL) /*!< Dual data line SPI. READ2IO (opcode 0xBB). */
11469 #define QSPI_IFCONFIG0_READOC_READ4O (0x3UL) /*!< Quad data line SPI. READ4O (opcode 0x6B). */
11470 #define QSPI_IFCONFIG0_READOC_READ4IO (0x4UL) /*!< Quad data line SPI. READ4IO (opcode 0xEB). */
11471 
11472 /* Register: QSPI_IFCONFIG1 */
11473 /* Description: Interface configuration. */
11474 
11475 /* Bits 31..28 : SCK frequency is given as 32 MHz / (SCKFREQ + 1). */
11476 #define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL) /*!< Position of SCKFREQ field. */
11477 #define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos) /*!< Bit mask of SCKFREQ field. */
11478 
11479 /* Bit 25 : Select SPI mode. */
11480 #define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */
11481 #define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */
11482 #define QSPI_IFCONFIG1_SPIMODE_MODE0 (0x0UL) /*!< Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */
11483 #define QSPI_IFCONFIG1_SPIMODE_MODE3 (0x1UL) /*!< Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). */
11484 
11485 /* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */
11486 #define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */
11487 #define QSPI_IFCONFIG1_DPMEN_Msk (0x1UL << QSPI_IFCONFIG1_DPMEN_Pos) /*!< Bit mask of DPMEN field. */
11488 #define QSPI_IFCONFIG1_DPMEN_Exit (0x0UL) /*!< Exit DPM. */
11489 #define QSPI_IFCONFIG1_DPMEN_Enter (0x1UL) /*!< Enter DPM. */
11490 
11491 /* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). */
11492 #define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */
11493 #define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */
11494 
11495 /* Register: QSPI_STATUS */
11496 /* Description: Status register. */
11497 
11498 /* Bits 31..24 : Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */
11499 #define QSPI_STATUS_SREG_Pos (24UL) /*!< Position of SREG field. */
11500 #define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos) /*!< Bit mask of SREG field. */
11501 
11502 /* Bit 3 : Ready status. */
11503 #define QSPI_STATUS_READY_Pos (3UL) /*!< Position of READY field. */
11504 #define QSPI_STATUS_READY_Msk (0x1UL << QSPI_STATUS_READY_Pos) /*!< Bit mask of READY field. */
11505 #define QSPI_STATUS_READY_BUSY (0x0UL) /*!< QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. */
11506 #define QSPI_STATUS_READY_READY (0x1UL) /*!< QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. */
11507 
11508 /* Bit 2 : Deep power-down mode (DPM) status of external flash. */
11509 #define QSPI_STATUS_DPM_Pos (2UL) /*!< Position of DPM field. */
11510 #define QSPI_STATUS_DPM_Msk (0x1UL << QSPI_STATUS_DPM_Pos) /*!< Bit mask of DPM field. */
11511 #define QSPI_STATUS_DPM_Disabled (0x0UL) /*!< External flash is not in DPM. */
11512 #define QSPI_STATUS_DPM_Enabled (0x1UL) /*!< External flash is in DPM. */
11513 
11514 /* Register: QSPI_DPMDUR */
11515 /* Description: Set the duration required to enter/exit deep power-down mode (DPM). */
11516 
11517 /* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. */
11518 #define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */
11519 #define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */
11520 
11521 /* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. */
11522 #define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */
11523 #define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */
11524 
11525 /* Register: QSPI_ADDRCONF */
11526 /* Description: Extended address configuration. */
11527 
11528 /* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */
11529 #define QSPI_ADDRCONF_WREN_Pos (27UL) /*!< Position of WREN field. */
11530 #define QSPI_ADDRCONF_WREN_Msk (0x1UL << QSPI_ADDRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
11531 #define QSPI_ADDRCONF_WREN_Disable (0x0UL) /*!< Do not send WREN. */
11532 #define QSPI_ADDRCONF_WREN_Enable (0x1UL) /*!< Send WREN. */
11533 
11534 /* Bit 26 : Wait for write complete before sending command. */
11535 #define QSPI_ADDRCONF_WIPWAIT_Pos (26UL) /*!< Position of WIPWAIT field. */
11536 #define QSPI_ADDRCONF_WIPWAIT_Msk (0x1UL << QSPI_ADDRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
11537 #define QSPI_ADDRCONF_WIPWAIT_Disable (0x0UL) /*!< No wait. */
11538 #define QSPI_ADDRCONF_WIPWAIT_Enable (0x1UL) /*!< Wait. */
11539 
11540 /* Bits 25..24 : Extended addressing mode. */
11541 #define QSPI_ADDRCONF_MODE_Pos (24UL) /*!< Position of MODE field. */
11542 #define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos) /*!< Bit mask of MODE field. */
11543 #define QSPI_ADDRCONF_MODE_NoInstr (0x0UL) /*!< Do not send any instruction. */
11544 #define QSPI_ADDRCONF_MODE_Opcode (0x1UL) /*!< Send opcode. */
11545 #define QSPI_ADDRCONF_MODE_OpByte0 (0x2UL) /*!< Send opcode, byte0. */
11546 #define QSPI_ADDRCONF_MODE_All (0x3UL) /*!< Send opcode, byte0, byte1. */
11547 
11548 /* Bits 23..16 : Byte 1 following byte 0. */
11549 #define QSPI_ADDRCONF_BYTE1_Pos (16UL) /*!< Position of BYTE1 field. */
11550 #define QSPI_ADDRCONF_BYTE1_Msk (0xFFUL << QSPI_ADDRCONF_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */
11551 
11552 /* Bits 15..8 : Byte 0 following opcode. */
11553 #define QSPI_ADDRCONF_BYTE0_Pos (8UL) /*!< Position of BYTE0 field. */
11554 #define QSPI_ADDRCONF_BYTE0_Msk (0xFFUL << QSPI_ADDRCONF_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */
11555 
11556 /* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */
11557 #define QSPI_ADDRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
11558 #define QSPI_ADDRCONF_OPCODE_Msk (0xFFUL << QSPI_ADDRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
11559 
11560 /* Register: QSPI_CINSTRCONF */
11561 /* Description: Custom instruction configuration register. */
11562 
11563 /* Bit 17 : Stop (finalize) long frame transaction */
11564 #define QSPI_CINSTRCONF_LFSTOP_Pos (17UL) /*!< Position of LFSTOP field. */
11565 #define QSPI_CINSTRCONF_LFSTOP_Msk (0x1UL << QSPI_CINSTRCONF_LFSTOP_Pos) /*!< Bit mask of LFSTOP field. */
11566 #define QSPI_CINSTRCONF_LFSTOP_Stop (0x1UL) /*!< Stop */
11567 
11568 /* Bit 16 : Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. */
11569 #define QSPI_CINSTRCONF_LFEN_Pos (16UL) /*!< Position of LFEN field. */
11570 #define QSPI_CINSTRCONF_LFEN_Msk (0x1UL << QSPI_CINSTRCONF_LFEN_Pos) /*!< Bit mask of LFEN field. */
11571 #define QSPI_CINSTRCONF_LFEN_Disable (0x0UL) /*!< Long frame mode disabled */
11572 #define QSPI_CINSTRCONF_LFEN_Enable (0x1UL) /*!< Long frame mode enabled */
11573 
11574 /* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */
11575 #define QSPI_CINSTRCONF_WREN_Pos (15UL) /*!< Position of WREN field. */
11576 #define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
11577 #define QSPI_CINSTRCONF_WREN_Disable (0x0UL) /*!< Do not send WREN. */
11578 #define QSPI_CINSTRCONF_WREN_Enable (0x1UL) /*!< Send WREN. */
11579 
11580 /* Bit 14 : Wait for write complete before sending command. */
11581 #define QSPI_CINSTRCONF_WIPWAIT_Pos (14UL) /*!< Position of WIPWAIT field. */
11582 #define QSPI_CINSTRCONF_WIPWAIT_Msk (0x1UL << QSPI_CINSTRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
11583 #define QSPI_CINSTRCONF_WIPWAIT_Disable (0x0UL) /*!< No wait. */
11584 #define QSPI_CINSTRCONF_WIPWAIT_Enable (0x1UL) /*!< Wait. */
11585 
11586 /* Bit 13 : Level of the IO3 pin (if connected) during transmission of custom instruction. */
11587 #define QSPI_CINSTRCONF_LIO3_Pos (13UL) /*!< Position of LIO3 field. */
11588 #define QSPI_CINSTRCONF_LIO3_Msk (0x1UL << QSPI_CINSTRCONF_LIO3_Pos) /*!< Bit mask of LIO3 field. */
11589 
11590 /* Bit 12 : Level of the IO2 pin (if connected) during transmission of custom instruction. */
11591 #define QSPI_CINSTRCONF_LIO2_Pos (12UL) /*!< Position of LIO2 field. */
11592 #define QSPI_CINSTRCONF_LIO2_Msk (0x1UL << QSPI_CINSTRCONF_LIO2_Pos) /*!< Bit mask of LIO2 field. */
11593 
11594 /* Bits 11..8 : Length of custom instruction in number of bytes. */
11595 #define QSPI_CINSTRCONF_LENGTH_Pos (8UL) /*!< Position of LENGTH field. */
11596 #define QSPI_CINSTRCONF_LENGTH_Msk (0xFUL << QSPI_CINSTRCONF_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
11597 #define QSPI_CINSTRCONF_LENGTH_1B (0x1UL) /*!< Send opcode only. */
11598 #define QSPI_CINSTRCONF_LENGTH_2B (0x2UL) /*!< Send opcode, CINSTRDAT0.BYTE0. */
11599 #define QSPI_CINSTRCONF_LENGTH_3B (0x3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. */
11600 #define QSPI_CINSTRCONF_LENGTH_4B (0x4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. */
11601 #define QSPI_CINSTRCONF_LENGTH_5B (0x5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. */
11602 #define QSPI_CINSTRCONF_LENGTH_6B (0x6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. */
11603 #define QSPI_CINSTRCONF_LENGTH_7B (0x7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. */
11604 #define QSPI_CINSTRCONF_LENGTH_8B (0x8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. */
11605 #define QSPI_CINSTRCONF_LENGTH_9B (0x9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. */
11606 
11607 /* Bits 7..0 : Opcode of Custom instruction. */
11608 #define QSPI_CINSTRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
11609 #define QSPI_CINSTRCONF_OPCODE_Msk (0xFFUL << QSPI_CINSTRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
11610 
11611 /* Register: QSPI_CINSTRDAT0 */
11612 /* Description: Custom instruction data register 0. */
11613 
11614 /* Bits 31..24 : Data byte 3 */
11615 #define QSPI_CINSTRDAT0_BYTE3_Pos (24UL) /*!< Position of BYTE3 field. */
11616 #define QSPI_CINSTRDAT0_BYTE3_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE3_Pos) /*!< Bit mask of BYTE3 field. */
11617 
11618 /* Bits 23..16 : Data byte 2 */
11619 #define QSPI_CINSTRDAT0_BYTE2_Pos (16UL) /*!< Position of BYTE2 field. */
11620 #define QSPI_CINSTRDAT0_BYTE2_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE2_Pos) /*!< Bit mask of BYTE2 field. */
11621 
11622 /* Bits 15..8 : Data byte 1 */
11623 #define QSPI_CINSTRDAT0_BYTE1_Pos (8UL) /*!< Position of BYTE1 field. */
11624 #define QSPI_CINSTRDAT0_BYTE1_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */
11625 
11626 /* Bits 7..0 : Data byte 0 */
11627 #define QSPI_CINSTRDAT0_BYTE0_Pos (0UL) /*!< Position of BYTE0 field. */
11628 #define QSPI_CINSTRDAT0_BYTE0_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */
11629 
11630 /* Register: QSPI_CINSTRDAT1 */
11631 /* Description: Custom instruction data register 1. */
11632 
11633 /* Bits 31..24 : Data byte 7 */
11634 #define QSPI_CINSTRDAT1_BYTE7_Pos (24UL) /*!< Position of BYTE7 field. */
11635 #define QSPI_CINSTRDAT1_BYTE7_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE7_Pos) /*!< Bit mask of BYTE7 field. */
11636 
11637 /* Bits 23..16 : Data byte 6 */
11638 #define QSPI_CINSTRDAT1_BYTE6_Pos (16UL) /*!< Position of BYTE6 field. */
11639 #define QSPI_CINSTRDAT1_BYTE6_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE6_Pos) /*!< Bit mask of BYTE6 field. */
11640 
11641 /* Bits 15..8 : Data byte 5 */
11642 #define QSPI_CINSTRDAT1_BYTE5_Pos (8UL) /*!< Position of BYTE5 field. */
11643 #define QSPI_CINSTRDAT1_BYTE5_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE5_Pos) /*!< Bit mask of BYTE5 field. */
11644 
11645 /* Bits 7..0 : Data byte 4 */
11646 #define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */
11647 #define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */
11648 
11649 /* Register: QSPI_IFTIMING */
11650 /* Description: SPI interface timing. */
11651 
11652 /* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. */
11653 #define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */
11654 #define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
11655 
11656 
11657 /* Peripheral: RADIO */
11658 /* Description: 2.4 GHz radio */
11659 
11660 /* Register: RADIO_TASKS_TXEN */
11661 /* Description: Enable RADIO in TX mode */
11662 
11663 /* Bit 0 : Enable RADIO in TX mode */
11664 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
11665 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
11666 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (0x1UL) /*!< Trigger task */
11667 
11668 /* Register: RADIO_TASKS_RXEN */
11669 /* Description: Enable RADIO in RX mode */
11670 
11671 /* Bit 0 : Enable RADIO in RX mode */
11672 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
11673 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
11674 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (0x1UL) /*!< Trigger task */
11675 
11676 /* Register: RADIO_TASKS_START */
11677 /* Description: Start RADIO */
11678 
11679 /* Bit 0 : Start RADIO */
11680 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11681 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11682 #define RADIO_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
11683 
11684 /* Register: RADIO_TASKS_STOP */
11685 /* Description: Stop RADIO */
11686 
11687 /* Bit 0 : Stop RADIO */
11688 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
11689 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
11690 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
11691 
11692 /* Register: RADIO_TASKS_DISABLE */
11693 /* Description: Disable RADIO */
11694 
11695 /* Bit 0 : Disable RADIO */
11696 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
11697 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
11698 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (0x1UL) /*!< Trigger task */
11699 
11700 /* Register: RADIO_TASKS_RSSISTART */
11701 /* Description: Start the RSSI and take one single sample of the receive signal strength */
11702 
11703 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */
11704 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
11705 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
11706 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (0x1UL) /*!< Trigger task */
11707 
11708 /* Register: RADIO_TASKS_RSSISTOP */
11709 /* Description: Stop the RSSI measurement */
11710 
11711 /* Bit 0 : Stop the RSSI measurement */
11712 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
11713 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
11714 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (0x1UL) /*!< Trigger task */
11715 
11716 /* Register: RADIO_TASKS_BCSTART */
11717 /* Description: Start the bit counter */
11718 
11719 /* Bit 0 : Start the bit counter */
11720 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
11721 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
11722 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (0x1UL) /*!< Trigger task */
11723 
11724 /* Register: RADIO_TASKS_BCSTOP */
11725 /* Description: Stop the bit counter */
11726 
11727 /* Bit 0 : Stop the bit counter */
11728 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
11729 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
11730 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (0x1UL) /*!< Trigger task */
11731 
11732 /* Register: RADIO_TASKS_EDSTART */
11733 /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */
11734 
11735 /* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */
11736 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */
11737 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */
11738 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (0x1UL) /*!< Trigger task */
11739 
11740 /* Register: RADIO_TASKS_EDSTOP */
11741 /* Description: Stop the energy detect measurement */
11742 
11743 /* Bit 0 : Stop the energy detect measurement */
11744 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */
11745 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */
11746 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (0x1UL) /*!< Trigger task */
11747 
11748 /* Register: RADIO_TASKS_CCASTART */
11749 /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */
11750 
11751 /* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */
11752 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */
11753 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */
11754 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (0x1UL) /*!< Trigger task */
11755 
11756 /* Register: RADIO_TASKS_CCASTOP */
11757 /* Description: Stop the clear channel assessment */
11758 
11759 /* Bit 0 : Stop the clear channel assessment */
11760 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */
11761 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */
11762 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (0x1UL) /*!< Trigger task */
11763 
11764 /* Register: RADIO_EVENTS_READY */
11765 /* Description: RADIO has ramped up and is ready to be started */
11766 
11767 /* Bit 0 : RADIO has ramped up and is ready to be started */
11768 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
11769 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
11770 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */
11771 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */
11772 
11773 /* Register: RADIO_EVENTS_ADDRESS */
11774 /* Description: Address sent or received */
11775 
11776 /* Bit 0 : Address sent or received */
11777 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
11778 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
11779 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0x0UL) /*!< Event not generated */
11780 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (0x1UL) /*!< Event generated */
11781 
11782 /* Register: RADIO_EVENTS_PAYLOAD */
11783 /* Description: Packet payload sent or received */
11784 
11785 /* Bit 0 : Packet payload sent or received */
11786 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
11787 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
11788 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0x0UL) /*!< Event not generated */
11789 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (0x1UL) /*!< Event generated */
11790 
11791 /* Register: RADIO_EVENTS_END */
11792 /* Description: Packet sent or received */
11793 
11794 /* Bit 0 : Packet sent or received */
11795 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
11796 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
11797 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
11798 #define RADIO_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */
11799 
11800 /* Register: RADIO_EVENTS_DISABLED */
11801 /* Description: RADIO has been disabled */
11802 
11803 /* Bit 0 : RADIO has been disabled */
11804 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
11805 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
11806 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0x0UL) /*!< Event not generated */
11807 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (0x1UL) /*!< Event generated */
11808 
11809 /* Register: RADIO_EVENTS_DEVMATCH */
11810 /* Description: A device address match occurred on the last received packet */
11811 
11812 /* Bit 0 : A device address match occurred on the last received packet */
11813 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
11814 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
11815 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0x0UL) /*!< Event not generated */
11816 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (0x1UL) /*!< Event generated */
11817 
11818 /* Register: RADIO_EVENTS_DEVMISS */
11819 /* Description: No device address match occurred on the last received packet */
11820 
11821 /* Bit 0 : No device address match occurred on the last received packet */
11822 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
11823 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
11824 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0x0UL) /*!< Event not generated */
11825 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (0x1UL) /*!< Event generated */
11826 
11827 /* Register: RADIO_EVENTS_RSSIEND */
11828 /* Description: Sampling of receive signal strength complete */
11829 
11830 /* Bit 0 : Sampling of receive signal strength complete */
11831 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
11832 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
11833 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0x0UL) /*!< Event not generated */
11834 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (0x1UL) /*!< Event generated */
11835 
11836 /* Register: RADIO_EVENTS_BCMATCH */
11837 /* Description: Bit counter reached bit count value */
11838 
11839 /* Bit 0 : Bit counter reached bit count value */
11840 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
11841 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
11842 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0x0UL) /*!< Event not generated */
11843 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (0x1UL) /*!< Event generated */
11844 
11845 /* Register: RADIO_EVENTS_CRCOK */
11846 /* Description: Packet received with CRC ok */
11847 
11848 /* Bit 0 : Packet received with CRC ok */
11849 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
11850 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
11851 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0x0UL) /*!< Event not generated */
11852 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (0x1UL) /*!< Event generated */
11853 
11854 /* Register: RADIO_EVENTS_CRCERROR */
11855 /* Description: Packet received with CRC error */
11856 
11857 /* Bit 0 : Packet received with CRC error */
11858 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
11859 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
11860 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0x0UL) /*!< Event not generated */
11861 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (0x1UL) /*!< Event generated */
11862 
11863 /* Register: RADIO_EVENTS_FRAMESTART */
11864 /* Description: IEEE 802.15.4 length field received */
11865 
11866 /* Bit 0 : IEEE 802.15.4 length field received */
11867 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */
11868 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */
11869 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */
11870 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (0x1UL) /*!< Event generated */
11871 
11872 /* Register: RADIO_EVENTS_EDEND */
11873 /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
11874 
11875 /* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
11876 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */
11877 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */
11878 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0x0UL) /*!< Event not generated */
11879 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (0x1UL) /*!< Event generated */
11880 
11881 /* Register: RADIO_EVENTS_EDSTOPPED */
11882 /* Description: The sampling of energy detection has stopped */
11883 
11884 /* Bit 0 : The sampling of energy detection has stopped */
11885 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */
11886 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */
11887 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */
11888 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (0x1UL) /*!< Event generated */
11889 
11890 /* Register: RADIO_EVENTS_CCAIDLE */
11891 /* Description: Wireless medium in idle - clear to send */
11892 
11893 /* Bit 0 : Wireless medium in idle - clear to send */
11894 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */
11895 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */
11896 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0x0UL) /*!< Event not generated */
11897 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (0x1UL) /*!< Event generated */
11898 
11899 /* Register: RADIO_EVENTS_CCABUSY */
11900 /* Description: Wireless medium busy - do not send */
11901 
11902 /* Bit 0 : Wireless medium busy - do not send */
11903 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */
11904 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */
11905 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0x0UL) /*!< Event not generated */
11906 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (0x1UL) /*!< Event generated */
11907 
11908 /* Register: RADIO_EVENTS_CCASTOPPED */
11909 /* Description: The CCA has stopped */
11910 
11911 /* Bit 0 : The CCA has stopped */
11912 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */
11913 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */
11914 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0x0UL) /*!< Event not generated */
11915 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (0x1UL) /*!< Event generated */
11916 
11917 /* Register: RADIO_EVENTS_RATEBOOST */
11918 /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
11919 
11920 /* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
11921 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */
11922 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */
11923 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0x0UL) /*!< Event not generated */
11924 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (0x1UL) /*!< Event generated */
11925 
11926 /* Register: RADIO_EVENTS_TXREADY */
11927 /* Description: RADIO has ramped up and is ready to be started TX path */
11928 
11929 /* Bit 0 : RADIO has ramped up and is ready to be started TX path */
11930 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */
11931 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */
11932 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0x0UL) /*!< Event not generated */
11933 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (0x1UL) /*!< Event generated */
11934 
11935 /* Register: RADIO_EVENTS_RXREADY */
11936 /* Description: RADIO has ramped up and is ready to be started RX path */
11937 
11938 /* Bit 0 : RADIO has ramped up and is ready to be started RX path */
11939 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */
11940 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */
11941 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0x0UL) /*!< Event not generated */
11942 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (0x1UL) /*!< Event generated */
11943 
11944 /* Register: RADIO_EVENTS_MHRMATCH */
11945 /* Description: MAC header match found */
11946 
11947 /* Bit 0 : MAC header match found */
11948 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */
11949 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */
11950 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0x0UL) /*!< Event not generated */
11951 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (0x1UL) /*!< Event generated */
11952 
11953 /* Register: RADIO_EVENTS_SYNC */
11954 /* Description: Preamble indicator. */
11955 
11956 /* Bit 0 : Preamble indicator. */
11957 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */
11958 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */
11959 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0x0UL) /*!< Event not generated */
11960 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (0x1UL) /*!< Event generated */
11961 
11962 /* Register: RADIO_EVENTS_PHYEND */
11963 /* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */
11964 
11965 /* Bit 0 : Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */
11966 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */
11967 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */
11968 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0x0UL) /*!< Event not generated */
11969 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (0x1UL) /*!< Event generated */
11970 
11971 /* Register: RADIO_SHORTS */
11972 /* Description: Shortcuts between local events and tasks */
11973 
11974 /* Bit 21 : Shortcut between event PHYEND and task START */
11975 #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */
11976 #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */
11977 #define RADIO_SHORTS_PHYEND_START_Disabled (0x0UL) /*!< Disable shortcut */
11978 #define RADIO_SHORTS_PHYEND_START_Enabled (0x1UL) /*!< Enable shortcut */
11979 
11980 /* Bit 20 : Shortcut between event PHYEND and task DISABLE */
11981 #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */
11982 #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */
11983 #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */
11984 #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */
11985 
11986 /* Bit 19 : Shortcut between event RXREADY and task START */
11987 #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */
11988 #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */
11989 #define RADIO_SHORTS_RXREADY_START_Disabled (0x0UL) /*!< Disable shortcut */
11990 #define RADIO_SHORTS_RXREADY_START_Enabled (0x1UL) /*!< Enable shortcut */
11991 
11992 /* Bit 18 : Shortcut between event TXREADY and task START */
11993 #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */
11994 #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */
11995 #define RADIO_SHORTS_TXREADY_START_Disabled (0x0UL) /*!< Disable shortcut */
11996 #define RADIO_SHORTS_TXREADY_START_Enabled (0x1UL) /*!< Enable shortcut */
11997 
11998 /* Bit 17 : Shortcut between event CCAIDLE and task STOP */
11999 #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */
12000 #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */
12001 #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0x0UL) /*!< Disable shortcut */
12002 #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (0x1UL) /*!< Enable shortcut */
12003 
12004 /* Bit 16 : Shortcut between event EDEND and task DISABLE */
12005 #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */
12006 #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */
12007 #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */
12008 #define RADIO_SHORTS_EDEND_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */
12009 
12010 /* Bit 15 : Shortcut between event READY and task EDSTART */
12011 #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */
12012 #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */
12013 #define RADIO_SHORTS_READY_EDSTART_Disabled (0x0UL) /*!< Disable shortcut */
12014 #define RADIO_SHORTS_READY_EDSTART_Enabled (0x1UL) /*!< Enable shortcut */
12015 
12016 /* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */
12017 #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */
12018 #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */
12019 #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0x0UL) /*!< Disable shortcut */
12020 #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (0x1UL) /*!< Enable shortcut */
12021 
12022 /* Bit 13 : Shortcut between event CCABUSY and task DISABLE */
12023 #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */
12024 #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
12025 #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */
12026 #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */
12027 
12028 /* Bit 12 : Shortcut between event CCAIDLE and task TXEN */
12029 #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */
12030 #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */
12031 #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0x0UL) /*!< Disable shortcut */
12032 #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (0x1UL) /*!< Enable shortcut */
12033 
12034 /* Bit 11 : Shortcut between event RXREADY and task CCASTART */
12035 #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */
12036 #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */
12037 #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0x0UL) /*!< Disable shortcut */
12038 #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (0x1UL) /*!< Enable shortcut */
12039 
12040 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
12041 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
12042 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
12043 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0x0UL) /*!< Disable shortcut */
12044 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (0x1UL) /*!< Enable shortcut */
12045 
12046 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
12047 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
12048 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
12049 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0x0UL) /*!< Disable shortcut */
12050 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (0x1UL) /*!< Enable shortcut */
12051 
12052 /* Bit 5 : Shortcut between event END and task START */
12053 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
12054 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
12055 #define RADIO_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */
12056 #define RADIO_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */
12057 
12058 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
12059 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
12060 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
12061 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0x0UL) /*!< Disable shortcut */
12062 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (0x1UL) /*!< Enable shortcut */
12063 
12064 /* Bit 3 : Shortcut between event DISABLED and task RXEN */
12065 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
12066 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
12067 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0x0UL) /*!< Disable shortcut */
12068 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (0x1UL) /*!< Enable shortcut */
12069 
12070 /* Bit 2 : Shortcut between event DISABLED and task TXEN */
12071 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
12072 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
12073 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0x0UL) /*!< Disable shortcut */
12074 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (0x1UL) /*!< Enable shortcut */
12075 
12076 /* Bit 1 : Shortcut between event END and task DISABLE */
12077 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
12078 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
12079 #define RADIO_SHORTS_END_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */
12080 #define RADIO_SHORTS_END_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */
12081 
12082 /* Bit 0 : Shortcut between event READY and task START */
12083 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
12084 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
12085 #define RADIO_SHORTS_READY_START_Disabled (0x0UL) /*!< Disable shortcut */
12086 #define RADIO_SHORTS_READY_START_Enabled (0x1UL) /*!< Enable shortcut */
12087 
12088 /* Register: RADIO_INTENSET */
12089 /* Description: Enable interrupt */
12090 
12091 /* Bit 27 : Write '1' to enable interrupt for event PHYEND */
12092 #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
12093 #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
12094 #define RADIO_INTENSET_PHYEND_Disabled (0x0UL) /*!< Read: Disabled */
12095 #define RADIO_INTENSET_PHYEND_Enabled (0x1UL) /*!< Read: Enabled */
12096 #define RADIO_INTENSET_PHYEND_Set (0x1UL) /*!< Enable */
12097 
12098 /* Bit 26 : Write '1' to enable interrupt for event SYNC */
12099 #define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */
12100 #define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */
12101 #define RADIO_INTENSET_SYNC_Disabled (0x0UL) /*!< Read: Disabled */
12102 #define RADIO_INTENSET_SYNC_Enabled (0x1UL) /*!< Read: Enabled */
12103 #define RADIO_INTENSET_SYNC_Set (0x1UL) /*!< Enable */
12104 
12105 /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */
12106 #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
12107 #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
12108 #define RADIO_INTENSET_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled */
12109 #define RADIO_INTENSET_MHRMATCH_Enabled (0x1UL) /*!< Read: Enabled */
12110 #define RADIO_INTENSET_MHRMATCH_Set (0x1UL) /*!< Enable */
12111 
12112 /* Bit 22 : Write '1' to enable interrupt for event RXREADY */
12113 #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
12114 #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
12115 #define RADIO_INTENSET_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */
12116 #define RADIO_INTENSET_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */
12117 #define RADIO_INTENSET_RXREADY_Set (0x1UL) /*!< Enable */
12118 
12119 /* Bit 21 : Write '1' to enable interrupt for event TXREADY */
12120 #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
12121 #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
12122 #define RADIO_INTENSET_TXREADY_Disabled (0x0UL) /*!< Read: Disabled */
12123 #define RADIO_INTENSET_TXREADY_Enabled (0x1UL) /*!< Read: Enabled */
12124 #define RADIO_INTENSET_TXREADY_Set (0x1UL) /*!< Enable */
12125 
12126 /* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
12127 #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
12128 #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
12129 #define RADIO_INTENSET_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled */
12130 #define RADIO_INTENSET_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled */
12131 #define RADIO_INTENSET_RATEBOOST_Set (0x1UL) /*!< Enable */
12132 
12133 /* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
12134 #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
12135 #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
12136 #define RADIO_INTENSET_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
12137 #define RADIO_INTENSET_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
12138 #define RADIO_INTENSET_CCASTOPPED_Set (0x1UL) /*!< Enable */
12139 
12140 /* Bit 18 : Write '1' to enable interrupt for event CCABUSY */
12141 #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
12142 #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
12143 #define RADIO_INTENSET_CCABUSY_Disabled (0x0UL) /*!< Read: Disabled */
12144 #define RADIO_INTENSET_CCABUSY_Enabled (0x1UL) /*!< Read: Enabled */
12145 #define RADIO_INTENSET_CCABUSY_Set (0x1UL) /*!< Enable */
12146 
12147 /* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
12148 #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
12149 #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
12150 #define RADIO_INTENSET_CCAIDLE_Disabled (0x0UL) /*!< Read: Disabled */
12151 #define RADIO_INTENSET_CCAIDLE_Enabled (0x1UL) /*!< Read: Enabled */
12152 #define RADIO_INTENSET_CCAIDLE_Set (0x1UL) /*!< Enable */
12153 
12154 /* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
12155 #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
12156 #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
12157 #define RADIO_INTENSET_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
12158 #define RADIO_INTENSET_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
12159 #define RADIO_INTENSET_EDSTOPPED_Set (0x1UL) /*!< Enable */
12160 
12161 /* Bit 15 : Write '1' to enable interrupt for event EDEND */
12162 #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */
12163 #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */
12164 #define RADIO_INTENSET_EDEND_Disabled (0x0UL) /*!< Read: Disabled */
12165 #define RADIO_INTENSET_EDEND_Enabled (0x1UL) /*!< Read: Enabled */
12166 #define RADIO_INTENSET_EDEND_Set (0x1UL) /*!< Enable */
12167 
12168 /* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */
12169 #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
12170 #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
12171 #define RADIO_INTENSET_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
12172 #define RADIO_INTENSET_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
12173 #define RADIO_INTENSET_FRAMESTART_Set (0x1UL) /*!< Enable */
12174 
12175 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
12176 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
12177 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
12178 #define RADIO_INTENSET_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled */
12179 #define RADIO_INTENSET_CRCERROR_Enabled (0x1UL) /*!< Read: Enabled */
12180 #define RADIO_INTENSET_CRCERROR_Set (0x1UL) /*!< Enable */
12181 
12182 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */
12183 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
12184 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
12185 #define RADIO_INTENSET_CRCOK_Disabled (0x0UL) /*!< Read: Disabled */
12186 #define RADIO_INTENSET_CRCOK_Enabled (0x1UL) /*!< Read: Enabled */
12187 #define RADIO_INTENSET_CRCOK_Set (0x1UL) /*!< Enable */
12188 
12189 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
12190 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
12191 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
12192 #define RADIO_INTENSET_BCMATCH_Disabled (0x0UL) /*!< Read: Disabled */
12193 #define RADIO_INTENSET_BCMATCH_Enabled (0x1UL) /*!< Read: Enabled */
12194 #define RADIO_INTENSET_BCMATCH_Set (0x1UL) /*!< Enable */
12195 
12196 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
12197 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
12198 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
12199 #define RADIO_INTENSET_RSSIEND_Disabled (0x0UL) /*!< Read: Disabled */
12200 #define RADIO_INTENSET_RSSIEND_Enabled (0x1UL) /*!< Read: Enabled */
12201 #define RADIO_INTENSET_RSSIEND_Set (0x1UL) /*!< Enable */
12202 
12203 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
12204 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
12205 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
12206 #define RADIO_INTENSET_DEVMISS_Disabled (0x0UL) /*!< Read: Disabled */
12207 #define RADIO_INTENSET_DEVMISS_Enabled (0x1UL) /*!< Read: Enabled */
12208 #define RADIO_INTENSET_DEVMISS_Set (0x1UL) /*!< Enable */
12209 
12210 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
12211 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
12212 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
12213 #define RADIO_INTENSET_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled */
12214 #define RADIO_INTENSET_DEVMATCH_Enabled (0x1UL) /*!< Read: Enabled */
12215 #define RADIO_INTENSET_DEVMATCH_Set (0x1UL) /*!< Enable */
12216 
12217 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */
12218 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
12219 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
12220 #define RADIO_INTENSET_DISABLED_Disabled (0x0UL) /*!< Read: Disabled */
12221 #define RADIO_INTENSET_DISABLED_Enabled (0x1UL) /*!< Read: Enabled */
12222 #define RADIO_INTENSET_DISABLED_Set (0x1UL) /*!< Enable */
12223 
12224 /* Bit 3 : Write '1' to enable interrupt for event END */
12225 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
12226 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
12227 #define RADIO_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
12228 #define RADIO_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
12229 #define RADIO_INTENSET_END_Set (0x1UL) /*!< Enable */
12230 
12231 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
12232 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
12233 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
12234 #define RADIO_INTENSET_PAYLOAD_Disabled (0x0UL) /*!< Read: Disabled */
12235 #define RADIO_INTENSET_PAYLOAD_Enabled (0x1UL) /*!< Read: Enabled */
12236 #define RADIO_INTENSET_PAYLOAD_Set (0x1UL) /*!< Enable */
12237 
12238 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
12239 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
12240 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
12241 #define RADIO_INTENSET_ADDRESS_Disabled (0x0UL) /*!< Read: Disabled */
12242 #define RADIO_INTENSET_ADDRESS_Enabled (0x1UL) /*!< Read: Enabled */
12243 #define RADIO_INTENSET_ADDRESS_Set (0x1UL) /*!< Enable */
12244 
12245 /* Bit 0 : Write '1' to enable interrupt for event READY */
12246 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
12247 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
12248 #define RADIO_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */
12249 #define RADIO_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */
12250 #define RADIO_INTENSET_READY_Set (0x1UL) /*!< Enable */
12251 
12252 /* Register: RADIO_INTENCLR */
12253 /* Description: Disable interrupt */
12254 
12255 /* Bit 27 : Write '1' to disable interrupt for event PHYEND */
12256 #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
12257 #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
12258 #define RADIO_INTENCLR_PHYEND_Disabled (0x0UL) /*!< Read: Disabled */
12259 #define RADIO_INTENCLR_PHYEND_Enabled (0x1UL) /*!< Read: Enabled */
12260 #define RADIO_INTENCLR_PHYEND_Clear (0x1UL) /*!< Disable */
12261 
12262 /* Bit 26 : Write '1' to disable interrupt for event SYNC */
12263 #define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */
12264 #define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */
12265 #define RADIO_INTENCLR_SYNC_Disabled (0x0UL) /*!< Read: Disabled */
12266 #define RADIO_INTENCLR_SYNC_Enabled (0x1UL) /*!< Read: Enabled */
12267 #define RADIO_INTENCLR_SYNC_Clear (0x1UL) /*!< Disable */
12268 
12269 /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */
12270 #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
12271 #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
12272 #define RADIO_INTENCLR_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled */
12273 #define RADIO_INTENCLR_MHRMATCH_Enabled (0x1UL) /*!< Read: Enabled */
12274 #define RADIO_INTENCLR_MHRMATCH_Clear (0x1UL) /*!< Disable */
12275 
12276 /* Bit 22 : Write '1' to disable interrupt for event RXREADY */
12277 #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
12278 #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
12279 #define RADIO_INTENCLR_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */
12280 #define RADIO_INTENCLR_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */
12281 #define RADIO_INTENCLR_RXREADY_Clear (0x1UL) /*!< Disable */
12282 
12283 /* Bit 21 : Write '1' to disable interrupt for event TXREADY */
12284 #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
12285 #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
12286 #define RADIO_INTENCLR_TXREADY_Disabled (0x0UL) /*!< Read: Disabled */
12287 #define RADIO_INTENCLR_TXREADY_Enabled (0x1UL) /*!< Read: Enabled */
12288 #define RADIO_INTENCLR_TXREADY_Clear (0x1UL) /*!< Disable */
12289 
12290 /* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
12291 #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
12292 #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
12293 #define RADIO_INTENCLR_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled */
12294 #define RADIO_INTENCLR_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled */
12295 #define RADIO_INTENCLR_RATEBOOST_Clear (0x1UL) /*!< Disable */
12296 
12297 /* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
12298 #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
12299 #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
12300 #define RADIO_INTENCLR_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
12301 #define RADIO_INTENCLR_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
12302 #define RADIO_INTENCLR_CCASTOPPED_Clear (0x1UL) /*!< Disable */
12303 
12304 /* Bit 18 : Write '1' to disable interrupt for event CCABUSY */
12305 #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
12306 #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
12307 #define RADIO_INTENCLR_CCABUSY_Disabled (0x0UL) /*!< Read: Disabled */
12308 #define RADIO_INTENCLR_CCABUSY_Enabled (0x1UL) /*!< Read: Enabled */
12309 #define RADIO_INTENCLR_CCABUSY_Clear (0x1UL) /*!< Disable */
12310 
12311 /* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
12312 #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
12313 #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
12314 #define RADIO_INTENCLR_CCAIDLE_Disabled (0x0UL) /*!< Read: Disabled */
12315 #define RADIO_INTENCLR_CCAIDLE_Enabled (0x1UL) /*!< Read: Enabled */
12316 #define RADIO_INTENCLR_CCAIDLE_Clear (0x1UL) /*!< Disable */
12317 
12318 /* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
12319 #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
12320 #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
12321 #define RADIO_INTENCLR_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
12322 #define RADIO_INTENCLR_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
12323 #define RADIO_INTENCLR_EDSTOPPED_Clear (0x1UL) /*!< Disable */
12324 
12325 /* Bit 15 : Write '1' to disable interrupt for event EDEND */
12326 #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */
12327 #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */
12328 #define RADIO_INTENCLR_EDEND_Disabled (0x0UL) /*!< Read: Disabled */
12329 #define RADIO_INTENCLR_EDEND_Enabled (0x1UL) /*!< Read: Enabled */
12330 #define RADIO_INTENCLR_EDEND_Clear (0x1UL) /*!< Disable */
12331 
12332 /* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */
12333 #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
12334 #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
12335 #define RADIO_INTENCLR_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
12336 #define RADIO_INTENCLR_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
12337 #define RADIO_INTENCLR_FRAMESTART_Clear (0x1UL) /*!< Disable */
12338 
12339 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
12340 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
12341 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
12342 #define RADIO_INTENCLR_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled */
12343 #define RADIO_INTENCLR_CRCERROR_Enabled (0x1UL) /*!< Read: Enabled */
12344 #define RADIO_INTENCLR_CRCERROR_Clear (0x1UL) /*!< Disable */
12345 
12346 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */
12347 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
12348 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
12349 #define RADIO_INTENCLR_CRCOK_Disabled (0x0UL) /*!< Read: Disabled */
12350 #define RADIO_INTENCLR_CRCOK_Enabled (0x1UL) /*!< Read: Enabled */
12351 #define RADIO_INTENCLR_CRCOK_Clear (0x1UL) /*!< Disable */
12352 
12353 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
12354 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
12355 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
12356 #define RADIO_INTENCLR_BCMATCH_Disabled (0x0UL) /*!< Read: Disabled */
12357 #define RADIO_INTENCLR_BCMATCH_Enabled (0x1UL) /*!< Read: Enabled */
12358 #define RADIO_INTENCLR_BCMATCH_Clear (0x1UL) /*!< Disable */
12359 
12360 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
12361 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
12362 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
12363 #define RADIO_INTENCLR_RSSIEND_Disabled (0x0UL) /*!< Read: Disabled */
12364 #define RADIO_INTENCLR_RSSIEND_Enabled (0x1UL) /*!< Read: Enabled */
12365 #define RADIO_INTENCLR_RSSIEND_Clear (0x1UL) /*!< Disable */
12366 
12367 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
12368 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
12369 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
12370 #define RADIO_INTENCLR_DEVMISS_Disabled (0x0UL) /*!< Read: Disabled */
12371 #define RADIO_INTENCLR_DEVMISS_Enabled (0x1UL) /*!< Read: Enabled */
12372 #define RADIO_INTENCLR_DEVMISS_Clear (0x1UL) /*!< Disable */
12373 
12374 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
12375 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
12376 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
12377 #define RADIO_INTENCLR_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled */
12378 #define RADIO_INTENCLR_DEVMATCH_Enabled (0x1UL) /*!< Read: Enabled */
12379 #define RADIO_INTENCLR_DEVMATCH_Clear (0x1UL) /*!< Disable */
12380 
12381 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */
12382 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
12383 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
12384 #define RADIO_INTENCLR_DISABLED_Disabled (0x0UL) /*!< Read: Disabled */
12385 #define RADIO_INTENCLR_DISABLED_Enabled (0x1UL) /*!< Read: Enabled */
12386 #define RADIO_INTENCLR_DISABLED_Clear (0x1UL) /*!< Disable */
12387 
12388 /* Bit 3 : Write '1' to disable interrupt for event END */
12389 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
12390 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
12391 #define RADIO_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
12392 #define RADIO_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
12393 #define RADIO_INTENCLR_END_Clear (0x1UL) /*!< Disable */
12394 
12395 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
12396 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
12397 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
12398 #define RADIO_INTENCLR_PAYLOAD_Disabled (0x0UL) /*!< Read: Disabled */
12399 #define RADIO_INTENCLR_PAYLOAD_Enabled (0x1UL) /*!< Read: Enabled */
12400 #define RADIO_INTENCLR_PAYLOAD_Clear (0x1UL) /*!< Disable */
12401 
12402 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
12403 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
12404 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
12405 #define RADIO_INTENCLR_ADDRESS_Disabled (0x0UL) /*!< Read: Disabled */
12406 #define RADIO_INTENCLR_ADDRESS_Enabled (0x1UL) /*!< Read: Enabled */
12407 #define RADIO_INTENCLR_ADDRESS_Clear (0x1UL) /*!< Disable */
12408 
12409 /* Bit 0 : Write '1' to disable interrupt for event READY */
12410 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
12411 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
12412 #define RADIO_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */
12413 #define RADIO_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */
12414 #define RADIO_INTENCLR_READY_Clear (0x1UL) /*!< Disable */
12415 
12416 /* Register: RADIO_CRCSTATUS */
12417 /* Description: CRC status */
12418 
12419 /* Bit 0 : CRC status of packet received */
12420 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
12421 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
12422 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0x0UL) /*!< Packet received with CRC error */
12423 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (0x1UL) /*!< Packet received with CRC ok */
12424 
12425 /* Register: RADIO_RXMATCH */
12426 /* Description: Received address */
12427 
12428 /* Bits 2..0 : Received address */
12429 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
12430 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
12431 
12432 /* Register: RADIO_RXCRC */
12433 /* Description: CRC field of previously received packet */
12434 
12435 /* Bits 23..0 : CRC field of previously received packet */
12436 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
12437 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
12438 
12439 /* Register: RADIO_DAI */
12440 /* Description: Device address match index */
12441 
12442 /* Bits 2..0 : Device address match index */
12443 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
12444 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
12445 
12446 /* Register: RADIO_PDUSTAT */
12447 /* Description: Payload status */
12448 
12449 /* Bits 2..1 : Status on what rate packet is received with in Long Range */
12450 #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */
12451 #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */
12452 #define RADIO_PDUSTAT_CISTAT_LR125kbit (0x0UL) /*!< Frame is received at 125kbps */
12453 #define RADIO_PDUSTAT_CISTAT_LR500kbit (0x1UL) /*!< Frame is received at 500kbps */
12454 
12455 /* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */
12456 #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */
12457 #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */
12458 #define RADIO_PDUSTAT_PDUSTAT_LessThan (0x0UL) /*!< Payload less than PCNF1.MAXLEN */
12459 #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (0x1UL) /*!< Payload greater than PCNF1.MAXLEN */
12460 
12461 /* Register: RADIO_PACKETPTR */
12462 /* Description: Packet pointer */
12463 
12464 /* Bits 31..0 : Packet pointer */
12465 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
12466 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
12467 
12468 /* Register: RADIO_FREQUENCY */
12469 /* Description: Frequency */
12470 
12471 /* Bit 8 : Channel map selection. */
12472 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
12473 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
12474 #define RADIO_FREQUENCY_MAP_Default (0x0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
12475 #define RADIO_FREQUENCY_MAP_Low (0x1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
12476 
12477 /* Bits 6..0 : Radio channel frequency */
12478 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
12479 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
12480 
12481 /* Register: RADIO_TXPOWER */
12482 /* Description: Output power */
12483 
12484 /* Bits 7..0 : RADIO output power */
12485 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
12486 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
12487 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
12488 #define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x02UL) /*!< +2 dBm */
12489 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
12490 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
12491 #define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x05UL) /*!< +5 dBm */
12492 #define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x06UL) /*!< +6 dBm */
12493 #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x07UL) /*!< +7 dBm */
12494 #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x08UL) /*!< +8 dBm */
12495 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
12496 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator -  -40 dBm */
12497 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
12498 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
12499 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
12500 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
12501 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
12502 
12503 /* Register: RADIO_MODE */
12504 /* Description: Data rate and modulation */
12505 
12506 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
12507 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
12508 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
12509 #define RADIO_MODE_MODE_Nrf_1Mbit (0x0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
12510 #define RADIO_MODE_MODE_Nrf_2Mbit (0x1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
12511 #define RADIO_MODE_MODE_Ble_1Mbit (0x3UL) /*!< 1 Mbit/s BLE */
12512 #define RADIO_MODE_MODE_Ble_2Mbit (0x4UL) /*!< 2 Mbit/s BLE */
12513 #define RADIO_MODE_MODE_Ble_LR125Kbit (0x5UL) /*!< Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
12514 #define RADIO_MODE_MODE_Ble_LR500Kbit (0x6UL) /*!< Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
12515 #define RADIO_MODE_MODE_Ieee802154_250Kbit (0xFUL) /*!< IEEE 802.15.4-2006 250 kbit/s */
12516 
12517 /* Register: RADIO_PCNF0 */
12518 /* Description: Packet configuration register 0 */
12519 
12520 /* Bits 30..29 : Length of TERM field in Long Range operation */
12521 #define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */
12522 #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */
12523 
12524 /* Bit 26 : Indicates if LENGTH field contains CRC or not */
12525 #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */
12526 #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */
12527 #define RADIO_PCNF0_CRCINC_Exclude (0x0UL) /*!< LENGTH does not contain CRC */
12528 #define RADIO_PCNF0_CRCINC_Include (0x1UL) /*!< LENGTH includes CRC */
12529 
12530 /* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */
12531 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
12532 #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
12533 #define RADIO_PCNF0_PLEN_8bit (0x0UL) /*!< 8-bit preamble */
12534 #define RADIO_PCNF0_PLEN_16bit (0x1UL) /*!< 16-bit preamble */
12535 #define RADIO_PCNF0_PLEN_32bitZero (0x2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
12536 #define RADIO_PCNF0_PLEN_LongRange (0x3UL) /*!< Preamble - used for BLE long range */
12537 
12538 /* Bits 23..22 : Length of code indicator - long range */
12539 #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */
12540 #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */
12541 
12542 /* Bit 20 : Include or exclude S1 field in RAM */
12543 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
12544 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
12545 #define RADIO_PCNF0_S1INCL_Automatic (0x0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
12546 #define RADIO_PCNF0_S1INCL_Include (0x1UL) /*!< Always include S1 field in RAM independent of S1LEN */
12547 
12548 /* Bits 19..16 : Length on air of S1 field in number of bits. */
12549 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
12550 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
12551 
12552 /* Bit 8 : Length on air of S0 field in number of bytes. */
12553 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
12554 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
12555 
12556 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */
12557 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
12558 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
12559 
12560 /* Register: RADIO_PCNF1 */
12561 /* Description: Packet configuration register 1 */
12562 
12563 /* Bit 25 : Enable or disable packet whitening */
12564 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
12565 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
12566 #define RADIO_PCNF1_WHITEEN_Disabled (0x0UL) /*!< Disable */
12567 #define RADIO_PCNF1_WHITEEN_Enabled (0x1UL) /*!< Enable */
12568 
12569 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
12570 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
12571 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
12572 #define RADIO_PCNF1_ENDIAN_Little (0x0UL) /*!< Least significant bit on air first */
12573 #define RADIO_PCNF1_ENDIAN_Big (0x1UL) /*!< Most significant bit on air first */
12574 
12575 /* Bits 18..16 : Base address length in number of bytes */
12576 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
12577 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
12578 
12579 /* Bits 15..8 : Static length in number of bytes */
12580 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
12581 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
12582 
12583 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
12584 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
12585 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
12586 
12587 /* Register: RADIO_BASE0 */
12588 /* Description: Base address 0 */
12589 
12590 /* Bits 31..0 : Base address 0 */
12591 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
12592 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
12593 
12594 /* Register: RADIO_BASE1 */
12595 /* Description: Base address 1 */
12596 
12597 /* Bits 31..0 : Base address 1 */
12598 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
12599 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
12600 
12601 /* Register: RADIO_PREFIX0 */
12602 /* Description: Prefixes bytes for logical addresses 0-3 */
12603 
12604 /* Bits 31..24 : Address prefix 3. */
12605 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
12606 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
12607 
12608 /* Bits 23..16 : Address prefix 2. */
12609 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
12610 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
12611 
12612 /* Bits 15..8 : Address prefix 1. */
12613 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
12614 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
12615 
12616 /* Bits 7..0 : Address prefix 0. */
12617 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
12618 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
12619 
12620 /* Register: RADIO_PREFIX1 */
12621 /* Description: Prefixes bytes for logical addresses 4-7 */
12622 
12623 /* Bits 31..24 : Address prefix 7. */
12624 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
12625 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
12626 
12627 /* Bits 23..16 : Address prefix 6. */
12628 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
12629 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
12630 
12631 /* Bits 15..8 : Address prefix 5. */
12632 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
12633 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
12634 
12635 /* Bits 7..0 : Address prefix 4. */
12636 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
12637 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
12638 
12639 /* Register: RADIO_TXADDRESS */
12640 /* Description: Transmit address select */
12641 
12642 /* Bits 2..0 : Transmit address select */
12643 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
12644 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
12645 
12646 /* Register: RADIO_RXADDRESSES */
12647 /* Description: Receive address select */
12648 
12649 /* Bit 7 : Enable or disable reception on logical address 7. */
12650 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
12651 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
12652 #define RADIO_RXADDRESSES_ADDR7_Disabled (0x0UL) /*!< Disable */
12653 #define RADIO_RXADDRESSES_ADDR7_Enabled (0x1UL) /*!< Enable */
12654 
12655 /* Bit 6 : Enable or disable reception on logical address 6. */
12656 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
12657 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
12658 #define RADIO_RXADDRESSES_ADDR6_Disabled (0x0UL) /*!< Disable */
12659 #define RADIO_RXADDRESSES_ADDR6_Enabled (0x1UL) /*!< Enable */
12660 
12661 /* Bit 5 : Enable or disable reception on logical address 5. */
12662 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
12663 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
12664 #define RADIO_RXADDRESSES_ADDR5_Disabled (0x0UL) /*!< Disable */
12665 #define RADIO_RXADDRESSES_ADDR5_Enabled (0x1UL) /*!< Enable */
12666 
12667 /* Bit 4 : Enable or disable reception on logical address 4. */
12668 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
12669 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
12670 #define RADIO_RXADDRESSES_ADDR4_Disabled (0x0UL) /*!< Disable */
12671 #define RADIO_RXADDRESSES_ADDR4_Enabled (0x1UL) /*!< Enable */
12672 
12673 /* Bit 3 : Enable or disable reception on logical address 3. */
12674 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
12675 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
12676 #define RADIO_RXADDRESSES_ADDR3_Disabled (0x0UL) /*!< Disable */
12677 #define RADIO_RXADDRESSES_ADDR3_Enabled (0x1UL) /*!< Enable */
12678 
12679 /* Bit 2 : Enable or disable reception on logical address 2. */
12680 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
12681 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
12682 #define RADIO_RXADDRESSES_ADDR2_Disabled (0x0UL) /*!< Disable */
12683 #define RADIO_RXADDRESSES_ADDR2_Enabled (0x1UL) /*!< Enable */
12684 
12685 /* Bit 1 : Enable or disable reception on logical address 1. */
12686 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
12687 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
12688 #define RADIO_RXADDRESSES_ADDR1_Disabled (0x0UL) /*!< Disable */
12689 #define RADIO_RXADDRESSES_ADDR1_Enabled (0x1UL) /*!< Enable */
12690 
12691 /* Bit 0 : Enable or disable reception on logical address 0. */
12692 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
12693 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
12694 #define RADIO_RXADDRESSES_ADDR0_Disabled (0x0UL) /*!< Disable */
12695 #define RADIO_RXADDRESSES_ADDR0_Enabled (0x1UL) /*!< Enable */
12696 
12697 /* Register: RADIO_CRCCNF */
12698 /* Description: CRC configuration */
12699 
12700 /* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */
12701 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
12702 #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
12703 #define RADIO_CRCCNF_SKIPADDR_Include (0x0UL) /*!< CRC calculation includes address field */
12704 #define RADIO_CRCCNF_SKIPADDR_Skip (0x1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
12705 #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (0x2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */
12706 
12707 /* Bits 1..0 : CRC length in number of bytes. */
12708 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
12709 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
12710 #define RADIO_CRCCNF_LEN_Disabled (0x0UL) /*!< CRC length is zero and CRC calculation is disabled */
12711 #define RADIO_CRCCNF_LEN_One (0x1UL) /*!< CRC length is one byte and CRC calculation is enabled */
12712 #define RADIO_CRCCNF_LEN_Two (0x2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
12713 #define RADIO_CRCCNF_LEN_Three (0x3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
12714 
12715 /* Register: RADIO_CRCPOLY */
12716 /* Description: CRC polynomial */
12717 
12718 /* Bits 23..0 : CRC polynomial */
12719 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
12720 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
12721 
12722 /* Register: RADIO_CRCINIT */
12723 /* Description: CRC initial value */
12724 
12725 /* Bits 23..0 : CRC initial value */
12726 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
12727 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
12728 
12729 /* Register: RADIO_TIFS */
12730 /* Description: Interframe spacing in us */
12731 
12732 /* Bits 9..0 : Interframe spacing in us */
12733 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
12734 #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
12735 
12736 /* Register: RADIO_RSSISAMPLE */
12737 /* Description: RSSI sample */
12738 
12739 /* Bits 6..0 : RSSI sample */
12740 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
12741 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
12742 
12743 /* Register: RADIO_STATE */
12744 /* Description: Current radio state */
12745 
12746 /* Bits 3..0 : Current radio state */
12747 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
12748 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
12749 #define RADIO_STATE_STATE_Disabled (0x0UL) /*!< RADIO is in the Disabled state */
12750 #define RADIO_STATE_STATE_RxRu (0x1UL) /*!< RADIO is in the RXRU state */
12751 #define RADIO_STATE_STATE_RxIdle (0x2UL) /*!< RADIO is in the RXIDLE state */
12752 #define RADIO_STATE_STATE_Rx (0x3UL) /*!< RADIO is in the RX state */
12753 #define RADIO_STATE_STATE_RxDisable (0x4UL) /*!< RADIO is in the RXDISABLED state */
12754 #define RADIO_STATE_STATE_TxRu (0x9UL) /*!< RADIO is in the TXRU state */
12755 #define RADIO_STATE_STATE_TxIdle (0xAUL) /*!< RADIO is in the TXIDLE state */
12756 #define RADIO_STATE_STATE_Tx (0xBUL) /*!< RADIO is in the TX state */
12757 #define RADIO_STATE_STATE_TxDisable (0xCUL) /*!< RADIO is in the TXDISABLED state */
12758 
12759 /* Register: RADIO_DATAWHITEIV */
12760 /* Description: Data whitening initial value */
12761 
12762 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
12763 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
12764 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
12765 
12766 /* Register: RADIO_BCC */
12767 /* Description: Bit counter compare */
12768 
12769 /* Bits 31..0 : Bit counter compare */
12770 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
12771 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
12772 
12773 /* Register: RADIO_DAB */
12774 /* Description: Description collection: Device address base segment n */
12775 
12776 /* Bits 31..0 : Device address base segment n */
12777 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
12778 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
12779 
12780 /* Register: RADIO_DAP */
12781 /* Description: Description collection: Device address prefix n */
12782 
12783 /* Bits 15..0 : Device address prefix n */
12784 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
12785 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
12786 
12787 /* Register: RADIO_DACNF */
12788 /* Description: Device address match configuration */
12789 
12790 /* Bit 15 : TxAdd for device address 7 */
12791 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
12792 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
12793 
12794 /* Bit 14 : TxAdd for device address 6 */
12795 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
12796 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
12797 
12798 /* Bit 13 : TxAdd for device address 5 */
12799 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
12800 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
12801 
12802 /* Bit 12 : TxAdd for device address 4 */
12803 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
12804 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
12805 
12806 /* Bit 11 : TxAdd for device address 3 */
12807 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
12808 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
12809 
12810 /* Bit 10 : TxAdd for device address 2 */
12811 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
12812 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
12813 
12814 /* Bit 9 : TxAdd for device address 1 */
12815 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
12816 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
12817 
12818 /* Bit 8 : TxAdd for device address 0 */
12819 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
12820 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
12821 
12822 /* Bit 7 : Enable or disable device address matching using device address 7 */
12823 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
12824 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
12825 #define RADIO_DACNF_ENA7_Disabled (0x0UL) /*!< Disabled */
12826 #define RADIO_DACNF_ENA7_Enabled (0x1UL) /*!< Enabled */
12827 
12828 /* Bit 6 : Enable or disable device address matching using device address 6 */
12829 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
12830 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
12831 #define RADIO_DACNF_ENA6_Disabled (0x0UL) /*!< Disabled */
12832 #define RADIO_DACNF_ENA6_Enabled (0x1UL) /*!< Enabled */
12833 
12834 /* Bit 5 : Enable or disable device address matching using device address 5 */
12835 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
12836 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
12837 #define RADIO_DACNF_ENA5_Disabled (0x0UL) /*!< Disabled */
12838 #define RADIO_DACNF_ENA5_Enabled (0x1UL) /*!< Enabled */
12839 
12840 /* Bit 4 : Enable or disable device address matching using device address 4 */
12841 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
12842 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
12843 #define RADIO_DACNF_ENA4_Disabled (0x0UL) /*!< Disabled */
12844 #define RADIO_DACNF_ENA4_Enabled (0x1UL) /*!< Enabled */
12845 
12846 /* Bit 3 : Enable or disable device address matching using device address 3 */
12847 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
12848 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
12849 #define RADIO_DACNF_ENA3_Disabled (0x0UL) /*!< Disabled */
12850 #define RADIO_DACNF_ENA3_Enabled (0x1UL) /*!< Enabled */
12851 
12852 /* Bit 2 : Enable or disable device address matching using device address 2 */
12853 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
12854 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
12855 #define RADIO_DACNF_ENA2_Disabled (0x0UL) /*!< Disabled */
12856 #define RADIO_DACNF_ENA2_Enabled (0x1UL) /*!< Enabled */
12857 
12858 /* Bit 1 : Enable or disable device address matching using device address 1 */
12859 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
12860 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
12861 #define RADIO_DACNF_ENA1_Disabled (0x0UL) /*!< Disabled */
12862 #define RADIO_DACNF_ENA1_Enabled (0x1UL) /*!< Enabled */
12863 
12864 /* Bit 0 : Enable or disable device address matching using device address 0 */
12865 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
12866 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
12867 #define RADIO_DACNF_ENA0_Disabled (0x0UL) /*!< Disabled */
12868 #define RADIO_DACNF_ENA0_Enabled (0x1UL) /*!< Enabled */
12869 
12870 /* Register: RADIO_MHRMATCHCONF */
12871 /* Description: Search pattern configuration */
12872 
12873 /* Bits 31..0 : Search pattern configuration */
12874 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */
12875 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */
12876 
12877 /* Register: RADIO_MHRMATCHMAS */
12878 /* Description: Pattern mask */
12879 
12880 /* Bits 31..0 : Pattern mask */
12881 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */
12882 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */
12883 
12884 /* Register: RADIO_MODECNF0 */
12885 /* Description: Radio mode configuration register 0 */
12886 
12887 /* Bits 9..8 : Default TX value */
12888 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
12889 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
12890 #define RADIO_MODECNF0_DTX_B1 (0x0UL) /*!< Transmit '1' */
12891 #define RADIO_MODECNF0_DTX_B0 (0x1UL) /*!< Transmit '0' */
12892 #define RADIO_MODECNF0_DTX_Center (0x2UL) /*!< Transmit center frequency */
12893 
12894 /* Bit 0 : Radio ramp-up time */
12895 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
12896 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
12897 #define RADIO_MODECNF0_RU_Default (0x0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */
12898 #define RADIO_MODECNF0_RU_Fast (0x1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */
12899 
12900 /* Register: RADIO_SFD */
12901 /* Description: IEEE 802.15.4 start of frame delimiter */
12902 
12903 /* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */
12904 #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */
12905 #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */
12906 
12907 /* Register: RADIO_EDCNT */
12908 /* Description: IEEE 802.15.4 energy detect loop count */
12909 
12910 /* Bits 20..0 : IEEE 802.15.4 energy detect loop count */
12911 #define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */
12912 #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */
12913 
12914 /* Register: RADIO_EDSAMPLE */
12915 /* Description: IEEE 802.15.4 energy detect level */
12916 
12917 /* Bits 7..0 : IEEE 802.15.4 energy detect level */
12918 #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */
12919 #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */
12920 
12921 /* Register: RADIO_CCACTRL */
12922 /* Description: IEEE 802.15.4 clear channel assessment control */
12923 
12924 /* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */
12925 #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */
12926 #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */
12927 
12928 /* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */
12929 #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */
12930 #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */
12931 
12932 /* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */
12933 #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */
12934 #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */
12935 
12936 /* Bits 2..0 : CCA mode of operation */
12937 #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */
12938 #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */
12939 #define RADIO_CCACTRL_CCAMODE_EdMode (0x0UL) /*!< Energy above threshold */
12940 #define RADIO_CCACTRL_CCAMODE_CarrierMode (0x1UL) /*!< Carrier seen */
12941 #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (0x2UL) /*!< Energy above threshold AND carrier seen */
12942 #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (0x3UL) /*!< Energy above threshold OR carrier seen */
12943 #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (0x4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
12944 
12945 /* Register: RADIO_POWER */
12946 /* Description: Peripheral power control */
12947 
12948 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
12949 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
12950 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
12951 #define RADIO_POWER_POWER_Disabled (0x0UL) /*!< Peripheral is powered off */
12952 #define RADIO_POWER_POWER_Enabled (0x1UL) /*!< Peripheral is powered on */
12953 
12954 
12955 /* Peripheral: RNG */
12956 /* Description: Random Number Generator */
12957 
12958 /* Register: RNG_TASKS_START */
12959 /* Description: Task starting the random number generator */
12960 
12961 /* Bit 0 : Task starting the random number generator */
12962 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
12963 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
12964 #define RNG_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
12965 
12966 /* Register: RNG_TASKS_STOP */
12967 /* Description: Task stopping the random number generator */
12968 
12969 /* Bit 0 : Task stopping the random number generator */
12970 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12971 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12972 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
12973 
12974 /* Register: RNG_EVENTS_VALRDY */
12975 /* Description: Event being generated for every new random number written to the VALUE register */
12976 
12977 /* Bit 0 : Event being generated for every new random number written to the VALUE register */
12978 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
12979 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
12980 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0x0UL) /*!< Event not generated */
12981 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (0x1UL) /*!< Event generated */
12982 
12983 /* Register: RNG_SHORTS */
12984 /* Description: Shortcuts between local events and tasks */
12985 
12986 /* Bit 0 : Shortcut between event VALRDY and task STOP */
12987 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
12988 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
12989 #define RNG_SHORTS_VALRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
12990 #define RNG_SHORTS_VALRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */
12991 
12992 /* Register: RNG_INTENSET */
12993 /* Description: Enable interrupt */
12994 
12995 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */
12996 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
12997 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
12998 #define RNG_INTENSET_VALRDY_Disabled (0x0UL) /*!< Read: Disabled */
12999 #define RNG_INTENSET_VALRDY_Enabled (0x1UL) /*!< Read: Enabled */
13000 #define RNG_INTENSET_VALRDY_Set (0x1UL) /*!< Enable */
13001 
13002 /* Register: RNG_INTENCLR */
13003 /* Description: Disable interrupt */
13004 
13005 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */
13006 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
13007 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
13008 #define RNG_INTENCLR_VALRDY_Disabled (0x0UL) /*!< Read: Disabled */
13009 #define RNG_INTENCLR_VALRDY_Enabled (0x1UL) /*!< Read: Enabled */
13010 #define RNG_INTENCLR_VALRDY_Clear (0x1UL) /*!< Disable */
13011 
13012 /* Register: RNG_CONFIG */
13013 /* Description: Configuration register */
13014 
13015 /* Bit 0 : Bias correction */
13016 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
13017 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
13018 #define RNG_CONFIG_DERCEN_Disabled (0x0UL) /*!< Disabled */
13019 #define RNG_CONFIG_DERCEN_Enabled (0x1UL) /*!< Enabled */
13020 
13021 /* Register: RNG_VALUE */
13022 /* Description: Output random number */
13023 
13024 /* Bits 7..0 : Generated random number */
13025 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
13026 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
13027 
13028 
13029 /* Peripheral: RTC */
13030 /* Description: Real time counter 0 */
13031 
13032 /* Register: RTC_TASKS_START */
13033 /* Description: Start RTC COUNTER */
13034 
13035 /* Bit 0 : Start RTC COUNTER */
13036 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
13037 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
13038 #define RTC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
13039 
13040 /* Register: RTC_TASKS_STOP */
13041 /* Description: Stop RTC COUNTER */
13042 
13043 /* Bit 0 : Stop RTC COUNTER */
13044 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
13045 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
13046 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
13047 
13048 /* Register: RTC_TASKS_CLEAR */
13049 /* Description: Clear RTC COUNTER */
13050 
13051 /* Bit 0 : Clear RTC COUNTER */
13052 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
13053 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
13054 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */
13055 
13056 /* Register: RTC_TASKS_TRIGOVRFLW */
13057 /* Description: Set COUNTER to 0xFFFFF0 */
13058 
13059 /* Bit 0 : Set COUNTER to 0xFFFFF0 */
13060 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
13061 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
13062 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (0x1UL) /*!< Trigger task */
13063 
13064 /* Register: RTC_EVENTS_TICK */
13065 /* Description: Event on COUNTER increment */
13066 
13067 /* Bit 0 : Event on COUNTER increment */
13068 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
13069 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
13070 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0x0UL) /*!< Event not generated */
13071 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (0x1UL) /*!< Event generated */
13072 
13073 /* Register: RTC_EVENTS_OVRFLW */
13074 /* Description: Event on COUNTER overflow */
13075 
13076 /* Bit 0 : Event on COUNTER overflow */
13077 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
13078 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
13079 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0x0UL) /*!< Event not generated */
13080 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (0x1UL) /*!< Event generated */
13081 
13082 /* Register: RTC_EVENTS_COMPARE */
13083 /* Description: Description collection: Compare event on CC[n] match */
13084 
13085 /* Bit 0 : Compare event on CC[n] match */
13086 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
13087 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
13088 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */
13089 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */
13090 
13091 /* Register: RTC_INTENSET */
13092 /* Description: Enable interrupt */
13093 
13094 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
13095 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
13096 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
13097 #define RTC_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
13098 #define RTC_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
13099 #define RTC_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */
13100 
13101 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
13102 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
13103 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
13104 #define RTC_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
13105 #define RTC_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
13106 #define RTC_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */
13107 
13108 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
13109 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
13110 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
13111 #define RTC_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
13112 #define RTC_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
13113 #define RTC_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */
13114 
13115 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
13116 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13117 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13118 #define RTC_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
13119 #define RTC_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
13120 #define RTC_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */
13121 
13122 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
13123 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
13124 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
13125 #define RTC_INTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
13126 #define RTC_INTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
13127 #define RTC_INTENSET_OVRFLW_Set (0x1UL) /*!< Enable */
13128 
13129 /* Bit 0 : Write '1' to enable interrupt for event TICK */
13130 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
13131 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
13132 #define RTC_INTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */
13133 #define RTC_INTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */
13134 #define RTC_INTENSET_TICK_Set (0x1UL) /*!< Enable */
13135 
13136 /* Register: RTC_INTENCLR */
13137 /* Description: Disable interrupt */
13138 
13139 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
13140 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
13141 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
13142 #define RTC_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
13143 #define RTC_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
13144 #define RTC_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */
13145 
13146 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
13147 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
13148 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
13149 #define RTC_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
13150 #define RTC_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
13151 #define RTC_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */
13152 
13153 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
13154 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
13155 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
13156 #define RTC_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
13157 #define RTC_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
13158 #define RTC_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */
13159 
13160 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
13161 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13162 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13163 #define RTC_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
13164 #define RTC_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
13165 #define RTC_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */
13166 
13167 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
13168 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
13169 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
13170 #define RTC_INTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
13171 #define RTC_INTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
13172 #define RTC_INTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */
13173 
13174 /* Bit 0 : Write '1' to disable interrupt for event TICK */
13175 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
13176 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
13177 #define RTC_INTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */
13178 #define RTC_INTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */
13179 #define RTC_INTENCLR_TICK_Clear (0x1UL) /*!< Disable */
13180 
13181 /* Register: RTC_EVTEN */
13182 /* Description: Enable or disable event routing */
13183 
13184 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
13185 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
13186 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
13187 #define RTC_EVTEN_COMPARE3_Disabled (0x0UL) /*!< Disable */
13188 #define RTC_EVTEN_COMPARE3_Enabled (0x1UL) /*!< Enable */
13189 
13190 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
13191 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
13192 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
13193 #define RTC_EVTEN_COMPARE2_Disabled (0x0UL) /*!< Disable */
13194 #define RTC_EVTEN_COMPARE2_Enabled (0x1UL) /*!< Enable */
13195 
13196 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
13197 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
13198 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
13199 #define RTC_EVTEN_COMPARE1_Disabled (0x0UL) /*!< Disable */
13200 #define RTC_EVTEN_COMPARE1_Enabled (0x1UL) /*!< Enable */
13201 
13202 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
13203 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13204 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13205 #define RTC_EVTEN_COMPARE0_Disabled (0x0UL) /*!< Disable */
13206 #define RTC_EVTEN_COMPARE0_Enabled (0x1UL) /*!< Enable */
13207 
13208 /* Bit 1 : Enable or disable event routing for event OVRFLW */
13209 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
13210 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
13211 #define RTC_EVTEN_OVRFLW_Disabled (0x0UL) /*!< Disable */
13212 #define RTC_EVTEN_OVRFLW_Enabled (0x1UL) /*!< Enable */
13213 
13214 /* Bit 0 : Enable or disable event routing for event TICK */
13215 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
13216 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
13217 #define RTC_EVTEN_TICK_Disabled (0x0UL) /*!< Disable */
13218 #define RTC_EVTEN_TICK_Enabled (0x1UL) /*!< Enable */
13219 
13220 /* Register: RTC_EVTENSET */
13221 /* Description: Enable event routing */
13222 
13223 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
13224 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
13225 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
13226 #define RTC_EVTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
13227 #define RTC_EVTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
13228 #define RTC_EVTENSET_COMPARE3_Set (0x1UL) /*!< Enable */
13229 
13230 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
13231 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
13232 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
13233 #define RTC_EVTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
13234 #define RTC_EVTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
13235 #define RTC_EVTENSET_COMPARE2_Set (0x1UL) /*!< Enable */
13236 
13237 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
13238 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
13239 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
13240 #define RTC_EVTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
13241 #define RTC_EVTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
13242 #define RTC_EVTENSET_COMPARE1_Set (0x1UL) /*!< Enable */
13243 
13244 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
13245 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13246 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13247 #define RTC_EVTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
13248 #define RTC_EVTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
13249 #define RTC_EVTENSET_COMPARE0_Set (0x1UL) /*!< Enable */
13250 
13251 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
13252 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
13253 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
13254 #define RTC_EVTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
13255 #define RTC_EVTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
13256 #define RTC_EVTENSET_OVRFLW_Set (0x1UL) /*!< Enable */
13257 
13258 /* Bit 0 : Write '1' to enable event routing for event TICK */
13259 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
13260 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
13261 #define RTC_EVTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */
13262 #define RTC_EVTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */
13263 #define RTC_EVTENSET_TICK_Set (0x1UL) /*!< Enable */
13264 
13265 /* Register: RTC_EVTENCLR */
13266 /* Description: Disable event routing */
13267 
13268 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
13269 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
13270 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
13271 #define RTC_EVTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
13272 #define RTC_EVTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
13273 #define RTC_EVTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */
13274 
13275 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
13276 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
13277 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
13278 #define RTC_EVTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
13279 #define RTC_EVTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
13280 #define RTC_EVTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */
13281 
13282 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
13283 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
13284 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
13285 #define RTC_EVTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
13286 #define RTC_EVTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
13287 #define RTC_EVTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */
13288 
13289 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
13290 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13291 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13292 #define RTC_EVTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
13293 #define RTC_EVTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
13294 #define RTC_EVTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */
13295 
13296 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
13297 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
13298 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
13299 #define RTC_EVTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
13300 #define RTC_EVTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
13301 #define RTC_EVTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */
13302 
13303 /* Bit 0 : Write '1' to disable event routing for event TICK */
13304 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
13305 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
13306 #define RTC_EVTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */
13307 #define RTC_EVTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */
13308 #define RTC_EVTENCLR_TICK_Clear (0x1UL) /*!< Disable */
13309 
13310 /* Register: RTC_COUNTER */
13311 /* Description: Current COUNTER value */
13312 
13313 /* Bits 23..0 : Counter value */
13314 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
13315 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
13316 
13317 /* Register: RTC_PRESCALER */
13318 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */
13319 
13320 /* Bits 11..0 : Prescaler value */
13321 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
13322 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
13323 
13324 /* Register: RTC_CC */
13325 /* Description: Description collection: Compare register n */
13326 
13327 /* Bits 23..0 : Compare value */
13328 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
13329 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
13330 
13331 
13332 /* Peripheral: SAADC */
13333 /* Description: Successive approximation register (SAR) analog-to-digital converter */
13334 
13335 /* Register: SAADC_TASKS_START */
13336 /* Description: Starts the SAADC and prepares the result buffer in RAM */
13337 
13338 /* Bit 0 : Starts the SAADC and prepares the result buffer in RAM */
13339 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
13340 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
13341 #define SAADC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
13342 
13343 /* Register: SAADC_TASKS_SAMPLE */
13344 /* Description: Takes one SAADC sample */
13345 
13346 /* Bit 0 : Takes one SAADC sample */
13347 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
13348 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
13349 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */
13350 
13351 /* Register: SAADC_TASKS_STOP */
13352 /* Description: Stops the SAADC and terminates all on-going conversions */
13353 
13354 /* Bit 0 : Stops the SAADC and terminates all on-going conversions */
13355 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
13356 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
13357 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
13358 
13359 /* Register: SAADC_TASKS_CALIBRATEOFFSET */
13360 /* Description: Starts offset auto-calibration */
13361 
13362 /* Bit 0 : Starts offset auto-calibration */
13363 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
13364 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
13365 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (0x1UL) /*!< Trigger task */
13366 
13367 /* Register: SAADC_EVENTS_STARTED */
13368 /* Description: The SAADC has started */
13369 
13370 /* Bit 0 : The SAADC has started */
13371 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
13372 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
13373 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
13374 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */
13375 
13376 /* Register: SAADC_EVENTS_END */
13377 /* Description: The SAADC has filled up the result buffer */
13378 
13379 /* Bit 0 : The SAADC has filled up the result buffer */
13380 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
13381 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
13382 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
13383 #define SAADC_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */
13384 
13385 /* Register: SAADC_EVENTS_DONE */
13386 /* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */
13387 
13388 /* Bit 0 : A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */
13389 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
13390 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
13391 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */
13392 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */
13393 
13394 /* Register: SAADC_EVENTS_RESULTDONE */
13395 /* Description: Result ready for transfer to RAM */
13396 
13397 /* Bit 0 : Result ready for transfer to RAM */
13398 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
13399 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
13400 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0x0UL) /*!< Event not generated */
13401 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (0x1UL) /*!< Event generated */
13402 
13403 /* Register: SAADC_EVENTS_CALIBRATEDONE */
13404 /* Description: Calibration is complete */
13405 
13406 /* Bit 0 : Calibration is complete */
13407 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
13408 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
13409 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0x0UL) /*!< Event not generated */
13410 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (0x1UL) /*!< Event generated */
13411 
13412 /* Register: SAADC_EVENTS_STOPPED */
13413 /* Description: The SAADC has stopped */
13414 
13415 /* Bit 0 : The SAADC has stopped */
13416 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
13417 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
13418 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
13419 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
13420 
13421 /* Register: SAADC_EVENTS_CH_LIMITH */
13422 /* Description: Description cluster: Last result is equal or above CH[n].LIMIT.HIGH */
13423 
13424 /* Bit 0 : Last result is equal or above CH[n].LIMIT.HIGH */
13425 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
13426 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
13427 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0x0UL) /*!< Event not generated */
13428 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (0x1UL) /*!< Event generated */
13429 
13430 /* Register: SAADC_EVENTS_CH_LIMITL */
13431 /* Description: Description cluster: Last result is equal or below CH[n].LIMIT.LOW */
13432 
13433 /* Bit 0 : Last result is equal or below CH[n].LIMIT.LOW */
13434 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
13435 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
13436 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0x0UL) /*!< Event not generated */
13437 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (0x1UL) /*!< Event generated */
13438 
13439 /* Register: SAADC_INTEN */
13440 /* Description: Enable or disable interrupt */
13441 
13442 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
13443 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
13444 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
13445 #define SAADC_INTEN_CH7LIMITL_Disabled (0x0UL) /*!< Disable */
13446 #define SAADC_INTEN_CH7LIMITL_Enabled (0x1UL) /*!< Enable */
13447 
13448 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
13449 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
13450 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
13451 #define SAADC_INTEN_CH7LIMITH_Disabled (0x0UL) /*!< Disable */
13452 #define SAADC_INTEN_CH7LIMITH_Enabled (0x1UL) /*!< Enable */
13453 
13454 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
13455 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
13456 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
13457 #define SAADC_INTEN_CH6LIMITL_Disabled (0x0UL) /*!< Disable */
13458 #define SAADC_INTEN_CH6LIMITL_Enabled (0x1UL) /*!< Enable */
13459 
13460 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
13461 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
13462 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
13463 #define SAADC_INTEN_CH6LIMITH_Disabled (0x0UL) /*!< Disable */
13464 #define SAADC_INTEN_CH6LIMITH_Enabled (0x1UL) /*!< Enable */
13465 
13466 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
13467 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
13468 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
13469 #define SAADC_INTEN_CH5LIMITL_Disabled (0x0UL) /*!< Disable */
13470 #define SAADC_INTEN_CH5LIMITL_Enabled (0x1UL) /*!< Enable */
13471 
13472 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
13473 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
13474 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
13475 #define SAADC_INTEN_CH5LIMITH_Disabled (0x0UL) /*!< Disable */
13476 #define SAADC_INTEN_CH5LIMITH_Enabled (0x1UL) /*!< Enable */
13477 
13478 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
13479 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
13480 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
13481 #define SAADC_INTEN_CH4LIMITL_Disabled (0x0UL) /*!< Disable */
13482 #define SAADC_INTEN_CH4LIMITL_Enabled (0x1UL) /*!< Enable */
13483 
13484 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
13485 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
13486 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
13487 #define SAADC_INTEN_CH4LIMITH_Disabled (0x0UL) /*!< Disable */
13488 #define SAADC_INTEN_CH4LIMITH_Enabled (0x1UL) /*!< Enable */
13489 
13490 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
13491 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
13492 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
13493 #define SAADC_INTEN_CH3LIMITL_Disabled (0x0UL) /*!< Disable */
13494 #define SAADC_INTEN_CH3LIMITL_Enabled (0x1UL) /*!< Enable */
13495 
13496 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
13497 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
13498 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
13499 #define SAADC_INTEN_CH3LIMITH_Disabled (0x0UL) /*!< Disable */
13500 #define SAADC_INTEN_CH3LIMITH_Enabled (0x1UL) /*!< Enable */
13501 
13502 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
13503 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
13504 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
13505 #define SAADC_INTEN_CH2LIMITL_Disabled (0x0UL) /*!< Disable */
13506 #define SAADC_INTEN_CH2LIMITL_Enabled (0x1UL) /*!< Enable */
13507 
13508 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
13509 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
13510 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
13511 #define SAADC_INTEN_CH2LIMITH_Disabled (0x0UL) /*!< Disable */
13512 #define SAADC_INTEN_CH2LIMITH_Enabled (0x1UL) /*!< Enable */
13513 
13514 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
13515 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
13516 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
13517 #define SAADC_INTEN_CH1LIMITL_Disabled (0x0UL) /*!< Disable */
13518 #define SAADC_INTEN_CH1LIMITL_Enabled (0x1UL) /*!< Enable */
13519 
13520 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
13521 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
13522 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
13523 #define SAADC_INTEN_CH1LIMITH_Disabled (0x0UL) /*!< Disable */
13524 #define SAADC_INTEN_CH1LIMITH_Enabled (0x1UL) /*!< Enable */
13525 
13526 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
13527 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
13528 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
13529 #define SAADC_INTEN_CH0LIMITL_Disabled (0x0UL) /*!< Disable */
13530 #define SAADC_INTEN_CH0LIMITL_Enabled (0x1UL) /*!< Enable */
13531 
13532 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
13533 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
13534 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
13535 #define SAADC_INTEN_CH0LIMITH_Disabled (0x0UL) /*!< Disable */
13536 #define SAADC_INTEN_CH0LIMITH_Enabled (0x1UL) /*!< Enable */
13537 
13538 /* Bit 5 : Enable or disable interrupt for event STOPPED */
13539 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
13540 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13541 #define SAADC_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
13542 #define SAADC_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
13543 
13544 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
13545 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
13546 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
13547 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0x0UL) /*!< Disable */
13548 #define SAADC_INTEN_CALIBRATEDONE_Enabled (0x1UL) /*!< Enable */
13549 
13550 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
13551 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
13552 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
13553 #define SAADC_INTEN_RESULTDONE_Disabled (0x0UL) /*!< Disable */
13554 #define SAADC_INTEN_RESULTDONE_Enabled (0x1UL) /*!< Enable */
13555 
13556 /* Bit 2 : Enable or disable interrupt for event DONE */
13557 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
13558 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
13559 #define SAADC_INTEN_DONE_Disabled (0x0UL) /*!< Disable */
13560 #define SAADC_INTEN_DONE_Enabled (0x1UL) /*!< Enable */
13561 
13562 /* Bit 1 : Enable or disable interrupt for event END */
13563 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
13564 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
13565 #define SAADC_INTEN_END_Disabled (0x0UL) /*!< Disable */
13566 #define SAADC_INTEN_END_Enabled (0x1UL) /*!< Enable */
13567 
13568 /* Bit 0 : Enable or disable interrupt for event STARTED */
13569 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
13570 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
13571 #define SAADC_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */
13572 #define SAADC_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */
13573 
13574 /* Register: SAADC_INTENSET */
13575 /* Description: Enable interrupt */
13576 
13577 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
13578 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
13579 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
13580 #define SAADC_INTENSET_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13581 #define SAADC_INTENSET_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13582 #define SAADC_INTENSET_CH7LIMITL_Set (0x1UL) /*!< Enable */
13583 
13584 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
13585 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
13586 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
13587 #define SAADC_INTENSET_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13588 #define SAADC_INTENSET_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13589 #define SAADC_INTENSET_CH7LIMITH_Set (0x1UL) /*!< Enable */
13590 
13591 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
13592 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
13593 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
13594 #define SAADC_INTENSET_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13595 #define SAADC_INTENSET_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13596 #define SAADC_INTENSET_CH6LIMITL_Set (0x1UL) /*!< Enable */
13597 
13598 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
13599 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
13600 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
13601 #define SAADC_INTENSET_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13602 #define SAADC_INTENSET_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13603 #define SAADC_INTENSET_CH6LIMITH_Set (0x1UL) /*!< Enable */
13604 
13605 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
13606 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
13607 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
13608 #define SAADC_INTENSET_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13609 #define SAADC_INTENSET_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13610 #define SAADC_INTENSET_CH5LIMITL_Set (0x1UL) /*!< Enable */
13611 
13612 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
13613 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
13614 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
13615 #define SAADC_INTENSET_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13616 #define SAADC_INTENSET_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13617 #define SAADC_INTENSET_CH5LIMITH_Set (0x1UL) /*!< Enable */
13618 
13619 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
13620 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
13621 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
13622 #define SAADC_INTENSET_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13623 #define SAADC_INTENSET_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13624 #define SAADC_INTENSET_CH4LIMITL_Set (0x1UL) /*!< Enable */
13625 
13626 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
13627 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
13628 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
13629 #define SAADC_INTENSET_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13630 #define SAADC_INTENSET_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13631 #define SAADC_INTENSET_CH4LIMITH_Set (0x1UL) /*!< Enable */
13632 
13633 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
13634 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
13635 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
13636 #define SAADC_INTENSET_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13637 #define SAADC_INTENSET_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13638 #define SAADC_INTENSET_CH3LIMITL_Set (0x1UL) /*!< Enable */
13639 
13640 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
13641 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
13642 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
13643 #define SAADC_INTENSET_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13644 #define SAADC_INTENSET_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13645 #define SAADC_INTENSET_CH3LIMITH_Set (0x1UL) /*!< Enable */
13646 
13647 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
13648 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
13649 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
13650 #define SAADC_INTENSET_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13651 #define SAADC_INTENSET_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13652 #define SAADC_INTENSET_CH2LIMITL_Set (0x1UL) /*!< Enable */
13653 
13654 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
13655 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
13656 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
13657 #define SAADC_INTENSET_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13658 #define SAADC_INTENSET_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13659 #define SAADC_INTENSET_CH2LIMITH_Set (0x1UL) /*!< Enable */
13660 
13661 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
13662 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
13663 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
13664 #define SAADC_INTENSET_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13665 #define SAADC_INTENSET_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13666 #define SAADC_INTENSET_CH1LIMITL_Set (0x1UL) /*!< Enable */
13667 
13668 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
13669 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
13670 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
13671 #define SAADC_INTENSET_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13672 #define SAADC_INTENSET_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13673 #define SAADC_INTENSET_CH1LIMITH_Set (0x1UL) /*!< Enable */
13674 
13675 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
13676 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
13677 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
13678 #define SAADC_INTENSET_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13679 #define SAADC_INTENSET_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13680 #define SAADC_INTENSET_CH0LIMITL_Set (0x1UL) /*!< Enable */
13681 
13682 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
13683 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
13684 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
13685 #define SAADC_INTENSET_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13686 #define SAADC_INTENSET_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13687 #define SAADC_INTENSET_CH0LIMITH_Set (0x1UL) /*!< Enable */
13688 
13689 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
13690 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
13691 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13692 #define SAADC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
13693 #define SAADC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
13694 #define SAADC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
13695 
13696 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
13697 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
13698 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
13699 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */
13700 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */
13701 #define SAADC_INTENSET_CALIBRATEDONE_Set (0x1UL) /*!< Enable */
13702 
13703 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
13704 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
13705 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
13706 #define SAADC_INTENSET_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */
13707 #define SAADC_INTENSET_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */
13708 #define SAADC_INTENSET_RESULTDONE_Set (0x1UL) /*!< Enable */
13709 
13710 /* Bit 2 : Write '1' to enable interrupt for event DONE */
13711 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
13712 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
13713 #define SAADC_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */
13714 #define SAADC_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */
13715 #define SAADC_INTENSET_DONE_Set (0x1UL) /*!< Enable */
13716 
13717 /* Bit 1 : Write '1' to enable interrupt for event END */
13718 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
13719 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
13720 #define SAADC_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
13721 #define SAADC_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
13722 #define SAADC_INTENSET_END_Set (0x1UL) /*!< Enable */
13723 
13724 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
13725 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
13726 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
13727 #define SAADC_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
13728 #define SAADC_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
13729 #define SAADC_INTENSET_STARTED_Set (0x1UL) /*!< Enable */
13730 
13731 /* Register: SAADC_INTENCLR */
13732 /* Description: Disable interrupt */
13733 
13734 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
13735 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
13736 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
13737 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13738 #define SAADC_INTENCLR_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13739 #define SAADC_INTENCLR_CH7LIMITL_Clear (0x1UL) /*!< Disable */
13740 
13741 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
13742 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
13743 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
13744 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13745 #define SAADC_INTENCLR_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13746 #define SAADC_INTENCLR_CH7LIMITH_Clear (0x1UL) /*!< Disable */
13747 
13748 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
13749 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
13750 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
13751 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13752 #define SAADC_INTENCLR_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13753 #define SAADC_INTENCLR_CH6LIMITL_Clear (0x1UL) /*!< Disable */
13754 
13755 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
13756 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
13757 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
13758 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13759 #define SAADC_INTENCLR_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13760 #define SAADC_INTENCLR_CH6LIMITH_Clear (0x1UL) /*!< Disable */
13761 
13762 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
13763 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
13764 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
13765 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13766 #define SAADC_INTENCLR_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13767 #define SAADC_INTENCLR_CH5LIMITL_Clear (0x1UL) /*!< Disable */
13768 
13769 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
13770 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
13771 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
13772 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13773 #define SAADC_INTENCLR_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13774 #define SAADC_INTENCLR_CH5LIMITH_Clear (0x1UL) /*!< Disable */
13775 
13776 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
13777 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
13778 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
13779 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13780 #define SAADC_INTENCLR_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13781 #define SAADC_INTENCLR_CH4LIMITL_Clear (0x1UL) /*!< Disable */
13782 
13783 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
13784 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
13785 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
13786 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13787 #define SAADC_INTENCLR_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13788 #define SAADC_INTENCLR_CH4LIMITH_Clear (0x1UL) /*!< Disable */
13789 
13790 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
13791 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
13792 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
13793 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13794 #define SAADC_INTENCLR_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13795 #define SAADC_INTENCLR_CH3LIMITL_Clear (0x1UL) /*!< Disable */
13796 
13797 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
13798 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
13799 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
13800 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13801 #define SAADC_INTENCLR_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13802 #define SAADC_INTENCLR_CH3LIMITH_Clear (0x1UL) /*!< Disable */
13803 
13804 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
13805 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
13806 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
13807 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13808 #define SAADC_INTENCLR_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13809 #define SAADC_INTENCLR_CH2LIMITL_Clear (0x1UL) /*!< Disable */
13810 
13811 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
13812 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
13813 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
13814 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13815 #define SAADC_INTENCLR_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13816 #define SAADC_INTENCLR_CH2LIMITH_Clear (0x1UL) /*!< Disable */
13817 
13818 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
13819 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
13820 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
13821 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13822 #define SAADC_INTENCLR_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13823 #define SAADC_INTENCLR_CH1LIMITL_Clear (0x1UL) /*!< Disable */
13824 
13825 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
13826 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
13827 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
13828 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13829 #define SAADC_INTENCLR_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13830 #define SAADC_INTENCLR_CH1LIMITH_Clear (0x1UL) /*!< Disable */
13831 
13832 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
13833 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
13834 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
13835 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
13836 #define SAADC_INTENCLR_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
13837 #define SAADC_INTENCLR_CH0LIMITL_Clear (0x1UL) /*!< Disable */
13838 
13839 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
13840 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
13841 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
13842 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
13843 #define SAADC_INTENCLR_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
13844 #define SAADC_INTENCLR_CH0LIMITH_Clear (0x1UL) /*!< Disable */
13845 
13846 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
13847 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
13848 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13849 #define SAADC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
13850 #define SAADC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
13851 #define SAADC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
13852 
13853 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
13854 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
13855 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
13856 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */
13857 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */
13858 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (0x1UL) /*!< Disable */
13859 
13860 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
13861 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
13862 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
13863 #define SAADC_INTENCLR_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */
13864 #define SAADC_INTENCLR_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */
13865 #define SAADC_INTENCLR_RESULTDONE_Clear (0x1UL) /*!< Disable */
13866 
13867 /* Bit 2 : Write '1' to disable interrupt for event DONE */
13868 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
13869 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
13870 #define SAADC_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */
13871 #define SAADC_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */
13872 #define SAADC_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */
13873 
13874 /* Bit 1 : Write '1' to disable interrupt for event END */
13875 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
13876 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
13877 #define SAADC_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
13878 #define SAADC_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
13879 #define SAADC_INTENCLR_END_Clear (0x1UL) /*!< Disable */
13880 
13881 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
13882 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
13883 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
13884 #define SAADC_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
13885 #define SAADC_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
13886 #define SAADC_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */
13887 
13888 /* Register: SAADC_STATUS */
13889 /* Description: Status */
13890 
13891 /* Bit 0 : Status */
13892 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
13893 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
13894 #define SAADC_STATUS_STATUS_Ready (0x0UL) /*!< SAADC is ready. No on-going conversions. */
13895 #define SAADC_STATUS_STATUS_Busy (0x1UL) /*!< SAADC is busy. Conversion in progress. */
13896 
13897 /* Register: SAADC_ENABLE */
13898 /* Description: Enable or disable SAADC */
13899 
13900 /* Bit 0 : Enable or disable SAADC */
13901 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13902 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13903 #define SAADC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SAADC */
13904 #define SAADC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable SAADC */
13905 
13906 /* Register: SAADC_CH_PSELP */
13907 /* Description: Description cluster: Input positive pin selection for CH[n] */
13908 
13909 /* Bits 4..0 : Analog positive input channel */
13910 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
13911 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
13912 #define SAADC_CH_PSELP_PSELP_NC (0x00UL) /*!< Not connected */
13913 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (0x01UL) /*!< AIN0 */
13914 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (0x02UL) /*!< AIN1 */
13915 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (0x03UL) /*!< AIN2 */
13916 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (0x04UL) /*!< AIN3 */
13917 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (0x05UL) /*!< AIN4 */
13918 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (0x06UL) /*!< AIN5 */
13919 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (0x07UL) /*!< AIN6 */
13920 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (0x08UL) /*!< AIN7 */
13921 #define SAADC_CH_PSELP_PSELP_VDD (0x09UL) /*!< VDD */
13922 #define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */
13923 
13924 /* Register: SAADC_CH_PSELN */
13925 /* Description: Description cluster: Input negative pin selection for CH[n] */
13926 
13927 /* Bits 4..0 : Analog negative input, enables differential channel */
13928 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
13929 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
13930 #define SAADC_CH_PSELN_PSELN_NC (0x00UL) /*!< Not connected */
13931 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (0x01UL) /*!< AIN0 */
13932 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (0x02UL) /*!< AIN1 */
13933 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (0x03UL) /*!< AIN2 */
13934 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (0x04UL) /*!< AIN3 */
13935 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (0x05UL) /*!< AIN4 */
13936 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (0x06UL) /*!< AIN5 */
13937 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (0x07UL) /*!< AIN6 */
13938 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (0x08UL) /*!< AIN7 */
13939 #define SAADC_CH_PSELN_PSELN_VDD (0x09UL) /*!< VDD */
13940 #define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */
13941 
13942 /* Register: SAADC_CH_CONFIG */
13943 /* Description: Description cluster: Input configuration for CH[n] */
13944 
13945 /* Bit 24 : Enable burst mode */
13946 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
13947 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
13948 #define SAADC_CH_CONFIG_BURST_Disabled (0x0UL) /*!< Burst mode is disabled (normal operation) */
13949 #define SAADC_CH_CONFIG_BURST_Enabled (0x1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
13950 
13951 /* Bit 20 : Enable differential mode */
13952 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
13953 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
13954 #define SAADC_CH_CONFIG_MODE_SE (0x0UL) /*!< Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND */
13955 #define SAADC_CH_CONFIG_MODE_Diff (0x1UL) /*!< Differential */
13956 
13957 /* Bits 18..16 : Acquisition time, the time the SAADC uses to sample the input voltage */
13958 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
13959 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
13960 #define SAADC_CH_CONFIG_TACQ_3us (0x0UL) /*!< 3 us */
13961 #define SAADC_CH_CONFIG_TACQ_5us (0x1UL) /*!< 5 us */
13962 #define SAADC_CH_CONFIG_TACQ_10us (0x2UL) /*!< 10 us */
13963 #define SAADC_CH_CONFIG_TACQ_15us (0x3UL) /*!< 15 us */
13964 #define SAADC_CH_CONFIG_TACQ_20us (0x4UL) /*!< 20 us */
13965 #define SAADC_CH_CONFIG_TACQ_40us (0x5UL) /*!< 40 us */
13966 
13967 /* Bit 12 : Reference control */
13968 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
13969 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
13970 #define SAADC_CH_CONFIG_REFSEL_Internal (0x0UL) /*!< Internal reference (0.6 V) */
13971 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (0x1UL) /*!< VDD/4 as reference */
13972 
13973 /* Bits 10..8 : Gain control */
13974 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
13975 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
13976 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0x0UL) /*!< 1/6 */
13977 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (0x1UL) /*!< 1/5 */
13978 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (0x2UL) /*!< 1/4 */
13979 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (0x3UL) /*!< 1/3 */
13980 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (0x4UL) /*!< 1/2 */
13981 #define SAADC_CH_CONFIG_GAIN_Gain1 (0x5UL) /*!< 1 */
13982 #define SAADC_CH_CONFIG_GAIN_Gain2 (0x6UL) /*!< 2 */
13983 #define SAADC_CH_CONFIG_GAIN_Gain4 (0x7UL) /*!< 4 */
13984 
13985 /* Bits 5..4 : Negative channel resistor control */
13986 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
13987 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
13988 #define SAADC_CH_CONFIG_RESN_Bypass (0x0UL) /*!< Bypass resistor ladder */
13989 #define SAADC_CH_CONFIG_RESN_Pulldown (0x1UL) /*!< Pull-down to GND */
13990 #define SAADC_CH_CONFIG_RESN_Pullup (0x2UL) /*!< Pull-up to VDD */
13991 #define SAADC_CH_CONFIG_RESN_VDD1_2 (0x3UL) /*!< Set input at VDD/2 */
13992 
13993 /* Bits 1..0 : Positive channel resistor control */
13994 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
13995 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
13996 #define SAADC_CH_CONFIG_RESP_Bypass (0x0UL) /*!< Bypass resistor ladder */
13997 #define SAADC_CH_CONFIG_RESP_Pulldown (0x1UL) /*!< Pull-down to GND */
13998 #define SAADC_CH_CONFIG_RESP_Pullup (0x2UL) /*!< Pull-up to VDD */
13999 #define SAADC_CH_CONFIG_RESP_VDD1_2 (0x3UL) /*!< Set input at VDD/2 */
14000 
14001 /* Register: SAADC_CH_LIMIT */
14002 /* Description: Description cluster: High/low limits for event monitoring of a channel */
14003 
14004 /* Bits 31..16 : High level limit */
14005 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
14006 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
14007 
14008 /* Bits 15..0 : Low level limit */
14009 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
14010 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
14011 
14012 /* Register: SAADC_RESOLUTION */
14013 /* Description: Resolution configuration */
14014 
14015 /* Bits 2..0 : Set the resolution */
14016 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
14017 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
14018 #define SAADC_RESOLUTION_VAL_8bit (0x0UL) /*!< 8 bits */
14019 #define SAADC_RESOLUTION_VAL_10bit (0x1UL) /*!< 10 bits */
14020 #define SAADC_RESOLUTION_VAL_12bit (0x2UL) /*!< 12 bits */
14021 #define SAADC_RESOLUTION_VAL_14bit (0x3UL) /*!< 14 bits */
14022 
14023 /* Register: SAADC_OVERSAMPLE */
14024 /* Description: Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
14025 
14026 /* Bits 3..0 : Oversample control */
14027 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
14028 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
14029 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0x0UL) /*!< Bypass oversampling */
14030 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (0x1UL) /*!< Oversample 2x */
14031 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (0x2UL) /*!< Oversample 4x */
14032 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (0x3UL) /*!< Oversample 8x */
14033 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (0x4UL) /*!< Oversample 16x */
14034 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (0x5UL) /*!< Oversample 32x */
14035 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (0x6UL) /*!< Oversample 64x */
14036 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (0x7UL) /*!< Oversample 128x */
14037 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (0x8UL) /*!< Oversample 256x */
14038 
14039 /* Register: SAADC_SAMPLERATE */
14040 /* Description: Controls normal or continuous sample rate */
14041 
14042 /* Bit 12 : Select mode for sample rate control */
14043 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
14044 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
14045 #define SAADC_SAMPLERATE_MODE_Task (0x0UL) /*!< Rate is controlled from SAMPLE task */
14046 #define SAADC_SAMPLERATE_MODE_Timers (0x1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
14047 
14048 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
14049 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
14050 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
14051 
14052 /* Register: SAADC_RESULT_PTR */
14053 /* Description: Data pointer */
14054 
14055 /* Bits 31..0 : Data pointer */
14056 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14057 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14058 
14059 /* Register: SAADC_RESULT_MAXCNT */
14060 /* Description: Maximum number of 16-bit samples to be written to output RAM buffer */
14061 
14062 /* Bits 14..0 : Maximum number of 16-bit samples to be written to output RAM buffer */
14063 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14064 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14065 
14066 /* Register: SAADC_RESULT_AMOUNT */
14067 /* Description: Number of 16-bit samples written to output RAM buffer since the previous START task */
14068 
14069 /* Bits 14..0 : Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. */
14070 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14071 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14072 
14073 
14074 /* Peripheral: SPI */
14075 /* Description: Serial Peripheral Interface 0 */
14076 
14077 /* Register: SPI_EVENTS_READY */
14078 /* Description: TXD byte sent and RXD byte received */
14079 
14080 /* Bit 0 : TXD byte sent and RXD byte received */
14081 #define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
14082 #define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
14083 #define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */
14084 #define SPI_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */
14085 
14086 /* Register: SPI_INTENSET */
14087 /* Description: Enable interrupt */
14088 
14089 /* Bit 2 : Write '1' to enable interrupt for event READY */
14090 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
14091 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
14092 #define SPI_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */
14093 #define SPI_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */
14094 #define SPI_INTENSET_READY_Set (0x1UL) /*!< Enable */
14095 
14096 /* Register: SPI_INTENCLR */
14097 /* Description: Disable interrupt */
14098 
14099 /* Bit 2 : Write '1' to disable interrupt for event READY */
14100 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
14101 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
14102 #define SPI_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */
14103 #define SPI_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */
14104 #define SPI_INTENCLR_READY_Clear (0x1UL) /*!< Disable */
14105 
14106 /* Register: SPI_ENABLE */
14107 /* Description: Enable SPI */
14108 
14109 /* Bits 3..0 : Enable or disable SPI */
14110 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14111 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14112 #define SPI_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPI */
14113 #define SPI_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable SPI */
14114 
14115 /* Register: SPI_PSEL_SCK */
14116 /* Description: Pin select for SCK */
14117 
14118 /* Bit 31 : Connection */
14119 #define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14120 #define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14121 #define SPI_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
14122 #define SPI_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14123 
14124 /* Bit 5 : Port number */
14125 #define SPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
14126 #define SPI_PSEL_SCK_PORT_Msk (0x1UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
14127 
14128 /* Bits 4..0 : Pin number */
14129 #define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
14130 #define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
14131 
14132 /* Register: SPI_PSEL_MOSI */
14133 /* Description: Pin select for MOSI signal */
14134 
14135 /* Bit 31 : Connection */
14136 #define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14137 #define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14138 #define SPI_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */
14139 #define SPI_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14140 
14141 /* Bit 5 : Port number */
14142 #define SPI_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
14143 #define SPI_PSEL_MOSI_PORT_Msk (0x1UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
14144 
14145 /* Bits 4..0 : Pin number */
14146 #define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
14147 #define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
14148 
14149 /* Register: SPI_PSEL_MISO */
14150 /* Description: Pin select for MISO signal */
14151 
14152 /* Bit 31 : Connection */
14153 #define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14154 #define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14155 #define SPI_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */
14156 #define SPI_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14157 
14158 /* Bit 5 : Port number */
14159 #define SPI_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
14160 #define SPI_PSEL_MISO_PORT_Msk (0x1UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
14161 
14162 /* Bits 4..0 : Pin number */
14163 #define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
14164 #define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
14165 
14166 /* Register: SPI_RXD */
14167 /* Description: RXD register. Register is cleared on read and the buffer pointer will be modified if read. */
14168 
14169 /* Bits 7..0 : RX data received. Double buffered */
14170 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
14171 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
14172 
14173 /* Register: SPI_TXD */
14174 /* Description: TXD register */
14175 
14176 /* Bits 7..0 : TX data to send. Double buffered. */
14177 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
14178 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
14179 
14180 /* Register: SPI_FREQUENCY */
14181 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
14182 
14183 /* Bits 31..0 : SPI master data rate */
14184 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
14185 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
14186 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
14187 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
14188 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
14189 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
14190 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
14191 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
14192 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
14193 
14194 /* Register: SPI_CONFIG */
14195 /* Description: Configuration register */
14196 
14197 /* Bit 2 : Serial clock (SCK) polarity */
14198 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
14199 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
14200 #define SPI_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */
14201 #define SPI_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */
14202 
14203 /* Bit 1 : Serial clock (SCK) phase */
14204 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
14205 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
14206 #define SPI_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
14207 #define SPI_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
14208 
14209 /* Bit 0 : Bit order */
14210 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
14211 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
14212 #define SPI_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */
14213 #define SPI_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */
14214 
14215 
14216 /* Peripheral: SPIM */
14217 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
14218 
14219 /* Register: SPIM_TASKS_START */
14220 /* Description: Start SPI transaction */
14221 
14222 /* Bit 0 : Start SPI transaction */
14223 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
14224 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
14225 #define SPIM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
14226 
14227 /* Register: SPIM_TASKS_STOP */
14228 /* Description: Stop SPI transaction */
14229 
14230 /* Bit 0 : Stop SPI transaction */
14231 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
14232 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
14233 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
14234 
14235 /* Register: SPIM_TASKS_SUSPEND */
14236 /* Description: Suspend SPI transaction */
14237 
14238 /* Bit 0 : Suspend SPI transaction */
14239 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
14240 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
14241 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */
14242 
14243 /* Register: SPIM_TASKS_RESUME */
14244 /* Description: Resume SPI transaction */
14245 
14246 /* Bit 0 : Resume SPI transaction */
14247 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
14248 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
14249 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */
14250 
14251 /* Register: SPIM_EVENTS_STOPPED */
14252 /* Description: SPI transaction has stopped */
14253 
14254 /* Bit 0 : SPI transaction has stopped */
14255 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
14256 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
14257 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
14258 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
14259 
14260 /* Register: SPIM_EVENTS_ENDRX */
14261 /* Description: End of RXD buffer reached */
14262 
14263 /* Bit 0 : End of RXD buffer reached */
14264 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
14265 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
14266 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
14267 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */
14268 
14269 /* Register: SPIM_EVENTS_END */
14270 /* Description: End of RXD buffer and TXD buffer reached */
14271 
14272 /* Bit 0 : End of RXD buffer and TXD buffer reached */
14273 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
14274 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
14275 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
14276 #define SPIM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */
14277 
14278 /* Register: SPIM_EVENTS_ENDTX */
14279 /* Description: End of TXD buffer reached */
14280 
14281 /* Bit 0 : End of TXD buffer reached */
14282 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
14283 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
14284 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */
14285 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */
14286 
14287 /* Register: SPIM_EVENTS_STARTED */
14288 /* Description: Transaction started */
14289 
14290 /* Bit 0 : Transaction started */
14291 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
14292 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
14293 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
14294 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */
14295 
14296 /* Register: SPIM_SHORTS */
14297 /* Description: Shortcuts between local events and tasks */
14298 
14299 /* Bit 17 : Shortcut between event END and task START */
14300 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
14301 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
14302 #define SPIM_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */
14303 #define SPIM_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */
14304 
14305 /* Register: SPIM_INTENSET */
14306 /* Description: Enable interrupt */
14307 
14308 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
14309 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
14310 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
14311 #define SPIM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
14312 #define SPIM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
14313 #define SPIM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */
14314 
14315 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
14316 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
14317 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
14318 #define SPIM_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
14319 #define SPIM_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
14320 #define SPIM_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */
14321 
14322 /* Bit 6 : Write '1' to enable interrupt for event END */
14323 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
14324 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
14325 #define SPIM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
14326 #define SPIM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
14327 #define SPIM_INTENSET_END_Set (0x1UL) /*!< Enable */
14328 
14329 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
14330 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
14331 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
14332 #define SPIM_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
14333 #define SPIM_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
14334 #define SPIM_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */
14335 
14336 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
14337 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14338 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14339 #define SPIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
14340 #define SPIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
14341 #define SPIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
14342 
14343 /* Register: SPIM_INTENCLR */
14344 /* Description: Disable interrupt */
14345 
14346 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
14347 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
14348 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
14349 #define SPIM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
14350 #define SPIM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
14351 #define SPIM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */
14352 
14353 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
14354 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
14355 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
14356 #define SPIM_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
14357 #define SPIM_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
14358 #define SPIM_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */
14359 
14360 /* Bit 6 : Write '1' to disable interrupt for event END */
14361 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
14362 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
14363 #define SPIM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
14364 #define SPIM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
14365 #define SPIM_INTENCLR_END_Clear (0x1UL) /*!< Disable */
14366 
14367 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
14368 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
14369 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
14370 #define SPIM_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
14371 #define SPIM_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
14372 #define SPIM_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */
14373 
14374 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
14375 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14376 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14377 #define SPIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
14378 #define SPIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
14379 #define SPIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
14380 
14381 /* Register: SPIM_STALLSTAT */
14382 /* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. */
14383 
14384 /* Bit 1 : Stall status for EasyDMA RAM writes */
14385 #define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */
14386 #define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */
14387 #define SPIM_STALLSTAT_RX_NOSTALL (0x0UL) /*!< No stall */
14388 #define SPIM_STALLSTAT_RX_STALL (0x1UL) /*!< A stall has occurred */
14389 
14390 /* Bit 0 : Stall status for EasyDMA RAM reads */
14391 #define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */
14392 #define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */
14393 #define SPIM_STALLSTAT_TX_NOSTALL (0x0UL) /*!< No stall */
14394 #define SPIM_STALLSTAT_TX_STALL (0x1UL) /*!< A stall has occurred */
14395 
14396 /* Register: SPIM_ENABLE */
14397 /* Description: Enable SPIM */
14398 
14399 /* Bits 3..0 : Enable or disable SPIM */
14400 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14401 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14402 #define SPIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPIM */
14403 #define SPIM_ENABLE_ENABLE_Enabled (0x7UL) /*!< Enable SPIM */
14404 
14405 /* Register: SPIM_PSEL_SCK */
14406 /* Description: Pin select for SCK */
14407 
14408 /* Bit 31 : Connection */
14409 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14410 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14411 #define SPIM_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
14412 #define SPIM_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14413 
14414 /* Bit 5 : Port number */
14415 #define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
14416 #define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
14417 
14418 /* Bits 4..0 : Pin number */
14419 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
14420 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
14421 
14422 /* Register: SPIM_PSEL_MOSI */
14423 /* Description: Pin select for MOSI signal */
14424 
14425 /* Bit 31 : Connection */
14426 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14427 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14428 #define SPIM_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */
14429 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14430 
14431 /* Bit 5 : Port number */
14432 #define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
14433 #define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
14434 
14435 /* Bits 4..0 : Pin number */
14436 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
14437 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
14438 
14439 /* Register: SPIM_PSEL_MISO */
14440 /* Description: Pin select for MISO signal */
14441 
14442 /* Bit 31 : Connection */
14443 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14444 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14445 #define SPIM_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */
14446 #define SPIM_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14447 
14448 /* Bit 5 : Port number */
14449 #define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
14450 #define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
14451 
14452 /* Bits 4..0 : Pin number */
14453 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
14454 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
14455 
14456 /* Register: SPIM_PSEL_CSN */
14457 /* Description: Pin select for CSN */
14458 
14459 /* Bit 31 : Connection */
14460 #define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14461 #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14462 #define SPIM_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */
14463 #define SPIM_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14464 
14465 /* Bit 5 : Port number */
14466 #define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
14467 #define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
14468 
14469 /* Bits 4..0 : Pin number */
14470 #define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
14471 #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
14472 
14473 /* Register: SPIM_FREQUENCY */
14474 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
14475 
14476 /* Bits 31..0 : SPI master data rate */
14477 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
14478 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
14479 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
14480 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
14481 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
14482 #define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */
14483 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
14484 #define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */
14485 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
14486 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
14487 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
14488 
14489 /* Register: SPIM_RXD_PTR */
14490 /* Description: Data pointer */
14491 
14492 /* Bits 31..0 : Data pointer */
14493 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14494 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14495 
14496 /* Register: SPIM_RXD_MAXCNT */
14497 /* Description: Maximum number of bytes in receive buffer */
14498 
14499 /* Bits 15..0 : Maximum number of bytes in receive buffer */
14500 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14501 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14502 
14503 /* Register: SPIM_RXD_AMOUNT */
14504 /* Description: Number of bytes transferred in the last transaction */
14505 
14506 /* Bits 15..0 : Number of bytes transferred in the last transaction */
14507 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14508 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14509 
14510 /* Register: SPIM_RXD_LIST */
14511 /* Description: EasyDMA list type */
14512 
14513 /* Bits 1..0 : List type */
14514 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14515 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14516 #define SPIM_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
14517 #define SPIM_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
14518 
14519 /* Register: SPIM_TXD_PTR */
14520 /* Description: Data pointer */
14521 
14522 /* Bits 31..0 : Data pointer */
14523 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14524 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14525 
14526 /* Register: SPIM_TXD_MAXCNT */
14527 /* Description: Number of bytes in transmit buffer */
14528 
14529 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
14530 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14531 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14532 
14533 /* Register: SPIM_TXD_AMOUNT */
14534 /* Description: Number of bytes transferred in the last transaction */
14535 
14536 /* Bits 15..0 : Number of bytes transferred in the last transaction */
14537 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14538 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14539 
14540 /* Register: SPIM_TXD_LIST */
14541 /* Description: EasyDMA list type */
14542 
14543 /* Bits 1..0 : List type */
14544 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14545 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14546 #define SPIM_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
14547 #define SPIM_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
14548 
14549 /* Register: SPIM_CONFIG */
14550 /* Description: Configuration register */
14551 
14552 /* Bit 2 : Serial clock (SCK) polarity */
14553 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
14554 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
14555 #define SPIM_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */
14556 #define SPIM_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */
14557 
14558 /* Bit 1 : Serial clock (SCK) phase */
14559 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
14560 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
14561 #define SPIM_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
14562 #define SPIM_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
14563 
14564 /* Bit 0 : Bit order */
14565 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
14566 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
14567 #define SPIM_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */
14568 #define SPIM_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */
14569 
14570 /* Register: SPIM_IFTIMING_RXDELAY */
14571 /* Description: Sample delay for input serial data on MISO */
14572 
14573 /* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */
14574 #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */
14575 #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
14576 
14577 /* Register: SPIM_IFTIMING_CSNDUR */
14578 /* Description: Minimum duration between edge of CSN and edge of SCK at the start and the end of a transaction, and minimum duration CSN will stay high between transactions if END-START shortcut is used */
14579 
14580 /* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK at the start and end of a transaction. If END-START shortcut is used, minimum duration CSN will stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */
14581 #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */
14582 #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */
14583 
14584 /* Register: SPIM_CSNPOL */
14585 /* Description: Polarity of CSN output */
14586 
14587 /* Bit 0 : Polarity of CSN output */
14588 #define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */
14589 #define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */
14590 #define SPIM_CSNPOL_CSNPOL_LOW (0x0UL) /*!< Active low (idle state high) */
14591 #define SPIM_CSNPOL_CSNPOL_HIGH (0x1UL) /*!< Active high (idle state low) */
14592 
14593 /* Register: SPIM_PSELDCX */
14594 /* Description: Pin select for DCX signal */
14595 
14596 /* Bit 31 : Connection */
14597 #define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14598 #define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14599 #define SPIM_PSELDCX_CONNECT_Connected (0x0UL) /*!< Connect */
14600 #define SPIM_PSELDCX_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14601 
14602 /* Bit 5 : Port number */
14603 #define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */
14604 #define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */
14605 
14606 /* Bits 4..0 : Pin number */
14607 #define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */
14608 #define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */
14609 
14610 /* Register: SPIM_DCXCNT */
14611 /* Description: DCX configuration */
14612 
14613 /* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */
14614 #define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */
14615 #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */
14616 
14617 /* Register: SPIM_ORC */
14618 /* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
14619 
14620 /* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */
14621 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
14622 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
14623 
14624 
14625 /* Peripheral: SPIS */
14626 /* Description: SPI Slave 0 */
14627 
14628 /* Register: SPIS_TASKS_ACQUIRE */
14629 /* Description: Acquire SPI semaphore */
14630 
14631 /* Bit 0 : Acquire SPI semaphore */
14632 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
14633 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
14634 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (0x1UL) /*!< Trigger task */
14635 
14636 /* Register: SPIS_TASKS_RELEASE */
14637 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
14638 
14639 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
14640 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
14641 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
14642 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (0x1UL) /*!< Trigger task */
14643 
14644 /* Register: SPIS_EVENTS_END */
14645 /* Description: Granted transaction completed */
14646 
14647 /* Bit 0 : Granted transaction completed */
14648 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
14649 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
14650 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
14651 #define SPIS_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */
14652 
14653 /* Register: SPIS_EVENTS_ENDRX */
14654 /* Description: End of RXD buffer reached */
14655 
14656 /* Bit 0 : End of RXD buffer reached */
14657 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
14658 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
14659 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
14660 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */
14661 
14662 /* Register: SPIS_EVENTS_ACQUIRED */
14663 /* Description: Semaphore acquired */
14664 
14665 /* Bit 0 : Semaphore acquired */
14666 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
14667 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
14668 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0x0UL) /*!< Event not generated */
14669 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (0x1UL) /*!< Event generated */
14670 
14671 /* Register: SPIS_SHORTS */
14672 /* Description: Shortcuts between local events and tasks */
14673 
14674 /* Bit 2 : Shortcut between event END and task ACQUIRE */
14675 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
14676 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
14677 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0x0UL) /*!< Disable shortcut */
14678 #define SPIS_SHORTS_END_ACQUIRE_Enabled (0x1UL) /*!< Enable shortcut */
14679 
14680 /* Register: SPIS_INTENSET */
14681 /* Description: Enable interrupt */
14682 
14683 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
14684 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
14685 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
14686 #define SPIS_INTENSET_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */
14687 #define SPIS_INTENSET_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */
14688 #define SPIS_INTENSET_ACQUIRED_Set (0x1UL) /*!< Enable */
14689 
14690 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
14691 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
14692 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
14693 #define SPIS_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
14694 #define SPIS_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
14695 #define SPIS_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */
14696 
14697 /* Bit 1 : Write '1' to enable interrupt for event END */
14698 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
14699 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
14700 #define SPIS_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
14701 #define SPIS_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
14702 #define SPIS_INTENSET_END_Set (0x1UL) /*!< Enable */
14703 
14704 /* Register: SPIS_INTENCLR */
14705 /* Description: Disable interrupt */
14706 
14707 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
14708 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
14709 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
14710 #define SPIS_INTENCLR_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */
14711 #define SPIS_INTENCLR_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */
14712 #define SPIS_INTENCLR_ACQUIRED_Clear (0x1UL) /*!< Disable */
14713 
14714 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
14715 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
14716 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
14717 #define SPIS_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
14718 #define SPIS_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
14719 #define SPIS_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */
14720 
14721 /* Bit 1 : Write '1' to disable interrupt for event END */
14722 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
14723 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
14724 #define SPIS_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
14725 #define SPIS_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
14726 #define SPIS_INTENCLR_END_Clear (0x1UL) /*!< Disable */
14727 
14728 /* Register: SPIS_SEMSTAT */
14729 /* Description: Semaphore status register */
14730 
14731 /* Bits 1..0 : Semaphore status */
14732 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
14733 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
14734 #define SPIS_SEMSTAT_SEMSTAT_Free (0x0UL) /*!< Semaphore is free */
14735 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x1UL) /*!< Semaphore is assigned to CPU */
14736 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x2UL) /*!< Semaphore is assigned to SPI slave */
14737 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
14738 
14739 /* Register: SPIS_STATUS */
14740 /* Description: Status from last transaction */
14741 
14742 /* Bit 1 : RX buffer overflow detected, and prevented */
14743 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
14744 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
14745 #define SPIS_STATUS_OVERFLOW_NotPresent (0x0UL) /*!< Read: error not present */
14746 #define SPIS_STATUS_OVERFLOW_Present (0x1UL) /*!< Read: error present */
14747 #define SPIS_STATUS_OVERFLOW_Clear (0x1UL) /*!< Write: clear error on writing '1' */
14748 
14749 /* Bit 0 : TX buffer over-read detected, and prevented */
14750 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
14751 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
14752 #define SPIS_STATUS_OVERREAD_NotPresent (0x0UL) /*!< Read: error not present */
14753 #define SPIS_STATUS_OVERREAD_Present (0x1UL) /*!< Read: error present */
14754 #define SPIS_STATUS_OVERREAD_Clear (0x1UL) /*!< Write: clear error on writing '1' */
14755 
14756 /* Register: SPIS_ENABLE */
14757 /* Description: Enable SPI slave */
14758 
14759 /* Bits 3..0 : Enable or disable SPI slave */
14760 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14761 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14762 #define SPIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPI slave */
14763 #define SPIS_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable SPI slave */
14764 
14765 /* Register: SPIS_PSEL_SCK */
14766 /* Description: Pin select for SCK */
14767 
14768 /* Bit 31 : Connection */
14769 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14770 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14771 #define SPIS_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
14772 #define SPIS_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14773 
14774 /* Bit 5 : Port number */
14775 #define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
14776 #define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
14777 
14778 /* Bits 4..0 : Pin number */
14779 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
14780 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
14781 
14782 /* Register: SPIS_PSEL_MISO */
14783 /* Description: Pin select for MISO signal */
14784 
14785 /* Bit 31 : Connection */
14786 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14787 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14788 #define SPIS_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */
14789 #define SPIS_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14790 
14791 /* Bit 5 : Port number */
14792 #define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
14793 #define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
14794 
14795 /* Bits 4..0 : Pin number */
14796 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
14797 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
14798 
14799 /* Register: SPIS_PSEL_MOSI */
14800 /* Description: Pin select for MOSI signal */
14801 
14802 /* Bit 31 : Connection */
14803 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14804 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14805 #define SPIS_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */
14806 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14807 
14808 /* Bit 5 : Port number */
14809 #define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
14810 #define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
14811 
14812 /* Bits 4..0 : Pin number */
14813 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
14814 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
14815 
14816 /* Register: SPIS_PSEL_CSN */
14817 /* Description: Pin select for CSN signal */
14818 
14819 /* Bit 31 : Connection */
14820 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14821 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14822 #define SPIS_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */
14823 #define SPIS_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
14824 
14825 /* Bit 5 : Port number */
14826 #define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
14827 #define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
14828 
14829 /* Bits 4..0 : Pin number */
14830 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
14831 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
14832 
14833 /* Register: SPIS_RXD_PTR */
14834 /* Description: RXD data pointer */
14835 
14836 /* Bits 31..0 : RXD data pointer */
14837 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14838 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14839 
14840 /* Register: SPIS_RXD_MAXCNT */
14841 /* Description: Maximum number of bytes in receive buffer */
14842 
14843 /* Bits 15..0 : Maximum number of bytes in receive buffer */
14844 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14845 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14846 
14847 /* Register: SPIS_RXD_AMOUNT */
14848 /* Description: Number of bytes received in last granted transaction */
14849 
14850 /* Bits 15..0 : Number of bytes received in the last granted transaction */
14851 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14852 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14853 
14854 /* Register: SPIS_RXD_LIST */
14855 /* Description: EasyDMA list type */
14856 
14857 /* Bits 1..0 : List type */
14858 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14859 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14860 #define SPIS_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
14861 #define SPIS_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
14862 
14863 /* Register: SPIS_TXD_PTR */
14864 /* Description: TXD data pointer */
14865 
14866 /* Bits 31..0 : TXD data pointer */
14867 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14868 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14869 
14870 /* Register: SPIS_TXD_MAXCNT */
14871 /* Description: Maximum number of bytes in transmit buffer */
14872 
14873 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
14874 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14875 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14876 
14877 /* Register: SPIS_TXD_AMOUNT */
14878 /* Description: Number of bytes transmitted in last granted transaction */
14879 
14880 /* Bits 15..0 : Number of bytes transmitted in last granted transaction */
14881 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14882 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14883 
14884 /* Register: SPIS_TXD_LIST */
14885 /* Description: EasyDMA list type */
14886 
14887 /* Bits 1..0 : List type */
14888 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14889 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14890 #define SPIS_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
14891 #define SPIS_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
14892 
14893 /* Register: SPIS_CONFIG */
14894 /* Description: Configuration register */
14895 
14896 /* Bit 2 : Serial clock (SCK) polarity */
14897 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
14898 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
14899 #define SPIS_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */
14900 #define SPIS_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */
14901 
14902 /* Bit 1 : Serial clock (SCK) phase */
14903 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
14904 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
14905 #define SPIS_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
14906 #define SPIS_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
14907 
14908 /* Bit 0 : Bit order */
14909 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
14910 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
14911 #define SPIS_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */
14912 #define SPIS_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */
14913 
14914 /* Register: SPIS_DEF */
14915 /* Description: Default character. Character clocked out in case of an ignored transaction. */
14916 
14917 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
14918 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
14919 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
14920 
14921 /* Register: SPIS_ORC */
14922 /* Description: Over-read character */
14923 
14924 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
14925 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
14926 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
14927 
14928 
14929 /* Peripheral: TEMP */
14930 /* Description: Temperature Sensor */
14931 
14932 /* Register: TEMP_TASKS_START */
14933 /* Description: Start temperature measurement */
14934 
14935 /* Bit 0 : Start temperature measurement */
14936 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
14937 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
14938 #define TEMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
14939 
14940 /* Register: TEMP_TASKS_STOP */
14941 /* Description: Stop temperature measurement */
14942 
14943 /* Bit 0 : Stop temperature measurement */
14944 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
14945 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
14946 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
14947 
14948 /* Register: TEMP_EVENTS_DATARDY */
14949 /* Description: Temperature measurement complete, data ready */
14950 
14951 /* Bit 0 : Temperature measurement complete, data ready */
14952 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
14953 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
14954 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0x0UL) /*!< Event not generated */
14955 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (0x1UL) /*!< Event generated */
14956 
14957 /* Register: TEMP_INTENSET */
14958 /* Description: Enable interrupt */
14959 
14960 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */
14961 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
14962 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
14963 #define TEMP_INTENSET_DATARDY_Disabled (0x0UL) /*!< Read: Disabled */
14964 #define TEMP_INTENSET_DATARDY_Enabled (0x1UL) /*!< Read: Enabled */
14965 #define TEMP_INTENSET_DATARDY_Set (0x1UL) /*!< Enable */
14966 
14967 /* Register: TEMP_INTENCLR */
14968 /* Description: Disable interrupt */
14969 
14970 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */
14971 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
14972 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
14973 #define TEMP_INTENCLR_DATARDY_Disabled (0x0UL) /*!< Read: Disabled */
14974 #define TEMP_INTENCLR_DATARDY_Enabled (0x1UL) /*!< Read: Enabled */
14975 #define TEMP_INTENCLR_DATARDY_Clear (0x1UL) /*!< Disable */
14976 
14977 /* Register: TEMP_TEMP */
14978 /* Description: Temperature in degC (0.25deg steps) */
14979 
14980 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
14981 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
14982 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
14983 
14984 /* Register: TEMP_A0 */
14985 /* Description: Slope of first piecewise linear function */
14986 
14987 /* Bits 11..0 : Slope of first piecewise linear function */
14988 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
14989 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
14990 
14991 /* Register: TEMP_A1 */
14992 /* Description: Slope of second piecewise linear function */
14993 
14994 /* Bits 11..0 : Slope of second piecewise linear function */
14995 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
14996 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
14997 
14998 /* Register: TEMP_A2 */
14999 /* Description: Slope of third piecewise linear function */
15000 
15001 /* Bits 11..0 : Slope of third piecewise linear function */
15002 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
15003 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
15004 
15005 /* Register: TEMP_A3 */
15006 /* Description: Slope of fourth piecewise linear function */
15007 
15008 /* Bits 11..0 : Slope of fourth piecewise linear function */
15009 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
15010 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
15011 
15012 /* Register: TEMP_A4 */
15013 /* Description: Slope of fifth piecewise linear function */
15014 
15015 /* Bits 11..0 : Slope of fifth piecewise linear function */
15016 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
15017 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
15018 
15019 /* Register: TEMP_A5 */
15020 /* Description: Slope of sixth piecewise linear function */
15021 
15022 /* Bits 11..0 : Slope of sixth piecewise linear function */
15023 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
15024 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
15025 
15026 /* Register: TEMP_B0 */
15027 /* Description: y-intercept of first piecewise linear function */
15028 
15029 /* Bits 13..0 : y-intercept of first piecewise linear function */
15030 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
15031 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
15032 
15033 /* Register: TEMP_B1 */
15034 /* Description: y-intercept of second piecewise linear function */
15035 
15036 /* Bits 13..0 : y-intercept of second piecewise linear function */
15037 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
15038 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
15039 
15040 /* Register: TEMP_B2 */
15041 /* Description: y-intercept of third piecewise linear function */
15042 
15043 /* Bits 13..0 : y-intercept of third piecewise linear function */
15044 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
15045 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
15046 
15047 /* Register: TEMP_B3 */
15048 /* Description: y-intercept of fourth piecewise linear function */
15049 
15050 /* Bits 13..0 : y-intercept of fourth piecewise linear function */
15051 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
15052 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
15053 
15054 /* Register: TEMP_B4 */
15055 /* Description: y-intercept of fifth piecewise linear function */
15056 
15057 /* Bits 13..0 : y-intercept of fifth piecewise linear function */
15058 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
15059 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
15060 
15061 /* Register: TEMP_B5 */
15062 /* Description: y-intercept of sixth piecewise linear function */
15063 
15064 /* Bits 13..0 : y-intercept of sixth piecewise linear function */
15065 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
15066 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
15067 
15068 /* Register: TEMP_T0 */
15069 /* Description: End point of first piecewise linear function */
15070 
15071 /* Bits 7..0 : End point of first piecewise linear function */
15072 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
15073 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
15074 
15075 /* Register: TEMP_T1 */
15076 /* Description: End point of second piecewise linear function */
15077 
15078 /* Bits 7..0 : End point of second piecewise linear function */
15079 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
15080 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
15081 
15082 /* Register: TEMP_T2 */
15083 /* Description: End point of third piecewise linear function */
15084 
15085 /* Bits 7..0 : End point of third piecewise linear function */
15086 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
15087 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
15088 
15089 /* Register: TEMP_T3 */
15090 /* Description: End point of fourth piecewise linear function */
15091 
15092 /* Bits 7..0 : End point of fourth piecewise linear function */
15093 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
15094 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
15095 
15096 /* Register: TEMP_T4 */
15097 /* Description: End point of fifth piecewise linear function */
15098 
15099 /* Bits 7..0 : End point of fifth piecewise linear function */
15100 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
15101 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
15102 
15103 
15104 /* Peripheral: TIMER */
15105 /* Description: Timer/Counter 0 */
15106 
15107 /* Register: TIMER_TASKS_START */
15108 /* Description: Start Timer */
15109 
15110 /* Bit 0 : Start Timer */
15111 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
15112 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
15113 #define TIMER_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
15114 
15115 /* Register: TIMER_TASKS_STOP */
15116 /* Description: Stop Timer */
15117 
15118 /* Bit 0 : Stop Timer */
15119 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
15120 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
15121 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
15122 
15123 /* Register: TIMER_TASKS_COUNT */
15124 /* Description: Increment Timer (Counter mode only) */
15125 
15126 /* Bit 0 : Increment Timer (Counter mode only) */
15127 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
15128 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
15129 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (0x1UL) /*!< Trigger task */
15130 
15131 /* Register: TIMER_TASKS_CLEAR */
15132 /* Description: Clear time */
15133 
15134 /* Bit 0 : Clear time */
15135 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
15136 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
15137 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */
15138 
15139 /* Register: TIMER_TASKS_SHUTDOWN */
15140 /* Description: Deprecated register - Shut down timer */
15141 
15142 /* Bit 0 : Deprecated field -  Shut down timer */
15143 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
15144 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
15145 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (0x1UL) /*!< Trigger task */
15146 
15147 /* Register: TIMER_TASKS_CAPTURE */
15148 /* Description: Description collection: Capture Timer value to CC[n] register */
15149 
15150 /* Bit 0 : Capture Timer value to CC[n] register */
15151 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
15152 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
15153 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */
15154 
15155 /* Register: TIMER_EVENTS_COMPARE */
15156 /* Description: Description collection: Compare event on CC[n] match */
15157 
15158 /* Bit 0 : Compare event on CC[n] match */
15159 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
15160 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
15161 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */
15162 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */
15163 
15164 /* Register: TIMER_SHORTS */
15165 /* Description: Shortcuts between local events and tasks */
15166 
15167 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
15168 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
15169 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
15170 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0x0UL) /*!< Disable shortcut */
15171 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (0x1UL) /*!< Enable shortcut */
15172 
15173 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
15174 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
15175 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
15176 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0x0UL) /*!< Disable shortcut */
15177 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (0x1UL) /*!< Enable shortcut */
15178 
15179 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
15180 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
15181 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
15182 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0x0UL) /*!< Disable shortcut */
15183 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (0x1UL) /*!< Enable shortcut */
15184 
15185 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
15186 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
15187 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
15188 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0x0UL) /*!< Disable shortcut */
15189 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (0x1UL) /*!< Enable shortcut */
15190 
15191 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
15192 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
15193 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
15194 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0x0UL) /*!< Disable shortcut */
15195 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (0x1UL) /*!< Enable shortcut */
15196 
15197 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
15198 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
15199 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
15200 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0x0UL) /*!< Disable shortcut */
15201 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (0x1UL) /*!< Enable shortcut */
15202 
15203 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
15204 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
15205 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
15206 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
15207 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
15208 
15209 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
15210 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
15211 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
15212 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
15213 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
15214 
15215 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
15216 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
15217 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
15218 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
15219 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
15220 
15221 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
15222 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
15223 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
15224 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
15225 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
15226 
15227 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
15228 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
15229 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
15230 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
15231 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
15232 
15233 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
15234 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
15235 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
15236 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
15237 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */
15238 
15239 /* Register: TIMER_INTENSET */
15240 /* Description: Enable interrupt */
15241 
15242 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
15243 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
15244 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
15245 #define TIMER_INTENSET_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */
15246 #define TIMER_INTENSET_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */
15247 #define TIMER_INTENSET_COMPARE5_Set (0x1UL) /*!< Enable */
15248 
15249 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
15250 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
15251 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
15252 #define TIMER_INTENSET_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */
15253 #define TIMER_INTENSET_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */
15254 #define TIMER_INTENSET_COMPARE4_Set (0x1UL) /*!< Enable */
15255 
15256 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
15257 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
15258 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
15259 #define TIMER_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
15260 #define TIMER_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
15261 #define TIMER_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */
15262 
15263 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
15264 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
15265 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
15266 #define TIMER_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
15267 #define TIMER_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
15268 #define TIMER_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */
15269 
15270 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
15271 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
15272 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
15273 #define TIMER_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
15274 #define TIMER_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
15275 #define TIMER_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */
15276 
15277 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
15278 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
15279 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
15280 #define TIMER_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
15281 #define TIMER_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
15282 #define TIMER_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */
15283 
15284 /* Register: TIMER_INTENCLR */
15285 /* Description: Disable interrupt */
15286 
15287 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
15288 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
15289 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
15290 #define TIMER_INTENCLR_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */
15291 #define TIMER_INTENCLR_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */
15292 #define TIMER_INTENCLR_COMPARE5_Clear (0x1UL) /*!< Disable */
15293 
15294 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
15295 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
15296 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
15297 #define TIMER_INTENCLR_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */
15298 #define TIMER_INTENCLR_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */
15299 #define TIMER_INTENCLR_COMPARE4_Clear (0x1UL) /*!< Disable */
15300 
15301 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
15302 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
15303 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
15304 #define TIMER_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
15305 #define TIMER_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
15306 #define TIMER_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */
15307 
15308 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
15309 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
15310 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
15311 #define TIMER_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
15312 #define TIMER_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
15313 #define TIMER_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */
15314 
15315 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
15316 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
15317 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
15318 #define TIMER_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
15319 #define TIMER_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
15320 #define TIMER_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */
15321 
15322 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
15323 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
15324 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
15325 #define TIMER_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
15326 #define TIMER_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
15327 #define TIMER_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */
15328 
15329 /* Register: TIMER_MODE */
15330 /* Description: Timer mode selection */
15331 
15332 /* Bits 1..0 : Timer mode */
15333 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
15334 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
15335 #define TIMER_MODE_MODE_Timer (0x0UL) /*!< Select Timer mode */
15336 #define TIMER_MODE_MODE_Counter (0x1UL) /*!< Deprecated enumerator -  Select Counter mode */
15337 #define TIMER_MODE_MODE_LowPowerCounter (0x2UL) /*!< Select Low Power Counter mode */
15338 
15339 /* Register: TIMER_BITMODE */
15340 /* Description: Configure the number of bits used by the TIMER */
15341 
15342 /* Bits 1..0 : Timer bit width */
15343 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
15344 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
15345 #define TIMER_BITMODE_BITMODE_16Bit (0x0UL) /*!< 16 bit timer bit width */
15346 #define TIMER_BITMODE_BITMODE_08Bit (0x1UL) /*!< 8 bit timer bit width */
15347 #define TIMER_BITMODE_BITMODE_24Bit (0x2UL) /*!< 24 bit timer bit width */
15348 #define TIMER_BITMODE_BITMODE_32Bit (0x3UL) /*!< 32 bit timer bit width */
15349 
15350 /* Register: TIMER_PRESCALER */
15351 /* Description: Timer prescaler register */
15352 
15353 /* Bits 3..0 : Prescaler value */
15354 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
15355 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
15356 
15357 /* Register: TIMER_CC */
15358 /* Description: Description collection: Capture/Compare register n */
15359 
15360 /* Bits 31..0 : Capture/Compare value */
15361 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
15362 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
15363 
15364 
15365 /* Peripheral: TWI */
15366 /* Description: I2C compatible Two-Wire Interface 0 */
15367 
15368 /* Register: TWI_TASKS_STARTRX */
15369 /* Description: Start TWI receive sequence */
15370 
15371 /* Bit 0 : Start TWI receive sequence */
15372 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
15373 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
15374 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */
15375 
15376 /* Register: TWI_TASKS_STARTTX */
15377 /* Description: Start TWI transmit sequence */
15378 
15379 /* Bit 0 : Start TWI transmit sequence */
15380 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
15381 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
15382 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */
15383 
15384 /* Register: TWI_TASKS_STOP */
15385 /* Description: Stop TWI transaction */
15386 
15387 /* Bit 0 : Stop TWI transaction */
15388 #define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
15389 #define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
15390 #define TWI_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
15391 
15392 /* Register: TWI_TASKS_SUSPEND */
15393 /* Description: Suspend TWI transaction */
15394 
15395 /* Bit 0 : Suspend TWI transaction */
15396 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
15397 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
15398 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */
15399 
15400 /* Register: TWI_TASKS_RESUME */
15401 /* Description: Resume TWI transaction */
15402 
15403 /* Bit 0 : Resume TWI transaction */
15404 #define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
15405 #define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
15406 #define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */
15407 
15408 /* Register: TWI_EVENTS_STOPPED */
15409 /* Description: TWI stopped */
15410 
15411 /* Bit 0 : TWI stopped */
15412 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
15413 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
15414 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
15415 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
15416 
15417 /* Register: TWI_EVENTS_RXDREADY */
15418 /* Description: TWI RXD byte received */
15419 
15420 /* Bit 0 : TWI RXD byte received */
15421 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */
15422 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */
15423 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0x0UL) /*!< Event not generated */
15424 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (0x1UL) /*!< Event generated */
15425 
15426 /* Register: TWI_EVENTS_TXDSENT */
15427 /* Description: TWI TXD byte sent */
15428 
15429 /* Bit 0 : TWI TXD byte sent */
15430 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */
15431 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */
15432 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0x0UL) /*!< Event not generated */
15433 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (0x1UL) /*!< Event generated */
15434 
15435 /* Register: TWI_EVENTS_ERROR */
15436 /* Description: TWI error */
15437 
15438 /* Bit 0 : TWI error */
15439 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
15440 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
15441 #define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
15442 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */
15443 
15444 /* Register: TWI_EVENTS_BB */
15445 /* Description: TWI byte boundary, generated before each byte that is sent or received */
15446 
15447 /* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */
15448 #define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */
15449 #define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */
15450 #define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0x0UL) /*!< Event not generated */
15451 #define TWI_EVENTS_BB_EVENTS_BB_Generated (0x1UL) /*!< Event generated */
15452 
15453 /* Register: TWI_EVENTS_SUSPENDED */
15454 /* Description: TWI entered the suspended state */
15455 
15456 /* Bit 0 : TWI entered the suspended state */
15457 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
15458 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
15459 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0x0UL) /*!< Event not generated */
15460 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (0x1UL) /*!< Event generated */
15461 
15462 /* Register: TWI_SHORTS */
15463 /* Description: Shortcuts between local events and tasks */
15464 
15465 /* Bit 1 : Shortcut between event BB and task STOP */
15466 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
15467 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
15468 #define TWI_SHORTS_BB_STOP_Disabled (0x0UL) /*!< Disable shortcut */
15469 #define TWI_SHORTS_BB_STOP_Enabled (0x1UL) /*!< Enable shortcut */
15470 
15471 /* Bit 0 : Shortcut between event BB and task SUSPEND */
15472 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
15473 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
15474 #define TWI_SHORTS_BB_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
15475 #define TWI_SHORTS_BB_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */
15476 
15477 /* Register: TWI_INTENSET */
15478 /* Description: Enable interrupt */
15479 
15480 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
15481 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
15482 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
15483 #define TWI_INTENSET_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */
15484 #define TWI_INTENSET_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */
15485 #define TWI_INTENSET_SUSPENDED_Set (0x1UL) /*!< Enable */
15486 
15487 /* Bit 14 : Write '1' to enable interrupt for event BB */
15488 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
15489 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
15490 #define TWI_INTENSET_BB_Disabled (0x0UL) /*!< Read: Disabled */
15491 #define TWI_INTENSET_BB_Enabled (0x1UL) /*!< Read: Enabled */
15492 #define TWI_INTENSET_BB_Set (0x1UL) /*!< Enable */
15493 
15494 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
15495 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15496 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
15497 #define TWI_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
15498 #define TWI_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
15499 #define TWI_INTENSET_ERROR_Set (0x1UL) /*!< Enable */
15500 
15501 /* Bit 7 : Write '1' to enable interrupt for event TXDSENT */
15502 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
15503 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
15504 #define TWI_INTENSET_TXDSENT_Disabled (0x0UL) /*!< Read: Disabled */
15505 #define TWI_INTENSET_TXDSENT_Enabled (0x1UL) /*!< Read: Enabled */
15506 #define TWI_INTENSET_TXDSENT_Set (0x1UL) /*!< Enable */
15507 
15508 /* Bit 2 : Write '1' to enable interrupt for event RXDREADY */
15509 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
15510 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
15511 #define TWI_INTENSET_RXDREADY_Disabled (0x0UL) /*!< Read: Disabled */
15512 #define TWI_INTENSET_RXDREADY_Enabled (0x1UL) /*!< Read: Enabled */
15513 #define TWI_INTENSET_RXDREADY_Set (0x1UL) /*!< Enable */
15514 
15515 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
15516 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15517 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15518 #define TWI_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
15519 #define TWI_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
15520 #define TWI_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
15521 
15522 /* Register: TWI_INTENCLR */
15523 /* Description: Disable interrupt */
15524 
15525 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
15526 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
15527 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
15528 #define TWI_INTENCLR_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */
15529 #define TWI_INTENCLR_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */
15530 #define TWI_INTENCLR_SUSPENDED_Clear (0x1UL) /*!< Disable */
15531 
15532 /* Bit 14 : Write '1' to disable interrupt for event BB */
15533 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
15534 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
15535 #define TWI_INTENCLR_BB_Disabled (0x0UL) /*!< Read: Disabled */
15536 #define TWI_INTENCLR_BB_Enabled (0x1UL) /*!< Read: Enabled */
15537 #define TWI_INTENCLR_BB_Clear (0x1UL) /*!< Disable */
15538 
15539 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
15540 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15541 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
15542 #define TWI_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
15543 #define TWI_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
15544 #define TWI_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */
15545 
15546 /* Bit 7 : Write '1' to disable interrupt for event TXDSENT */
15547 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
15548 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
15549 #define TWI_INTENCLR_TXDSENT_Disabled (0x0UL) /*!< Read: Disabled */
15550 #define TWI_INTENCLR_TXDSENT_Enabled (0x1UL) /*!< Read: Enabled */
15551 #define TWI_INTENCLR_TXDSENT_Clear (0x1UL) /*!< Disable */
15552 
15553 /* Bit 2 : Write '1' to disable interrupt for event RXDREADY */
15554 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
15555 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
15556 #define TWI_INTENCLR_RXDREADY_Disabled (0x0UL) /*!< Read: Disabled */
15557 #define TWI_INTENCLR_RXDREADY_Enabled (0x1UL) /*!< Read: Enabled */
15558 #define TWI_INTENCLR_RXDREADY_Clear (0x1UL) /*!< Disable */
15559 
15560 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
15561 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15562 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15563 #define TWI_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
15564 #define TWI_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
15565 #define TWI_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
15566 
15567 /* Register: TWI_ERRORSRC */
15568 /* Description: Error source */
15569 
15570 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
15571 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
15572 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
15573 #define TWI_ERRORSRC_DNACK_NotPresent (0x0UL) /*!< Read: error not present */
15574 #define TWI_ERRORSRC_DNACK_Present (0x1UL) /*!< Read: error present */
15575 
15576 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
15577 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
15578 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
15579 #define TWI_ERRORSRC_ANACK_NotPresent (0x0UL) /*!< Read: error not present */
15580 #define TWI_ERRORSRC_ANACK_Present (0x1UL) /*!< Read: error present */
15581 
15582 /* Bit 0 : Overrun error */
15583 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
15584 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
15585 #define TWI_ERRORSRC_OVERRUN_NotPresent (0x0UL) /*!< Read: no overrun occured */
15586 #define TWI_ERRORSRC_OVERRUN_Present (0x1UL) /*!< Read: overrun occured */
15587 
15588 /* Register: TWI_ENABLE */
15589 /* Description: Enable TWI */
15590 
15591 /* Bits 3..0 : Enable or disable TWI */
15592 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
15593 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
15594 #define TWI_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWI */
15595 #define TWI_ENABLE_ENABLE_Enabled (0x5UL) /*!< Enable TWI */
15596 
15597 /* Register: TWI_PSEL_SCL */
15598 /* Description: Pin select for SCL */
15599 
15600 /* Bit 31 : Connection */
15601 #define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15602 #define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15603 #define TWI_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */
15604 #define TWI_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
15605 
15606 /* Bit 5 : Port number */
15607 #define TWI_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
15608 #define TWI_PSEL_SCL_PORT_Msk (0x1UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
15609 
15610 /* Bits 4..0 : Pin number */
15611 #define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
15612 #define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
15613 
15614 /* Register: TWI_PSEL_SDA */
15615 /* Description: Pin select for SDA */
15616 
15617 /* Bit 31 : Connection */
15618 #define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15619 #define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15620 #define TWI_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */
15621 #define TWI_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
15622 
15623 /* Bit 5 : Port number */
15624 #define TWI_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
15625 #define TWI_PSEL_SDA_PORT_Msk (0x1UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
15626 
15627 /* Bits 4..0 : Pin number */
15628 #define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
15629 #define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
15630 
15631 /* Register: TWI_RXD */
15632 /* Description: RXD register. Register is cleared on read and the buffer pointer will be modified if read. */
15633 
15634 /* Bits 7..0 : RXD register */
15635 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
15636 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
15637 
15638 /* Register: TWI_TXD */
15639 /* Description: TXD register */
15640 
15641 /* Bits 7..0 : TXD register */
15642 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
15643 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
15644 
15645 /* Register: TWI_FREQUENCY */
15646 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
15647 
15648 /* Bits 31..0 : TWI master clock frequency */
15649 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
15650 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
15651 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
15652 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
15653 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
15654 
15655 /* Register: TWI_ADDRESS */
15656 /* Description: Address used in the TWI transfer */
15657 
15658 /* Bits 6..0 : Address used in the TWI transfer */
15659 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
15660 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
15661 
15662 
15663 /* Peripheral: TWIM */
15664 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
15665 
15666 /* Register: TWIM_TASKS_STARTRX */
15667 /* Description: Start TWI receive sequence */
15668 
15669 /* Bit 0 : Start TWI receive sequence */
15670 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
15671 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
15672 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */
15673 
15674 /* Register: TWIM_TASKS_STARTTX */
15675 /* Description: Start TWI transmit sequence */
15676 
15677 /* Bit 0 : Start TWI transmit sequence */
15678 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
15679 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
15680 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */
15681 
15682 /* Register: TWIM_TASKS_STOP */
15683 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
15684 
15685 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
15686 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
15687 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
15688 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
15689 
15690 /* Register: TWIM_TASKS_SUSPEND */
15691 /* Description: Suspend TWI transaction */
15692 
15693 /* Bit 0 : Suspend TWI transaction */
15694 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
15695 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
15696 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */
15697 
15698 /* Register: TWIM_TASKS_RESUME */
15699 /* Description: Resume TWI transaction */
15700 
15701 /* Bit 0 : Resume TWI transaction */
15702 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
15703 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
15704 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */
15705 
15706 /* Register: TWIM_EVENTS_STOPPED */
15707 /* Description: TWI stopped */
15708 
15709 /* Bit 0 : TWI stopped */
15710 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
15711 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
15712 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
15713 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
15714 
15715 /* Register: TWIM_EVENTS_ERROR */
15716 /* Description: TWI error */
15717 
15718 /* Bit 0 : TWI error */
15719 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
15720 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
15721 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
15722 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */
15723 
15724 /* Register: TWIM_EVENTS_SUSPENDED */
15725 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */
15726 
15727 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
15728 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
15729 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
15730 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0x0UL) /*!< Event not generated */
15731 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (0x1UL) /*!< Event generated */
15732 
15733 /* Register: TWIM_EVENTS_RXSTARTED */
15734 /* Description: Receive sequence started */
15735 
15736 /* Bit 0 : Receive sequence started */
15737 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
15738 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
15739 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
15740 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */
15741 
15742 /* Register: TWIM_EVENTS_TXSTARTED */
15743 /* Description: Transmit sequence started */
15744 
15745 /* Bit 0 : Transmit sequence started */
15746 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
15747 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
15748 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
15749 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */
15750 
15751 /* Register: TWIM_EVENTS_LASTRX */
15752 /* Description: Byte boundary, starting to receive the last byte */
15753 
15754 /* Bit 0 : Byte boundary, starting to receive the last byte */
15755 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
15756 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
15757 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0x0UL) /*!< Event not generated */
15758 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (0x1UL) /*!< Event generated */
15759 
15760 /* Register: TWIM_EVENTS_LASTTX */
15761 /* Description: Byte boundary, starting to transmit the last byte */
15762 
15763 /* Bit 0 : Byte boundary, starting to transmit the last byte */
15764 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
15765 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
15766 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0x0UL) /*!< Event not generated */
15767 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (0x1UL) /*!< Event generated */
15768 
15769 /* Register: TWIM_SHORTS */
15770 /* Description: Shortcuts between local events and tasks */
15771 
15772 /* Bit 12 : Shortcut between event LASTRX and task STOP */
15773 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
15774 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
15775 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0x0UL) /*!< Disable shortcut */
15776 #define TWIM_SHORTS_LASTRX_STOP_Enabled (0x1UL) /*!< Enable shortcut */
15777 
15778 /* Bit 11 : Shortcut between event LASTRX and task SUSPEND */
15779 #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */
15780 #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */
15781 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
15782 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */
15783 
15784 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
15785 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
15786 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
15787 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0x0UL) /*!< Disable shortcut */
15788 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (0x1UL) /*!< Enable shortcut */
15789 
15790 /* Bit 9 : Shortcut between event LASTTX and task STOP */
15791 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
15792 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
15793 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0x0UL) /*!< Disable shortcut */
15794 #define TWIM_SHORTS_LASTTX_STOP_Enabled (0x1UL) /*!< Enable shortcut */
15795 
15796 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
15797 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
15798 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
15799 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
15800 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */
15801 
15802 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
15803 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
15804 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
15805 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */
15806 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */
15807 
15808 /* Register: TWIM_INTEN */
15809 /* Description: Enable or disable interrupt */
15810 
15811 /* Bit 24 : Enable or disable interrupt for event LASTTX */
15812 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
15813 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
15814 #define TWIM_INTEN_LASTTX_Disabled (0x0UL) /*!< Disable */
15815 #define TWIM_INTEN_LASTTX_Enabled (0x1UL) /*!< Enable */
15816 
15817 /* Bit 23 : Enable or disable interrupt for event LASTRX */
15818 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
15819 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
15820 #define TWIM_INTEN_LASTRX_Disabled (0x0UL) /*!< Disable */
15821 #define TWIM_INTEN_LASTRX_Enabled (0x1UL) /*!< Enable */
15822 
15823 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
15824 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15825 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15826 #define TWIM_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */
15827 #define TWIM_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */
15828 
15829 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
15830 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15831 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15832 #define TWIM_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */
15833 #define TWIM_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */
15834 
15835 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
15836 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
15837 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
15838 #define TWIM_INTEN_SUSPENDED_Disabled (0x0UL) /*!< Disable */
15839 #define TWIM_INTEN_SUSPENDED_Enabled (0x1UL) /*!< Enable */
15840 
15841 /* Bit 9 : Enable or disable interrupt for event ERROR */
15842 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15843 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
15844 #define TWIM_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
15845 #define TWIM_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */
15846 
15847 /* Bit 1 : Enable or disable interrupt for event STOPPED */
15848 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15849 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15850 #define TWIM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
15851 #define TWIM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
15852 
15853 /* Register: TWIM_INTENSET */
15854 /* Description: Enable interrupt */
15855 
15856 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
15857 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
15858 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
15859 #define TWIM_INTENSET_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */
15860 #define TWIM_INTENSET_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */
15861 #define TWIM_INTENSET_LASTTX_Set (0x1UL) /*!< Enable */
15862 
15863 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
15864 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
15865 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
15866 #define TWIM_INTENSET_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */
15867 #define TWIM_INTENSET_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */
15868 #define TWIM_INTENSET_LASTRX_Set (0x1UL) /*!< Enable */
15869 
15870 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
15871 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15872 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15873 #define TWIM_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15874 #define TWIM_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15875 #define TWIM_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */
15876 
15877 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
15878 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15879 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15880 #define TWIM_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15881 #define TWIM_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15882 #define TWIM_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */
15883 
15884 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
15885 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
15886 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
15887 #define TWIM_INTENSET_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */
15888 #define TWIM_INTENSET_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */
15889 #define TWIM_INTENSET_SUSPENDED_Set (0x1UL) /*!< Enable */
15890 
15891 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
15892 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15893 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
15894 #define TWIM_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
15895 #define TWIM_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
15896 #define TWIM_INTENSET_ERROR_Set (0x1UL) /*!< Enable */
15897 
15898 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
15899 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15900 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15901 #define TWIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
15902 #define TWIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
15903 #define TWIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
15904 
15905 /* Register: TWIM_INTENCLR */
15906 /* Description: Disable interrupt */
15907 
15908 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
15909 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
15910 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
15911 #define TWIM_INTENCLR_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */
15912 #define TWIM_INTENCLR_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */
15913 #define TWIM_INTENCLR_LASTTX_Clear (0x1UL) /*!< Disable */
15914 
15915 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
15916 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
15917 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
15918 #define TWIM_INTENCLR_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */
15919 #define TWIM_INTENCLR_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */
15920 #define TWIM_INTENCLR_LASTRX_Clear (0x1UL) /*!< Disable */
15921 
15922 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
15923 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15924 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15925 #define TWIM_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15926 #define TWIM_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15927 #define TWIM_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */
15928 
15929 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
15930 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15931 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15932 #define TWIM_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
15933 #define TWIM_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
15934 #define TWIM_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */
15935 
15936 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
15937 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
15938 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
15939 #define TWIM_INTENCLR_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */
15940 #define TWIM_INTENCLR_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */
15941 #define TWIM_INTENCLR_SUSPENDED_Clear (0x1UL) /*!< Disable */
15942 
15943 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
15944 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15945 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
15946 #define TWIM_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
15947 #define TWIM_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
15948 #define TWIM_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */
15949 
15950 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
15951 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15952 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15953 #define TWIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
15954 #define TWIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
15955 #define TWIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
15956 
15957 /* Register: TWIM_ERRORSRC */
15958 /* Description: Error source */
15959 
15960 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
15961 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
15962 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
15963 #define TWIM_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */
15964 #define TWIM_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */
15965 
15966 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
15967 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
15968 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
15969 #define TWIM_ERRORSRC_ANACK_NotReceived (0x0UL) /*!< Error did not occur */
15970 #define TWIM_ERRORSRC_ANACK_Received (0x1UL) /*!< Error occurred */
15971 
15972 /* Bit 0 : Overrun error */
15973 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
15974 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
15975 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0x0UL) /*!< Error did not occur */
15976 #define TWIM_ERRORSRC_OVERRUN_Received (0x1UL) /*!< Error occurred */
15977 
15978 /* Register: TWIM_ENABLE */
15979 /* Description: Enable TWIM */
15980 
15981 /* Bits 3..0 : Enable or disable TWIM */
15982 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
15983 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
15984 #define TWIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIM */
15985 #define TWIM_ENABLE_ENABLE_Enabled (0x6UL) /*!< Enable TWIM */
15986 
15987 /* Register: TWIM_PSEL_SCL */
15988 /* Description: Pin select for SCL signal */
15989 
15990 /* Bit 31 : Connection */
15991 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15992 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15993 #define TWIM_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */
15994 #define TWIM_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
15995 
15996 /* Bit 5 : Port number */
15997 #define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
15998 #define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
15999 
16000 /* Bits 4..0 : Pin number */
16001 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
16002 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
16003 
16004 /* Register: TWIM_PSEL_SDA */
16005 /* Description: Pin select for SDA signal */
16006 
16007 /* Bit 31 : Connection */
16008 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16009 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16010 #define TWIM_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */
16011 #define TWIM_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
16012 
16013 /* Bit 5 : Port number */
16014 #define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
16015 #define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
16016 
16017 /* Bits 4..0 : Pin number */
16018 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
16019 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
16020 
16021 /* Register: TWIM_FREQUENCY */
16022 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
16023 
16024 /* Bits 31..0 : TWI master clock frequency */
16025 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
16026 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
16027 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
16028 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
16029 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
16030 
16031 /* Register: TWIM_RXD_PTR */
16032 /* Description: Data pointer */
16033 
16034 /* Bits 31..0 : Data pointer */
16035 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16036 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16037 
16038 /* Register: TWIM_RXD_MAXCNT */
16039 /* Description: Maximum number of bytes in receive buffer */
16040 
16041 /* Bits 15..0 : Maximum number of bytes in receive buffer */
16042 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16043 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16044 
16045 /* Register: TWIM_RXD_AMOUNT */
16046 /* Description: Number of bytes transferred in the last transaction */
16047 
16048 /* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
16049 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16050 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16051 
16052 /* Register: TWIM_RXD_LIST */
16053 /* Description: EasyDMA list type */
16054 
16055 /* Bits 2..0 : List type */
16056 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
16057 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
16058 #define TWIM_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
16059 #define TWIM_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
16060 
16061 /* Register: TWIM_TXD_PTR */
16062 /* Description: Data pointer */
16063 
16064 /* Bits 31..0 : Data pointer */
16065 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16066 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16067 
16068 /* Register: TWIM_TXD_MAXCNT */
16069 /* Description: Maximum number of bytes in transmit buffer */
16070 
16071 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
16072 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16073 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16074 
16075 /* Register: TWIM_TXD_AMOUNT */
16076 /* Description: Number of bytes transferred in the last transaction */
16077 
16078 /* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
16079 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16080 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16081 
16082 /* Register: TWIM_TXD_LIST */
16083 /* Description: EasyDMA list type */
16084 
16085 /* Bits 2..0 : List type */
16086 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
16087 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
16088 #define TWIM_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
16089 #define TWIM_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
16090 
16091 /* Register: TWIM_ADDRESS */
16092 /* Description: Address used in the TWI transfer */
16093 
16094 /* Bits 6..0 : Address used in the TWI transfer */
16095 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
16096 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
16097 
16098 
16099 /* Peripheral: TWIS */
16100 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
16101 
16102 /* Register: TWIS_TASKS_STOP */
16103 /* Description: Stop TWI transaction */
16104 
16105 /* Bit 0 : Stop TWI transaction */
16106 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
16107 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
16108 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */
16109 
16110 /* Register: TWIS_TASKS_SUSPEND */
16111 /* Description: Suspend TWI transaction */
16112 
16113 /* Bit 0 : Suspend TWI transaction */
16114 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
16115 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
16116 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */
16117 
16118 /* Register: TWIS_TASKS_RESUME */
16119 /* Description: Resume TWI transaction */
16120 
16121 /* Bit 0 : Resume TWI transaction */
16122 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
16123 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
16124 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */
16125 
16126 /* Register: TWIS_TASKS_PREPARERX */
16127 /* Description: Prepare the TWI slave to respond to a write command */
16128 
16129 /* Bit 0 : Prepare the TWI slave to respond to a write command */
16130 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
16131 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
16132 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (0x1UL) /*!< Trigger task */
16133 
16134 /* Register: TWIS_TASKS_PREPARETX */
16135 /* Description: Prepare the TWI slave to respond to a read command */
16136 
16137 /* Bit 0 : Prepare the TWI slave to respond to a read command */
16138 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
16139 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
16140 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (0x1UL) /*!< Trigger task */
16141 
16142 /* Register: TWIS_EVENTS_STOPPED */
16143 /* Description: TWI stopped */
16144 
16145 /* Bit 0 : TWI stopped */
16146 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
16147 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
16148 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
16149 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */
16150 
16151 /* Register: TWIS_EVENTS_ERROR */
16152 /* Description: TWI error */
16153 
16154 /* Bit 0 : TWI error */
16155 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
16156 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
16157 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
16158 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */
16159 
16160 /* Register: TWIS_EVENTS_RXSTARTED */
16161 /* Description: Receive sequence started */
16162 
16163 /* Bit 0 : Receive sequence started */
16164 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
16165 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
16166 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
16167 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */
16168 
16169 /* Register: TWIS_EVENTS_TXSTARTED */
16170 /* Description: Transmit sequence started */
16171 
16172 /* Bit 0 : Transmit sequence started */
16173 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
16174 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
16175 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
16176 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */
16177 
16178 /* Register: TWIS_EVENTS_WRITE */
16179 /* Description: Write command received */
16180 
16181 /* Bit 0 : Write command received */
16182 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
16183 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
16184 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0x0UL) /*!< Event not generated */
16185 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (0x1UL) /*!< Event generated */
16186 
16187 /* Register: TWIS_EVENTS_READ */
16188 /* Description: Read command received */
16189 
16190 /* Bit 0 : Read command received */
16191 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
16192 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
16193 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0x0UL) /*!< Event not generated */
16194 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (0x1UL) /*!< Event generated */
16195 
16196 /* Register: TWIS_SHORTS */
16197 /* Description: Shortcuts between local events and tasks */
16198 
16199 /* Bit 14 : Shortcut between event READ and task SUSPEND */
16200 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
16201 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
16202 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
16203 #define TWIS_SHORTS_READ_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */
16204 
16205 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
16206 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
16207 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
16208 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
16209 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */
16210 
16211 /* Register: TWIS_INTEN */
16212 /* Description: Enable or disable interrupt */
16213 
16214 /* Bit 26 : Enable or disable interrupt for event READ */
16215 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
16216 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
16217 #define TWIS_INTEN_READ_Disabled (0x0UL) /*!< Disable */
16218 #define TWIS_INTEN_READ_Enabled (0x1UL) /*!< Enable */
16219 
16220 /* Bit 25 : Enable or disable interrupt for event WRITE */
16221 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
16222 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
16223 #define TWIS_INTEN_WRITE_Disabled (0x0UL) /*!< Disable */
16224 #define TWIS_INTEN_WRITE_Enabled (0x1UL) /*!< Enable */
16225 
16226 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
16227 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
16228 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
16229 #define TWIS_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */
16230 #define TWIS_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */
16231 
16232 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
16233 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
16234 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
16235 #define TWIS_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */
16236 #define TWIS_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */
16237 
16238 /* Bit 9 : Enable or disable interrupt for event ERROR */
16239 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
16240 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
16241 #define TWIS_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
16242 #define TWIS_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */
16243 
16244 /* Bit 1 : Enable or disable interrupt for event STOPPED */
16245 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
16246 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
16247 #define TWIS_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
16248 #define TWIS_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */
16249 
16250 /* Register: TWIS_INTENSET */
16251 /* Description: Enable interrupt */
16252 
16253 /* Bit 26 : Write '1' to enable interrupt for event READ */
16254 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
16255 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
16256 #define TWIS_INTENSET_READ_Disabled (0x0UL) /*!< Read: Disabled */
16257 #define TWIS_INTENSET_READ_Enabled (0x1UL) /*!< Read: Enabled */
16258 #define TWIS_INTENSET_READ_Set (0x1UL) /*!< Enable */
16259 
16260 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
16261 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
16262 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
16263 #define TWIS_INTENSET_WRITE_Disabled (0x0UL) /*!< Read: Disabled */
16264 #define TWIS_INTENSET_WRITE_Enabled (0x1UL) /*!< Read: Enabled */
16265 #define TWIS_INTENSET_WRITE_Set (0x1UL) /*!< Enable */
16266 
16267 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
16268 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
16269 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
16270 #define TWIS_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
16271 #define TWIS_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
16272 #define TWIS_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */
16273 
16274 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
16275 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
16276 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
16277 #define TWIS_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
16278 #define TWIS_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
16279 #define TWIS_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */
16280 
16281 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
16282 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
16283 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
16284 #define TWIS_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
16285 #define TWIS_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
16286 #define TWIS_INTENSET_ERROR_Set (0x1UL) /*!< Enable */
16287 
16288 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
16289 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
16290 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
16291 #define TWIS_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
16292 #define TWIS_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
16293 #define TWIS_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */
16294 
16295 /* Register: TWIS_INTENCLR */
16296 /* Description: Disable interrupt */
16297 
16298 /* Bit 26 : Write '1' to disable interrupt for event READ */
16299 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
16300 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
16301 #define TWIS_INTENCLR_READ_Disabled (0x0UL) /*!< Read: Disabled */
16302 #define TWIS_INTENCLR_READ_Enabled (0x1UL) /*!< Read: Enabled */
16303 #define TWIS_INTENCLR_READ_Clear (0x1UL) /*!< Disable */
16304 
16305 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
16306 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
16307 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
16308 #define TWIS_INTENCLR_WRITE_Disabled (0x0UL) /*!< Read: Disabled */
16309 #define TWIS_INTENCLR_WRITE_Enabled (0x1UL) /*!< Read: Enabled */
16310 #define TWIS_INTENCLR_WRITE_Clear (0x1UL) /*!< Disable */
16311 
16312 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
16313 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
16314 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
16315 #define TWIS_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
16316 #define TWIS_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
16317 #define TWIS_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */
16318 
16319 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
16320 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
16321 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
16322 #define TWIS_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
16323 #define TWIS_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
16324 #define TWIS_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */
16325 
16326 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
16327 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
16328 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
16329 #define TWIS_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
16330 #define TWIS_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
16331 #define TWIS_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */
16332 
16333 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
16334 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
16335 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
16336 #define TWIS_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
16337 #define TWIS_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
16338 #define TWIS_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */
16339 
16340 /* Register: TWIS_ERRORSRC */
16341 /* Description: Error source */
16342 
16343 /* Bit 3 : TX buffer over-read detected, and prevented */
16344 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
16345 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
16346 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0x0UL) /*!< Error did not occur */
16347 #define TWIS_ERRORSRC_OVERREAD_Detected (0x1UL) /*!< Error occurred */
16348 
16349 /* Bit 2 : NACK sent after receiving a data byte */
16350 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
16351 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
16352 #define TWIS_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */
16353 #define TWIS_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */
16354 
16355 /* Bit 0 : RX buffer overflow detected, and prevented */
16356 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
16357 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
16358 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0x0UL) /*!< Error did not occur */
16359 #define TWIS_ERRORSRC_OVERFLOW_Detected (0x1UL) /*!< Error occurred */
16360 
16361 /* Register: TWIS_MATCH */
16362 /* Description: Status register indicating which address had a match */
16363 
16364 /* Bit 0 : Indication of which address in ADDRESS that matched the incoming address */
16365 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
16366 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
16367 
16368 /* Register: TWIS_ENABLE */
16369 /* Description: Enable TWIS */
16370 
16371 /* Bits 3..0 : Enable or disable TWIS */
16372 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
16373 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
16374 #define TWIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIS */
16375 #define TWIS_ENABLE_ENABLE_Enabled (0x9UL) /*!< Enable TWIS */
16376 
16377 /* Register: TWIS_PSEL_SCL */
16378 /* Description: Pin select for SCL signal */
16379 
16380 /* Bit 31 : Connection */
16381 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16382 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16383 #define TWIS_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */
16384 #define TWIS_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
16385 
16386 /* Bit 5 : Port number */
16387 #define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
16388 #define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
16389 
16390 /* Bits 4..0 : Pin number */
16391 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
16392 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
16393 
16394 /* Register: TWIS_PSEL_SDA */
16395 /* Description: Pin select for SDA signal */
16396 
16397 /* Bit 31 : Connection */
16398 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16399 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16400 #define TWIS_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */
16401 #define TWIS_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
16402 
16403 /* Bit 5 : Port number */
16404 #define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
16405 #define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
16406 
16407 /* Bits 4..0 : Pin number */
16408 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
16409 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
16410 
16411 /* Register: TWIS_RXD_PTR */
16412 /* Description: RXD Data pointer */
16413 
16414 /* Bits 31..0 : RXD Data pointer */
16415 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16416 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16417 
16418 /* Register: TWIS_RXD_MAXCNT */
16419 /* Description: Maximum number of bytes in RXD buffer */
16420 
16421 /* Bits 15..0 : Maximum number of bytes in RXD buffer */
16422 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16423 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16424 
16425 /* Register: TWIS_RXD_AMOUNT */
16426 /* Description: Number of bytes transferred in the last RXD transaction */
16427 
16428 /* Bits 15..0 : Number of bytes transferred in the last RXD transaction */
16429 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16430 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16431 
16432 /* Register: TWIS_RXD_LIST */
16433 /* Description: EasyDMA list type */
16434 
16435 /* Bits 1..0 : List type */
16436 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
16437 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
16438 #define TWIS_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
16439 #define TWIS_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
16440 
16441 /* Register: TWIS_TXD_PTR */
16442 /* Description: TXD Data pointer */
16443 
16444 /* Bits 31..0 : TXD Data pointer */
16445 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16446 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16447 
16448 /* Register: TWIS_TXD_MAXCNT */
16449 /* Description: Maximum number of bytes in TXD buffer */
16450 
16451 /* Bits 15..0 : Maximum number of bytes in TXD buffer */
16452 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16453 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16454 
16455 /* Register: TWIS_TXD_AMOUNT */
16456 /* Description: Number of bytes transferred in the last TXD transaction */
16457 
16458 /* Bits 15..0 : Number of bytes transferred in the last TXD transaction */
16459 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16460 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16461 
16462 /* Register: TWIS_TXD_LIST */
16463 /* Description: EasyDMA list type */
16464 
16465 /* Bits 1..0 : List type */
16466 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
16467 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
16468 #define TWIS_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
16469 #define TWIS_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */
16470 
16471 /* Register: TWIS_ADDRESS */
16472 /* Description: Description collection: TWI slave address n */
16473 
16474 /* Bits 6..0 : TWI slave address */
16475 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
16476 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
16477 
16478 /* Register: TWIS_CONFIG */
16479 /* Description: Configuration register for the address match mechanism */
16480 
16481 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
16482 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
16483 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
16484 #define TWIS_CONFIG_ADDRESS1_Disabled (0x0UL) /*!< Disabled */
16485 #define TWIS_CONFIG_ADDRESS1_Enabled (0x1UL) /*!< Enabled */
16486 
16487 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
16488 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
16489 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
16490 #define TWIS_CONFIG_ADDRESS0_Disabled (0x0UL) /*!< Disabled */
16491 #define TWIS_CONFIG_ADDRESS0_Enabled (0x1UL) /*!< Enabled */
16492 
16493 /* Register: TWIS_ORC */
16494 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
16495 
16496 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
16497 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
16498 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
16499 
16500 
16501 /* Peripheral: UART */
16502 /* Description: Universal Asynchronous Receiver/Transmitter */
16503 
16504 /* Register: UART_TASKS_STARTRX */
16505 /* Description: Start UART receiver */
16506 
16507 /* Bit 0 : Start UART receiver */
16508 #define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
16509 #define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
16510 #define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */
16511 
16512 /* Register: UART_TASKS_STOPRX */
16513 /* Description: Stop UART receiver */
16514 
16515 /* Bit 0 : Stop UART receiver */
16516 #define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
16517 #define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
16518 #define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (0x1UL) /*!< Trigger task */
16519 
16520 /* Register: UART_TASKS_STARTTX */
16521 /* Description: Start UART transmitter */
16522 
16523 /* Bit 0 : Start UART transmitter */
16524 #define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
16525 #define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
16526 #define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */
16527 
16528 /* Register: UART_TASKS_STOPTX */
16529 /* Description: Stop UART transmitter */
16530 
16531 /* Bit 0 : Stop UART transmitter */
16532 #define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
16533 #define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
16534 #define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (0x1UL) /*!< Trigger task */
16535 
16536 /* Register: UART_TASKS_SUSPEND */
16537 /* Description: Suspend UART */
16538 
16539 /* Bit 0 : Suspend UART */
16540 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
16541 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
16542 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */
16543 
16544 /* Register: UART_EVENTS_CTS */
16545 /* Description: CTS is activated (set low). Clear To Send. */
16546 
16547 /* Bit 0 : CTS is activated (set low). Clear To Send. */
16548 #define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
16549 #define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
16550 #define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0x0UL) /*!< Event not generated */
16551 #define UART_EVENTS_CTS_EVENTS_CTS_Generated (0x1UL) /*!< Event generated */
16552 
16553 /* Register: UART_EVENTS_NCTS */
16554 /* Description: CTS is deactivated (set high). Not Clear To Send. */
16555 
16556 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
16557 #define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
16558 #define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
16559 #define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0x0UL) /*!< Event not generated */
16560 #define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (0x1UL) /*!< Event generated */
16561 
16562 /* Register: UART_EVENTS_RXDRDY */
16563 /* Description: Data received in RXD */
16564 
16565 /* Bit 0 : Data received in RXD */
16566 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
16567 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
16568 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0x0UL) /*!< Event not generated */
16569 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (0x1UL) /*!< Event generated */
16570 
16571 /* Register: UART_EVENTS_TXDRDY */
16572 /* Description: Data sent from TXD */
16573 
16574 /* Bit 0 : Data sent from TXD */
16575 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
16576 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
16577 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0x0UL) /*!< Event not generated */
16578 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (0x1UL) /*!< Event generated */
16579 
16580 /* Register: UART_EVENTS_ERROR */
16581 /* Description: Error detected */
16582 
16583 /* Bit 0 : Error detected */
16584 #define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
16585 #define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
16586 #define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
16587 #define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */
16588 
16589 /* Register: UART_EVENTS_RXTO */
16590 /* Description: Receiver timeout */
16591 
16592 /* Bit 0 : Receiver timeout */
16593 #define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
16594 #define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
16595 #define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0x0UL) /*!< Event not generated */
16596 #define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (0x1UL) /*!< Event generated */
16597 
16598 /* Register: UART_SHORTS */
16599 /* Description: Shortcuts between local events and tasks */
16600 
16601 /* Bit 4 : Shortcut between event NCTS and task STOPRX */
16602 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
16603 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
16604 #define UART_SHORTS_NCTS_STOPRX_Disabled (0x0UL) /*!< Disable shortcut */
16605 #define UART_SHORTS_NCTS_STOPRX_Enabled (0x1UL) /*!< Enable shortcut */
16606 
16607 /* Bit 3 : Shortcut between event CTS and task STARTRX */
16608 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
16609 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
16610 #define UART_SHORTS_CTS_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */
16611 #define UART_SHORTS_CTS_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */
16612 
16613 /* Register: UART_INTENSET */
16614 /* Description: Enable interrupt */
16615 
16616 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
16617 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
16618 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
16619 #define UART_INTENSET_RXTO_Disabled (0x0UL) /*!< Read: Disabled */
16620 #define UART_INTENSET_RXTO_Enabled (0x1UL) /*!< Read: Enabled */
16621 #define UART_INTENSET_RXTO_Set (0x1UL) /*!< Enable */
16622 
16623 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
16624 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
16625 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
16626 #define UART_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
16627 #define UART_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
16628 #define UART_INTENSET_ERROR_Set (0x1UL) /*!< Enable */
16629 
16630 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
16631 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
16632 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
16633 #define UART_INTENSET_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
16634 #define UART_INTENSET_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
16635 #define UART_INTENSET_TXDRDY_Set (0x1UL) /*!< Enable */
16636 
16637 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
16638 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
16639 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
16640 #define UART_INTENSET_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
16641 #define UART_INTENSET_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
16642 #define UART_INTENSET_RXDRDY_Set (0x1UL) /*!< Enable */
16643 
16644 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
16645 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
16646 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
16647 #define UART_INTENSET_NCTS_Disabled (0x0UL) /*!< Read: Disabled */
16648 #define UART_INTENSET_NCTS_Enabled (0x1UL) /*!< Read: Enabled */
16649 #define UART_INTENSET_NCTS_Set (0x1UL) /*!< Enable */
16650 
16651 /* Bit 0 : Write '1' to enable interrupt for event CTS */
16652 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
16653 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
16654 #define UART_INTENSET_CTS_Disabled (0x0UL) /*!< Read: Disabled */
16655 #define UART_INTENSET_CTS_Enabled (0x1UL) /*!< Read: Enabled */
16656 #define UART_INTENSET_CTS_Set (0x1UL) /*!< Enable */
16657 
16658 /* Register: UART_INTENCLR */
16659 /* Description: Disable interrupt */
16660 
16661 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
16662 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
16663 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
16664 #define UART_INTENCLR_RXTO_Disabled (0x0UL) /*!< Read: Disabled */
16665 #define UART_INTENCLR_RXTO_Enabled (0x1UL) /*!< Read: Enabled */
16666 #define UART_INTENCLR_RXTO_Clear (0x1UL) /*!< Disable */
16667 
16668 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
16669 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
16670 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
16671 #define UART_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
16672 #define UART_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
16673 #define UART_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */
16674 
16675 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
16676 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
16677 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
16678 #define UART_INTENCLR_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
16679 #define UART_INTENCLR_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
16680 #define UART_INTENCLR_TXDRDY_Clear (0x1UL) /*!< Disable */
16681 
16682 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
16683 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
16684 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
16685 #define UART_INTENCLR_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
16686 #define UART_INTENCLR_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
16687 #define UART_INTENCLR_RXDRDY_Clear (0x1UL) /*!< Disable */
16688 
16689 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
16690 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
16691 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
16692 #define UART_INTENCLR_NCTS_Disabled (0x0UL) /*!< Read: Disabled */
16693 #define UART_INTENCLR_NCTS_Enabled (0x1UL) /*!< Read: Enabled */
16694 #define UART_INTENCLR_NCTS_Clear (0x1UL) /*!< Disable */
16695 
16696 /* Bit 0 : Write '1' to disable interrupt for event CTS */
16697 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
16698 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
16699 #define UART_INTENCLR_CTS_Disabled (0x0UL) /*!< Read: Disabled */
16700 #define UART_INTENCLR_CTS_Enabled (0x1UL) /*!< Read: Enabled */
16701 #define UART_INTENCLR_CTS_Clear (0x1UL) /*!< Disable */
16702 
16703 /* Register: UART_ERRORSRC */
16704 /* Description: Error source */
16705 
16706 /* Bit 3 : Break condition */
16707 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
16708 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
16709 #define UART_ERRORSRC_BREAK_NotPresent (0x0UL) /*!< Read: error not present */
16710 #define UART_ERRORSRC_BREAK_Present (0x1UL) /*!< Read: error present */
16711 
16712 /* Bit 2 : Framing error occurred */
16713 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
16714 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
16715 #define UART_ERRORSRC_FRAMING_NotPresent (0x0UL) /*!< Read: error not present */
16716 #define UART_ERRORSRC_FRAMING_Present (0x1UL) /*!< Read: error present */
16717 
16718 /* Bit 1 : Parity error */
16719 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
16720 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
16721 #define UART_ERRORSRC_PARITY_NotPresent (0x0UL) /*!< Read: error not present */
16722 #define UART_ERRORSRC_PARITY_Present (0x1UL) /*!< Read: error present */
16723 
16724 /* Bit 0 : Overrun error */
16725 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
16726 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
16727 #define UART_ERRORSRC_OVERRUN_NotPresent (0x0UL) /*!< Read: error not present */
16728 #define UART_ERRORSRC_OVERRUN_Present (0x1UL) /*!< Read: error present */
16729 
16730 /* Register: UART_ENABLE */
16731 /* Description: Enable UART */
16732 
16733 /* Bits 3..0 : Enable or disable UART */
16734 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
16735 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
16736 #define UART_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable UART */
16737 #define UART_ENABLE_ENABLE_Enabled (0x4UL) /*!< Enable UART */
16738 
16739 /* Register: UART_PSEL_RTS */
16740 /* Description: Pin select for RTS */
16741 
16742 /* Bit 31 : Connection */
16743 #define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16744 #define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16745 #define UART_PSEL_RTS_CONNECT_Connected (0x0UL) /*!< Connect */
16746 #define UART_PSEL_RTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
16747 
16748 /* Bit 5 : Port number */
16749 #define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
16750 #define UART_PSEL_RTS_PORT_Msk (0x1UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
16751 
16752 /* Bits 4..0 : Pin number */
16753 #define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
16754 #define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
16755 
16756 /* Register: UART_PSEL_TXD */
16757 /* Description: Pin select for TXD */
16758 
16759 /* Bit 31 : Connection */
16760 #define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16761 #define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16762 #define UART_PSEL_TXD_CONNECT_Connected (0x0UL) /*!< Connect */
16763 #define UART_PSEL_TXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
16764 
16765 /* Bit 5 : Port number */
16766 #define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
16767 #define UART_PSEL_TXD_PORT_Msk (0x1UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
16768 
16769 /* Bits 4..0 : Pin number */
16770 #define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
16771 #define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
16772 
16773 /* Register: UART_PSEL_CTS */
16774 /* Description: Pin select for CTS */
16775 
16776 /* Bit 31 : Connection */
16777 #define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16778 #define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16779 #define UART_PSEL_CTS_CONNECT_Connected (0x0UL) /*!< Connect */
16780 #define UART_PSEL_CTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
16781 
16782 /* Bit 5 : Port number */
16783 #define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
16784 #define UART_PSEL_CTS_PORT_Msk (0x1UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
16785 
16786 /* Bits 4..0 : Pin number */
16787 #define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
16788 #define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
16789 
16790 /* Register: UART_PSEL_RXD */
16791 /* Description: Pin select for RXD */
16792 
16793 /* Bit 31 : Connection */
16794 #define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16795 #define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16796 #define UART_PSEL_RXD_CONNECT_Connected (0x0UL) /*!< Connect */
16797 #define UART_PSEL_RXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
16798 
16799 /* Bit 5 : Port number */
16800 #define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
16801 #define UART_PSEL_RXD_PORT_Msk (0x1UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
16802 
16803 /* Bits 4..0 : Pin number */
16804 #define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
16805 #define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
16806 
16807 /* Register: UART_RXD */
16808 /* Description: RXD register. Register is cleared on read and the double buffered byte will be moved to RXD if it exists. */
16809 
16810 /* Bits 7..0 : RX data received in previous transfers, double buffered */
16811 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
16812 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
16813 
16814 /* Register: UART_TXD */
16815 /* Description: TXD register */
16816 
16817 /* Bits 7..0 : TX data to be transferred */
16818 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
16819 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
16820 
16821 /* Register: UART_BAUDRATE */
16822 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
16823 
16824 /* Bits 31..0 : Baud rate */
16825 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
16826 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
16827 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
16828 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
16829 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
16830 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
16831 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
16832 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
16833 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
16834 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
16835 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
16836 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
16837 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
16838 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
16839 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
16840 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
16841 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
16842 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
16843 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
16844 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
16845 
16846 /* Register: UART_CONFIG */
16847 /* Description: Configuration of parity and hardware flow control */
16848 
16849 /* Bit 4 : Stop bits */
16850 #define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
16851 #define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
16852 #define UART_CONFIG_STOP_One (0x0UL) /*!< One stop bit */
16853 #define UART_CONFIG_STOP_Two (0x1UL) /*!< Two stop bits */
16854 
16855 /* Bits 3..1 : Parity */
16856 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
16857 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
16858 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
16859 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
16860 
16861 /* Bit 0 : Hardware flow control */
16862 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
16863 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
16864 #define UART_CONFIG_HWFC_Disabled (0x0UL) /*!< Disabled */
16865 #define UART_CONFIG_HWFC_Enabled (0x1UL) /*!< Enabled */
16866 
16867 
16868 /* Peripheral: UARTE */
16869 /* Description: UART with EasyDMA 0 */
16870 
16871 /* Register: UARTE_TASKS_STARTRX */
16872 /* Description: Start UART receiver */
16873 
16874 /* Bit 0 : Start UART receiver */
16875 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
16876 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
16877 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */
16878 
16879 /* Register: UARTE_TASKS_STOPRX */
16880 /* Description: Stop UART receiver */
16881 
16882 /* Bit 0 : Stop UART receiver */
16883 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
16884 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
16885 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (0x1UL) /*!< Trigger task */
16886 
16887 /* Register: UARTE_TASKS_STARTTX */
16888 /* Description: Start UART transmitter */
16889 
16890 /* Bit 0 : Start UART transmitter */
16891 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
16892 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
16893 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */
16894 
16895 /* Register: UARTE_TASKS_STOPTX */
16896 /* Description: Stop UART transmitter */
16897 
16898 /* Bit 0 : Stop UART transmitter */
16899 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
16900 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
16901 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (0x1UL) /*!< Trigger task */
16902 
16903 /* Register: UARTE_TASKS_FLUSHRX */
16904 /* Description: Flush RX FIFO into RX buffer */
16905 
16906 /* Bit 0 : Flush RX FIFO into RX buffer */
16907 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
16908 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
16909 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (0x1UL) /*!< Trigger task */
16910 
16911 /* Register: UARTE_EVENTS_CTS */
16912 /* Description: CTS is activated (set low). Clear To Send. */
16913 
16914 /* Bit 0 : CTS is activated (set low). Clear To Send. */
16915 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
16916 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
16917 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0x0UL) /*!< Event not generated */
16918 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (0x1UL) /*!< Event generated */
16919 
16920 /* Register: UARTE_EVENTS_NCTS */
16921 /* Description: CTS is deactivated (set high). Not Clear To Send. */
16922 
16923 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
16924 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
16925 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
16926 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0x0UL) /*!< Event not generated */
16927 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (0x1UL) /*!< Event generated */
16928 
16929 /* Register: UARTE_EVENTS_RXDRDY */
16930 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
16931 
16932 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
16933 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
16934 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
16935 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0x0UL) /*!< Event not generated */
16936 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (0x1UL) /*!< Event generated */
16937 
16938 /* Register: UARTE_EVENTS_ENDRX */
16939 /* Description: Receive buffer is filled up */
16940 
16941 /* Bit 0 : Receive buffer is filled up */
16942 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
16943 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
16944 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
16945 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */
16946 
16947 /* Register: UARTE_EVENTS_TXDRDY */
16948 /* Description: Data sent from TXD */
16949 
16950 /* Bit 0 : Data sent from TXD */
16951 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
16952 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
16953 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0x0UL) /*!< Event not generated */
16954 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (0x1UL) /*!< Event generated */
16955 
16956 /* Register: UARTE_EVENTS_ENDTX */
16957 /* Description: Last TX byte transmitted */
16958 
16959 /* Bit 0 : Last TX byte transmitted */
16960 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
16961 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
16962 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */
16963 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */
16964 
16965 /* Register: UARTE_EVENTS_ERROR */
16966 /* Description: Error detected */
16967 
16968 /* Bit 0 : Error detected */
16969 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
16970 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
16971 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
16972 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */
16973 
16974 /* Register: UARTE_EVENTS_RXTO */
16975 /* Description: Receiver timeout */
16976 
16977 /* Bit 0 : Receiver timeout */
16978 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
16979 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
16980 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0x0UL) /*!< Event not generated */
16981 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (0x1UL) /*!< Event generated */
16982 
16983 /* Register: UARTE_EVENTS_RXSTARTED */
16984 /* Description: UART receiver has started */
16985 
16986 /* Bit 0 : UART receiver has started */
16987 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
16988 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
16989 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
16990 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */
16991 
16992 /* Register: UARTE_EVENTS_TXSTARTED */
16993 /* Description: UART transmitter has started */
16994 
16995 /* Bit 0 : UART transmitter has started */
16996 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
16997 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
16998 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
16999 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */
17000 
17001 /* Register: UARTE_EVENTS_TXSTOPPED */
17002 /* Description: Transmitter stopped */
17003 
17004 /* Bit 0 : Transmitter stopped */
17005 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
17006 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
17007 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */
17008 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (0x1UL) /*!< Event generated */
17009 
17010 /* Register: UARTE_SHORTS */
17011 /* Description: Shortcuts between local events and tasks */
17012 
17013 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
17014 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
17015 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
17016 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0x0UL) /*!< Disable shortcut */
17017 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (0x1UL) /*!< Enable shortcut */
17018 
17019 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
17020 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
17021 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
17022 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */
17023 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */
17024 
17025 /* Register: UARTE_INTEN */
17026 /* Description: Enable or disable interrupt */
17027 
17028 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
17029 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
17030 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
17031 #define UARTE_INTEN_TXSTOPPED_Disabled (0x0UL) /*!< Disable */
17032 #define UARTE_INTEN_TXSTOPPED_Enabled (0x1UL) /*!< Enable */
17033 
17034 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
17035 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
17036 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
17037 #define UARTE_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */
17038 #define UARTE_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */
17039 
17040 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
17041 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
17042 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
17043 #define UARTE_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */
17044 #define UARTE_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */
17045 
17046 /* Bit 17 : Enable or disable interrupt for event RXTO */
17047 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
17048 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
17049 #define UARTE_INTEN_RXTO_Disabled (0x0UL) /*!< Disable */
17050 #define UARTE_INTEN_RXTO_Enabled (0x1UL) /*!< Enable */
17051 
17052 /* Bit 9 : Enable or disable interrupt for event ERROR */
17053 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
17054 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
17055 #define UARTE_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
17056 #define UARTE_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */
17057 
17058 /* Bit 8 : Enable or disable interrupt for event ENDTX */
17059 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
17060 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
17061 #define UARTE_INTEN_ENDTX_Disabled (0x0UL) /*!< Disable */
17062 #define UARTE_INTEN_ENDTX_Enabled (0x1UL) /*!< Enable */
17063 
17064 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
17065 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
17066 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
17067 #define UARTE_INTEN_TXDRDY_Disabled (0x0UL) /*!< Disable */
17068 #define UARTE_INTEN_TXDRDY_Enabled (0x1UL) /*!< Enable */
17069 
17070 /* Bit 4 : Enable or disable interrupt for event ENDRX */
17071 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
17072 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
17073 #define UARTE_INTEN_ENDRX_Disabled (0x0UL) /*!< Disable */
17074 #define UARTE_INTEN_ENDRX_Enabled (0x1UL) /*!< Enable */
17075 
17076 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
17077 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
17078 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
17079 #define UARTE_INTEN_RXDRDY_Disabled (0x0UL) /*!< Disable */
17080 #define UARTE_INTEN_RXDRDY_Enabled (0x1UL) /*!< Enable */
17081 
17082 /* Bit 1 : Enable or disable interrupt for event NCTS */
17083 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
17084 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
17085 #define UARTE_INTEN_NCTS_Disabled (0x0UL) /*!< Disable */
17086 #define UARTE_INTEN_NCTS_Enabled (0x1UL) /*!< Enable */
17087 
17088 /* Bit 0 : Enable or disable interrupt for event CTS */
17089 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
17090 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
17091 #define UARTE_INTEN_CTS_Disabled (0x0UL) /*!< Disable */
17092 #define UARTE_INTEN_CTS_Enabled (0x1UL) /*!< Enable */
17093 
17094 /* Register: UARTE_INTENSET */
17095 /* Description: Enable interrupt */
17096 
17097 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
17098 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
17099 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
17100 #define UARTE_INTENSET_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
17101 #define UARTE_INTENSET_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
17102 #define UARTE_INTENSET_TXSTOPPED_Set (0x1UL) /*!< Enable */
17103 
17104 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
17105 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
17106 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
17107 #define UARTE_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
17108 #define UARTE_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
17109 #define UARTE_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */
17110 
17111 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
17112 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
17113 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
17114 #define UARTE_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
17115 #define UARTE_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
17116 #define UARTE_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */
17117 
17118 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
17119 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
17120 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
17121 #define UARTE_INTENSET_RXTO_Disabled (0x0UL) /*!< Read: Disabled */
17122 #define UARTE_INTENSET_RXTO_Enabled (0x1UL) /*!< Read: Enabled */
17123 #define UARTE_INTENSET_RXTO_Set (0x1UL) /*!< Enable */
17124 
17125 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
17126 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
17127 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
17128 #define UARTE_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
17129 #define UARTE_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
17130 #define UARTE_INTENSET_ERROR_Set (0x1UL) /*!< Enable */
17131 
17132 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
17133 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
17134 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
17135 #define UARTE_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
17136 #define UARTE_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
17137 #define UARTE_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */
17138 
17139 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
17140 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
17141 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
17142 #define UARTE_INTENSET_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
17143 #define UARTE_INTENSET_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
17144 #define UARTE_INTENSET_TXDRDY_Set (0x1UL) /*!< Enable */
17145 
17146 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
17147 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
17148 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
17149 #define UARTE_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
17150 #define UARTE_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
17151 #define UARTE_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */
17152 
17153 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
17154 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
17155 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
17156 #define UARTE_INTENSET_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
17157 #define UARTE_INTENSET_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
17158 #define UARTE_INTENSET_RXDRDY_Set (0x1UL) /*!< Enable */
17159 
17160 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
17161 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
17162 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
17163 #define UARTE_INTENSET_NCTS_Disabled (0x0UL) /*!< Read: Disabled */
17164 #define UARTE_INTENSET_NCTS_Enabled (0x1UL) /*!< Read: Enabled */
17165 #define UARTE_INTENSET_NCTS_Set (0x1UL) /*!< Enable */
17166 
17167 /* Bit 0 : Write '1' to enable interrupt for event CTS */
17168 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
17169 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
17170 #define UARTE_INTENSET_CTS_Disabled (0x0UL) /*!< Read: Disabled */
17171 #define UARTE_INTENSET_CTS_Enabled (0x1UL) /*!< Read: Enabled */
17172 #define UARTE_INTENSET_CTS_Set (0x1UL) /*!< Enable */
17173 
17174 /* Register: UARTE_INTENCLR */
17175 /* Description: Disable interrupt */
17176 
17177 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
17178 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
17179 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
17180 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
17181 #define UARTE_INTENCLR_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
17182 #define UARTE_INTENCLR_TXSTOPPED_Clear (0x1UL) /*!< Disable */
17183 
17184 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
17185 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
17186 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
17187 #define UARTE_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
17188 #define UARTE_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
17189 #define UARTE_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */
17190 
17191 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
17192 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
17193 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
17194 #define UARTE_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
17195 #define UARTE_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
17196 #define UARTE_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */
17197 
17198 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
17199 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
17200 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
17201 #define UARTE_INTENCLR_RXTO_Disabled (0x0UL) /*!< Read: Disabled */
17202 #define UARTE_INTENCLR_RXTO_Enabled (0x1UL) /*!< Read: Enabled */
17203 #define UARTE_INTENCLR_RXTO_Clear (0x1UL) /*!< Disable */
17204 
17205 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
17206 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
17207 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
17208 #define UARTE_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
17209 #define UARTE_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
17210 #define UARTE_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */
17211 
17212 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
17213 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
17214 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
17215 #define UARTE_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
17216 #define UARTE_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
17217 #define UARTE_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */
17218 
17219 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
17220 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
17221 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
17222 #define UARTE_INTENCLR_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
17223 #define UARTE_INTENCLR_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
17224 #define UARTE_INTENCLR_TXDRDY_Clear (0x1UL) /*!< Disable */
17225 
17226 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
17227 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
17228 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
17229 #define UARTE_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
17230 #define UARTE_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
17231 #define UARTE_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */
17232 
17233 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
17234 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
17235 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
17236 #define UARTE_INTENCLR_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
17237 #define UARTE_INTENCLR_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
17238 #define UARTE_INTENCLR_RXDRDY_Clear (0x1UL) /*!< Disable */
17239 
17240 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
17241 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
17242 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
17243 #define UARTE_INTENCLR_NCTS_Disabled (0x0UL) /*!< Read: Disabled */
17244 #define UARTE_INTENCLR_NCTS_Enabled (0x1UL) /*!< Read: Enabled */
17245 #define UARTE_INTENCLR_NCTS_Clear (0x1UL) /*!< Disable */
17246 
17247 /* Bit 0 : Write '1' to disable interrupt for event CTS */
17248 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
17249 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
17250 #define UARTE_INTENCLR_CTS_Disabled (0x0UL) /*!< Read: Disabled */
17251 #define UARTE_INTENCLR_CTS_Enabled (0x1UL) /*!< Read: Enabled */
17252 #define UARTE_INTENCLR_CTS_Clear (0x1UL) /*!< Disable */
17253 
17254 /* Register: UARTE_ERRORSRC */
17255 /* Description: Error source This register is read/write one to clear. */
17256 
17257 /* Bit 3 : Break condition */
17258 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
17259 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
17260 #define UARTE_ERRORSRC_BREAK_NotPresent (0x0UL) /*!< Read: error not present */
17261 #define UARTE_ERRORSRC_BREAK_Present (0x1UL) /*!< Read: error present */
17262 
17263 /* Bit 2 : Framing error occurred */
17264 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
17265 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
17266 #define UARTE_ERRORSRC_FRAMING_NotPresent (0x0UL) /*!< Read: error not present */
17267 #define UARTE_ERRORSRC_FRAMING_Present (0x1UL) /*!< Read: error present */
17268 
17269 /* Bit 1 : Parity error */
17270 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
17271 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
17272 #define UARTE_ERRORSRC_PARITY_NotPresent (0x0UL) /*!< Read: error not present */
17273 #define UARTE_ERRORSRC_PARITY_Present (0x1UL) /*!< Read: error present */
17274 
17275 /* Bit 0 : Overrun error */
17276 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
17277 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
17278 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0x0UL) /*!< Read: error not present */
17279 #define UARTE_ERRORSRC_OVERRUN_Present (0x1UL) /*!< Read: error present */
17280 
17281 /* Register: UARTE_ENABLE */
17282 /* Description: Enable UART */
17283 
17284 /* Bits 3..0 : Enable or disable UARTE */
17285 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
17286 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
17287 #define UARTE_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable UARTE */
17288 #define UARTE_ENABLE_ENABLE_Enabled (0x8UL) /*!< Enable UARTE */
17289 
17290 /* Register: UARTE_PSEL_RTS */
17291 /* Description: Pin select for RTS signal */
17292 
17293 /* Bit 31 : Connection */
17294 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
17295 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
17296 #define UARTE_PSEL_RTS_CONNECT_Connected (0x0UL) /*!< Connect */
17297 #define UARTE_PSEL_RTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
17298 
17299 /* Bit 5 : Port number */
17300 #define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
17301 #define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
17302 
17303 /* Bits 4..0 : Pin number */
17304 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
17305 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
17306 
17307 /* Register: UARTE_PSEL_TXD */
17308 /* Description: Pin select for TXD signal */
17309 
17310 /* Bit 31 : Connection */
17311 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
17312 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
17313 #define UARTE_PSEL_TXD_CONNECT_Connected (0x0UL) /*!< Connect */
17314 #define UARTE_PSEL_TXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
17315 
17316 /* Bit 5 : Port number */
17317 #define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
17318 #define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
17319 
17320 /* Bits 4..0 : Pin number */
17321 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
17322 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
17323 
17324 /* Register: UARTE_PSEL_CTS */
17325 /* Description: Pin select for CTS signal */
17326 
17327 /* Bit 31 : Connection */
17328 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
17329 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
17330 #define UARTE_PSEL_CTS_CONNECT_Connected (0x0UL) /*!< Connect */
17331 #define UARTE_PSEL_CTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
17332 
17333 /* Bit 5 : Port number */
17334 #define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
17335 #define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
17336 
17337 /* Bits 4..0 : Pin number */
17338 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
17339 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
17340 
17341 /* Register: UARTE_PSEL_RXD */
17342 /* Description: Pin select for RXD signal */
17343 
17344 /* Bit 31 : Connection */
17345 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
17346 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
17347 #define UARTE_PSEL_RXD_CONNECT_Connected (0x0UL) /*!< Connect */
17348 #define UARTE_PSEL_RXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
17349 
17350 /* Bit 5 : Port number */
17351 #define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
17352 #define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
17353 
17354 /* Bits 4..0 : Pin number */
17355 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
17356 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
17357 
17358 /* Register: UARTE_BAUDRATE */
17359 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
17360 
17361 /* Bits 31..0 : Baud rate */
17362 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
17363 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
17364 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
17365 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
17366 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
17367 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
17368 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
17369 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
17370 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
17371 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
17372 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
17373 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
17374 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
17375 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
17376 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
17377 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
17378 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
17379 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
17380 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
17381 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
17382 
17383 /* Register: UARTE_RXD_PTR */
17384 /* Description: Data pointer */
17385 
17386 /* Bits 31..0 : Data pointer */
17387 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
17388 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
17389 
17390 /* Register: UARTE_RXD_MAXCNT */
17391 /* Description: Maximum number of bytes in receive buffer */
17392 
17393 /* Bits 15..0 : Maximum number of bytes in receive buffer */
17394 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
17395 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
17396 
17397 /* Register: UARTE_RXD_AMOUNT */
17398 /* Description: Number of bytes transferred in the last transaction */
17399 
17400 /* Bits 15..0 : Number of bytes transferred in the last transaction */
17401 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
17402 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
17403 
17404 /* Register: UARTE_TXD_PTR */
17405 /* Description: Data pointer */
17406 
17407 /* Bits 31..0 : Data pointer */
17408 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
17409 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
17410 
17411 /* Register: UARTE_TXD_MAXCNT */
17412 /* Description: Maximum number of bytes in transmit buffer */
17413 
17414 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
17415 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
17416 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
17417 
17418 /* Register: UARTE_TXD_AMOUNT */
17419 /* Description: Number of bytes transferred in the last transaction */
17420 
17421 /* Bits 15..0 : Number of bytes transferred in the last transaction */
17422 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
17423 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
17424 
17425 /* Register: UARTE_CONFIG */
17426 /* Description: Configuration of parity and hardware flow control */
17427 
17428 /* Bit 4 : Stop bits */
17429 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
17430 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
17431 #define UARTE_CONFIG_STOP_One (0x0UL) /*!< One stop bit */
17432 #define UARTE_CONFIG_STOP_Two (0x1UL) /*!< Two stop bits */
17433 
17434 /* Bits 3..1 : Parity */
17435 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
17436 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
17437 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
17438 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
17439 
17440 /* Bit 0 : Hardware flow control */
17441 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
17442 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
17443 #define UARTE_CONFIG_HWFC_Disabled (0x0UL) /*!< Disabled */
17444 #define UARTE_CONFIG_HWFC_Enabled (0x1UL) /*!< Enabled */
17445 
17446 
17447 /* Peripheral: UICR */
17448 /* Description: User information configuration registers */
17449 
17450 /* Register: UICR_NRFFW */
17451 /* Description: Description collection: Reserved for Nordic firmware design */
17452 
17453 /* Bits 31..0 : Reserved for Nordic firmware design */
17454 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
17455 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
17456 
17457 /* Register: UICR_NRFHW */
17458 /* Description: Description collection: Reserved for Nordic hardware design */
17459 
17460 /* Bits 31..0 : Reserved for Nordic hardware design */
17461 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
17462 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
17463 
17464 /* Register: UICR_CUSTOMER */
17465 /* Description: Description collection: Reserved for customer */
17466 
17467 /* Bits 31..0 : Reserved for customer */
17468 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
17469 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
17470 
17471 /* Register: UICR_PSELRESET */
17472 /* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */
17473 
17474 /* Bit 31 : Connection */
17475 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
17476 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
17477 #define UICR_PSELRESET_CONNECT_Connected (0x0UL) /*!< Connect */
17478 #define UICR_PSELRESET_CONNECT_Disconnected (0x1UL) /*!< Disconnect */
17479 
17480 /* Bit 5 : Port number onto which nRESET is exposed */
17481 #define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */
17482 #define UICR_PSELRESET_PORT_Msk (0x1UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */
17483 
17484 /* Bits 4..0 : GPIO pin number onto which nRESET is exposed */
17485 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
17486 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
17487 
17488 /* Register: UICR_APPROTECT */
17489 /* Description: Access port protection */
17490 
17491 /* Bits 7..0 : Enable or disable access port protection. */
17492 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
17493 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
17494 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
17495 #define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */
17496 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */
17497 
17498 /* Register: UICR_NFCPINS */
17499 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
17500 
17501 /* Bit 0 : Setting of pins dedicated to NFC functionality */
17502 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
17503 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
17504 #define UICR_NFCPINS_PROTECT_Disabled (0x0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins. */
17505 #define UICR_NFCPINS_PROTECT_NFC (0x1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */
17506 
17507 /* Register: UICR_DEBUGCTRL */
17508 /* Description: Processor debug control */
17509 
17510 /* Bits 15..8 : Configure CPU flash patch and breakpoint (FPB) unit behavior */
17511 #define UICR_DEBUGCTRL_CPUFPBEN_Pos (8UL) /*!< Position of CPUFPBEN field. */
17512 #define UICR_DEBUGCTRL_CPUFPBEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUFPBEN_Pos) /*!< Bit mask of CPUFPBEN field. */
17513 #define UICR_DEBUGCTRL_CPUFPBEN_Disabled (0x00UL) /*!< Disable CPU FPB unit. Writes into the FPB registers will be ignored. */
17514 #define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */
17515 
17516 /* Bits 7..0 : Configure CPU non-intrusive debug features */
17517 #define UICR_DEBUGCTRL_CPUNIDEN_Pos (0UL) /*!< Position of CPUNIDEN field. */
17518 #define UICR_DEBUGCTRL_CPUNIDEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUNIDEN_Pos) /*!< Bit mask of CPUNIDEN field. */
17519 #define UICR_DEBUGCTRL_CPUNIDEN_Disabled (0x00UL) /*!< Disable CPU ITM and ETM functionality */
17520 #define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */
17521 
17522 /* Register: UICR_REGOUT0 */
17523 /* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. */
17524 
17525 /* Bits 2..0 : Output voltage from REG0 regulator stage. */
17526 #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */
17527 #define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */
17528 #define UICR_REGOUT0_VOUT_1V8 (0x0UL) /*!< 1.8 V */
17529 #define UICR_REGOUT0_VOUT_2V1 (0x1UL) /*!< 2.1 V */
17530 #define UICR_REGOUT0_VOUT_2V4 (0x2UL) /*!< 2.4 V */
17531 #define UICR_REGOUT0_VOUT_2V7 (0x3UL) /*!< 2.7 V */
17532 #define UICR_REGOUT0_VOUT_3V0 (0x4UL) /*!< 3.0 V */
17533 #define UICR_REGOUT0_VOUT_3V3 (0x5UL) /*!< 3.3 V */
17534 #define UICR_REGOUT0_VOUT_DEFAULT (0x7UL) /*!< Default voltage: 1.8 V */
17535 
17536 
17537 /* Peripheral: USBD */
17538 /* Description: Universal serial bus device */
17539 
17540 /* Register: USBD_TASKS_STARTEPIN */
17541 /* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
17542 
17543 /* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
17544 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */
17545 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */
17546 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (0x1UL) /*!< Trigger task */
17547 
17548 /* Register: USBD_TASKS_STARTISOIN */
17549 /* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
17550 
17551 /* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
17552 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */
17553 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */
17554 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (0x1UL) /*!< Trigger task */
17555 
17556 /* Register: USBD_TASKS_STARTEPOUT */
17557 /* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
17558 
17559 /* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
17560 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */
17561 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */
17562 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (0x1UL) /*!< Trigger task */
17563 
17564 /* Register: USBD_TASKS_STARTISOOUT */
17565 /* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
17566 
17567 /* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
17568 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */
17569 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */
17570 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (0x1UL) /*!< Trigger task */
17571 
17572 /* Register: USBD_TASKS_EP0RCVOUT */
17573 /* Description: Allows OUT data stage on control endpoint 0 */
17574 
17575 /* Bit 0 : Allows OUT data stage on control endpoint 0 */
17576 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */
17577 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */
17578 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (0x1UL) /*!< Trigger task */
17579 
17580 /* Register: USBD_TASKS_EP0STATUS */
17581 /* Description: Allows status stage on control endpoint 0 */
17582 
17583 /* Bit 0 : Allows status stage on control endpoint 0 */
17584 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */
17585 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */
17586 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (0x1UL) /*!< Trigger task */
17587 
17588 /* Register: USBD_TASKS_EP0STALL */
17589 /* Description: Stalls data and status stage on control endpoint 0 */
17590 
17591 /* Bit 0 : Stalls data and status stage on control endpoint 0 */
17592 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */
17593 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */
17594 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (0x1UL) /*!< Trigger task */
17595 
17596 /* Register: USBD_TASKS_DPDMDRIVE */
17597 /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */
17598 
17599 /* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */
17600 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */
17601 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */
17602 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (0x1UL) /*!< Trigger task */
17603 
17604 /* Register: USBD_TASKS_DPDMNODRIVE */
17605 /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */
17606 
17607 /* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */
17608 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */
17609 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */
17610 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (0x1UL) /*!< Trigger task */
17611 
17612 /* Register: USBD_EVENTS_USBRESET */
17613 /* Description: Signals that a USB reset condition has been detected on USB lines */
17614 
17615 /* Bit 0 : Signals that a USB reset condition has been detected on USB lines */
17616 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */
17617 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */
17618 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0x0UL) /*!< Event not generated */
17619 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (0x1UL) /*!< Event generated */
17620 
17621 /* Register: USBD_EVENTS_STARTED */
17622 /* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
17623 
17624 /* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
17625 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
17626 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
17627 #define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
17628 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */
17629 
17630 /* Register: USBD_EVENTS_ENDEPIN */
17631 /* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
17632 
17633 /* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
17634 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */
17635 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */
17636 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0x0UL) /*!< Event not generated */
17637 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (0x1UL) /*!< Event generated */
17638 
17639 /* Register: USBD_EVENTS_EP0DATADONE */
17640 /* Description: An acknowledged data transfer has taken place on the control endpoint */
17641 
17642 /* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */
17643 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */
17644 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */
17645 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0x0UL) /*!< Event not generated */
17646 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (0x1UL) /*!< Event generated */
17647 
17648 /* Register: USBD_EVENTS_ENDISOIN */
17649 /* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
17650 
17651 /* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
17652 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */
17653 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */
17654 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0x0UL) /*!< Event not generated */
17655 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (0x1UL) /*!< Event generated */
17656 
17657 /* Register: USBD_EVENTS_ENDEPOUT */
17658 /* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
17659 
17660 /* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
17661 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */
17662 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */
17663 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0x0UL) /*!< Event not generated */
17664 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (0x1UL) /*!< Event generated */
17665 
17666 /* Register: USBD_EVENTS_ENDISOOUT */
17667 /* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
17668 
17669 /* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
17670 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */
17671 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */
17672 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0x0UL) /*!< Event not generated */
17673 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (0x1UL) /*!< Event generated */
17674 
17675 /* Register: USBD_EVENTS_SOF */
17676 /* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */
17677 
17678 /* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */
17679 #define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */
17680 #define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */
17681 #define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0x0UL) /*!< Event not generated */
17682 #define USBD_EVENTS_SOF_EVENTS_SOF_Generated (0x1UL) /*!< Event generated */
17683 
17684 /* Register: USBD_EVENTS_USBEVENT */
17685 /* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
17686 
17687 /* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
17688 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */
17689 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */
17690 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0x0UL) /*!< Event not generated */
17691 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (0x1UL) /*!< Event generated */
17692 
17693 /* Register: USBD_EVENTS_EP0SETUP */
17694 /* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */
17695 
17696 /* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */
17697 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */
17698 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */
17699 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0x0UL) /*!< Event not generated */
17700 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (0x1UL) /*!< Event generated */
17701 
17702 /* Register: USBD_EVENTS_EPDATA */
17703 /* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
17704 
17705 /* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
17706 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */
17707 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */
17708 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0x0UL) /*!< Event not generated */
17709 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (0x1UL) /*!< Event generated */
17710 
17711 /* Register: USBD_SHORTS */
17712 /* Description: Shortcuts between local events and tasks */
17713 
17714 /* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */
17715 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */
17716 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */
17717 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0x0UL) /*!< Disable shortcut */
17718 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (0x1UL) /*!< Enable shortcut */
17719 
17720 /* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */
17721 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */
17722 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */
17723 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0x0UL) /*!< Disable shortcut */
17724 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (0x1UL) /*!< Enable shortcut */
17725 
17726 /* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */
17727 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */
17728 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */
17729 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0x0UL) /*!< Disable shortcut */
17730 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (0x1UL) /*!< Enable shortcut */
17731 
17732 /* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */
17733 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */
17734 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */
17735 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0x0UL) /*!< Disable shortcut */
17736 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (0x1UL) /*!< Enable shortcut */
17737 
17738 /* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */
17739 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */
17740 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */
17741 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0x0UL) /*!< Disable shortcut */
17742 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (0x1UL) /*!< Enable shortcut */
17743 
17744 /* Register: USBD_INTEN */
17745 /* Description: Enable or disable interrupt */
17746 
17747 /* Bit 24 : Enable or disable interrupt for event EPDATA */
17748 #define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
17749 #define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
17750 #define USBD_INTEN_EPDATA_Disabled (0x0UL) /*!< Disable */
17751 #define USBD_INTEN_EPDATA_Enabled (0x1UL) /*!< Enable */
17752 
17753 /* Bit 23 : Enable or disable interrupt for event EP0SETUP */
17754 #define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
17755 #define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
17756 #define USBD_INTEN_EP0SETUP_Disabled (0x0UL) /*!< Disable */
17757 #define USBD_INTEN_EP0SETUP_Enabled (0x1UL) /*!< Enable */
17758 
17759 /* Bit 22 : Enable or disable interrupt for event USBEVENT */
17760 #define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
17761 #define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
17762 #define USBD_INTEN_USBEVENT_Disabled (0x0UL) /*!< Disable */
17763 #define USBD_INTEN_USBEVENT_Enabled (0x1UL) /*!< Enable */
17764 
17765 /* Bit 21 : Enable or disable interrupt for event SOF */
17766 #define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */
17767 #define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */
17768 #define USBD_INTEN_SOF_Disabled (0x0UL) /*!< Disable */
17769 #define USBD_INTEN_SOF_Enabled (0x1UL) /*!< Enable */
17770 
17771 /* Bit 20 : Enable or disable interrupt for event ENDISOOUT */
17772 #define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
17773 #define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
17774 #define USBD_INTEN_ENDISOOUT_Disabled (0x0UL) /*!< Disable */
17775 #define USBD_INTEN_ENDISOOUT_Enabled (0x1UL) /*!< Enable */
17776 
17777 /* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */
17778 #define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
17779 #define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
17780 #define USBD_INTEN_ENDEPOUT7_Disabled (0x0UL) /*!< Disable */
17781 #define USBD_INTEN_ENDEPOUT7_Enabled (0x1UL) /*!< Enable */
17782 
17783 /* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */
17784 #define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
17785 #define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
17786 #define USBD_INTEN_ENDEPOUT6_Disabled (0x0UL) /*!< Disable */
17787 #define USBD_INTEN_ENDEPOUT6_Enabled (0x1UL) /*!< Enable */
17788 
17789 /* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */
17790 #define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
17791 #define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
17792 #define USBD_INTEN_ENDEPOUT5_Disabled (0x0UL) /*!< Disable */
17793 #define USBD_INTEN_ENDEPOUT5_Enabled (0x1UL) /*!< Enable */
17794 
17795 /* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */
17796 #define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
17797 #define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
17798 #define USBD_INTEN_ENDEPOUT4_Disabled (0x0UL) /*!< Disable */
17799 #define USBD_INTEN_ENDEPOUT4_Enabled (0x1UL) /*!< Enable */
17800 
17801 /* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */
17802 #define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
17803 #define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
17804 #define USBD_INTEN_ENDEPOUT3_Disabled (0x0UL) /*!< Disable */
17805 #define USBD_INTEN_ENDEPOUT3_Enabled (0x1UL) /*!< Enable */
17806 
17807 /* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */
17808 #define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
17809 #define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
17810 #define USBD_INTEN_ENDEPOUT2_Disabled (0x0UL) /*!< Disable */
17811 #define USBD_INTEN_ENDEPOUT2_Enabled (0x1UL) /*!< Enable */
17812 
17813 /* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */
17814 #define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
17815 #define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
17816 #define USBD_INTEN_ENDEPOUT1_Disabled (0x0UL) /*!< Disable */
17817 #define USBD_INTEN_ENDEPOUT1_Enabled (0x1UL) /*!< Enable */
17818 
17819 /* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */
17820 #define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
17821 #define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
17822 #define USBD_INTEN_ENDEPOUT0_Disabled (0x0UL) /*!< Disable */
17823 #define USBD_INTEN_ENDEPOUT0_Enabled (0x1UL) /*!< Enable */
17824 
17825 /* Bit 11 : Enable or disable interrupt for event ENDISOIN */
17826 #define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
17827 #define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
17828 #define USBD_INTEN_ENDISOIN_Disabled (0x0UL) /*!< Disable */
17829 #define USBD_INTEN_ENDISOIN_Enabled (0x1UL) /*!< Enable */
17830 
17831 /* Bit 10 : Enable or disable interrupt for event EP0DATADONE */
17832 #define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
17833 #define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
17834 #define USBD_INTEN_EP0DATADONE_Disabled (0x0UL) /*!< Disable */
17835 #define USBD_INTEN_EP0DATADONE_Enabled (0x1UL) /*!< Enable */
17836 
17837 /* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */
17838 #define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
17839 #define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
17840 #define USBD_INTEN_ENDEPIN7_Disabled (0x0UL) /*!< Disable */
17841 #define USBD_INTEN_ENDEPIN7_Enabled (0x1UL) /*!< Enable */
17842 
17843 /* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */
17844 #define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
17845 #define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
17846 #define USBD_INTEN_ENDEPIN6_Disabled (0x0UL) /*!< Disable */
17847 #define USBD_INTEN_ENDEPIN6_Enabled (0x1UL) /*!< Enable */
17848 
17849 /* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */
17850 #define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
17851 #define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
17852 #define USBD_INTEN_ENDEPIN5_Disabled (0x0UL) /*!< Disable */
17853 #define USBD_INTEN_ENDEPIN5_Enabled (0x1UL) /*!< Enable */
17854 
17855 /* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */
17856 #define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
17857 #define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
17858 #define USBD_INTEN_ENDEPIN4_Disabled (0x0UL) /*!< Disable */
17859 #define USBD_INTEN_ENDEPIN4_Enabled (0x1UL) /*!< Enable */
17860 
17861 /* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */
17862 #define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
17863 #define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
17864 #define USBD_INTEN_ENDEPIN3_Disabled (0x0UL) /*!< Disable */
17865 #define USBD_INTEN_ENDEPIN3_Enabled (0x1UL) /*!< Enable */
17866 
17867 /* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */
17868 #define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
17869 #define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
17870 #define USBD_INTEN_ENDEPIN2_Disabled (0x0UL) /*!< Disable */
17871 #define USBD_INTEN_ENDEPIN2_Enabled (0x1UL) /*!< Enable */
17872 
17873 /* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */
17874 #define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
17875 #define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
17876 #define USBD_INTEN_ENDEPIN1_Disabled (0x0UL) /*!< Disable */
17877 #define USBD_INTEN_ENDEPIN1_Enabled (0x1UL) /*!< Enable */
17878 
17879 /* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */
17880 #define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
17881 #define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
17882 #define USBD_INTEN_ENDEPIN0_Disabled (0x0UL) /*!< Disable */
17883 #define USBD_INTEN_ENDEPIN0_Enabled (0x1UL) /*!< Enable */
17884 
17885 /* Bit 1 : Enable or disable interrupt for event STARTED */
17886 #define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */
17887 #define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
17888 #define USBD_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */
17889 #define USBD_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */
17890 
17891 /* Bit 0 : Enable or disable interrupt for event USBRESET */
17892 #define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
17893 #define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
17894 #define USBD_INTEN_USBRESET_Disabled (0x0UL) /*!< Disable */
17895 #define USBD_INTEN_USBRESET_Enabled (0x1UL) /*!< Enable */
17896 
17897 /* Register: USBD_INTENSET */
17898 /* Description: Enable interrupt */
17899 
17900 /* Bit 24 : Write '1' to enable interrupt for event EPDATA */
17901 #define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
17902 #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
17903 #define USBD_INTENSET_EPDATA_Disabled (0x0UL) /*!< Read: Disabled */
17904 #define USBD_INTENSET_EPDATA_Enabled (0x1UL) /*!< Read: Enabled */
17905 #define USBD_INTENSET_EPDATA_Set (0x1UL) /*!< Enable */
17906 
17907 /* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */
17908 #define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
17909 #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
17910 #define USBD_INTENSET_EP0SETUP_Disabled (0x0UL) /*!< Read: Disabled */
17911 #define USBD_INTENSET_EP0SETUP_Enabled (0x1UL) /*!< Read: Enabled */
17912 #define USBD_INTENSET_EP0SETUP_Set (0x1UL) /*!< Enable */
17913 
17914 /* Bit 22 : Write '1' to enable interrupt for event USBEVENT */
17915 #define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
17916 #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
17917 #define USBD_INTENSET_USBEVENT_Disabled (0x0UL) /*!< Read: Disabled */
17918 #define USBD_INTENSET_USBEVENT_Enabled (0x1UL) /*!< Read: Enabled */
17919 #define USBD_INTENSET_USBEVENT_Set (0x1UL) /*!< Enable */
17920 
17921 /* Bit 21 : Write '1' to enable interrupt for event SOF */
17922 #define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */
17923 #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */
17924 #define USBD_INTENSET_SOF_Disabled (0x0UL) /*!< Read: Disabled */
17925 #define USBD_INTENSET_SOF_Enabled (0x1UL) /*!< Read: Enabled */
17926 #define USBD_INTENSET_SOF_Set (0x1UL) /*!< Enable */
17927 
17928 /* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */
17929 #define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
17930 #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
17931 #define USBD_INTENSET_ENDISOOUT_Disabled (0x0UL) /*!< Read: Disabled */
17932 #define USBD_INTENSET_ENDISOOUT_Enabled (0x1UL) /*!< Read: Enabled */
17933 #define USBD_INTENSET_ENDISOOUT_Set (0x1UL) /*!< Enable */
17934 
17935 /* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */
17936 #define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
17937 #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
17938 #define USBD_INTENSET_ENDEPOUT7_Disabled (0x0UL) /*!< Read: Disabled */
17939 #define USBD_INTENSET_ENDEPOUT7_Enabled (0x1UL) /*!< Read: Enabled */
17940 #define USBD_INTENSET_ENDEPOUT7_Set (0x1UL) /*!< Enable */
17941 
17942 /* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */
17943 #define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
17944 #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
17945 #define USBD_INTENSET_ENDEPOUT6_Disabled (0x0UL) /*!< Read: Disabled */
17946 #define USBD_INTENSET_ENDEPOUT6_Enabled (0x1UL) /*!< Read: Enabled */
17947 #define USBD_INTENSET_ENDEPOUT6_Set (0x1UL) /*!< Enable */
17948 
17949 /* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */
17950 #define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
17951 #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
17952 #define USBD_INTENSET_ENDEPOUT5_Disabled (0x0UL) /*!< Read: Disabled */
17953 #define USBD_INTENSET_ENDEPOUT5_Enabled (0x1UL) /*!< Read: Enabled */
17954 #define USBD_INTENSET_ENDEPOUT5_Set (0x1UL) /*!< Enable */
17955 
17956 /* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */
17957 #define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
17958 #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
17959 #define USBD_INTENSET_ENDEPOUT4_Disabled (0x0UL) /*!< Read: Disabled */
17960 #define USBD_INTENSET_ENDEPOUT4_Enabled (0x1UL) /*!< Read: Enabled */
17961 #define USBD_INTENSET_ENDEPOUT4_Set (0x1UL) /*!< Enable */
17962 
17963 /* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */
17964 #define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
17965 #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
17966 #define USBD_INTENSET_ENDEPOUT3_Disabled (0x0UL) /*!< Read: Disabled */
17967 #define USBD_INTENSET_ENDEPOUT3_Enabled (0x1UL) /*!< Read: Enabled */
17968 #define USBD_INTENSET_ENDEPOUT3_Set (0x1UL) /*!< Enable */
17969 
17970 /* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */
17971 #define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
17972 #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
17973 #define USBD_INTENSET_ENDEPOUT2_Disabled (0x0UL) /*!< Read: Disabled */
17974 #define USBD_INTENSET_ENDEPOUT2_Enabled (0x1UL) /*!< Read: Enabled */
17975 #define USBD_INTENSET_ENDEPOUT2_Set (0x1UL) /*!< Enable */
17976 
17977 /* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */
17978 #define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
17979 #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
17980 #define USBD_INTENSET_ENDEPOUT1_Disabled (0x0UL) /*!< Read: Disabled */
17981 #define USBD_INTENSET_ENDEPOUT1_Enabled (0x1UL) /*!< Read: Enabled */
17982 #define USBD_INTENSET_ENDEPOUT1_Set (0x1UL) /*!< Enable */
17983 
17984 /* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */
17985 #define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
17986 #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
17987 #define USBD_INTENSET_ENDEPOUT0_Disabled (0x0UL) /*!< Read: Disabled */
17988 #define USBD_INTENSET_ENDEPOUT0_Enabled (0x1UL) /*!< Read: Enabled */
17989 #define USBD_INTENSET_ENDEPOUT0_Set (0x1UL) /*!< Enable */
17990 
17991 /* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */
17992 #define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
17993 #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
17994 #define USBD_INTENSET_ENDISOIN_Disabled (0x0UL) /*!< Read: Disabled */
17995 #define USBD_INTENSET_ENDISOIN_Enabled (0x1UL) /*!< Read: Enabled */
17996 #define USBD_INTENSET_ENDISOIN_Set (0x1UL) /*!< Enable */
17997 
17998 /* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */
17999 #define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
18000 #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
18001 #define USBD_INTENSET_EP0DATADONE_Disabled (0x0UL) /*!< Read: Disabled */
18002 #define USBD_INTENSET_EP0DATADONE_Enabled (0x1UL) /*!< Read: Enabled */
18003 #define USBD_INTENSET_EP0DATADONE_Set (0x1UL) /*!< Enable */
18004 
18005 /* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */
18006 #define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
18007 #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
18008 #define USBD_INTENSET_ENDEPIN7_Disabled (0x0UL) /*!< Read: Disabled */
18009 #define USBD_INTENSET_ENDEPIN7_Enabled (0x1UL) /*!< Read: Enabled */
18010 #define USBD_INTENSET_ENDEPIN7_Set (0x1UL) /*!< Enable */
18011 
18012 /* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */
18013 #define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
18014 #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
18015 #define USBD_INTENSET_ENDEPIN6_Disabled (0x0UL) /*!< Read: Disabled */
18016 #define USBD_INTENSET_ENDEPIN6_Enabled (0x1UL) /*!< Read: Enabled */
18017 #define USBD_INTENSET_ENDEPIN6_Set (0x1UL) /*!< Enable */
18018 
18019 /* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */
18020 #define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
18021 #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
18022 #define USBD_INTENSET_ENDEPIN5_Disabled (0x0UL) /*!< Read: Disabled */
18023 #define USBD_INTENSET_ENDEPIN5_Enabled (0x1UL) /*!< Read: Enabled */
18024 #define USBD_INTENSET_ENDEPIN5_Set (0x1UL) /*!< Enable */
18025 
18026 /* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */
18027 #define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
18028 #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
18029 #define USBD_INTENSET_ENDEPIN4_Disabled (0x0UL) /*!< Read: Disabled */
18030 #define USBD_INTENSET_ENDEPIN4_Enabled (0x1UL) /*!< Read: Enabled */
18031 #define USBD_INTENSET_ENDEPIN4_Set (0x1UL) /*!< Enable */
18032 
18033 /* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */
18034 #define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
18035 #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
18036 #define USBD_INTENSET_ENDEPIN3_Disabled (0x0UL) /*!< Read: Disabled */
18037 #define USBD_INTENSET_ENDEPIN3_Enabled (0x1UL) /*!< Read: Enabled */
18038 #define USBD_INTENSET_ENDEPIN3_Set (0x1UL) /*!< Enable */
18039 
18040 /* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */
18041 #define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
18042 #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
18043 #define USBD_INTENSET_ENDEPIN2_Disabled (0x0UL) /*!< Read: Disabled */
18044 #define USBD_INTENSET_ENDEPIN2_Enabled (0x1UL) /*!< Read: Enabled */
18045 #define USBD_INTENSET_ENDEPIN2_Set (0x1UL) /*!< Enable */
18046 
18047 /* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */
18048 #define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
18049 #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
18050 #define USBD_INTENSET_ENDEPIN1_Disabled (0x0UL) /*!< Read: Disabled */
18051 #define USBD_INTENSET_ENDEPIN1_Enabled (0x1UL) /*!< Read: Enabled */
18052 #define USBD_INTENSET_ENDEPIN1_Set (0x1UL) /*!< Enable */
18053 
18054 /* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */
18055 #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
18056 #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
18057 #define USBD_INTENSET_ENDEPIN0_Disabled (0x0UL) /*!< Read: Disabled */
18058 #define USBD_INTENSET_ENDEPIN0_Enabled (0x1UL) /*!< Read: Enabled */
18059 #define USBD_INTENSET_ENDEPIN0_Set (0x1UL) /*!< Enable */
18060 
18061 /* Bit 1 : Write '1' to enable interrupt for event STARTED */
18062 #define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */
18063 #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
18064 #define USBD_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
18065 #define USBD_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
18066 #define USBD_INTENSET_STARTED_Set (0x1UL) /*!< Enable */
18067 
18068 /* Bit 0 : Write '1' to enable interrupt for event USBRESET */
18069 #define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
18070 #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
18071 #define USBD_INTENSET_USBRESET_Disabled (0x0UL) /*!< Read: Disabled */
18072 #define USBD_INTENSET_USBRESET_Enabled (0x1UL) /*!< Read: Enabled */
18073 #define USBD_INTENSET_USBRESET_Set (0x1UL) /*!< Enable */
18074 
18075 /* Register: USBD_INTENCLR */
18076 /* Description: Disable interrupt */
18077 
18078 /* Bit 24 : Write '1' to disable interrupt for event EPDATA */
18079 #define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
18080 #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
18081 #define USBD_INTENCLR_EPDATA_Disabled (0x0UL) /*!< Read: Disabled */
18082 #define USBD_INTENCLR_EPDATA_Enabled (0x1UL) /*!< Read: Enabled */
18083 #define USBD_INTENCLR_EPDATA_Clear (0x1UL) /*!< Disable */
18084 
18085 /* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */
18086 #define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
18087 #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
18088 #define USBD_INTENCLR_EP0SETUP_Disabled (0x0UL) /*!< Read: Disabled */
18089 #define USBD_INTENCLR_EP0SETUP_Enabled (0x1UL) /*!< Read: Enabled */
18090 #define USBD_INTENCLR_EP0SETUP_Clear (0x1UL) /*!< Disable */
18091 
18092 /* Bit 22 : Write '1' to disable interrupt for event USBEVENT */
18093 #define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
18094 #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
18095 #define USBD_INTENCLR_USBEVENT_Disabled (0x0UL) /*!< Read: Disabled */
18096 #define USBD_INTENCLR_USBEVENT_Enabled (0x1UL) /*!< Read: Enabled */
18097 #define USBD_INTENCLR_USBEVENT_Clear (0x1UL) /*!< Disable */
18098 
18099 /* Bit 21 : Write '1' to disable interrupt for event SOF */
18100 #define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */
18101 #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */
18102 #define USBD_INTENCLR_SOF_Disabled (0x0UL) /*!< Read: Disabled */
18103 #define USBD_INTENCLR_SOF_Enabled (0x1UL) /*!< Read: Enabled */
18104 #define USBD_INTENCLR_SOF_Clear (0x1UL) /*!< Disable */
18105 
18106 /* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */
18107 #define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
18108 #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
18109 #define USBD_INTENCLR_ENDISOOUT_Disabled (0x0UL) /*!< Read: Disabled */
18110 #define USBD_INTENCLR_ENDISOOUT_Enabled (0x1UL) /*!< Read: Enabled */
18111 #define USBD_INTENCLR_ENDISOOUT_Clear (0x1UL) /*!< Disable */
18112 
18113 /* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */
18114 #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
18115 #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
18116 #define USBD_INTENCLR_ENDEPOUT7_Disabled (0x0UL) /*!< Read: Disabled */
18117 #define USBD_INTENCLR_ENDEPOUT7_Enabled (0x1UL) /*!< Read: Enabled */
18118 #define USBD_INTENCLR_ENDEPOUT7_Clear (0x1UL) /*!< Disable */
18119 
18120 /* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */
18121 #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
18122 #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
18123 #define USBD_INTENCLR_ENDEPOUT6_Disabled (0x0UL) /*!< Read: Disabled */
18124 #define USBD_INTENCLR_ENDEPOUT6_Enabled (0x1UL) /*!< Read: Enabled */
18125 #define USBD_INTENCLR_ENDEPOUT6_Clear (0x1UL) /*!< Disable */
18126 
18127 /* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */
18128 #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
18129 #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
18130 #define USBD_INTENCLR_ENDEPOUT5_Disabled (0x0UL) /*!< Read: Disabled */
18131 #define USBD_INTENCLR_ENDEPOUT5_Enabled (0x1UL) /*!< Read: Enabled */
18132 #define USBD_INTENCLR_ENDEPOUT5_Clear (0x1UL) /*!< Disable */
18133 
18134 /* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */
18135 #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
18136 #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
18137 #define USBD_INTENCLR_ENDEPOUT4_Disabled (0x0UL) /*!< Read: Disabled */
18138 #define USBD_INTENCLR_ENDEPOUT4_Enabled (0x1UL) /*!< Read: Enabled */
18139 #define USBD_INTENCLR_ENDEPOUT4_Clear (0x1UL) /*!< Disable */
18140 
18141 /* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */
18142 #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
18143 #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
18144 #define USBD_INTENCLR_ENDEPOUT3_Disabled (0x0UL) /*!< Read: Disabled */
18145 #define USBD_INTENCLR_ENDEPOUT3_Enabled (0x1UL) /*!< Read: Enabled */
18146 #define USBD_INTENCLR_ENDEPOUT3_Clear (0x1UL) /*!< Disable */
18147 
18148 /* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */
18149 #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
18150 #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
18151 #define USBD_INTENCLR_ENDEPOUT2_Disabled (0x0UL) /*!< Read: Disabled */
18152 #define USBD_INTENCLR_ENDEPOUT2_Enabled (0x1UL) /*!< Read: Enabled */
18153 #define USBD_INTENCLR_ENDEPOUT2_Clear (0x1UL) /*!< Disable */
18154 
18155 /* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */
18156 #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
18157 #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
18158 #define USBD_INTENCLR_ENDEPOUT1_Disabled (0x0UL) /*!< Read: Disabled */
18159 #define USBD_INTENCLR_ENDEPOUT1_Enabled (0x1UL) /*!< Read: Enabled */
18160 #define USBD_INTENCLR_ENDEPOUT1_Clear (0x1UL) /*!< Disable */
18161 
18162 /* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */
18163 #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
18164 #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
18165 #define USBD_INTENCLR_ENDEPOUT0_Disabled (0x0UL) /*!< Read: Disabled */
18166 #define USBD_INTENCLR_ENDEPOUT0_Enabled (0x1UL) /*!< Read: Enabled */
18167 #define USBD_INTENCLR_ENDEPOUT0_Clear (0x1UL) /*!< Disable */
18168 
18169 /* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */
18170 #define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
18171 #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
18172 #define USBD_INTENCLR_ENDISOIN_Disabled (0x0UL) /*!< Read: Disabled */
18173 #define USBD_INTENCLR_ENDISOIN_Enabled (0x1UL) /*!< Read: Enabled */
18174 #define USBD_INTENCLR_ENDISOIN_Clear (0x1UL) /*!< Disable */
18175 
18176 /* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */
18177 #define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
18178 #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
18179 #define USBD_INTENCLR_EP0DATADONE_Disabled (0x0UL) /*!< Read: Disabled */
18180 #define USBD_INTENCLR_EP0DATADONE_Enabled (0x1UL) /*!< Read: Enabled */
18181 #define USBD_INTENCLR_EP0DATADONE_Clear (0x1UL) /*!< Disable */
18182 
18183 /* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */
18184 #define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
18185 #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
18186 #define USBD_INTENCLR_ENDEPIN7_Disabled (0x0UL) /*!< Read: Disabled */
18187 #define USBD_INTENCLR_ENDEPIN7_Enabled (0x1UL) /*!< Read: Enabled */
18188 #define USBD_INTENCLR_ENDEPIN7_Clear (0x1UL) /*!< Disable */
18189 
18190 /* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */
18191 #define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
18192 #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
18193 #define USBD_INTENCLR_ENDEPIN6_Disabled (0x0UL) /*!< Read: Disabled */
18194 #define USBD_INTENCLR_ENDEPIN6_Enabled (0x1UL) /*!< Read: Enabled */
18195 #define USBD_INTENCLR_ENDEPIN6_Clear (0x1UL) /*!< Disable */
18196 
18197 /* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */
18198 #define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
18199 #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
18200 #define USBD_INTENCLR_ENDEPIN5_Disabled (0x0UL) /*!< Read: Disabled */
18201 #define USBD_INTENCLR_ENDEPIN5_Enabled (0x1UL) /*!< Read: Enabled */
18202 #define USBD_INTENCLR_ENDEPIN5_Clear (0x1UL) /*!< Disable */
18203 
18204 /* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */
18205 #define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
18206 #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
18207 #define USBD_INTENCLR_ENDEPIN4_Disabled (0x0UL) /*!< Read: Disabled */
18208 #define USBD_INTENCLR_ENDEPIN4_Enabled (0x1UL) /*!< Read: Enabled */
18209 #define USBD_INTENCLR_ENDEPIN4_Clear (0x1UL) /*!< Disable */
18210 
18211 /* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */
18212 #define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
18213 #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
18214 #define USBD_INTENCLR_ENDEPIN3_Disabled (0x0UL) /*!< Read: Disabled */
18215 #define USBD_INTENCLR_ENDEPIN3_Enabled (0x1UL) /*!< Read: Enabled */
18216 #define USBD_INTENCLR_ENDEPIN3_Clear (0x1UL) /*!< Disable */
18217 
18218 /* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */
18219 #define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
18220 #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
18221 #define USBD_INTENCLR_ENDEPIN2_Disabled (0x0UL) /*!< Read: Disabled */
18222 #define USBD_INTENCLR_ENDEPIN2_Enabled (0x1UL) /*!< Read: Enabled */
18223 #define USBD_INTENCLR_ENDEPIN2_Clear (0x1UL) /*!< Disable */
18224 
18225 /* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */
18226 #define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
18227 #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
18228 #define USBD_INTENCLR_ENDEPIN1_Disabled (0x0UL) /*!< Read: Disabled */
18229 #define USBD_INTENCLR_ENDEPIN1_Enabled (0x1UL) /*!< Read: Enabled */
18230 #define USBD_INTENCLR_ENDEPIN1_Clear (0x1UL) /*!< Disable */
18231 
18232 /* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */
18233 #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
18234 #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
18235 #define USBD_INTENCLR_ENDEPIN0_Disabled (0x0UL) /*!< Read: Disabled */
18236 #define USBD_INTENCLR_ENDEPIN0_Enabled (0x1UL) /*!< Read: Enabled */
18237 #define USBD_INTENCLR_ENDEPIN0_Clear (0x1UL) /*!< Disable */
18238 
18239 /* Bit 1 : Write '1' to disable interrupt for event STARTED */
18240 #define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */
18241 #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
18242 #define USBD_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
18243 #define USBD_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
18244 #define USBD_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */
18245 
18246 /* Bit 0 : Write '1' to disable interrupt for event USBRESET */
18247 #define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
18248 #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
18249 #define USBD_INTENCLR_USBRESET_Disabled (0x0UL) /*!< Read: Disabled */
18250 #define USBD_INTENCLR_USBRESET_Enabled (0x1UL) /*!< Read: Enabled */
18251 #define USBD_INTENCLR_USBRESET_Clear (0x1UL) /*!< Disable */
18252 
18253 /* Register: USBD_EVENTCAUSE */
18254 /* Description: Details on what caused the USBEVENT event */
18255 
18256 /* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */
18257 #define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */
18258 #define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */
18259 #define USBD_EVENTCAUSE_READY_NotDetected (0x0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */
18260 #define USBD_EVENTCAUSE_READY_Ready (0x1UL) /*!< USBD peripheral is ready */
18261 
18262 /* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */
18263 #define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */
18264 #define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */
18265 #define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0x0UL) /*!< Wake up not allowed */
18266 #define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (0x1UL) /*!< Wake up allowed */
18267 
18268 /* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */
18269 #define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */
18270 #define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */
18271 #define USBD_EVENTCAUSE_RESUME_NotDetected (0x0UL) /*!< Resume not detected */
18272 #define USBD_EVENTCAUSE_RESUME_Detected (0x1UL) /*!< Resume detected */
18273 
18274 /* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */
18275 #define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */
18276 #define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */
18277 #define USBD_EVENTCAUSE_SUSPEND_NotDetected (0x0UL) /*!< Suspend not detected */
18278 #define USBD_EVENTCAUSE_SUSPEND_Detected (0x1UL) /*!< Suspend detected */
18279 
18280 /* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */
18281 #define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */
18282 #define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */
18283 #define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0x0UL) /*!< No error detected */
18284 #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (0x1UL) /*!< Error detected */
18285 
18286 /* Register: USBD_HALTED_EPIN */
18287 /* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
18288 
18289 /* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
18290 #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
18291 #define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
18292 #define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0x0000UL) /*!< Endpoint is not halted */
18293 #define USBD_HALTED_EPIN_GETSTATUS_Halted (0x0001UL) /*!< Endpoint is halted */
18294 
18295 /* Register: USBD_HALTED_EPOUT */
18296 /* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
18297 
18298 /* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
18299 #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
18300 #define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
18301 #define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0x0000UL) /*!< Endpoint is not halted */
18302 #define USBD_HALTED_EPOUT_GETSTATUS_Halted (0x0001UL) /*!< Endpoint is halted */
18303 
18304 /* Register: USBD_EPSTATUS */
18305 /* Description: Provides information on which endpoint's EasyDMA registers have been captured */
18306 
18307 /* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18308 #define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */
18309 #define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */
18310 #define USBD_EPSTATUS_EPOUT8_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18311 #define USBD_EPSTATUS_EPOUT8_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18312 
18313 /* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18314 #define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
18315 #define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
18316 #define USBD_EPSTATUS_EPOUT7_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18317 #define USBD_EPSTATUS_EPOUT7_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18318 
18319 /* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18320 #define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
18321 #define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
18322 #define USBD_EPSTATUS_EPOUT6_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18323 #define USBD_EPSTATUS_EPOUT6_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18324 
18325 /* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18326 #define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
18327 #define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
18328 #define USBD_EPSTATUS_EPOUT5_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18329 #define USBD_EPSTATUS_EPOUT5_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18330 
18331 /* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18332 #define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
18333 #define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
18334 #define USBD_EPSTATUS_EPOUT4_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18335 #define USBD_EPSTATUS_EPOUT4_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18336 
18337 /* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18338 #define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
18339 #define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
18340 #define USBD_EPSTATUS_EPOUT3_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18341 #define USBD_EPSTATUS_EPOUT3_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18342 
18343 /* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18344 #define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
18345 #define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
18346 #define USBD_EPSTATUS_EPOUT2_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18347 #define USBD_EPSTATUS_EPOUT2_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18348 
18349 /* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18350 #define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
18351 #define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
18352 #define USBD_EPSTATUS_EPOUT1_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18353 #define USBD_EPSTATUS_EPOUT1_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18354 
18355 /* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18356 #define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */
18357 #define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */
18358 #define USBD_EPSTATUS_EPOUT0_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18359 #define USBD_EPSTATUS_EPOUT0_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18360 
18361 /* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18362 #define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */
18363 #define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */
18364 #define USBD_EPSTATUS_EPIN8_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18365 #define USBD_EPSTATUS_EPIN8_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18366 
18367 /* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18368 #define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
18369 #define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
18370 #define USBD_EPSTATUS_EPIN7_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18371 #define USBD_EPSTATUS_EPIN7_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18372 
18373 /* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18374 #define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
18375 #define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
18376 #define USBD_EPSTATUS_EPIN6_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18377 #define USBD_EPSTATUS_EPIN6_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18378 
18379 /* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18380 #define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
18381 #define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
18382 #define USBD_EPSTATUS_EPIN5_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18383 #define USBD_EPSTATUS_EPIN5_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18384 
18385 /* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18386 #define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
18387 #define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
18388 #define USBD_EPSTATUS_EPIN4_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18389 #define USBD_EPSTATUS_EPIN4_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18390 
18391 /* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18392 #define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
18393 #define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
18394 #define USBD_EPSTATUS_EPIN3_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18395 #define USBD_EPSTATUS_EPIN3_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18396 
18397 /* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18398 #define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
18399 #define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
18400 #define USBD_EPSTATUS_EPIN2_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18401 #define USBD_EPSTATUS_EPIN2_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18402 
18403 /* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18404 #define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
18405 #define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
18406 #define USBD_EPSTATUS_EPIN1_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18407 #define USBD_EPSTATUS_EPIN1_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18408 
18409 /* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
18410 #define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */
18411 #define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */
18412 #define USBD_EPSTATUS_EPIN0_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
18413 #define USBD_EPSTATUS_EPIN0_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */
18414 
18415 /* Register: USBD_EPDATASTATUS */
18416 /* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */
18417 
18418 /* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
18419 #define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
18420 #define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
18421 #define USBD_EPDATASTATUS_EPOUT7_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18422 #define USBD_EPDATASTATUS_EPOUT7_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18423 
18424 /* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
18425 #define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
18426 #define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
18427 #define USBD_EPDATASTATUS_EPOUT6_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18428 #define USBD_EPDATASTATUS_EPOUT6_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18429 
18430 /* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
18431 #define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
18432 #define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
18433 #define USBD_EPDATASTATUS_EPOUT5_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18434 #define USBD_EPDATASTATUS_EPOUT5_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18435 
18436 /* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
18437 #define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
18438 #define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
18439 #define USBD_EPDATASTATUS_EPOUT4_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18440 #define USBD_EPDATASTATUS_EPOUT4_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18441 
18442 /* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
18443 #define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
18444 #define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
18445 #define USBD_EPDATASTATUS_EPOUT3_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18446 #define USBD_EPDATASTATUS_EPOUT3_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18447 
18448 /* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
18449 #define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
18450 #define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
18451 #define USBD_EPDATASTATUS_EPOUT2_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18452 #define USBD_EPDATASTATUS_EPOUT2_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18453 
18454 /* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
18455 #define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
18456 #define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
18457 #define USBD_EPDATASTATUS_EPOUT1_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18458 #define USBD_EPDATASTATUS_EPOUT1_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18459 
18460 /* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
18461 #define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
18462 #define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
18463 #define USBD_EPDATASTATUS_EPIN7_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18464 #define USBD_EPDATASTATUS_EPIN7_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18465 
18466 /* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
18467 #define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
18468 #define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
18469 #define USBD_EPDATASTATUS_EPIN6_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18470 #define USBD_EPDATASTATUS_EPIN6_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18471 
18472 /* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
18473 #define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
18474 #define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
18475 #define USBD_EPDATASTATUS_EPIN5_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18476 #define USBD_EPDATASTATUS_EPIN5_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18477 
18478 /* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
18479 #define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
18480 #define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
18481 #define USBD_EPDATASTATUS_EPIN4_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18482 #define USBD_EPDATASTATUS_EPIN4_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18483 
18484 /* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
18485 #define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
18486 #define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
18487 #define USBD_EPDATASTATUS_EPIN3_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18488 #define USBD_EPDATASTATUS_EPIN3_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18489 
18490 /* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
18491 #define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
18492 #define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
18493 #define USBD_EPDATASTATUS_EPIN2_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18494 #define USBD_EPDATASTATUS_EPIN2_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18495 
18496 /* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
18497 #define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
18498 #define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
18499 #define USBD_EPDATASTATUS_EPIN1_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
18500 #define USBD_EPDATASTATUS_EPIN1_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
18501 
18502 /* Register: USBD_USBADDR */
18503 /* Description: Device USB address */
18504 
18505 /* Bits 6..0 : Device USB address */
18506 #define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
18507 #define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
18508 
18509 /* Register: USBD_BMREQUESTTYPE */
18510 /* Description: SETUP data, byte 0, bmRequestType */
18511 
18512 /* Bit 7 : Data transfer direction */
18513 #define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */
18514 #define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */
18515 #define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0x0UL) /*!< Host-to-device */
18516 #define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (0x1UL) /*!< Device-to-host */
18517 
18518 /* Bits 6..5 : Data transfer type */
18519 #define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */
18520 #define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */
18521 #define USBD_BMREQUESTTYPE_TYPE_Standard (0x0UL) /*!< Standard */
18522 #define USBD_BMREQUESTTYPE_TYPE_Class (0x1UL) /*!< Class */
18523 #define USBD_BMREQUESTTYPE_TYPE_Vendor (0x2UL) /*!< Vendor */
18524 
18525 /* Bits 4..0 : Data transfer type */
18526 #define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */
18527 #define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */
18528 #define USBD_BMREQUESTTYPE_RECIPIENT_Device (0x00UL) /*!< Device */
18529 #define USBD_BMREQUESTTYPE_RECIPIENT_Interface (0x01UL) /*!< Interface */
18530 #define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (0x02UL) /*!< Endpoint */
18531 #define USBD_BMREQUESTTYPE_RECIPIENT_Other (0x03UL) /*!< Other */
18532 
18533 /* Register: USBD_BREQUEST */
18534 /* Description: SETUP data, byte 1, bRequest */
18535 
18536 /* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */
18537 #define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */
18538 #define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */
18539 #define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0x00UL) /*!< Standard request GET_STATUS */
18540 #define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (0x01UL) /*!< Standard request CLEAR_FEATURE */
18541 #define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (0x03UL) /*!< Standard request SET_FEATURE */
18542 #define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (0x05UL) /*!< Standard request SET_ADDRESS */
18543 #define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (0x06UL) /*!< Standard request GET_DESCRIPTOR */
18544 #define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (0x07UL) /*!< Standard request SET_DESCRIPTOR */
18545 #define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (0x08UL) /*!< Standard request GET_CONFIGURATION */
18546 #define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (0x09UL) /*!< Standard request SET_CONFIGURATION */
18547 #define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (0x0AUL) /*!< Standard request GET_INTERFACE */
18548 #define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (0x0BUL) /*!< Standard request SET_INTERFACE */
18549 #define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (0x0CUL) /*!< Standard request SYNCH_FRAME */
18550 
18551 /* Register: USBD_WVALUEL */
18552 /* Description: SETUP data, byte 2, LSB of wValue */
18553 
18554 /* Bits 7..0 : SETUP data, byte 2, LSB of wValue */
18555 #define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */
18556 #define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */
18557 
18558 /* Register: USBD_WVALUEH */
18559 /* Description: SETUP data, byte 3, MSB of wValue */
18560 
18561 /* Bits 7..0 : SETUP data, byte 3, MSB of wValue */
18562 #define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */
18563 #define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */
18564 
18565 /* Register: USBD_WINDEXL */
18566 /* Description: SETUP data, byte 4, LSB of wIndex */
18567 
18568 /* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */
18569 #define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */
18570 #define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */
18571 
18572 /* Register: USBD_WINDEXH */
18573 /* Description: SETUP data, byte 5, MSB of wIndex */
18574 
18575 /* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */
18576 #define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */
18577 #define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */
18578 
18579 /* Register: USBD_WLENGTHL */
18580 /* Description: SETUP data, byte 6, LSB of wLength */
18581 
18582 /* Bits 7..0 : SETUP data, byte 6, LSB of wLength */
18583 #define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */
18584 #define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */
18585 
18586 /* Register: USBD_WLENGTHH */
18587 /* Description: SETUP data, byte 7, MSB of wLength */
18588 
18589 /* Bits 7..0 : SETUP data, byte 7, MSB of wLength */
18590 #define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */
18591 #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */
18592 
18593 /* Register: USBD_SIZE_EPOUT */
18594 /* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */
18595 
18596 /* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */
18597 #define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
18598 #define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
18599 
18600 /* Register: USBD_SIZE_ISOOUT */
18601 /* Description: Number of bytes received last on this ISO OUT data endpoint */
18602 
18603 /* Bit 16 : Zero-length data packet received */
18604 #define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */
18605 #define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */
18606 #define USBD_SIZE_ISOOUT_ZERO_Normal (0x0UL) /*!< No zero-length data received, use value in SIZE */
18607 #define USBD_SIZE_ISOOUT_ZERO_ZeroData (0x1UL) /*!< Zero-length data received, ignore value in SIZE */
18608 
18609 /* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */
18610 #define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
18611 #define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
18612 
18613 /* Register: USBD_ENABLE */
18614 /* Description: Enable USB */
18615 
18616 /* Bit 0 : Enable USB */
18617 #define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
18618 #define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
18619 #define USBD_ENABLE_ENABLE_Disabled (0x0UL) /*!< USB peripheral is disabled */
18620 #define USBD_ENABLE_ENABLE_Enabled (0x1UL) /*!< USB peripheral is enabled */
18621 
18622 /* Register: USBD_USBPULLUP */
18623 /* Description: Control of the USB pull-up */
18624 
18625 /* Bit 0 : Control of the USB pull-up on the D+ line */
18626 #define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */
18627 #define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
18628 #define USBD_USBPULLUP_CONNECT_Disabled (0x0UL) /*!< Pull-up is disconnected */
18629 #define USBD_USBPULLUP_CONNECT_Enabled (0x1UL) /*!< Pull-up is connected to D+ */
18630 
18631 /* Register: USBD_DPDMVALUE */
18632 /* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */
18633 
18634 /* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */
18635 #define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */
18636 #define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */
18637 #define USBD_DPDMVALUE_STATE_Resume (0x01UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */
18638 #define USBD_DPDMVALUE_STATE_J (0x02UL) /*!< D+ forced high, D- forced low (J state) */
18639 #define USBD_DPDMVALUE_STATE_K (0x04UL) /*!< D+ forced low, D- forced high (K state) */
18640 
18641 /* Register: USBD_DTOGGLE */
18642 /* Description: Data toggle control and status */
18643 
18644 /* Bits 9..8 : Data toggle value */
18645 #define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */
18646 #define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */
18647 #define USBD_DTOGGLE_VALUE_Nop (0x0UL) /*!< No action on data toggle when writing the register with this value */
18648 #define USBD_DTOGGLE_VALUE_Data0 (0x1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */
18649 #define USBD_DTOGGLE_VALUE_Data1 (0x2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */
18650 
18651 /* Bit 7 : Selects IN or OUT endpoint */
18652 #define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */
18653 #define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */
18654 #define USBD_DTOGGLE_IO_Out (0x0UL) /*!< Selects OUT endpoint */
18655 #define USBD_DTOGGLE_IO_In (0x1UL) /*!< Selects IN endpoint */
18656 
18657 /* Bits 2..0 : Select bulk endpoint number */
18658 #define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */
18659 #define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */
18660 
18661 /* Register: USBD_EPINEN */
18662 /* Description: Endpoint IN enable */
18663 
18664 /* Bit 8 : Enable ISO IN endpoint */
18665 #define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */
18666 #define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */
18667 #define USBD_EPINEN_ISOIN_Disable (0x0UL) /*!< Disable ISO IN endpoint 8 */
18668 #define USBD_EPINEN_ISOIN_Enable (0x1UL) /*!< Enable ISO IN endpoint 8 */
18669 
18670 /* Bit 7 : Enable IN endpoint 7 */
18671 #define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */
18672 #define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */
18673 #define USBD_EPINEN_IN7_Disable (0x0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */
18674 #define USBD_EPINEN_IN7_Enable (0x1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */
18675 
18676 /* Bit 6 : Enable IN endpoint 6 */
18677 #define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */
18678 #define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */
18679 #define USBD_EPINEN_IN6_Disable (0x0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
18680 #define USBD_EPINEN_IN6_Enable (0x1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */
18681 
18682 /* Bit 5 : Enable IN endpoint 5 */
18683 #define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */
18684 #define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */
18685 #define USBD_EPINEN_IN5_Disable (0x0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
18686 #define USBD_EPINEN_IN5_Enable (0x1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */
18687 
18688 /* Bit 4 : Enable IN endpoint 4 */
18689 #define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */
18690 #define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */
18691 #define USBD_EPINEN_IN4_Disable (0x0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
18692 #define USBD_EPINEN_IN4_Enable (0x1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */
18693 
18694 /* Bit 3 : Enable IN endpoint 3 */
18695 #define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */
18696 #define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */
18697 #define USBD_EPINEN_IN3_Disable (0x0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
18698 #define USBD_EPINEN_IN3_Enable (0x1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */
18699 
18700 /* Bit 2 : Enable IN endpoint 2 */
18701 #define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
18702 #define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */
18703 #define USBD_EPINEN_IN2_Disable (0x0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
18704 #define USBD_EPINEN_IN2_Enable (0x1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
18705 
18706 /* Bit 1 : Enable IN endpoint 1 */
18707 #define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */
18708 #define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */
18709 #define USBD_EPINEN_IN1_Disable (0x0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
18710 #define USBD_EPINEN_IN1_Enable (0x1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */
18711 
18712 /* Bit 0 : Enable IN endpoint 0 */
18713 #define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */
18714 #define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */
18715 #define USBD_EPINEN_IN0_Disable (0x0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
18716 #define USBD_EPINEN_IN0_Enable (0x1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */
18717 
18718 /* Register: USBD_EPOUTEN */
18719 /* Description: Endpoint OUT enable */
18720 
18721 /* Bit 8 : Enable ISO OUT endpoint 8 */
18722 #define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */
18723 #define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */
18724 #define USBD_EPOUTEN_ISOOUT_Disable (0x0UL) /*!< Disable ISO OUT endpoint 8 */
18725 #define USBD_EPOUTEN_ISOOUT_Enable (0x1UL) /*!< Enable ISO OUT endpoint 8 */
18726 
18727 /* Bit 7 : Enable OUT endpoint 7 */
18728 #define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */
18729 #define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */
18730 #define USBD_EPOUTEN_OUT7_Disable (0x0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
18731 #define USBD_EPOUTEN_OUT7_Enable (0x1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */
18732 
18733 /* Bit 6 : Enable OUT endpoint 6 */
18734 #define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */
18735 #define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */
18736 #define USBD_EPOUTEN_OUT6_Disable (0x0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
18737 #define USBD_EPOUTEN_OUT6_Enable (0x1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */
18738 
18739 /* Bit 5 : Enable OUT endpoint 5 */
18740 #define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */
18741 #define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */
18742 #define USBD_EPOUTEN_OUT5_Disable (0x0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
18743 #define USBD_EPOUTEN_OUT5_Enable (0x1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */
18744 
18745 /* Bit 4 : Enable OUT endpoint 4 */
18746 #define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */
18747 #define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */
18748 #define USBD_EPOUTEN_OUT4_Disable (0x0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
18749 #define USBD_EPOUTEN_OUT4_Enable (0x1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */
18750 
18751 /* Bit 3 : Enable OUT endpoint 3 */
18752 #define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */
18753 #define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */
18754 #define USBD_EPOUTEN_OUT3_Disable (0x0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
18755 #define USBD_EPOUTEN_OUT3_Enable (0x1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */
18756 
18757 /* Bit 2 : Enable OUT endpoint 2 */
18758 #define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
18759 #define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */
18760 #define USBD_EPOUTEN_OUT2_Disable (0x0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
18761 #define USBD_EPOUTEN_OUT2_Enable (0x1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
18762 
18763 /* Bit 1 : Enable OUT endpoint 1 */
18764 #define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */
18765 #define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */
18766 #define USBD_EPOUTEN_OUT1_Disable (0x0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
18767 #define USBD_EPOUTEN_OUT1_Enable (0x1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */
18768 
18769 /* Bit 0 : Enable OUT endpoint 0 */
18770 #define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */
18771 #define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */
18772 #define USBD_EPOUTEN_OUT0_Disable (0x0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
18773 #define USBD_EPOUTEN_OUT0_Enable (0x1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */
18774 
18775 /* Register: USBD_EPSTALL */
18776 /* Description: STALL endpoints */
18777 
18778 /* Bit 8 : Stall selected endpoint */
18779 #define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */
18780 #define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */
18781 #define USBD_EPSTALL_STALL_UnStall (0x0UL) /*!< Don't stall selected endpoint */
18782 #define USBD_EPSTALL_STALL_Stall (0x1UL) /*!< Stall selected endpoint */
18783 
18784 /* Bit 7 : Selects IN or OUT endpoint */
18785 #define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */
18786 #define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */
18787 #define USBD_EPSTALL_IO_Out (0x0UL) /*!< Selects OUT endpoint */
18788 #define USBD_EPSTALL_IO_In (0x1UL) /*!< Selects IN endpoint */
18789 
18790 /* Bits 2..0 : Select endpoint number */
18791 #define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */
18792 #define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */
18793 
18794 /* Register: USBD_ISOSPLIT */
18795 /* Description: Controls the split of ISO buffers */
18796 
18797 /* Bits 15..0 : Controls the split of ISO buffers */
18798 #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */
18799 #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */
18800 #define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */
18801 #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */
18802 
18803 /* Register: USBD_FRAMECNTR */
18804 /* Description: Returns the current value of the start of frame counter */
18805 
18806 /* Bits 10..0 : Returns the current value of the start of frame counter */
18807 #define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */
18808 #define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */
18809 
18810 /* Register: USBD_LOWPOWER */
18811 /* Description: Controls USBD peripheral low power mode during USB suspend */
18812 
18813 /* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */
18814 #define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */
18815 #define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */
18816 #define USBD_LOWPOWER_LOWPOWER_ForceNormal (0x0UL) /*!< Software must write this value to exit low power mode and before performing a remote wake-up */
18817 #define USBD_LOWPOWER_LOWPOWER_LowPower (0x1UL) /*!< Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral */
18818 
18819 /* Register: USBD_ISOINCONFIG */
18820 /* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
18821 
18822 /* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
18823 #define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */
18824 #define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */
18825 #define USBD_ISOINCONFIG_RESPONSE_NoResp (0x0UL) /*!< Endpoint does not respond in that case */
18826 #define USBD_ISOINCONFIG_RESPONSE_ZeroData (0x1UL) /*!< Endpoint responds with a zero-length data packet in that case */
18827 
18828 /* Register: USBD_EPIN_PTR */
18829 /* Description: Description cluster: Data pointer */
18830 
18831 /* Bits 31..0 : Data pointer */
18832 #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
18833 #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
18834 
18835 /* Register: USBD_EPIN_MAXCNT */
18836 /* Description: Description cluster: Maximum number of bytes to transfer */
18837 
18838 /* Bits 6..0 : Maximum number of bytes to transfer */
18839 #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
18840 #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
18841 
18842 /* Register: USBD_EPIN_AMOUNT */
18843 /* Description: Description cluster: Number of bytes transferred in the last transaction */
18844 
18845 /* Bits 6..0 : Number of bytes transferred in the last transaction */
18846 #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
18847 #define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
18848 
18849 /* Register: USBD_ISOIN_PTR */
18850 /* Description: Data pointer */
18851 
18852 /* Bits 31..0 : Data pointer */
18853 #define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
18854 #define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
18855 
18856 /* Register: USBD_ISOIN_MAXCNT */
18857 /* Description: Maximum number of bytes to transfer */
18858 
18859 /* Bits 9..0 : Maximum number of bytes to transfer */
18860 #define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
18861 #define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
18862 
18863 /* Register: USBD_ISOIN_AMOUNT */
18864 /* Description: Number of bytes transferred in the last transaction */
18865 
18866 /* Bits 9..0 : Number of bytes transferred in the last transaction */
18867 #define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
18868 #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
18869 
18870 /* Register: USBD_EPOUT_PTR */
18871 /* Description: Description cluster: Data pointer */
18872 
18873 /* Bits 31..0 : Data pointer */
18874 #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
18875 #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
18876 
18877 /* Register: USBD_EPOUT_MAXCNT */
18878 /* Description: Description cluster: Maximum number of bytes to transfer */
18879 
18880 /* Bits 6..0 : Maximum number of bytes to transfer */
18881 #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
18882 #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
18883 
18884 /* Register: USBD_EPOUT_AMOUNT */
18885 /* Description: Description cluster: Number of bytes transferred in the last transaction */
18886 
18887 /* Bits 6..0 : Number of bytes transferred in the last transaction */
18888 #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
18889 #define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
18890 
18891 /* Register: USBD_ISOOUT_PTR */
18892 /* Description: Data pointer */
18893 
18894 /* Bits 31..0 : Data pointer */
18895 #define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
18896 #define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
18897 
18898 /* Register: USBD_ISOOUT_MAXCNT */
18899 /* Description: Maximum number of bytes to transfer */
18900 
18901 /* Bits 9..0 : Maximum number of bytes to transfer */
18902 #define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
18903 #define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
18904 
18905 /* Register: USBD_ISOOUT_AMOUNT */
18906 /* Description: Number of bytes transferred in the last transaction */
18907 
18908 /* Bits 9..0 : Number of bytes transferred in the last transaction */
18909 #define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
18910 #define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
18911 
18912 
18913 /* Peripheral: WDT */
18914 /* Description: Watchdog Timer */
18915 
18916 /* Register: WDT_TASKS_START */
18917 /* Description: Start the watchdog */
18918 
18919 /* Bit 0 : Start the watchdog */
18920 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
18921 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
18922 #define WDT_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */
18923 
18924 /* Register: WDT_EVENTS_TIMEOUT */
18925 /* Description: Watchdog timeout */
18926 
18927 /* Bit 0 : Watchdog timeout */
18928 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
18929 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
18930 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0x0UL) /*!< Event not generated */
18931 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (0x1UL) /*!< Event generated */
18932 
18933 /* Register: WDT_INTENSET */
18934 /* Description: Enable interrupt */
18935 
18936 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
18937 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
18938 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
18939 #define WDT_INTENSET_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */
18940 #define WDT_INTENSET_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */
18941 #define WDT_INTENSET_TIMEOUT_Set (0x1UL) /*!< Enable */
18942 
18943 /* Register: WDT_INTENCLR */
18944 /* Description: Disable interrupt */
18945 
18946 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
18947 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
18948 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
18949 #define WDT_INTENCLR_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */
18950 #define WDT_INTENCLR_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */
18951 #define WDT_INTENCLR_TIMEOUT_Clear (0x1UL) /*!< Disable */
18952 
18953 /* Register: WDT_RUNSTATUS */
18954 /* Description: Run status */
18955 
18956 /* Bit 0 : Indicates whether or not the watchdog is running */
18957 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
18958 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
18959 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0x0UL) /*!< Watchdog not running */
18960 #define WDT_RUNSTATUS_RUNSTATUS_Running (0x1UL) /*!< Watchdog is running */
18961 
18962 /* Register: WDT_REQSTATUS */
18963 /* Description: Request status */
18964 
18965 /* Bit 7 : Request status for RR[7] register */
18966 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
18967 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
18968 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0x0UL) /*!< RR[7] register is not enabled, or is already requesting reload */
18969 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (0x1UL) /*!< RR[7] register is enabled, and is not yet requesting reload */
18970 
18971 /* Bit 6 : Request status for RR[6] register */
18972 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
18973 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
18974 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0x0UL) /*!< RR[6] register is not enabled, or is already requesting reload */
18975 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (0x1UL) /*!< RR[6] register is enabled, and is not yet requesting reload */
18976 
18977 /* Bit 5 : Request status for RR[5] register */
18978 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
18979 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
18980 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0x0UL) /*!< RR[5] register is not enabled, or is already requesting reload */
18981 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (0x1UL) /*!< RR[5] register is enabled, and is not yet requesting reload */
18982 
18983 /* Bit 4 : Request status for RR[4] register */
18984 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
18985 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
18986 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0x0UL) /*!< RR[4] register is not enabled, or is already requesting reload */
18987 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (0x1UL) /*!< RR[4] register is enabled, and is not yet requesting reload */
18988 
18989 /* Bit 3 : Request status for RR[3] register */
18990 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
18991 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
18992 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0x0UL) /*!< RR[3] register is not enabled, or is already requesting reload */
18993 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (0x1UL) /*!< RR[3] register is enabled, and is not yet requesting reload */
18994 
18995 /* Bit 2 : Request status for RR[2] register */
18996 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
18997 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
18998 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0x0UL) /*!< RR[2] register is not enabled, or is already requesting reload */
18999 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (0x1UL) /*!< RR[2] register is enabled, and is not yet requesting reload */
19000 
19001 /* Bit 1 : Request status for RR[1] register */
19002 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
19003 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
19004 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0x0UL) /*!< RR[1] register is not enabled, or is already requesting reload */
19005 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (0x1UL) /*!< RR[1] register is enabled, and is not yet requesting reload */
19006 
19007 /* Bit 0 : Request status for RR[0] register */
19008 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
19009 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
19010 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0x0UL) /*!< RR[0] register is not enabled, or is already requesting reload */
19011 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (0x1UL) /*!< RR[0] register is enabled, and is not yet requesting reload */
19012 
19013 /* Register: WDT_CRV */
19014 /* Description: Counter reload value */
19015 
19016 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
19017 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
19018 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
19019 
19020 /* Register: WDT_RREN */
19021 /* Description: Enable register for reload request registers */
19022 
19023 /* Bit 7 : Enable or disable RR[7] register */
19024 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
19025 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
19026 #define WDT_RREN_RR7_Disabled (0x0UL) /*!< Disable RR[7] register */
19027 #define WDT_RREN_RR7_Enabled (0x1UL) /*!< Enable RR[7] register */
19028 
19029 /* Bit 6 : Enable or disable RR[6] register */
19030 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
19031 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
19032 #define WDT_RREN_RR6_Disabled (0x0UL) /*!< Disable RR[6] register */
19033 #define WDT_RREN_RR6_Enabled (0x1UL) /*!< Enable RR[6] register */
19034 
19035 /* Bit 5 : Enable or disable RR[5] register */
19036 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
19037 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
19038 #define WDT_RREN_RR5_Disabled (0x0UL) /*!< Disable RR[5] register */
19039 #define WDT_RREN_RR5_Enabled (0x1UL) /*!< Enable RR[5] register */
19040 
19041 /* Bit 4 : Enable or disable RR[4] register */
19042 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
19043 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
19044 #define WDT_RREN_RR4_Disabled (0x0UL) /*!< Disable RR[4] register */
19045 #define WDT_RREN_RR4_Enabled (0x1UL) /*!< Enable RR[4] register */
19046 
19047 /* Bit 3 : Enable or disable RR[3] register */
19048 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
19049 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
19050 #define WDT_RREN_RR3_Disabled (0x0UL) /*!< Disable RR[3] register */
19051 #define WDT_RREN_RR3_Enabled (0x1UL) /*!< Enable RR[3] register */
19052 
19053 /* Bit 2 : Enable or disable RR[2] register */
19054 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
19055 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
19056 #define WDT_RREN_RR2_Disabled (0x0UL) /*!< Disable RR[2] register */
19057 #define WDT_RREN_RR2_Enabled (0x1UL) /*!< Enable RR[2] register */
19058 
19059 /* Bit 1 : Enable or disable RR[1] register */
19060 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
19061 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
19062 #define WDT_RREN_RR1_Disabled (0x0UL) /*!< Disable RR[1] register */
19063 #define WDT_RREN_RR1_Enabled (0x1UL) /*!< Enable RR[1] register */
19064 
19065 /* Bit 0 : Enable or disable RR[0] register */
19066 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
19067 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
19068 #define WDT_RREN_RR0_Disabled (0x0UL) /*!< Disable RR[0] register */
19069 #define WDT_RREN_RR0_Enabled (0x1UL) /*!< Enable RR[0] register */
19070 
19071 /* Register: WDT_CONFIG */
19072 /* Description: Configuration register */
19073 
19074 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
19075 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
19076 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
19077 #define WDT_CONFIG_HALT_Pause (0x0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
19078 #define WDT_CONFIG_HALT_Run (0x1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
19079 
19080 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
19081 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
19082 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
19083 #define WDT_CONFIG_SLEEP_Pause (0x0UL) /*!< Pause watchdog while the CPU is sleeping */
19084 #define WDT_CONFIG_SLEEP_Run (0x1UL) /*!< Keep the watchdog running while the CPU is sleeping */
19085 
19086 /* Register: WDT_RR */
19087 /* Description: Description collection: Reload request n */
19088 
19089 /* Bits 31..0 : Reload request register */
19090 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
19091 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
19092 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
19093 
19094 
19095 /*lint --flb "Leave library region" */
19096 #endif
19097