xref: /hal_nordic-latest/nrfx/mdk/nrf5340_application_bitfields.h

/*

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#ifndef __NRF5340_APPLICATION_BITS_H
#define __NRF5340_APPLICATION_BITS_H

/*lint ++flb "Enter library region" */

/* Peripheral: CACHEDATA */
/* Description: CACHEDATA */

/* Register: CACHEDATA_SET_WAY_DATA0 */
/* Description: Description cluster: Cache data bits [31:0] of SET[n], WAY[o]. */

/* Bits 31..0 : Data */
#define CACHEDATA_SET_WAY_DATA0_Data_Pos (0UL) /*!< Position of Data field. */
#define CACHEDATA_SET_WAY_DATA0_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA0_Data_Pos) /*!< Bit mask of Data field. */

/* Register: CACHEDATA_SET_WAY_DATA1 */
/* Description: Description cluster: Cache data bits [63:32] of SET[n], WAY[o]. */

/* Bits 31..0 : Data */
#define CACHEDATA_SET_WAY_DATA1_Data_Pos (0UL) /*!< Position of Data field. */
#define CACHEDATA_SET_WAY_DATA1_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA1_Data_Pos) /*!< Bit mask of Data field. */

/* Register: CACHEDATA_SET_WAY_DATA2 */
/* Description: Description cluster: Cache data bits [95:64] of SET[n], WAY[o]. */

/* Bits 31..0 : Data */
#define CACHEDATA_SET_WAY_DATA2_Data_Pos (0UL) /*!< Position of Data field. */
#define CACHEDATA_SET_WAY_DATA2_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA2_Data_Pos) /*!< Bit mask of Data field. */

/* Register: CACHEDATA_SET_WAY_DATA3 */
/* Description: Description cluster: Cache data bits [127:96] of SET[n], WAY[o]. */

/* Bits 31..0 : Data */
#define CACHEDATA_SET_WAY_DATA3_Data_Pos (0UL) /*!< Position of Data field. */
#define CACHEDATA_SET_WAY_DATA3_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA3_Data_Pos) /*!< Bit mask of Data field. */


/* Peripheral: CACHEINFO */
/* Description: CACHEINFO */

/* Register: CACHEINFO_SET_WAY */
/* Description: Description collection: Cache information for SET[n], WAY[o]. */

/* Bit 31 : Most recently used way. */
#define CACHEINFO_SET_WAY_MRU_Pos (31UL) /*!< Position of MRU field. */
#define CACHEINFO_SET_WAY_MRU_Msk (0x1UL << CACHEINFO_SET_WAY_MRU_Pos) /*!< Bit mask of MRU field. */
#define CACHEINFO_SET_WAY_MRU_Way0 (0x0UL) /*!< Way0 was most recently used */
#define CACHEINFO_SET_WAY_MRU_Way1 (0x1UL) /*!< Way1 was most recently used */

/* Bit 30 : Valid bit */
#define CACHEINFO_SET_WAY_V_Pos (30UL) /*!< Position of V field. */
#define CACHEINFO_SET_WAY_V_Msk (0x1UL << CACHEINFO_SET_WAY_V_Pos) /*!< Bit mask of V field. */
#define CACHEINFO_SET_WAY_V_Invalid (0x0UL) /*!< Invalid cache line */
#define CACHEINFO_SET_WAY_V_Valid (0x1UL) /*!< Valid cache line */

/* Bits 16..0 : Cache tag. */
#define CACHEINFO_SET_WAY_TAG_Pos (0UL) /*!< Position of TAG field. */
#define CACHEINFO_SET_WAY_TAG_Msk (0x1FFFFUL << CACHEINFO_SET_WAY_TAG_Pos) /*!< Bit mask of TAG field. */


/* Peripheral: CACHE */
/* Description: Cache */

/* Register: CACHE_PROFILING_IHIT */
/* Description: Description cluster: Instruction fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. */

/* Bits 31..0 : Number of instruction cache hits */
#define CACHE_PROFILING_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
#define CACHE_PROFILING_IHIT_HITS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */

/* Register: CACHE_PROFILING_IMISS */
/* Description: Description cluster: Instruction fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. */

/* Bits 31..0 : Number of instruction cache misses */
#define CACHE_PROFILING_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
#define CACHE_PROFILING_IMISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */

/* Register: CACHE_PROFILING_DHIT */
/* Description: Description cluster: Data fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. */

/* Bits 31..0 : Number of data cache hits */
#define CACHE_PROFILING_DHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
#define CACHE_PROFILING_DHIT_HITS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_DHIT_HITS_Pos) /*!< Bit mask of HITS field. */

/* Register: CACHE_PROFILING_DMISS */
/* Description: Description cluster: Data fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. */

/* Bits 31..0 : Number of data cache misses */
#define CACHE_PROFILING_DMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
#define CACHE_PROFILING_DMISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_DMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */

/* Register: CACHE_ENABLE */
/* Description: Enable cache. */

/* Bit 0 : Enable cache */
#define CACHE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CACHE_ENABLE_ENABLE_Msk (0x1UL << CACHE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CACHE_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable cache */
#define CACHE_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable cache */

/* Register: CACHE_INVALIDATE */
/* Description: Invalidate the cache. */

/* Bit 0 : Invalidate the cache */
#define CACHE_INVALIDATE_INVALIDATE_Pos (0UL) /*!< Position of INVALIDATE field. */
#define CACHE_INVALIDATE_INVALIDATE_Msk (0x1UL << CACHE_INVALIDATE_INVALIDATE_Pos) /*!< Bit mask of INVALIDATE field. */
#define CACHE_INVALIDATE_INVALIDATE_Invalidate (0x1UL) /*!< Invalidate the cache */

/* Register: CACHE_ERASE */
/* Description: Erase the cache. */

/* Bit 0 : Erase the cache */
#define CACHE_ERASE_ERASE_Pos (0UL) /*!< Position of ERASE field. */
#define CACHE_ERASE_ERASE_Msk (0x1UL << CACHE_ERASE_ERASE_Pos) /*!< Bit mask of ERASE field. */
#define CACHE_ERASE_ERASE_Erase (0x1UL) /*!< Erase cache */

/* Register: CACHE_PROFILINGENABLE */
/* Description: Enable the profiling counters. */

/* Bit 0 : Enable the profiling counters */
#define CACHE_PROFILINGENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CACHE_PROFILINGENABLE_ENABLE_Msk (0x1UL << CACHE_PROFILINGENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CACHE_PROFILINGENABLE_ENABLE_Disable (0x0UL) /*!< Disable profiling */
#define CACHE_PROFILINGENABLE_ENABLE_Enable (0x1UL) /*!< Enable profiling */

/* Register: CACHE_PROFILINGCLEAR */
/* Description: Clear the profiling counters. */

/* Bit 0 : Clearing the profiling counters */
#define CACHE_PROFILINGCLEAR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */
#define CACHE_PROFILINGCLEAR_CLEAR_Msk (0x1UL << CACHE_PROFILINGCLEAR_CLEAR_Pos) /*!< Bit mask of CLEAR field. */
#define CACHE_PROFILINGCLEAR_CLEAR_Clear (0x1UL) /*!< Clear the profiling counters */

/* Register: CACHE_MODE */
/* Description: Cache mode. Switching from Cache to Ram mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. */

/* Bit 0 : Cache mode */
#define CACHE_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define CACHE_MODE_MODE_Msk (0x1UL << CACHE_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define CACHE_MODE_MODE_Cache (0x0UL) /*!< Cache mode */
#define CACHE_MODE_MODE_Ram (0x1UL) /*!< RAM mode */

/* Register: CACHE_DEBUGLOCK */
/* Description: Lock debug mode. */

/* Bit 0 : Lock debug mode */
#define CACHE_DEBUGLOCK_DEBUGLOCK_Pos (0UL) /*!< Position of DEBUGLOCK field. */
#define CACHE_DEBUGLOCK_DEBUGLOCK_Msk (0x1UL << CACHE_DEBUGLOCK_DEBUGLOCK_Pos) /*!< Bit mask of DEBUGLOCK field. */
#define CACHE_DEBUGLOCK_DEBUGLOCK_Unlocked (0x0UL) /*!< Debug mode unlocked */
#define CACHE_DEBUGLOCK_DEBUGLOCK_Locked (0x1UL) /*!< Debug mode locked */

/* Register: CACHE_ERASESTATUS */
/* Description: Cache erase status. */

/* Bit 0 : Cache erase status */
#define CACHE_ERASESTATUS_ERASESTATUS_Pos (0UL) /*!< Position of ERASESTATUS field. */
#define CACHE_ERASESTATUS_ERASESTATUS_Msk (0x1UL << CACHE_ERASESTATUS_ERASESTATUS_Pos) /*!< Bit mask of ERASESTATUS field. */
#define CACHE_ERASESTATUS_ERASESTATUS_Idle (0x0UL) /*!< Erase is not complete or hasn't started */
#define CACHE_ERASESTATUS_ERASESTATUS_Finished (0x1UL) /*!< Cache erase is finished */

/* Register: CACHE_WRITELOCK */
/* Description: Lock cache updates. Prevents updating of cache content on cache misses, but will continue to lookup instruction/data fetches in content already present in the cache. Ignored in RAM mode. */

/* Bit 0 : Lock cache updates */
#define CACHE_WRITELOCK_WRITELOCK_Pos (0UL) /*!< Position of WRITELOCK field. */
#define CACHE_WRITELOCK_WRITELOCK_Msk (0x1UL << CACHE_WRITELOCK_WRITELOCK_Pos) /*!< Bit mask of WRITELOCK field. */
#define CACHE_WRITELOCK_WRITELOCK_Unlocked (0x0UL) /*!< Cache updates unlocked */
#define CACHE_WRITELOCK_WRITELOCK_Locked (0x1UL) /*!< Cache updates locked */


/* Peripheral: CC_AES */
/* Description: CRYPTOCELL AES engine */

/* Register: CC_AES_AES_KEY_0 */
/* Description: Description collection: AES key value to use in non-tunneling operations, or as the first tunnel stage key in tunneling operations.
        The initial AES_KEY_0[0] register holds the least significant bits [31:0] of the key value. */

/* Bits 31..0 : AES non-tunneling or first tunnel stage key value. */
#define CC_AES_AES_KEY_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_AES_AES_KEY_0_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_KEY_0_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_AES_AES_KEY_1 */
/* Description: Description collection: AES key value to use as the second tunnel stage key in tunneling operations.
        The initial AES_KEY_1[0] register holds the least significant bits [31:0] of the key value. */

/* Bits 31..0 : AES second tunnel stage key value. */
#define CC_AES_AES_KEY_1_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_AES_AES_KEY_1_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_KEY_1_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_AES_AES_IV_0 */
/* Description: Description collection: AES Initialization Vector (IV) to use in non-tunneling operations, or as the first tunnel stage IV in tunneling operations.
        The initial AES_IV_0[0] register holds the least significant bits [31:0] of the IV. */

/* Bits 31..0 : AES non-tunneling or first tunnel stage IV value. */
#define CC_AES_AES_IV_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_AES_AES_IV_0_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_IV_0_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_AES_AES_IV_1 */
/* Description: Description collection: AES Initialization Vector (IV) to use as the second tunnel stage IV in tunneling operations.
        The initial AES_IV_1[0] register holds the least significant bits [31:0] of the IV. */

/* Bits 31..0 : AES second tunnel stage IV value. */
#define CC_AES_AES_IV_1_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_AES_AES_IV_1_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_IV_1_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_AES_AES_CTR */
/* Description: Description collection: AES counter (CTR) to use in non-tunneling and tunneling operations.
        The initial AES_CTR[0] register holds the least significant bits [31:0] of the CTR. */

/* Bits 31..0 : AES CTR value. */
#define CC_AES_AES_CTR_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_AES_AES_CTR_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_CTR_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_AES_AES_BUSY */
/* Description: Status register for AES engine activity. */

/* Bit 0 : AES engine status. */
#define CC_AES_AES_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_AES_AES_BUSY_STATUS_Msk (0x1UL << CC_AES_AES_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_AES_AES_BUSY_STATUS_Idle (0x0UL) /*!< AES engine is idle */
#define CC_AES_AES_BUSY_STATUS_Busy (0x1UL) /*!< AES engine is busy */

/* Register: CC_AES_AES_CMAC_INIT */
/* Description: Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations. */

/* Bit 0 : Generate K1 and K2 for the AES-CMAC operations. */
#define CC_AES_AES_CMAC_INIT_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_AES_AES_CMAC_INIT_ENABLE_Msk (0x1UL << CC_AES_AES_CMAC_INIT_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_AES_AES_CMAC_INIT_ENABLE_Enable (0x1UL) /*!< Initialize AES-CMAC operations. */

/* Register: CC_AES_AES_REMAINING_BYTES */
/* Description: This register should be set with the amount of remaining bytes until the end of the current AES operation. */

/* Bits 31..0 : Remaining bytes util the end of the current AES operation. */
#define CC_AES_AES_REMAINING_BYTES_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_AES_AES_REMAINING_BYTES_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_REMAINING_BYTES_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_AES_AES_CONTROL */
/* Description: Control the AES engine behavior. */

/* Bit 31 : Using direct access and not the DIN-DOUT DMA interface */
#define CC_AES_AES_CONTROL_DIRECT_ACCESS_Pos (31UL) /*!< Position of DIRECT_ACCESS field. */
#define CC_AES_AES_CONTROL_DIRECT_ACCESS_Msk (0x1UL << CC_AES_AES_CONTROL_DIRECT_ACCESS_Pos) /*!< Bit mask of DIRECT_ACCESS field. */
#define CC_AES_AES_CONTROL_DIRECT_ACCESS_Disable (0x0UL) /*!< Access using the DIN-DOUT DMA interface */
#define CC_AES_AES_CONTROL_DIRECT_ACCESS_Enable (0x1UL) /*!< Access using direct access */

/* Bit 28 : This field determines for AES-TO-HASH-AND-DOUT tunneling operations, whether the AES outputs to the HASH the result of the first or the second tunneling stage. */
#define CC_AES_AES_CONTROL_AES_OUT_MID_TUN_TO_HASH_Pos (28UL) /*!< Position of AES_OUT_MID_TUN_TO_HASH field. */
#define CC_AES_AES_CONTROL_AES_OUT_MID_TUN_TO_HASH_Msk (0x1UL << CC_AES_AES_CONTROL_AES_OUT_MID_TUN_TO_HASH_Pos) /*!< Bit mask of AES_OUT_MID_TUN_TO_HASH field. */
#define CC_AES_AES_CONTROL_AES_OUT_MID_TUN_TO_HASH_SecondStage (0x0UL) /*!< The AES engine writes to the HASH the result of the second tunnel stage. */
#define CC_AES_AES_CONTROL_AES_OUT_MID_TUN_TO_HASH_FirstStage (0x1UL) /*!< The AES engine writes to the HASH the result of the first tunnel stage. */

/* Bit 26 : This field configure if the input data to the second tunnel stage is to be padded with zeroes according to how many bytes are remaining. */
#define CC_AES_AES_CONTROL_AES_TUNNEL_B1_PAD_EN_Pos (26UL) /*!< Position of AES_TUNNEL_B1_PAD_EN field. */
#define CC_AES_AES_CONTROL_AES_TUNNEL_B1_PAD_EN_Msk (0x1UL << CC_AES_AES_CONTROL_AES_TUNNEL_B1_PAD_EN_Pos) /*!< Bit mask of AES_TUNNEL_B1_PAD_EN field. */
#define CC_AES_AES_CONTROL_AES_TUNNEL_B1_PAD_EN_Disable (0x0UL) /*!< The data input to the second tunnel stage is not padded with zeros. */
#define CC_AES_AES_CONTROL_AES_TUNNEL_B1_PAD_EN_Enable (0x1UL) /*!< The data input to the second tunnel stage is padded with zeros. */

/* Bit 25 : This fields configure if the AES engine output is the result of the first or second tunneling stage. */
#define CC_AES_AES_CONTROL_AES_OUTPUT_MID_TUNNEL_DATA_Pos (25UL) /*!< Position of AES_OUTPUT_MID_TUNNEL_DATA field. */
#define CC_AES_AES_CONTROL_AES_OUTPUT_MID_TUNNEL_DATA_Msk (0x1UL << CC_AES_AES_CONTROL_AES_OUTPUT_MID_TUNNEL_DATA_Pos) /*!< Bit mask of AES_OUTPUT_MID_TUNNEL_DATA field. */
#define CC_AES_AES_CONTROL_AES_OUTPUT_MID_TUNNEL_DATA_SecondStage (0x0UL) /*!< Output result from the second tunnel stage (standard tunneling). */
#define CC_AES_AES_CONTROL_AES_OUTPUT_MID_TUNNEL_DATA_FirstStage (0x1UL) /*!< Output result from the first tunnel stage. */

/* Bit 24 : Configure if first tunnel stage performs encrypt or decrypt operation. */
#define CC_AES_AES_CONTROL_AES_TUNNEL0_ENCRYPT_Pos (24UL) /*!< Position of AES_TUNNEL0_ENCRYPT field. */
#define CC_AES_AES_CONTROL_AES_TUNNEL0_ENCRYPT_Msk (0x1UL << CC_AES_AES_CONTROL_AES_TUNNEL0_ENCRYPT_Pos) /*!< Bit mask of AES_TUNNEL0_ENCRYPT field. */
#define CC_AES_AES_CONTROL_AES_TUNNEL0_ENCRYPT_Decrypt (0x0UL) /*!< First tunnel stage performs decrypt operations. */
#define CC_AES_AES_CONTROL_AES_TUNNEL0_ENCRYPT_Encrypt (0x1UL) /*!< First tunnel stage performs encrypt operations. */

/* Bit 23 : For tunneling operations this field determine the data that is fed to the second tunneling stage. */
#define CC_AES_AES_CONTROL_AES_TUN_B1_USES_PADDED_DATA_IN_Pos (23UL) /*!< Position of AES_TUN_B1_USES_PADDED_DATA_IN field. */
#define CC_AES_AES_CONTROL_AES_TUN_B1_USES_PADDED_DATA_IN_Msk (0x1UL << CC_AES_AES_CONTROL_AES_TUN_B1_USES_PADDED_DATA_IN_Pos) /*!< Bit mask of AES_TUN_B1_USES_PADDED_DATA_IN field. */
#define CC_AES_AES_CONTROL_AES_TUN_B1_USES_PADDED_DATA_IN_Disable (0x0UL) /*!< The output of the first block is used directly (standard tunneling operation). */
#define CC_AES_AES_CONTROL_AES_TUN_B1_USES_PADDED_DATA_IN_Enable (0x1UL) /*!< The output of the first block is padded before use. */

/* Bit 22 : Configure if first tunnel stage performs encrypt or decrypt operation. */
#define CC_AES_AES_CONTROL_AES_TUNNEL1_DECRYPT_Pos (22UL) /*!< Position of AES_TUNNEL1_DECRYPT field. */
#define CC_AES_AES_CONTROL_AES_TUNNEL1_DECRYPT_Msk (0x1UL << CC_AES_AES_CONTROL_AES_TUNNEL1_DECRYPT_Pos) /*!< Bit mask of AES_TUNNEL1_DECRYPT field. */
#define CC_AES_AES_CONTROL_AES_TUNNEL1_DECRYPT_Encrypt (0x0UL) /*!< Second tunnel stage performs encrypt operations. */
#define CC_AES_AES_CONTROL_AES_TUNNEL1_DECRYPT_Decrypt (0x1UL) /*!< Second tunnel stage performs decrypt operations. */

/* Bits 15..14 : Set the AES key length of the second stage in tunneling operations. */
#define CC_AES_AES_CONTROL_NK_KEY1_Pos (14UL) /*!< Position of NK_KEY1 field. */
#define CC_AES_AES_CONTROL_NK_KEY1_Msk (0x3UL << CC_AES_AES_CONTROL_NK_KEY1_Pos) /*!< Bit mask of NK_KEY1 field. */
#define CC_AES_AES_CONTROL_NK_KEY1_128Bits (0x0UL) /*!< 128 bits key length */
#define CC_AES_AES_CONTROL_NK_KEY1_192Bits (0x1UL) /*!< 192 bits key length */
#define CC_AES_AES_CONTROL_NK_KEY1_256Bits (0x2UL) /*!< 256 bits key length */

/* Bits 13..12 : Set the AES key length in non-tunneling operations, or the AES key length of the first stage in tunneling operations. */
#define CC_AES_AES_CONTROL_NK_KEY0_Pos (12UL) /*!< Position of NK_KEY0 field. */
#define CC_AES_AES_CONTROL_NK_KEY0_Msk (0x3UL << CC_AES_AES_CONTROL_NK_KEY0_Pos) /*!< Bit mask of NK_KEY0 field. */
#define CC_AES_AES_CONTROL_NK_KEY0_128Bits (0x0UL) /*!< 128 bits key length */
#define CC_AES_AES_CONTROL_NK_KEY0_192Bits (0x1UL) /*!< 192 bits key length */
#define CC_AES_AES_CONTROL_NK_KEY0_256Bits (0x2UL) /*!< 256 bits key length */

/* Bit 11 : If MODE_KEY0 is set to CBC, and this field is set, the mode is CBC Bitlocker. */
#define CC_AES_AES_CONTROL_CBC_IS_BITLOCKER_Pos (11UL) /*!< Position of CBC_IS_BITLOCKER field. */
#define CC_AES_AES_CONTROL_CBC_IS_BITLOCKER_Msk (0x1UL << CC_AES_AES_CONTROL_CBC_IS_BITLOCKER_Pos) /*!< Bit mask of CBC_IS_BITLOCKER field. */
#define CC_AES_AES_CONTROL_CBC_IS_BITLOCKER_Disable (0x0UL) /*!< Disable CBC Bitlocker mode */
#define CC_AES_AES_CONTROL_CBC_IS_BITLOCKER_Enable (0x1UL) /*!< Enable CBC Bitlocker mode */

/* Bit 10 : Configure AES engine for standard non-tunneling or tunneling operations. */
#define CC_AES_AES_CONTROL_AES_TUNNEL_Pos (10UL) /*!< Position of AES_TUNNEL field. */
#define CC_AES_AES_CONTROL_AES_TUNNEL_Msk (0x1UL << CC_AES_AES_CONTROL_AES_TUNNEL_Pos) /*!< Bit mask of AES_TUNNEL field. */
#define CC_AES_AES_CONTROL_AES_TUNNEL_Disable (0x0UL) /*!< Standard non-tunneling operations */
#define CC_AES_AES_CONTROL_AES_TUNNEL_Enable (0x1UL) /*!< Enable tunneling operations */

/* Bit 8 : If MODE_KEY0 is set to CBC, and this field is set, the mode is CBC with ESSIV. */
#define CC_AES_AES_CONTROL_CBC_IS_ESSIV_Pos (8UL) /*!< Position of CBC_IS_ESSIV field. */
#define CC_AES_AES_CONTROL_CBC_IS_ESSIV_Msk (0x1UL << CC_AES_AES_CONTROL_CBC_IS_ESSIV_Pos) /*!< Bit mask of CBC_IS_ESSIV field. */
#define CC_AES_AES_CONTROL_CBC_IS_ESSIV_Disable (0x0UL) /*!< Disable CBC with ESSIV mode */
#define CC_AES_AES_CONTROL_CBC_IS_ESSIV_Enable (0x1UL) /*!< Enable CBC with ESSIV mode */

/* Bits 7..5 : Set the AES mode of the second stage in tunneling operations */
#define CC_AES_AES_CONTROL_MODE_KEY1_Pos (5UL) /*!< Position of MODE_KEY1 field. */
#define CC_AES_AES_CONTROL_MODE_KEY1_Msk (0x7UL << CC_AES_AES_CONTROL_MODE_KEY1_Pos) /*!< Bit mask of MODE_KEY1 field. */
#define CC_AES_AES_CONTROL_MODE_KEY1_ECB (0x0UL) /*!< Electronic codebook mode */
#define CC_AES_AES_CONTROL_MODE_KEY1_CBC (0x1UL) /*!< Cipher block chaining mode */
#define CC_AES_AES_CONTROL_MODE_KEY1_CTR (0x2UL) /*!< Counter mode */
#define CC_AES_AES_CONTROL_MODE_KEY1_CBC_MAC (0x3UL) /*!< Cipher block chaining message authentication code mode */
#define CC_AES_AES_CONTROL_MODE_KEY1_XEX_XTS (0x4UL) /*!< Xor-Encrypt-Xor (XEX)-based tweaked-codebook mode with ciphertext stealing (XTS) */
#define CC_AES_AES_CONTROL_MODE_KEY1_XCBC_MAC (0x5UL) /*!< AES in CBC mode with extensions to overcome fixed length limitations */
#define CC_AES_AES_CONTROL_MODE_KEY1_OFB (0x6UL) /*!< AES Output FeedBack mode */
#define CC_AES_AES_CONTROL_MODE_KEY1_CMAC (0x7UL) /*!< Cipher-based Message Authentication Code */

/* Bits 4..2 : Set the AES mode in non-tunneling operations, or the AES mode of the first stage in tunneling operations. */
#define CC_AES_AES_CONTROL_MODE_KEY0_Pos (2UL) /*!< Position of MODE_KEY0 field. */
#define CC_AES_AES_CONTROL_MODE_KEY0_Msk (0x7UL << CC_AES_AES_CONTROL_MODE_KEY0_Pos) /*!< Bit mask of MODE_KEY0 field. */
#define CC_AES_AES_CONTROL_MODE_KEY0_ECB (0x0UL) /*!< Electronic codebook mode */
#define CC_AES_AES_CONTROL_MODE_KEY0_CBC (0x1UL) /*!< Cipher block chaining mode */
#define CC_AES_AES_CONTROL_MODE_KEY0_CTR (0x2UL) /*!< Counter mode */
#define CC_AES_AES_CONTROL_MODE_KEY0_CBC_MAC (0x3UL) /*!< Cipher Block Chaining Message Authentication Code */
#define CC_AES_AES_CONTROL_MODE_KEY0_XEX_XTS (0x4UL) /*!< Xor-Encrypt-Xor (XEX)-based tweaked-codebook mode with ciphertext stealing (XTS) */
#define CC_AES_AES_CONTROL_MODE_KEY0_XCBC_MAC (0x5UL) /*!< AES in CBC mode with extensions to overcome fixed length limitations */
#define CC_AES_AES_CONTROL_MODE_KEY0_OFB (0x6UL) /*!< AES Output FeedBack mode */
#define CC_AES_AES_CONTROL_MODE_KEY0_CMAC (0x7UL) /*!< Cipher-based Message Authentication Code */

/* Bit 1 : This field allows to add distinction to the CBC and CTR modes defined in field MODE_KEY0.
          If MODE_KEY0 is set to CBC in combination with this field, AES mode is CBC-CTS. If MODE_KEY0
          is set to CTR in combination with this field, AES mode is GCTR. */
#define CC_AES_AES_CONTROL_MODE0_IS_CBC_CTS_Pos (1UL) /*!< Position of MODE0_IS_CBC_CTS field. */
#define CC_AES_AES_CONTROL_MODE0_IS_CBC_CTS_Msk (0x1UL << CC_AES_AES_CONTROL_MODE0_IS_CBC_CTS_Pos) /*!< Bit mask of MODE0_IS_CBC_CTS field. */
#define CC_AES_AES_CONTROL_MODE0_IS_CBC_CTS_Disable (0x0UL) /*!< Disable CBC-CTS and GCTR mode */
#define CC_AES_AES_CONTROL_MODE0_IS_CBC_CTS_Enable (0x1UL) /*!< Enable CBC-CTS and GCTR mode */

/* Bit 0 : Set AES encrypt or decrypt mode in non-tunneling operations. */
#define CC_AES_AES_CONTROL_DEC_KEY0_Pos (0UL) /*!< Position of DEC_KEY0 field. */
#define CC_AES_AES_CONTROL_DEC_KEY0_Msk (0x1UL << CC_AES_AES_CONTROL_DEC_KEY0_Pos) /*!< Bit mask of DEC_KEY0 field. */
#define CC_AES_AES_CONTROL_DEC_KEY0_Encrypt (0x0UL) /*!< Perform AES encryption */
#define CC_AES_AES_CONTROL_DEC_KEY0_Decrypt (0x1UL) /*!< Perform AES decryption */

/* Register: CC_AES_AES_HW_FLAGS */
/* Description: Hardware configuration of the AES engine. Reset value holds the supported features. */

/* Bit 12 : If this flag is set, the engine support DFA countermeasures. */
#define CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Pos (12UL) /*!< Position of DFA_CNTRMSR_EXIST field. */
#define CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Pos) /*!< Bit mask of DFA_CNTRMSR_EXIST field. */

/* Bit 11 : If this flag is set, the engine support a second register set for tunneling operations. */
#define CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Pos (11UL) /*!< Position of SECOND_REGS_SET_EXIST field. */
#define CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Pos) /*!< Bit mask of SECOND_REGS_SET_EXIST field. */

/* Bit 10 : If this flag is set, the engine support tunneling operations. */
#define CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Pos (10UL) /*!< Position of AES_TUNNEL_EXIST field. */
#define CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Pos) /*!< Bit mask of AES_TUNNEL_EXIST field. */

/* Bit 9 : If this flag is set, the engine contains the PREV_IV register for faster AES XCBC MAC calculation. */
#define CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Pos (9UL) /*!< Position of AES_SUPPORT_PREV_IV field. */
#define CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Pos) /*!< Bit mask of AES_SUPPORT_PREV_IV field. */

/* Bit 8 : If this flag is set, the engine uses 5 SBOX where each AES round takes 4 cycles. */
#define CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Pos (8UL) /*!< Position of USE_5_SBOXES field. */
#define CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Msk (0x1UL << CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Pos) /*!< Bit mask of USE_5_SBOXES field. */

/* Bit 5 : If this flag is set, the engine uses SBOX tables. */
#define CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Pos (5UL) /*!< Position of USE_SBOX_TABLE field. */
#define CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Msk (0x1UL << CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Pos) /*!< Bit mask of USE_SBOX_TABLE field. */

/* Bit 4 : If this flag is set, the engine only support encrypt operations. */
#define CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Pos (4UL) /*!< Position of ONLY_ENCRYPT field. */
#define CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Msk (0x1UL << CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Pos) /*!< Bit mask of ONLY_ENCRYPT field. */

/* Bit 3 : If this flag is set, the engine support AES CTR mode. */
#define CC_AES_AES_HW_FLAGS_CTR_EXIST_Pos (3UL) /*!< Position of CTR_EXIST field. */
#define CC_AES_AES_HW_FLAGS_CTR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_CTR_EXIST_Pos) /*!< Bit mask of CTR_EXIST field. */

/* Bit 2 : If this flag is set, the engine support DPA countermeasures. */
#define CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Pos (2UL) /*!< Position of DPA_CNTRMSR_EXIST field. */
#define CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Pos) /*!< Bit mask of DPA_CNTRMSR_EXIST field. */

/* Bit 1 : If this flag is set, the engine support AES_LARGE_RKEK. */
#define CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Pos (1UL) /*!< Position of AES_LARGE_RKEK field. */
#define CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Pos) /*!< Bit mask of AES_LARGE_RKEK field. */

/* Bit 0 : If this flag is set, the engine support 192 bits and 256 bits key size. */
#define CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Pos (0UL) /*!< Position of SUPPORT_256_192_KEY field. */
#define CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Msk (0x1UL << CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Pos) /*!< Bit mask of SUPPORT_256_192_KEY field. */

/* Register: CC_AES_AES_CTR_NO_INCREMENT */
/* Description: This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks */

/* Bit 0 : This field enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks */
#define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Msk (0x1UL << CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Disable (0x0UL) /*!< Counter always incremented between blocks */
#define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Enable (0x1UL) /*!< Do not increment counter between blocks */

/* Register: CC_AES_AES_SW_RESET */
/* Description: Reset the AES engine. */

/* Bit 0 : Writing any value to this address resets the AES engine. The reset takes 4 CPU clock cycles to complete. */
#define CC_AES_AES_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
#define CC_AES_AES_SW_RESET_RESET_Msk (0x1UL << CC_AES_AES_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
#define CC_AES_AES_SW_RESET_RESET_Enable (0x1UL) /*!< Reset AES engine. */

/* Register: CC_AES_AES_CMAC_SIZE0_KICK */
/* Description: Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register. */

/* Bit 0 : Force AES CMAC operation with size 0. */
#define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Msk (0x1UL << CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Disable (0x0UL) /*!< Normal AES CMAC operation */
#define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Enable (0x1UL) /*!< Force CMAC operation with size 0 */


/* Peripheral: CC_AHB */
/* Description: CRYPTOCELL AHB interface */

/* Register: CC_AHB_AHBM_SINGLES */
/* Description: This register forces the AHB transactions from CRYPTOCELL master to be always singles. */

/* Bit 0 : Force AHB singles */
#define CC_AHB_AHBM_SINGLES_AHB_SINGLES_Pos (0UL) /*!< Position of AHB_SINGLES field. */
#define CC_AHB_AHBM_SINGLES_AHB_SINGLES_Msk (0x1UL << CC_AHB_AHBM_SINGLES_AHB_SINGLES_Pos) /*!< Bit mask of AHB_SINGLES field. */

/* Register: CC_AHB_AHBM_HPROT */
/* Description: This register holds the AHB HPROT value */

/* Bits 3..0 : The AHB HPROT value */
#define CC_AHB_AHBM_HPROT_AHB_HPROT_Pos (0UL) /*!< Position of AHB_HPROT field. */
#define CC_AHB_AHBM_HPROT_AHB_HPROT_Msk (0xFUL << CC_AHB_AHBM_HPROT_AHB_HPROT_Pos) /*!< Bit mask of AHB_HPROT field. */

/* Register: CC_AHB_AHBM_HMASTLOCK */
/* Description: This register holds AHB HMASTLOCK value */

/* Bit 0 : The AHB HMASTLOCK value. */
#define CC_AHB_AHBM_HMASTLOCK_AHB_HMASTLOCK_Pos (0UL) /*!< Position of AHB_HMASTLOCK field. */
#define CC_AHB_AHBM_HMASTLOCK_AHB_HMASTLOCK_Msk (0x1UL << CC_AHB_AHBM_HMASTLOCK_AHB_HMASTLOCK_Pos) /*!< Bit mask of AHB_HMASTLOCK field. */

/* Register: CC_AHB_AHBM_HNONSEC */
/* Description: This register holds AHB HNONSEC value */

/* Bit 1 : The AHB HNONSEC value for read transaction. */
#define CC_AHB_AHBM_HNONSEC_AHB_READ_HNONSEC_Pos (1UL) /*!< Position of AHB_READ_HNONSEC field. */
#define CC_AHB_AHBM_HNONSEC_AHB_READ_HNONSEC_Msk (0x1UL << CC_AHB_AHBM_HNONSEC_AHB_READ_HNONSEC_Pos) /*!< Bit mask of AHB_READ_HNONSEC field. */

/* Bit 0 : The AHB HNONSEC value for write transaction. */
#define CC_AHB_AHBM_HNONSEC_AHB_WRITE_HNONSEC_Pos (0UL) /*!< Position of AHB_WRITE_HNONSEC field. */
#define CC_AHB_AHBM_HNONSEC_AHB_WRITE_HNONSEC_Msk (0x1UL << CC_AHB_AHBM_HNONSEC_AHB_WRITE_HNONSEC_Pos) /*!< Bit mask of AHB_WRITE_HNONSEC field. */


/* Peripheral: CC_AO */
/* Description: CryptoCell AO */

/* Register: CC_AO_AO_APB_FILTERING */
/* Description: This register holds the AO_APB_FILTERING configuration. */

/* Bit 3 : When this FW controlled field is set, the APBC_ONLY_PRIV_ACCESS_ALLOWED field cannot be modified until the next PoR */
#define CC_AO_AO_APB_FILTERING_ONLY_PRIV_ACCESS_ALLOWED_LOCK_Pos (3UL) /*!< Position of ONLY_PRIV_ACCESS_ALLOWED_LOCK field. */
#define CC_AO_AO_APB_FILTERING_ONLY_PRIV_ACCESS_ALLOWED_LOCK_Msk (0x1UL << CC_AO_AO_APB_FILTERING_ONLY_PRIV_ACCESS_ALLOWED_LOCK_Pos) /*!< Bit mask of ONLY_PRIV_ACCESS_ALLOWED_LOCK field. */

/* Bit 2 : When this FW controlled field is set, the APB slave accepts only privileged accesses */
#define CC_AO_AO_APB_FILTERING_ONLY_PRIV_ACCESS_ALLOWED_Pos (2UL) /*!< Position of ONLY_PRIV_ACCESS_ALLOWED field. */
#define CC_AO_AO_APB_FILTERING_ONLY_PRIV_ACCESS_ALLOWED_Msk (0x1UL << CC_AO_AO_APB_FILTERING_ONLY_PRIV_ACCESS_ALLOWED_Pos) /*!< Bit mask of ONLY_PRIV_ACCESS_ALLOWED field. */

/* Bit 1 : When this FW controlled field is set, the ONLY_SEC_ACCESS_ALLOWED field cannot be modified until the next PoR */
#define CC_AO_AO_APB_FILTERING_ONLY_SEC_ACCESS_ALLOWED_LOCK_Pos (1UL) /*!< Position of ONLY_SEC_ACCESS_ALLOWED_LOCK field. */
#define CC_AO_AO_APB_FILTERING_ONLY_SEC_ACCESS_ALLOWED_LOCK_Msk (0x1UL << CC_AO_AO_APB_FILTERING_ONLY_SEC_ACCESS_ALLOWED_LOCK_Pos) /*!< Bit mask of ONLY_SEC_ACCESS_ALLOWED_LOCK field. */

/* Bit 0 : When this FW controlled field is set, the APB slave accepts only secure accesses */
#define CC_AO_AO_APB_FILTERING_ONLY_SEC_ACCESS_ALLOWED_Pos (0UL) /*!< Position of ONLY_SEC_ACCESS_ALLOWED field. */
#define CC_AO_AO_APB_FILTERING_ONLY_SEC_ACCESS_ALLOWED_Msk (0x1UL << CC_AO_AO_APB_FILTERING_ONLY_SEC_ACCESS_ALLOWED_Pos) /*!< Bit mask of ONLY_SEC_ACCESS_ALLOWED field. */

/* Register: CC_AO_CC_SW_RESET */
/* Description: Reset the CRYPTOCELL subsystem. */

/* Bit 0 : Writing any value to this address resets the CRYPTOCELL subsystem. The reset takes 4 CPU clock cycles to complete. */
#define CC_AO_CC_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
#define CC_AO_CC_SW_RESET_RESET_Msk (0x1UL << CC_AO_CC_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
#define CC_AO_CC_SW_RESET_RESET_Enable (0x1UL) /*!< Reset CRYPTOCELL subsystem. */


/* Peripheral: CC_CHACHA */
/* Description: CRYPTOCELL CHACHA engine */

/* Register: CC_CHACHA_CHACHA_CONTROL */
/* Description: Control the CHACHA engine behavior. */

/* Bit 10 : Use 96 bits Initialization Vector (IV) */
#define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Pos (10UL) /*!< Position of USE_IV_96BIT field. */
#define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Pos) /*!< Bit mask of USE_IV_96BIT field. */
#define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Disable (0x0UL) /*!< Use default size IV of 64 bit */
#define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Enable (0x1UL) /*!< The IV is 96 bits */

/* Bit 9 : Reset block counter for new messages */
#define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Pos (9UL) /*!< Position of RESET_BLOCK_CNT field. */
#define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Pos) /*!< Bit mask of RESET_BLOCK_CNT field. */
#define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Disable (0x0UL) /*!< Use current block counter value */
#define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Enable (0x1UL) /*!< Reset block counter value to zero */

/* Bits 5..4 : Set number of permutation rounds, default value is 20. */
#define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Pos (4UL) /*!< Position of NUM_OF_ROUNDS field. */
#define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Msk (0x3UL << CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Pos) /*!< Bit mask of NUM_OF_ROUNDS field. */
#define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Default (0x0UL) /*!< Use 20 rounds of rotation (default) */
#define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_12Rounds (0x1UL) /*!< Use 12 rounds of rotation */
#define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_8Rounds (0x2UL) /*!< Use 8 rounds of rotation */

/* Bit 3 : Key length selection. */
#define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Pos (3UL) /*!< Position of KEY_LEN field. */
#define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Pos) /*!< Bit mask of KEY_LEN field. */
#define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_256Bits (0x0UL) /*!< Use 256 bits key length */
#define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_128Bits (0x1UL) /*!< Use 128 bits key length */

/* Bit 2 : Generate the key to use in Poly1305 message authentication code calculation. */
#define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Pos (2UL) /*!< Position of GEN_KEY_POLY1305 field. */
#define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Pos) /*!< Bit mask of GEN_KEY_POLY1305 field. */
#define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Disable (0x0UL) /*!< Do not generate Poly1305 key */
#define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Enable (0x1UL) /*!< Generate Poly1305 key */

/* Bit 1 : Perform initialization for a new message */
#define CC_CHACHA_CHACHA_CONTROL_INIT_Pos (1UL) /*!< Position of INIT field. */
#define CC_CHACHA_CHACHA_CONTROL_INIT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_INIT_Pos) /*!< Bit mask of INIT field. */
#define CC_CHACHA_CHACHA_CONTROL_INIT_Disable (0x0UL) /*!< Message already initialized */
#define CC_CHACHA_CHACHA_CONTROL_INIT_Enable (0x1UL) /*!< Initialize new message */

/* Bit 0 : Run engine in ChaCha or Salsa mode */
#define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Pos (0UL) /*!< Position of CHACHA_OR_SALSA field. */
#define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Pos) /*!< Bit mask of CHACHA_OR_SALSA field. */
#define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_ChaCha (0x0UL) /*!< Run engine in ChaCha mode */
#define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Salsa (0x1UL) /*!< Run engine in Salsa mode */

/* Register: CC_CHACHA_CHACHA_VERSION */
/* Description: CHACHA engine HW version */

/* Bits 31..0 :   */
#define CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Pos (0UL) /*!< Position of CHACHA_VERSION field. */
#define CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Pos) /*!< Bit mask of CHACHA_VERSION field. */

/* Register: CC_CHACHA_CHACHA_KEY */
/* Description: Description collection: CHACHA key value to use. The initial CHACHA_KEY[0] register holds the least significant bits [31:0] of the key value. */

/* Bits 31..0 : CHACHA key value. */
#define CC_CHACHA_CHACHA_KEY_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_CHACHA_CHACHA_KEY_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_KEY_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_CHACHA_CHACHA_IV */
/* Description: Description collection: CHACHA Initialization Vector (IV) to use. The IV is also known as the nonce. */

/* Bits 31..0 : CHACHA IV value. */
#define CC_CHACHA_CHACHA_IV_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_CHACHA_CHACHA_IV_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_IV_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_CHACHA_CHACHA_BUSY */
/* Description: Status register for CHACHA engine activity. */

/* Bit 0 : CHACHA engine status. */
#define CC_CHACHA_CHACHA_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_CHACHA_CHACHA_BUSY_STATUS_Msk (0x1UL << CC_CHACHA_CHACHA_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_CHACHA_CHACHA_BUSY_STATUS_Idle (0x0UL) /*!< CHACHA engine is idle */
#define CC_CHACHA_CHACHA_BUSY_STATUS_Busy (0x1UL) /*!< CHACHA engine is busy */

/* Register: CC_CHACHA_CHACHA_HW_FLAGS */
/* Description: Hardware configuration of the CHACHA engine. Reset value holds the supported features. */

/* Bit 2 : If this flag is set, the next matrix calculated when the current one is written to data output path. */
#define CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Pos (2UL) /*!< Position of FAST_CHACHA field. */
#define CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Pos) /*!< Bit mask of FAST_CHACHA field. */

/* Bit 1 : If this flag is set, the engine include Salsa support */
#define CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Pos (1UL) /*!< Position of SALSA_EXISTS field. */
#define CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Pos) /*!< Bit mask of SALSA_EXISTS field. */

/* Bit 0 : If this flag is set, the engine include ChaCha support */
#define CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Pos (0UL) /*!< Position of CHACHA_EXISTS field. */
#define CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Pos) /*!< Bit mask of CHACHA_EXISTS field. */

/* Register: CC_CHACHA_CHACHA_BLOCK_CNT_LSB */
/* Description: Store the LSB value of the block counter, in order to support suspend/resume of operation */

/* Bits 31..0 : This register holds the ChaCha block counter bits [31:0] and must be read and written during respectively suspend and resume operations. */
#define CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_CHACHA_CHACHA_BLOCK_CNT_MSB */
/* Description: Store the MSB value of the block counter, in order to support suspend/resume of operation */

/* Bits 31..0 : This register holds the ChaCha block counter bits [63:32] and must be read and written during respectively suspend and resume operations. */
#define CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_CHACHA_CHACHA_SW_RESET */
/* Description: Reset the CHACHA engine. */

/* Bit 0 : Writing any value to this address resets the CHACHA engine. The reset takes 4 CPU clock cycles to complete. */
#define CC_CHACHA_CHACHA_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
#define CC_CHACHA_CHACHA_SW_RESET_RESET_Msk (0x1UL << CC_CHACHA_CHACHA_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
#define CC_CHACHA_CHACHA_SW_RESET_RESET_Enable (0x1UL) /*!< Reset CHACHA engine. */

/* Register: CC_CHACHA_CHACHA_POLY1305_KEY */
/* Description: Description collection: The auto-generated key to use in Poly1305 MAC calculation. The initial CHACHA_POLY1305_KEY[0] register holds the least significant bits [31:0] of the key value. */

/* Bits 31..0 : Poly1305 key value. */
#define CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_CHACHA_CHACHA_ENDIANNESS */
/* Description: CHACHA engine data order configuration. */

/* Bit 4 : Change the byte order of the output data. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Pos (4UL) /*!< Position of CHACHA_DOUT_BYTE_ORDER field. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Pos) /*!< Bit mask of CHACHA_DOUT_BYTE_ORDER field. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Default (0x0UL) /*!< Use default byte order within each output word, where bytes are ordered as follows: B0, B1, B2, B3. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Reverse (0x1UL) /*!< Reverse the byte order within each output word, where bytes are re-ordered as follows: B3, B2, B1, B0. */

/* Bit 3 : Change the word order of the output data. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Pos (3UL) /*!< Position of CHACHA_DOUT_WORD_ORDER field. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Pos) /*!< Bit mask of CHACHA_DOUT_WORD_ORDER field. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Default (0x0UL) /*!< Uses default word order for 128-bits output, where words are ordered as follows: w0, w1, w2, w3. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Reverse (0x1UL) /*!< Reverse the word order for 128-bits output, where words are re-ordered as follows: w3, w2, w1, w0. */

/* Bit 2 : Change the quarter of a matrix order in the engine. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Pos (2UL) /*!< Position of CHACHA_CORE_MATRIX_LBE_ORDER field. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Pos) /*!< Bit mask of CHACHA_CORE_MATRIX_LBE_ORDER field. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Default (0x0UL) /*!< Use default quarter of matrix order, where quarters are ordered as follows: q0, q1, q2, q3. Each quarter represents a 128-bits section of the matrix. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Reverse (0x1UL) /*!< Reverse the order of matrix quarters, where quarters are re-ordered as follows: q3, q2, q1, q0. Each quarter represents a 128-bits section of the matrix. */

/* Bit 1 : Change the byte order of the input data. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Pos (1UL) /*!< Position of CHACHA_DIN_BYTE_ORDER field. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Pos) /*!< Bit mask of CHACHA_DIN_BYTE_ORDER field. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Default (0x0UL) /*!< Use default byte order within each input word, where bytes are ordered as follows: B0, B1, B2, B3. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Reverse (0x1UL) /*!< Reverse the byte order within each input word, where bytes are re-ordered as follows: B3, B2, B1, B0. */

/* Bit 0 : Change the word order of the input data. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Pos (0UL) /*!< Position of CHACHA_DIN_WORD_ORDER field. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Pos) /*!< Bit mask of CHACHA_DIN_WORD_ORDER field. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Default (0x0UL) /*!< Use default word order for 128-bits input, where words are ordered as follows: w0, w1, w2, w3. */
#define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Reverse (0x1UL) /*!< Reverses the word order for 128-bits input, where words are re-ordered as follows: w3, w2, w1, w0. */

/* Register: CC_CHACHA_CHACHA_DEBUG */
/* Description: Debug register for the CHACHA engine */

/* Bits 1..0 : Reflects the debug state of the CHACHA FSM. */
#define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Pos (0UL) /*!< Position of FSM_STATE field. */
#define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Msk (0x3UL << CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Pos) /*!< Bit mask of FSM_STATE field. */
#define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_IDLE_STATE (0x0UL) /*!< CHACHA FSM is in idle state */
#define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_INIT_STATE (0x1UL) /*!< CHACHA FSM is in init state */
#define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_ROUNDS_STATE (0x2UL) /*!< CHACHA FSM is in rounds state */
#define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_FINAL_STATE (0x3UL) /*!< CHACHA FSM is in final state */


/* Peripheral: CC_CTL */
/* Description: CRYPTOCELL CTL interface */

/* Register: CC_CTL_CRYPTO_CTL */
/* Description: Defines the cryptographic flow. */

/* Bits 4..0 : Configure the cryptographic engine mode. */
#define CC_CTL_CRYPTO_CTL_MODE_Pos (0UL) /*!< Position of MODE field. */
#define CC_CTL_CRYPTO_CTL_MODE_Msk (0x1FUL << CC_CTL_CRYPTO_CTL_MODE_Pos) /*!< Bit mask of MODE field. */
#define CC_CTL_CRYPTO_CTL_MODE_Bypass (0x00UL) /*!< Bypass cryptographic engine */
#define CC_CTL_CRYPTO_CTL_MODE_AESActive (0x01UL) /*!< Use AES engine */
#define CC_CTL_CRYPTO_CTL_MODE_AESToHashActive (0x02UL) /*!< Pipe AES engine output to HASH engine input */
#define CC_CTL_CRYPTO_CTL_MODE_AESAndHashActive (0x03UL) /*!< Process input using both AES and HASH engine in parallell */
#define CC_CTL_CRYPTO_CTL_MODE_HashActive (0x07UL) /*!< Use HASH engine */
#define CC_CTL_CRYPTO_CTL_MODE_AESMACAndBypassActive (0x09UL) /*!< Calculate AES MAC and bypass */
#define CC_CTL_CRYPTO_CTL_MODE_AESToHashAndDOUTActive (0x0AUL) /*!< Pipe AES engine output to HASH engine input. The resulting digest output is piped to DOUT buffer. */
#define CC_CTL_CRYPTO_CTL_MODE_ChaChaActive (0x10UL) /*!< Use CHACHA engine */

/* Register: CC_CTL_CRYPTO_BUSY */
/* Description: Status register for cryptographic cores engine activity. */

/* Bit 0 : Cryptographic core engines status. */
#define CC_CTL_CRYPTO_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_CTL_CRYPTO_BUSY_STATUS_Msk (0x1UL << CC_CTL_CRYPTO_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_CTL_CRYPTO_BUSY_STATUS_Idle (0x0UL) /*!< Cryptographic core engines are idle */
#define CC_CTL_CRYPTO_BUSY_STATUS_Busy (0x1UL) /*!< Cryptographic core engines are busy */

/* Register: CC_CTL_HASH_BUSY */
/* Description: Status register for HASH engine activity. */

/* Bit 0 : Hash engine status. */
#define CC_CTL_HASH_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_CTL_HASH_BUSY_STATUS_Msk (0x1UL << CC_CTL_HASH_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_CTL_HASH_BUSY_STATUS_Idle (0x0UL) /*!< HASH engine is idle */
#define CC_CTL_HASH_BUSY_STATUS_Busy (0x1UL) /*!< HASH engine is busy */

/* Register: CC_CTL_CONTEXT_ID */
/* Description: A general-purpose read/write register. */

/* Bits 7..0 : Context ID */
#define CC_CTL_CONTEXT_ID_CONTEXT_ID_Pos (0UL) /*!< Position of CONTEXT_ID field. */
#define CC_CTL_CONTEXT_ID_CONTEXT_ID_Msk (0xFFUL << CC_CTL_CONTEXT_ID_CONTEXT_ID_Pos) /*!< Bit mask of CONTEXT_ID field. */


/* Peripheral: CC_DIN */
/* Description: CRYPTOCELL Data IN interface */

/* Register: CC_DIN_DIN_BUFFER */
/* Description: Used by CPU to write data directly to the DIN buffer, which is then sent to the cryptographic engines for processing. */

/* Bits 31..0 : This register is mapped into 8 addresses in order to enable a CPU burst. */
#define CC_DIN_DIN_BUFFER_DATA_Pos (0UL) /*!< Position of DATA field. */
#define CC_DIN_DIN_BUFFER_DATA_Msk (0xFFFFFFFFUL << CC_DIN_DIN_BUFFER_DATA_Pos) /*!< Bit mask of DATA field. */

/* Register: CC_DIN_DIN_DMA_MEM_BUSY */
/* Description: Status register for DIN DMA engine activity when accessing memory. */

/* Bit 0 : DIN memory DMA engine status. */
#define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Msk (0x1UL << CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Idle (0x0UL) /*!< DIN memory DMA engine is idle */
#define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Busy (0x1UL) /*!< DIN memory DMA engine is busy */

/* Register: CC_DIN_SRC_MEM_ADDR */
/* Description: Data source address in memory. */

/* Bits 31..0 : Source address in memory. */
#define CC_DIN_SRC_MEM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
#define CC_DIN_SRC_MEM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DIN_SRC_MEM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */

/* Register: CC_DIN_SRC_MEM_SIZE */
/* Description: The number of bytes to be read from memory. Writing to this register triggers the DMA operation. */

/* Bit 31 : This field is reserved */
#define CC_DIN_SRC_MEM_SIZE_LAST_Pos (31UL) /*!< Position of LAST field. */
#define CC_DIN_SRC_MEM_SIZE_LAST_Msk (0x1UL << CC_DIN_SRC_MEM_SIZE_LAST_Pos) /*!< Bit mask of LAST field. */

/* Bit 30 : This field is reserved */
#define CC_DIN_SRC_MEM_SIZE_FIRST_Pos (30UL) /*!< Position of FIRST field. */
#define CC_DIN_SRC_MEM_SIZE_FIRST_Msk (0x1UL << CC_DIN_SRC_MEM_SIZE_FIRST_Pos) /*!< Bit mask of FIRST field. */

/* Bits 29..0 : Total number of bytes to read from memory. */
#define CC_DIN_SRC_MEM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
#define CC_DIN_SRC_MEM_SIZE_SIZE_Msk (0x3FFFFFFFUL << CC_DIN_SRC_MEM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */

/* Register: CC_DIN_SRC_SRAM_ADDR */
/* Description: Data source address in RNG SRAM. */

/* Bits 31..0 : Source address in RNG SRAM. */
#define CC_DIN_SRC_SRAM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
#define CC_DIN_SRC_SRAM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DIN_SRC_SRAM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */

/* Register: CC_DIN_SRC_SRAM_SIZE */
/* Description: The number of bytes to be read from RNG SRAM. Writing to this register triggers the DMA operation. */

/* Bits 31..0 : Total number of bytes to read from RNG SRAM. */
#define CC_DIN_SRC_SRAM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
#define CC_DIN_SRC_SRAM_SIZE_SIZE_Msk (0xFFFFFFFFUL << CC_DIN_SRC_SRAM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */

/* Register: CC_DIN_DIN_DMA_SRAM_BUSY */
/* Description: Status register for DIN DMA engine activity when accessing RNG SRAM. */

/* Bit 0 : DIN RNG SRAM DMA engine status. */
#define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Msk (0x1UL << CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Idle (0x0UL) /*!< DIN RNG SRAM DMA engine is idle */
#define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Busy (0x1UL) /*!< DIN RNG SRAM DMA engine is busy */

/* Register: CC_DIN_DIN_DMA_SRAM_ENDIANNESS */
/* Description: Configure the endianness of DIN DMA transactions towards RNG SRAM. */

/* Bit 0 : Endianness of DIN DMA transactions towards RNG SRAM. The default value is little-endian. */
#define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */
#define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
#define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for RNG SRAM DMA transactions */
#define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for RNG SRAM DMA transactions */

/* Register: CC_DIN_DIN_SW_RESET */
/* Description: Reset the DIN DMA engine. */

/* Bit 0 : Writing any value to this address resets the DIN DMA engine. The reset takes 4 CPU clock cycles to complete. */
#define CC_DIN_DIN_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
#define CC_DIN_DIN_SW_RESET_RESET_Msk (0x1UL << CC_DIN_DIN_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
#define CC_DIN_DIN_SW_RESET_RESET_Enable (0x1UL) /*!< Reset DIN DMA engine. */

/* Register: CC_DIN_DIN_CPU_DATA */
/* Description: Specifies the number of bytes the CPU will write to the DIN_BUFFER, ensuring the cryptographic engine processes the correct amount of data. */

/* Bits 15..0 : When using CPU direct write to the DIN_BUFFER, the size of input data in bytes should be written to this register. */
#define CC_DIN_DIN_CPU_DATA_SIZE_Pos (0UL) /*!< Position of SIZE field. */
#define CC_DIN_DIN_CPU_DATA_SIZE_Msk (0xFFFFUL << CC_DIN_DIN_CPU_DATA_SIZE_Pos) /*!< Bit mask of SIZE field. */

/* Register: CC_DIN_DIN_WRITE_ALIGN */
/* Description: Indicates that the next CPU write to the DIN_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). */

/* Bit 0 : Next CPU write to the DIN_BUFFER is the last word. */
#define CC_DIN_DIN_WRITE_ALIGN_LAST_Pos (0UL) /*!< Position of LAST field. */
#define CC_DIN_DIN_WRITE_ALIGN_LAST_Msk (0x1UL << CC_DIN_DIN_WRITE_ALIGN_LAST_Pos) /*!< Bit mask of LAST field. */
#define CC_DIN_DIN_WRITE_ALIGN_LAST_Confirm (0x1UL) /*!< The next CPU write is the last in the sequence. */

/* Register: CC_DIN_DIN_FIFO_EMPTY */
/* Description: Register indicating if DIN FIFO is empty and if more data can be accepted. */

/* Bit 0 : DIN FIFO status */
#define CC_DIN_DIN_FIFO_EMPTY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_DIN_DIN_FIFO_EMPTY_STATUS_Msk (0x1UL << CC_DIN_DIN_FIFO_EMPTY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_DIN_DIN_FIFO_EMPTY_STATUS_NotEmpty (0x0UL) /*!< DIN FIFO is not empty */
#define CC_DIN_DIN_FIFO_EMPTY_STATUS_Empty (0x1UL) /*!< DIN FIFO is empty, and more data can be accepted */

/* Register: CC_DIN_DIN_FIFO_RESET */
/* Description: Reset the DIN FIFO, effectively clearing the FIFO for new data. */

/* Bit 0 : Writing any value to this address resets the DIN FIFO. */
#define CC_DIN_DIN_FIFO_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
#define CC_DIN_DIN_FIFO_RESET_RESET_Msk (0x1UL << CC_DIN_DIN_FIFO_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
#define CC_DIN_DIN_FIFO_RESET_RESET_Enable (0x1UL) /*!< Reset DIN FIFO. */


/* Peripheral: CC_DOUT */
/* Description: CRYPTOCELL Data OUT interface */

/* Register: CC_DOUT_DOUT_BUFFER */
/* Description: Cryptographic results directly accessible by the CPU. */

/* Bits 31..0 : This address can be used by the CPU to read data directly from the DOUT buffer. */
#define CC_DOUT_DOUT_BUFFER_DATA_Pos (0UL) /*!< Position of DATA field. */
#define CC_DOUT_DOUT_BUFFER_DATA_Msk (0xFFFFFFFFUL << CC_DOUT_DOUT_BUFFER_DATA_Pos) /*!< Bit mask of DATA field. */

/* Register: CC_DOUT_DOUT_DMA_MEM_BUSY */
/* Description: Status register for DOUT DMA engine activity when accessing memory. */

/* Bit 0 : DOUT memory DMA engine status. */
#define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Idle (0x0UL) /*!< DOUT memory DMA engine is idle */
#define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Busy (0x1UL) /*!< DOUT memory DMA engine is busy */

/* Register: CC_DOUT_DST_MEM_ADDR */
/* Description: Data destination address in memory. */

/* Bits 31..0 : Destination address in memory. */
#define CC_DOUT_DST_MEM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
#define CC_DOUT_DST_MEM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DOUT_DST_MEM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */

/* Register: CC_DOUT_DST_MEM_SIZE */
/* Description: The number of bytes to be written to memory. */

/* Bit 31 : This field is reserved */
#define CC_DOUT_DST_MEM_SIZE_LAST_Pos (31UL) /*!< Position of LAST field. */
#define CC_DOUT_DST_MEM_SIZE_LAST_Msk (0x1UL << CC_DOUT_DST_MEM_SIZE_LAST_Pos) /*!< Bit mask of LAST field. */

/* Bit 30 : This field is reserved */
#define CC_DOUT_DST_MEM_SIZE_FIRST_Pos (30UL) /*!< Position of FIRST field. */
#define CC_DOUT_DST_MEM_SIZE_FIRST_Msk (0x1UL << CC_DOUT_DST_MEM_SIZE_FIRST_Pos) /*!< Bit mask of FIRST field. */

/* Bits 29..0 : Total number of bytes to write to memory. */
#define CC_DOUT_DST_MEM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
#define CC_DOUT_DST_MEM_SIZE_SIZE_Msk (0x3FFFFFFFUL << CC_DOUT_DST_MEM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */

/* Register: CC_DOUT_DST_SRAM_ADDR */
/* Description: Data destination address in RNG SRAM. */

/* Bits 31..0 : Destination address in RNG SRAM. */
#define CC_DOUT_DST_SRAM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
#define CC_DOUT_DST_SRAM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DOUT_DST_SRAM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */

/* Register: CC_DOUT_DST_SRAM_SIZE */
/* Description: The number of bytes to be written to RNG SRAM. */

/* Bits 31..0 : Total number of bytes to write to RNG SRAM. */
#define CC_DOUT_DST_SRAM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
#define CC_DOUT_DST_SRAM_SIZE_SIZE_Msk (0xFFFFFFFFUL << CC_DOUT_DST_SRAM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */

/* Register: CC_DOUT_DOUT_DMA_SRAM_BUSY */
/* Description: Status register for DOUT DMA engine activity when accessing RNG SRAM. */

/* Bit 0 : DOUT RNG SRAM DMA engine status. */
#define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Idle (0x0UL) /*!< DOUT RNG SRAM DMA engine is idle */
#define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Busy (0x1UL) /*!< DOUT RNG SRAM DMA engine is busy */

/* Register: CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS */
/* Description: Configure the endianness of DOUT DMA transactions towards RNG SRAM. */

/* Bit 0 : Endianness of DOUT DMA transactions towards RNG SRAM. The default value is little-endian. */
#define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */
#define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
#define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for RNG SRAM DMA transactions */
#define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for RNG SRAM DMA transactions */

/* Register: CC_DOUT_DOUT_READ_ALIGN */
/* Description: Indication that the next CPU read from the DOUT_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). */

/* Bit 0 : Next CPU read from the DOUT_BUFFER is the last word, and the remaining read aligned content can be flushed. */
#define CC_DOUT_DOUT_READ_ALIGN_LAST_Pos (0UL) /*!< Position of LAST field. */
#define CC_DOUT_DOUT_READ_ALIGN_LAST_Msk (0x1UL << CC_DOUT_DOUT_READ_ALIGN_LAST_Pos) /*!< Bit mask of LAST field. */
#define CC_DOUT_DOUT_READ_ALIGN_LAST_Flush (0x1UL) /*!< Flush the remaining read aligned content. */

/* Register: CC_DOUT_DOUT_FIFO_EMPTY */
/* Description: Register indicating if DOUT FIFO is empty or if more data will come. */

/* Bit 0 : DOUT FIFO status */
#define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_NotEmpty (0x0UL) /*!< DOUT FIFO is not empty, and more data will come */
#define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Empty (0x1UL) /*!< DOUT FIFO is empty */

/* Register: CC_DOUT_DOUT_SW_RESET */
/* Description: Reset the DOUT DMA engine. */

/* Bit 0 : Writing any value to this address resets the DOUT DMA engine. The reset takes 4 CPU clock cycles to complete. */
#define CC_DOUT_DOUT_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
#define CC_DOUT_DOUT_SW_RESET_RESET_Msk (0x1UL << CC_DOUT_DOUT_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
#define CC_DOUT_DOUT_SW_RESET_RESET_Enable (0x1UL) /*!< Reset DOUT DMA engine. */


/* Peripheral: CC_GHASH */
/* Description: CRYPTOCELL GHASH engine */

/* Register: CC_GHASH_GHASH_SUBKEY */
/* Description: Description collection: GHASH subkey value to use. The initial GHASH_SUBKEY[0] register holds the least significant bits [31:0] of the subkey value. */

/* Bits 31..0 : GHASH subkey value. */
#define CC_GHASH_GHASH_SUBKEY_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_GHASH_GHASH_SUBKEY_VALUE_Msk (0xFFFFFFFFUL << CC_GHASH_GHASH_SUBKEY_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_GHASH_GHASH_IV */
/* Description: Description collection: GHASH Initialization Vector (IV) to use. The initial GHASH_IV[0] register holds the least significant bits [31:0] of the IV. */

/* Bits 31..0 : GHASH IV value. */
#define CC_GHASH_GHASH_IV_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_GHASH_GHASH_IV_VALUE_Msk (0xFFFFFFFFUL << CC_GHASH_GHASH_IV_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_GHASH_GHASH_BUSY */
/* Description: Status register for GHASH engine activity. */

/* Bit 0 : GHASH engine status. */
#define CC_GHASH_GHASH_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_GHASH_GHASH_BUSY_STATUS_Msk (0x1UL << CC_GHASH_GHASH_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_GHASH_GHASH_BUSY_STATUS_Idle (0x0UL) /*!< GHASH engine is idle */
#define CC_GHASH_GHASH_BUSY_STATUS_Busy (0x1UL) /*!< GHASH engine is busy */

/* Register: CC_GHASH_GHASH_INIT */
/* Description: Configure the GHASH engine for a new GHASH operation. */

/* Bit 0 : Initialize a new GHASH operation. */
#define CC_GHASH_GHASH_INIT_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_GHASH_GHASH_INIT_ENABLE_Msk (0x1UL << CC_GHASH_GHASH_INIT_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_GHASH_GHASH_INIT_ENABLE_Enable (0x1UL) /*!< Initialize GHASH operation */


/* Peripheral: CC_HASH */
/* Description: CRYPTOCELL HASH engine */

/* Register: CC_HASH_HASH_H */
/* Description: Description collection: HASH_H value registers. The initial HASH_H[0] register holds the least significant bits [31:0] of the value. */

/* Bits 31..0 : Write the initial hash value before start of digest operation, and read the final hash value result after
          the digest operation has been completed. */
#define CC_HASH_HASH_H_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_HASH_HASH_H_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_H_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_HASH_HASH_PAD_AUTO */
/* Description: Configure the HASH engine to automatically pad data at the end of the DMA transfer to complete the digest operation. */

/* Bit 0 : Enable automatic padding in hardware. */
#define CC_HASH_HASH_PAD_AUTO_HWPAD_Pos (0UL) /*!< Position of HWPAD field. */
#define CC_HASH_HASH_PAD_AUTO_HWPAD_Msk (0x1UL << CC_HASH_HASH_PAD_AUTO_HWPAD_Pos) /*!< Bit mask of HWPAD field. */
#define CC_HASH_HASH_PAD_AUTO_HWPAD_Disable (0x0UL) /*!< Do not enable automatic hardware padding. */
#define CC_HASH_HASH_PAD_AUTO_HWPAD_Enable (0x1UL) /*!< Enable automatic hardware padding. */

/* Register: CC_HASH_HASH_XOR_DIN */
/* Description: Perform an XOR operation of the DIN DMA engine input data being fed into the HASH engine.
        Set this register to '0' if XOR is not required. */

/* Bits 31..0 : The value to XOR with the HASH engine input data. */
#define CC_HASH_HASH_XOR_DIN_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_HASH_HASH_XOR_DIN_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_XOR_DIN_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_HASH_HASH_INIT_STATE */
/* Description: Configure HASH engine initial state registers. */

/* Bit 0 : Enable loading of data to initial state registers. Digest/IV for HASH/AES_MAC. */
#define CC_HASH_HASH_INIT_STATE_LOAD_Pos (0UL) /*!< Position of LOAD field. */
#define CC_HASH_HASH_INIT_STATE_LOAD_Msk (0x1UL << CC_HASH_HASH_INIT_STATE_LOAD_Pos) /*!< Bit mask of LOAD field. */
#define CC_HASH_HASH_INIT_STATE_LOAD_Disable (0x0UL) /*!< Disable loading of data to initial state registers. */
#define CC_HASH_HASH_INIT_STATE_LOAD_Enable (0x1UL) /*!< Enable loading of data to initial state registers. */

/* Register: CC_HASH_HASH_SELECT */
/* Description: Select HASH or GHASH engine as the digest engine to use. */

/* Bits 1..0 : Select HASH or GHASH engine as the digest engine. */
#define CC_HASH_HASH_SELECT_ENGINE_Pos (0UL) /*!< Position of ENGINE field. */
#define CC_HASH_HASH_SELECT_ENGINE_Msk (0x3UL << CC_HASH_HASH_SELECT_ENGINE_Pos) /*!< Bit mask of ENGINE field. */
#define CC_HASH_HASH_SELECT_ENGINE_HASH (0x0UL) /*!< Select the HASH engine */
#define CC_HASH_HASH_SELECT_ENGINE_GHASH (0x2UL) /*!< Select the GHASH engine */

/* Register: CC_HASH_HASH_CONTROL */
/* Description: Control the HASH engine behavior. */

/* Bits 3..0 : Select HASH mode to execute */
#define CC_HASH_HASH_CONTROL_MODE_Pos (0UL) /*!< Position of MODE field. */
#define CC_HASH_HASH_CONTROL_MODE_Msk (0xFUL << CC_HASH_HASH_CONTROL_MODE_Pos) /*!< Bit mask of MODE field. */
#define CC_HASH_HASH_CONTROL_MODE_SHA1 (0x1UL) /*!< Select SHA1 mode */
#define CC_HASH_HASH_CONTROL_MODE_SHA256 (0x2UL) /*!< Select SHA256 mode */
#define CC_HASH_HASH_CONTROL_MODE_SHA224 (0xAUL) /*!< Select SHA224 mode */

/* Register: CC_HASH_HASH_PAD */
/* Description: Enable the hardware padding feature of the HASH engine. */

/* Bit 0 : Configure hardware padding feature. */
#define CC_HASH_HASH_PAD_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_HASH_HASH_PAD_ENABLE_Msk (0x1UL << CC_HASH_HASH_PAD_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_HASH_HASH_PAD_ENABLE_Disable (0x0UL) /*!< Disable hardware padding feature. */
#define CC_HASH_HASH_PAD_ENABLE_Enable (0x1UL) /*!< Enable hardware padding feature. */

/* Register: CC_HASH_HASH_PAD_FORCE */
/* Description: Force the hardware padding operation to trigger if the input data length is zero bytes. */

/* Bit 2 : Trigger hardware padding operation. */
#define CC_HASH_HASH_PAD_FORCE_ENABLE_Pos (2UL) /*!< Position of ENABLE field. */
#define CC_HASH_HASH_PAD_FORCE_ENABLE_Msk (0x1UL << CC_HASH_HASH_PAD_FORCE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_HASH_HASH_PAD_FORCE_ENABLE_Disable (0x0UL) /*!< Do not force hardware padding to trigger. */
#define CC_HASH_HASH_PAD_FORCE_ENABLE_Enable (0x1UL) /*!< Force hardware padding to trigger. */

/* Register: CC_HASH_HASH_CUR_LEN_0 */
/* Description: Bits [31:0] of the number of bytes that have been digested so far. */

/* Bits 31..0 : Bits [31:0] of current length of digested data in bytes. */
#define CC_HASH_HASH_CUR_LEN_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_HASH_HASH_CUR_LEN_0_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_CUR_LEN_0_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_HASH_HASH_CUR_LEN_1 */
/* Description: Bits [63:32] of the number of bytes that have been digested so far. */

/* Bits 31..0 : Bits [63:32] of current length of digested data in bytes. */
#define CC_HASH_HASH_CUR_LEN_1_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_HASH_HASH_CUR_LEN_1_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_CUR_LEN_1_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_HASH_HASH_HW_FLAGS */
/* Description: Hardware configuration of the HASH engine. Reset value holds the supported features. */

/* Bit 18 : If this flag is set, the engine include HASH to DOUT support. */
#define CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Pos (18UL) /*!< Position of DUMP_HASH_TO_DOUT_EXISTS field. */
#define CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Pos) /*!< Bit mask of DUMP_HASH_TO_DOUT_EXISTS field. */

/* Bit 17 : If this flag is set, the engine include compare digest logic. */
#define CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Pos (17UL) /*!< Position of HASH_COMPARE_EXISTS field. */
#define CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Pos) /*!< Bit mask of HASH_COMPARE_EXISTS field. */

/* Bit 16 : If this flag is set, the engine include SHA-256 support. */
#define CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Pos (16UL) /*!< Position of SHA_256_EXISTS field. */
#define CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Pos) /*!< Bit mask of SHA_256_EXISTS field. */

/* Bit 15 : If this flag is set, the engine include HMAC support. */
#define CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Pos (15UL) /*!< Position of HMAC_EXISTS field. */
#define CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Pos) /*!< Bit mask of HMAC_EXISTS field. */

/* Bit 14 : If this flag is set, the engine include MD5 support. */
#define CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Pos (14UL) /*!< Position of MD5_EXISTS field. */
#define CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Pos) /*!< Bit mask of MD5_EXISTS field. */

/* Bit 13 : If this flag is set, the engine include pad block support. */
#define CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Pos (13UL) /*!< Position of PAD_EXISTS field. */
#define CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Pos) /*!< Bit mask of PAD_EXISTS field. */

/* Bit 12 : If this flag is set, the engine include SHA-512 support. */
#define CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Pos (12UL) /*!< Position of SHA_512_EXISTS field. */
#define CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Pos) /*!< Bit mask of SHA_512_EXISTS field. */

/* Bits 11..8 : Determine the granularity of word size. */
#define CC_HASH_HASH_HW_FLAGS_DW_Pos (8UL) /*!< Position of DW field. */
#define CC_HASH_HASH_HW_FLAGS_DW_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_DW_Pos) /*!< Bit mask of DW field. */
#define CC_HASH_HASH_HW_FLAGS_DW_32Bits (0x0UL) /*!< 32 bits word data. */
#define CC_HASH_HASH_HW_FLAGS_DW_64Bits (0x1UL) /*!< 64 bits word data. */

/* Bits 7..4 : Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi. */
#define CC_HASH_HASH_HW_FLAGS_CH_Pos (4UL) /*!< Position of CH field. */
#define CC_HASH_HASH_HW_FLAGS_CH_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_CH_Pos) /*!< Bit mask of CH field. */
#define CC_HASH_HASH_HW_FLAGS_CH_One (0x0UL) /*!< One Hi value is updated at a time. */
#define CC_HASH_HASH_HW_FLAGS_CH_All (0x1UL) /*!< All Hi values are updated at the same time. */

/* Bits 3..0 : Indicates the number of concurrent words the hash is using to compute signature. */
#define CC_HASH_HASH_HW_FLAGS_CW_Pos (0UL) /*!< Position of CW field. */
#define CC_HASH_HASH_HW_FLAGS_CW_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_CW_Pos) /*!< Bit mask of CW field. */
#define CC_HASH_HASH_HW_FLAGS_CW_One (0x1UL) /*!< One concurrent word used by hash during signature generation */
#define CC_HASH_HASH_HW_FLAGS_CW_Two (0x2UL) /*!< Two concurrent words used by hash during signature generation */

/* Register: CC_HASH_HASH_SW_RESET */
/* Description: Reset the HASH engine. */

/* Bit 0 : Writing any value to this address resets the HASH engine. The reset takes 4 CPU clock cycles to complete. */
#define CC_HASH_HASH_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
#define CC_HASH_HASH_SW_RESET_RESET_Msk (0x1UL << CC_HASH_HASH_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
#define CC_HASH_HASH_SW_RESET_RESET_Enable (0x1UL) /*!< Reset HASH engine. */

/* Register: CC_HASH_HASH_ENDIANNESS */
/* Description: Configure the endianness of HASH data and padding generation. */

/* Bit 0 : Endianness of HASH data and padding generation. The default value is little-endian. */
#define CC_HASH_HASH_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */
#define CC_HASH_HASH_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_HASH_HASH_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
#define CC_HASH_HASH_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for data and padding */
#define CC_HASH_HASH_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for data and padding */


/* Peripheral: CC_HOST_RGF */
/* Description: CRYPTOCELL HOST register interface */

/* Register: CC_HOST_RGF_IRR */
/* Description: Interrupt request register. Each bit of this register holds the interrupt
        status of a single interrupt source. If corresponding IMR bit is
        unmasked, an interrupt is generated. */

/* Bit 11 : The symmetric engine DMA completed interrupt status. */
#define CC_HOST_RGF_IRR_SYM_DMA_INT_Pos (11UL) /*!< Position of SYM_DMA_INT field. */
#define CC_HOST_RGF_IRR_SYM_DMA_INT_Msk (0x1UL << CC_HOST_RGF_IRR_SYM_DMA_INT_Pos) /*!< Bit mask of SYM_DMA_INT field. */

/* Bit 10 : The RNG interrupt status. */
#define CC_HOST_RGF_IRR_RNG_INT_Pos (10UL) /*!< Position of RNG_INT field. */
#define CC_HOST_RGF_IRR_RNG_INT_Msk (0x1UL << CC_HOST_RGF_IRR_RNG_INT_Pos) /*!< Bit mask of RNG_INT field. */

/* Bit 9 : The PKA end of operation interrupt status. */
#define CC_HOST_RGF_IRR_PKA_INT_Pos (9UL) /*!< Position of PKA_INT field. */
#define CC_HOST_RGF_IRR_PKA_INT_Msk (0x1UL << CC_HOST_RGF_IRR_PKA_INT_Pos) /*!< Bit mask of PKA_INT field. */

/* Bit 8 : The AHB error interrupt status. */
#define CC_HOST_RGF_IRR_AHB_ERR_INT_Pos (8UL) /*!< Position of AHB_ERR_INT field. */
#define CC_HOST_RGF_IRR_AHB_ERR_INT_Msk (0x1UL << CC_HOST_RGF_IRR_AHB_ERR_INT_Pos) /*!< Bit mask of AHB_ERR_INT field. */

/* Bit 7 : The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to memory. */
#define CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Pos (7UL) /*!< Position of DOUT_TO_MEM_INT field. */
#define CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Msk (0x1UL << CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Pos) /*!< Bit mask of DOUT_TO_MEM_INT field. */

/* Bit 6 : The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from memory to DIN buffer. */
#define CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Pos (6UL) /*!< Position of MEM_TO_DIN_INT field. */
#define CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Msk (0x1UL << CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Pos) /*!< Bit mask of MEM_TO_DIN_INT field. */

/* Bit 5 : The DOUT to RNG SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to RNG SRAM. */
#define CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Pos (5UL) /*!< Position of DOUT_TO_SRAM_INT field. */
#define CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Msk (0x1UL << CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Pos) /*!< Bit mask of DOUT_TO_SRAM_INT field. */

/* Bit 4 : The RNG SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from RNG SRAM to DIN buffer. */
#define CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Pos (4UL) /*!< Position of SRAM_TO_DIN_INT field. */
#define CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Msk (0x1UL << CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Pos) /*!< Bit mask of SRAM_TO_DIN_INT field. */

/* Register: CC_HOST_RGF_IMR */
/* Description: Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. */

/* Bit 11 : The symmetric engine DMA completed interrupt mask. */
#define CC_HOST_RGF_IMR_SYM_DMA_MASK_Pos (11UL) /*!< Position of SYM_DMA_MASK field. */
#define CC_HOST_RGF_IMR_SYM_DMA_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_SYM_DMA_MASK_Pos) /*!< Bit mask of SYM_DMA_MASK field. */
#define CC_HOST_RGF_IMR_SYM_DMA_MASK_IRQEnable (0x0UL) /*!< Do not mask the symmetric engine DMA completed interrupt i.e. interrupt is generated */
#define CC_HOST_RGF_IMR_SYM_DMA_MASK_IRQDisable (0x1UL) /*!< Mask the symmetric engine DMA completed interrupt i.e. no interrupt is generated */

/* Bit 10 : The RNG interrupt mask. */
#define CC_HOST_RGF_IMR_RNG_MASK_Pos (10UL) /*!< Position of RNG_MASK field. */
#define CC_HOST_RGF_IMR_RNG_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_RNG_MASK_Pos) /*!< Bit mask of RNG_MASK field. */
#define CC_HOST_RGF_IMR_RNG_MASK_IRQEnable (0x0UL) /*!< Do not mask RNG interrupt i.e. interrupt is generated */
#define CC_HOST_RGF_IMR_RNG_MASK_IRQDisable (0x1UL) /*!< Mask RNG interrupt i.e. no interrupt is generated */

/* Bit 9 : The PKA end of operation interrupt mask. */
#define CC_HOST_RGF_IMR_PKA_MASK_Pos (9UL) /*!< Position of PKA_MASK field. */
#define CC_HOST_RGF_IMR_PKA_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_PKA_MASK_Pos) /*!< Bit mask of PKA_MASK field. */
#define CC_HOST_RGF_IMR_PKA_MASK_IRQEnable (0x0UL) /*!< Do not mask PKA end of operation interrupt i.e. interrupt is generated */
#define CC_HOST_RGF_IMR_PKA_MASK_IRQDisable (0x1UL) /*!< Mask PKA end of operation interrupt i.e. no interrupt is generated */

/* Bit 8 : The AHB error interrupt mask. */
#define CC_HOST_RGF_IMR_AHB_ERR_MASK_Pos (8UL) /*!< Position of AHB_ERR_MASK field. */
#define CC_HOST_RGF_IMR_AHB_ERR_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_AHB_ERR_MASK_Pos) /*!< Bit mask of AHB_ERR_MASK field. */
#define CC_HOST_RGF_IMR_AHB_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask AHB error interrupt i.e. interrupt is generated */
#define CC_HOST_RGF_IMR_AHB_ERR_MASK_IRQDisable (0x1UL) /*!< Mask AHB error interrupt i.e. no interrupt is generated */

/* Bit 7 : The DOUT to memory DMA done interrupt mask. */
#define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Pos (7UL) /*!< Position of DOUT_TO_MEM_MASK field. */
#define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Pos) /*!< Bit mask of DOUT_TO_MEM_MASK field. */
#define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_IRQEnable (0x0UL) /*!< Do not mask DOUT to memory DMA done interrupt i.e. interrupt is generated */
#define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_IRQDisable (0x1UL) /*!< Mask DOUT to memory DMA done interrupt i.e. no interrupt is generated */

/* Bit 6 : The memory to DIN DMA done interrupt mask. */
#define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Pos (6UL) /*!< Position of MEM_TO_DIN_MASK field. */
#define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Pos) /*!< Bit mask of MEM_TO_DIN_MASK field. */
#define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_IRQEnable (0x0UL) /*!< Do not mask memory to DIN DMA done interrupt i.e. interrupt is generated */
#define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_IRQDisable (0x1UL) /*!< Mask memory to DIN DMA done interrupt i.e. no interrupt is generated */

/* Bit 5 : The DOUT to RNG SRAM DMA done interrupt mask. */
#define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Pos (5UL) /*!< Position of DOUT_TO_SRAM_MASK field. */
#define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Pos) /*!< Bit mask of DOUT_TO_SRAM_MASK field. */
#define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_IRQEnable (0x0UL) /*!< Do not mask DOUT to RNG SRAM DMA done interrupt i.e. interrupt is generated */
#define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_IRQDisable (0x1UL) /*!< Mask DOUT to RNG SRAM DMA done interrupt i.e. no interrupt is generated */

/* Bit 4 : The RNG SRAM to DIN DMA done interrupt mask. */
#define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Pos (4UL) /*!< Position of SRAM_TO_DIN_MASK field. */
#define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Pos) /*!< Bit mask of SRAM_TO_DIN_MASK field. */
#define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_IRQEnable (0x0UL) /*!< Do not mask RNG SRAM to DIN DMA done interrupt i.e. interrupt is generated */
#define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_IRQDisable (0x1UL) /*!< Mask RNG SRAM to DIN DMA done interrupt i.e. no interrupt is generated */

/* Register: CC_HOST_RGF_ICR */
/* Description: Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR. */

/* Bit 11 : The symmetric engine DMA completed interrupt clear. */
#define CC_HOST_RGF_ICR_SYM_DMA_CLEAR_Pos (11UL) /*!< Position of SYM_DMA_CLEAR field. */
#define CC_HOST_RGF_ICR_SYM_DMA_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_SYM_DMA_CLEAR_Pos) /*!< Bit mask of SYM_DMA_CLEAR field. */

/* Bit 10 : The RNG interrupt clear. Register RNG_ISR in the RNG engine must be cleared before this interrupt can be cleared. */
#define CC_HOST_RGF_ICR_RNG_CLEAR_Pos (10UL) /*!< Position of RNG_CLEAR field. */
#define CC_HOST_RGF_ICR_RNG_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_RNG_CLEAR_Pos) /*!< Bit mask of RNG_CLEAR field. */

/* Bit 9 : The PKA end of operation interrupt clear. */
#define CC_HOST_RGF_ICR_PKA_CLEAR_Pos (9UL) /*!< Position of PKA_CLEAR field. */
#define CC_HOST_RGF_ICR_PKA_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_PKA_CLEAR_Pos) /*!< Bit mask of PKA_CLEAR field. */

/* Bit 8 : The AHB error interrupt clear. */
#define CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Pos (8UL) /*!< Position of AHB_ERR_CLEAR field. */
#define CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Pos) /*!< Bit mask of AHB_ERR_CLEAR field. */

/* Bit 7 : The DOUT to memory DMA done interrupt clear. */
#define CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Pos (7UL) /*!< Position of DOUT_TO_MEM_CLEAR field. */
#define CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Pos) /*!< Bit mask of DOUT_TO_MEM_CLEAR field. */

/* Bit 6 : The memory to DIN DMA done interrupt clear. */
#define CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Pos (6UL) /*!< Position of MEM_TO_DIN_CLEAR field. */
#define CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Pos) /*!< Bit mask of MEM_TO_DIN_CLEAR field. */

/* Bit 5 : The DOUT to RNG SRAM DMA done interrupt clear. */
#define CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Pos (5UL) /*!< Position of DOUT_TO_SRAM_CLEAR field. */
#define CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Pos) /*!< Bit mask of DOUT_TO_SRAM_CLEAR field. */

/* Bit 4 : The RNG SRAM to DIN DMA done interrupt clear. */
#define CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Pos (4UL) /*!< Position of SRAM_TO_DIN_CLEAR field. */
#define CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Pos) /*!< Bit mask of SRAM_TO_DIN_CLEAR field. */

/* Register: CC_HOST_RGF_ENDIANNESS */
/* Description: This register defines the endianness of the Host-accessible registers, and can only be written once. */

/* Bit 15 : DIN read word endianness. */
#define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Pos (15UL) /*!< Position of DIN_RD_WBG field. */
#define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Pos) /*!< Bit mask of DIN_RD_WBG field. */
#define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_LittleEndian (0x0UL) /*!< Configure DIN read word as little-endian */
#define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_BigEndian (0x1UL) /*!< Configure DIN read word as big-endian */

/* Bit 11 : DOUT write word endianness. */
#define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Pos (11UL) /*!< Position of DOUT_WR_WBG field. */
#define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Pos) /*!< Bit mask of DOUT_WR_WBG field. */
#define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_LittleEndian (0x0UL) /*!< Configure DOUT write word as little-endian */
#define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_BigEndian (0x1UL) /*!< Configure DOUT write word as big-endian */

/* Bit 7 : DIN read endianness. */
#define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Pos (7UL) /*!< Position of DIN_RD_BG field. */
#define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Pos) /*!< Bit mask of DIN_RD_BG field. */
#define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_LittleEndian (0x0UL) /*!< Configure DIN read as little-endian */
#define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_BigEndian (0x1UL) /*!< Configure DIN read as big-endian */

/* Bit 3 : DOUT write endianness. */
#define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Pos (3UL) /*!< Position of DOUT_WR_BG field. */
#define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Pos) /*!< Bit mask of DOUT_WR_BG field. */
#define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_LittleEndian (0x0UL) /*!< Configure DOUT write as little-endian */
#define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_BigEndian (0x1UL) /*!< Configure DOUT write as big-endian */

/* Register: CC_HOST_RGF_HOST_SIGNATURE */
/* Description: This register holds the CRYPTOCELL subsystem signature. See reset value. */

/* Bits 31..0 : Fixed-value identification signature used by host driver to verify CRYPTOCELL presence at this address. */
#define CC_HOST_RGF_HOST_SIGNATURE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_HOST_RGF_HOST_SIGNATURE_VALUE_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_SIGNATURE_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_HOST_RGF_HOST_BOOT */
/* Description: Hardware configuration of the CRYPTOCELL subsystem. Reset value holds the supported features. */

/* Bit 30 : If this flag is set, the AES engine is present */
#define CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Pos (30UL) /*!< Position of AES_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_EXISTS_LOCAL field. */

/* Bit 29 : If this flag is set, the AES engine only support encryption */
#define CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Pos (29UL) /*!< Position of ONLY_ENCRYPT_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Pos) /*!< Bit mask of ONLY_ENCRYPT_LOCAL field. */

/* Bit 28 : If this flag is set, the AES engine supports 192/256 bits key sizes */
#define CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Pos (28UL) /*!< Position of SUPPORT_256_192_KEY_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Pos) /*!< Bit mask of SUPPORT_256_192_KEY_LOCAL field. */

/* Bit 27 : If this flag is set, the AES engine supports tunneling operations */
#define CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Pos (27UL) /*!< Position of TUNNELING_ENB_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Pos) /*!< Bit mask of TUNNELING_ENB_LOCAL field. */

/* Bit 26 : If this flag is set, the AES engine data input support byte size resolution */
#define CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Pos (26UL) /*!< Position of AES_DIN_BYTE_RESOLUTION_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Pos) /*!< Bit mask of AES_DIN_BYTE_RESOLUTION_LOCAL field. */

/* Bit 25 : If this flag is set, AES CTR mode is supported */
#define CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Pos (25UL) /*!< Position of CTR_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Pos) /*!< Bit mask of CTR_EXISTS_LOCAL field. */

/* Bit 24 : If this flag is set, AES XEX mode is supported */
#define CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Pos (24UL) /*!< Position of AES_XEX_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_XEX_EXISTS_LOCAL field. */

/* Bit 23 : If this flag is set, AES XEX mode T-value calculation in HW is supported */
#define CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Pos (23UL) /*!< Position of AES_XEX_HW_T_CALC_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Pos) /*!< Bit mask of AES_XEX_HW_T_CALC_LOCAL field. */

/* Bit 22 : If this flag is set, AES CCM mode is supported */
#define CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Pos (22UL) /*!< Position of AES_CCM_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_CCM_EXISTS_LOCAL field. */

/* Bit 21 : If this flag is set, AES CMAC mode is supported */
#define CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Pos (21UL) /*!< Position of AES_CMAC_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_CMAC_EXISTS_LOCAL field. */

/* Bit 20 : If this flag is set, AES XCBC-MAC mode is supported */
#define CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Pos (20UL) /*!< Position of AES_XCBC_MAC_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_XCBC_MAC_EXISTS_LOCAL field. */

/* Bit 19 : If this flag is set, the DES engine is present */
#define CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Pos (19UL) /*!< Position of DES_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Pos) /*!< Bit mask of DES_EXISTS_LOCAL field. */

/* Bit 18 : If this flag is set, the C2 engine is present */
#define CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Pos (18UL) /*!< Position of C2_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Pos) /*!< Bit mask of C2_EXISTS_LOCAL field. */

/* Bit 17 : If this flag is set, the HASH engine is present */
#define CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Pos (17UL) /*!< Position of HASH_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Pos) /*!< Bit mask of HASH_EXISTS_LOCAL field. */

/* Bit 16 : If this flag is set, the HASH engine supports MD5 */
#define CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Pos (16UL) /*!< Position of MD5_PRSNT_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Pos) /*!< Bit mask of MD5_PRSNT_LOCAL field. */

/* Bit 15 : If this flag is set, the HASH engine supports SHA256 */
#define CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Pos (15UL) /*!< Position of SHA_256_PRSNT_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Pos) /*!< Bit mask of SHA_256_PRSNT_LOCAL field. */

/* Bit 14 : If this flag is set, the HASH engine supports SHA512 */
#define CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Pos (14UL) /*!< Position of SHA_512_PRSNT_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Pos) /*!< Bit mask of SHA_512_PRSNT_LOCAL field. */

/* Bit 13 : If this flag is set, the RC4 engine is present */
#define CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Pos (13UL) /*!< Position of RC4_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Pos) /*!< Bit mask of RC4_EXISTS_LOCAL field. */

/* Bit 12 : If this flag is set, the PKA engine is present */
#define CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Pos (12UL) /*!< Position of PKA_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Pos) /*!< Bit mask of PKA_EXISTS_LOCAL field. */

/* Bit 11 : If this flag is set, the RNG engine is present */
#define CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Pos (11UL) /*!< Position of RNG_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Pos) /*!< Bit mask of RNG_EXISTS_LOCAL field. */

/* Bit 10 : If this flag is set, PAU is supported */
#define CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Pos (10UL) /*!< Position of PAU_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Pos) /*!< Bit mask of PAU_EXISTS_LOCAL field. */

/* Bit 9 : If this flag is set, Descriptors are supported */
#define CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Pos (9UL) /*!< Position of DSCRPTR_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Pos) /*!< Bit mask of DSCRPTR_EXISTS_LOCAL field. */

/* Bits 8..6 : SRAM size */
#define CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Pos (6UL) /*!< Position of SRAM_SIZE_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Msk (0x7UL << CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Pos) /*!< Bit mask of SRAM_SIZE_LOCAL field. */

/* Bit 5 : If this flag is set, RKEK ECC is supported */
#define CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Pos (5UL) /*!< Position of RKEK_ECC_EXISTS_LOCAL_N field. */
#define CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Pos) /*!< Bit mask of RKEK_ECC_EXISTS_LOCAL_N field. */

/* Bit 3 : If this flag is set, external secure memory is supported */
#define CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Pos (3UL) /*!< Position of EXT_MEM_SECURED_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Pos) /*!< Bit mask of EXT_MEM_SECURED_LOCAL field. */

/* Bit 2 : If this flag is set, HASH in fuses is supported */
#define CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Pos (2UL) /*!< Position of HASH_IN_FUSES_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Pos) /*!< Bit mask of HASH_IN_FUSES_LOCAL field. */

/* Bit 1 : If this flag is set, large RKEK is supported */
#define CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Pos (1UL) /*!< Position of LARGE_RKEK_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Pos) /*!< Bit mask of LARGE_RKEK_LOCAL field. */

/* Bit 0 : If this flag is set, full power gating is implemented */
#define CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Pos (0UL) /*!< Position of POWER_GATING_EXISTS_LOCAL field. */
#define CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Pos) /*!< Bit mask of POWER_GATING_EXISTS_LOCAL field. */

/* Register: CC_HOST_RGF_HOST_CC_IS_IDLE */
/* Description: Idle state register for the CRYPTOCELL subsystem. */

/* Bit 9 : Cryptographic flow idle state. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_CRYPTO_IS_IDLE_Pos (9UL) /*!< Position of CRYPTO_IS_IDLE field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_CRYPTO_IS_IDLE_Msk (0x1UL << CC_HOST_RGF_HOST_CC_IS_IDLE_CRYPTO_IS_IDLE_Pos) /*!< Bit mask of CRYPTO_IS_IDLE field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_CRYPTO_IS_IDLE_Busy (0x0UL) /*!< Cryptographic flow busy. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_CRYPTO_IS_IDLE_Idle (0x1UL) /*!< Cryptographic flow idle. */

/* Bit 8 : PKA engine idle state. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_PKA_IS_IDLE_Pos (8UL) /*!< Position of PKA_IS_IDLE field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_PKA_IS_IDLE_Msk (0x1UL << CC_HOST_RGF_HOST_CC_IS_IDLE_PKA_IS_IDLE_Pos) /*!< Bit mask of PKA_IS_IDLE field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_PKA_IS_IDLE_Busy (0x0UL) /*!< PKA engine busy. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_PKA_IS_IDLE_Idle (0x1UL) /*!< PKA engine idle. */

/* Bit 7 : RNG engine idle state. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_RNG_IS_IDLE_Pos (7UL) /*!< Position of RNG_IS_IDLE field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_RNG_IS_IDLE_Msk (0x1UL << CC_HOST_RGF_HOST_CC_IS_IDLE_RNG_IS_IDLE_Pos) /*!< Bit mask of RNG_IS_IDLE field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_RNG_IS_IDLE_Busy (0x0UL) /*!< RNG engine busy. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_RNG_IS_IDLE_Idle (0x1UL) /*!< RNG engine idle. */

/* Bit 3 : AHB state machine idle state. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_AHB_IS_IDLE_Pos (3UL) /*!< Position of AHB_IS_IDLE field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_AHB_IS_IDLE_Msk (0x1UL << CC_HOST_RGF_HOST_CC_IS_IDLE_AHB_IS_IDLE_Pos) /*!< Bit mask of AHB_IS_IDLE field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_AHB_IS_IDLE_Busy (0x0UL) /*!< AHB state machine busy. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_AHB_IS_IDLE_Idle (0x1UL) /*!< AHB state machine idle. */

/* Bit 2 : Symmetric flow busy state. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_SYM_IS_BUSY_Pos (2UL) /*!< Position of SYM_IS_BUSY field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_SYM_IS_BUSY_Msk (0x1UL << CC_HOST_RGF_HOST_CC_IS_IDLE_SYM_IS_BUSY_Pos) /*!< Bit mask of SYM_IS_BUSY field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_SYM_IS_BUSY_Idle (0x0UL) /*!< Symmetric flow idle. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_SYM_IS_BUSY_Busy (0x1UL) /*!< Symmetric flow busy. */

/* Bit 0 : CRYPTOCELL idle state. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_HOST_CC_IS_IDLE_Pos (0UL) /*!< Position of HOST_CC_IS_IDLE field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_HOST_CC_IS_IDLE_Msk (0x1UL << CC_HOST_RGF_HOST_CC_IS_IDLE_HOST_CC_IS_IDLE_Pos) /*!< Bit mask of HOST_CC_IS_IDLE field. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_HOST_CC_IS_IDLE_Busy (0x0UL) /*!< CRYPTOCELL subsystem busy. */
#define CC_HOST_RGF_HOST_CC_IS_IDLE_HOST_CC_IS_IDLE_Idle (0x1UL) /*!< CRYPTOCELL subsystem idle. */

/* Register: CC_HOST_RGF_HOST_POWERDOWN */
/* Description: This register start the power-down sequence. */

/* Bit 0 : Power down enable register. */
#define CC_HOST_RGF_HOST_POWERDOWN_HOST_POWERDOWN_Pos (0UL) /*!< Position of HOST_POWERDOWN field. */
#define CC_HOST_RGF_HOST_POWERDOWN_HOST_POWERDOWN_Msk (0x1UL << CC_HOST_RGF_HOST_POWERDOWN_HOST_POWERDOWN_Pos) /*!< Bit mask of HOST_POWERDOWN field. */


/* Peripheral: CC_MISC */
/* Description: CRYPTOCELL MISC interface */

/* Register: CC_MISC_AES_CLK */
/* Description: Clock control for the AES engine. */

/* Bit 0 : Enables clock for the AES engine. */
#define CC_MISC_AES_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_MISC_AES_CLK_ENABLE_Msk (0x1UL << CC_MISC_AES_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_MISC_AES_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the AES engine. */
#define CC_MISC_AES_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the AES engine. */

/* Register: CC_MISC_HASH_CLK */
/* Description: Clock control for the HASH engine. */

/* Bit 0 : Enables clock for the HASH engine. */
#define CC_MISC_HASH_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_MISC_HASH_CLK_ENABLE_Msk (0x1UL << CC_MISC_HASH_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_MISC_HASH_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the HASH engine. */
#define CC_MISC_HASH_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the HASH engine. */

/* Register: CC_MISC_PKA_CLK */
/* Description: Clock control for the PKA engine. */

/* Bit 0 : Enables clock for the PKA engine. */
#define CC_MISC_PKA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_MISC_PKA_CLK_ENABLE_Msk (0x1UL << CC_MISC_PKA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_MISC_PKA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the PKA engine. */
#define CC_MISC_PKA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the PKA engine. */

/* Register: CC_MISC_DMA_CLK */
/* Description: Clock control for the DMA engines. */

/* Bit 0 : Enables clock for the DMA engines. */
#define CC_MISC_DMA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_MISC_DMA_CLK_ENABLE_Msk (0x1UL << CC_MISC_DMA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_MISC_DMA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the DMA engines. */
#define CC_MISC_DMA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the DMA engines. */

/* Register: CC_MISC_CLK_STATUS */
/* Description: CRYPTOCELL clocks status register. */

/* Bit 8 : Status of DMA engines clock. */
#define CC_MISC_CLK_STATUS_DMA_CLK_Pos (8UL) /*!< Position of DMA_CLK field. */
#define CC_MISC_CLK_STATUS_DMA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_DMA_CLK_Pos) /*!< Bit mask of DMA_CLK field. */
#define CC_MISC_CLK_STATUS_DMA_CLK_Disabled (0x0UL) /*!< Clocks for DMA engines are disabled */
#define CC_MISC_CLK_STATUS_DMA_CLK_Enabled (0x1UL) /*!< Clocks for DMA engines are enabled */

/* Bit 7 : Status of CHACHA engine clock. */
#define CC_MISC_CLK_STATUS_CHACHA_CLK_Pos (7UL) /*!< Position of CHACHA_CLK field. */
#define CC_MISC_CLK_STATUS_CHACHA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_CHACHA_CLK_Pos) /*!< Bit mask of CHACHA_CLK field. */
#define CC_MISC_CLK_STATUS_CHACHA_CLK_Disabled (0x0UL) /*!< Clock for CHACHA engine is disabled */
#define CC_MISC_CLK_STATUS_CHACHA_CLK_Enabled (0x1UL) /*!< Clock for CHACHA engine is enabled */

/* Bit 3 : Status of PKA engine clock. */
#define CC_MISC_CLK_STATUS_PKA_CLK_Pos (3UL) /*!< Position of PKA_CLK field. */
#define CC_MISC_CLK_STATUS_PKA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_PKA_CLK_Pos) /*!< Bit mask of PKA_CLK field. */
#define CC_MISC_CLK_STATUS_PKA_CLK_Disabled (0x0UL) /*!< Clock for PKA engine is disabled */
#define CC_MISC_CLK_STATUS_PKA_CLK_Enabled (0x1UL) /*!< Clock for PKA engine is enabled */

/* Bit 2 : Status of HASH engine clock. */
#define CC_MISC_CLK_STATUS_HASH_CLK_Pos (2UL) /*!< Position of HASH_CLK field. */
#define CC_MISC_CLK_STATUS_HASH_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_HASH_CLK_Pos) /*!< Bit mask of HASH_CLK field. */
#define CC_MISC_CLK_STATUS_HASH_CLK_Disabled (0x0UL) /*!< Clock for HASH engine is disabled */
#define CC_MISC_CLK_STATUS_HASH_CLK_Enabled (0x1UL) /*!< Clock for HASH engine is enabled */

/* Bit 0 : Status of AES engine clock. */
#define CC_MISC_CLK_STATUS_AES_CLK_Pos (0UL) /*!< Position of AES_CLK field. */
#define CC_MISC_CLK_STATUS_AES_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_AES_CLK_Pos) /*!< Bit mask of AES_CLK field. */
#define CC_MISC_CLK_STATUS_AES_CLK_Disabled (0x0UL) /*!< Clock for AES engine is disabled */
#define CC_MISC_CLK_STATUS_AES_CLK_Enabled (0x1UL) /*!< Clock for AES engine is enabled */

/* Register: CC_MISC_CHACHA_CLK */
/* Description: Clock control for the CHACHA engine. */

/* Bit 0 : Enables clock for the CHACHA engine. */
#define CC_MISC_CHACHA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_MISC_CHACHA_CLK_ENABLE_Msk (0x1UL << CC_MISC_CHACHA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_MISC_CHACHA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the CHACHA engine. */
#define CC_MISC_CHACHA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the CHACHA engine. */


/* Peripheral: CC_PKA */
/* Description: CRYPTOCELL PKA engine */

/* Register: CC_PKA_MEMORY_MAP */
/* Description: Description collection: Register for mapping the virtual register R[n] to a physical address in the PKA SRAM. */

/* Bits 10..1 : The physical word address used for the virtual register. */
#define CC_PKA_MEMORY_MAP_ADDR_Pos (1UL) /*!< Position of ADDR field. */
#define CC_PKA_MEMORY_MAP_ADDR_Msk (0x3FFUL << CC_PKA_MEMORY_MAP_ADDR_Pos) /*!< Bit mask of ADDR field. */

/* Register: CC_PKA_OPCODE */
/* Description: Operation code to be executed by the PKA engine. Writing to this register triggers the PKA operation. */

/* Bits 31..27 : Operation code to be executed by the PKA engine */
#define CC_PKA_OPCODE_OPCODE_Pos (27UL) /*!< Position of OPCODE field. */
#define CC_PKA_OPCODE_OPCODE_Msk (0x1FUL << CC_PKA_OPCODE_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
#define CC_PKA_OPCODE_OPCODE_Terminate (0x00UL) /*!< Terminate operation */
#define CC_PKA_OPCODE_OPCODE_AddInc (0x04UL) /*!< Add or Increment */
#define CC_PKA_OPCODE_OPCODE_SubDecNeg (0x05UL) /*!< Subtract, Decrement, or Negate */
#define CC_PKA_OPCODE_OPCODE_ModAddInc (0x06UL) /*!< Modular Add or Modular Increment */
#define CC_PKA_OPCODE_OPCODE_ModSubDecNeg (0x07UL) /*!< Modular Subtract, Modular Decrement, or Modular Negate */
#define CC_PKA_OPCODE_OPCODE_ANDTST0CLR0 (0x08UL) /*!< Perform AND, test, or clear */
#define CC_PKA_OPCODE_OPCODE_ORCOPYSET0 (0x09UL) /*!< Perform OR, copy, or set bits */
#define CC_PKA_OPCODE_OPCODE_XORFLP0INVCMP (0x0AUL) /*!< Perform XOR, flip bits, invert, or compare */
#define CC_PKA_OPCODE_OPCODE_SHR0 (0x0CUL) /*!< Shift right 0 operation */
#define CC_PKA_OPCODE_OPCODE_SHR1 (0x0DUL) /*!< Shift right 1 operation */
#define CC_PKA_OPCODE_OPCODE_SHL0 (0x0EUL) /*!< Shift left 0 operation */
#define CC_PKA_OPCODE_OPCODE_SHL1 (0x0FUL) /*!< Shift left 1 operation */
#define CC_PKA_OPCODE_OPCODE_MulLow (0x10UL) /*!< Multiply low operation */
#define CC_PKA_OPCODE_OPCODE_ModMul (0x11UL) /*!< Modular multiply operation */
#define CC_PKA_OPCODE_OPCODE_ModMulN (0x12UL) /*!< Modular multiply N operation */
#define CC_PKA_OPCODE_OPCODE_ModExp (0x13UL) /*!< Modular exponentiation operation */
#define CC_PKA_OPCODE_OPCODE_Division (0x14UL) /*!< Division operation */
#define CC_PKA_OPCODE_OPCODE_ModInv (0x15UL) /*!< Modular inversion operation */
#define CC_PKA_OPCODE_OPCODE_ModDiv (0x16UL) /*!< Modular division operation */
#define CC_PKA_OPCODE_OPCODE_MulHigh (0x17UL) /*!< Multiply high operation */
#define CC_PKA_OPCODE_OPCODE_ModMLAC (0x18UL) /*!< Modular multiplication acceleration */
#define CC_PKA_OPCODE_OPCODE_ModMLACNR (0x19UL) /*!< Modular multiplication acceleration where final reduction is omitted */
#define CC_PKA_OPCODE_OPCODE_Reduction (0x1BUL) /*!< Reduction operation */

/* Bits 26..24 : The length of the operands. This value serves as an PKA length register index. E.g.: if LEN field value is set to 0, PKA_L[0] holds the size of the operands. */
#define CC_PKA_OPCODE_LEN_Pos (24UL) /*!< Position of LEN field. */
#define CC_PKA_OPCODE_LEN_Msk (0x7UL << CC_PKA_OPCODE_LEN_Pos) /*!< Bit mask of LEN field. */

/* Bit 23 : This field controls the interpretation of REG_A. */
#define CC_PKA_OPCODE_CONST_A_Pos (23UL) /*!< Position of CONST_A field. */
#define CC_PKA_OPCODE_CONST_A_Msk (0x1UL << CC_PKA_OPCODE_CONST_A_Pos) /*!< Bit mask of CONST_A field. */
#define CC_PKA_OPCODE_CONST_A_Register (0x0UL) /*!< REG_A is intepreted as a register index. */
#define CC_PKA_OPCODE_CONST_A_Constant (0x1UL) /*!< REG_A is intepreted as a constant. */

/* Bits 22..18 : Operand A virtual register index. */
#define CC_PKA_OPCODE_REG_A_Pos (18UL) /*!< Position of REG_A field. */
#define CC_PKA_OPCODE_REG_A_Msk (0x1FUL << CC_PKA_OPCODE_REG_A_Pos) /*!< Bit mask of REG_A field. */

/* Bit 17 : This field controls the interpretation of REG_B. */
#define CC_PKA_OPCODE_CONST_B_Pos (17UL) /*!< Position of CONST_B field. */
#define CC_PKA_OPCODE_CONST_B_Msk (0x1UL << CC_PKA_OPCODE_CONST_B_Pos) /*!< Bit mask of CONST_B field. */
#define CC_PKA_OPCODE_CONST_B_Register (0x0UL) /*!< REG_B is intepreted as a register index. */
#define CC_PKA_OPCODE_CONST_B_Constant (0x1UL) /*!< REG_B is intepreted as a constant. */

/* Bits 16..12 : Operand B virtual register index. */
#define CC_PKA_OPCODE_REG_B_Pos (12UL) /*!< Position of REG_B field. */
#define CC_PKA_OPCODE_REG_B_Msk (0x1FUL << CC_PKA_OPCODE_REG_B_Pos) /*!< Bit mask of REG_B field. */

/* Bit 11 : This field controls the interpretation of REG_R. */
#define CC_PKA_OPCODE_DISCARD_R_Pos (11UL) /*!< Position of DISCARD_R field. */
#define CC_PKA_OPCODE_DISCARD_R_Msk (0x1UL << CC_PKA_OPCODE_DISCARD_R_Pos) /*!< Bit mask of DISCARD_R field. */
#define CC_PKA_OPCODE_DISCARD_R_Register (0x0UL) /*!< REG_R is intepreted as a register index. */
#define CC_PKA_OPCODE_DISCARD_R_Discard (0x1UL) /*!< Result is discarded. */

/* Bits 10..6 : Result register virtual register index. */
#define CC_PKA_OPCODE_REG_R_Pos (6UL) /*!< Position of REG_R field. */
#define CC_PKA_OPCODE_REG_R_Msk (0x1FUL << CC_PKA_OPCODE_REG_R_Pos) /*!< Bit mask of REG_R field. */

/* Bits 5..0 : Holds the operation tag or the operand C virtual register index. */
#define CC_PKA_OPCODE_TAG_Pos (0UL) /*!< Position of TAG field. */
#define CC_PKA_OPCODE_TAG_Msk (0x3FUL << CC_PKA_OPCODE_TAG_Pos) /*!< Bit mask of TAG field. */

/* Register: CC_PKA_N_NP_T0_T1_ADDR */
/* Description: This register defines the N, Np, T0, and T1 virtual register index. */

/* Bits 19..15 : Temporary register 1 virtual register index. Default is R31. */
#define CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Pos (15UL) /*!< Position of T1_VIRTUAL_ADDR field. */
#define CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Pos) /*!< Bit mask of T1_VIRTUAL_ADDR field. */

/* Bits 14..10 : Temporary register 0 virtual register index. Default is R30. */
#define CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Pos (10UL) /*!< Position of T0_VIRTUAL_ADDR field. */
#define CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Pos) /*!< Bit mask of T0_VIRTUAL_ADDR field. */

/* Bits 9..5 : Register Np virtual register index. Default is R1. */
#define CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Pos (5UL) /*!< Position of NP_VIRTUAL_ADDR field. */
#define CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Pos) /*!< Bit mask of NP_VIRTUAL_ADDR field. */

/* Bits 4..0 : Register N virtual register index. Default is R0. */
#define CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Pos (0UL) /*!< Position of N_VIRTUAL_ADDR field. */
#define CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Pos) /*!< Bit mask of N_VIRTUAL_ADDR field. */

/* Register: CC_PKA_PKA_STATUS */
/* Description: This register holds the status for the PKA pipeline. */

/* Bits 20..16 : Opcode of the last operation */
#define CC_PKA_PKA_STATUS_OPCODE_Pos (16UL) /*!< Position of OPCODE field. */
#define CC_PKA_PKA_STATUS_OPCODE_Msk (0x1FUL << CC_PKA_PKA_STATUS_OPCODE_Pos) /*!< Bit mask of OPCODE field. */

/* Bit 15 : Indicates the modular inverse of zero. */
#define CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Pos (15UL) /*!< Position of MODINV_OF_ZERO field. */
#define CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Pos) /*!< Bit mask of MODINV_OF_ZERO field. */

/* Bit 14 : Indication if the division is done by zero. */
#define CC_PKA_PKA_STATUS_DIV_BY_ZERO_Pos (14UL) /*!< Position of DIV_BY_ZERO field. */
#define CC_PKA_PKA_STATUS_DIV_BY_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_DIV_BY_ZERO_Pos) /*!< Bit mask of DIV_BY_ZERO field. */

/* Bit 13 : Modular overflow flag. */
#define CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Pos (13UL) /*!< Position of ALU_MODOVRFLW field. */
#define CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Pos) /*!< Bit mask of ALU_MODOVRFLW field. */

/* Bit 12 : Indicates if the result of ALU OUT is zero. */
#define CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Pos (12UL) /*!< Position of ALU_OUT_ZERO field. */
#define CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Pos) /*!< Bit mask of ALU_OUT_ZERO field. */

/* Bit 11 : Indicates the last subtraction operation sign. */
#define CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Pos (11UL) /*!< Position of ALU_SUB_IS_ZERO field. */
#define CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Pos) /*!< Bit mask of ALU_SUB_IS_ZERO field. */

/* Bit 10 : Holds the carry of the last modular operation. */
#define CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Pos (10UL) /*!< Position of ALU_CARRY_MOD field. */
#define CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Pos) /*!< Bit mask of ALU_CARRY_MOD field. */

/* Bit 9 : Holds the carry of the last ALU operation. */
#define CC_PKA_PKA_STATUS_ALU_CARRY_Pos (9UL) /*!< Position of ALU_CARRY field. */
#define CC_PKA_PKA_STATUS_ALU_CARRY_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_CARRY_Pos) /*!< Bit mask of ALU_CARRY field. */

/* Bit 8 : Indicates the MSB sign of the last operation. */
#define CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Pos (8UL) /*!< Position of ALU_SIGN_OUT field. */
#define CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Pos) /*!< Bit mask of ALU_SIGN_OUT field. */

/* Bits 7..4 : The least significant 4-bits of the operand updated in shift operation. */
#define CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Pos (4UL) /*!< Position of ALU_LSB_4BITS field. */
#define CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Msk (0xFUL << CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Pos) /*!< Bit mask of ALU_LSB_4BITS field. */

/* Bits 3..0 : The most significant 4-bits of the operand updated in shift operation. */
#define CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Pos (0UL) /*!< Position of ALU_MSB_4BITS field. */
#define CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Msk (0xFUL << CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Pos) /*!< Bit mask of ALU_MSB_4BITS field. */

/* Register: CC_PKA_PKA_SW_RESET */
/* Description: Reset the PKA engine. */

/* Bit 0 : Writing any value to this address resets the PKA engine. The reset takes 4 CPU clock cycles to complete. */
#define CC_PKA_PKA_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
#define CC_PKA_PKA_SW_RESET_RESET_Msk (0x1UL << CC_PKA_PKA_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
#define CC_PKA_PKA_SW_RESET_RESET_Enable (0x1UL) /*!< Reset PKA engine. */

/* Register: CC_PKA_PKA_L */
/* Description: Description collection: This register holds the operands bit size. */

/* Bits 12..0 : Operand bit size. */
#define CC_PKA_PKA_L_OpSize_Pos (0UL) /*!< Position of OpSize field. */
#define CC_PKA_PKA_L_OpSize_Msk (0x1FFFUL << CC_PKA_PKA_L_OpSize_Pos) /*!< Bit mask of OpSize field. */

/* Register: CC_PKA_PKA_PIPE */
/* Description: Status register indicating if the PKA pipeline is ready to receive a new OPCODE. */

/* Bit 0 : PKA pipeline status. */
#define CC_PKA_PKA_PIPE_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_PKA_PKA_PIPE_STATUS_Msk (0x1UL << CC_PKA_PKA_PIPE_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_PKA_PKA_PIPE_STATUS_NotReady (0x0UL) /*!< PKA pipeline is not ready for a new OPCODE */
#define CC_PKA_PKA_PIPE_STATUS_Ready (0x1UL) /*!< PKA pipeline is ready for a new OPCODE */

/* Register: CC_PKA_PKA_DONE */
/* Description: Status register indicating if the PKA operation has been completed. */

/* Bit 0 : PKA operation status. */
#define CC_PKA_PKA_DONE_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_PKA_PKA_DONE_STATUS_Msk (0x1UL << CC_PKA_PKA_DONE_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_PKA_PKA_DONE_STATUS_Processing (0x0UL) /*!< PKA operation is processing */
#define CC_PKA_PKA_DONE_STATUS_Completed (0x1UL) /*!< PKA operation is completed and pipeline is empty */

/* Register: CC_PKA_PKA_VERSION */
/* Description: PKA engine HW version. Reset value holds the version. */

/* Bits 31..0 :   */
#define CC_PKA_PKA_VERSION_PKA_VERSION_Pos (0UL) /*!< Position of PKA_VERSION field. */
#define CC_PKA_PKA_VERSION_PKA_VERSION_Msk (0xFFFFFFFFUL << CC_PKA_PKA_VERSION_PKA_VERSION_Pos) /*!< Bit mask of PKA_VERSION field. */

/* Register: CC_PKA_PKA_SRAM_WADDR */
/* Description: Start address in PKA SRAM for subsequent write transactions. */

/* Bits 31..0 : PKA SRAM start address for write transaction */
#define CC_PKA_PKA_SRAM_WADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
#define CC_PKA_PKA_SRAM_WADDR_ADDR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */

/* Register: CC_PKA_PKA_SRAM_WDATA */
/* Description: Write data to PKA SRAM. Writing to this register triggers a DMA transaction writing data into PKA SRAM. The DMA address offset is automatically incremented during write. */

/* Bits 31..0 : Data to write to PKA SRAM. */
#define CC_PKA_PKA_SRAM_WDATA_DATA_Pos (0UL) /*!< Position of DATA field. */
#define CC_PKA_PKA_SRAM_WDATA_DATA_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WDATA_DATA_Pos) /*!< Bit mask of DATA field. */

/* Register: CC_PKA_PKA_SRAM_RDATA */
/* Description: Read data from PKA SRAM. Reading from this register triggers a DMA transaction read data from PKA SRAM. The DMA address offset is automatically incremented during read. */

/* Bits 31..0 : Data to read from PKA SRAM */
#define CC_PKA_PKA_SRAM_RDATA_DATA_Pos (0UL) /*!< Position of DATA field. */
#define CC_PKA_PKA_SRAM_RDATA_DATA_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_RDATA_DATA_Pos) /*!< Bit mask of DATA field. */

/* Register: CC_PKA_PKA_SRAM_WCLEAR */
/* Description: Register for clearing PKA SRAM write buffer. */

/* Bits 31..0 : Clear the PKA SRAM write buffer. */
#define CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */
#define CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Pos) /*!< Bit mask of CLEAR field. */

/* Register: CC_PKA_PKA_SRAM_RADDR */
/* Description: Start address in PKA SRAM for subsequent read transactions. */

/* Bits 31..0 : PKA SRAM start address for read transaction */
#define CC_PKA_PKA_SRAM_RADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
#define CC_PKA_PKA_SRAM_RADDR_ADDR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_RADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */


/* Peripheral: CC_RNG */
/* Description: CRYPTOCELL RNG engine */

/* Register: CC_RNG_RNG_IMR */
/* Description: Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. */

/* Bit 5 : See RNG_ISR for explanation on this interrupt. */
#define CC_RNG_RNG_IMR_DMA_DONE_MASK_Pos (5UL) /*!< Position of DMA_DONE_MASK field. */
#define CC_RNG_RNG_IMR_DMA_DONE_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_DMA_DONE_MASK_Pos) /*!< Bit mask of DMA_DONE_MASK field. */
#define CC_RNG_RNG_IMR_DMA_DONE_MASK_IRQEnable (0x0UL) /*!< Do not mask the RNG DMA completion interrupt i.e. interrupt is generated */
#define CC_RNG_RNG_IMR_DMA_DONE_MASK_IRQDisable (0x1UL) /*!< Mask the RNG DMA completion interrupt i.e. no interrupt is generated */

/* Bit 4 : See RNG_ISR for explanation on this interrupt. */
#define CC_RNG_RNG_IMR_WATCHDOG_MASK_Pos (4UL) /*!< Position of WATCHDOG_MASK field. */
#define CC_RNG_RNG_IMR_WATCHDOG_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_WATCHDOG_MASK_Pos) /*!< Bit mask of WATCHDOG_MASK field. */
#define CC_RNG_RNG_IMR_WATCHDOG_MASK_IRQEnable (0x0UL) /*!< Do not mask the watchdog interrupt i.e. interrupt is generated */
#define CC_RNG_RNG_IMR_WATCHDOG_MASK_IRQDisable (0x1UL) /*!< Mask the watchdog interrupt i.e. no interrupt is generated */

/* Bit 3 : See RNG_ISR for explanation on this interrupt. */
#define CC_RNG_RNG_IMR_VNC_ERR_MASK_Pos (3UL) /*!< Position of VNC_ERR_MASK field. */
#define CC_RNG_RNG_IMR_VNC_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_VNC_ERR_MASK_Pos) /*!< Bit mask of VNC_ERR_MASK field. */
#define CC_RNG_RNG_IMR_VNC_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask the von Neumann corrector error interrupt i.e. interrupt is generated */
#define CC_RNG_RNG_IMR_VNC_ERR_MASK_IRQDisable (0x1UL) /*!< Mask the von Neumann corrector error interrupt i.e. no interrupt is generated */

/* Bit 2 : See RNG_ISR for explanation on this interrupt. */
#define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Pos (2UL) /*!< Position of CRNGT_ERR_MASK field. */
#define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Pos) /*!< Bit mask of CRNGT_ERR_MASK field. */
#define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask the CRNGT error interrupt i.e. interrupt is generated */
#define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_IRQDisable (0x1UL) /*!< Mask the CRNGT error interrupt i.e. no interrupt is generated */

/* Bit 1 : See RNG_ISR for explanation on this interrupt. */
#define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Pos (1UL) /*!< Position of AUTOCORR_ERR_MASK field. */
#define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Pos) /*!< Bit mask of AUTOCORR_ERR_MASK field. */
#define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask autocorrelation interrupt i.e. interrupt is generated */
#define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_IRQDisable (0x1UL) /*!< Mask autocorrelation interrupt i.e. no interrupt is generated */

/* Bit 0 : See RNG_ISR for explanation on this interrupt. */
#define CC_RNG_RNG_IMR_EHR_VALID_MASK_Pos (0UL) /*!< Position of EHR_VALID_MASK field. */
#define CC_RNG_RNG_IMR_EHR_VALID_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_EHR_VALID_MASK_Pos) /*!< Bit mask of EHR_VALID_MASK field. */
#define CC_RNG_RNG_IMR_EHR_VALID_MASK_IRQEnable (0x0UL) /*!< Do not mask EHR interrupt i.e. interrupt is generated */
#define CC_RNG_RNG_IMR_EHR_VALID_MASK_IRQDisable (0x1UL) /*!< Mask EHR interrupt i.e. no interrupt is generated */

/* Register: CC_RNG_RNG_ISR */
/* Description: Interrupt status register. Each bit of this register holds the interrupt
        status of a single interrupt source. If corresponding RNG_IMR bit is
        unmasked, an interrupt is generated. */

/* Bit 5 : RNG DMA to SRAM is completed. */
#define CC_RNG_RNG_ISR_DMA_DONE_INT_Pos (5UL) /*!< Position of DMA_DONE_INT field. */
#define CC_RNG_RNG_ISR_DMA_DONE_INT_Msk (0x1UL << CC_RNG_RNG_ISR_DMA_DONE_INT_Pos) /*!< Bit mask of DMA_DONE_INT field. */

/* Bit 4 : Maximum number of CPU clock cycles per sample have been exceeded. See RNG_WATCHDOG_VAL for more information. */
#define CC_RNG_RNG_ISR_WATCHDOG_INT_Pos (4UL) /*!< Position of WATCHDOG_INT field. */
#define CC_RNG_RNG_ISR_WATCHDOG_INT_Msk (0x1UL << CC_RNG_RNG_ISR_WATCHDOG_INT_Pos) /*!< Bit mask of WATCHDOG_INT field. */

/* Bit 3 : von Neumann corrector error. Failure occurs if 32 consecutive collected bits are identical, ZERO, or ONE. */
#define CC_RNG_RNG_ISR_VNC_ERR_INT_Pos (3UL) /*!< Position of VNC_ERR_INT field. */
#define CC_RNG_RNG_ISR_VNC_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_VNC_ERR_INT_Pos) /*!< Bit mask of VNC_ERR_INT field. */

/* Bit 2 : Continuous random number generator test error. Failure occurs when two consecutive blocks of 16 collected bits are equal. */
#define CC_RNG_RNG_ISR_CRNGT_ERR_INT_Pos (2UL) /*!< Position of CRNGT_ERR_INT field. */
#define CC_RNG_RNG_ISR_CRNGT_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_CRNGT_ERR_INT_Pos) /*!< Bit mask of CRNGT_ERR_INT field. */

/* Bit 1 : Autocorrelation error. Failure occurs when autocorrelation test has failed four times in a row. Once set, the TRNG ceases to function until next reset. */
#define CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Pos (1UL) /*!< Position of AUTOCORR_ERR_INT field. */
#define CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Pos) /*!< Bit mask of AUTOCORR_ERR_INT field. */

/* Bit 0 : 192-bits have been collected and are ready to be read. */
#define CC_RNG_RNG_ISR_EHR_VALID_INT_Pos (0UL) /*!< Position of EHR_VALID_INT field. */
#define CC_RNG_RNG_ISR_EHR_VALID_INT_Msk (0x1UL << CC_RNG_RNG_ISR_EHR_VALID_INT_Pos) /*!< Bit mask of EHR_VALID_INT field. */

/* Register: CC_RNG_RNG_ICR */
/* Description: Interrupt clear register. Writing a 1 bit into a field in this register
        will clear the corresponding bit in RNG_ISR. */

/* Bit 5 : Writing value '1' clears corresponding bit in RNG_ISR */
#define CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Pos (5UL) /*!< Position of DMA_DONE_CLEAR field. */
#define CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Pos) /*!< Bit mask of DMA_DONE_CLEAR field. */

/* Bit 4 : Writing value '1' clears corresponding bit in RNG_ISR */
#define CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Pos (4UL) /*!< Position of WATCHDOG_CLEAR field. */
#define CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Pos) /*!< Bit mask of WATCHDOG_CLEAR field. */

/* Bit 3 : Writing value '1' clears corresponding bit in RNG_ISR */
#define CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Pos (3UL) /*!< Position of VNC_ERR_CLEAR field. */
#define CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Pos) /*!< Bit mask of VNC_ERR_CLEAR field. */

/* Bit 2 : Writing value '1' clears corresponding bit in RNG_ISR */
#define CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Pos (2UL) /*!< Position of CRNGT_ERR_CLEAR field. */
#define CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Pos) /*!< Bit mask of CRNGT_ERR_CLEAR field. */

/* Bit 1 : Cannot be cleared by software! Only RNG reset clears this bit. */
#define CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Pos (1UL) /*!< Position of AUTOCORR_ERR_CLEAR field. */
#define CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Pos) /*!< Bit mask of AUTOCORR_ERR_CLEAR field. */

/* Bit 0 : Writing value '1' clears corresponding bit in RNG_ISR */
#define CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Pos (0UL) /*!< Position of EHR_VALID_CLEAR field. */
#define CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Pos) /*!< Bit mask of EHR_VALID_CLEAR field. */

/* Register: CC_RNG_TRNG_CONFIG */
/* Description: TRNG ring oscillator length configuration */

/* Bits 1..0 : Set the length of the oscillator ring (= the number of inverters) out of four possible configurations. */
#define CC_RNG_TRNG_CONFIG_ROSC_LEN_Pos (0UL) /*!< Position of ROSC_LEN field. */
#define CC_RNG_TRNG_CONFIG_ROSC_LEN_Msk (0x3UL << CC_RNG_TRNG_CONFIG_ROSC_LEN_Pos) /*!< Bit mask of ROSC_LEN field. */
#define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC1 (0x0UL) /*!< Use shortest ROSC1 ring oscillator configuration. */
#define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC2 (0x1UL) /*!< Use ROSC2 ring oscillator configuration. */
#define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC3 (0x2UL) /*!< Use ROSC3 ring oscillator configuration. */
#define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC4 (0x3UL) /*!< Use longest ROSC4 ring oscillator configuration. */

/* Register: CC_RNG_TRNG_VALID */
/* Description: This register indicates if TRNG entropy collection is valid. */

/* Bit 0 : A value of 1 indicates that collection of bits in the TRNG is completed, and data can be read from EHR_DATA registers. */
#define CC_RNG_TRNG_VALID_EHR_DATA_Pos (0UL) /*!< Position of EHR_DATA field. */
#define CC_RNG_TRNG_VALID_EHR_DATA_Msk (0x1UL << CC_RNG_TRNG_VALID_EHR_DATA_Pos) /*!< Bit mask of EHR_DATA field. */
#define CC_RNG_TRNG_VALID_EHR_DATA_NotValid (0x0UL) /*!< Collection of bits not valid. */
#define CC_RNG_TRNG_VALID_EHR_DATA_Valid (0x1UL) /*!< Collection of bits valid. */

/* Register: CC_RNG_EHR_DATA */
/* Description: Description collection: The entropy holding registers (EHR) hold 192-bits random data collected by the TRNG. The initial EHR_DATA[0] register holds the least significant bits [31:0] of the random data value. */

/* Bits 31..0 : Random data value. */
#define CC_RNG_EHR_DATA_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_RNG_EHR_DATA_VALUE_Msk (0xFFFFFFFFUL << CC_RNG_EHR_DATA_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_RNG_NOISE_SOURCE */
/* Description: This register controls the ring oscillator circuit used as a noise source. */

/* Bit 0 : Enable or disable the noise source. */
#define CC_RNG_NOISE_SOURCE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_RNG_NOISE_SOURCE_ENABLE_Msk (0x1UL << CC_RNG_NOISE_SOURCE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_RNG_NOISE_SOURCE_ENABLE_Disabled (0x0UL) /*!< Noise source is disabled */
#define CC_RNG_NOISE_SOURCE_ENABLE_Enabled (0x1UL) /*!< Noise source is enabled */

/* Register: CC_RNG_SAMPLE_CNT */
/* Description: Sample count defining the number of CPU clock cycles between two consecutive noise source samples. */

/* Bits 31..0 : Number of CPU clock cycles between two consecutive noise source samples. */
#define CC_RNG_SAMPLE_CNT_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define CC_RNG_SAMPLE_CNT_VALUE_Msk (0xFFFFFFFFUL << CC_RNG_SAMPLE_CNT_VALUE_Pos) /*!< Bit mask of VALUE field. */

/* Register: CC_RNG_AUTOCORR_STATISTIC */
/* Description: Statistics counter for autocorrelation test activations. Statistics collection is stopped if one of the counters reach its limit of all ones. */

/* Bits 21..14 : Count each time an autocorrelation test fails. Any write to the field resets the counter. */
#define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Pos (14UL) /*!< Position of AUTOCORR_FAILS field. */
#define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Msk (0xFFUL << CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Pos) /*!< Bit mask of AUTOCORR_FAILS field. */

/* Bits 13..0 : Count each time an autocorrelation test starts. Any write to the field resets the counter. */
#define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Pos (0UL) /*!< Position of AUTOCORR_TRYS field. */
#define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Msk (0x3FFFUL << CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Pos) /*!< Bit mask of AUTOCORR_TRYS field. */

/* Register: CC_RNG_TRNG_DEBUG */
/* Description: Debug register for the TRNG. This register is used to bypass TRNG tests in hardware. */

/* Bit 3 : Bypass the autocorrelation test. */
#define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Pos (3UL) /*!< Position of AUTOCORR_BYPASS field. */
#define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Pos) /*!< Bit mask of AUTOCORR_BYPASS field. */
#define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Disabled (0x0UL) /*!< Autocorrelation test is active */
#define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Enabled (0x1UL) /*!< Bypass the autocorrelation test */

/* Bit 2 : Bypass the Continuous Random Number Generator Test (CRNGT). */
#define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Pos (2UL) /*!< Position of CRNGT_BYPASS field. */
#define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Pos) /*!< Bit mask of CRNGT_BYPASS field. */
#define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Disabled (0x0UL) /*!< CRNGT is active */
#define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Enabled (0x1UL) /*!< Bypass CRNGT */

/* Bit 1 : Bypass the von Neumann corrector post-processing test, including the 32 consecutive bits test. */
#define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Pos (1UL) /*!< Position of VNC_BYPASS field. */
#define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_VNC_BYPASS_Pos) /*!< Bit mask of VNC_BYPASS field. */
#define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Disabled (0x0UL) /*!< von Neumann corrector post-processing is active */
#define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Enabled (0x1UL) /*!< Bypass the von Neumann corrector */

/* Register: CC_RNG_RNG_SW_RESET */
/* Description: Reset the RNG engine. */

/* Bit 0 : Writing any value to this address resets the RNG engine. The reset takes 4 CPU clock cycles to complete. */
#define CC_RNG_RNG_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
#define CC_RNG_RNG_SW_RESET_RESET_Msk (0x1UL << CC_RNG_RNG_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
#define CC_RNG_RNG_SW_RESET_RESET_Enable (0x1UL) /*!< Reset RNG engine. */

/* Register: CC_RNG_RNG_BUSY */
/* Description: Status register for RNG engine activity. */

/* Bit 1 : TRNG status. */
#define CC_RNG_RNG_BUSY_TRNG_STATUS_Pos (1UL) /*!< Position of TRNG_STATUS field. */
#define CC_RNG_RNG_BUSY_TRNG_STATUS_Msk (0x1UL << CC_RNG_RNG_BUSY_TRNG_STATUS_Pos) /*!< Bit mask of TRNG_STATUS field. */
#define CC_RNG_RNG_BUSY_TRNG_STATUS_Idle (0x0UL) /*!< TRNG is idle */
#define CC_RNG_RNG_BUSY_TRNG_STATUS_Busy (0x1UL) /*!< TRNG is busy */

/* Bit 0 : RNG engine status. */
#define CC_RNG_RNG_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_RNG_RNG_BUSY_STATUS_Msk (0x1UL << CC_RNG_RNG_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_RNG_RNG_BUSY_STATUS_Idle (0x0UL) /*!< RNG engine is idle */
#define CC_RNG_RNG_BUSY_STATUS_Busy (0x1UL) /*!< RNG engine is busy */

/* Register: CC_RNG_TRNG_RESET */
/* Description: Reset the TRNG, including internal counter of collected bits and registers EHR_DATA and TRNG_VALID. */

/* Bit 0 : Writing any value to this address resets the internal bits counter and registers EHR_DATA and TRNG_VALID. Register NOISE_SOURCE must be disabled in order for the reset to take place. */
#define CC_RNG_TRNG_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
#define CC_RNG_TRNG_RESET_RESET_Msk (0x1UL << CC_RNG_TRNG_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
#define CC_RNG_TRNG_RESET_RESET_Enable (0x1UL) /*!< Reset TRNG. */

/* Register: CC_RNG_RNG_HW_FLAGS */
/* Description: Hardware configuration of RNG engine. Reset value holds the supported features. */

/* Bit 7 :   */
#define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Pos (7UL) /*!< Position of RNG_USE_5_SBOXES field. */
#define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Pos) /*!< Bit mask of RNG_USE_5_SBOXES field. */
#define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Disable (0x0UL) /*!< 20 SBOX AES */
#define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Enable (0x1UL) /*!< 5 SBOX AES */

/* Bit 6 : If this flag is set, the engine include support for automatic reseeding. */
#define CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Pos (6UL) /*!< Position of RESEEDING_EXISTS field. */
#define CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Pos) /*!< Bit mask of RESEEDING_EXISTS field. */

/* Bit 5 : If this flag is set, the engine include support for known answer tests. */
#define CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Pos (5UL) /*!< Position of KAT_EXISTS field. */
#define CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Pos) /*!< Bit mask of KAT_EXISTS field. */

/* Bit 4 : If this flag is set, the engine include a pseudo-random number generator. */
#define CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Pos (4UL) /*!< Position of PRNG_EXISTS field. */
#define CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Pos) /*!< Bit mask of PRNG_EXISTS field. */

/* Bit 3 : If this flag is set, the engine include support for bypassing TRNG tests. */
#define CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Pos (3UL) /*!< Position of BYPASS_EXISTS field. */
#define CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Pos) /*!< Bit mask of BYPASS_EXISTS field. */

/* Bit 2 : If this flag is set, the engine include support for autocorrelation test. */
#define CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Pos (2UL) /*!< Position of AUTOCORR_EXISTS field. */
#define CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Pos) /*!< Bit mask of AUTOCORR_EXISTS field. */

/* Bit 1 : If this flag is set, the engine include support for continuous random number generator test. */
#define CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Pos (1UL) /*!< Position of CRNGT_EXISTS field. */
#define CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Pos) /*!< Bit mask of CRNGT_EXISTS field. */

/* Bit 0 : Data width supported by the entropy collector */
#define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Pos (0UL) /*!< Position of EHR_WIDTH field. */
#define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Pos) /*!< Bit mask of EHR_WIDTH field. */
#define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_128Bits (0x0UL) /*!< 128 bits EHR width */
#define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_192Bits (0x1UL) /*!< 192 bits EHR width */

/* Register: CC_RNG_RNG_CLK */
/* Description: Control clock for the RNG engine. */

/* Bit 0 : Enables clock for the RNG engine. */
#define CC_RNG_RNG_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_RNG_RNG_CLK_ENABLE_Msk (0x1UL << CC_RNG_RNG_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_RNG_RNG_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for RNG engine. */
#define CC_RNG_RNG_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for RNG engine. */

/* Register: CC_RNG_RNG_DMA */
/* Description: Writing to this register enables the RNG DMA engine. */

/* Bit 0 :   */
#define CC_RNG_RNG_DMA_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CC_RNG_RNG_DMA_ENABLE_Msk (0x1UL << CC_RNG_RNG_DMA_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CC_RNG_RNG_DMA_ENABLE_Disable (0x0UL) /*!< Disable RNG DMA engine */
#define CC_RNG_RNG_DMA_ENABLE_Enable (0x1UL) /*!< Enable RNG DMA engine This value is cleared when the RNG DMA engine completes its operation. */

/* Register: CC_RNG_RNG_DMA_ROSC_LEN */
/* Description: This register defines which ring oscillator length configuration should be used when using the RNG DMA engine. */

/* Bit 3 : Use longest ROSC4 ring oscillator configuration. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Pos (3UL) /*!< Position of ROSC4 field. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Disable (0x0UL) /*!< Disable ROSC4 */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Enable (0x1UL) /*!< Enable ROSC4 */

/* Bit 2 : Use ROSC3 ring oscillator configuration. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Pos (2UL) /*!< Position of ROSC3 field. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Disable (0x0UL) /*!< Disable ROSC3 */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Enable (0x1UL) /*!< Enable ROSC3 */

/* Bit 1 : Use ROSC2 ring oscillator configuration. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Pos (1UL) /*!< Position of ROSC2 field. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Disable (0x0UL) /*!< Disable ROSC2 */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Enable (0x1UL) /*!< Enable ROSC2 */

/* Bit 0 : Use shortest ROSC1 ring oscillator configuration. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Disable (0x0UL) /*!< Disable ROSC1 */
#define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Enable (0x1UL) /*!< Enable ROSC1 */

/* Register: CC_RNG_RNG_DMA_SRAM_ADDR */
/* Description: This register defines the start address in TRNG SRAM for the TRNG data to be collected by the RNG DMA engine. */

/* Bits 10..0 : Start address of the TRNG data in TRNG SRAM. */
#define CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Pos (0UL) /*!< Position of RNG_SRAM_DMA_ADDR field. */
#define CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Msk (0x7FFUL << CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Pos) /*!< Bit mask of RNG_SRAM_DMA_ADDR field. */

/* Register: CC_RNG_RNG_DMA_SAMPLES_NUM */
/* Description: This register defines the number of 192-bits samples that the RNG DMA engine collects per run. */

/* Bits 7..0 : Defines the number of 192-bits samples that the DMA engine collects per run. */
#define CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Pos (0UL) /*!< Position of RNG_SAMPLES_NUM field. */
#define CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Msk (0xFFUL << CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Pos) /*!< Bit mask of RNG_SAMPLES_NUM field. */

/* Register: CC_RNG_RNG_WATCHDOG_VAL */
/* Description: This register defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. */

/* Bits 31..0 : Defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. */
#define CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Pos (0UL) /*!< Position of RNG_WATCHDOG_VAL field. */
#define CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Msk (0xFFFFFFFFUL << CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Pos) /*!< Bit mask of RNG_WATCHDOG_VAL field. */

/* Register: CC_RNG_RNG_DMA_BUSY */
/* Description: Status register for RNG DMA engine activity. */

/* Bits 10..3 : Number of samples already collected using the current ring oscillator configuration. */
#define CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Pos (3UL) /*!< Position of NUM_OF_SAMPLES field. */
#define CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Msk (0xFFUL << CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Pos) /*!< Bit mask of NUM_OF_SAMPLES field. */

/* Bits 2..1 : The active ring oscillator length configuration used by the RNG DMA engine. */
#define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Pos (1UL) /*!< Position of ROSC_LEN field. */
#define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Msk (0x3UL << CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Pos) /*!< Bit mask of ROSC_LEN field. */
#define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC1 (0x0UL) /*!< Shortest ROSC1 ring oscillator configuration used. */
#define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC2 (0x1UL) /*!< ROSC2 ring oscillator configuration used. */
#define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC3 (0x2UL) /*!< ROSC3 ring oscillator configuration used. */
#define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC4 (0x3UL) /*!< Longest ROSC4 ring oscillator configuration used. */

/* Bit 0 : RNG DMA engine status. */
#define CC_RNG_RNG_DMA_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CC_RNG_RNG_DMA_BUSY_STATUS_Msk (0x1UL << CC_RNG_RNG_DMA_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CC_RNG_RNG_DMA_BUSY_STATUS_Idle (0x0UL) /*!< RNG DMA engine is idle */
#define CC_RNG_RNG_DMA_BUSY_STATUS_Busy (0x1UL) /*!< RNG DMA engine is busy */


/* Peripheral: CC_RNG_SRAM */
/* Description: CRYPTOCELL RNG SRAM interface */

/* Register: CC_RNG_SRAM_SRAM_DATA */
/* Description: Read/Write data from RNG SRAM */

/* Bits 31..0 : 32 bits DMA read/write from/to RNG SRAM. A 'read' or 'write' operation to this register will trigger the DMA address to be automatically incremented. */
#define CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Pos (0UL) /*!< Position of SRAM_DATA field. */
#define CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Msk (0xFFFFFFFFUL << CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Pos) /*!< Bit mask of SRAM_DATA field. */

/* Register: CC_RNG_SRAM_SRAM_ADDR */
/* Description: First address given to RNG SRAM DMA for read/write transactions from/to RNG SRAM. */

/* Bits 14..0 : RNG SRAM starting address */
#define CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Pos (0UL) /*!< Position of SRAM_ADDR field. */
#define CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Msk (0x7FFFUL << CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Pos) /*!< Bit mask of SRAM_ADDR field. */

/* Register: CC_RNG_SRAM_SRAM_DATA_READY */
/* Description: RNG SRAM DMA engine is ready to read/write from/to RNG SRAM. */

/* Bit 0 : RNG SRAM DMA status. */
#define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Pos (0UL) /*!< Position of SRAM_READY field. */
#define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Msk (0x1UL << CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Pos) /*!< Bit mask of SRAM_READY field. */
#define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Busy (0x0UL) /*!< DMA is busy */
#define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Idle (0x1UL) /*!< DMA is idle */


/* Peripheral: CLOCK */
/* Description: Clock management 0 */

/* Register: CLOCK_TASKS_HFCLKSTART */
/* Description: Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */

/* Bit 0 : Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */
#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (0x1UL) /*!< Trigger task */

/* Register: CLOCK_TASKS_HFCLKSTOP */
/* Description: Stop HFCLK128M/HFCLK64M source */

/* Bit 0 : Stop HFCLK128M/HFCLK64M source */
#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: CLOCK_TASKS_LFCLKSTART */
/* Description: Start LFCLK source as selected in LFCLKSRC */

/* Bit 0 : Start LFCLK source as selected in LFCLKSRC */
#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (0x1UL) /*!< Trigger task */

/* Register: CLOCK_TASKS_LFCLKSTOP */
/* Description: Stop LFCLK source */

/* Bit 0 : Stop LFCLK source */
#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: CLOCK_TASKS_CAL */
/* Description: Start calibration of LFRC oscillator */

/* Bit 0 : Start calibration of LFRC oscillator */
#define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
#define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (0x1UL) /*!< Trigger task */

/* Register: CLOCK_TASKS_HFCLKAUDIOSTART */
/* Description: Start HFCLKAUDIO source */

/* Bit 0 : Start HFCLKAUDIO source */
#define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTART field. */
#define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTART field. */
#define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Trigger (0x1UL) /*!< Trigger task */

/* Register: CLOCK_TASKS_HFCLKAUDIOSTOP */
/* Description: Stop HFCLKAUDIO source */

/* Bit 0 : Stop HFCLKAUDIO source */
#define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTOP field. */
#define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTOP field. */
#define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: CLOCK_TASKS_HFCLK192MSTART */
/* Description: Start HFCLK192M source as selected in HFCLK192MSRC */

/* Bit 0 : Start HFCLK192M source as selected in HFCLK192MSRC */
#define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTART field. */
#define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos) /*!< Bit mask of TASKS_HFCLK192MSTART field. */
#define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Trigger (0x1UL) /*!< Trigger task */

/* Register: CLOCK_TASKS_HFCLK192MSTOP */
/* Description: Stop HFCLK192M source */

/* Bit 0 : Stop HFCLK192M source */
#define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTOP field. */
#define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos) /*!< Bit mask of TASKS_HFCLK192MSTOP field. */
#define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: CLOCK_SUBSCRIBE_HFCLKSTART */
/* Description: Subscribe configuration for task HFCLKSTART */

/* Bit 31 :   */
#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0x0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */
#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */
/* Description: Subscribe configuration for task HFCLKSTOP */

/* Bit 31 :   */
#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */
#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_SUBSCRIBE_LFCLKSTART */
/* Description: Subscribe configuration for task LFCLKSTART */

/* Bit 31 :   */
#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0x0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */
#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */
/* Description: Subscribe configuration for task LFCLKSTOP */

/* Bit 31 :   */
#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */
#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_SUBSCRIBE_CAL */
/* Description: Subscribe configuration for task CAL */

/* Bit 31 :   */
#define CLOCK_SUBSCRIBE_CAL_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_SUBSCRIBE_CAL_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_CAL_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0x0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_CAL_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task CAL will subscribe to */
#define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTART */
/* Description: Subscribe configuration for task HFCLKAUDIOSTART */

/* Bit 31 :   */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Disabled (0x0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task HFCLKAUDIOSTART will subscribe to */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP */
/* Description: Subscribe configuration for task HFCLKAUDIOSTOP */

/* Bit 31 :   */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task HFCLKAUDIOSTOP will subscribe to */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_SUBSCRIBE_HFCLK192MSTART */
/* Description: Subscribe configuration for task HFCLK192MSTART */

/* Bit 31 :   */
#define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Disabled (0x0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task HFCLK192MSTART will subscribe to */
#define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_SUBSCRIBE_HFCLK192MSTOP */
/* Description: Subscribe configuration for task HFCLK192MSTOP */

/* Bit 31 :   */
#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task HFCLK192MSTOP will subscribe to */
#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_EVENTS_HFCLKSTARTED */
/* Description: HFCLK128M/HFCLK64M source started */

/* Bit 0 : HFCLK128M/HFCLK64M source started */
#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: CLOCK_EVENTS_LFCLKSTARTED */
/* Description: LFCLK source started */

/* Bit 0 : LFCLK source started */
#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: CLOCK_EVENTS_DONE */
/* Description: Calibration of LFRC oscillator complete event */

/* Bit 0 : Calibration of LFRC oscillator complete event */
#define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
#define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */
#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */

/* Register: CLOCK_EVENTS_HFCLKAUDIOSTARTED */
/* Description: HFCLKAUDIO source started */

/* Bit 0 : HFCLKAUDIO source started */
#define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKAUDIOSTARTED field. */
#define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKAUDIOSTARTED field. */
#define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: CLOCK_EVENTS_HFCLK192MSTARTED */
/* Description: HFCLK192M source started */

/* Bit 0 : HFCLK192M source started */
#define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLK192MSTARTED field. */
#define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLK192MSTARTED field. */
#define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: CLOCK_PUBLISH_HFCLKSTARTED */
/* Description: Publish configuration for event HFCLKSTARTED */

/* Bit 31 :   */
#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to */
#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_PUBLISH_LFCLKSTARTED */
/* Description: Publish configuration for event LFCLKSTARTED */

/* Bit 31 :   */
#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to */
#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_PUBLISH_DONE */
/* Description: Publish configuration for event DONE */

/* Bit 31 :   */
#define CLOCK_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_PUBLISH_DONE_EN_Msk (0x1UL << CLOCK_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_PUBLISH_DONE_EN_Disabled (0x0UL) /*!< Disable publishing */
#define CLOCK_PUBLISH_DONE_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event DONE will publish to */
#define CLOCK_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_PUBLISH_DONE_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_PUBLISH_HFCLKAUDIOSTARTED */
/* Description: Publish configuration for event HFCLKAUDIOSTARTED */

/* Bit 31 :   */
#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event HFCLKAUDIOSTARTED will publish to */
#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_PUBLISH_HFCLK192MSTARTED */
/* Description: Publish configuration for event HFCLK192MSTARTED */

/* Bit 31 :   */
#define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event HFCLK192MSTARTED will publish to */
#define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: CLOCK_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 9 : Enable or disable interrupt for event HFCLK192MSTARTED */
#define CLOCK_INTEN_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
#define CLOCK_INTEN_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
#define CLOCK_INTEN_HFCLK192MSTARTED_Disabled (0x0UL) /*!< Disable */
#define CLOCK_INTEN_HFCLK192MSTARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 8 : Enable or disable interrupt for event HFCLKAUDIOSTARTED */
#define CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
#define CLOCK_INTEN_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
#define CLOCK_INTEN_HFCLKAUDIOSTARTED_Disabled (0x0UL) /*!< Disable */
#define CLOCK_INTEN_HFCLKAUDIOSTARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 7 : Enable or disable interrupt for event DONE */
#define CLOCK_INTEN_DONE_Pos (7UL) /*!< Position of DONE field. */
#define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTEN_DONE_Disabled (0x0UL) /*!< Disable */
#define CLOCK_INTEN_DONE_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
#define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTEN_LFCLKSTARTED_Disabled (0x0UL) /*!< Disable */
#define CLOCK_INTEN_LFCLKSTARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */
#define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTEN_HFCLKSTARTED_Disabled (0x0UL) /*!< Disable */
#define CLOCK_INTEN_HFCLKSTARTED_Enabled (0x1UL) /*!< Enable */

/* Register: CLOCK_INTENSET */
/* Description: Enable interrupt */

/* Bit 9 : Write '1' to enable interrupt for event HFCLK192MSTARTED */
#define CLOCK_INTENSET_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
#define CLOCK_INTENSET_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
#define CLOCK_INTENSET_HFCLK192MSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_HFCLK192MSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_HFCLK192MSTARTED_Set (0x1UL) /*!< Enable */

/* Bit 8 : Write '1' to enable interrupt for event HFCLKAUDIOSTARTED */
#define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
#define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
#define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Set (0x1UL) /*!< Enable */

/* Bit 7 : Write '1' to enable interrupt for event DONE */
#define CLOCK_INTENSET_DONE_Pos (7UL) /*!< Position of DONE field. */
#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_DONE_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_LFCLKSTARTED_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_HFCLKSTARTED_Set (0x1UL) /*!< Enable */

/* Register: CLOCK_INTENCLR */
/* Description: Disable interrupt */

/* Bit 9 : Write '1' to disable interrupt for event HFCLK192MSTARTED */
#define CLOCK_INTENCLR_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
#define CLOCK_INTENCLR_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
#define CLOCK_INTENCLR_HFCLK192MSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_HFCLK192MSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_HFCLK192MSTARTED_Clear (0x1UL) /*!< Disable */

/* Bit 8 : Write '1' to disable interrupt for event HFCLKAUDIOSTARTED */
#define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
#define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
#define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Clear (0x1UL) /*!< Disable */

/* Bit 7 : Write '1' to disable interrupt for event DONE */
#define CLOCK_INTENCLR_DONE_Pos (7UL) /*!< Position of DONE field. */
#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (0x1UL) /*!< Disable */

/* Register: CLOCK_INTPEND */
/* Description: Pending interrupts */

/* Bit 9 : Read pending status of interrupt for event HFCLK192MSTARTED */
#define CLOCK_INTPEND_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
#define CLOCK_INTPEND_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
#define CLOCK_INTPEND_HFCLK192MSTARTED_NotPending (0x0UL) /*!< Read: Not pending */
#define CLOCK_INTPEND_HFCLK192MSTARTED_Pending (0x1UL) /*!< Read: Pending */

/* Bit 8 : Read pending status of interrupt for event HFCLKAUDIOSTARTED */
#define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
#define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
#define CLOCK_INTPEND_HFCLKAUDIOSTARTED_NotPending (0x0UL) /*!< Read: Not pending */
#define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pending (0x1UL) /*!< Read: Pending */

/* Bit 7 : Read pending status of interrupt for event DONE */
#define CLOCK_INTPEND_DONE_Pos (7UL) /*!< Position of DONE field. */
#define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos) /*!< Bit mask of DONE field. */
#define CLOCK_INTPEND_DONE_NotPending (0x0UL) /*!< Read: Not pending */
#define CLOCK_INTPEND_DONE_Pending (0x1UL) /*!< Read: Pending */

/* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */
#define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
#define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
#define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0x0UL) /*!< Read: Not pending */
#define CLOCK_INTPEND_LFCLKSTARTED_Pending (0x1UL) /*!< Read: Pending */

/* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */
#define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
#define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
#define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0x0UL) /*!< Read: Not pending */
#define CLOCK_INTPEND_HFCLKSTARTED_Pending (0x1UL) /*!< Read: Pending */

/* Register: CLOCK_HFCLKRUN */
/* Description: Status indicating that HFCLKSTART task has been triggered */

/* Bit 0 : HFCLKSTART task triggered or not */
#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */
#define CLOCK_HFCLKRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */

/* Register: CLOCK_HFCLKSTAT */
/* Description: Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */

/* Bit 16 : HFCLK state */
#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
#define CLOCK_HFCLKSTAT_STATE_NotRunning (0x0UL) /*!< HFCLK not running */
#define CLOCK_HFCLKSTAT_STATE_Running (0x1UL) /*!< HFCLK running */

/* Bit 4 : ALWAYSRUN activated */
#define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
#define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
#define CLOCK_HFCLKSTAT_ALWAYSRUNNING_NotRunning (0x0UL) /*!< Automatic clock control enabled */
#define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Running (0x1UL) /*!< Oscillator is always running */

/* Bit 0 : Active clock source */
#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_HFCLKSTAT_SRC_HFINT (0x0UL) /*!< Clock source: HFINT - 128 MHz on-chip oscillator */
#define CLOCK_HFCLKSTAT_SRC_HFXO (0x1UL) /*!< Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator */

/* Register: CLOCK_LFCLKRUN */
/* Description: Status indicating that LFCLKSTART task has been triggered */

/* Bit 0 : LFCLKSTART task triggered or not */
#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */
#define CLOCK_LFCLKRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */

/* Register: CLOCK_LFCLKSTAT */
/* Description: Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */

/* Bit 16 : LFCLK state */
#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
#define CLOCK_LFCLKSTAT_STATE_NotRunning (0x0UL) /*!< LFCLK not running */
#define CLOCK_LFCLKSTAT_STATE_Running (0x1UL) /*!< LFCLK running */

/* Bit 4 : ALWAYSRUN activated */
#define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
#define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
#define CLOCK_LFCLKSTAT_ALWAYSRUNNING_NotRunning (0x0UL) /*!< Automatic clock control enabled */
#define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Running (0x1UL) /*!< Oscillator is always running */

/* Bits 1..0 : Active clock source */
#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSTAT_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */
#define CLOCK_LFCLKSTAT_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */
#define CLOCK_LFCLKSTAT_SRC_LFSYNT (0x3UL) /*!< 32.768 kHz synthesized from HFCLK */

/* Register: CLOCK_LFCLKSRCCOPY */
/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */

/* Bits 1..0 : Clock source */
#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSRCCOPY_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */
#define CLOCK_LFCLKSRCCOPY_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */
#define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (0x3UL) /*!< 32.768 kHz synthesized from HFCLK */

/* Register: CLOCK_HFCLKAUDIORUN */
/* Description: Status indicating that HFCLKAUDIOSTART task has been triggered */

/* Bit 0 : HFCLKAUDIOSTART task triggered or not */
#define CLOCK_HFCLKAUDIORUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CLOCK_HFCLKAUDIORUN_STATUS_Msk (0x1UL << CLOCK_HFCLKAUDIORUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CLOCK_HFCLKAUDIORUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */
#define CLOCK_HFCLKAUDIORUN_STATUS_Triggered (0x1UL) /*!< Task triggered */

/* Register: CLOCK_HFCLKAUDIOSTAT */
/* Description: Status indicating which HFCLKAUDIO source is running */

/* Bit 16 : HFCLKAUDIO state */
#define CLOCK_HFCLKAUDIOSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
#define CLOCK_HFCLKAUDIOSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
#define CLOCK_HFCLKAUDIOSTAT_STATE_NotRunning (0x0UL) /*!< HFCLKAUDIO not running */
#define CLOCK_HFCLKAUDIOSTAT_STATE_Running (0x1UL) /*!< HFCLKAUDIO running */

/* Bit 4 : ALWAYSRUN activated */
#define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
#define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
#define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_NotRunning (0x0UL) /*!< Automatic clock control enabled */
#define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Running (0x1UL) /*!< Oscillator is always running */

/* Register: CLOCK_HFCLK192MRUN */
/* Description: Status indicating that HFCLK192MSTART task has been triggered */

/* Bit 0 : HFCLK192MSTART task triggered or not */
#define CLOCK_HFCLK192MRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define CLOCK_HFCLK192MRUN_STATUS_Msk (0x1UL << CLOCK_HFCLK192MRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define CLOCK_HFCLK192MRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */
#define CLOCK_HFCLK192MRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */

/* Register: CLOCK_HFCLK192MSTAT */
/* Description: Status indicating which HFCLK192M source is running */

/* Bit 16 : HFCLK192M state */
#define CLOCK_HFCLK192MSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
#define CLOCK_HFCLK192MSTAT_STATE_Msk (0x1UL << CLOCK_HFCLK192MSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
#define CLOCK_HFCLK192MSTAT_STATE_NotRunning (0x0UL) /*!< HFCLK192M not running */
#define CLOCK_HFCLK192MSTAT_STATE_Running (0x1UL) /*!< HFCLK192M running */

/* Bit 4 : ALWAYSRUN activated */
#define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
#define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
#define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_NotRunning (0x0UL) /*!< Automatic clock control enabled */
#define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Running (0x1UL) /*!< Oscillator is always running */

/* Bit 0 : Active clock source */
#define CLOCK_HFCLK192MSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_HFCLK192MSTAT_SRC_Msk (0x1UL << CLOCK_HFCLK192MSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_HFCLK192MSTAT_SRC_HFINT (0x0UL) /*!< Clock source: HFINT - on-chip oscillator */
#define CLOCK_HFCLK192MSTAT_SRC_HFXO (0x1UL) /*!< Clock source: HFXO - derived from external 32 MHz crystal oscillator */

/* Register: CLOCK_HFCLKSRC */
/* Description: Clock source for HFCLK128M/HFCLK64M */

/* Bit 0 : Select which HFCLK source is started by the HFCLKSTART task */
#define CLOCK_HFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_HFCLKSRC_SRC_Msk (0x1UL << CLOCK_HFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_HFCLKSRC_SRC_HFINT (0x0UL) /*!< HFCLKSTART task starts HFINT oscillator */
#define CLOCK_HFCLKSRC_SRC_HFXO (0x1UL) /*!< HFCLKSTART task starts HFXO oscillator */

/* Register: CLOCK_LFCLKSRC */
/* Description: Clock source for LFCLK */

/* Bits 1..0 : Select which LFCLK source is started by the LFCLKSTART task */
#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_LFCLKSRC_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */
#define CLOCK_LFCLKSRC_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */
#define CLOCK_LFCLKSRC_SRC_LFSYNT (0x3UL) /*!< 32.768 kHz synthesized from HFCLK */

/* Register: CLOCK_HFCLKCTRL */
/* Description: HFCLK128M frequency configuration */

/* Bits 1..0 : High frequency clock HCLK */
#define CLOCK_HFCLKCTRL_HCLK_Pos (0UL) /*!< Position of HCLK field. */
#define CLOCK_HFCLKCTRL_HCLK_Msk (0x3UL << CLOCK_HFCLKCTRL_HCLK_Pos) /*!< Bit mask of HCLK field. */
#define CLOCK_HFCLKCTRL_HCLK_Div1 (0x0UL) /*!< Divide HFCLK by 1 */
#define CLOCK_HFCLKCTRL_HCLK_Div2 (0x1UL) /*!< Divide HFCLK by 2 */

/* Register: CLOCK_HFCLKAUDIO_FREQUENCY */
/* Description: Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands */

/* Bits 15..0 : Frequency 0: 10.666 MHz 65535: 13.333 MHz */
#define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Msk (0xFFFFUL << CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */

/* Register: CLOCK_HFCLKALWAYSRUN */
/* Description: Automatic or manual control of HFCLK128M/HFCLK64M */

/* Bit 0 : Ensure clock is always running */
#define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
#define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
#define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Automatic (0x0UL) /*!< Use automatic clock control */
#define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (0x1UL) /*!< Ensure clock is always running */

/* Register: CLOCK_LFCLKALWAYSRUN */
/* Description: Automatic or manual control of LFCLK */

/* Bit 0 : Ensure clock is always running */
#define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
#define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
#define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Automatic (0x0UL) /*!< Use automatic clock control */
#define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (0x1UL) /*!< Ensure clock is always running */

/* Register: CLOCK_HFCLKAUDIOALWAYSRUN */
/* Description: Automatic or manual control of HFCLKAUDIO */

/* Bit 0 : Ensure clock is always running */
#define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
#define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
#define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Automatic (0x0UL) /*!< Use automatic clock control */
#define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_AlwaysRun (0x1UL) /*!< Ensure clock is always running */

/* Register: CLOCK_HFCLK192MSRC */
/* Description: Clock source for HFCLK192M */

/* Bit 0 : Select which HFCLK192M source is started by the HFCLK192MSTART task */
#define CLOCK_HFCLK192MSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
#define CLOCK_HFCLK192MSRC_SRC_Msk (0x1UL << CLOCK_HFCLK192MSRC_SRC_Pos) /*!< Bit mask of SRC field. */
#define CLOCK_HFCLK192MSRC_SRC_HFINT (0x0UL) /*!< HFCLK192MSTART task starts HFINT oscillator */
#define CLOCK_HFCLK192MSRC_SRC_HFXO (0x1UL) /*!< HFCLK192MSTART task starts HFXO oscillator */

/* Register: CLOCK_HFCLK192MALWAYSRUN */
/* Description: Automatic or manual control of HFCLK192M */

/* Bit 0 : Ensure clock is always running */
#define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
#define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
#define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Automatic (0x0UL) /*!< Use automatic clock control */
#define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_AlwaysRun (0x1UL) /*!< Ensure clock is always running */

/* Register: CLOCK_HFCLK192MCTRL */
/* Description: HFCLK192M frequency configuration */

/* Bits 1..0 : High frequency clock HCLK192M */
#define CLOCK_HFCLK192MCTRL_HCLK192M_Pos (0UL) /*!< Position of HCLK192M field. */
#define CLOCK_HFCLK192MCTRL_HCLK192M_Msk (0x3UL << CLOCK_HFCLK192MCTRL_HCLK192M_Pos) /*!< Bit mask of HCLK192M field. */
#define CLOCK_HFCLK192MCTRL_HCLK192M_Div1 (0x0UL) /*!< Divide HFCLK192M by 1 */
#define CLOCK_HFCLK192MCTRL_HCLK192M_Div2 (0x1UL) /*!< Divide HFCLK192M by 2 */
#define CLOCK_HFCLK192MCTRL_HCLK192M_Div4 (0x2UL) /*!< Divide HFCLK192M by 4 */


/* Peripheral: COMP */
/* Description: Comparator 0 */

/* Register: COMP_TASKS_START */
/* Description: Start comparator */

/* Bit 0 : Start comparator */
#define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define COMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */

/* Register: COMP_TASKS_STOP */
/* Description: Stop comparator */

/* Bit 0 : Stop comparator */
#define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define COMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: COMP_TASKS_SAMPLE */
/* Description: Sample comparator value */

/* Bit 0 : Sample comparator value */
#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */

/* Register: COMP_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */

/* Bit 31 :   */
#define COMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define COMP_SUBSCRIBE_START_EN_Msk (0x1UL << COMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define COMP_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
#define COMP_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define COMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define COMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: COMP_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define COMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define COMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << COMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define COMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define COMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define COMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define COMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: COMP_SUBSCRIBE_SAMPLE */
/* Description: Subscribe configuration for task SAMPLE */

/* Bit 31 :   */
#define COMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */
#define COMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << COMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */
#define COMP_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define COMP_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */
#define COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define COMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: COMP_EVENTS_READY */
/* Description: COMP is ready and output is valid */

/* Bit 0 : COMP is ready and output is valid */
#define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
#define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */
#define COMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */

/* Register: COMP_EVENTS_DOWN */
/* Description: Downward crossing */

/* Bit 0 : Downward crossing */
#define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
#define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated */
#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated */

/* Register: COMP_EVENTS_UP */
/* Description: Upward crossing */

/* Bit 0 : Upward crossing */
#define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
#define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated */
#define COMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated */

/* Register: COMP_EVENTS_CROSS */
/* Description: Downward or upward crossing */

/* Bit 0 : Downward or upward crossing */
#define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
#define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated */
#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated */

/* Register: COMP_PUBLISH_READY */
/* Description: Publish configuration for event READY */

/* Bit 31 :   */
#define COMP_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */
#define COMP_PUBLISH_READY_EN_Msk (0x1UL << COMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */
#define COMP_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */
#define COMP_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event READY will publish to */
#define COMP_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define COMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << COMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: COMP_PUBLISH_DOWN */
/* Description: Publish configuration for event DOWN */

/* Bit 31 :   */
#define COMP_PUBLISH_DOWN_EN_Pos (31UL) /*!< Position of EN field. */
#define COMP_PUBLISH_DOWN_EN_Msk (0x1UL << COMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field. */
#define COMP_PUBLISH_DOWN_EN_Disabled (0x0UL) /*!< Disable publishing */
#define COMP_PUBLISH_DOWN_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event DOWN will publish to */
#define COMP_PUBLISH_DOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define COMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << COMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: COMP_PUBLISH_UP */
/* Description: Publish configuration for event UP */

/* Bit 31 :   */
#define COMP_PUBLISH_UP_EN_Pos (31UL) /*!< Position of EN field. */
#define COMP_PUBLISH_UP_EN_Msk (0x1UL << COMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field. */
#define COMP_PUBLISH_UP_EN_Disabled (0x0UL) /*!< Disable publishing */
#define COMP_PUBLISH_UP_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event UP will publish to */
#define COMP_PUBLISH_UP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define COMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << COMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: COMP_PUBLISH_CROSS */
/* Description: Publish configuration for event CROSS */

/* Bit 31 :   */
#define COMP_PUBLISH_CROSS_EN_Pos (31UL) /*!< Position of EN field. */
#define COMP_PUBLISH_CROSS_EN_Msk (0x1UL << COMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field. */
#define COMP_PUBLISH_CROSS_EN_Disabled (0x0UL) /*!< Disable publishing */
#define COMP_PUBLISH_CROSS_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event CROSS will publish to */
#define COMP_PUBLISH_CROSS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define COMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << COMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: COMP_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 4 : Shortcut between event CROSS and task STOP */
#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
#define COMP_SHORTS_CROSS_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define COMP_SHORTS_CROSS_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 3 : Shortcut between event UP and task STOP */
#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
#define COMP_SHORTS_UP_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define COMP_SHORTS_UP_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 2 : Shortcut between event DOWN and task STOP */
#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
#define COMP_SHORTS_DOWN_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define COMP_SHORTS_DOWN_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 1 : Shortcut between event READY and task STOP */
#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
#define COMP_SHORTS_READY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define COMP_SHORTS_READY_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 0 : Shortcut between event READY and task SAMPLE */
#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
#define COMP_SHORTS_READY_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut */
#define COMP_SHORTS_READY_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: COMP_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 3 : Enable or disable interrupt for event CROSS */
#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTEN_CROSS_Disabled (0x0UL) /*!< Disable */
#define COMP_INTEN_CROSS_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event UP */
#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTEN_UP_Disabled (0x0UL) /*!< Disable */
#define COMP_INTEN_UP_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event DOWN */
#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTEN_DOWN_Disabled (0x0UL) /*!< Disable */
#define COMP_INTEN_DOWN_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event READY */
#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTEN_READY_Disabled (0x0UL) /*!< Disable */
#define COMP_INTEN_READY_Enabled (0x1UL) /*!< Enable */

/* Register: COMP_INTENSET */
/* Description: Enable interrupt */

/* Bit 3 : Write '1' to enable interrupt for event CROSS */
#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTENSET_CROSS_Disabled (0x0UL) /*!< Read: Disabled */
#define COMP_INTENSET_CROSS_Enabled (0x1UL) /*!< Read: Enabled */
#define COMP_INTENSET_CROSS_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event UP */
#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTENSET_UP_Disabled (0x0UL) /*!< Read: Disabled */
#define COMP_INTENSET_UP_Enabled (0x1UL) /*!< Read: Enabled */
#define COMP_INTENSET_UP_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event DOWN */
#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTENSET_DOWN_Disabled (0x0UL) /*!< Read: Disabled */
#define COMP_INTENSET_DOWN_Enabled (0x1UL) /*!< Read: Enabled */
#define COMP_INTENSET_DOWN_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event READY */
#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */
#define COMP_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */
#define COMP_INTENSET_READY_Set (0x1UL) /*!< Enable */

/* Register: COMP_INTENCLR */
/* Description: Disable interrupt */

/* Bit 3 : Write '1' to disable interrupt for event CROSS */
#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define COMP_INTENCLR_CROSS_Disabled (0x0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_CROSS_Enabled (0x1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_CROSS_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event UP */
#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
#define COMP_INTENCLR_UP_Disabled (0x0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_UP_Enabled (0x1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_UP_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event DOWN */
#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define COMP_INTENCLR_DOWN_Disabled (0x0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_DOWN_Enabled (0x1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_DOWN_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event READY */
#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define COMP_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */
#define COMP_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */
#define COMP_INTENCLR_READY_Clear (0x1UL) /*!< Disable */

/* Register: COMP_RESULT */
/* Description: Compare result */

/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
#define COMP_RESULT_RESULT_Below (0x0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
#define COMP_RESULT_RESULT_Above (0x1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */

/* Register: COMP_ENABLE */
/* Description: COMP enable */

/* Bits 1..0 : Enable or disable COMP */
#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define COMP_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
#define COMP_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable */

/* Register: COMP_PSEL */
/* Description: Pin select */

/* Bits 2..0 : Analog pin select */
#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
#define COMP_PSEL_PSEL_AnalogInput0 (0x0UL) /*!< AIN0 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput1 (0x1UL) /*!< AIN1 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput2 (0x2UL) /*!< AIN2 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput3 (0x3UL) /*!< AIN3 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput4 (0x4UL) /*!< AIN4 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput5 (0x5UL) /*!< AIN5 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput6 (0x6UL) /*!< AIN6 selected as analog input */
#define COMP_PSEL_PSEL_AnalogInput7 (0x7UL) /*!< AIN7 selected as analog input */

/* Register: COMP_REFSEL */
/* Description: Reference source select for single-ended mode */

/* Bits 2..0 : Reference select */
#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define COMP_REFSEL_REFSEL_Int1V2 (0x0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
#define COMP_REFSEL_REFSEL_Int1V8 (0x1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
#define COMP_REFSEL_REFSEL_Int2V4 (0x2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
#define COMP_REFSEL_REFSEL_VDD (0x4UL) /*!< VREF = VDD */
#define COMP_REFSEL_REFSEL_ARef (0x5UL) /*!< VREF = AREF */

/* Register: COMP_EXTREFSEL */
/* Description: External reference select */

/* Bits 2..0 : External analog reference select */
#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0x0UL) /*!< Use AIN0 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (0x1UL) /*!< Use AIN1 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (0x2UL) /*!< Use AIN2 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (0x3UL) /*!< Use AIN3 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (0x4UL) /*!< Use AIN4 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (0x5UL) /*!< Use AIN5 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (0x6UL) /*!< Use AIN6 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (0x7UL) /*!< Use AIN7 as external analog reference */

/* Register: COMP_TH */
/* Description: Threshold configuration for hysteresis unit */

/* Bits 13..8 : VUP = (THUP+1)/64*VREF */
#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */

/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */

/* Register: COMP_MODE */
/* Description: Mode configuration */

/* Bit 8 : Main operation modes */
#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
#define COMP_MODE_MAIN_SE (0x0UL) /*!< Single-ended mode */
#define COMP_MODE_MAIN_Diff (0x1UL) /*!< Differential mode */

/* Bits 1..0 : Speed and power modes */
#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
#define COMP_MODE_SP_Low (0x0UL) /*!< Low-power mode */
#define COMP_MODE_SP_Normal (0x1UL) /*!< Normal mode */
#define COMP_MODE_SP_High (0x2UL) /*!< High-speed mode */

/* Register: COMP_HYST */
/* Description: Comparator hysteresis enable */

/* Bit 0 : Comparator hysteresis */
#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
#define COMP_HYST_HYST_NoHyst (0x0UL) /*!< Comparator hysteresis disabled */
#define COMP_HYST_HYST_Hyst50mV (0x1UL) /*!< Comparator hysteresis enabled */

/* Register: COMP_ISOURCE */
/* Description: Current source select on analog input */

/* Bits 1..0 : Comparator hysteresis */
#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
#define COMP_ISOURCE_ISOURCE_Off (0x0UL) /*!< Current source disabled */
#define COMP_ISOURCE_ISOURCE_Ien2mA5 (0x1UL) /*!< Current source enabled (+/- 2.5 uA) */
#define COMP_ISOURCE_ISOURCE_Ien5mA (0x2UL) /*!< Current source enabled (+/- 5 uA) */
#define COMP_ISOURCE_ISOURCE_Ien10mA (0x3UL) /*!< Current source enabled (+/- 10 uA) */


/* Peripheral: CRYPTOCELL */
/* Description: CRYPTOCELL register interface */

/* Register: CRYPTOCELL_ENABLE */
/* Description: Enable CRYPTOCELL subsystem. */

/* Bit 0 : Enable or disable the CRYPTOCELL subsystem. */
#define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0x0UL) /*!< CRYPTOCELL subsystem disabled. */
#define CRYPTOCELL_ENABLE_ENABLE_Enabled (0x1UL) /*!< CRYPTOCELL subsystem enabled. */


/* Peripheral: CTI */
/* Description: Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. */

/* Register: CTI_CTICONTROL */
/* Description: CTI Control register */

/* Bit 0 : Enables or disables the CTI. */
#define CTI_CTICONTROL_GLBEN_Pos (0UL) /*!< Position of GLBEN field. */
#define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos) /*!< Bit mask of GLBEN field. */
#define CTI_CTICONTROL_GLBEN_Disabled (0x0UL) /*!< All cross-triggering mapping logic functionality is disabled. */
#define CTI_CTICONTROL_GLBEN_Enabled (0x1UL) /*!< Cross-triggering mapping logic functionality is enabled. */

/* Register: CTI_CTIINTACK */
/* Description: CTI Interrupt Acknowledge register */

/* Bit 7 : Acknowledges the ctitrigout 7 output. */
#define CTI_CTIINTACK_INTACK_7_Pos (7UL) /*!< Position of INTACK_7 field. */
#define CTI_CTIINTACK_INTACK_7_Msk (0x1UL << CTI_CTIINTACK_INTACK_7_Pos) /*!< Bit mask of INTACK_7 field. */
#define CTI_CTIINTACK_INTACK_7_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */

/* Bit 6 : Acknowledges the ctitrigout 6 output. */
#define CTI_CTIINTACK_INTACK_6_Pos (6UL) /*!< Position of INTACK_6 field. */
#define CTI_CTIINTACK_INTACK_6_Msk (0x1UL << CTI_CTIINTACK_INTACK_6_Pos) /*!< Bit mask of INTACK_6 field. */
#define CTI_CTIINTACK_INTACK_6_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */

/* Bit 5 : Acknowledges the ctitrigout 5 output. */
#define CTI_CTIINTACK_INTACK_5_Pos (5UL) /*!< Position of INTACK_5 field. */
#define CTI_CTIINTACK_INTACK_5_Msk (0x1UL << CTI_CTIINTACK_INTACK_5_Pos) /*!< Bit mask of INTACK_5 field. */
#define CTI_CTIINTACK_INTACK_5_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */

/* Bit 4 : Acknowledges the ctitrigout 4 output. */
#define CTI_CTIINTACK_INTACK_4_Pos (4UL) /*!< Position of INTACK_4 field. */
#define CTI_CTIINTACK_INTACK_4_Msk (0x1UL << CTI_CTIINTACK_INTACK_4_Pos) /*!< Bit mask of INTACK_4 field. */
#define CTI_CTIINTACK_INTACK_4_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */

/* Bit 3 : Acknowledges the ctitrigout 3 output. */
#define CTI_CTIINTACK_INTACK_3_Pos (3UL) /*!< Position of INTACK_3 field. */
#define CTI_CTIINTACK_INTACK_3_Msk (0x1UL << CTI_CTIINTACK_INTACK_3_Pos) /*!< Bit mask of INTACK_3 field. */
#define CTI_CTIINTACK_INTACK_3_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */

/* Bit 2 : Acknowledges the ctitrigout 2 output. */
#define CTI_CTIINTACK_INTACK_2_Pos (2UL) /*!< Position of INTACK_2 field. */
#define CTI_CTIINTACK_INTACK_2_Msk (0x1UL << CTI_CTIINTACK_INTACK_2_Pos) /*!< Bit mask of INTACK_2 field. */
#define CTI_CTIINTACK_INTACK_2_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */

/* Bit 1 : Acknowledges the ctitrigout 1 output. */
#define CTI_CTIINTACK_INTACK_1_Pos (1UL) /*!< Position of INTACK_1 field. */
#define CTI_CTIINTACK_INTACK_1_Msk (0x1UL << CTI_CTIINTACK_INTACK_1_Pos) /*!< Bit mask of INTACK_1 field. */
#define CTI_CTIINTACK_INTACK_1_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */

/* Bit 0 : Acknowledges the ctitrigout 0 output. */
#define CTI_CTIINTACK_INTACK_0_Pos (0UL) /*!< Position of INTACK_0 field. */
#define CTI_CTIINTACK_INTACK_0_Msk (0x1UL << CTI_CTIINTACK_INTACK_0_Pos) /*!< Bit mask of INTACK_0 field. */
#define CTI_CTIINTACK_INTACK_0_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */

/* Register: CTI_CTIAPPSET */
/* Description: CTI Application Trigger Set register */

/* Bit 3 : Application trigger event for channel 3. */
#define CTI_CTIAPPSET_APPSET_3_Pos (3UL) /*!< Position of APPSET_3 field. */
#define CTI_CTIAPPSET_APPSET_3_Msk (0x1UL << CTI_CTIAPPSET_APPSET_3_Pos) /*!< Bit mask of APPSET_3 field. */
#define CTI_CTIAPPSET_APPSET_3_Inactive (0x0UL) /*!< Application trigger 3 is inactive. */
#define CTI_CTIAPPSET_APPSET_3_Active (0x1UL) /*!< Application trigger 3 is active. */
#define CTI_CTIAPPSET_APPSET_3_Activate (0x1UL) /*!< Generate channel event for channel 3. */

/* Bit 2 : Application trigger event for channel 2. */
#define CTI_CTIAPPSET_APPSET_2_Pos (2UL) /*!< Position of APPSET_2 field. */
#define CTI_CTIAPPSET_APPSET_2_Msk (0x1UL << CTI_CTIAPPSET_APPSET_2_Pos) /*!< Bit mask of APPSET_2 field. */
#define CTI_CTIAPPSET_APPSET_2_Inactive (0x0UL) /*!< Application trigger 2 is inactive. */
#define CTI_CTIAPPSET_APPSET_2_Active (0x1UL) /*!< Application trigger 2 is active. */
#define CTI_CTIAPPSET_APPSET_2_Activate (0x1UL) /*!< Generate channel event for channel 2. */

/* Bit 1 : Application trigger event for channel 1. */
#define CTI_CTIAPPSET_APPSET_1_Pos (1UL) /*!< Position of APPSET_1 field. */
#define CTI_CTIAPPSET_APPSET_1_Msk (0x1UL << CTI_CTIAPPSET_APPSET_1_Pos) /*!< Bit mask of APPSET_1 field. */
#define CTI_CTIAPPSET_APPSET_1_Inactive (0x0UL) /*!< Application trigger 1 is inactive. */
#define CTI_CTIAPPSET_APPSET_1_Active (0x1UL) /*!< Application trigger 1 is active. */
#define CTI_CTIAPPSET_APPSET_1_Activate (0x1UL) /*!< Generate channel event for channel 1. */

/* Bit 0 : Application trigger event for channel 0. */
#define CTI_CTIAPPSET_APPSET_0_Pos (0UL) /*!< Position of APPSET_0 field. */
#define CTI_CTIAPPSET_APPSET_0_Msk (0x1UL << CTI_CTIAPPSET_APPSET_0_Pos) /*!< Bit mask of APPSET_0 field. */
#define CTI_CTIAPPSET_APPSET_0_Inactive (0x0UL) /*!< Application trigger 0 is inactive. */
#define CTI_CTIAPPSET_APPSET_0_Active (0x1UL) /*!< Application trigger 0 is active. */
#define CTI_CTIAPPSET_APPSET_0_Activate (0x1UL) /*!< Generate channel event for channel 0. */

/* Register: CTI_CTIAPPCLEAR */
/* Description: CTI Application Trigger Clear register */

/* Bit 3 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
#define CTI_CTIAPPCLEAR_APPCLEAR_3_Pos (3UL) /*!< Position of APPCLEAR_3 field. */
#define CTI_CTIAPPCLEAR_APPCLEAR_3_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_3_Pos) /*!< Bit mask of APPCLEAR_3 field. */
#define CTI_CTIAPPCLEAR_APPCLEAR_3_Clear (0x1UL) /*!< Clears the event for channel 3. */

/* Bit 2 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
#define CTI_CTIAPPCLEAR_APPCLEAR_2_Pos (2UL) /*!< Position of APPCLEAR_2 field. */
#define CTI_CTIAPPCLEAR_APPCLEAR_2_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_2_Pos) /*!< Bit mask of APPCLEAR_2 field. */
#define CTI_CTIAPPCLEAR_APPCLEAR_2_Clear (0x1UL) /*!< Clears the event for channel 2. */

/* Bit 1 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
#define CTI_CTIAPPCLEAR_APPCLEAR_1_Pos (1UL) /*!< Position of APPCLEAR_1 field. */
#define CTI_CTIAPPCLEAR_APPCLEAR_1_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_1_Pos) /*!< Bit mask of APPCLEAR_1 field. */
#define CTI_CTIAPPCLEAR_APPCLEAR_1_Clear (0x1UL) /*!< Clears the event for channel 1. */

/* Bit 0 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
#define CTI_CTIAPPCLEAR_APPCLEAR_0_Pos (0UL) /*!< Position of APPCLEAR_0 field. */
#define CTI_CTIAPPCLEAR_APPCLEAR_0_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_0_Pos) /*!< Bit mask of APPCLEAR_0 field. */
#define CTI_CTIAPPCLEAR_APPCLEAR_0_Clear (0x1UL) /*!< Clears the event for channel 0. */

/* Register: CTI_CTIAPPPULSE */
/* Description: CTI Application Pulse register */

/* Bit 3 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
#define CTI_CTIAPPPULSE_APPULSE_3_Pos (3UL) /*!< Position of APPULSE_3 field. */
#define CTI_CTIAPPPULSE_APPULSE_3_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_3_Pos) /*!< Bit mask of APPULSE_3 field. */
#define CTI_CTIAPPPULSE_APPULSE_3_Generate (0x1UL) /*!< Generates an event pulse on channel 3. */

/* Bit 2 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
#define CTI_CTIAPPPULSE_APPULSE_2_Pos (2UL) /*!< Position of APPULSE_2 field. */
#define CTI_CTIAPPPULSE_APPULSE_2_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_2_Pos) /*!< Bit mask of APPULSE_2 field. */
#define CTI_CTIAPPPULSE_APPULSE_2_Generate (0x1UL) /*!< Generates an event pulse on channel 2. */

/* Bit 1 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
#define CTI_CTIAPPPULSE_APPULSE_1_Pos (1UL) /*!< Position of APPULSE_1 field. */
#define CTI_CTIAPPPULSE_APPULSE_1_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_1_Pos) /*!< Bit mask of APPULSE_1 field. */
#define CTI_CTIAPPPULSE_APPULSE_1_Generate (0x1UL) /*!< Generates an event pulse on channel 1. */

/* Bit 0 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
#define CTI_CTIAPPPULSE_APPULSE_0_Pos (0UL) /*!< Position of APPULSE_0 field. */
#define CTI_CTIAPPPULSE_APPULSE_0_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_0_Pos) /*!< Bit mask of APPULSE_0 field. */
#define CTI_CTIAPPPULSE_APPULSE_0_Generate (0x1UL) /*!< Generates an event pulse on channel 0. */

/* Register: CTI_CTIINEN */
/* Description: Description collection: CTI Trigger to Channel Enable register */

/* Bit 3 : Enables a cross trigger event to channel 3 when a ctitrigin input is activated. */
#define CTI_CTIINEN_TRIGINEN_3_Pos (3UL) /*!< Position of TRIGINEN_3 field. */
#define CTI_CTIINEN_TRIGINEN_3_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_3_Pos) /*!< Bit mask of TRIGINEN_3 field. */
#define CTI_CTIINEN_TRIGINEN_3_Disabled (0x0UL) /*!< Input trigger n events are ignored by channel 3. */
#define CTI_CTIINEN_TRIGINEN_3_Enabled (0x1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. */

/* Bit 2 : Enables a cross trigger event to channel 2 when a ctitrigin input is activated. */
#define CTI_CTIINEN_TRIGINEN_2_Pos (2UL) /*!< Position of TRIGINEN_2 field. */
#define CTI_CTIINEN_TRIGINEN_2_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_2_Pos) /*!< Bit mask of TRIGINEN_2 field. */
#define CTI_CTIINEN_TRIGINEN_2_Disabled (0x0UL) /*!< Input trigger n events are ignored by channel 2. */
#define CTI_CTIINEN_TRIGINEN_2_Enabled (0x1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. */

/* Bit 1 : Enables a cross trigger event to channel 1 when a ctitrigin input is activated. */
#define CTI_CTIINEN_TRIGINEN_1_Pos (1UL) /*!< Position of TRIGINEN_1 field. */
#define CTI_CTIINEN_TRIGINEN_1_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_1_Pos) /*!< Bit mask of TRIGINEN_1 field. */
#define CTI_CTIINEN_TRIGINEN_1_Disabled (0x0UL) /*!< Input trigger n events are ignored by channel 1. */
#define CTI_CTIINEN_TRIGINEN_1_Enabled (0x1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. */

/* Bit 0 : Enables a cross trigger event to channel 0 when a ctitrigin input is activated. */
#define CTI_CTIINEN_TRIGINEN_0_Pos (0UL) /*!< Position of TRIGINEN_0 field. */
#define CTI_CTIINEN_TRIGINEN_0_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_0_Pos) /*!< Bit mask of TRIGINEN_0 field. */
#define CTI_CTIINEN_TRIGINEN_0_Disabled (0x0UL) /*!< Input trigger n events are ignored by channel 0. */
#define CTI_CTIINEN_TRIGINEN_0_Enabled (0x1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. */

/* Register: CTI_CTIOUTEN */
/* Description: Description collection: CTI Channel to Trigger Enable register */

/* Bit 3 : Enables a cross trigger event to ctitrigout when channel 3 is activated. */
#define CTI_CTIOUTEN_TRIGOUTEN_3_Pos (3UL) /*!< Position of TRIGOUTEN_3 field. */
#define CTI_CTIOUTEN_TRIGOUTEN_3_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_3_Pos) /*!< Bit mask of TRIGOUTEN_3 field. */
#define CTI_CTIOUTEN_TRIGOUTEN_3_Disabled (0x0UL) /*!< Channel 3 is ignored by output trigger n. */
#define CTI_CTIOUTEN_TRIGOUTEN_3_Enabled (0x1UL) /*!< When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). */

/* Bit 2 : Enables a cross trigger event to ctitrigout when channel 2 is activated. */
#define CTI_CTIOUTEN_TRIGOUTEN_2_Pos (2UL) /*!< Position of TRIGOUTEN_2 field. */
#define CTI_CTIOUTEN_TRIGOUTEN_2_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_2_Pos) /*!< Bit mask of TRIGOUTEN_2 field. */
#define CTI_CTIOUTEN_TRIGOUTEN_2_Disabled (0x0UL) /*!< Channel 2 is ignored by output trigger n. */
#define CTI_CTIOUTEN_TRIGOUTEN_2_Enabled (0x1UL) /*!< When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). */

/* Bit 1 : Enables a cross trigger event to ctitrigout when channel 1 is activated. */
#define CTI_CTIOUTEN_TRIGOUTEN_1_Pos (1UL) /*!< Position of TRIGOUTEN_1 field. */
#define CTI_CTIOUTEN_TRIGOUTEN_1_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_1_Pos) /*!< Bit mask of TRIGOUTEN_1 field. */
#define CTI_CTIOUTEN_TRIGOUTEN_1_Disabled (0x0UL) /*!< Channel 1 is ignored by output trigger n. */
#define CTI_CTIOUTEN_TRIGOUTEN_1_Enabled (0x1UL) /*!< When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). */

/* Bit 0 : Enables a cross trigger event to ctitrigout when channel 0 is activated. */
#define CTI_CTIOUTEN_TRIGOUTEN_0_Pos (0UL) /*!< Position of TRIGOUTEN_0 field. */
#define CTI_CTIOUTEN_TRIGOUTEN_0_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_0_Pos) /*!< Bit mask of TRIGOUTEN_0 field. */
#define CTI_CTIOUTEN_TRIGOUTEN_0_Disabled (0x0UL) /*!< Channel 0 is ignored by output trigger n. */
#define CTI_CTIOUTEN_TRIGOUTEN_0_Enabled (0x1UL) /*!< When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). */

/* Register: CTI_CTITRIGINSTATUS */
/* Description: CTI Trigger In Status register */

/* Bit 7 : Shows the status of ctitrigin7 input. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_7_Pos (7UL) /*!< Position of TRIGINSTATUS_7 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_7_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS_7_Pos) /*!< Bit mask of TRIGINSTATUS_7 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_7_Inactive (0x0UL) /*!< Ctitrigin 7 is inactive. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_7_Active (0x1UL) /*!< Ctitrigin 7 is active. */

/* Bit 6 : Shows the status of ctitrigin6 input. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_6_Pos (6UL) /*!< Position of TRIGINSTATUS_6 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_6_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS_6_Pos) /*!< Bit mask of TRIGINSTATUS_6 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_6_Inactive (0x0UL) /*!< Ctitrigin 6 is inactive. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_6_Active (0x1UL) /*!< Ctitrigin 6 is active. */

/* Bit 5 : Shows the status of ctitrigin5 input. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_5_Pos (5UL) /*!< Position of TRIGINSTATUS_5 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_5_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS_5_Pos) /*!< Bit mask of TRIGINSTATUS_5 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_5_Inactive (0x0UL) /*!< Ctitrigin 5 is inactive. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_5_Active (0x1UL) /*!< Ctitrigin 5 is active. */

/* Bit 4 : Shows the status of ctitrigin4 input. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_4_Pos (4UL) /*!< Position of TRIGINSTATUS_4 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_4_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS_4_Pos) /*!< Bit mask of TRIGINSTATUS_4 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_4_Inactive (0x0UL) /*!< Ctitrigin 4 is inactive. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_4_Active (0x1UL) /*!< Ctitrigin 4 is active. */

/* Bit 3 : Shows the status of ctitrigin3 input. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_3_Pos (3UL) /*!< Position of TRIGINSTATUS_3 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_3_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS_3_Pos) /*!< Bit mask of TRIGINSTATUS_3 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_3_Inactive (0x0UL) /*!< Ctitrigin 3 is inactive. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_3_Active (0x1UL) /*!< Ctitrigin 3 is active. */

/* Bit 2 : Shows the status of ctitrigin2 input. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_2_Pos (2UL) /*!< Position of TRIGINSTATUS_2 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_2_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS_2_Pos) /*!< Bit mask of TRIGINSTATUS_2 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_2_Inactive (0x0UL) /*!< Ctitrigin 2 is inactive. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_2_Active (0x1UL) /*!< Ctitrigin 2 is active. */

/* Bit 1 : Shows the status of ctitrigin1 input. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_1_Pos (1UL) /*!< Position of TRIGINSTATUS_1 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_1_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS_1_Pos) /*!< Bit mask of TRIGINSTATUS_1 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_1_Inactive (0x0UL) /*!< Ctitrigin 1 is inactive. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_1_Active (0x1UL) /*!< Ctitrigin 1 is active. */

/* Bit 0 : Shows the status of ctitrigin0 input. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_0_Pos (0UL) /*!< Position of TRIGINSTATUS_0 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_0_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS_0_Pos) /*!< Bit mask of TRIGINSTATUS_0 field. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_0_Inactive (0x0UL) /*!< Ctitrigin 0 is inactive. */
#define CTI_CTITRIGINSTATUS_TRIGINSTATUS_0_Active (0x1UL) /*!< Ctitrigin 0 is active. */

/* Register: CTI_CTITRIGOUTSTATUS */
/* Description: CTI Trigger Out Status register */

/* Bit 7 : Shows the status of ctitrigout7 output. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_7_Pos (7UL) /*!< Position of TRIGOUTSTATUS_7 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_7_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_7_Pos) /*!< Bit mask of TRIGOUTSTATUS_7 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_7_Inactive (0x0UL) /*!< Ctitrigout 7 is inactive. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_7_Active (0x1UL) /*!< Ctitrigout 7 is active. */

/* Bit 6 : Shows the status of ctitrigout6 output. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_6_Pos (6UL) /*!< Position of TRIGOUTSTATUS_6 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_6_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_6_Pos) /*!< Bit mask of TRIGOUTSTATUS_6 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_6_Inactive (0x0UL) /*!< Ctitrigout 6 is inactive. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_6_Active (0x1UL) /*!< Ctitrigout 6 is active. */

/* Bit 5 : Shows the status of ctitrigout5 output. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_5_Pos (5UL) /*!< Position of TRIGOUTSTATUS_5 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_5_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_5_Pos) /*!< Bit mask of TRIGOUTSTATUS_5 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_5_Inactive (0x0UL) /*!< Ctitrigout 5 is inactive. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_5_Active (0x1UL) /*!< Ctitrigout 5 is active. */

/* Bit 4 : Shows the status of ctitrigout4 output. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_4_Pos (4UL) /*!< Position of TRIGOUTSTATUS_4 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_4_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_4_Pos) /*!< Bit mask of TRIGOUTSTATUS_4 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_4_Inactive (0x0UL) /*!< Ctitrigout 4 is inactive. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_4_Active (0x1UL) /*!< Ctitrigout 4 is active. */

/* Bit 3 : Shows the status of ctitrigout3 output. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_3_Pos (3UL) /*!< Position of TRIGOUTSTATUS_3 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_3_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_3_Pos) /*!< Bit mask of TRIGOUTSTATUS_3 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_3_Inactive (0x0UL) /*!< Ctitrigout 3 is inactive. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_3_Active (0x1UL) /*!< Ctitrigout 3 is active. */

/* Bit 2 : Shows the status of ctitrigout2 output. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_2_Pos (2UL) /*!< Position of TRIGOUTSTATUS_2 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_2_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_2_Pos) /*!< Bit mask of TRIGOUTSTATUS_2 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_2_Inactive (0x0UL) /*!< Ctitrigout 2 is inactive. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_2_Active (0x1UL) /*!< Ctitrigout 2 is active. */

/* Bit 1 : Shows the status of ctitrigout1 output. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_1_Pos (1UL) /*!< Position of TRIGOUTSTATUS_1 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_1_Pos) /*!< Bit mask of TRIGOUTSTATUS_1 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_1_Inactive (0x0UL) /*!< Ctitrigout 1 is inactive. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_1_Active (0x1UL) /*!< Ctitrigout 1 is active. */

/* Bit 0 : Shows the status of ctitrigout0 output. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_0_Pos (0UL) /*!< Position of TRIGOUTSTATUS_0 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_0_Pos) /*!< Bit mask of TRIGOUTSTATUS_0 field. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_0_Inactive (0x0UL) /*!< Ctitrigout 0 is inactive. */
#define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS_0_Active (0x1UL) /*!< Ctitrigout 0 is active. */

/* Register: CTI_CTICHINSTATUS */
/* Description: CTI Channel In Status register */

/* Bit 3 : Shows the status of the ctitrigin 3 input. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos (3UL) /*!< Position of CTICHINSTATUS_3 field. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos) /*!< Bit mask of CTICHINSTATUS_3 field. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Inactive (0x0UL) /*!< Ctichin 3 is inactive. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Active (0x1UL) /*!< Ctichin 3 is active. */

/* Bit 2 : Shows the status of the ctitrigin 2 input. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos (2UL) /*!< Position of CTICHINSTATUS_2 field. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos) /*!< Bit mask of CTICHINSTATUS_2 field. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Inactive (0x0UL) /*!< Ctichin 2 is inactive. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Active (0x1UL) /*!< Ctichin 2 is active. */

/* Bit 1 : Shows the status of the ctitrigin 1 input. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos (1UL) /*!< Position of CTICHINSTATUS_1 field. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos) /*!< Bit mask of CTICHINSTATUS_1 field. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Inactive (0x0UL) /*!< Ctichin 1 is inactive. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Active (0x1UL) /*!< Ctichin 1 is active. */

/* Bit 0 : Shows the status of the ctitrigin 0 input. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos (0UL) /*!< Position of CTICHINSTATUS_0 field. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos) /*!< Bit mask of CTICHINSTATUS_0 field. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Inactive (0x0UL) /*!< Ctichin 0 is inactive. */
#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Active (0x1UL) /*!< Ctichin 0 is active. */

/* Register: CTI_CTIGATE */
/* Description: Enable CTI Channel Gate register */

/* Bit 3 : Enable ctichout3. */
#define CTI_CTIGATE_CTIGATEEN_3_Pos (3UL) /*!< Position of CTIGATEEN_3 field. */
#define CTI_CTIGATE_CTIGATEEN_3_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_3_Pos) /*!< Bit mask of CTIGATEEN_3 field. */
#define CTI_CTIGATE_CTIGATEEN_3_Disabled (0x0UL) /*!< Disable ctichout channel 3 propagation. */
#define CTI_CTIGATE_CTIGATEEN_3_Enabled (0x1UL) /*!< Enable ctichout channel 3 propagation. */

/* Bit 2 : Enable ctichout2. */
#define CTI_CTIGATE_CTIGATEEN_2_Pos (2UL) /*!< Position of CTIGATEEN_2 field. */
#define CTI_CTIGATE_CTIGATEEN_2_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_2_Pos) /*!< Bit mask of CTIGATEEN_2 field. */
#define CTI_CTIGATE_CTIGATEEN_2_Disabled (0x0UL) /*!< Disable ctichout channel 2 propagation. */
#define CTI_CTIGATE_CTIGATEEN_2_Enabled (0x1UL) /*!< Enable ctichout channel 2 propagation. */

/* Bit 1 : Enable ctichout1. */
#define CTI_CTIGATE_CTIGATEEN_1_Pos (1UL) /*!< Position of CTIGATEEN_1 field. */
#define CTI_CTIGATE_CTIGATEEN_1_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_1_Pos) /*!< Bit mask of CTIGATEEN_1 field. */
#define CTI_CTIGATE_CTIGATEEN_1_Disabled (0x0UL) /*!< Disable ctichout channel 1 propagation. */
#define CTI_CTIGATE_CTIGATEEN_1_Enabled (0x1UL) /*!< Enable ctichout channel 1 propagation. */

/* Bit 0 : Enable ctichout0. */
#define CTI_CTIGATE_CTIGATEEN_0_Pos (0UL) /*!< Position of CTIGATEEN_0 field. */
#define CTI_CTIGATE_CTIGATEEN_0_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_0_Pos) /*!< Bit mask of CTIGATEEN_0 field. */
#define CTI_CTIGATE_CTIGATEEN_0_Disabled (0x0UL) /*!< Disable ctichout channel 0 propagation. */
#define CTI_CTIGATE_CTIGATEEN_0_Enabled (0x1UL) /*!< Enable ctichout channel 0 propagation. */

/* Register: CTI_DEVARCH */
/* Description: Device Architecture register */

/* Bit 0 : Contains the CTI device architecture. */
#define CTI_DEVARCH_Architecture_Pos (0UL) /*!< Position of Architecture field. */
#define CTI_DEVARCH_Architecture_Msk (0x1UL << CTI_DEVARCH_Architecture_Pos) /*!< Bit mask of Architecture field. */

/* Register: CTI_DEVID */
/* Description: Device Configuration register */

/* Bits 19..16 : Number of ECT channels available. */
#define CTI_DEVID_NUMCH_Pos (16UL) /*!< Position of NUMCH field. */
#define CTI_DEVID_NUMCH_Msk (0xFUL << CTI_DEVID_NUMCH_Pos) /*!< Bit mask of NUMCH field. */

/* Bits 15..8 : Number of ECT triggers available. */
#define CTI_DEVID_NUMTRIG_Pos (8UL) /*!< Position of NUMTRIG field. */
#define CTI_DEVID_NUMTRIG_Msk (0xFFUL << CTI_DEVID_NUMTRIG_Pos) /*!< Bit mask of NUMTRIG field. */

/* Bits 4..0 : Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl.
                    The default value of 0b00000 indicates that no multiplexing is present. */
#define CTI_DEVID_EXTMUXNUM_Pos (0UL) /*!< Position of EXTMUXNUM field. */
#define CTI_DEVID_EXTMUXNUM_Msk (0x1FUL << CTI_DEVID_EXTMUXNUM_Pos) /*!< Bit mask of EXTMUXNUM field. */

/* Register: CTI_DEVTYPE */
/* Description: Device Type Identifier register */

/* Bits 7..4 : Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within
                    the major classification as specified in the MAJOR field. */
#define CTI_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */
#define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */
#define CTI_DEVTYPE_SUB_Crosstrigger (0x1UL) /*!< Indicates that this component is a sub-triggering component. */

/* Bits 3..0 : Major classification of the type of the debug component as specified in the Arm Architecture Specification for this
                    debug and trace component. */
#define CTI_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */
#define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */
#define CTI_DEVTYPE_MAJOR_Controller (0x4UL) /*!< Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. */

/* Register: CTI_PIDR4 */
/* Description: Peripheral ID4 Register */

/* Bits 7..4 : Always 0b0000. Indicates that the device only occupies 4KB of memory. */
#define CTI_PIDR4_SIZE_Pos (4UL) /*!< Position of SIZE field. */
#define CTI_PIDR4_SIZE_Msk (0xFUL << CTI_PIDR4_SIZE_Pos) /*!< Bit mask of SIZE field. */

/* Bits 3..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
#define CTI_PIDR4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */
#define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field. */
#define CTI_PIDR4_DES_2_Code (0x4UL) /*!< JEDEC continuation code. */

/* Register: CTI_PIDR0 */
/* Description: Peripheral ID0 Register */

/* Bits 7..0 : Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. */
#define CTI_PIDR0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */
#define CTI_PIDR0_PART_0_Msk (0xFFUL << CTI_PIDR0_PART_0_Pos) /*!< Bit mask of PART_0 field. */
#define CTI_PIDR0_PART_0_PartnumberL (0x21UL) /*!< Indicates bits[7:0] of the part number of the component. */

/* Register: CTI_PIDR1 */
/* Description: Peripheral ID1 Register */

/* Bits 7..4 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
#define CTI_PIDR1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */
#define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field. */
#define CTI_PIDR1_DES_0_Arm (0xBUL) /*!< Arm. Bits[3:0] of the JEDEC JEP106 Identity Code */

/* Bits 3..0 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. */
#define CTI_PIDR1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */
#define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field. */
#define CTI_PIDR1_PART_1_PartnumberH (0xDUL) /*!< Indicates bits[11:8] of the part number of the component. */

/* Register: CTI_PIDR2 */
/* Description: Peripheral ID2 Register */

/* Bits 7..4 : Peripheral revision */
#define CTI_PIDR2_REVISION_Pos (4UL) /*!< Position of REVISION field. */
#define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field. */
#define CTI_PIDR2_REVISION_Rev0p0 (0x0UL) /*!< This device is at r0p0 */

/* Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used. */
#define CTI_PIDR2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */
#define CTI_PIDR2_JEDEC_Msk (0x1UL << CTI_PIDR2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */

/* Bits 2..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
#define CTI_PIDR2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */
#define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field. */
#define CTI_PIDR2_DES_1_Arm (0x3UL) /*!< Arm. Bits[6:4] of the JEDEC JEP106 Identity Code */

/* Register: CTI_PIDR3 */
/* Description: Peripheral ID3 Register */

/* Bits 7..4 : Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after
                    implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a
                    metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. */
#define CTI_PIDR3_REVAND_Pos (4UL) /*!< Position of REVAND field. */
#define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field. */
#define CTI_PIDR3_REVAND_NoErrata (0x0UL) /*!< Indicates that there are no errata fixes to this component. */

/* Bits 3..0 : Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases,
                    this field is 0b0000. Customers change this value when they make authorized modifications to this component. */
#define CTI_PIDR3_CMOD_Pos (0UL) /*!< Position of CMOD field. */
#define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field. */
#define CTI_PIDR3_CMOD_Unmodified (0x0UL) /*!< Indicates that the customer has not modified this component. */

/* Register: CTI_CIDR0 */
/* Description: Component ID0 Register */

/* Bits 7..0 : Preamble[0]. Contains bits[7:0] of the component identification code. */
#define CTI_CIDR0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */
#define CTI_CIDR0_PRMBL_0_Msk (0xFFUL << CTI_CIDR0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */
#define CTI_CIDR0_PRMBL_0_Value (0x0DUL) /*!< Bits[7:0] of the identification code. */

/* Register: CTI_CIDR1 */
/* Description: Component ID1 Register */

/* Bits 7..4 : Class of the component, for example, whether the component is a ROM table or a generic CoreSight component.
                    Contains bits[15:12] of the component identification code */
#define CTI_CIDR1_CLASS_Pos (4UL) /*!< Position of CLASS field. */
#define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field. */
#define CTI_CIDR1_CLASS_Coresight (0x9UL) /*!< Indicates that the component is a CoreSight component. */

/* Bits 3..0 : Preamble[1]. Contains bits[11:8] of the component identification code. */
#define CTI_CIDR1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */
#define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */
#define CTI_CIDR1_PRMBL_1_Value (0x0UL) /*!< Bits[11:8] of the identification code. */

/* Register: CTI_CIDR2 */
/* Description: Component ID2 Register */

/* Bits 7..0 : Preamble[2]. Contains bits[23:16] of the component identification code. */
#define CTI_CIDR2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */
#define CTI_CIDR2_PRMBL_2_Msk (0xFFUL << CTI_CIDR2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */
#define CTI_CIDR2_PRMBL_2_Value (0x05UL) /*!< Bits[23:16] of the identification code. */

/* Register: CTI_CIDR3 */
/* Description: Component ID3 Register */

/* Bits 7..0 : Preamble[3]. Contains bits[31:24] of the component identification code. */
#define CTI_CIDR3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */
#define CTI_CIDR3_PRMBL_3_Msk (0xFFUL << CTI_CIDR3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */
#define CTI_CIDR3_PRMBL_3_Value (0xB1UL) /*!< Bits[31:24] of the identification code. */


/* Peripheral: CTRLAPPERI */
/* Description: Control access port 0 */

/* Register: CTRLAPPERI_MAILBOX_RXDATA */
/* Description: Data sent from the debugger to the CPU. */

/* Bits 31..0 : Data received from debugger */
#define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */
#define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */

/* Register: CTRLAPPERI_MAILBOX_RXSTATUS */
/* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */

/* Bit 0 : Status of data in register RXDATA */
#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */
#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */
#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register RXDATA */
#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (0x1UL) /*!< Data pending in register RXDATA */

/* Register: CTRLAPPERI_MAILBOX_TXDATA */
/* Description: Data sent from the CPU to the debugger. */

/* Bits 31..0 : Data sent to debugger */
#define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */
#define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */

/* Register: CTRLAPPERI_MAILBOX_TXSTATUS */
/* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */

/* Bit 0 : Status of data in register TXDATA */
#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */
#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */
#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register TXDATA */
#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (0x1UL) /*!< Data pending in register TXDATA */

/* Register: CTRLAPPERI_ERASEPROTECT_LOCK */
/* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */

/* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */
#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0x0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */
#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (0x1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */

/* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */
/* Description: This register disables the ERASEPROTECT register and performs an  ERASEALL operation. */

/* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */
#define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
#define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */

/* Register: CTRLAPPERI_APPROTECT_LOCK */
/* Description: This register locks the APPROTECT.DISABLE register from being written to until next reset. */

/* Bit 0 : Lock the APPROTECT.DISABLE register from being written to until next reset */
#define CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
#define CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define CTRLAPPERI_APPROTECT_LOCK_LOCK_Unlocked (0x0UL) /*!< Register APPROTECT.DISABLE is writeable */
#define CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked (0x1UL) /*!< Register APPROTECT.DISABLE is read-only */

/* Register: CTRLAPPERI_APPROTECT_DISABLE */
/* Description: This register disables the APPROTECT register and enables debug access to non-secure mode. */

/* Bits 31..0 : If the value of the KEY field is non-zero, and the KEY fields match on both the
        CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until
        the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. */
#define CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
#define CTRLAPPERI_APPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */

/* Register: CTRLAPPERI_SECUREAPPROTECT_LOCK */
/* Description: This register locks the SECUREAPPROTECT.DISABLE register from being written until next reset. */

/* Bit 0 : Lock register SECUREAPPROTECT.DISABLE from being written until next reset */
#define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
#define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Unlocked (0x0UL) /*!< Register SECUREAPPROTECT.DISABLE is writeable */
#define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked (0x1UL) /*!< Register SECUREAPPROTECT.DISABLE is read-only */

/* Register: CTRLAPPERI_SECUREAPPROTECT_DISABLE */
/* Description: This register disables the SECUREAPPROTECT register and enables debug access to secure mode. */

/* Bits 31..0 : If the value of the KEY field is non-zero, and the KEY fields match on both the
        CPU and debugger sides, disable SECUREAPPROTECT and enable debug access to secure mode until
        the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.SECUREAPPROTECT protection needs to be disabled. */
#define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
#define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */

/* Register: CTRLAPPERI_STATUS */
/* Description: Status bits for CTRL-AP peripheral. */

/* Bit 2 : Status bit for device debug interface mode */
#define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (2UL) /*!< Position of DBGIFACEMODE field. */
#define CTRLAPPERI_STATUS_DBGIFACEMODE_Msk (0x1UL << CTRLAPPERI_STATUS_DBGIFACEMODE_Pos) /*!< Bit mask of DBGIFACEMODE field. */
#define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0x0UL) /*!< No debugger attached */
#define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (0x1UL) /*!< Debugger is attached and device is in debug interface mode */

/* Bit 1 : Status bit for UICR part of secure access port protection at last reset. */
#define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Pos (1UL) /*!< Position of UICRSECUREAPPROTECT field. */
#define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Pos) /*!< Bit mask of UICRSECUREAPPROTECT field. */
#define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Enabled (0x0UL) /*!< SECUREAPPROTECT was enabled in UICR */
#define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Disabled (0x1UL) /*!< SECUREAPPROTECT was disabled in UICR */

/* Bit 0 : Status bit for UICR part of access port protection at last reset. */
#define CTRLAPPERI_STATUS_UICRAPPROTECT_Pos (0UL) /*!< Position of UICRAPPROTECT field. */
#define CTRLAPPERI_STATUS_UICRAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_UICRAPPROTECT_Pos) /*!< Bit mask of UICRAPPROTECT field. */
#define CTRLAPPERI_STATUS_UICRAPPROTECT_Enabled (0x0UL) /*!< APPROTECT was enabled in UICR */
#define CTRLAPPERI_STATUS_UICRAPPROTECT_Disabled (0x1UL) /*!< APPROTECT wasdisabled in UICR */


/* Peripheral: DCNF */
/* Description: Domain configuration management 0 */

/* Register: DCNF_CPUID */
/* Description: CPU ID of this subsystem */

/* Bits 7..0 : CPU ID */
#define DCNF_CPUID_CPUID_Pos (0UL) /*!< Position of CPUID field. */
#define DCNF_CPUID_CPUID_Msk (0xFFUL << DCNF_CPUID_CPUID_Pos) /*!< Bit mask of CPUID field. */

/* Register: DCNF_EXTPERI_PROTECT */
/* Description: Description cluster: Control access for master connected to AMLI master port EXTPERI[n] */

/* Bit 0 : Control access to slave 0 of master EXTPERI[n] */
#define DCNF_EXTPERI_PROTECT_SLAVE0_Pos (0UL) /*!< Position of SLAVE0 field. */
#define DCNF_EXTPERI_PROTECT_SLAVE0_Msk (0x1UL << DCNF_EXTPERI_PROTECT_SLAVE0_Pos) /*!< Bit mask of SLAVE0 field. */
#define DCNF_EXTPERI_PROTECT_SLAVE0_Allowed (0x0UL) /*!< Access to slave is allowed */
#define DCNF_EXTPERI_PROTECT_SLAVE0_Blocked (0x1UL) /*!< Access to slave is blocked */

/* Register: DCNF_EXTRAM_PROTECT */
/* Description: Description cluster: Control access from master connected to AMLI master port EXTRAM[n] */

/* Bit 7 : Control access to slave 7 of master EXTRAM[n] */
#define DCNF_EXTRAM_PROTECT_SLAVE7_Pos (7UL) /*!< Position of SLAVE7 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE7_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE7_Pos) /*!< Bit mask of SLAVE7 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE7_Allowed (0x0UL) /*!< Access to slave is allowed */
#define DCNF_EXTRAM_PROTECT_SLAVE7_Blocked (0x1UL) /*!< Access to slave is blocked */

/* Bit 6 : Control access to slave 6 of master EXTRAM[n] */
#define DCNF_EXTRAM_PROTECT_SLAVE6_Pos (6UL) /*!< Position of SLAVE6 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE6_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE6_Pos) /*!< Bit mask of SLAVE6 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE6_Allowed (0x0UL) /*!< Access to slave is allowed */
#define DCNF_EXTRAM_PROTECT_SLAVE6_Blocked (0x1UL) /*!< Access to slave is blocked */

/* Bit 5 : Control access to slave 5 of master EXTRAM[n] */
#define DCNF_EXTRAM_PROTECT_SLAVE5_Pos (5UL) /*!< Position of SLAVE5 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE5_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE5_Pos) /*!< Bit mask of SLAVE5 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE5_Allowed (0x0UL) /*!< Access to slave is allowed */
#define DCNF_EXTRAM_PROTECT_SLAVE5_Blocked (0x1UL) /*!< Access to slave is blocked */

/* Bit 4 : Control access to slave 4 of master EXTRAM[n] */
#define DCNF_EXTRAM_PROTECT_SLAVE4_Pos (4UL) /*!< Position of SLAVE4 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE4_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE4_Pos) /*!< Bit mask of SLAVE4 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE4_Allowed (0x0UL) /*!< Access to slave is allowed */
#define DCNF_EXTRAM_PROTECT_SLAVE4_Blocked (0x1UL) /*!< Access to slave is blocked */

/* Bit 3 : Control access to slave 3 of master EXTRAM[n] */
#define DCNF_EXTRAM_PROTECT_SLAVE3_Pos (3UL) /*!< Position of SLAVE3 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE3_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE3_Pos) /*!< Bit mask of SLAVE3 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE3_Allowed (0x0UL) /*!< Access to slave is allowed */
#define DCNF_EXTRAM_PROTECT_SLAVE3_Blocked (0x1UL) /*!< Access to slave is blocked */

/* Bit 2 : Control access to slave 2 of master EXTRAM[n] */
#define DCNF_EXTRAM_PROTECT_SLAVE2_Pos (2UL) /*!< Position of SLAVE2 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE2_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE2_Pos) /*!< Bit mask of SLAVE2 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE2_Allowed (0x0UL) /*!< Access to slave is allowed */
#define DCNF_EXTRAM_PROTECT_SLAVE2_Blocked (0x1UL) /*!< Access to slave is blocked */

/* Bit 1 : Control access to slave 1 of master EXTRAM[n] */
#define DCNF_EXTRAM_PROTECT_SLAVE1_Pos (1UL) /*!< Position of SLAVE1 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE1_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE1_Pos) /*!< Bit mask of SLAVE1 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE1_Allowed (0x0UL) /*!< Access to slave is allowed */
#define DCNF_EXTRAM_PROTECT_SLAVE1_Blocked (0x1UL) /*!< Access to slave is blocked */

/* Bit 0 : Control access to slave 0 of master EXTRAM[n] */
#define DCNF_EXTRAM_PROTECT_SLAVE0_Pos (0UL) /*!< Position of SLAVE0 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE0_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE0_Pos) /*!< Bit mask of SLAVE0 field. */
#define DCNF_EXTRAM_PROTECT_SLAVE0_Allowed (0x0UL) /*!< Access to slave is allowed */
#define DCNF_EXTRAM_PROTECT_SLAVE0_Blocked (0x1UL) /*!< Access to slave is blocked */

/* Register: DCNF_EXTCODE_PROTECT */
/* Description: Description cluster: Control access from master connected to AMLI master port EXTCODE[n] */

/* Bit 0 : Control access to slave 0 of master EXTCODE[n] */
#define DCNF_EXTCODE_PROTECT_SLAVE0_Pos (0UL) /*!< Position of SLAVE0 field. */
#define DCNF_EXTCODE_PROTECT_SLAVE0_Msk (0x1UL << DCNF_EXTCODE_PROTECT_SLAVE0_Pos) /*!< Bit mask of SLAVE0 field. */
#define DCNF_EXTCODE_PROTECT_SLAVE0_Allowed (0x0UL) /*!< Access to slave is allowed */
#define DCNF_EXTCODE_PROTECT_SLAVE0_Blocked (0x1UL) /*!< Access to slave is blocked */


/* Peripheral: DPPIC */
/* Description: Distributed programmable peripheral interconnect controller 0 */

/* Register: DPPIC_TASKS_CHG_EN */
/* Description: Description cluster: Enable channel group n */

/* Bit 0 : Enable channel group n */
#define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
#define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
#define DPPIC_TASKS_CHG_EN_EN_Trigger (0x1UL) /*!< Trigger task */

/* Register: DPPIC_TASKS_CHG_DIS */
/* Description: Description cluster: Disable channel group n */

/* Bit 0 : Disable channel group n */
#define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
#define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
#define DPPIC_TASKS_CHG_DIS_DIS_Trigger (0x1UL) /*!< Trigger task */

/* Register: DPPIC_SUBSCRIBE_CHG_EN */
/* Description: Description cluster: Subscribe configuration for task CHG[n].EN */

/* Bit 31 :   */
#define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */
#define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
#define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0x0UL) /*!< Disable subscription */
#define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */
#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: DPPIC_SUBSCRIBE_CHG_DIS */
/* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */

/* Bit 31 :   */
#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */
#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */
#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0x0UL) /*!< Disable subscription */
#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */
#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: DPPIC_CHEN */
/* Description: Channel enable register */

/* Bit 31 : Enable or disable channel 31 */
#define DPPIC_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define DPPIC_CHEN_CH31_Msk (0x1UL << DPPIC_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
#define DPPIC_CHEN_CH31_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH31_Enabled (0x1UL) /*!< Enable channel */

/* Bit 30 : Enable or disable channel 30 */
#define DPPIC_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define DPPIC_CHEN_CH30_Msk (0x1UL << DPPIC_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
#define DPPIC_CHEN_CH30_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH30_Enabled (0x1UL) /*!< Enable channel */

/* Bit 29 : Enable or disable channel 29 */
#define DPPIC_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define DPPIC_CHEN_CH29_Msk (0x1UL << DPPIC_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
#define DPPIC_CHEN_CH29_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH29_Enabled (0x1UL) /*!< Enable channel */

/* Bit 28 : Enable or disable channel 28 */
#define DPPIC_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define DPPIC_CHEN_CH28_Msk (0x1UL << DPPIC_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
#define DPPIC_CHEN_CH28_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH28_Enabled (0x1UL) /*!< Enable channel */

/* Bit 27 : Enable or disable channel 27 */
#define DPPIC_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define DPPIC_CHEN_CH27_Msk (0x1UL << DPPIC_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
#define DPPIC_CHEN_CH27_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH27_Enabled (0x1UL) /*!< Enable channel */

/* Bit 26 : Enable or disable channel 26 */
#define DPPIC_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define DPPIC_CHEN_CH26_Msk (0x1UL << DPPIC_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
#define DPPIC_CHEN_CH26_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH26_Enabled (0x1UL) /*!< Enable channel */

/* Bit 25 : Enable or disable channel 25 */
#define DPPIC_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define DPPIC_CHEN_CH25_Msk (0x1UL << DPPIC_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
#define DPPIC_CHEN_CH25_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH25_Enabled (0x1UL) /*!< Enable channel */

/* Bit 24 : Enable or disable channel 24 */
#define DPPIC_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define DPPIC_CHEN_CH24_Msk (0x1UL << DPPIC_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
#define DPPIC_CHEN_CH24_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH24_Enabled (0x1UL) /*!< Enable channel */

/* Bit 23 : Enable or disable channel 23 */
#define DPPIC_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define DPPIC_CHEN_CH23_Msk (0x1UL << DPPIC_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
#define DPPIC_CHEN_CH23_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH23_Enabled (0x1UL) /*!< Enable channel */

/* Bit 22 : Enable or disable channel 22 */
#define DPPIC_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define DPPIC_CHEN_CH22_Msk (0x1UL << DPPIC_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
#define DPPIC_CHEN_CH22_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH22_Enabled (0x1UL) /*!< Enable channel */

/* Bit 21 : Enable or disable channel 21 */
#define DPPIC_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define DPPIC_CHEN_CH21_Msk (0x1UL << DPPIC_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
#define DPPIC_CHEN_CH21_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH21_Enabled (0x1UL) /*!< Enable channel */

/* Bit 20 : Enable or disable channel 20 */
#define DPPIC_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define DPPIC_CHEN_CH20_Msk (0x1UL << DPPIC_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
#define DPPIC_CHEN_CH20_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH20_Enabled (0x1UL) /*!< Enable channel */

/* Bit 19 : Enable or disable channel 19 */
#define DPPIC_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define DPPIC_CHEN_CH19_Msk (0x1UL << DPPIC_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
#define DPPIC_CHEN_CH19_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH19_Enabled (0x1UL) /*!< Enable channel */

/* Bit 18 : Enable or disable channel 18 */
#define DPPIC_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define DPPIC_CHEN_CH18_Msk (0x1UL << DPPIC_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
#define DPPIC_CHEN_CH18_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH18_Enabled (0x1UL) /*!< Enable channel */

/* Bit 17 : Enable or disable channel 17 */
#define DPPIC_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define DPPIC_CHEN_CH17_Msk (0x1UL << DPPIC_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
#define DPPIC_CHEN_CH17_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH17_Enabled (0x1UL) /*!< Enable channel */

/* Bit 16 : Enable or disable channel 16 */
#define DPPIC_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define DPPIC_CHEN_CH16_Msk (0x1UL << DPPIC_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
#define DPPIC_CHEN_CH16_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH16_Enabled (0x1UL) /*!< Enable channel */

/* Bit 15 : Enable or disable channel 15 */
#define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
#define DPPIC_CHEN_CH15_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH15_Enabled (0x1UL) /*!< Enable channel */

/* Bit 14 : Enable or disable channel 14 */
#define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
#define DPPIC_CHEN_CH14_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH14_Enabled (0x1UL) /*!< Enable channel */

/* Bit 13 : Enable or disable channel 13 */
#define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
#define DPPIC_CHEN_CH13_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH13_Enabled (0x1UL) /*!< Enable channel */

/* Bit 12 : Enable or disable channel 12 */
#define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
#define DPPIC_CHEN_CH12_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH12_Enabled (0x1UL) /*!< Enable channel */

/* Bit 11 : Enable or disable channel 11 */
#define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
#define DPPIC_CHEN_CH11_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH11_Enabled (0x1UL) /*!< Enable channel */

/* Bit 10 : Enable or disable channel 10 */
#define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
#define DPPIC_CHEN_CH10_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH10_Enabled (0x1UL) /*!< Enable channel */

/* Bit 9 : Enable or disable channel 9 */
#define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
#define DPPIC_CHEN_CH9_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH9_Enabled (0x1UL) /*!< Enable channel */

/* Bit 8 : Enable or disable channel 8 */
#define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
#define DPPIC_CHEN_CH8_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH8_Enabled (0x1UL) /*!< Enable channel */

/* Bit 7 : Enable or disable channel 7 */
#define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
#define DPPIC_CHEN_CH7_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH7_Enabled (0x1UL) /*!< Enable channel */

/* Bit 6 : Enable or disable channel 6 */
#define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
#define DPPIC_CHEN_CH6_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH6_Enabled (0x1UL) /*!< Enable channel */

/* Bit 5 : Enable or disable channel 5 */
#define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
#define DPPIC_CHEN_CH5_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH5_Enabled (0x1UL) /*!< Enable channel */

/* Bit 4 : Enable or disable channel 4 */
#define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
#define DPPIC_CHEN_CH4_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH4_Enabled (0x1UL) /*!< Enable channel */

/* Bit 3 : Enable or disable channel 3 */
#define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
#define DPPIC_CHEN_CH3_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH3_Enabled (0x1UL) /*!< Enable channel */

/* Bit 2 : Enable or disable channel 2 */
#define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
#define DPPIC_CHEN_CH2_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH2_Enabled (0x1UL) /*!< Enable channel */

/* Bit 1 : Enable or disable channel 1 */
#define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
#define DPPIC_CHEN_CH1_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH1_Enabled (0x1UL) /*!< Enable channel */

/* Bit 0 : Enable or disable channel 0 */
#define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
#define DPPIC_CHEN_CH0_Disabled (0x0UL) /*!< Disable channel */
#define DPPIC_CHEN_CH0_Enabled (0x1UL) /*!< Enable channel */

/* Register: DPPIC_CHENSET */
/* Description: Channel enable set register */

/* Bit 31 : Channel 31 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define DPPIC_CHENSET_CH31_Msk (0x1UL << DPPIC_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
#define DPPIC_CHENSET_CH31_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH31_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH31_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 30 : Channel 30 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define DPPIC_CHENSET_CH30_Msk (0x1UL << DPPIC_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
#define DPPIC_CHENSET_CH30_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH30_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH30_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 29 : Channel 29 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define DPPIC_CHENSET_CH29_Msk (0x1UL << DPPIC_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
#define DPPIC_CHENSET_CH29_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH29_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH29_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 28 : Channel 28 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define DPPIC_CHENSET_CH28_Msk (0x1UL << DPPIC_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
#define DPPIC_CHENSET_CH28_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH28_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH28_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 27 : Channel 27 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define DPPIC_CHENSET_CH27_Msk (0x1UL << DPPIC_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
#define DPPIC_CHENSET_CH27_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH27_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH27_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 26 : Channel 26 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define DPPIC_CHENSET_CH26_Msk (0x1UL << DPPIC_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
#define DPPIC_CHENSET_CH26_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH26_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH26_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 25 : Channel 25 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define DPPIC_CHENSET_CH25_Msk (0x1UL << DPPIC_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
#define DPPIC_CHENSET_CH25_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH25_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH25_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 24 : Channel 24 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define DPPIC_CHENSET_CH24_Msk (0x1UL << DPPIC_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
#define DPPIC_CHENSET_CH24_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH24_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH24_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 23 : Channel 23 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define DPPIC_CHENSET_CH23_Msk (0x1UL << DPPIC_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
#define DPPIC_CHENSET_CH23_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH23_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH23_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 22 : Channel 22 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define DPPIC_CHENSET_CH22_Msk (0x1UL << DPPIC_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
#define DPPIC_CHENSET_CH22_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH22_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH22_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 21 : Channel 21 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define DPPIC_CHENSET_CH21_Msk (0x1UL << DPPIC_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
#define DPPIC_CHENSET_CH21_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH21_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH21_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 20 : Channel 20 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define DPPIC_CHENSET_CH20_Msk (0x1UL << DPPIC_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
#define DPPIC_CHENSET_CH20_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH20_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH20_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 19 : Channel 19 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define DPPIC_CHENSET_CH19_Msk (0x1UL << DPPIC_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
#define DPPIC_CHENSET_CH19_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH19_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH19_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 18 : Channel 18 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define DPPIC_CHENSET_CH18_Msk (0x1UL << DPPIC_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
#define DPPIC_CHENSET_CH18_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH18_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH18_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 17 : Channel 17 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define DPPIC_CHENSET_CH17_Msk (0x1UL << DPPIC_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
#define DPPIC_CHENSET_CH17_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH17_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH17_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 16 : Channel 16 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define DPPIC_CHENSET_CH16_Msk (0x1UL << DPPIC_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
#define DPPIC_CHENSET_CH16_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH16_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH16_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
#define DPPIC_CHENSET_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH15_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
#define DPPIC_CHENSET_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH14_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
#define DPPIC_CHENSET_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH13_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
#define DPPIC_CHENSET_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH12_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
#define DPPIC_CHENSET_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH11_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
#define DPPIC_CHENSET_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH10_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
#define DPPIC_CHENSET_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH9_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
#define DPPIC_CHENSET_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH8_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
#define DPPIC_CHENSET_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH7_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
#define DPPIC_CHENSET_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH6_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
#define DPPIC_CHENSET_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH5_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
#define DPPIC_CHENSET_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH4_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
#define DPPIC_CHENSET_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH3_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
#define DPPIC_CHENSET_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH2_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
#define DPPIC_CHENSET_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH1_Set (0x1UL) /*!< Write: Enable channel */

/* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */
#define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
#define DPPIC_CHENSET_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENSET_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENSET_CH0_Set (0x1UL) /*!< Write: Enable channel */

/* Register: DPPIC_CHENCLR */
/* Description: Channel enable clear register */

/* Bit 31 : Channel 31 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define DPPIC_CHENCLR_CH31_Msk (0x1UL << DPPIC_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
#define DPPIC_CHENCLR_CH31_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH31_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH31_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 30 : Channel 30 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define DPPIC_CHENCLR_CH30_Msk (0x1UL << DPPIC_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
#define DPPIC_CHENCLR_CH30_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH30_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH30_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 29 : Channel 29 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define DPPIC_CHENCLR_CH29_Msk (0x1UL << DPPIC_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
#define DPPIC_CHENCLR_CH29_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH29_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH29_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 28 : Channel 28 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define DPPIC_CHENCLR_CH28_Msk (0x1UL << DPPIC_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
#define DPPIC_CHENCLR_CH28_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH28_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH28_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 27 : Channel 27 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define DPPIC_CHENCLR_CH27_Msk (0x1UL << DPPIC_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
#define DPPIC_CHENCLR_CH27_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH27_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH27_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 26 : Channel 26 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define DPPIC_CHENCLR_CH26_Msk (0x1UL << DPPIC_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
#define DPPIC_CHENCLR_CH26_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH26_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH26_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 25 : Channel 25 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define DPPIC_CHENCLR_CH25_Msk (0x1UL << DPPIC_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
#define DPPIC_CHENCLR_CH25_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH25_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH25_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 24 : Channel 24 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define DPPIC_CHENCLR_CH24_Msk (0x1UL << DPPIC_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
#define DPPIC_CHENCLR_CH24_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH24_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH24_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 23 : Channel 23 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define DPPIC_CHENCLR_CH23_Msk (0x1UL << DPPIC_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
#define DPPIC_CHENCLR_CH23_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH23_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH23_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 22 : Channel 22 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define DPPIC_CHENCLR_CH22_Msk (0x1UL << DPPIC_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
#define DPPIC_CHENCLR_CH22_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH22_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH22_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 21 : Channel 21 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define DPPIC_CHENCLR_CH21_Msk (0x1UL << DPPIC_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
#define DPPIC_CHENCLR_CH21_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH21_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH21_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 20 : Channel 20 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define DPPIC_CHENCLR_CH20_Msk (0x1UL << DPPIC_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
#define DPPIC_CHENCLR_CH20_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH20_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH20_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 19 : Channel 19 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define DPPIC_CHENCLR_CH19_Msk (0x1UL << DPPIC_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
#define DPPIC_CHENCLR_CH19_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH19_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH19_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 18 : Channel 18 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define DPPIC_CHENCLR_CH18_Msk (0x1UL << DPPIC_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
#define DPPIC_CHENCLR_CH18_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH18_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH18_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 17 : Channel 17 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define DPPIC_CHENCLR_CH17_Msk (0x1UL << DPPIC_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
#define DPPIC_CHENCLR_CH17_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH17_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH17_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 16 : Channel 16 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define DPPIC_CHENCLR_CH16_Msk (0x1UL << DPPIC_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
#define DPPIC_CHENCLR_CH16_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH16_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH16_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 15 : Channel 15 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
#define DPPIC_CHENCLR_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH15_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 14 : Channel 14 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
#define DPPIC_CHENCLR_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH14_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 13 : Channel 13 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
#define DPPIC_CHENCLR_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH13_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 12 : Channel 12 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
#define DPPIC_CHENCLR_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH12_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 11 : Channel 11 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
#define DPPIC_CHENCLR_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH11_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 10 : Channel 10 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
#define DPPIC_CHENCLR_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH10_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 9 : Channel 9 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
#define DPPIC_CHENCLR_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH9_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 8 : Channel 8 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
#define DPPIC_CHENCLR_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH8_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 7 : Channel 7 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
#define DPPIC_CHENCLR_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH7_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 6 : Channel 6 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
#define DPPIC_CHENCLR_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH6_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 5 : Channel 5 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
#define DPPIC_CHENCLR_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH5_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 4 : Channel 4 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
#define DPPIC_CHENCLR_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH4_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 3 : Channel 3 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
#define DPPIC_CHENCLR_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH3_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 2 : Channel 2 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
#define DPPIC_CHENCLR_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH2_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 1 : Channel 1 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
#define DPPIC_CHENCLR_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH1_Clear (0x1UL) /*!< Write: Disable channel */

/* Bit 0 : Channel 0 enable clear register.  Writing 0 has no effect. */
#define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
#define DPPIC_CHENCLR_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */
#define DPPIC_CHENCLR_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */
#define DPPIC_CHENCLR_CH0_Clear (0x1UL) /*!< Write: Disable channel */

/* Register: DPPIC_CHG */
/* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */

/* Bit 31 : Include or exclude channel 31 */
#define DPPIC_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
#define DPPIC_CHG_CH31_Msk (0x1UL << DPPIC_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
#define DPPIC_CHG_CH31_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH31_Included (0x1UL) /*!< Include */

/* Bit 30 : Include or exclude channel 30 */
#define DPPIC_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
#define DPPIC_CHG_CH30_Msk (0x1UL << DPPIC_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
#define DPPIC_CHG_CH30_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH30_Included (0x1UL) /*!< Include */

/* Bit 29 : Include or exclude channel 29 */
#define DPPIC_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
#define DPPIC_CHG_CH29_Msk (0x1UL << DPPIC_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
#define DPPIC_CHG_CH29_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH29_Included (0x1UL) /*!< Include */

/* Bit 28 : Include or exclude channel 28 */
#define DPPIC_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
#define DPPIC_CHG_CH28_Msk (0x1UL << DPPIC_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
#define DPPIC_CHG_CH28_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH28_Included (0x1UL) /*!< Include */

/* Bit 27 : Include or exclude channel 27 */
#define DPPIC_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
#define DPPIC_CHG_CH27_Msk (0x1UL << DPPIC_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
#define DPPIC_CHG_CH27_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH27_Included (0x1UL) /*!< Include */

/* Bit 26 : Include or exclude channel 26 */
#define DPPIC_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
#define DPPIC_CHG_CH26_Msk (0x1UL << DPPIC_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
#define DPPIC_CHG_CH26_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH26_Included (0x1UL) /*!< Include */

/* Bit 25 : Include or exclude channel 25 */
#define DPPIC_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
#define DPPIC_CHG_CH25_Msk (0x1UL << DPPIC_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
#define DPPIC_CHG_CH25_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH25_Included (0x1UL) /*!< Include */

/* Bit 24 : Include or exclude channel 24 */
#define DPPIC_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
#define DPPIC_CHG_CH24_Msk (0x1UL << DPPIC_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
#define DPPIC_CHG_CH24_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH24_Included (0x1UL) /*!< Include */

/* Bit 23 : Include or exclude channel 23 */
#define DPPIC_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
#define DPPIC_CHG_CH23_Msk (0x1UL << DPPIC_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
#define DPPIC_CHG_CH23_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH23_Included (0x1UL) /*!< Include */

/* Bit 22 : Include or exclude channel 22 */
#define DPPIC_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
#define DPPIC_CHG_CH22_Msk (0x1UL << DPPIC_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
#define DPPIC_CHG_CH22_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH22_Included (0x1UL) /*!< Include */

/* Bit 21 : Include or exclude channel 21 */
#define DPPIC_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
#define DPPIC_CHG_CH21_Msk (0x1UL << DPPIC_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
#define DPPIC_CHG_CH21_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH21_Included (0x1UL) /*!< Include */

/* Bit 20 : Include or exclude channel 20 */
#define DPPIC_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
#define DPPIC_CHG_CH20_Msk (0x1UL << DPPIC_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
#define DPPIC_CHG_CH20_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH20_Included (0x1UL) /*!< Include */

/* Bit 19 : Include or exclude channel 19 */
#define DPPIC_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
#define DPPIC_CHG_CH19_Msk (0x1UL << DPPIC_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
#define DPPIC_CHG_CH19_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH19_Included (0x1UL) /*!< Include */

/* Bit 18 : Include or exclude channel 18 */
#define DPPIC_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
#define DPPIC_CHG_CH18_Msk (0x1UL << DPPIC_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
#define DPPIC_CHG_CH18_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH18_Included (0x1UL) /*!< Include */

/* Bit 17 : Include or exclude channel 17 */
#define DPPIC_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
#define DPPIC_CHG_CH17_Msk (0x1UL << DPPIC_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
#define DPPIC_CHG_CH17_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH17_Included (0x1UL) /*!< Include */

/* Bit 16 : Include or exclude channel 16 */
#define DPPIC_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
#define DPPIC_CHG_CH16_Msk (0x1UL << DPPIC_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
#define DPPIC_CHG_CH16_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH16_Included (0x1UL) /*!< Include */

/* Bit 15 : Include or exclude channel 15 */
#define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
#define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
#define DPPIC_CHG_CH15_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH15_Included (0x1UL) /*!< Include */

/* Bit 14 : Include or exclude channel 14 */
#define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
#define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
#define DPPIC_CHG_CH14_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH14_Included (0x1UL) /*!< Include */

/* Bit 13 : Include or exclude channel 13 */
#define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
#define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
#define DPPIC_CHG_CH13_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH13_Included (0x1UL) /*!< Include */

/* Bit 12 : Include or exclude channel 12 */
#define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
#define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
#define DPPIC_CHG_CH12_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH12_Included (0x1UL) /*!< Include */

/* Bit 11 : Include or exclude channel 11 */
#define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
#define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
#define DPPIC_CHG_CH11_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH11_Included (0x1UL) /*!< Include */

/* Bit 10 : Include or exclude channel 10 */
#define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
#define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
#define DPPIC_CHG_CH10_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH10_Included (0x1UL) /*!< Include */

/* Bit 9 : Include or exclude channel 9 */
#define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
#define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
#define DPPIC_CHG_CH9_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH9_Included (0x1UL) /*!< Include */

/* Bit 8 : Include or exclude channel 8 */
#define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
#define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
#define DPPIC_CHG_CH8_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH8_Included (0x1UL) /*!< Include */

/* Bit 7 : Include or exclude channel 7 */
#define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
#define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
#define DPPIC_CHG_CH7_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH7_Included (0x1UL) /*!< Include */

/* Bit 6 : Include or exclude channel 6 */
#define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
#define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
#define DPPIC_CHG_CH6_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH6_Included (0x1UL) /*!< Include */

/* Bit 5 : Include or exclude channel 5 */
#define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
#define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
#define DPPIC_CHG_CH5_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH5_Included (0x1UL) /*!< Include */

/* Bit 4 : Include or exclude channel 4 */
#define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
#define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
#define DPPIC_CHG_CH4_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH4_Included (0x1UL) /*!< Include */

/* Bit 3 : Include or exclude channel 3 */
#define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
#define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
#define DPPIC_CHG_CH3_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH3_Included (0x1UL) /*!< Include */

/* Bit 2 : Include or exclude channel 2 */
#define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
#define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
#define DPPIC_CHG_CH2_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH2_Included (0x1UL) /*!< Include */

/* Bit 1 : Include or exclude channel 1 */
#define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
#define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
#define DPPIC_CHG_CH1_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH1_Included (0x1UL) /*!< Include */

/* Bit 0 : Include or exclude channel 0 */
#define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
#define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
#define DPPIC_CHG_CH0_Excluded (0x0UL) /*!< Exclude */
#define DPPIC_CHG_CH0_Included (0x1UL) /*!< Include */


/* Peripheral: EGU */
/* Description: Event generator unit 0 */

/* Register: EGU_TASKS_TRIGGER */
/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */

/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */

/* Register: EGU_SUBSCRIBE_TRIGGER */
/* Description: Description collection: Subscribe configuration for task TRIGGER[n] */

/* Bit 31 :   */
#define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */
#define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */
#define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL) /*!< Disable subscription */
#define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */
#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: EGU_EVENTS_TRIGGERED */
/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */

/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated */
#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated */

/* Register: EGU_PUBLISH_TRIGGERED */
/* Description: Description collection: Publish configuration for event TRIGGERED[n] */

/* Bit 31 :   */
#define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */
#define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */
#define EGU_PUBLISH_TRIGGERED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define EGU_PUBLISH_TRIGGERED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to */
#define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: EGU_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTEN_TRIGGERED15_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED15_Enabled (0x1UL) /*!< Enable */

/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTEN_TRIGGERED14_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED14_Enabled (0x1UL) /*!< Enable */

/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTEN_TRIGGERED13_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED13_Enabled (0x1UL) /*!< Enable */

/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTEN_TRIGGERED12_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED12_Enabled (0x1UL) /*!< Enable */

/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTEN_TRIGGERED11_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED11_Enabled (0x1UL) /*!< Enable */

/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTEN_TRIGGERED10_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED10_Enabled (0x1UL) /*!< Enable */

/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTEN_TRIGGERED9_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED9_Enabled (0x1UL) /*!< Enable */

/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTEN_TRIGGERED8_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED8_Enabled (0x1UL) /*!< Enable */

/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTEN_TRIGGERED7_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED7_Enabled (0x1UL) /*!< Enable */

/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTEN_TRIGGERED6_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED6_Enabled (0x1UL) /*!< Enable */

/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTEN_TRIGGERED5_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED5_Enabled (0x1UL) /*!< Enable */

/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTEN_TRIGGERED4_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED4_Enabled (0x1UL) /*!< Enable */

/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTEN_TRIGGERED3_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED3_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTEN_TRIGGERED2_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED2_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTEN_TRIGGERED1_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED1_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTEN_TRIGGERED0_Disabled (0x0UL) /*!< Disable */
#define EGU_INTEN_TRIGGERED0_Enabled (0x1UL) /*!< Enable */

/* Register: EGU_INTENSET */
/* Description: Enable interrupt */

/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTENSET_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED15_Set (0x1UL) /*!< Enable */

/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTENSET_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED14_Set (0x1UL) /*!< Enable */

/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTENSET_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED13_Set (0x1UL) /*!< Enable */

/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTENSET_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED12_Set (0x1UL) /*!< Enable */

/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTENSET_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED11_Set (0x1UL) /*!< Enable */

/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTENSET_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED10_Set (0x1UL) /*!< Enable */

/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTENSET_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED9_Set (0x1UL) /*!< Enable */

/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTENSET_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED8_Set (0x1UL) /*!< Enable */

/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTENSET_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED7_Set (0x1UL) /*!< Enable */

/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTENSET_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED6_Set (0x1UL) /*!< Enable */

/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTENSET_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED5_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTENSET_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED4_Set (0x1UL) /*!< Enable */

/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTENSET_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED3_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTENSET_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED2_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTENSET_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED1_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTENSET_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENSET_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENSET_TRIGGERED0_Set (0x1UL) /*!< Enable */

/* Register: EGU_INTENCLR */
/* Description: Disable interrupt */

/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
#define EGU_INTENCLR_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED15_Clear (0x1UL) /*!< Disable */

/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
#define EGU_INTENCLR_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED14_Clear (0x1UL) /*!< Disable */

/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
#define EGU_INTENCLR_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED13_Clear (0x1UL) /*!< Disable */

/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
#define EGU_INTENCLR_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED12_Clear (0x1UL) /*!< Disable */

/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
#define EGU_INTENCLR_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED11_Clear (0x1UL) /*!< Disable */

/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
#define EGU_INTENCLR_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED10_Clear (0x1UL) /*!< Disable */

/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
#define EGU_INTENCLR_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED9_Clear (0x1UL) /*!< Disable */

/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
#define EGU_INTENCLR_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED8_Clear (0x1UL) /*!< Disable */

/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
#define EGU_INTENCLR_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED7_Clear (0x1UL) /*!< Disable */

/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
#define EGU_INTENCLR_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED6_Clear (0x1UL) /*!< Disable */

/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
#define EGU_INTENCLR_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED5_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
#define EGU_INTENCLR_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED4_Clear (0x1UL) /*!< Disable */

/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
#define EGU_INTENCLR_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED3_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
#define EGU_INTENCLR_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED2_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
#define EGU_INTENCLR_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED1_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
#define EGU_INTENCLR_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */
#define EGU_INTENCLR_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */
#define EGU_INTENCLR_TRIGGERED0_Clear (0x1UL) /*!< Disable */


/* Peripheral: FICR */
/* Description: Factory Information Configuration Registers */

/* Register: FICR_INFO_CONFIGID */
/* Description: Configuration identifier */

/* Bits 15..0 : Identification number for the HW */
#define FICR_INFO_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
#define FICR_INFO_CONFIGID_HWID_Msk (0xFFFFUL << FICR_INFO_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */

/* Register: FICR_INFO_DEVICEID */
/* Description: Description collection: Device identifier */

/* Bits 31..0 : 64 bit unique device identifier */
#define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
#define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */

/* Register: FICR_INFO_PART */
/* Description: Part code */

/* Bits 31..0 : Part code */
#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
#define FICR_INFO_PART_PART_N5340 (0x00005340UL) /*!< nRF5340 */
#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */

/* Register: FICR_INFO_VARIANT */
/* Description: Part Variant, Hardware version and Production configuration */

/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
#define FICR_INFO_VARIANT_VARIANT_CLAA (0x434C4141UL) /*!< CLAA */
#define FICR_INFO_VARIANT_VARIANT_QKAA (0x514B4141UL) /*!< QKAA */
#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */

/* Register: FICR_INFO_PACKAGE */
/* Description: Package option */

/* Bits 31..0 : Package option */
#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
#define FICR_INFO_PACKAGE_PACKAGE_QK (0x00002000UL) /*!< QKxx - 94-pin aQFN */
#define FICR_INFO_PACKAGE_PACKAGE_CL (0x00002005UL) /*!< CLxx - WLCSP */
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */

/* Register: FICR_INFO_RAM */
/* Description: RAM variant */

/* Bits 31..0 : RAM variant */
#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
#define FICR_INFO_RAM_RAM_K16 (0x00000010UL) /*!< 16 kByte RAM */
#define FICR_INFO_RAM_RAM_K32 (0x00000020UL) /*!< 32 kByte RAM */
#define FICR_INFO_RAM_RAM_K64 (0x00000040UL) /*!< 64 kByte RAM */
#define FICR_INFO_RAM_RAM_K128 (0x00000080UL) /*!< 128 kByte RAM */
#define FICR_INFO_RAM_RAM_K256 (0x00000100UL) /*!< 256 kByte RAM */
#define FICR_INFO_RAM_RAM_K512 (0x00000200UL) /*!< 512 kByte RAM */
#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */

/* Register: FICR_INFO_FLASH */
/* Description: Flash variant */

/* Bits 31..0 : Flash variant */
#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
#define FICR_INFO_FLASH_FLASH_K128 (0x00000080UL) /*!< 128 kByte FLASH */
#define FICR_INFO_FLASH_FLASH_K256 (0x00000100UL) /*!< 256 kByte FLASH */
#define FICR_INFO_FLASH_FLASH_K512 (0x00000200UL) /*!< 512 kByte FLASH */
#define FICR_INFO_FLASH_FLASH_K1024 (0x00000400UL) /*!< 1 MByte FLASH */
#define FICR_INFO_FLASH_FLASH_K2048 (0x00000800UL) /*!< 2 MByte FLASH */
#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */

/* Register: FICR_INFO_CODEPAGESIZE */
/* Description: Code memory page size in bytes */

/* Bits 31..0 : Code memory page size in bytes */
#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x00001000UL) /*!< 4 kByte */

/* Register: FICR_INFO_CODESIZE */
/* Description: Code memory size */

/* Bits 31..0 : Code memory size in number of pages */
#define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
#define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
#define FICR_INFO_CODESIZE_CODESIZE_P256 (0x00000100UL) /*!< 256 pages */

/* Register: FICR_INFO_DEVICETYPE */
/* Description: Device type */

/* Bits 31..0 : Device type */
#define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */
#define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */
#define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x00000000UL) /*!< Device is an physical DIE */
#define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */

/* Register: FICR_TRIMCNF_ADDR */
/* Description: Description cluster: Address of the PAR register which will be written */

/* Bits 31..0 : Address */
#define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */
#define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */

/* Register: FICR_TRIMCNF_DATA */
/* Description: Description cluster: Data */

/* Bits 31..0 : Data to be written into the PAR register */
#define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */
#define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */

/* Register: FICR_NFC_TAGHEADER0 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */

/* Bits 31..24 : Unique identifier byte 3 */
#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */

/* Bits 23..16 : Unique identifier byte 2 */
#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */

/* Bits 15..8 : Unique identifier byte 1 */
#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */

/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */

/* Register: FICR_NFC_TAGHEADER1 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */

/* Bits 31..24 : Unique identifier byte 7 */
#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */

/* Bits 23..16 : Unique identifier byte 6 */
#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */

/* Bits 15..8 : Unique identifier byte 5 */
#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */

/* Bits 7..0 : Unique identifier byte 4 */
#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */

/* Register: FICR_NFC_TAGHEADER2 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */

/* Bits 31..24 : Unique identifier byte 11 */
#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */

/* Bits 23..16 : Unique identifier byte 10 */
#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */

/* Bits 15..8 : Unique identifier byte 9 */
#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */

/* Bits 7..0 : Unique identifier byte 8 */
#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */

/* Register: FICR_NFC_TAGHEADER3 */
/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */

/* Bits 31..24 : Unique identifier byte 15 */
#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */

/* Bits 23..16 : Unique identifier byte 14 */
#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */

/* Bits 15..8 : Unique identifier byte 13 */
#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */

/* Bits 7..0 : Unique identifier byte 12 */
#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */

/* Register: FICR_TRNG90B_BYTES */
/* Description: Amount of bytes for the required entropy bits */

/* Bits 31..0 : Amount of bytes for the required entropy bits */
#define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */
#define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */

/* Register: FICR_TRNG90B_RCCUTOFF */
/* Description: Repetition counter cutoff */

/* Bits 31..0 : Repetition counter cutoff */
#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */
#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */

/* Register: FICR_TRNG90B_APCUTOFF */
/* Description: Adaptive proportion cutoff */

/* Bits 31..0 : Adaptive proportion cutoff */
#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */
#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */

/* Register: FICR_TRNG90B_STARTUP */
/* Description: Amount of bytes for the startup tests */

/* Bits 31..0 : Amount of bytes for the startup tests */
#define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */
#define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */

/* Register: FICR_TRNG90B_ROSC1 */
/* Description: Sample count for ring oscillator 1 */

/* Bits 31..0 : Sample count for ring oscillator 1 */
#define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
#define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */

/* Register: FICR_TRNG90B_ROSC2 */
/* Description: Sample count for ring oscillator 2 */

/* Bits 31..0 : Sample count for ring oscillator 2 */
#define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */
#define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */

/* Register: FICR_TRNG90B_ROSC3 */
/* Description: Sample count for ring oscillator 3 */

/* Bits 31..0 : Sample count for ring oscillator 3 */
#define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */
#define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */

/* Register: FICR_TRNG90B_ROSC4 */
/* Description: Sample count for ring oscillator 4 */

/* Bits 31..0 : Sample count for ring oscillator 4 */
#define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */
#define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */

/* Register: FICR_XOSC32MTRIM */
/* Description: XOSC32M capacitor selection trim values */

/* Bits 9..5 : Offset trim factor on integer form */
#define FICR_XOSC32MTRIM_OFFSET_Pos (5UL) /*!< Position of OFFSET field. */
#define FICR_XOSC32MTRIM_OFFSET_Msk (0x1FUL << FICR_XOSC32MTRIM_OFFSET_Pos) /*!< Bit mask of OFFSET field. */

/* Bits 4..0 : Slope trim factor on twos complement form */
#define FICR_XOSC32MTRIM_SLOPE_Pos (0UL) /*!< Position of SLOPE field. */
#define FICR_XOSC32MTRIM_SLOPE_Msk (0x1FUL << FICR_XOSC32MTRIM_SLOPE_Pos) /*!< Bit mask of SLOPE field. */


/* Peripheral: FPU */
/* Description: FPU control peripheral 0 */

/* Register: FPU_EVENTS_INVALIDOPERATION */
/* Description: An FPUIOC exception triggered by an invalid operation has occurred in the FPU */

/* Bit 0 : An FPUIOC exception triggered by an invalid operation has occurred in the FPU */
#define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Pos (0UL) /*!< Position of EVENTS_INVALIDOPERATION field. */
#define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Msk (0x1UL << FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Pos) /*!< Bit mask of EVENTS_INVALIDOPERATION field. */
#define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_NotGenerated (0x0UL) /*!< Event not generated */
#define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Generated (0x1UL) /*!< Event generated */

/* Register: FPU_EVENTS_DIVIDEBYZERO */
/* Description: An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU */

/* Bit 0 : An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU */
#define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Pos (0UL) /*!< Position of EVENTS_DIVIDEBYZERO field. */
#define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Msk (0x1UL << FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Pos) /*!< Bit mask of EVENTS_DIVIDEBYZERO field. */
#define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_NotGenerated (0x0UL) /*!< Event not generated */
#define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Generated (0x1UL) /*!< Event generated */

/* Register: FPU_EVENTS_OVERFLOW */
/* Description: An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU */

/* Bit 0 : An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU */
#define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Pos (0UL) /*!< Position of EVENTS_OVERFLOW field. */
#define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Msk (0x1UL << FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Pos) /*!< Bit mask of EVENTS_OVERFLOW field. */
#define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_NotGenerated (0x0UL) /*!< Event not generated */
#define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Generated (0x1UL) /*!< Event generated */

/* Register: FPU_EVENTS_UNDERFLOW */
/* Description: An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU */

/* Bit 0 : An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU */
#define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Pos (0UL) /*!< Position of EVENTS_UNDERFLOW field. */
#define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Msk (0x1UL << FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Pos) /*!< Bit mask of EVENTS_UNDERFLOW field. */
#define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_NotGenerated (0x0UL) /*!< Event not generated */
#define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Generated (0x1UL) /*!< Event generated */

/* Register: FPU_EVENTS_INEXACT */
/* Description: An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU */

/* Bit 0 : An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU */
#define FPU_EVENTS_INEXACT_EVENTS_INEXACT_Pos (0UL) /*!< Position of EVENTS_INEXACT field. */
#define FPU_EVENTS_INEXACT_EVENTS_INEXACT_Msk (0x1UL << FPU_EVENTS_INEXACT_EVENTS_INEXACT_Pos) /*!< Bit mask of EVENTS_INEXACT field. */
#define FPU_EVENTS_INEXACT_EVENTS_INEXACT_NotGenerated (0x0UL) /*!< Event not generated */
#define FPU_EVENTS_INEXACT_EVENTS_INEXACT_Generated (0x1UL) /*!< Event generated */

/* Register: FPU_EVENTS_DENORMALINPUT */
/* Description: An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU */

/* Bit 0 : An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU */
#define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Pos (0UL) /*!< Position of EVENTS_DENORMALINPUT field. */
#define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Msk (0x1UL << FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Pos) /*!< Bit mask of EVENTS_DENORMALINPUT field. */
#define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_NotGenerated (0x0UL) /*!< Event not generated */
#define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Generated (0x1UL) /*!< Event generated */

/* Register: FPU_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 5 : Enable or disable interrupt for event DENORMALINPUT */
#define FPU_INTEN_DENORMALINPUT_Pos (5UL) /*!< Position of DENORMALINPUT field. */
#define FPU_INTEN_DENORMALINPUT_Msk (0x1UL << FPU_INTEN_DENORMALINPUT_Pos) /*!< Bit mask of DENORMALINPUT field. */
#define FPU_INTEN_DENORMALINPUT_Disabled (0x0UL) /*!< Disable */
#define FPU_INTEN_DENORMALINPUT_Enabled (0x1UL) /*!< Enable */

/* Bit 4 : Enable or disable interrupt for event INEXACT */
#define FPU_INTEN_INEXACT_Pos (4UL) /*!< Position of INEXACT field. */
#define FPU_INTEN_INEXACT_Msk (0x1UL << FPU_INTEN_INEXACT_Pos) /*!< Bit mask of INEXACT field. */
#define FPU_INTEN_INEXACT_Disabled (0x0UL) /*!< Disable */
#define FPU_INTEN_INEXACT_Enabled (0x1UL) /*!< Enable */

/* Bit 3 : Enable or disable interrupt for event UNDERFLOW */
#define FPU_INTEN_UNDERFLOW_Pos (3UL) /*!< Position of UNDERFLOW field. */
#define FPU_INTEN_UNDERFLOW_Msk (0x1UL << FPU_INTEN_UNDERFLOW_Pos) /*!< Bit mask of UNDERFLOW field. */
#define FPU_INTEN_UNDERFLOW_Disabled (0x0UL) /*!< Disable */
#define FPU_INTEN_UNDERFLOW_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event OVERFLOW */
#define FPU_INTEN_OVERFLOW_Pos (2UL) /*!< Position of OVERFLOW field. */
#define FPU_INTEN_OVERFLOW_Msk (0x1UL << FPU_INTEN_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
#define FPU_INTEN_OVERFLOW_Disabled (0x0UL) /*!< Disable */
#define FPU_INTEN_OVERFLOW_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event DIVIDEBYZERO */
#define FPU_INTEN_DIVIDEBYZERO_Pos (1UL) /*!< Position of DIVIDEBYZERO field. */
#define FPU_INTEN_DIVIDEBYZERO_Msk (0x1UL << FPU_INTEN_DIVIDEBYZERO_Pos) /*!< Bit mask of DIVIDEBYZERO field. */
#define FPU_INTEN_DIVIDEBYZERO_Disabled (0x0UL) /*!< Disable */
#define FPU_INTEN_DIVIDEBYZERO_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event INVALIDOPERATION */
#define FPU_INTEN_INVALIDOPERATION_Pos (0UL) /*!< Position of INVALIDOPERATION field. */
#define FPU_INTEN_INVALIDOPERATION_Msk (0x1UL << FPU_INTEN_INVALIDOPERATION_Pos) /*!< Bit mask of INVALIDOPERATION field. */
#define FPU_INTEN_INVALIDOPERATION_Disabled (0x0UL) /*!< Disable */
#define FPU_INTEN_INVALIDOPERATION_Enabled (0x1UL) /*!< Enable */

/* Register: FPU_INTENSET */
/* Description: Enable interrupt */

/* Bit 5 : Write '1' to enable interrupt for event DENORMALINPUT */
#define FPU_INTENSET_DENORMALINPUT_Pos (5UL) /*!< Position of DENORMALINPUT field. */
#define FPU_INTENSET_DENORMALINPUT_Msk (0x1UL << FPU_INTENSET_DENORMALINPUT_Pos) /*!< Bit mask of DENORMALINPUT field. */
#define FPU_INTENSET_DENORMALINPUT_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENSET_DENORMALINPUT_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENSET_DENORMALINPUT_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event INEXACT */
#define FPU_INTENSET_INEXACT_Pos (4UL) /*!< Position of INEXACT field. */
#define FPU_INTENSET_INEXACT_Msk (0x1UL << FPU_INTENSET_INEXACT_Pos) /*!< Bit mask of INEXACT field. */
#define FPU_INTENSET_INEXACT_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENSET_INEXACT_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENSET_INEXACT_Set (0x1UL) /*!< Enable */

/* Bit 3 : Write '1' to enable interrupt for event UNDERFLOW */
#define FPU_INTENSET_UNDERFLOW_Pos (3UL) /*!< Position of UNDERFLOW field. */
#define FPU_INTENSET_UNDERFLOW_Msk (0x1UL << FPU_INTENSET_UNDERFLOW_Pos) /*!< Bit mask of UNDERFLOW field. */
#define FPU_INTENSET_UNDERFLOW_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENSET_UNDERFLOW_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENSET_UNDERFLOW_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event OVERFLOW */
#define FPU_INTENSET_OVERFLOW_Pos (2UL) /*!< Position of OVERFLOW field. */
#define FPU_INTENSET_OVERFLOW_Msk (0x1UL << FPU_INTENSET_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
#define FPU_INTENSET_OVERFLOW_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENSET_OVERFLOW_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENSET_OVERFLOW_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event DIVIDEBYZERO */
#define FPU_INTENSET_DIVIDEBYZERO_Pos (1UL) /*!< Position of DIVIDEBYZERO field. */
#define FPU_INTENSET_DIVIDEBYZERO_Msk (0x1UL << FPU_INTENSET_DIVIDEBYZERO_Pos) /*!< Bit mask of DIVIDEBYZERO field. */
#define FPU_INTENSET_DIVIDEBYZERO_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENSET_DIVIDEBYZERO_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENSET_DIVIDEBYZERO_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event INVALIDOPERATION */
#define FPU_INTENSET_INVALIDOPERATION_Pos (0UL) /*!< Position of INVALIDOPERATION field. */
#define FPU_INTENSET_INVALIDOPERATION_Msk (0x1UL << FPU_INTENSET_INVALIDOPERATION_Pos) /*!< Bit mask of INVALIDOPERATION field. */
#define FPU_INTENSET_INVALIDOPERATION_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENSET_INVALIDOPERATION_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENSET_INVALIDOPERATION_Set (0x1UL) /*!< Enable */

/* Register: FPU_INTENCLR */
/* Description: Disable interrupt */

/* Bit 5 : Write '1' to disable interrupt for event DENORMALINPUT */
#define FPU_INTENCLR_DENORMALINPUT_Pos (5UL) /*!< Position of DENORMALINPUT field. */
#define FPU_INTENCLR_DENORMALINPUT_Msk (0x1UL << FPU_INTENCLR_DENORMALINPUT_Pos) /*!< Bit mask of DENORMALINPUT field. */
#define FPU_INTENCLR_DENORMALINPUT_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENCLR_DENORMALINPUT_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENCLR_DENORMALINPUT_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event INEXACT */
#define FPU_INTENCLR_INEXACT_Pos (4UL) /*!< Position of INEXACT field. */
#define FPU_INTENCLR_INEXACT_Msk (0x1UL << FPU_INTENCLR_INEXACT_Pos) /*!< Bit mask of INEXACT field. */
#define FPU_INTENCLR_INEXACT_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENCLR_INEXACT_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENCLR_INEXACT_Clear (0x1UL) /*!< Disable */

/* Bit 3 : Write '1' to disable interrupt for event UNDERFLOW */
#define FPU_INTENCLR_UNDERFLOW_Pos (3UL) /*!< Position of UNDERFLOW field. */
#define FPU_INTENCLR_UNDERFLOW_Msk (0x1UL << FPU_INTENCLR_UNDERFLOW_Pos) /*!< Bit mask of UNDERFLOW field. */
#define FPU_INTENCLR_UNDERFLOW_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENCLR_UNDERFLOW_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENCLR_UNDERFLOW_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event OVERFLOW */
#define FPU_INTENCLR_OVERFLOW_Pos (2UL) /*!< Position of OVERFLOW field. */
#define FPU_INTENCLR_OVERFLOW_Msk (0x1UL << FPU_INTENCLR_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
#define FPU_INTENCLR_OVERFLOW_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENCLR_OVERFLOW_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENCLR_OVERFLOW_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event DIVIDEBYZERO */
#define FPU_INTENCLR_DIVIDEBYZERO_Pos (1UL) /*!< Position of DIVIDEBYZERO field. */
#define FPU_INTENCLR_DIVIDEBYZERO_Msk (0x1UL << FPU_INTENCLR_DIVIDEBYZERO_Pos) /*!< Bit mask of DIVIDEBYZERO field. */
#define FPU_INTENCLR_DIVIDEBYZERO_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENCLR_DIVIDEBYZERO_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENCLR_DIVIDEBYZERO_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event INVALIDOPERATION */
#define FPU_INTENCLR_INVALIDOPERATION_Pos (0UL) /*!< Position of INVALIDOPERATION field. */
#define FPU_INTENCLR_INVALIDOPERATION_Msk (0x1UL << FPU_INTENCLR_INVALIDOPERATION_Pos) /*!< Bit mask of INVALIDOPERATION field. */
#define FPU_INTENCLR_INVALIDOPERATION_Disabled (0x0UL) /*!< Read: Disabled */
#define FPU_INTENCLR_INVALIDOPERATION_Enabled (0x1UL) /*!< Read: Enabled */
#define FPU_INTENCLR_INVALIDOPERATION_Clear (0x1UL) /*!< Disable */


/* Peripheral: GPIOTE */
/* Description: GPIO Tasks and Events 0 */

/* Register: GPIOTE_TASKS_OUT */
/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */

/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (0x1UL) /*!< Trigger task */

/* Register: GPIOTE_TASKS_SET */
/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */

/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (0x1UL) /*!< Trigger task */

/* Register: GPIOTE_TASKS_CLR */
/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */

/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (0x1UL) /*!< Trigger task */

/* Register: GPIOTE_SUBSCRIBE_OUT */
/* Description: Description collection: Subscribe configuration for task OUT[n] */

/* Bit 31 :   */
#define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */
#define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */
#define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0x0UL) /*!< Disable subscription */
#define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */
#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: GPIOTE_SUBSCRIBE_SET */
/* Description: Description collection: Subscribe configuration for task SET[n] */

/* Bit 31 :   */
#define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */
#define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */
#define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0x0UL) /*!< Disable subscription */
#define GPIOTE_SUBSCRIBE_SET_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */
#define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: GPIOTE_SUBSCRIBE_CLR */
/* Description: Description collection: Subscribe configuration for task CLR[n] */

/* Bit 31 :   */
#define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */
#define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */
#define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0x0UL) /*!< Disable subscription */
#define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */
#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: GPIOTE_EVENTS_IN */
/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */

/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0x0UL) /*!< Event not generated */
#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (0x1UL) /*!< Event generated */

/* Register: GPIOTE_EVENTS_PORT */
/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */

/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0x0UL) /*!< Event not generated */
#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (0x1UL) /*!< Event generated */

/* Register: GPIOTE_PUBLISH_IN */
/* Description: Description collection: Publish configuration for event IN[n] */

/* Bit 31 :   */
#define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */
#define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */
#define GPIOTE_PUBLISH_IN_EN_Disabled (0x0UL) /*!< Disable publishing */
#define GPIOTE_PUBLISH_IN_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event IN[n] will publish to */
#define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: GPIOTE_PUBLISH_PORT */
/* Description: Publish configuration for event PORT */

/* Bit 31 :   */
#define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */
#define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */
#define GPIOTE_PUBLISH_PORT_EN_Disabled (0x0UL) /*!< Disable publishing */
#define GPIOTE_PUBLISH_PORT_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event PORT will publish to */
#define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: GPIOTE_INTENSET */
/* Description: Enable interrupt */

/* Bit 31 : Write '1' to enable interrupt for event PORT */
#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
#define GPIOTE_INTENSET_PORT_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_PORT_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_PORT_Set (0x1UL) /*!< Enable */

/* Bit 7 : Write '1' to enable interrupt for event IN[7] */
#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
#define GPIOTE_INTENSET_IN7_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN7_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN7_Set (0x1UL) /*!< Enable */

/* Bit 6 : Write '1' to enable interrupt for event IN[6] */
#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
#define GPIOTE_INTENSET_IN6_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN6_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN6_Set (0x1UL) /*!< Enable */

/* Bit 5 : Write '1' to enable interrupt for event IN[5] */
#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
#define GPIOTE_INTENSET_IN5_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN5_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN5_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event IN[4] */
#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
#define GPIOTE_INTENSET_IN4_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN4_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN4_Set (0x1UL) /*!< Enable */

/* Bit 3 : Write '1' to enable interrupt for event IN[3] */
#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
#define GPIOTE_INTENSET_IN3_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN3_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN3_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event IN[2] */
#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
#define GPIOTE_INTENSET_IN2_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN2_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN2_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event IN[1] */
#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
#define GPIOTE_INTENSET_IN1_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN1_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN1_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event IN[0] */
#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
#define GPIOTE_INTENSET_IN0_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENSET_IN0_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENSET_IN0_Set (0x1UL) /*!< Enable */

/* Register: GPIOTE_INTENCLR */
/* Description: Disable interrupt */

/* Bit 31 : Write '1' to disable interrupt for event PORT */
#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
#define GPIOTE_INTENCLR_PORT_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_PORT_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_PORT_Clear (0x1UL) /*!< Disable */

/* Bit 7 : Write '1' to disable interrupt for event IN[7] */
#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
#define GPIOTE_INTENCLR_IN7_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN7_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN7_Clear (0x1UL) /*!< Disable */

/* Bit 6 : Write '1' to disable interrupt for event IN[6] */
#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
#define GPIOTE_INTENCLR_IN6_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN6_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN6_Clear (0x1UL) /*!< Disable */

/* Bit 5 : Write '1' to disable interrupt for event IN[5] */
#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
#define GPIOTE_INTENCLR_IN5_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN5_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN5_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event IN[4] */
#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
#define GPIOTE_INTENCLR_IN4_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN4_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN4_Clear (0x1UL) /*!< Disable */

/* Bit 3 : Write '1' to disable interrupt for event IN[3] */
#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
#define GPIOTE_INTENCLR_IN3_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN3_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN3_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event IN[2] */
#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
#define GPIOTE_INTENCLR_IN2_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN2_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN2_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event IN[1] */
#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
#define GPIOTE_INTENCLR_IN1_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN1_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN1_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event IN[0] */
#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
#define GPIOTE_INTENCLR_IN0_Disabled (0x0UL) /*!< Read: Disabled */
#define GPIOTE_INTENCLR_IN0_Enabled (0x1UL) /*!< Read: Enabled */
#define GPIOTE_INTENCLR_IN0_Clear (0x1UL) /*!< Disable */

/* Register: GPIOTE_LATENCY */
/* Description: Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. */

/* Bit 0 : Latency setting */
#define GPIOTE_LATENCY_LATENCY_Pos (0UL) /*!< Position of LATENCY field. */
#define GPIOTE_LATENCY_LATENCY_Msk (0x1UL << GPIOTE_LATENCY_LATENCY_Pos) /*!< Bit mask of LATENCY field. */
#define GPIOTE_LATENCY_LATENCY_LowPower (0x0UL) /*!< Low power setting */
#define GPIOTE_LATENCY_LATENCY_LowLatency (0x1UL) /*!< Low latency setting */

/* Register: GPIOTE_CONFIG */
/* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */

/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
#define GPIOTE_CONFIG_OUTINIT_Low (0x0UL) /*!< Task mode: Initial value of pin before task triggering is low */
#define GPIOTE_CONFIG_OUTINIT_High (0x1UL) /*!< Task mode: Initial value of pin before task triggering is high */

/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
#define GPIOTE_CONFIG_POLARITY_None (0x0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
#define GPIOTE_CONFIG_POLARITY_LoToHi (0x1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
#define GPIOTE_CONFIG_POLARITY_HiToLo (0x2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
#define GPIOTE_CONFIG_POLARITY_Toggle (0x3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */

/* Bit 13 : Port number */
#define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */
#define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */

/* Bits 1..0 : Mode */
#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
#define GPIOTE_CONFIG_MODE_Disabled (0x0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
#define GPIOTE_CONFIG_MODE_Event (0x1UL) /*!< Event mode */
#define GPIOTE_CONFIG_MODE_Task (0x3UL) /*!< Task mode */


/* Peripheral: I2S */
/* Description: Inter-IC Sound 0 */

/* Register: I2S_TASKS_START */
/* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled */

/* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled */
#define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define I2S_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */

/* Register: I2S_TASKS_STOP */
/* Description: Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. */

/* Bit 0 : Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. */
#define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define I2S_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: I2S_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */

/* Bit 31 :   */
#define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define I2S_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
#define I2S_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: I2S_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define I2S_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define I2S_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: I2S_EVENTS_RXPTRUPD */
/* Description: The RXD.PTR register has been copied to internal double-buffers.
      When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. */

/* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
      When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. */
#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */
#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (0x1UL) /*!< Event generated */

/* Register: I2S_EVENTS_STOPPED */
/* Description: I2S transfer stopped. */

/* Bit 0 : I2S transfer stopped. */
#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */

/* Register: I2S_EVENTS_TXPTRUPD */
/* Description: The TDX.PTR register has been copied to internal double-buffers.
      When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */

/* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
      When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */
#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (0x1UL) /*!< Event generated */

/* Register: I2S_EVENTS_FRAMESTART */
/* Description: Frame start event, generated on the active edge of LRCK */

/* Bit 0 : Frame start event, generated on the active edge of LRCK */
#define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */
#define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */
#define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */
#define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (0x1UL) /*!< Event generated */

/* Register: I2S_PUBLISH_RXPTRUPD */
/* Description: Publish configuration for event RXPTRUPD */

/* Bit 31 :   */
#define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
#define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
#define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */
#define I2S_PUBLISH_RXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to */
#define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: I2S_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */

/* Bit 31 :   */
#define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
#define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
#define I2S_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define I2S_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: I2S_PUBLISH_TXPTRUPD */
/* Description: Publish configuration for event TXPTRUPD */

/* Bit 31 :   */
#define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
#define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
#define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */
#define I2S_PUBLISH_TXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to */
#define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: I2S_PUBLISH_FRAMESTART */
/* Description: Publish configuration for event FRAMESTART */

/* Bit 31 :   */
#define I2S_PUBLISH_FRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */
#define I2S_PUBLISH_FRAMESTART_EN_Msk (0x1UL << I2S_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field. */
#define I2S_PUBLISH_FRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing */
#define I2S_PUBLISH_FRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event FRAMESTART will publish to */
#define I2S_PUBLISH_FRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define I2S_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << I2S_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: I2S_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 7 : Enable or disable interrupt for event FRAMESTART */
#define I2S_INTEN_FRAMESTART_Pos (7UL) /*!< Position of FRAMESTART field. */
#define I2S_INTEN_FRAMESTART_Msk (0x1UL << I2S_INTEN_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
#define I2S_INTEN_FRAMESTART_Disabled (0x0UL) /*!< Disable */
#define I2S_INTEN_FRAMESTART_Enabled (0x1UL) /*!< Enable */

/* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTEN_TXPTRUPD_Disabled (0x0UL) /*!< Disable */
#define I2S_INTEN_TXPTRUPD_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event STOPPED */
#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
#define I2S_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTEN_RXPTRUPD_Disabled (0x0UL) /*!< Disable */
#define I2S_INTEN_RXPTRUPD_Enabled (0x1UL) /*!< Enable */

/* Register: I2S_INTENSET */
/* Description: Enable interrupt */

/* Bit 7 : Write '1' to enable interrupt for event FRAMESTART */
#define I2S_INTENSET_FRAMESTART_Pos (7UL) /*!< Position of FRAMESTART field. */
#define I2S_INTENSET_FRAMESTART_Msk (0x1UL << I2S_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
#define I2S_INTENSET_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
#define I2S_INTENSET_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
#define I2S_INTENSET_FRAMESTART_Set (0x1UL) /*!< Enable */

/* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTENSET_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
#define I2S_INTENSET_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
#define I2S_INTENSET_TXPTRUPD_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event STOPPED */
#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define I2S_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define I2S_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTENSET_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
#define I2S_INTENSET_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
#define I2S_INTENSET_RXPTRUPD_Set (0x1UL) /*!< Enable */

/* Register: I2S_INTENCLR */
/* Description: Disable interrupt */

/* Bit 7 : Write '1' to disable interrupt for event FRAMESTART */
#define I2S_INTENCLR_FRAMESTART_Pos (7UL) /*!< Position of FRAMESTART field. */
#define I2S_INTENCLR_FRAMESTART_Msk (0x1UL << I2S_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
#define I2S_INTENCLR_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_FRAMESTART_Clear (0x1UL) /*!< Disable */

/* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
#define I2S_INTENCLR_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_TXPTRUPD_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event STOPPED */
#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define I2S_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
#define I2S_INTENCLR_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */
#define I2S_INTENCLR_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */
#define I2S_INTENCLR_RXPTRUPD_Clear (0x1UL) /*!< Disable */

/* Register: I2S_ENABLE */
/* Description: Enable I2S module */

/* Bit 0 : Enable I2S module */
#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define I2S_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
#define I2S_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */

/* Register: I2S_CONFIG_MODE */
/* Description: I2S mode */

/* Bit 0 : I2S mode */
#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define I2S_CONFIG_MODE_MODE_Master (0x0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
#define I2S_CONFIG_MODE_MODE_Slave (0x1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */

/* Register: I2S_CONFIG_RXEN */
/* Description: Reception (RX) enable */

/* Bit 0 : Reception (RX) enable */
#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
#define I2S_CONFIG_RXEN_RXEN_Disabled (0x0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
#define I2S_CONFIG_RXEN_RXEN_Enabled (0x1UL) /*!< Reception enabled. */

/* Register: I2S_CONFIG_TXEN */
/* Description: Transmission (TX) enable */

/* Bit 0 : Transmission (TX) enable */
#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
#define I2S_CONFIG_TXEN_TXEN_Disabled (0x0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
#define I2S_CONFIG_TXEN_TXEN_Enabled (0x1UL) /*!< Transmission enabled. */

/* Register: I2S_CONFIG_MCKEN */
/* Description: Master clock generator enable */

/* Bit 0 : Master clock generator enable */
#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0x0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
#define I2S_CONFIG_MCKEN_MCKEN_Enabled (0x1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */

/* Register: I2S_CONFIG_MCKFREQ */
/* Description: I2S clock generator control */

/* Bits 31..0 : I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. */
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. */

/* Register: I2S_CONFIG_RATIO */
/* Description: MCK / LRCK ratio */

/* Bits 3..0 : MCK / LRCK ratio */
#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
#define I2S_CONFIG_RATIO_RATIO_32X (0x0UL) /*!< LRCK = MCK / 32 */
#define I2S_CONFIG_RATIO_RATIO_48X (0x1UL) /*!< LRCK = MCK / 48 */
#define I2S_CONFIG_RATIO_RATIO_64X (0x2UL) /*!< LRCK = MCK / 64 */
#define I2S_CONFIG_RATIO_RATIO_96X (0x3UL) /*!< LRCK = MCK / 96 */
#define I2S_CONFIG_RATIO_RATIO_128X (0x4UL) /*!< LRCK = MCK / 128 */
#define I2S_CONFIG_RATIO_RATIO_192X (0x5UL) /*!< LRCK = MCK / 192 */
#define I2S_CONFIG_RATIO_RATIO_256X (0x6UL) /*!< LRCK = MCK / 256 */
#define I2S_CONFIG_RATIO_RATIO_384X (0x7UL) /*!< LRCK = MCK / 384 */
#define I2S_CONFIG_RATIO_RATIO_512X (0x8UL) /*!< LRCK = MCK / 512 */

/* Register: I2S_CONFIG_SWIDTH */
/* Description: Sample width */

/* Bits 2..0 : Sample and half-frame width */
#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x7UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0x0UL) /*!< 8 bit sample. */
#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (0x1UL) /*!< 16 bit sample. */
#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (0x2UL) /*!< 24 bit sample. */
#define I2S_CONFIG_SWIDTH_SWIDTH_32Bit (0x3UL) /*!< 32 bit sample. */
#define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16 (0x4UL) /*!< 8 bit sample in a 16-bit half-frame. */
#define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32 (0x5UL) /*!< 8 bit sample in a 32-bit half-frame. */
#define I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32 (0x6UL) /*!< 16 bit sample in a 32-bit half-frame. */
#define I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32 (0x7UL) /*!< 24 bit sample in a 32-bit half-frame. */

/* Register: I2S_CONFIG_ALIGN */
/* Description: Alignment of sample within a frame */

/* Bit 0 : Alignment of sample within a frame */
#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
#define I2S_CONFIG_ALIGN_ALIGN_Left (0x0UL) /*!< Left-aligned. */
#define I2S_CONFIG_ALIGN_ALIGN_Right (0x1UL) /*!< Right-aligned. */

/* Register: I2S_CONFIG_FORMAT */
/* Description: Frame format */

/* Bit 0 : Frame format */
#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
#define I2S_CONFIG_FORMAT_FORMAT_I2S (0x0UL) /*!< Original I2S format. */
#define I2S_CONFIG_FORMAT_FORMAT_Aligned (0x1UL) /*!< Alternate (left- or right-aligned) format. */

/* Register: I2S_CONFIG_CHANNELS */
/* Description: Enable channels */

/* Bits 1..0 : Enable channels */
#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0x0UL) /*!< Stereo. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Left (0x1UL) /*!< Left only. */
#define I2S_CONFIG_CHANNELS_CHANNELS_Right (0x2UL) /*!< Right only. */

/* Register: I2S_CONFIG_CLKCONFIG */
/* Description: Clock source selection for the I2S module */

/* Bit 8 : Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. */
#define I2S_CONFIG_CLKCONFIG_BYPASS_Pos (8UL) /*!< Position of BYPASS field. */
#define I2S_CONFIG_CLKCONFIG_BYPASS_Msk (0x1UL << I2S_CONFIG_CLKCONFIG_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
#define I2S_CONFIG_CLKCONFIG_BYPASS_Disable (0x0UL) /*!< Disable bypass */
#define I2S_CONFIG_CLKCONFIG_BYPASS_Enable (0x1UL) /*!< Enable bypass */

/* Bit 0 : Clock source selection */
#define I2S_CONFIG_CLKCONFIG_CLKSRC_Pos (0UL) /*!< Position of CLKSRC field. */
#define I2S_CONFIG_CLKCONFIG_CLKSRC_Msk (0x1UL << I2S_CONFIG_CLKCONFIG_CLKSRC_Pos) /*!< Bit mask of CLKSRC field. */
#define I2S_CONFIG_CLKCONFIG_CLKSRC_PCLK32M (0x0UL) /*!< 32MHz peripheral clock */
#define I2S_CONFIG_CLKCONFIG_CLKSRC_ACLK (0x1UL) /*!< Audio PLL clock */

/* Register: I2S_RXD_PTR */
/* Description: Receive buffer RAM start address. */

/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: I2S_TXD_PTR */
/* Description: Transmit buffer RAM start address */

/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: I2S_RXTXD_MAXCNT */
/* Description: Size of RXD and TXD buffers */

/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words */
#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: I2S_PSEL_MCK */
/* Description: Pin select for MCK signal */

/* Bit 31 : Connection */
#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_MCK_CONNECT_Connected (0x0UL) /*!< Connect */
#define I2S_PSEL_MCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define I2S_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */
#define I2S_PSEL_MCK_PORT_Msk (0x1UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: I2S_PSEL_SCK */
/* Description: Pin select for SCK signal */

/* Bit 31 : Connection */
#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
#define I2S_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define I2S_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
#define I2S_PSEL_SCK_PORT_Msk (0x1UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: I2S_PSEL_LRCK */
/* Description: Pin select for LRCK signal */

/* Bit 31 : Connection */
#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_LRCK_CONNECT_Connected (0x0UL) /*!< Connect */
#define I2S_PSEL_LRCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define I2S_PSEL_LRCK_PORT_Pos (5UL) /*!< Position of PORT field. */
#define I2S_PSEL_LRCK_PORT_Msk (0x1UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: I2S_PSEL_SDIN */
/* Description: Pin select for SDIN signal */

/* Bit 31 : Connection */
#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_SDIN_CONNECT_Connected (0x0UL) /*!< Connect */
#define I2S_PSEL_SDIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define I2S_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */
#define I2S_PSEL_SDIN_PORT_Msk (0x1UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: I2S_PSEL_SDOUT */
/* Description: Pin select for SDOUT signal */

/* Bit 31 : Connection */
#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define I2S_PSEL_SDOUT_CONNECT_Connected (0x0UL) /*!< Connect */
#define I2S_PSEL_SDOUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define I2S_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */
#define I2S_PSEL_SDOUT_PORT_Msk (0x1UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */


/* Peripheral: IPC */
/* Description: Interprocessor communication 0 */

/* Register: IPC_TASKS_SEND */
/* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */

/* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */
#define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */
#define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */
#define IPC_TASKS_SEND_TASKS_SEND_Trigger (0x1UL) /*!< Trigger task */

/* Register: IPC_SUBSCRIBE_SEND */
/* Description: Description collection: Subscribe configuration for task SEND[n] */

/* Bit 31 :   */
#define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */
#define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */
#define IPC_SUBSCRIBE_SEND_EN_Disabled (0x0UL) /*!< Disable subscription */
#define IPC_SUBSCRIBE_SEND_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */
#define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: IPC_EVENTS_RECEIVE */
/* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */

/* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */
#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */
#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0x0UL) /*!< Event not generated */
#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (0x1UL) /*!< Event generated */

/* Register: IPC_PUBLISH_RECEIVE */
/* Description: Description collection: Publish configuration for event RECEIVE[n] */

/* Bit 31 :   */
#define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */
#define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */
#define IPC_PUBLISH_RECEIVE_EN_Disabled (0x0UL) /*!< Disable publishing */
#define IPC_PUBLISH_RECEIVE_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to */
#define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: IPC_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
#define IPC_INTEN_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
#define IPC_INTEN_RECEIVE15_Msk (0x1UL << IPC_INTEN_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
#define IPC_INTEN_RECEIVE15_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE15_Enabled (0x1UL) /*!< Enable */

/* Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
#define IPC_INTEN_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
#define IPC_INTEN_RECEIVE14_Msk (0x1UL << IPC_INTEN_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
#define IPC_INTEN_RECEIVE14_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE14_Enabled (0x1UL) /*!< Enable */

/* Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
#define IPC_INTEN_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
#define IPC_INTEN_RECEIVE13_Msk (0x1UL << IPC_INTEN_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
#define IPC_INTEN_RECEIVE13_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE13_Enabled (0x1UL) /*!< Enable */

/* Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
#define IPC_INTEN_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
#define IPC_INTEN_RECEIVE12_Msk (0x1UL << IPC_INTEN_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
#define IPC_INTEN_RECEIVE12_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE12_Enabled (0x1UL) /*!< Enable */

/* Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
#define IPC_INTEN_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
#define IPC_INTEN_RECEIVE11_Msk (0x1UL << IPC_INTEN_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
#define IPC_INTEN_RECEIVE11_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE11_Enabled (0x1UL) /*!< Enable */

/* Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
#define IPC_INTEN_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
#define IPC_INTEN_RECEIVE10_Msk (0x1UL << IPC_INTEN_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
#define IPC_INTEN_RECEIVE10_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE10_Enabled (0x1UL) /*!< Enable */

/* Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
#define IPC_INTEN_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
#define IPC_INTEN_RECEIVE9_Msk (0x1UL << IPC_INTEN_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
#define IPC_INTEN_RECEIVE9_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE9_Enabled (0x1UL) /*!< Enable */

/* Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
#define IPC_INTEN_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
#define IPC_INTEN_RECEIVE8_Msk (0x1UL << IPC_INTEN_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
#define IPC_INTEN_RECEIVE8_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE8_Enabled (0x1UL) /*!< Enable */

/* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
#define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
#define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
#define IPC_INTEN_RECEIVE7_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE7_Enabled (0x1UL) /*!< Enable */

/* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
#define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
#define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
#define IPC_INTEN_RECEIVE6_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE6_Enabled (0x1UL) /*!< Enable */

/* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
#define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
#define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
#define IPC_INTEN_RECEIVE5_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE5_Enabled (0x1UL) /*!< Enable */

/* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
#define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
#define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
#define IPC_INTEN_RECEIVE4_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE4_Enabled (0x1UL) /*!< Enable */

/* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
#define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
#define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
#define IPC_INTEN_RECEIVE3_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE3_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
#define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
#define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
#define IPC_INTEN_RECEIVE2_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE2_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
#define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
#define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
#define IPC_INTEN_RECEIVE1_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE1_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
#define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
#define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
#define IPC_INTEN_RECEIVE0_Disabled (0x0UL) /*!< Disable */
#define IPC_INTEN_RECEIVE0_Enabled (0x1UL) /*!< Enable */

/* Register: IPC_INTENSET */
/* Description: Enable interrupt */

/* Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
#define IPC_INTENSET_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
#define IPC_INTENSET_RECEIVE15_Msk (0x1UL << IPC_INTENSET_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
#define IPC_INTENSET_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE15_Set (0x1UL) /*!< Enable */

/* Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
#define IPC_INTENSET_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
#define IPC_INTENSET_RECEIVE14_Msk (0x1UL << IPC_INTENSET_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
#define IPC_INTENSET_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE14_Set (0x1UL) /*!< Enable */

/* Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
#define IPC_INTENSET_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
#define IPC_INTENSET_RECEIVE13_Msk (0x1UL << IPC_INTENSET_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
#define IPC_INTENSET_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE13_Set (0x1UL) /*!< Enable */

/* Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
#define IPC_INTENSET_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
#define IPC_INTENSET_RECEIVE12_Msk (0x1UL << IPC_INTENSET_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
#define IPC_INTENSET_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE12_Set (0x1UL) /*!< Enable */

/* Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
#define IPC_INTENSET_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
#define IPC_INTENSET_RECEIVE11_Msk (0x1UL << IPC_INTENSET_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
#define IPC_INTENSET_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE11_Set (0x1UL) /*!< Enable */

/* Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
#define IPC_INTENSET_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
#define IPC_INTENSET_RECEIVE10_Msk (0x1UL << IPC_INTENSET_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
#define IPC_INTENSET_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE10_Set (0x1UL) /*!< Enable */

/* Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
#define IPC_INTENSET_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
#define IPC_INTENSET_RECEIVE9_Msk (0x1UL << IPC_INTENSET_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
#define IPC_INTENSET_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE9_Set (0x1UL) /*!< Enable */

/* Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
#define IPC_INTENSET_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
#define IPC_INTENSET_RECEIVE8_Msk (0x1UL << IPC_INTENSET_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
#define IPC_INTENSET_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE8_Set (0x1UL) /*!< Enable */

/* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
#define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
#define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
#define IPC_INTENSET_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE7_Set (0x1UL) /*!< Enable */

/* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
#define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
#define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
#define IPC_INTENSET_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE6_Set (0x1UL) /*!< Enable */

/* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
#define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
#define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
#define IPC_INTENSET_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE5_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
#define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
#define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
#define IPC_INTENSET_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE4_Set (0x1UL) /*!< Enable */

/* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
#define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
#define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
#define IPC_INTENSET_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE3_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
#define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
#define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
#define IPC_INTENSET_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE2_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
#define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
#define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
#define IPC_INTENSET_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE1_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
#define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
#define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
#define IPC_INTENSET_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENSET_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENSET_RECEIVE0_Set (0x1UL) /*!< Enable */

/* Register: IPC_INTENCLR */
/* Description: Disable interrupt */

/* Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
#define IPC_INTENCLR_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
#define IPC_INTENCLR_RECEIVE15_Msk (0x1UL << IPC_INTENCLR_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
#define IPC_INTENCLR_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE15_Clear (0x1UL) /*!< Disable */

/* Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
#define IPC_INTENCLR_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
#define IPC_INTENCLR_RECEIVE14_Msk (0x1UL << IPC_INTENCLR_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
#define IPC_INTENCLR_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE14_Clear (0x1UL) /*!< Disable */

/* Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
#define IPC_INTENCLR_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
#define IPC_INTENCLR_RECEIVE13_Msk (0x1UL << IPC_INTENCLR_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
#define IPC_INTENCLR_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE13_Clear (0x1UL) /*!< Disable */

/* Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
#define IPC_INTENCLR_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
#define IPC_INTENCLR_RECEIVE12_Msk (0x1UL << IPC_INTENCLR_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
#define IPC_INTENCLR_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE12_Clear (0x1UL) /*!< Disable */

/* Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
#define IPC_INTENCLR_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
#define IPC_INTENCLR_RECEIVE11_Msk (0x1UL << IPC_INTENCLR_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
#define IPC_INTENCLR_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE11_Clear (0x1UL) /*!< Disable */

/* Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
#define IPC_INTENCLR_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
#define IPC_INTENCLR_RECEIVE10_Msk (0x1UL << IPC_INTENCLR_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
#define IPC_INTENCLR_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE10_Clear (0x1UL) /*!< Disable */

/* Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
#define IPC_INTENCLR_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
#define IPC_INTENCLR_RECEIVE9_Msk (0x1UL << IPC_INTENCLR_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
#define IPC_INTENCLR_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE9_Clear (0x1UL) /*!< Disable */

/* Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
#define IPC_INTENCLR_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
#define IPC_INTENCLR_RECEIVE8_Msk (0x1UL << IPC_INTENCLR_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
#define IPC_INTENCLR_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE8_Clear (0x1UL) /*!< Disable */

/* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
#define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
#define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
#define IPC_INTENCLR_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE7_Clear (0x1UL) /*!< Disable */

/* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
#define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
#define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
#define IPC_INTENCLR_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE6_Clear (0x1UL) /*!< Disable */

/* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
#define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
#define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
#define IPC_INTENCLR_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE5_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
#define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
#define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
#define IPC_INTENCLR_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE4_Clear (0x1UL) /*!< Disable */

/* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
#define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
#define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
#define IPC_INTENCLR_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE3_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
#define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
#define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
#define IPC_INTENCLR_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE2_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
#define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
#define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
#define IPC_INTENCLR_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE1_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
#define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
#define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
#define IPC_INTENCLR_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */
#define IPC_INTENCLR_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */
#define IPC_INTENCLR_RECEIVE0_Clear (0x1UL) /*!< Disable */

/* Register: IPC_INTPEND */
/* Description: Pending interrupts */

/* Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
#define IPC_INTPEND_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
#define IPC_INTPEND_RECEIVE15_Msk (0x1UL << IPC_INTPEND_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
#define IPC_INTPEND_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE15_Pending (0x1UL) /*!< Read: Pending */

/* Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
#define IPC_INTPEND_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
#define IPC_INTPEND_RECEIVE14_Msk (0x1UL << IPC_INTPEND_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
#define IPC_INTPEND_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE14_Pending (0x1UL) /*!< Read: Pending */

/* Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
#define IPC_INTPEND_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
#define IPC_INTPEND_RECEIVE13_Msk (0x1UL << IPC_INTPEND_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
#define IPC_INTPEND_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE13_Pending (0x1UL) /*!< Read: Pending */

/* Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
#define IPC_INTPEND_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
#define IPC_INTPEND_RECEIVE12_Msk (0x1UL << IPC_INTPEND_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
#define IPC_INTPEND_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE12_Pending (0x1UL) /*!< Read: Pending */

/* Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
#define IPC_INTPEND_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
#define IPC_INTPEND_RECEIVE11_Msk (0x1UL << IPC_INTPEND_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
#define IPC_INTPEND_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE11_Pending (0x1UL) /*!< Read: Pending */

/* Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
#define IPC_INTPEND_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
#define IPC_INTPEND_RECEIVE10_Msk (0x1UL << IPC_INTPEND_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
#define IPC_INTPEND_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE10_Pending (0x1UL) /*!< Read: Pending */

/* Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
#define IPC_INTPEND_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
#define IPC_INTPEND_RECEIVE9_Msk (0x1UL << IPC_INTPEND_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
#define IPC_INTPEND_RECEIVE9_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE9_Pending (0x1UL) /*!< Read: Pending */

/* Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
#define IPC_INTPEND_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
#define IPC_INTPEND_RECEIVE8_Msk (0x1UL << IPC_INTPEND_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
#define IPC_INTPEND_RECEIVE8_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE8_Pending (0x1UL) /*!< Read: Pending */

/* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
#define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
#define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
#define IPC_INTPEND_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */

/* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
#define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
#define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
#define IPC_INTPEND_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */

/* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
#define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
#define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
#define IPC_INTPEND_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */

/* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
#define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
#define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
#define IPC_INTPEND_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */

/* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
#define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
#define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
#define IPC_INTPEND_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */

/* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
#define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
#define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
#define IPC_INTPEND_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */

/* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
#define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
#define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
#define IPC_INTPEND_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */

/* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
#define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
#define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
#define IPC_INTPEND_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */
#define IPC_INTPEND_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */

/* Register: IPC_SEND_CNF */
/* Description: Description collection: Send event configuration for TASKS_SEND[n] */

/* Bit 15 : Enable broadcasting on IPC channel 15 */
#define IPC_SEND_CNF_CHEN15_Pos (15UL) /*!< Position of CHEN15 field. */
#define IPC_SEND_CNF_CHEN15_Msk (0x1UL << IPC_SEND_CNF_CHEN15_Pos) /*!< Bit mask of CHEN15 field. */
#define IPC_SEND_CNF_CHEN15_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN15_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 14 : Enable broadcasting on IPC channel 14 */
#define IPC_SEND_CNF_CHEN14_Pos (14UL) /*!< Position of CHEN14 field. */
#define IPC_SEND_CNF_CHEN14_Msk (0x1UL << IPC_SEND_CNF_CHEN14_Pos) /*!< Bit mask of CHEN14 field. */
#define IPC_SEND_CNF_CHEN14_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN14_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 13 : Enable broadcasting on IPC channel 13 */
#define IPC_SEND_CNF_CHEN13_Pos (13UL) /*!< Position of CHEN13 field. */
#define IPC_SEND_CNF_CHEN13_Msk (0x1UL << IPC_SEND_CNF_CHEN13_Pos) /*!< Bit mask of CHEN13 field. */
#define IPC_SEND_CNF_CHEN13_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN13_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 12 : Enable broadcasting on IPC channel 12 */
#define IPC_SEND_CNF_CHEN12_Pos (12UL) /*!< Position of CHEN12 field. */
#define IPC_SEND_CNF_CHEN12_Msk (0x1UL << IPC_SEND_CNF_CHEN12_Pos) /*!< Bit mask of CHEN12 field. */
#define IPC_SEND_CNF_CHEN12_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN12_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 11 : Enable broadcasting on IPC channel 11 */
#define IPC_SEND_CNF_CHEN11_Pos (11UL) /*!< Position of CHEN11 field. */
#define IPC_SEND_CNF_CHEN11_Msk (0x1UL << IPC_SEND_CNF_CHEN11_Pos) /*!< Bit mask of CHEN11 field. */
#define IPC_SEND_CNF_CHEN11_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN11_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 10 : Enable broadcasting on IPC channel 10 */
#define IPC_SEND_CNF_CHEN10_Pos (10UL) /*!< Position of CHEN10 field. */
#define IPC_SEND_CNF_CHEN10_Msk (0x1UL << IPC_SEND_CNF_CHEN10_Pos) /*!< Bit mask of CHEN10 field. */
#define IPC_SEND_CNF_CHEN10_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN10_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 9 : Enable broadcasting on IPC channel 9 */
#define IPC_SEND_CNF_CHEN9_Pos (9UL) /*!< Position of CHEN9 field. */
#define IPC_SEND_CNF_CHEN9_Msk (0x1UL << IPC_SEND_CNF_CHEN9_Pos) /*!< Bit mask of CHEN9 field. */
#define IPC_SEND_CNF_CHEN9_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN9_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 8 : Enable broadcasting on IPC channel 8 */
#define IPC_SEND_CNF_CHEN8_Pos (8UL) /*!< Position of CHEN8 field. */
#define IPC_SEND_CNF_CHEN8_Msk (0x1UL << IPC_SEND_CNF_CHEN8_Pos) /*!< Bit mask of CHEN8 field. */
#define IPC_SEND_CNF_CHEN8_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN8_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 7 : Enable broadcasting on IPC channel 7 */
#define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
#define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
#define IPC_SEND_CNF_CHEN7_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN7_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 6 : Enable broadcasting on IPC channel 6 */
#define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
#define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
#define IPC_SEND_CNF_CHEN6_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN6_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 5 : Enable broadcasting on IPC channel 5 */
#define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
#define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
#define IPC_SEND_CNF_CHEN5_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN5_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 4 : Enable broadcasting on IPC channel 4 */
#define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
#define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
#define IPC_SEND_CNF_CHEN4_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN4_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 3 : Enable broadcasting on IPC channel 3 */
#define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
#define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
#define IPC_SEND_CNF_CHEN3_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN3_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 2 : Enable broadcasting on IPC channel 2 */
#define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
#define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
#define IPC_SEND_CNF_CHEN2_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN2_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 1 : Enable broadcasting on IPC channel 1 */
#define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
#define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
#define IPC_SEND_CNF_CHEN1_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN1_Enable (0x1UL) /*!< Enable broadcast */

/* Bit 0 : Enable broadcasting on IPC channel 0 */
#define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
#define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
#define IPC_SEND_CNF_CHEN0_Disable (0x0UL) /*!< Disable broadcast */
#define IPC_SEND_CNF_CHEN0_Enable (0x1UL) /*!< Enable broadcast */

/* Register: IPC_RECEIVE_CNF */
/* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */

/* Bit 15 : Enable subscription to IPC channel 15 */
#define IPC_RECEIVE_CNF_CHEN15_Pos (15UL) /*!< Position of CHEN15 field. */
#define IPC_RECEIVE_CNF_CHEN15_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN15_Pos) /*!< Bit mask of CHEN15 field. */
#define IPC_RECEIVE_CNF_CHEN15_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN15_Enable (0x1UL) /*!< Enable events */

/* Bit 14 : Enable subscription to IPC channel 14 */
#define IPC_RECEIVE_CNF_CHEN14_Pos (14UL) /*!< Position of CHEN14 field. */
#define IPC_RECEIVE_CNF_CHEN14_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN14_Pos) /*!< Bit mask of CHEN14 field. */
#define IPC_RECEIVE_CNF_CHEN14_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN14_Enable (0x1UL) /*!< Enable events */

/* Bit 13 : Enable subscription to IPC channel 13 */
#define IPC_RECEIVE_CNF_CHEN13_Pos (13UL) /*!< Position of CHEN13 field. */
#define IPC_RECEIVE_CNF_CHEN13_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN13_Pos) /*!< Bit mask of CHEN13 field. */
#define IPC_RECEIVE_CNF_CHEN13_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN13_Enable (0x1UL) /*!< Enable events */

/* Bit 12 : Enable subscription to IPC channel 12 */
#define IPC_RECEIVE_CNF_CHEN12_Pos (12UL) /*!< Position of CHEN12 field. */
#define IPC_RECEIVE_CNF_CHEN12_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN12_Pos) /*!< Bit mask of CHEN12 field. */
#define IPC_RECEIVE_CNF_CHEN12_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN12_Enable (0x1UL) /*!< Enable events */

/* Bit 11 : Enable subscription to IPC channel 11 */
#define IPC_RECEIVE_CNF_CHEN11_Pos (11UL) /*!< Position of CHEN11 field. */
#define IPC_RECEIVE_CNF_CHEN11_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN11_Pos) /*!< Bit mask of CHEN11 field. */
#define IPC_RECEIVE_CNF_CHEN11_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN11_Enable (0x1UL) /*!< Enable events */

/* Bit 10 : Enable subscription to IPC channel 10 */
#define IPC_RECEIVE_CNF_CHEN10_Pos (10UL) /*!< Position of CHEN10 field. */
#define IPC_RECEIVE_CNF_CHEN10_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN10_Pos) /*!< Bit mask of CHEN10 field. */
#define IPC_RECEIVE_CNF_CHEN10_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN10_Enable (0x1UL) /*!< Enable events */

/* Bit 9 : Enable subscription to IPC channel 9 */
#define IPC_RECEIVE_CNF_CHEN9_Pos (9UL) /*!< Position of CHEN9 field. */
#define IPC_RECEIVE_CNF_CHEN9_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN9_Pos) /*!< Bit mask of CHEN9 field. */
#define IPC_RECEIVE_CNF_CHEN9_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN9_Enable (0x1UL) /*!< Enable events */

/* Bit 8 : Enable subscription to IPC channel 8 */
#define IPC_RECEIVE_CNF_CHEN8_Pos (8UL) /*!< Position of CHEN8 field. */
#define IPC_RECEIVE_CNF_CHEN8_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN8_Pos) /*!< Bit mask of CHEN8 field. */
#define IPC_RECEIVE_CNF_CHEN8_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN8_Enable (0x1UL) /*!< Enable events */

/* Bit 7 : Enable subscription to IPC channel 7 */
#define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
#define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
#define IPC_RECEIVE_CNF_CHEN7_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN7_Enable (0x1UL) /*!< Enable events */

/* Bit 6 : Enable subscription to IPC channel 6 */
#define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
#define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
#define IPC_RECEIVE_CNF_CHEN6_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN6_Enable (0x1UL) /*!< Enable events */

/* Bit 5 : Enable subscription to IPC channel 5 */
#define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
#define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
#define IPC_RECEIVE_CNF_CHEN5_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN5_Enable (0x1UL) /*!< Enable events */

/* Bit 4 : Enable subscription to IPC channel 4 */
#define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
#define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
#define IPC_RECEIVE_CNF_CHEN4_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN4_Enable (0x1UL) /*!< Enable events */

/* Bit 3 : Enable subscription to IPC channel 3 */
#define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
#define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
#define IPC_RECEIVE_CNF_CHEN3_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN3_Enable (0x1UL) /*!< Enable events */

/* Bit 2 : Enable subscription to IPC channel 2 */
#define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
#define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
#define IPC_RECEIVE_CNF_CHEN2_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN2_Enable (0x1UL) /*!< Enable events */

/* Bit 1 : Enable subscription to IPC channel 1 */
#define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
#define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
#define IPC_RECEIVE_CNF_CHEN1_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN1_Enable (0x1UL) /*!< Enable events */

/* Bit 0 : Enable subscription to IPC channel 0 */
#define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
#define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
#define IPC_RECEIVE_CNF_CHEN0_Disable (0x0UL) /*!< Disable events */
#define IPC_RECEIVE_CNF_CHEN0_Enable (0x1UL) /*!< Enable events */

/* Register: IPC_GPMEM */
/* Description: Description collection: General purpose memory */

/* Bits 31..0 : General purpose memory */
#define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */
#define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos) /*!< Bit mask of GPMEM field. */


/* Peripheral: KMU */
/* Description: Key management unit 0 */

/* Register: KMU_TASKS_PUSH_KEYSLOT */
/* Description: Push a key slot over secure APB */

/* Bit 0 : Push a key slot over secure APB */
#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL) /*!< Position of TASKS_PUSH_KEYSLOT field. */
#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos) /*!< Bit mask of TASKS_PUSH_KEYSLOT field. */
#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (0x1UL) /*!< Trigger task */

/* Register: KMU_EVENTS_KEYSLOT_PUSHED */
/* Description: Key slot successfully pushed over secure APB */

/* Bit 0 : Key slot successfully pushed over secure APB */
#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */
#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */
#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0x0UL) /*!< Event not generated */
#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (0x1UL) /*!< Event generated */

/* Register: KMU_EVENTS_KEYSLOT_REVOKED */
/* Description: Key slot has been revoked and cannot be tasked for selection */

/* Bit 0 : Key slot has been revoked and cannot be tasked for selection */
#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */
#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */
#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0x0UL) /*!< Event not generated */
#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (0x1UL) /*!< Event generated */

/* Register: KMU_EVENTS_KEYSLOT_ERROR */
/* Description: No key slot selected, no destination address defined, or error during push operation */

/* Bit 0 : No key slot selected, no destination address defined, or error during push operation */
#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_ERROR field. */
#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos) /*!< Bit mask of EVENTS_KEYSLOT_ERROR field. */
#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (0x1UL) /*!< Event generated */

/* Register: KMU_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */
#define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
#define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
#define KMU_INTEN_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Disable */
#define KMU_INTEN_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */
#define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
#define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
#define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Disable */
#define KMU_INTEN_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */
#define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
#define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
#define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Disable */
#define KMU_INTEN_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Enable */

/* Register: KMU_INTENSET */
/* Description: Enable interrupt */

/* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */
#define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
#define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
#define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define KMU_INTENSET_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define KMU_INTENSET_KEYSLOT_ERROR_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */
#define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
#define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
#define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Read: Disabled */
#define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Read: Enabled */
#define KMU_INTENSET_KEYSLOT_REVOKED_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */
#define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
#define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
#define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Read: Disabled */
#define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Read: Enabled */
#define KMU_INTENSET_KEYSLOT_PUSHED_Set (0x1UL) /*!< Enable */

/* Register: KMU_INTENCLR */
/* Description: Disable interrupt */

/* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */
#define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
#define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
#define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define KMU_INTENCLR_KEYSLOT_ERROR_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */
#define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
#define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
#define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Read: Disabled */
#define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Read: Enabled */
#define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */
#define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
#define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
#define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Read: Disabled */
#define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Read: Enabled */
#define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (0x1UL) /*!< Disable */

/* Register: KMU_INTPEND */
/* Description: Pending interrupts */

/* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */
#define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
#define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
#define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0x0UL) /*!< Read: Not pending */
#define KMU_INTPEND_KEYSLOT_ERROR_Pending (0x1UL) /*!< Read: Pending */

/* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */
#define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
#define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
#define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0x0UL) /*!< Read: Not pending */
#define KMU_INTPEND_KEYSLOT_REVOKED_Pending (0x1UL) /*!< Read: Pending */

/* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */
#define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
#define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
#define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0x0UL) /*!< Read: Not pending */
#define KMU_INTPEND_KEYSLOT_PUSHED_Pending (0x1UL) /*!< Read: Pending */

/* Register: KMU_STATUS */
/* Description: Status bits for KMU operation */

/* Bit 1 : Violation status */
#define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */
#define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos) /*!< Bit mask of BLOCKED field. */
#define KMU_STATUS_BLOCKED_Disabled (0x0UL) /*!< No access violation detected */
#define KMU_STATUS_BLOCKED_Enabled (0x1UL) /*!< Access violation detected and blocked */

/* Bit 0 : Key slot ID successfully selected by the KMU */
#define KMU_STATUS_SELECTED_Pos (0UL) /*!< Position of SELECTED field. */
#define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define KMU_STATUS_SELECTED_Disabled (0x0UL) /*!< No key slot ID selected by KMU */
#define KMU_STATUS_SELECTED_Enabled (0x1UL) /*!< Key slot ID successfully selected by KMU */

/* Register: KMU_SELECTKEYSLOT */
/* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */

/* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. */
#define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */
#define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */


/* Peripheral: LPCOMP */
/* Description: Low-power comparator 0 */

/* Register: LPCOMP_TASKS_START */
/* Description: Start comparator */

/* Bit 0 : Start comparator */
#define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define LPCOMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */

/* Register: LPCOMP_TASKS_STOP */
/* Description: Stop comparator */

/* Bit 0 : Stop comparator */
#define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: LPCOMP_TASKS_SAMPLE */
/* Description: Sample comparator value */

/* Bit 0 : Sample comparator value */
#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */

/* Register: LPCOMP_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */

/* Bit 31 :   */
#define LPCOMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define LPCOMP_SUBSCRIBE_START_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define LPCOMP_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
#define LPCOMP_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define LPCOMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define LPCOMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: LPCOMP_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define LPCOMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define LPCOMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define LPCOMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define LPCOMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define LPCOMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: LPCOMP_SUBSCRIBE_SAMPLE */
/* Description: Subscribe configuration for task SAMPLE */

/* Bit 31 :   */
#define LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */
#define LPCOMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */
#define LPCOMP_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define LPCOMP_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */
#define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: LPCOMP_EVENTS_READY */
/* Description: LPCOMP is ready and output is valid */

/* Bit 0 : LPCOMP is ready and output is valid */
#define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
#define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
#define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */
#define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */

/* Register: LPCOMP_EVENTS_DOWN */
/* Description: Downward crossing */

/* Bit 0 : Downward crossing */
#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated */
#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated */

/* Register: LPCOMP_EVENTS_UP */
/* Description: Upward crossing */

/* Bit 0 : Upward crossing */
#define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
#define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
#define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated */
#define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated */

/* Register: LPCOMP_EVENTS_CROSS */
/* Description: Downward or upward crossing */

/* Bit 0 : Downward or upward crossing */
#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated */
#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated */

/* Register: LPCOMP_PUBLISH_READY */
/* Description: Publish configuration for event READY */

/* Bit 31 :   */
#define LPCOMP_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */
#define LPCOMP_PUBLISH_READY_EN_Msk (0x1UL << LPCOMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */
#define LPCOMP_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */
#define LPCOMP_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event READY will publish to */
#define LPCOMP_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define LPCOMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: LPCOMP_PUBLISH_DOWN */
/* Description: Publish configuration for event DOWN */

/* Bit 31 :   */
#define LPCOMP_PUBLISH_DOWN_EN_Pos (31UL) /*!< Position of EN field. */
#define LPCOMP_PUBLISH_DOWN_EN_Msk (0x1UL << LPCOMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field. */
#define LPCOMP_PUBLISH_DOWN_EN_Disabled (0x0UL) /*!< Disable publishing */
#define LPCOMP_PUBLISH_DOWN_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event DOWN will publish to */
#define LPCOMP_PUBLISH_DOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define LPCOMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: LPCOMP_PUBLISH_UP */
/* Description: Publish configuration for event UP */

/* Bit 31 :   */
#define LPCOMP_PUBLISH_UP_EN_Pos (31UL) /*!< Position of EN field. */
#define LPCOMP_PUBLISH_UP_EN_Msk (0x1UL << LPCOMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field. */
#define LPCOMP_PUBLISH_UP_EN_Disabled (0x0UL) /*!< Disable publishing */
#define LPCOMP_PUBLISH_UP_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event UP will publish to */
#define LPCOMP_PUBLISH_UP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define LPCOMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: LPCOMP_PUBLISH_CROSS */
/* Description: Publish configuration for event CROSS */

/* Bit 31 :   */
#define LPCOMP_PUBLISH_CROSS_EN_Pos (31UL) /*!< Position of EN field. */
#define LPCOMP_PUBLISH_CROSS_EN_Msk (0x1UL << LPCOMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field. */
#define LPCOMP_PUBLISH_CROSS_EN_Disabled (0x0UL) /*!< Disable publishing */
#define LPCOMP_PUBLISH_CROSS_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event CROSS will publish to */
#define LPCOMP_PUBLISH_CROSS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define LPCOMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: LPCOMP_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 4 : Shortcut between event CROSS and task STOP */
#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_CROSS_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 3 : Shortcut between event UP and task STOP */
#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
#define LPCOMP_SHORTS_UP_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_UP_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 2 : Shortcut between event DOWN and task STOP */
#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_DOWN_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 1 : Shortcut between event READY and task STOP */
#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
#define LPCOMP_SHORTS_READY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_READY_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 0 : Shortcut between event READY and task SAMPLE */
#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut */
#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: LPCOMP_INTENSET */
/* Description: Enable interrupt */

/* Bit 3 : Write '1' to enable interrupt for event CROSS */
#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define LPCOMP_INTENSET_CROSS_Disabled (0x0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_CROSS_Enabled (0x1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_CROSS_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event UP */
#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
#define LPCOMP_INTENSET_UP_Disabled (0x0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_UP_Enabled (0x1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_UP_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event DOWN */
#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define LPCOMP_INTENSET_DOWN_Disabled (0x0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_DOWN_Enabled (0x1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_DOWN_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event READY */
#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define LPCOMP_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */
#define LPCOMP_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */
#define LPCOMP_INTENSET_READY_Set (0x1UL) /*!< Enable */

/* Register: LPCOMP_INTENCLR */
/* Description: Disable interrupt */

/* Bit 3 : Write '1' to disable interrupt for event CROSS */
#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
#define LPCOMP_INTENCLR_CROSS_Disabled (0x0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_CROSS_Enabled (0x1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_CROSS_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event UP */
#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
#define LPCOMP_INTENCLR_UP_Disabled (0x0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_UP_Enabled (0x1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_UP_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event DOWN */
#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
#define LPCOMP_INTENCLR_DOWN_Disabled (0x0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_DOWN_Enabled (0x1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_DOWN_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event READY */
#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define LPCOMP_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */
#define LPCOMP_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */
#define LPCOMP_INTENCLR_READY_Clear (0x1UL) /*!< Disable */

/* Register: LPCOMP_RESULT */
/* Description: Compare result */

/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
#define LPCOMP_RESULT_RESULT_Below (0x0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-) */
#define LPCOMP_RESULT_RESULT_Above (0x1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-) */

/* Register: LPCOMP_ENABLE */
/* Description: Enable LPCOMP */

/* Bits 1..0 : Enable or disable LPCOMP */
#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define LPCOMP_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
#define LPCOMP_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */

/* Register: LPCOMP_PSEL */
/* Description: Input pin select */

/* Bits 2..0 : Analog pin select */
#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
#define LPCOMP_PSEL_PSEL_AnalogInput0 (0x0UL) /*!< AIN0 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput1 (0x1UL) /*!< AIN1 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput2 (0x2UL) /*!< AIN2 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput3 (0x3UL) /*!< AIN3 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput4 (0x4UL) /*!< AIN4 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput5 (0x5UL) /*!< AIN5 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput6 (0x6UL) /*!< AIN6 selected as analog input */
#define LPCOMP_PSEL_PSEL_AnalogInput7 (0x7UL) /*!< AIN7 selected as analog input */

/* Register: LPCOMP_REFSEL */
/* Description: Reference select */

/* Bits 3..0 : Reference select */
#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0x0UL) /*!< VDD * 1/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (0x1UL) /*!< VDD * 2/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (0x2UL) /*!< VDD * 3/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (0x3UL) /*!< VDD * 4/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (0x4UL) /*!< VDD * 5/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (0x5UL) /*!< VDD * 6/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (0x6UL) /*!< VDD * 7/8 selected as reference */
#define LPCOMP_REFSEL_REFSEL_ARef (0x7UL) /*!< External analog reference selected */
#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (0x8UL) /*!< VDD * 1/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (0x9UL) /*!< VDD * 3/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (0xAUL) /*!< VDD * 5/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (0xBUL) /*!< VDD * 7/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (0xCUL) /*!< VDD * 9/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (0xDUL) /*!< VDD * 11/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (0xEUL) /*!< VDD * 13/16 selected as reference */
#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (0xFUL) /*!< VDD * 15/16 selected as reference */

/* Register: LPCOMP_EXTREFSEL */
/* Description: External reference select */

/* Bit 0 : External analog reference select */
#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0x0UL) /*!< Use AIN0 as external analog reference */
#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (0x1UL) /*!< Use AIN1 as external analog reference */

/* Register: LPCOMP_ANADETECT */
/* Description: Analog detect configuration */

/* Bits 1..0 : Analog detect configuration */
#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
#define LPCOMP_ANADETECT_ANADETECT_Cross (0x0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
#define LPCOMP_ANADETECT_ANADETECT_Up (0x1UL) /*!< Generate ANADETECT on upward crossing only */
#define LPCOMP_ANADETECT_ANADETECT_Down (0x2UL) /*!< Generate ANADETECT on downward crossing only */

/* Register: LPCOMP_HYST */
/* Description: Comparator hysteresis enable */

/* Bit 0 : Comparator hysteresis enable */
#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
#define LPCOMP_HYST_HYST_Disabled (0x0UL) /*!< Comparator hysteresis disabled */
#define LPCOMP_HYST_HYST_Enabled (0x1UL) /*!< Comparator hysteresis enabled */


/* Peripheral: MUTEX */
/* Description: MUTEX 0 */

/* Register: MUTEX_MUTEX */
/* Description: Description collection: Mutex register */

/* Bit 0 : Mutex register n */
#define MUTEX_MUTEX_MUTEX_Pos (0UL) /*!< Position of MUTEX field. */
#define MUTEX_MUTEX_MUTEX_Msk (0x1UL << MUTEX_MUTEX_MUTEX_Pos) /*!< Bit mask of MUTEX field. */
#define MUTEX_MUTEX_MUTEX_Unlocked (0x0UL) /*!< Mutex n is in unlocked state */
#define MUTEX_MUTEX_MUTEX_Locked (0x1UL) /*!< Mutex n is in locked state */


/* Peripheral: NFCT */
/* Description: NFC-A compatible radio 0 */

/* Register: NFCT_TASKS_ACTIVATE */
/* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */

/* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (0x1UL) /*!< Trigger task */

/* Register: NFCT_TASKS_DISABLE */
/* Description: Disable NFCT peripheral */

/* Bit 0 : Disable NFCT peripheral */
#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (0x1UL) /*!< Trigger task */

/* Register: NFCT_TASKS_SENSE */
/* Description: Enable NFC sense field mode, change state to sense mode */

/* Bit 0 : Enable NFC sense field mode, change state to sense mode */
#define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */
#define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */
#define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (0x1UL) /*!< Trigger task */

/* Register: NFCT_TASKS_STARTTX */
/* Description: Start transmission of an outgoing frame, change state to transmit */

/* Bit 0 : Start transmission of an outgoing frame, change state to transmit */
#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */

/* Register: NFCT_TASKS_ENABLERXDATA */
/* Description: Initializes the EasyDMA for receive. */

/* Bit 0 : Initializes the EasyDMA for receive. */
#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */
#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */
#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (0x1UL) /*!< Trigger task */

/* Register: NFCT_TASKS_GOIDLE */
/* Description: Force state machine to IDLE state */

/* Bit 0 : Force state machine to IDLE state */
#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */
#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */
#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (0x1UL) /*!< Trigger task */

/* Register: NFCT_TASKS_GOSLEEP */
/* Description: Force state machine to SLEEP_A state */

/* Bit 0 : Force state machine to SLEEP_A state */
#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */
#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */
#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (0x1UL) /*!< Trigger task */

/* Register: NFCT_SUBSCRIBE_ACTIVATE */
/* Description: Subscribe configuration for task ACTIVATE */

/* Bit 31 :   */
#define NFCT_SUBSCRIBE_ACTIVATE_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_SUBSCRIBE_ACTIVATE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ACTIVATE_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_SUBSCRIBE_ACTIVATE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define NFCT_SUBSCRIBE_ACTIVATE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task ACTIVATE will subscribe to */
#define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_SUBSCRIBE_DISABLE */
/* Description: Subscribe configuration for task DISABLE */

/* Bit 31 :   */
#define NFCT_SUBSCRIBE_DISABLE_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_SUBSCRIBE_DISABLE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define NFCT_SUBSCRIBE_DISABLE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task DISABLE will subscribe to */
#define NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_SUBSCRIBE_SENSE */
/* Description: Subscribe configuration for task SENSE */

/* Bit 31 :   */
#define NFCT_SUBSCRIBE_SENSE_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_SUBSCRIBE_SENSE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_SENSE_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_SUBSCRIBE_SENSE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define NFCT_SUBSCRIBE_SENSE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SENSE will subscribe to */
#define NFCT_SUBSCRIBE_SENSE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_SUBSCRIBE_SENSE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_SENSE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_SUBSCRIBE_STARTTX */
/* Description: Subscribe configuration for task STARTTX */

/* Bit 31 :   */
#define NFCT_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << NFCT_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription */
#define NFCT_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
#define NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_SUBSCRIBE_ENABLERXDATA */
/* Description: Subscribe configuration for task ENABLERXDATA */

/* Bit 31 :   */
#define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Disabled (0x0UL) /*!< Disable subscription */
#define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task ENABLERXDATA will subscribe to */
#define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_SUBSCRIBE_GOIDLE */
/* Description: Subscribe configuration for task GOIDLE */

/* Bit 31 :   */
#define NFCT_SUBSCRIBE_GOIDLE_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_SUBSCRIBE_GOIDLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOIDLE_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_SUBSCRIBE_GOIDLE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define NFCT_SUBSCRIBE_GOIDLE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task GOIDLE will subscribe to */
#define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_SUBSCRIBE_GOSLEEP */
/* Description: Subscribe configuration for task GOSLEEP */

/* Bit 31 :   */
#define NFCT_SUBSCRIBE_GOSLEEP_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_SUBSCRIBE_GOSLEEP_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOSLEEP_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_SUBSCRIBE_GOSLEEP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define NFCT_SUBSCRIBE_GOSLEEP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task GOSLEEP will subscribe to */
#define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_EVENTS_READY */
/* Description: The NFCT peripheral is ready to receive and send frames */

/* Bit 0 : The NFCT peripheral is ready to receive and send frames */
#define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
#define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
#define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_FIELDDETECTED */
/* Description: Remote NFC field detected */

/* Bit 0 : Remote NFC field detected */
#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */
#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */
#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_FIELDLOST */
/* Description: Remote NFC field lost */

/* Bit 0 : Remote NFC field lost */
#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */
#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */
#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_TXFRAMESTART */
/* Description: Marks the start of the first symbol of a transmitted frame */

/* Bit 0 : Marks the start of the first symbol of a transmitted frame */
#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */
#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */
#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_TXFRAMEEND */
/* Description: Marks the end of the last transmitted on-air symbol of a frame */

/* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */
#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */
#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */
#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_RXFRAMESTART */
/* Description: Marks the end of the first symbol of a received frame */

/* Bit 0 : Marks the end of the first symbol of a received frame */
#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */
#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */
#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_RXFRAMEEND */
/* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */

/* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */
#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */
#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_ERROR */
/* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */

/* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
#define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_RXERROR */
/* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */

/* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */
#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */
#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_ENDRX */
/* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */

/* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_ENDTX */
/* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */

/* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */
/* Description: Auto collision resolution process has started */

/* Bit 0 : Auto collision resolution process has started */
#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */
#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */
#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_COLLISION */
/* Description: NFC auto collision resolution error reported. */

/* Bit 0 : NFC auto collision resolution error reported. */
#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */
#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */
#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_SELECTED */
/* Description: NFC auto collision resolution successfully completed */

/* Bit 0 : NFC auto collision resolution successfully completed */
#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */
#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */
#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_EVENTS_STARTED */
/* Description: EasyDMA is ready to receive or send frames. */

/* Bit 0 : EasyDMA is ready to receive or send frames. */
#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
#define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */

/* Register: NFCT_PUBLISH_READY */
/* Description: Publish configuration for event READY */

/* Bit 31 :   */
#define NFCT_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_READY_EN_Msk (0x1UL << NFCT_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event READY will publish to */
#define NFCT_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_READY_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_FIELDDETECTED */
/* Description: Publish configuration for event FIELDDETECTED */

/* Bit 31 :   */
#define NFCT_PUBLISH_FIELDDETECTED_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_FIELDDETECTED_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDDETECTED_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_FIELDDETECTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_FIELDDETECTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event FIELDDETECTED will publish to */
#define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_FIELDLOST */
/* Description: Publish configuration for event FIELDLOST */

/* Bit 31 :   */
#define NFCT_PUBLISH_FIELDLOST_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_FIELDLOST_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDLOST_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_FIELDLOST_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_FIELDLOST_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event FIELDLOST will publish to */
#define NFCT_PUBLISH_FIELDLOST_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_FIELDLOST_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDLOST_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_TXFRAMESTART */
/* Description: Publish configuration for event TXFRAMESTART */

/* Bit 31 :   */
#define NFCT_PUBLISH_TXFRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_TXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMESTART_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_TXFRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_TXFRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TXFRAMESTART will publish to */
#define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_TXFRAMEEND */
/* Description: Publish configuration for event TXFRAMEEND */

/* Bit 31 :   */
#define NFCT_PUBLISH_TXFRAMEEND_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_TXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMEEND_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_TXFRAMEEND_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_TXFRAMEEND_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TXFRAMEEND will publish to */
#define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_RXFRAMESTART */
/* Description: Publish configuration for event RXFRAMESTART */

/* Bit 31 :   */
#define NFCT_PUBLISH_RXFRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_RXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMESTART_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_RXFRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_RXFRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RXFRAMESTART will publish to */
#define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_RXFRAMEEND */
/* Description: Publish configuration for event RXFRAMEEND */

/* Bit 31 :   */
#define NFCT_PUBLISH_RXFRAMEEND_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_RXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMEEND_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_RXFRAMEEND_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_RXFRAMEEND_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RXFRAMEEND will publish to */
#define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_ERROR */
/* Description: Publish configuration for event ERROR */

/* Bit 31 :   */
#define NFCT_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_ERROR_EN_Msk (0x1UL << NFCT_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ERROR will publish to */
#define NFCT_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_RXERROR */
/* Description: Publish configuration for event RXERROR */

/* Bit 31 :   */
#define NFCT_PUBLISH_RXERROR_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_RXERROR_EN_Msk (0x1UL << NFCT_PUBLISH_RXERROR_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_RXERROR_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_RXERROR_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RXERROR will publish to */
#define NFCT_PUBLISH_RXERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_RXERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_ENDRX */
/* Description: Publish configuration for event ENDRX */

/* Bit 31 :   */
#define NFCT_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_ENDRX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDRX will publish to */
#define NFCT_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_ENDTX */
/* Description: Publish configuration for event ENDTX */

/* Bit 31 :   */
#define NFCT_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_ENDTX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_ENDTX_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_ENDTX_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDTX will publish to */
#define NFCT_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_AUTOCOLRESSTARTED */
/* Description: Publish configuration for event AUTOCOLRESSTARTED */

/* Bit 31 :   */
#define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Msk (0x1UL << NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event AUTOCOLRESSTARTED will publish to */
#define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_COLLISION */
/* Description: Publish configuration for event COLLISION */

/* Bit 31 :   */
#define NFCT_PUBLISH_COLLISION_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_COLLISION_EN_Msk (0x1UL << NFCT_PUBLISH_COLLISION_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_COLLISION_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_COLLISION_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event COLLISION will publish to */
#define NFCT_PUBLISH_COLLISION_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_COLLISION_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_COLLISION_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_SELECTED */
/* Description: Publish configuration for event SELECTED */

/* Bit 31 :   */
#define NFCT_PUBLISH_SELECTED_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_SELECTED_EN_Msk (0x1UL << NFCT_PUBLISH_SELECTED_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_SELECTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_SELECTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event SELECTED will publish to */
#define NFCT_PUBLISH_SELECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_SELECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_SELECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_PUBLISH_STARTED */
/* Description: Publish configuration for event STARTED */

/* Bit 31 :   */
#define NFCT_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define NFCT_PUBLISH_STARTED_EN_Msk (0x1UL << NFCT_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
#define NFCT_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define NFCT_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STARTED will publish to */
#define NFCT_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define NFCT_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: NFCT_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */
#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */
#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */
#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0x0UL) /*!< Disable shortcut */
#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 1 : Shortcut between event FIELDLOST and task SENSE */
#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0x0UL) /*!< Disable shortcut */
#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0x0UL) /*!< Disable shortcut */
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: NFCT_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 20 : Enable or disable interrupt for event STARTED */
#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 19 : Enable or disable interrupt for event SELECTED */
#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTEN_SELECTED_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_SELECTED_Enabled (0x1UL) /*!< Enable */

/* Bit 18 : Enable or disable interrupt for event COLLISION */
#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTEN_COLLISION_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_COLLISION_Enabled (0x1UL) /*!< Enable */

/* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 12 : Enable or disable interrupt for event ENDTX */
#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTEN_ENDTX_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_ENDTX_Enabled (0x1UL) /*!< Enable */

/* Bit 11 : Enable or disable interrupt for event ENDRX */
#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTEN_ENDRX_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_ENDRX_Enabled (0x1UL) /*!< Enable */

/* Bit 10 : Enable or disable interrupt for event RXERROR */
#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTEN_RXERROR_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_RXERROR_Enabled (0x1UL) /*!< Enable */

/* Bit 7 : Enable or disable interrupt for event ERROR */
#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */

/* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */
#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTEN_RXFRAMEEND_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_RXFRAMEEND_Enabled (0x1UL) /*!< Enable */

/* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */
#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTEN_RXFRAMESTART_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_RXFRAMESTART_Enabled (0x1UL) /*!< Enable */

/* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */
#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTEN_TXFRAMEEND_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_TXFRAMEEND_Enabled (0x1UL) /*!< Enable */

/* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */
#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTEN_TXFRAMESTART_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_TXFRAMESTART_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event FIELDLOST */
#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTEN_FIELDLOST_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_FIELDLOST_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */
#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTEN_FIELDDETECTED_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_FIELDDETECTED_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event READY */
#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTEN_READY_Disabled (0x0UL) /*!< Disable */
#define NFCT_INTEN_READY_Enabled (0x1UL) /*!< Enable */

/* Register: NFCT_INTENSET */
/* Description: Enable interrupt */

/* Bit 20 : Write '1' to enable interrupt for event STARTED */
#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_STARTED_Set (0x1UL) /*!< Enable */

/* Bit 19 : Write '1' to enable interrupt for event SELECTED */
#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTENSET_SELECTED_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_SELECTED_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_SELECTED_Set (0x1UL) /*!< Enable */

/* Bit 18 : Write '1' to enable interrupt for event COLLISION */
#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTENSET_COLLISION_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_COLLISION_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_COLLISION_Set (0x1UL) /*!< Enable */

/* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (0x1UL) /*!< Enable */

/* Bit 12 : Write '1' to enable interrupt for event ENDTX */
#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */

/* Bit 11 : Write '1' to enable interrupt for event ENDRX */
#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */

/* Bit 10 : Write '1' to enable interrupt for event RXERROR */
#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTENSET_RXERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXERROR_Set (0x1UL) /*!< Enable */

/* Bit 7 : Write '1' to enable interrupt for event ERROR */
#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_ERROR_Set (0x1UL) /*!< Enable */

/* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */
#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTENSET_RXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXFRAMEEND_Set (0x1UL) /*!< Enable */

/* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */
#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTENSET_RXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_RXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_RXFRAMESTART_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */
#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTENSET_TXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_TXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_TXFRAMEEND_Set (0x1UL) /*!< Enable */

/* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */
#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTENSET_TXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_TXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_TXFRAMESTART_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */
#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTENSET_FIELDLOST_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_FIELDLOST_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_FIELDLOST_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */
#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTENSET_FIELDDETECTED_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_FIELDDETECTED_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_FIELDDETECTED_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event READY */
#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENSET_READY_Set (0x1UL) /*!< Enable */

/* Register: NFCT_INTENCLR */
/* Description: Disable interrupt */

/* Bit 20 : Write '1' to disable interrupt for event STARTED */
#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define NFCT_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */

/* Bit 19 : Write '1' to disable interrupt for event SELECTED */
#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
#define NFCT_INTENCLR_SELECTED_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_SELECTED_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_SELECTED_Clear (0x1UL) /*!< Disable */

/* Bit 18 : Write '1' to disable interrupt for event COLLISION */
#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
#define NFCT_INTENCLR_COLLISION_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_COLLISION_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_COLLISION_Clear (0x1UL) /*!< Disable */

/* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (0x1UL) /*!< Disable */

/* Bit 12 : Write '1' to disable interrupt for event ENDTX */
#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define NFCT_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */

/* Bit 11 : Write '1' to disable interrupt for event ENDRX */
#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define NFCT_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */

/* Bit 10 : Write '1' to disable interrupt for event RXERROR */
#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
#define NFCT_INTENCLR_RXERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXERROR_Clear (0x1UL) /*!< Disable */

/* Bit 7 : Write '1' to disable interrupt for event ERROR */
#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define NFCT_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */

/* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */
#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXFRAMEEND_Clear (0x1UL) /*!< Disable */

/* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */
#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_RXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_RXFRAMESTART_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */
#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_TXFRAMEEND_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_TXFRAMEEND_Clear (0x1UL) /*!< Disable */

/* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */
#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_TXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_TXFRAMESTART_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */
#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
#define NFCT_INTENCLR_FIELDLOST_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_FIELDLOST_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_FIELDLOST_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */
#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_FIELDDETECTED_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_FIELDDETECTED_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event READY */
#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define NFCT_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */
#define NFCT_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */
#define NFCT_INTENCLR_READY_Clear (0x1UL) /*!< Disable */

/* Register: NFCT_ERRORSTATUS */
/* Description: NFC Error Status register */

/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */

/* Register: NFCT_FRAMESTATUS_RX */
/* Description: Result of last incoming frame */

/* Bit 3 : Overrun detected */
#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0x0UL) /*!< No overrun detected */
#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (0x1UL) /*!< Overrun error */

/* Bit 2 : Parity status of received frame */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0x0UL) /*!< Frame received with parity OK */
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (0x1UL) /*!< Frame received with parity error */

/* Bit 0 : No valid end of frame (EoF) detected */
#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0x0UL) /*!< Valid CRC detected */
#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (0x1UL) /*!< CRC received does not match local check */

/* Register: NFCT_NFCTAGSTATE */
/* Description: Current operating state of NFC tag */

/* Bits 2..0 : NfcTag state */
#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */
#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */
#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0x0UL) /*!< Disabled or sense */
#define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (0x2UL) /*!< RampUp */
#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (0x3UL) /*!< Idle */
#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (0x4UL) /*!< Receive */
#define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (0x5UL) /*!< FrameDelay */
#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (0x6UL) /*!< Transmit */

/* Register: NFCT_SLEEPSTATE */
/* Description: Sleep state during automatic collision resolution */

/* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE
        by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a
        GOSLEEP task. */
#define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */
#define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */
#define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0x0UL) /*!< State is IDLE. */
#define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (0x1UL) /*!< State is SLEEP_A. */

/* Register: NFCT_FIELDPRESENT */
/* Description: Indicates the presence or not of a valid field */

/* Bit 1 : Indicates if the low level has locked to the field */
#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0x0UL) /*!< Not locked to field */
#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (0x1UL) /*!< Locked to field */

/* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */
#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0x0UL) /*!< No valid field detected */
#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (0x1UL) /*!< Valid field detected */

/* Register: NFCT_FRAMEDELAYMIN */
/* Description: Minimum frame delay */

/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clock cycles */
#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */

/* Register: NFCT_FRAMEDELAYMAX */
/* Description: Maximum frame delay */

/* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clock cycles */
#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */

/* Register: NFCT_FRAMEDELAYMODE */
/* Description: Configuration register for the Frame Delay Timer */

/* Bits 1..0 : Configuration register for the Frame Delay Timer */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0x0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (0x1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (0x2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (0x3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */

/* Register: NFCT_PACKETPTR */
/* Description: Packet pointer for TXD and RXD data storage in Data RAM */

/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */
#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: NFCT_MAXLEN */
/* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */

/* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */
#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */

/* Register: NFCT_TXD_FRAMECONFIG */
/* Description: Configuration of outgoing frames */

/* Bit 4 : CRC mode for outgoing frames */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0x0UL) /*!< CRC is not added to the frame */
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (0x1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */

/* Bit 2 : Adding SoF or not in TX frames */
#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0x0UL) /*!< SoF symbol not added */
#define NFCT_TXD_FRAMECONFIG_SOF_SoF (0x1UL) /*!< SoF symbol added */

/* Bit 1 : Discarding unused bits at start or end of a frame */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0x0UL) /*!< Unused bits are discarded at end of frame (EoF) */
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (0x1UL) /*!< Unused bits are discarded at start of frame (SoF) */

/* Bit 0 : Indicates if parity is added to the frame */
#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0x0UL) /*!< Parity is not added to TX frames */
#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (0x1UL) /*!< Parity is added to TX frames */

/* Register: NFCT_TXD_AMOUNT */
/* Description: Size of outgoing frame */

/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. */
#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */

/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */

/* Register: NFCT_RXD_FRAMECONFIG */
/* Description: Configuration of incoming frames */

/* Bit 4 : CRC mode for incoming frames */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0x0UL) /*!< CRC is not expected in RX frames */
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (0x1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */

/* Bit 2 : SoF expected or not in RX frames */
#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0x0UL) /*!< SoF symbol is not expected in RX frames */
#define NFCT_RXD_FRAMECONFIG_SOF_SoF (0x1UL) /*!< SoF symbol is expected in RX frames */

/* Bit 0 : Indicates if parity expected in RX frame */
#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0x0UL) /*!< Parity is not expected in RX frames */
#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (0x1UL) /*!< Parity is expected in RX frames */

/* Register: NFCT_RXD_AMOUNT */
/* Description: Size of last incoming frame */

/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */

/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */

/* Register: NFCT_MODULATIONCTRL */
/* Description: Enables the modulation output to a GPIO pin which can be connected to a second external antenna. */

/* Bits 1..0 : Configuration of modulation control. */
#define NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos (0UL) /*!< Position of MODULATIONCTRL field. */
#define NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk (0x3UL << NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos) /*!< Bit mask of MODULATIONCTRL field. */
#define NFCT_MODULATIONCTRL_MODULATIONCTRL_Invalid (0x0UL) /*!< Invalid, defaults to same behaviour as for Internal */
#define NFCT_MODULATIONCTRL_MODULATIONCTRL_Internal (0x1UL) /*!< Use internal modulator only */
#define NFCT_MODULATIONCTRL_MODULATIONCTRL_ModToGpio (0x2UL) /*!< Output digital modulation signal to a GPIO pin. */
#define NFCT_MODULATIONCTRL_MODULATIONCTRL_InternalAndModToGpio (0x3UL) /*!< Use internal modulator and output digital modulation signal to a GPIO pin. */

/* Register: NFCT_MODULATIONPSEL */
/* Description: Pin select for Modulation control */

/* Bit 31 : Connection */
#define NFCT_MODULATIONPSEL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define NFCT_MODULATIONPSEL_CONNECT_Msk (0x1UL << NFCT_MODULATIONPSEL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define NFCT_MODULATIONPSEL_CONNECT_Connected (0x0UL) /*!< Connect */
#define NFCT_MODULATIONPSEL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define NFCT_MODULATIONPSEL_PORT_Pos (5UL) /*!< Position of PORT field. */
#define NFCT_MODULATIONPSEL_PORT_Msk (0x1UL << NFCT_MODULATIONPSEL_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define NFCT_MODULATIONPSEL_PIN_Pos (0UL) /*!< Position of PIN field. */
#define NFCT_MODULATIONPSEL_PIN_Msk (0x1FUL << NFCT_MODULATIONPSEL_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: NFCT_NFCID1_LAST */
/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */

/* Bits 31..24 : NFCID1 byte W */
#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */

/* Bits 23..16 : NFCID1 byte X */
#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */

/* Bits 15..8 : NFCID1 byte Y */
#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */

/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */

/* Register: NFCT_NFCID1_2ND_LAST */
/* Description: Second last NFCID1 part (7 or 10 bytes ID) */

/* Bits 23..16 : NFCID1 byte T */
#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */

/* Bits 15..8 : NFCID1 byte U */
#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */

/* Bits 7..0 : NFCID1 byte V */
#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */

/* Register: NFCT_NFCID1_3RD_LAST */
/* Description: Third last NFCID1 part (10 bytes ID) */

/* Bits 23..16 : NFCID1 byte Q */
#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */

/* Bits 15..8 : NFCID1 byte R */
#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */

/* Bits 7..0 : NFCID1 byte S */
#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */

/* Register: NFCT_AUTOCOLRESCONFIG */
/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. */

/* Bit 0 : Enables/disables auto collision resolution */
#define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
#define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
#define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0x0UL) /*!< Auto collision resolution enabled */
#define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (0x1UL) /*!< Auto collision resolution disabled */

/* Register: NFCT_SENSRES */
/* Description: NFC-A SENS_RES auto-response settings */

/* Bits 15..12 : Reserved for future use. Shall be 0. */
#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */

/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */

/* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */
#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0x0UL) /*!< NFCID1 size: single (4 bytes) */
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (0x1UL) /*!< NFCID1 size: double (7 bytes) */
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (0x2UL) /*!< NFCID1 size: triple (10 bytes) */

/* Bit 5 : Reserved for future use. Shall be 0. */
#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */

/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0x00UL) /*!< SDD pattern 00000 */
#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (0x01UL) /*!< SDD pattern 00001 */
#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (0x02UL) /*!< SDD pattern 00010 */
#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (0x04UL) /*!< SDD pattern 00100 */
#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (0x08UL) /*!< SDD pattern 01000 */
#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (0x10UL) /*!< SDD pattern 10000 */

/* Register: NFCT_SELRES */
/* Description: NFC-A SEL_RES auto-response settings */

/* Bit 7 : Reserved for future use. Shall be 0. */
#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */

/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */

/* Bits 4..3 : Reserved for future use. Shall be 0. */
#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */

/* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */
#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */

/* Bits 1..0 : Reserved for future use. Shall be 0. */
#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */


/* Peripheral: NVMC */
/* Description: Non-volatile memory controller 0 */

/* Register: NVMC_READY */
/* Description: Ready flag */

/* Bit 0 : NVMC is ready or busy */
#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
#define NVMC_READY_READY_Busy (0x0UL) /*!< NVMC is busy (ongoing write or erase operation) */
#define NVMC_READY_READY_Ready (0x1UL) /*!< NVMC is ready */

/* Register: NVMC_READYNEXT */
/* Description: Ready flag */

/* Bit 0 : NVMC can accept a new write operation */
#define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
#define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
#define NVMC_READYNEXT_READYNEXT_Busy (0x0UL) /*!< NVMC cannot accept any write operation */
#define NVMC_READYNEXT_READYNEXT_Ready (0x1UL) /*!< NVMC is ready */

/* Register: NVMC_CONFIG */
/* Description: Configuration register */

/* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */
#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
#define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
#define NVMC_CONFIG_WEN_Ren (0x0UL) /*!< Read only access */
#define NVMC_CONFIG_WEN_Wen (0x1UL) /*!< Write enabled */
#define NVMC_CONFIG_WEN_Een (0x2UL) /*!< Erase enabled */
#define NVMC_CONFIG_WEN_PEen (0x4UL) /*!< Partial erase enabled */

/* Register: NVMC_ERASEALL */
/* Description: Register for erasing all non-volatile user memory */

/* Bit 0 : Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. */
#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
#define NVMC_ERASEALL_ERASEALL_NoOperation (0x0UL) /*!< No operation */
#define NVMC_ERASEALL_ERASEALL_Erase (0x1UL) /*!< Start chip erase */

/* Register: NVMC_ERASEPAGEPARTIALCFG */
/* Description: Register for partial erase configuration */

/* Bits 6..0 : Duration of the partial erase in milliseconds */
#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */

/* Register: NVMC_CONFIGNS */
/* Description: Non-secure configuration register */

/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */
#define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */
#define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */
#define NVMC_CONFIGNS_WEN_Ren (0x0UL) /*!< Read only access */
#define NVMC_CONFIGNS_WEN_Wen (0x1UL) /*!< Write enabled */
#define NVMC_CONFIGNS_WEN_Een (0x2UL) /*!< Erase enabled */

/* Register: NVMC_WRITEUICRNS */
/* Description: Non-secure APPROTECT enable register */

/* Bits 31..4 : Key to write in order to validate the write operation */
#define NVMC_WRITEUICRNS_KEY_Pos (4UL) /*!< Position of KEY field. */
#define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos) /*!< Bit mask of KEY field. */
#define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL) /*!< Key value */

/* Bit 0 : Allow non-secure code to set APPROTECT */
#define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */
#define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */
#define NVMC_WRITEUICRNS_SET_Set (0x1UL) /*!< Set value */


/* Peripheral: OSCILLATORS */
/* Description: Oscillator control 0 */

/* Register: OSCILLATORS_XOSC32MCAPS */
/* Description: Programmable capacitance of XC1 and XC2 */

/* Bit 8 : Enable on-chip capacitors on XC1 and XC2 */
#define OSCILLATORS_XOSC32MCAPS_ENABLE_Pos (8UL) /*!< Position of ENABLE field. */
#define OSCILLATORS_XOSC32MCAPS_ENABLE_Msk (0x1UL << OSCILLATORS_XOSC32MCAPS_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define OSCILLATORS_XOSC32MCAPS_ENABLE_Disabled (0x0UL) /*!< Capacitor disabled (use external caps) */
#define OSCILLATORS_XOSC32MCAPS_ENABLE_Enabled (0x1UL) /*!< Capacitor enabled */

/* Bits 4..0 : Value representing capacitance, calculated using provided equation */
#define OSCILLATORS_XOSC32MCAPS_CAPVALUE_Pos (0UL) /*!< Position of CAPVALUE field. */
#define OSCILLATORS_XOSC32MCAPS_CAPVALUE_Msk (0x1FUL << OSCILLATORS_XOSC32MCAPS_CAPVALUE_Pos) /*!< Bit mask of CAPVALUE field. */

/* Register: OSCILLATORS_XOSC32KI_BYPASS */
/* Description: Enable or disable bypass of LFCLK crystal oscillator with external clock source */

/* Bit 0 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
#define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos (0UL) /*!< Position of BYPASS field. */
#define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Msk (0x1UL << OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
#define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Disabled (0x0UL) /*!< Disable (use with crystal or low-swing external source) */
#define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Enabled (0x1UL) /*!< Enable (use with rail-to-rail external source) */

/* Register: OSCILLATORS_XOSC32KI_INTCAP */
/* Description: Control usage of internal load capacitors */

/* Bits 1..0 : Control usage of internal load capacitors */
#define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_Pos (0UL) /*!< Position of INTCAP field. */
#define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_Msk (0x3UL << OSCILLATORS_XOSC32KI_INTCAP_INTCAP_Pos) /*!< Bit mask of INTCAP field. */
#define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_External (0x0UL) /*!< Use external load capacitors */
#define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C6PF (0x1UL) /*!< 6 pF internal load capacitance */
#define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C7PF (0x2UL) /*!< 7 pF internal load capacitance */
#define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C9PF (0x3UL) /*!< 9 pF internal load capacitance */


/* Peripheral: GPIO */
/* Description: GPIO Port 0 */

/* Register: GPIO_OUT */
/* Description: Write GPIO port */

/* Bit 31 : Pin 31 */
#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUT_PIN31_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN31_High (0x1UL) /*!< Pin driver is high */

/* Bit 30 : Pin 30 */
#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUT_PIN30_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN30_High (0x1UL) /*!< Pin driver is high */

/* Bit 29 : Pin 29 */
#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUT_PIN29_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN29_High (0x1UL) /*!< Pin driver is high */

/* Bit 28 : Pin 28 */
#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUT_PIN28_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN28_High (0x1UL) /*!< Pin driver is high */

/* Bit 27 : Pin 27 */
#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUT_PIN27_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN27_High (0x1UL) /*!< Pin driver is high */

/* Bit 26 : Pin 26 */
#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUT_PIN26_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN26_High (0x1UL) /*!< Pin driver is high */

/* Bit 25 : Pin 25 */
#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUT_PIN25_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN25_High (0x1UL) /*!< Pin driver is high */

/* Bit 24 : Pin 24 */
#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUT_PIN24_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN24_High (0x1UL) /*!< Pin driver is high */

/* Bit 23 : Pin 23 */
#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUT_PIN23_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN23_High (0x1UL) /*!< Pin driver is high */

/* Bit 22 : Pin 22 */
#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUT_PIN22_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN22_High (0x1UL) /*!< Pin driver is high */

/* Bit 21 : Pin 21 */
#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUT_PIN21_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN21_High (0x1UL) /*!< Pin driver is high */

/* Bit 20 : Pin 20 */
#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUT_PIN20_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN20_High (0x1UL) /*!< Pin driver is high */

/* Bit 19 : Pin 19 */
#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUT_PIN19_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN19_High (0x1UL) /*!< Pin driver is high */

/* Bit 18 : Pin 18 */
#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUT_PIN18_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN18_High (0x1UL) /*!< Pin driver is high */

/* Bit 17 : Pin 17 */
#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUT_PIN17_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN17_High (0x1UL) /*!< Pin driver is high */

/* Bit 16 : Pin 16 */
#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUT_PIN16_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN16_High (0x1UL) /*!< Pin driver is high */

/* Bit 15 : Pin 15 */
#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUT_PIN15_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN15_High (0x1UL) /*!< Pin driver is high */

/* Bit 14 : Pin 14 */
#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUT_PIN14_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN14_High (0x1UL) /*!< Pin driver is high */

/* Bit 13 : Pin 13 */
#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUT_PIN13_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN13_High (0x1UL) /*!< Pin driver is high */

/* Bit 12 : Pin 12 */
#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUT_PIN12_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN12_High (0x1UL) /*!< Pin driver is high */

/* Bit 11 : Pin 11 */
#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUT_PIN11_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN11_High (0x1UL) /*!< Pin driver is high */

/* Bit 10 : Pin 10 */
#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUT_PIN10_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN10_High (0x1UL) /*!< Pin driver is high */

/* Bit 9 : Pin 9 */
#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUT_PIN9_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN9_High (0x1UL) /*!< Pin driver is high */

/* Bit 8 : Pin 8 */
#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUT_PIN8_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN8_High (0x1UL) /*!< Pin driver is high */

/* Bit 7 : Pin 7 */
#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUT_PIN7_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN7_High (0x1UL) /*!< Pin driver is high */

/* Bit 6 : Pin 6 */
#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUT_PIN6_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN6_High (0x1UL) /*!< Pin driver is high */

/* Bit 5 : Pin 5 */
#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUT_PIN5_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN5_High (0x1UL) /*!< Pin driver is high */

/* Bit 4 : Pin 4 */
#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUT_PIN4_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN4_High (0x1UL) /*!< Pin driver is high */

/* Bit 3 : Pin 3 */
#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUT_PIN3_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN3_High (0x1UL) /*!< Pin driver is high */

/* Bit 2 : Pin 2 */
#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUT_PIN2_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN2_High (0x1UL) /*!< Pin driver is high */

/* Bit 1 : Pin 1 */
#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUT_PIN1_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN1_High (0x1UL) /*!< Pin driver is high */

/* Bit 0 : Pin 0 */
#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUT_PIN0_Low (0x0UL) /*!< Pin driver is low */
#define GPIO_OUT_PIN0_High (0x1UL) /*!< Pin driver is high */

/* Register: GPIO_OUTSET */
/* Description: Set individual bits in GPIO port */

/* Bit 31 : Pin 31 */
#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUTSET_PIN31_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN31_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 30 : Pin 30 */
#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUTSET_PIN30_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN30_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 29 : Pin 29 */
#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUTSET_PIN29_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN29_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 28 : Pin 28 */
#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUTSET_PIN28_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN28_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 27 : Pin 27 */
#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUTSET_PIN27_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN27_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 26 : Pin 26 */
#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUTSET_PIN26_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN26_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 25 : Pin 25 */
#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUTSET_PIN25_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN25_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 24 : Pin 24 */
#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUTSET_PIN24_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN24_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 23 : Pin 23 */
#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUTSET_PIN23_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN23_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 22 : Pin 22 */
#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUTSET_PIN22_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN22_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 21 : Pin 21 */
#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUTSET_PIN21_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN21_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 20 : Pin 20 */
#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUTSET_PIN20_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN20_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 19 : Pin 19 */
#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUTSET_PIN19_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN19_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 18 : Pin 18 */
#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUTSET_PIN18_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN18_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 17 : Pin 17 */
#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUTSET_PIN17_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN17_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 16 : Pin 16 */
#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUTSET_PIN16_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN16_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 15 : Pin 15 */
#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUTSET_PIN15_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN15_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 14 : Pin 14 */
#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUTSET_PIN14_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN14_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 13 : Pin 13 */
#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUTSET_PIN13_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN13_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 12 : Pin 12 */
#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUTSET_PIN12_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN12_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 11 : Pin 11 */
#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUTSET_PIN11_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN11_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 10 : Pin 10 */
#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUTSET_PIN10_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN10_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 9 : Pin 9 */
#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUTSET_PIN9_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN9_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 8 : Pin 8 */
#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUTSET_PIN8_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN8_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 7 : Pin 7 */
#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUTSET_PIN7_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN7_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 6 : Pin 6 */
#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUTSET_PIN6_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN6_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 5 : Pin 5 */
#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUTSET_PIN5_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN5_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 4 : Pin 4 */
#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUTSET_PIN4_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN4_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 3 : Pin 3 */
#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUTSET_PIN3_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN3_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 2 : Pin 2 */
#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUTSET_PIN2_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN2_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 1 : Pin 1 */
#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUTSET_PIN1_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN1_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Bit 0 : Pin 0 */
#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUTSET_PIN0_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTSET_PIN0_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */

/* Register: GPIO_OUTCLR */
/* Description: Clear individual bits in GPIO port */

/* Bit 31 : Pin 31 */
#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_OUTCLR_PIN31_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN31_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 30 : Pin 30 */
#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_OUTCLR_PIN30_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN30_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 29 : Pin 29 */
#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_OUTCLR_PIN29_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN29_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 28 : Pin 28 */
#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_OUTCLR_PIN28_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN28_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 27 : Pin 27 */
#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_OUTCLR_PIN27_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN27_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 26 : Pin 26 */
#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_OUTCLR_PIN26_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN26_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 25 : Pin 25 */
#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_OUTCLR_PIN25_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN25_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 24 : Pin 24 */
#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_OUTCLR_PIN24_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN24_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 23 : Pin 23 */
#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_OUTCLR_PIN23_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN23_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 22 : Pin 22 */
#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_OUTCLR_PIN22_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN22_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 21 : Pin 21 */
#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_OUTCLR_PIN21_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN21_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 20 : Pin 20 */
#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_OUTCLR_PIN20_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN20_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 19 : Pin 19 */
#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_OUTCLR_PIN19_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN19_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 18 : Pin 18 */
#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_OUTCLR_PIN18_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN18_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 17 : Pin 17 */
#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_OUTCLR_PIN17_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN17_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 16 : Pin 16 */
#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_OUTCLR_PIN16_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN16_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 15 : Pin 15 */
#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_OUTCLR_PIN15_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN15_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 14 : Pin 14 */
#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_OUTCLR_PIN14_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN14_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 13 : Pin 13 */
#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_OUTCLR_PIN13_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN13_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 12 : Pin 12 */
#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_OUTCLR_PIN12_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN12_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 11 : Pin 11 */
#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_OUTCLR_PIN11_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN11_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 10 : Pin 10 */
#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_OUTCLR_PIN10_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN10_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 9 : Pin 9 */
#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_OUTCLR_PIN9_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN9_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 8 : Pin 8 */
#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_OUTCLR_PIN8_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN8_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 7 : Pin 7 */
#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_OUTCLR_PIN7_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN7_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 6 : Pin 6 */
#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_OUTCLR_PIN6_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN6_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 5 : Pin 5 */
#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_OUTCLR_PIN5_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN5_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 4 : Pin 4 */
#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_OUTCLR_PIN4_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN4_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 3 : Pin 3 */
#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_OUTCLR_PIN3_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN3_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 2 : Pin 2 */
#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_OUTCLR_PIN2_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN2_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 1 : Pin 1 */
#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_OUTCLR_PIN1_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN1_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Bit 0 : Pin 0 */
#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_OUTCLR_PIN0_Low (0x0UL) /*!< Read: pin driver is low */
#define GPIO_OUTCLR_PIN0_High (0x1UL) /*!< Read: pin driver is high */
#define GPIO_OUTCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */

/* Register: GPIO_IN */
/* Description: Read GPIO port */

/* Bit 31 : Pin 31 */
#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_IN_PIN31_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN31_High (0x1UL) /*!< Pin input is high */

/* Bit 30 : Pin 30 */
#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_IN_PIN30_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN30_High (0x1UL) /*!< Pin input is high */

/* Bit 29 : Pin 29 */
#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_IN_PIN29_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN29_High (0x1UL) /*!< Pin input is high */

/* Bit 28 : Pin 28 */
#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_IN_PIN28_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN28_High (0x1UL) /*!< Pin input is high */

/* Bit 27 : Pin 27 */
#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_IN_PIN27_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN27_High (0x1UL) /*!< Pin input is high */

/* Bit 26 : Pin 26 */
#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_IN_PIN26_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN26_High (0x1UL) /*!< Pin input is high */

/* Bit 25 : Pin 25 */
#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_IN_PIN25_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN25_High (0x1UL) /*!< Pin input is high */

/* Bit 24 : Pin 24 */
#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_IN_PIN24_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN24_High (0x1UL) /*!< Pin input is high */

/* Bit 23 : Pin 23 */
#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_IN_PIN23_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN23_High (0x1UL) /*!< Pin input is high */

/* Bit 22 : Pin 22 */
#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_IN_PIN22_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN22_High (0x1UL) /*!< Pin input is high */

/* Bit 21 : Pin 21 */
#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_IN_PIN21_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN21_High (0x1UL) /*!< Pin input is high */

/* Bit 20 : Pin 20 */
#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_IN_PIN20_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN20_High (0x1UL) /*!< Pin input is high */

/* Bit 19 : Pin 19 */
#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_IN_PIN19_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN19_High (0x1UL) /*!< Pin input is high */

/* Bit 18 : Pin 18 */
#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_IN_PIN18_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN18_High (0x1UL) /*!< Pin input is high */

/* Bit 17 : Pin 17 */
#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_IN_PIN17_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN17_High (0x1UL) /*!< Pin input is high */

/* Bit 16 : Pin 16 */
#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_IN_PIN16_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN16_High (0x1UL) /*!< Pin input is high */

/* Bit 15 : Pin 15 */
#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_IN_PIN15_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN15_High (0x1UL) /*!< Pin input is high */

/* Bit 14 : Pin 14 */
#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_IN_PIN14_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN14_High (0x1UL) /*!< Pin input is high */

/* Bit 13 : Pin 13 */
#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_IN_PIN13_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN13_High (0x1UL) /*!< Pin input is high */

/* Bit 12 : Pin 12 */
#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_IN_PIN12_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN12_High (0x1UL) /*!< Pin input is high */

/* Bit 11 : Pin 11 */
#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_IN_PIN11_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN11_High (0x1UL) /*!< Pin input is high */

/* Bit 10 : Pin 10 */
#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_IN_PIN10_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN10_High (0x1UL) /*!< Pin input is high */

/* Bit 9 : Pin 9 */
#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_IN_PIN9_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN9_High (0x1UL) /*!< Pin input is high */

/* Bit 8 : Pin 8 */
#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_IN_PIN8_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN8_High (0x1UL) /*!< Pin input is high */

/* Bit 7 : Pin 7 */
#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_IN_PIN7_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN7_High (0x1UL) /*!< Pin input is high */

/* Bit 6 : Pin 6 */
#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_IN_PIN6_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN6_High (0x1UL) /*!< Pin input is high */

/* Bit 5 : Pin 5 */
#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_IN_PIN5_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN5_High (0x1UL) /*!< Pin input is high */

/* Bit 4 : Pin 4 */
#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_IN_PIN4_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN4_High (0x1UL) /*!< Pin input is high */

/* Bit 3 : Pin 3 */
#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_IN_PIN3_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN3_High (0x1UL) /*!< Pin input is high */

/* Bit 2 : Pin 2 */
#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_IN_PIN2_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN2_High (0x1UL) /*!< Pin input is high */

/* Bit 1 : Pin 1 */
#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_IN_PIN1_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN1_High (0x1UL) /*!< Pin input is high */

/* Bit 0 : Pin 0 */
#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_IN_PIN0_Low (0x0UL) /*!< Pin input is low */
#define GPIO_IN_PIN0_High (0x1UL) /*!< Pin input is high */

/* Register: GPIO_DIR */
/* Description: Direction of GPIO pins */

/* Bit 31 : Pin 31 */
#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIR_PIN31_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN31_Output (0x1UL) /*!< Pin set as output */

/* Bit 30 : Pin 30 */
#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIR_PIN30_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN30_Output (0x1UL) /*!< Pin set as output */

/* Bit 29 : Pin 29 */
#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIR_PIN29_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN29_Output (0x1UL) /*!< Pin set as output */

/* Bit 28 : Pin 28 */
#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIR_PIN28_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN28_Output (0x1UL) /*!< Pin set as output */

/* Bit 27 : Pin 27 */
#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIR_PIN27_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN27_Output (0x1UL) /*!< Pin set as output */

/* Bit 26 : Pin 26 */
#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIR_PIN26_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN26_Output (0x1UL) /*!< Pin set as output */

/* Bit 25 : Pin 25 */
#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIR_PIN25_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN25_Output (0x1UL) /*!< Pin set as output */

/* Bit 24 : Pin 24 */
#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIR_PIN24_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN24_Output (0x1UL) /*!< Pin set as output */

/* Bit 23 : Pin 23 */
#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIR_PIN23_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN23_Output (0x1UL) /*!< Pin set as output */

/* Bit 22 : Pin 22 */
#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIR_PIN22_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN22_Output (0x1UL) /*!< Pin set as output */

/* Bit 21 : Pin 21 */
#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIR_PIN21_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN21_Output (0x1UL) /*!< Pin set as output */

/* Bit 20 : Pin 20 */
#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIR_PIN20_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN20_Output (0x1UL) /*!< Pin set as output */

/* Bit 19 : Pin 19 */
#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIR_PIN19_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN19_Output (0x1UL) /*!< Pin set as output */

/* Bit 18 : Pin 18 */
#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIR_PIN18_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN18_Output (0x1UL) /*!< Pin set as output */

/* Bit 17 : Pin 17 */
#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIR_PIN17_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN17_Output (0x1UL) /*!< Pin set as output */

/* Bit 16 : Pin 16 */
#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIR_PIN16_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN16_Output (0x1UL) /*!< Pin set as output */

/* Bit 15 : Pin 15 */
#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIR_PIN15_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN15_Output (0x1UL) /*!< Pin set as output */

/* Bit 14 : Pin 14 */
#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIR_PIN14_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN14_Output (0x1UL) /*!< Pin set as output */

/* Bit 13 : Pin 13 */
#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIR_PIN13_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN13_Output (0x1UL) /*!< Pin set as output */

/* Bit 12 : Pin 12 */
#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIR_PIN12_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN12_Output (0x1UL) /*!< Pin set as output */

/* Bit 11 : Pin 11 */
#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIR_PIN11_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN11_Output (0x1UL) /*!< Pin set as output */

/* Bit 10 : Pin 10 */
#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIR_PIN10_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN10_Output (0x1UL) /*!< Pin set as output */

/* Bit 9 : Pin 9 */
#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIR_PIN9_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN9_Output (0x1UL) /*!< Pin set as output */

/* Bit 8 : Pin 8 */
#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIR_PIN8_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN8_Output (0x1UL) /*!< Pin set as output */

/* Bit 7 : Pin 7 */
#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIR_PIN7_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN7_Output (0x1UL) /*!< Pin set as output */

/* Bit 6 : Pin 6 */
#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIR_PIN6_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN6_Output (0x1UL) /*!< Pin set as output */

/* Bit 5 : Pin 5 */
#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIR_PIN5_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN5_Output (0x1UL) /*!< Pin set as output */

/* Bit 4 : Pin 4 */
#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIR_PIN4_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN4_Output (0x1UL) /*!< Pin set as output */

/* Bit 3 : Pin 3 */
#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIR_PIN3_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN3_Output (0x1UL) /*!< Pin set as output */

/* Bit 2 : Pin 2 */
#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIR_PIN2_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN2_Output (0x1UL) /*!< Pin set as output */

/* Bit 1 : Pin 1 */
#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIR_PIN1_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN1_Output (0x1UL) /*!< Pin set as output */

/* Bit 0 : Pin 0 */
#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIR_PIN0_Input (0x0UL) /*!< Pin set as input */
#define GPIO_DIR_PIN0_Output (0x1UL) /*!< Pin set as output */

/* Register: GPIO_DIRSET */
/* Description: DIR set register */

/* Bit 31 : Set as output pin 31 */
#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIRSET_PIN31_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN31_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 30 : Set as output pin 30 */
#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIRSET_PIN30_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN30_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 29 : Set as output pin 29 */
#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIRSET_PIN29_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN29_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 28 : Set as output pin 28 */
#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIRSET_PIN28_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN28_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 27 : Set as output pin 27 */
#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIRSET_PIN27_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN27_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 26 : Set as output pin 26 */
#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIRSET_PIN26_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN26_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 25 : Set as output pin 25 */
#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIRSET_PIN25_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN25_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 24 : Set as output pin 24 */
#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIRSET_PIN24_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN24_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 23 : Set as output pin 23 */
#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIRSET_PIN23_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN23_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 22 : Set as output pin 22 */
#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIRSET_PIN22_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN22_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 21 : Set as output pin 21 */
#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIRSET_PIN21_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN21_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 20 : Set as output pin 20 */
#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIRSET_PIN20_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN20_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 19 : Set as output pin 19 */
#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIRSET_PIN19_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN19_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 18 : Set as output pin 18 */
#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIRSET_PIN18_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN18_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 17 : Set as output pin 17 */
#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIRSET_PIN17_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN17_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 16 : Set as output pin 16 */
#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIRSET_PIN16_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN16_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 15 : Set as output pin 15 */
#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIRSET_PIN15_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN15_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 14 : Set as output pin 14 */
#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIRSET_PIN14_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN14_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 13 : Set as output pin 13 */
#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIRSET_PIN13_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN13_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 12 : Set as output pin 12 */
#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIRSET_PIN12_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN12_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 11 : Set as output pin 11 */
#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIRSET_PIN11_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN11_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 10 : Set as output pin 10 */
#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIRSET_PIN10_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN10_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 9 : Set as output pin 9 */
#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIRSET_PIN9_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN9_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 8 : Set as output pin 8 */
#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIRSET_PIN8_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN8_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 7 : Set as output pin 7 */
#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIRSET_PIN7_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN7_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 6 : Set as output pin 6 */
#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIRSET_PIN6_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN6_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 5 : Set as output pin 5 */
#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIRSET_PIN5_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN5_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 4 : Set as output pin 4 */
#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIRSET_PIN4_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN4_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 3 : Set as output pin 3 */
#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIRSET_PIN3_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN3_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 2 : Set as output pin 2 */
#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIRSET_PIN2_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN2_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 1 : Set as output pin 1 */
#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIRSET_PIN1_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN1_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Bit 0 : Set as output pin 0 */
#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIRSET_PIN0_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRSET_PIN0_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* Register: GPIO_DIRCLR */
/* Description: DIR clear register */

/* Bit 31 : Set as input pin 31 */
#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_DIRCLR_PIN31_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN31_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 30 : Set as input pin 30 */
#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_DIRCLR_PIN30_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN30_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 29 : Set as input pin 29 */
#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_DIRCLR_PIN29_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN29_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 28 : Set as input pin 28 */
#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_DIRCLR_PIN28_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN28_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 27 : Set as input pin 27 */
#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_DIRCLR_PIN27_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN27_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 26 : Set as input pin 26 */
#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_DIRCLR_PIN26_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN26_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 25 : Set as input pin 25 */
#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_DIRCLR_PIN25_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN25_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 24 : Set as input pin 24 */
#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_DIRCLR_PIN24_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN24_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 23 : Set as input pin 23 */
#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_DIRCLR_PIN23_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN23_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 22 : Set as input pin 22 */
#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_DIRCLR_PIN22_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN22_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 21 : Set as input pin 21 */
#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_DIRCLR_PIN21_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN21_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 20 : Set as input pin 20 */
#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_DIRCLR_PIN20_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN20_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 19 : Set as input pin 19 */
#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_DIRCLR_PIN19_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN19_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 18 : Set as input pin 18 */
#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_DIRCLR_PIN18_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN18_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 17 : Set as input pin 17 */
#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_DIRCLR_PIN17_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN17_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 16 : Set as input pin 16 */
#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_DIRCLR_PIN16_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN16_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 15 : Set as input pin 15 */
#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_DIRCLR_PIN15_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN15_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 14 : Set as input pin 14 */
#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_DIRCLR_PIN14_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN14_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 13 : Set as input pin 13 */
#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_DIRCLR_PIN13_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN13_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 12 : Set as input pin 12 */
#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_DIRCLR_PIN12_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN12_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 11 : Set as input pin 11 */
#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_DIRCLR_PIN11_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN11_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 10 : Set as input pin 10 */
#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_DIRCLR_PIN10_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN10_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 9 : Set as input pin 9 */
#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_DIRCLR_PIN9_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN9_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 8 : Set as input pin 8 */
#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_DIRCLR_PIN8_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN8_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 7 : Set as input pin 7 */
#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_DIRCLR_PIN7_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN7_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 6 : Set as input pin 6 */
#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_DIRCLR_PIN6_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN6_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 5 : Set as input pin 5 */
#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_DIRCLR_PIN5_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN5_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 4 : Set as input pin 4 */
#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_DIRCLR_PIN4_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN4_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 3 : Set as input pin 3 */
#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_DIRCLR_PIN3_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN3_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 2 : Set as input pin 2 */
#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_DIRCLR_PIN2_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN2_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 1 : Set as input pin 1 */
#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_DIRCLR_PIN1_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN1_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Bit 0 : Set as input pin 0 */
#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_DIRCLR_PIN0_Input (0x0UL) /*!< Read: pin set as input */
#define GPIO_DIRCLR_PIN0_Output (0x1UL) /*!< Read: pin set as output */
#define GPIO_DIRCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */

/* Register: GPIO_LATCH */
/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */

/* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define GPIO_LATCH_PIN31_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN31_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define GPIO_LATCH_PIN30_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN30_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define GPIO_LATCH_PIN29_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN29_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define GPIO_LATCH_PIN28_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN28_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define GPIO_LATCH_PIN27_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN27_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define GPIO_LATCH_PIN26_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN26_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define GPIO_LATCH_PIN25_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN25_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define GPIO_LATCH_PIN24_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN24_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define GPIO_LATCH_PIN23_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN23_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define GPIO_LATCH_PIN22_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN22_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define GPIO_LATCH_PIN21_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN21_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define GPIO_LATCH_PIN20_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN20_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define GPIO_LATCH_PIN19_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN19_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define GPIO_LATCH_PIN18_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN18_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define GPIO_LATCH_PIN17_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN17_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define GPIO_LATCH_PIN16_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN16_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define GPIO_LATCH_PIN15_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN15_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define GPIO_LATCH_PIN14_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN14_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define GPIO_LATCH_PIN13_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN13_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define GPIO_LATCH_PIN12_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN12_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define GPIO_LATCH_PIN11_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN11_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define GPIO_LATCH_PIN10_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN10_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define GPIO_LATCH_PIN9_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN9_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define GPIO_LATCH_PIN8_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN8_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define GPIO_LATCH_PIN7_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN7_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define GPIO_LATCH_PIN6_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN6_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define GPIO_LATCH_PIN5_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN5_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define GPIO_LATCH_PIN4_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN4_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define GPIO_LATCH_PIN3_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN3_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define GPIO_LATCH_PIN2_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN2_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define GPIO_LATCH_PIN1_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN1_Latched (0x1UL) /*!< Criteria has been met */

/* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */
#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define GPIO_LATCH_PIN0_NotLatched (0x0UL) /*!< Criteria has not been met */
#define GPIO_LATCH_PIN0_Latched (0x1UL) /*!< Criteria has been met */

/* Register: GPIO_DETECTMODE */
/* Description: Select between default DETECT signal behavior and LDETECT mode */

/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
#define GPIO_DETECTMODE_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */
#define GPIO_DETECTMODE_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */

/* Register: GPIO_DETECTMODE_SEC */
/* Description: Select between default DETECT signal behavior and LDETECT mode */

/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
#define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
#define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
#define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */
#define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */

/* Register: GPIO_PIN_CNF */
/* Description: Description collection: Configuration of GPIO pins */

/* Bits 30..28 : Select which MCU/Subsystem controls this pin Note: this field is only accessible from secure code. */
#define GPIO_PIN_CNF_MCUSEL_Pos (28UL) /*!< Position of MCUSEL field. */
#define GPIO_PIN_CNF_MCUSEL_Msk (0x7UL << GPIO_PIN_CNF_MCUSEL_Pos) /*!< Bit mask of MCUSEL field. */
#define GPIO_PIN_CNF_MCUSEL_AppMCU (0x0UL) /*!< Application MCU */
#define GPIO_PIN_CNF_MCUSEL_NetworkMCU (0x1UL) /*!< Network MCU */
#define GPIO_PIN_CNF_MCUSEL_Peripheral (0x3UL) /*!< Peripheral with dedicated pins */
#define GPIO_PIN_CNF_MCUSEL_TND (0x7UL) /*!< Trace and Debug Subsystem */

/* Bits 17..16 : Pin sensing mechanism */
#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
#define GPIO_PIN_CNF_SENSE_Disabled (0x0UL) /*!< Disabled */
#define GPIO_PIN_CNF_SENSE_High (0x2UL) /*!< Sense for high level */
#define GPIO_PIN_CNF_SENSE_Low (0x3UL) /*!< Sense for low level */

/* Bits 11..8 : Drive configuration */
#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
#define GPIO_PIN_CNF_DRIVE_Msk (0xFUL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
#define GPIO_PIN_CNF_DRIVE_S0S1 (0x0UL) /*!< Standard '0', standard '1' */
#define GPIO_PIN_CNF_DRIVE_H0S1 (0x1UL) /*!< High drive '0', standard '1' */
#define GPIO_PIN_CNF_DRIVE_S0H1 (0x2UL) /*!< Standard '0', high drive '1' */
#define GPIO_PIN_CNF_DRIVE_H0H1 (0x3UL) /*!< High drive '0', high 'drive '1'' */
#define GPIO_PIN_CNF_DRIVE_D0S1 (0x4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */
#define GPIO_PIN_CNF_DRIVE_D0H1 (0x5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
#define GPIO_PIN_CNF_DRIVE_S0D1 (0x6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */
#define GPIO_PIN_CNF_DRIVE_H0D1 (0x7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
#define GPIO_PIN_CNF_DRIVE_E0E1 (0xBUL) /*!< Extra high drive '0', extra high drive '1' */

/* Bits 3..2 : Pull configuration */
#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
#define GPIO_PIN_CNF_PULL_Disabled (0x0UL) /*!< No pull */
#define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull down on pin */
#define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull up on pin */

/* Bit 1 : Connect or disconnect input buffer */
#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
#define GPIO_PIN_CNF_INPUT_Connect (0x0UL) /*!< Connect input buffer */
#define GPIO_PIN_CNF_INPUT_Disconnect (0x1UL) /*!< Disconnect input buffer */

/* Bit 0 : Pin direction. Same physical register as DIR register */
#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
#define GPIO_PIN_CNF_DIR_Input (0x0UL) /*!< Configure pin as an input pin */
#define GPIO_PIN_CNF_DIR_Output (0x1UL) /*!< Configure pin as an output pin */


/* Peripheral: PDM */
/* Description: Pulse Density Modulation (Digital Microphone) Interface 0 */

/* Register: PDM_TASKS_START */
/* Description: Starts continuous PDM transfer */

/* Bit 0 : Starts continuous PDM transfer */
#define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define PDM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */

/* Register: PDM_TASKS_STOP */
/* Description: Stops PDM transfer */

/* Bit 0 : Stops PDM transfer */
#define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define PDM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: PDM_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */

/* Bit 31 :   */
#define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define PDM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
#define PDM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PDM_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define PDM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define PDM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PDM_EVENTS_STARTED */
/* Description: PDM transfer has started */

/* Bit 0 : PDM transfer has started */
#define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
#define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */

/* Register: PDM_EVENTS_STOPPED */
/* Description: PDM transfer has finished */

/* Bit 0 : PDM transfer has finished */
#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */

/* Register: PDM_EVENTS_END */
/* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */

/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
#define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
#define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
#define PDM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */

/* Register: PDM_PUBLISH_STARTED */
/* Description: Publish configuration for event STARTED */

/* Bit 31 :   */
#define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
#define PDM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define PDM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STARTED will publish to */
#define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PDM_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */

/* Bit 31 :   */
#define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
#define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
#define PDM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define PDM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PDM_PUBLISH_END */
/* Description: Publish configuration for event END */

/* Bit 31 :   */
#define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
#define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
#define PDM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */
#define PDM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event END will publish to */
#define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PDM_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 2 : Enable or disable interrupt for event END */
#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTEN_END_Disabled (0x0UL) /*!< Disable */
#define PDM_INTEN_END_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event STOPPED */
#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
#define PDM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event STARTED */
#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */
#define PDM_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */

/* Register: PDM_INTENSET */
/* Description: Enable interrupt */

/* Bit 2 : Write '1' to enable interrupt for event END */
#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
#define PDM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
#define PDM_INTENSET_END_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define PDM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define PDM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event STARTED */
#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define PDM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define PDM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */

/* Register: PDM_INTENCLR */
/* Description: Disable interrupt */

/* Bit 2 : Write '1' to disable interrupt for event END */
#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define PDM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_END_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PDM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event STARTED */
#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define PDM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define PDM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define PDM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */

/* Register: PDM_ENABLE */
/* Description: PDM module enable register */

/* Bit 0 : Enable or disable PDM module */
#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define PDM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
#define PDM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */

/* Register: PDM_PDMCLKCTRL */
/* Description: PDM clock generator control */

/* Bits 31..0 : PDM_CLK frequency configuration. Enumerations are deprecated, use
        PDMCLKCTRL equation to find the register value. The 12 least significant bits of the
        register are ignored and shall be set to zero. */
#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
#define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
#define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
#define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */

/* Register: PDM_MODE */
/* Description: Defines the routing of the connected PDM microphones' signals */

/* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */
#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
#define PDM_MODE_EDGE_LeftFalling (0x0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
#define PDM_MODE_EDGE_LeftRising (0x1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */

/* Bit 0 : Mono or stereo operation */
#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
#define PDM_MODE_OPERATION_Stereo (0x0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */
#define PDM_MODE_OPERATION_Mono (0x1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */

/* Register: PDM_GAINL */
/* Description: Left output gain adjustment */

/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */

/* Register: PDM_GAINR */
/* Description: Right output gain adjustment */

/* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
#define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */

/* Register: PDM_RATIO */
/* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */

/* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
#define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
#define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
#define PDM_RATIO_RATIO_Ratio64 (0x0UL) /*!< Ratio of 64 */
#define PDM_RATIO_RATIO_Ratio80 (0x1UL) /*!< Ratio of 80 */

/* Register: PDM_PSEL_CLK */
/* Description: Pin number configuration for PDM CLK signal */

/* Bit 31 : Connection */
#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define PDM_PSEL_CLK_CONNECT_Connected (0x0UL) /*!< Connect */
#define PDM_PSEL_CLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */
#define PDM_PSEL_CLK_PORT_Msk (0x1UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: PDM_PSEL_DIN */
/* Description: Pin number configuration for PDM DIN signal */

/* Bit 31 : Connection */
#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define PDM_PSEL_DIN_CONNECT_Connected (0x0UL) /*!< Connect */
#define PDM_PSEL_DIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */
#define PDM_PSEL_DIN_PORT_Msk (0x1UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: PDM_MCLKCONFIG */
/* Description: Master clock generator configuration */

/* Bit 0 : Master clock source selection */
#define PDM_MCLKCONFIG_SRC_Pos (0UL) /*!< Position of SRC field. */
#define PDM_MCLKCONFIG_SRC_Msk (0x1UL << PDM_MCLKCONFIG_SRC_Pos) /*!< Bit mask of SRC field. */
#define PDM_MCLKCONFIG_SRC_PCLK32M (0x0UL) /*!< 32 MHz peripheral clock */
#define PDM_MCLKCONFIG_SRC_ACLK (0x1UL) /*!< Audio PLL clock */

/* Register: PDM_SAMPLE_PTR */
/* Description: RAM address pointer to write samples to with EasyDMA */

/* Bits 31..0 : Address to write PDM samples to over DMA */
#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */

/* Register: PDM_SAMPLE_MAXCNT */
/* Description: Number of samples to allocate memory for in EasyDMA mode */

/* Bits 14..0 : Length of DMA RAM allocation in number of samples */
#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */


/* Peripheral: POWER */
/* Description: Power control 0 */

/* Register: POWER_TASKS_CONSTLAT */
/* Description: Enable Constant Latency mode */

/* Bit 0 : Enable Constant Latency mode */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (0x1UL) /*!< Trigger task */

/* Register: POWER_TASKS_LOWPWR */
/* Description: Enable Low-Power mode (variable latency) */

/* Bit 0 : Enable Low-Power mode (variable latency) */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (0x1UL) /*!< Trigger task */

/* Register: POWER_SUBSCRIBE_CONSTLAT */
/* Description: Subscribe configuration for task CONSTLAT */

/* Bit 31 :   */
#define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */
#define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */
#define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0x0UL) /*!< Disable subscription */
#define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */
#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: POWER_SUBSCRIBE_LOWPWR */
/* Description: Subscribe configuration for task LOWPWR */

/* Bit 31 :   */
#define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */
#define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */
#define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0x0UL) /*!< Disable subscription */
#define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */
#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: POWER_EVENTS_POFWARN */
/* Description: Power failure warning */

/* Bit 0 : Power failure warning */
#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0x0UL) /*!< Event not generated */
#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (0x1UL) /*!< Event generated */

/* Register: POWER_EVENTS_SLEEPENTER */
/* Description: CPU entered WFI/WFE sleep */

/* Bit 0 : CPU entered WFI/WFE sleep */
#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0x0UL) /*!< Event not generated */
#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (0x1UL) /*!< Event generated */

/* Register: POWER_EVENTS_SLEEPEXIT */
/* Description: CPU exited WFI/WFE sleep */

/* Bit 0 : CPU exited WFI/WFE sleep */
#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0x0UL) /*!< Event not generated */
#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (0x1UL) /*!< Event generated */

/* Register: POWER_PUBLISH_POFWARN */
/* Description: Publish configuration for event POFWARN */

/* Bit 31 :   */
#define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */
#define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */
#define POWER_PUBLISH_POFWARN_EN_Disabled (0x0UL) /*!< Disable publishing */
#define POWER_PUBLISH_POFWARN_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event POFWARN will publish to */
#define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: POWER_PUBLISH_SLEEPENTER */
/* Description: Publish configuration for event SLEEPENTER */

/* Bit 31 :   */
#define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */
#define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */
#define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0x0UL) /*!< Disable publishing */
#define POWER_PUBLISH_SLEEPENTER_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to */
#define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: POWER_PUBLISH_SLEEPEXIT */
/* Description: Publish configuration for event SLEEPEXIT */

/* Bit 31 :   */
#define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */
#define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */
#define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0x0UL) /*!< Disable publishing */
#define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to */
#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: POWER_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */
#define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
#define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
#define POWER_INTEN_SLEEPEXIT_Disabled (0x0UL) /*!< Disable */
#define POWER_INTEN_SLEEPEXIT_Enabled (0x1UL) /*!< Enable */

/* Bit 5 : Enable or disable interrupt for event SLEEPENTER */
#define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
#define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
#define POWER_INTEN_SLEEPENTER_Disabled (0x0UL) /*!< Disable */
#define POWER_INTEN_SLEEPENTER_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event POFWARN */
#define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
#define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
#define POWER_INTEN_POFWARN_Disabled (0x0UL) /*!< Disable */
#define POWER_INTEN_POFWARN_Enabled (0x1UL) /*!< Enable */

/* Register: POWER_INTENSET */
/* Description: Enable interrupt */

/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
#define POWER_INTENSET_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */
#define POWER_INTENSET_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */
#define POWER_INTENSET_SLEEPEXIT_Set (0x1UL) /*!< Enable */

/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
#define POWER_INTENSET_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */
#define POWER_INTENSET_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */
#define POWER_INTENSET_SLEEPENTER_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event POFWARN */
#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
#define POWER_INTENSET_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */
#define POWER_INTENSET_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */
#define POWER_INTENSET_POFWARN_Set (0x1UL) /*!< Enable */

/* Register: POWER_INTENCLR */
/* Description: Disable interrupt */

/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
#define POWER_INTENCLR_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_SLEEPEXIT_Clear (0x1UL) /*!< Disable */

/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
#define POWER_INTENCLR_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_SLEEPENTER_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event POFWARN */
#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
#define POWER_INTENCLR_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */
#define POWER_INTENCLR_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */
#define POWER_INTENCLR_POFWARN_Clear (0x1UL) /*!< Disable */

/* Register: POWER_GPREGRET */
/* Description: Description collection: General purpose retention register */

/* Bits 7..0 : General purpose retention register */
#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */


/* Peripheral: PWM */
/* Description: Pulse width modulation unit 0 */

/* Register: PWM_TASKS_STOP */
/* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */

/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
#define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define PWM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: PWM_TASKS_SEQSTART */
/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */

/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (0x1UL) /*!< Trigger task */

/* Register: PWM_TASKS_NEXTSTEP */
/* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */

/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (0x1UL) /*!< Trigger task */

/* Register: PWM_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define PWM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define PWM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PWM_SUBSCRIBE_SEQSTART */
/* Description: Description collection: Subscribe configuration for task SEQSTART[n] */

/* Bit 31 :   */
#define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL) /*!< Position of EN field. */
#define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field. */
#define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0x0UL) /*!< Disable subscription */
#define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */
#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PWM_SUBSCRIBE_NEXTSTEP */
/* Description: Subscribe configuration for task NEXTSTEP */

/* Bit 31 :   */
#define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */
#define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */
#define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */
#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PWM_EVENTS_STOPPED */
/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */

/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */

/* Register: PWM_EVENTS_SEQSTARTED */
/* Description: Description collection: First PWM period started on sequence n */

/* Bit 0 : First PWM period started on sequence n */
#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: PWM_EVENTS_SEQEND */
/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */

/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0x0UL) /*!< Event not generated */
#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (0x1UL) /*!< Event generated */

/* Register: PWM_EVENTS_PWMPERIODEND */
/* Description: Emitted at the end of each PWM period */

/* Bit 0 : Emitted at the end of each PWM period */
#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated */
#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated */

/* Register: PWM_EVENTS_LOOPSDONE */
/* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */

/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0x0UL) /*!< Event not generated */
#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (0x1UL) /*!< Event generated */

/* Register: PWM_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */

/* Bit 31 :   */
#define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
#define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
#define PWM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define PWM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PWM_PUBLISH_SEQSTARTED */
/* Description: Description collection: Publish configuration for event SEQSTARTED[n] */

/* Bit 31 :   */
#define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define PWM_PUBLISH_SEQSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to */
#define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PWM_PUBLISH_SEQEND */
/* Description: Description collection: Publish configuration for event SEQEND[n] */

/* Bit 31 :   */
#define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */
#define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */
#define PWM_PUBLISH_SEQEND_EN_Disabled (0x0UL) /*!< Disable publishing */
#define PWM_PUBLISH_SEQEND_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to */
#define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PWM_PUBLISH_PWMPERIODEND */
/* Description: Publish configuration for event PWMPERIODEND */

/* Bit 31 :   */
#define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */
#define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */
#define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0x0UL) /*!< Disable publishing */
#define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to */
#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PWM_PUBLISH_LOOPSDONE */
/* Description: Publish configuration for event LOOPSDONE */

/* Bit 31 :   */
#define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */
#define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */
#define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0x0UL) /*!< Disable publishing */
#define PWM_PUBLISH_LOOPSDONE_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to */
#define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: PWM_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0x0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0x0UL) /*!< Disable shortcut */
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
#define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
#define PWM_SHORTS_SEQEND0_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define PWM_SHORTS_SEQEND0_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: PWM_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTEN_LOOPSDONE_Disabled (0x0UL) /*!< Disable */
#define PWM_INTEN_LOOPSDONE_Enabled (0x1UL) /*!< Enable */

/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTEN_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */
#define PWM_INTEN_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */

/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTEN_SEQEND1_Disabled (0x0UL) /*!< Disable */
#define PWM_INTEN_SEQEND1_Enabled (0x1UL) /*!< Enable */

/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTEN_SEQEND0_Disabled (0x0UL) /*!< Disable */
#define PWM_INTEN_SEQEND0_Enabled (0x1UL) /*!< Enable */

/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTEN_SEQSTARTED1_Disabled (0x0UL) /*!< Disable */
#define PWM_INTEN_SEQSTARTED1_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTEN_SEQSTARTED0_Disabled (0x0UL) /*!< Disable */
#define PWM_INTEN_SEQSTARTED0_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event STOPPED */
#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
#define PWM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */

/* Register: PWM_INTENSET */
/* Description: Enable interrupt */

/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTENSET_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENSET_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENSET_LOOPSDONE_Set (0x1UL) /*!< Enable */

/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENSET_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENSET_PWMPERIODEND_Set (0x1UL) /*!< Enable */

/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTENSET_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQEND1_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTENSET_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQEND0_Set (0x1UL) /*!< Enable */

/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTENSET_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQSTARTED1_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTENSET_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENSET_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENSET_SEQSTARTED0_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */

/* Register: PWM_INTENCLR */
/* Description: Disable interrupt */

/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
#define PWM_INTENCLR_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_LOOPSDONE_Clear (0x1UL) /*!< Disable */

/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
#define PWM_INTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_PWMPERIODEND_Clear (0x1UL) /*!< Disable */

/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
#define PWM_INTENCLR_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQEND1_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
#define PWM_INTENCLR_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQEND0_Clear (0x1UL) /*!< Disable */

/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
#define PWM_INTENCLR_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQSTARTED1_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
#define PWM_INTENCLR_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_SEQSTARTED0_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define PWM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define PWM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define PWM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */

/* Register: PWM_ENABLE */
/* Description: PWM module enable register */

/* Bit 0 : Enable or disable PWM module */
#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define PWM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disabled */
#define PWM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */

/* Register: PWM_MODE */
/* Description: Selects operating mode of the wave counter */

/* Bit 0 : Selects up mode or up-and-down mode for the counter */
#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
#define PWM_MODE_UPDOWN_Up (0x0UL) /*!< Up counter, edge-aligned PWM duty cycle */
#define PWM_MODE_UPDOWN_UpAndDown (0x1UL) /*!< Up and down counter, center-aligned PWM duty cycle */

/* Register: PWM_COUNTERTOP */
/* Description: Value up to which the pulse generator counter counts */

/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */

/* Register: PWM_PRESCALER */
/* Description: Configuration for PWM_CLK */

/* Bits 2..0 : Prescaler of PWM_CLK */
#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
#define PWM_PRESCALER_PRESCALER_DIV_1 (0x0UL) /*!< Divide by 1 (16 MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_2 (0x1UL) /*!< Divide by 2 (8 MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_4 (0x2UL) /*!< Divide by 4 (4 MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_8 (0x3UL) /*!< Divide by 8 (2 MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_16 (0x4UL) /*!< Divide by 16 (1 MHz) */
#define PWM_PRESCALER_PRESCALER_DIV_32 (0x5UL) /*!< Divide by 32 (500 kHz) */
#define PWM_PRESCALER_PRESCALER_DIV_64 (0x6UL) /*!< Divide by 64 (250 kHz) */
#define PWM_PRESCALER_PRESCALER_DIV_128 (0x7UL) /*!< Divide by 128 (125 kHz) */

/* Register: PWM_DECODER */
/* Description: Configuration of the decoder */

/* Bit 8 : Selects source for advancing the active sequence */
#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
#define PWM_DECODER_MODE_RefreshCount (0x0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
#define PWM_DECODER_MODE_NextStep (0x1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */

/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
#define PWM_DECODER_LOAD_Common (0x0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
#define PWM_DECODER_LOAD_Grouped (0x1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
#define PWM_DECODER_LOAD_Individual (0x2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
#define PWM_DECODER_LOAD_WaveForm (0x3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */

/* Register: PWM_LOOP */
/* Description: Number of playbacks of a loop */

/* Bits 15..0 : Number of playbacks of pattern cycles */
#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
#define PWM_LOOP_CNT_Disabled (0x0000UL) /*!< Looping disabled (stop at the end of the sequence) */

/* Register: PWM_SEQ_PTR */
/* Description: Description cluster: Beginning address in RAM of this sequence */

/* Bits 31..0 : Beginning address in RAM of this sequence */
#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: PWM_SEQ_CNT */
/* Description: Description cluster: Number of values (duty cycles) in this sequence */

/* Bits 14..0 : Number of values (duty cycles) in this sequence */
#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
#define PWM_SEQ_CNT_CNT_Disabled (0x0000UL) /*!< Sequence is disabled, and shall not be started as it is empty */

/* Register: PWM_SEQ_REFRESH */
/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */

/* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
#define PWM_SEQ_REFRESH_CNT_Continuous (0x000000UL) /*!< Update every PWM period */

/* Register: PWM_SEQ_ENDDELAY */
/* Description: Description cluster: Time added after the sequence */

/* Bits 23..0 : Time added after the sequence in PWM periods */
#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */

/* Register: PWM_PSEL_OUT */
/* Description: Description collection: Output pin select for PWM channel n */

/* Bit 31 : Connection */
#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define PWM_PSEL_OUT_CONNECT_Connected (0x0UL) /*!< Connect */
#define PWM_PSEL_OUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */
#define PWM_PSEL_OUT_PORT_Msk (0x1UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */


/* Peripheral: QDEC */
/* Description: Quadrature Decoder 0 */

/* Register: QDEC_TASKS_START */
/* Description: Task starting the quadrature decoder */

/* Bit 0 : Task starting the quadrature decoder */
#define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define QDEC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */

/* Register: QDEC_TASKS_STOP */
/* Description: Task stopping the quadrature decoder */

/* Bit 0 : Task stopping the quadrature decoder */
#define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: QDEC_TASKS_READCLRACC */
/* Description: Read and clear ACC and ACCDBL */

/* Bit 0 : Read and clear ACC and ACCDBL */
#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */
#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */
#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (0x1UL) /*!< Trigger task */

/* Register: QDEC_TASKS_RDCLRACC */
/* Description: Read and clear ACC */

/* Bit 0 : Read and clear ACC */
#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */
#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */
#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (0x1UL) /*!< Trigger task */

/* Register: QDEC_TASKS_RDCLRDBL */
/* Description: Read and clear ACCDBL */

/* Bit 0 : Read and clear ACCDBL */
#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */
#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */
#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (0x1UL) /*!< Trigger task */

/* Register: QDEC_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */

/* Bit 31 :   */
#define QDEC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define QDEC_SUBSCRIBE_START_EN_Msk (0x1UL << QDEC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define QDEC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
#define QDEC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define QDEC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QDEC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QDEC_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define QDEC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define QDEC_SUBSCRIBE_STOP_EN_Msk (0x1UL << QDEC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define QDEC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define QDEC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define QDEC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QDEC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QDEC_SUBSCRIBE_READCLRACC */
/* Description: Subscribe configuration for task READCLRACC */

/* Bit 31 :   */
#define QDEC_SUBSCRIBE_READCLRACC_EN_Pos (31UL) /*!< Position of EN field. */
#define QDEC_SUBSCRIBE_READCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_READCLRACC_EN_Pos) /*!< Bit mask of EN field. */
#define QDEC_SUBSCRIBE_READCLRACC_EN_Disabled (0x0UL) /*!< Disable subscription */
#define QDEC_SUBSCRIBE_READCLRACC_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task READCLRACC will subscribe to */
#define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QDEC_SUBSCRIBE_RDCLRACC */
/* Description: Subscribe configuration for task RDCLRACC */

/* Bit 31 :   */
#define QDEC_SUBSCRIBE_RDCLRACC_EN_Pos (31UL) /*!< Position of EN field. */
#define QDEC_SUBSCRIBE_RDCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRACC_EN_Pos) /*!< Bit mask of EN field. */
#define QDEC_SUBSCRIBE_RDCLRACC_EN_Disabled (0x0UL) /*!< Disable subscription */
#define QDEC_SUBSCRIBE_RDCLRACC_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task RDCLRACC will subscribe to */
#define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QDEC_SUBSCRIBE_RDCLRDBL */
/* Description: Subscribe configuration for task RDCLRDBL */

/* Bit 31 :   */
#define QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos (31UL) /*!< Position of EN field. */
#define QDEC_SUBSCRIBE_RDCLRDBL_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos) /*!< Bit mask of EN field. */
#define QDEC_SUBSCRIBE_RDCLRDBL_EN_Disabled (0x0UL) /*!< Disable subscription */
#define QDEC_SUBSCRIBE_RDCLRDBL_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task RDCLRDBL will subscribe to */
#define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QDEC_EVENTS_SAMPLERDY */
/* Description: Event being generated for every new sample value written to the SAMPLE register */

/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */
#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */
#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0x0UL) /*!< Event not generated */
#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (0x1UL) /*!< Event generated */

/* Register: QDEC_EVENTS_REPORTRDY */
/* Description: Non-null report ready */

/* Bit 0 : Non-null report ready */
#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */
#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */
#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0x0UL) /*!< Event not generated */
#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (0x1UL) /*!< Event generated */

/* Register: QDEC_EVENTS_ACCOF */
/* Description: ACC or ACCDBL register overflow */

/* Bit 0 : ACC or ACCDBL register overflow */
#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */
#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */
#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0x0UL) /*!< Event not generated */
#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (0x1UL) /*!< Event generated */

/* Register: QDEC_EVENTS_DBLRDY */
/* Description: Double displacement(s) detected */

/* Bit 0 : Double displacement(s) detected */
#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */
#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */
#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0x0UL) /*!< Event not generated */
#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (0x1UL) /*!< Event generated */

/* Register: QDEC_EVENTS_STOPPED */
/* Description: QDEC has been stopped */

/* Bit 0 : QDEC has been stopped */
#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */

/* Register: QDEC_PUBLISH_SAMPLERDY */
/* Description: Publish configuration for event SAMPLERDY */

/* Bit 31 :   */
#define QDEC_PUBLISH_SAMPLERDY_EN_Pos (31UL) /*!< Position of EN field. */
#define QDEC_PUBLISH_SAMPLERDY_EN_Msk (0x1UL << QDEC_PUBLISH_SAMPLERDY_EN_Pos) /*!< Bit mask of EN field. */
#define QDEC_PUBLISH_SAMPLERDY_EN_Disabled (0x0UL) /*!< Disable publishing */
#define QDEC_PUBLISH_SAMPLERDY_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event SAMPLERDY will publish to */
#define QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QDEC_PUBLISH_SAMPLERDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QDEC_PUBLISH_REPORTRDY */
/* Description: Publish configuration for event REPORTRDY */

/* Bit 31 :   */
#define QDEC_PUBLISH_REPORTRDY_EN_Pos (31UL) /*!< Position of EN field. */
#define QDEC_PUBLISH_REPORTRDY_EN_Msk (0x1UL << QDEC_PUBLISH_REPORTRDY_EN_Pos) /*!< Bit mask of EN field. */
#define QDEC_PUBLISH_REPORTRDY_EN_Disabled (0x0UL) /*!< Disable publishing */
#define QDEC_PUBLISH_REPORTRDY_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event REPORTRDY will publish to */
#define QDEC_PUBLISH_REPORTRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QDEC_PUBLISH_REPORTRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_REPORTRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QDEC_PUBLISH_ACCOF */
/* Description: Publish configuration for event ACCOF */

/* Bit 31 :   */
#define QDEC_PUBLISH_ACCOF_EN_Pos (31UL) /*!< Position of EN field. */
#define QDEC_PUBLISH_ACCOF_EN_Msk (0x1UL << QDEC_PUBLISH_ACCOF_EN_Pos) /*!< Bit mask of EN field. */
#define QDEC_PUBLISH_ACCOF_EN_Disabled (0x0UL) /*!< Disable publishing */
#define QDEC_PUBLISH_ACCOF_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ACCOF will publish to */
#define QDEC_PUBLISH_ACCOF_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QDEC_PUBLISH_ACCOF_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_ACCOF_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QDEC_PUBLISH_DBLRDY */
/* Description: Publish configuration for event DBLRDY */

/* Bit 31 :   */
#define QDEC_PUBLISH_DBLRDY_EN_Pos (31UL) /*!< Position of EN field. */
#define QDEC_PUBLISH_DBLRDY_EN_Msk (0x1UL << QDEC_PUBLISH_DBLRDY_EN_Pos) /*!< Bit mask of EN field. */
#define QDEC_PUBLISH_DBLRDY_EN_Disabled (0x0UL) /*!< Disable publishing */
#define QDEC_PUBLISH_DBLRDY_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event DBLRDY will publish to */
#define QDEC_PUBLISH_DBLRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QDEC_PUBLISH_DBLRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_DBLRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QDEC_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */

/* Bit 31 :   */
#define QDEC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
#define QDEC_PUBLISH_STOPPED_EN_Msk (0x1UL << QDEC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
#define QDEC_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define QDEC_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define QDEC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QDEC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QDEC_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 5 : Shortcut between event DBLRDY and task STOP */
#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_DBLRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0x0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 3 : Shortcut between event REPORTRDY and task STOP */
#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0x0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */
#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut */
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: QDEC_INTENSET */
/* Description: Enable interrupt */

/* Bit 4 : Write '1' to enable interrupt for event STOPPED */
#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define QDEC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */

/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */
#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
#define QDEC_INTENSET_DBLRDY_Disabled (0x0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_DBLRDY_Enabled (0x1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_DBLRDY_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event ACCOF */
#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
#define QDEC_INTENSET_ACCOF_Disabled (0x0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_ACCOF_Enabled (0x1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_ACCOF_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
#define QDEC_INTENSET_REPORTRDY_Disabled (0x0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_REPORTRDY_Enabled (0x1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_REPORTRDY_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
#define QDEC_INTENSET_SAMPLERDY_Disabled (0x0UL) /*!< Read: Disabled */
#define QDEC_INTENSET_SAMPLERDY_Enabled (0x1UL) /*!< Read: Enabled */
#define QDEC_INTENSET_SAMPLERDY_Set (0x1UL) /*!< Enable */

/* Register: QDEC_INTENCLR */
/* Description: Disable interrupt */

/* Bit 4 : Write '1' to disable interrupt for event STOPPED */
#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define QDEC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */

/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */
#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
#define QDEC_INTENCLR_DBLRDY_Disabled (0x0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_DBLRDY_Enabled (0x1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_DBLRDY_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event ACCOF */
#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
#define QDEC_INTENCLR_ACCOF_Disabled (0x0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_ACCOF_Enabled (0x1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_ACCOF_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
#define QDEC_INTENCLR_REPORTRDY_Disabled (0x0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_REPORTRDY_Enabled (0x1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_REPORTRDY_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
#define QDEC_INTENCLR_SAMPLERDY_Disabled (0x0UL) /*!< Read: Disabled */
#define QDEC_INTENCLR_SAMPLERDY_Enabled (0x1UL) /*!< Read: Enabled */
#define QDEC_INTENCLR_SAMPLERDY_Clear (0x1UL) /*!< Disable */

/* Register: QDEC_ENABLE */
/* Description: Enable the quadrature decoder */

/* Bit 0 : Enable or disable the quadrature decoder */
#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define QDEC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */
#define QDEC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */

/* Register: QDEC_LEDPOL */
/* Description: LED output pin polarity */

/* Bit 0 : LED output pin polarity */
#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
#define QDEC_LEDPOL_LEDPOL_ActiveLow (0x0UL) /*!< Led active on output pin low */
#define QDEC_LEDPOL_LEDPOL_ActiveHigh (0x1UL) /*!< Led active on output pin high */

/* Register: QDEC_SAMPLEPER */
/* Description: Sample period */

/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x0UL) /*!< 128 us */
#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x1UL) /*!< 256 us */
#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x2UL) /*!< 512 us */
#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x3UL) /*!< 1024 us */
#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x4UL) /*!< 2048 us */
#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x5UL) /*!< 4096 us */
#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x6UL) /*!< 8192 us */
#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x7UL) /*!< 16384 us */
#define QDEC_SAMPLEPER_SAMPLEPER_32ms (0x8UL) /*!< 32768 us */
#define QDEC_SAMPLEPER_SAMPLEPER_65ms (0x9UL) /*!< 65536 us */
#define QDEC_SAMPLEPER_SAMPLEPER_131ms (0xAUL) /*!< 131072 us */

/* Register: QDEC_SAMPLE */
/* Description: Motion sample value */

/* Bits 31..0 : Last motion sample */
#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */

/* Register: QDEC_REPORTPER */
/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */

/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */
#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
#define QDEC_REPORTPER_REPORTPER_10Smpl (0x0UL) /*!< 10 samples/report */
#define QDEC_REPORTPER_REPORTPER_40Smpl (0x1UL) /*!< 40 samples/report */
#define QDEC_REPORTPER_REPORTPER_80Smpl (0x2UL) /*!< 80 samples/report */
#define QDEC_REPORTPER_REPORTPER_120Smpl (0x3UL) /*!< 120 samples/report */
#define QDEC_REPORTPER_REPORTPER_160Smpl (0x4UL) /*!< 160 samples/report */
#define QDEC_REPORTPER_REPORTPER_200Smpl (0x5UL) /*!< 200 samples/report */
#define QDEC_REPORTPER_REPORTPER_240Smpl (0x6UL) /*!< 240 samples/report */
#define QDEC_REPORTPER_REPORTPER_280Smpl (0x7UL) /*!< 280 samples/report */
#define QDEC_REPORTPER_REPORTPER_1Smpl (0x8UL) /*!< 1 sample/report */

/* Register: QDEC_ACC */
/* Description: Register accumulating the valid transitions */

/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */
#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */

/* Register: QDEC_ACCREAD */
/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */

/* Bits 31..0 : Snapshot of the ACC register. */
#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */

/* Register: QDEC_PSEL_LED */
/* Description: Pin select for LED signal */

/* Bit 31 : Connection */
#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QDEC_PSEL_LED_CONNECT_Connected (0x0UL) /*!< Connect */
#define QDEC_PSEL_LED_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */
#define QDEC_PSEL_LED_PORT_Msk (0x1UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: QDEC_PSEL_A */
/* Description: Pin select for A signal */

/* Bit 31 : Connection */
#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QDEC_PSEL_A_CONNECT_Connected (0x0UL) /*!< Connect */
#define QDEC_PSEL_A_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */
#define QDEC_PSEL_A_PORT_Msk (0x1UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: QDEC_PSEL_B */
/* Description: Pin select for B signal */

/* Bit 31 : Connection */
#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QDEC_PSEL_B_CONNECT_Connected (0x0UL) /*!< Connect */
#define QDEC_PSEL_B_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */
#define QDEC_PSEL_B_PORT_Msk (0x1UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: QDEC_DBFEN */
/* Description: Enable input debounce filters */

/* Bit 0 : Enable input debounce filters */
#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
#define QDEC_DBFEN_DBFEN_Disabled (0x0UL) /*!< Debounce input filters disabled */
#define QDEC_DBFEN_DBFEN_Enabled (0x1UL) /*!< Debounce input filters enabled */

/* Register: QDEC_LEDPRE */
/* Description: Time period the LED is switched ON prior to sampling */

/* Bits 8..0 : Period in us the LED is switched on prior to sampling */
#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */

/* Register: QDEC_ACCDBL */
/* Description: Register accumulating the number of detected double transitions */

/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */

/* Register: QDEC_ACCDBLREAD */
/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */

/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */


/* Peripheral: QSPI */
/* Description: External flash interface 0 */

/* Register: QSPI_TASKS_ACTIVATE */
/* Description: Activate QSPI interface */

/* Bit 0 : Activate QSPI interface */
#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (0x1UL) /*!< Trigger task */

/* Register: QSPI_TASKS_READSTART */
/* Description: Start transfer from external flash memory to internal RAM */

/* Bit 0 : Start transfer from external flash memory to internal RAM */
#define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL) /*!< Position of TASKS_READSTART field. */
#define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos) /*!< Bit mask of TASKS_READSTART field. */
#define QSPI_TASKS_READSTART_TASKS_READSTART_Trigger (0x1UL) /*!< Trigger task */

/* Register: QSPI_TASKS_WRITESTART */
/* Description: Start transfer from internal RAM to external flash memory */

/* Bit 0 : Start transfer from internal RAM to external flash memory */
#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL) /*!< Position of TASKS_WRITESTART field. */
#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos) /*!< Bit mask of TASKS_WRITESTART field. */
#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Trigger (0x1UL) /*!< Trigger task */

/* Register: QSPI_TASKS_ERASESTART */
/* Description: Start external flash memory erase operation */

/* Bit 0 : Start external flash memory erase operation */
#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL) /*!< Position of TASKS_ERASESTART field. */
#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos) /*!< Bit mask of TASKS_ERASESTART field. */
#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Trigger (0x1UL) /*!< Trigger task */

/* Register: QSPI_TASKS_DEACTIVATE */
/* Description: Deactivate QSPI interface */

/* Bit 0 : Deactivate QSPI interface */
#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL) /*!< Position of TASKS_DEACTIVATE field. */
#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos) /*!< Bit mask of TASKS_DEACTIVATE field. */
#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Trigger (0x1UL) /*!< Trigger task */

/* Register: QSPI_SUBSCRIBE_ACTIVATE */
/* Description: Subscribe configuration for task ACTIVATE */

/* Bit 31 :   */
#define QSPI_SUBSCRIBE_ACTIVATE_EN_Pos (31UL) /*!< Position of EN field. */
#define QSPI_SUBSCRIBE_ACTIVATE_EN_Msk (0x1UL << QSPI_SUBSCRIBE_ACTIVATE_EN_Pos) /*!< Bit mask of EN field. */
#define QSPI_SUBSCRIBE_ACTIVATE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define QSPI_SUBSCRIBE_ACTIVATE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task ACTIVATE will subscribe to */
#define QSPI_SUBSCRIBE_ACTIVATE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QSPI_SUBSCRIBE_ACTIVATE_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_ACTIVATE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QSPI_SUBSCRIBE_READSTART */
/* Description: Subscribe configuration for task READSTART */

/* Bit 31 :   */
#define QSPI_SUBSCRIBE_READSTART_EN_Pos (31UL) /*!< Position of EN field. */
#define QSPI_SUBSCRIBE_READSTART_EN_Msk (0x1UL << QSPI_SUBSCRIBE_READSTART_EN_Pos) /*!< Bit mask of EN field. */
#define QSPI_SUBSCRIBE_READSTART_EN_Disabled (0x0UL) /*!< Disable subscription */
#define QSPI_SUBSCRIBE_READSTART_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task READSTART will subscribe to */
#define QSPI_SUBSCRIBE_READSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QSPI_SUBSCRIBE_READSTART_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_READSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QSPI_SUBSCRIBE_WRITESTART */
/* Description: Subscribe configuration for task WRITESTART */

/* Bit 31 :   */
#define QSPI_SUBSCRIBE_WRITESTART_EN_Pos (31UL) /*!< Position of EN field. */
#define QSPI_SUBSCRIBE_WRITESTART_EN_Msk (0x1UL << QSPI_SUBSCRIBE_WRITESTART_EN_Pos) /*!< Bit mask of EN field. */
#define QSPI_SUBSCRIBE_WRITESTART_EN_Disabled (0x0UL) /*!< Disable subscription */
#define QSPI_SUBSCRIBE_WRITESTART_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task WRITESTART will subscribe to */
#define QSPI_SUBSCRIBE_WRITESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QSPI_SUBSCRIBE_WRITESTART_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_WRITESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QSPI_SUBSCRIBE_ERASESTART */
/* Description: Subscribe configuration for task ERASESTART */

/* Bit 31 :   */
#define QSPI_SUBSCRIBE_ERASESTART_EN_Pos (31UL) /*!< Position of EN field. */
#define QSPI_SUBSCRIBE_ERASESTART_EN_Msk (0x1UL << QSPI_SUBSCRIBE_ERASESTART_EN_Pos) /*!< Bit mask of EN field. */
#define QSPI_SUBSCRIBE_ERASESTART_EN_Disabled (0x0UL) /*!< Disable subscription */
#define QSPI_SUBSCRIBE_ERASESTART_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task ERASESTART will subscribe to */
#define QSPI_SUBSCRIBE_ERASESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QSPI_SUBSCRIBE_ERASESTART_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_ERASESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QSPI_SUBSCRIBE_DEACTIVATE */
/* Description: Subscribe configuration for task DEACTIVATE */

/* Bit 31 :   */
#define QSPI_SUBSCRIBE_DEACTIVATE_EN_Pos (31UL) /*!< Position of EN field. */
#define QSPI_SUBSCRIBE_DEACTIVATE_EN_Msk (0x1UL << QSPI_SUBSCRIBE_DEACTIVATE_EN_Pos) /*!< Bit mask of EN field. */
#define QSPI_SUBSCRIBE_DEACTIVATE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define QSPI_SUBSCRIBE_DEACTIVATE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task DEACTIVATE will subscribe to */
#define QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QSPI_EVENTS_READY */
/* Description: QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. */

/* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. */
#define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
#define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
#define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */
#define QSPI_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */

/* Register: QSPI_PUBLISH_READY */
/* Description: Publish configuration for event READY */

/* Bit 31 :   */
#define QSPI_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */
#define QSPI_PUBLISH_READY_EN_Msk (0x1UL << QSPI_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */
#define QSPI_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */
#define QSPI_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event READY will publish to */
#define QSPI_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define QSPI_PUBLISH_READY_CHIDX_Msk (0xFFUL << QSPI_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: QSPI_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 0 : Enable or disable interrupt for event READY */
#define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
#define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */
#define QSPI_INTEN_READY_Disabled (0x0UL) /*!< Disable */
#define QSPI_INTEN_READY_Enabled (0x1UL) /*!< Enable */

/* Register: QSPI_INTENSET */
/* Description: Enable interrupt */

/* Bit 0 : Write '1' to enable interrupt for event READY */
#define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
#define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
#define QSPI_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */
#define QSPI_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */
#define QSPI_INTENSET_READY_Set (0x1UL) /*!< Enable */

/* Register: QSPI_INTENCLR */
/* Description: Disable interrupt */

/* Bit 0 : Write '1' to disable interrupt for event READY */
#define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
#define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
#define QSPI_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */
#define QSPI_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */
#define QSPI_INTENCLR_READY_Clear (0x1UL) /*!< Disable */

/* Register: QSPI_ENABLE */
/* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */

/* Bit 0 : Enable or disable QSPI */
#define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define QSPI_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable QSPI */
#define QSPI_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable QSPI */

/* Register: QSPI_READ_SRC */
/* Description: Flash memory source address */

/* Bits 31..0 : Word-aligned flash memory source address. */
#define QSPI_READ_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
#define QSPI_READ_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_READ_SRC_SRC_Pos) /*!< Bit mask of SRC field. */

/* Register: QSPI_READ_DST */
/* Description: RAM destination address */

/* Bits 31..0 : Word-aligned RAM destination address. */
#define QSPI_READ_DST_DST_Pos (0UL) /*!< Position of DST field. */
#define QSPI_READ_DST_DST_Msk (0xFFFFFFFFUL << QSPI_READ_DST_DST_Pos) /*!< Bit mask of DST field. */

/* Register: QSPI_READ_CNT */
/* Description: Read transfer length */

/* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */
#define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
#define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */

/* Register: QSPI_WRITE_DST */
/* Description: Flash destination address */

/* Bits 31..0 : Word-aligned flash destination address. */
#define QSPI_WRITE_DST_DST_Pos (0UL) /*!< Position of DST field. */
#define QSPI_WRITE_DST_DST_Msk (0xFFFFFFFFUL << QSPI_WRITE_DST_DST_Pos) /*!< Bit mask of DST field. */

/* Register: QSPI_WRITE_SRC */
/* Description: RAM source address */

/* Bits 31..0 : Word-aligned RAM source address. */
#define QSPI_WRITE_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
#define QSPI_WRITE_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_WRITE_SRC_SRC_Pos) /*!< Bit mask of SRC field. */

/* Register: QSPI_WRITE_CNT */
/* Description: Write transfer length */

/* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */
#define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
#define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */

/* Register: QSPI_ERASE_PTR */
/* Description: Start address of flash block to be erased */

/* Bits 31..0 : Word-aligned start address of block to be erased. */
#define QSPI_ERASE_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define QSPI_ERASE_PTR_PTR_Msk (0xFFFFFFFFUL << QSPI_ERASE_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: QSPI_ERASE_LEN */
/* Description: Size of block to be erased. */

/* Bits 1..0 : LEN */
#define QSPI_ERASE_LEN_LEN_Pos (0UL) /*!< Position of LEN field. */
#define QSPI_ERASE_LEN_LEN_Msk (0x3UL << QSPI_ERASE_LEN_LEN_Pos) /*!< Bit mask of LEN field. */
#define QSPI_ERASE_LEN_LEN_4KB (0x0UL) /*!< Erase 4 kB block (flash command 0x20) */
#define QSPI_ERASE_LEN_LEN_64KB (0x1UL) /*!< Erase 64 kB block (flash command 0xD8) */
#define QSPI_ERASE_LEN_LEN_All (0x2UL) /*!< Erase all (flash command 0xC7) */

/* Register: QSPI_PSEL_SCK */
/* Description: Pin select for serial clock SCK */

/* Bit 31 : Connection */
#define QSPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QSPI_PSEL_SCK_CONNECT_Msk (0x1UL << QSPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QSPI_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
#define QSPI_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define QSPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
#define QSPI_PSEL_SCK_PORT_Msk (0x1UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define QSPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QSPI_PSEL_SCK_PIN_Msk (0x1FUL << QSPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: QSPI_PSEL_CSN */
/* Description: Pin select for chip select signal CSN. */

/* Bit 31 : Connection */
#define QSPI_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QSPI_PSEL_CSN_CONNECT_Msk (0x1UL << QSPI_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QSPI_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */
#define QSPI_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define QSPI_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
#define QSPI_PSEL_CSN_PORT_Msk (0x1UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define QSPI_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QSPI_PSEL_CSN_PIN_Msk (0x1FUL << QSPI_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: QSPI_PSEL_IO0 */
/* Description: Pin select for serial data MOSI/IO0. */

/* Bit 31 : Connection */
#define QSPI_PSEL_IO0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QSPI_PSEL_IO0_CONNECT_Msk (0x1UL << QSPI_PSEL_IO0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QSPI_PSEL_IO0_CONNECT_Connected (0x0UL) /*!< Connect */
#define QSPI_PSEL_IO0_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define QSPI_PSEL_IO0_PORT_Pos (5UL) /*!< Position of PORT field. */
#define QSPI_PSEL_IO0_PORT_Msk (0x1UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define QSPI_PSEL_IO0_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QSPI_PSEL_IO0_PIN_Msk (0x1FUL << QSPI_PSEL_IO0_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: QSPI_PSEL_IO1 */
/* Description: Pin select for serial data MISO/IO1. */

/* Bit 31 : Connection */
#define QSPI_PSEL_IO1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QSPI_PSEL_IO1_CONNECT_Msk (0x1UL << QSPI_PSEL_IO1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QSPI_PSEL_IO1_CONNECT_Connected (0x0UL) /*!< Connect */
#define QSPI_PSEL_IO1_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define QSPI_PSEL_IO1_PORT_Pos (5UL) /*!< Position of PORT field. */
#define QSPI_PSEL_IO1_PORT_Msk (0x1UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define QSPI_PSEL_IO1_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: QSPI_PSEL_IO2 */
/* Description: Pin select for serial data WP/IO2. */

/* Bit 31 : Connection */
#define QSPI_PSEL_IO2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QSPI_PSEL_IO2_CONNECT_Msk (0x1UL << QSPI_PSEL_IO2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QSPI_PSEL_IO2_CONNECT_Connected (0x0UL) /*!< Connect */
#define QSPI_PSEL_IO2_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define QSPI_PSEL_IO2_PORT_Pos (5UL) /*!< Position of PORT field. */
#define QSPI_PSEL_IO2_PORT_Msk (0x1UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define QSPI_PSEL_IO2_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: QSPI_PSEL_IO3 */
/* Description: Pin select for serial data HOLD/IO3. */

/* Bit 31 : Connection */
#define QSPI_PSEL_IO3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define QSPI_PSEL_IO3_CONNECT_Msk (0x1UL << QSPI_PSEL_IO3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define QSPI_PSEL_IO3_CONNECT_Connected (0x0UL) /*!< Connect */
#define QSPI_PSEL_IO3_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define QSPI_PSEL_IO3_PORT_Pos (5UL) /*!< Position of PORT field. */
#define QSPI_PSEL_IO3_PORT_Msk (0x1UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define QSPI_PSEL_IO3_PIN_Pos (0UL) /*!< Position of PIN field. */
#define QSPI_PSEL_IO3_PIN_Msk (0x1FUL << QSPI_PSEL_IO3_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: QSPI_XIPOFFSET */
/* Description: Address offset into the external memory for Execute in Place operation. */

/* Bits 31..0 : Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. */
#define QSPI_XIPOFFSET_XIPOFFSET_Pos (0UL) /*!< Position of XIPOFFSET field. */
#define QSPI_XIPOFFSET_XIPOFFSET_Msk (0xFFFFFFFFUL << QSPI_XIPOFFSET_XIPOFFSET_Pos) /*!< Bit mask of XIPOFFSET field. */

/* Register: QSPI_IFCONFIG0 */
/* Description: Interface configuration. */

/* Bit 12 : Page size for commands PP, PP2O, PP4O and PP4IO. */
#define QSPI_IFCONFIG0_PPSIZE_Pos (12UL) /*!< Position of PPSIZE field. */
#define QSPI_IFCONFIG0_PPSIZE_Msk (0x1UL << QSPI_IFCONFIG0_PPSIZE_Pos) /*!< Bit mask of PPSIZE field. */
#define QSPI_IFCONFIG0_PPSIZE_256Bytes (0x0UL) /*!< 256 bytes. */
#define QSPI_IFCONFIG0_PPSIZE_512Bytes (0x1UL) /*!< 512 bytes. */

/* Bit 7 : Enable deep power-down mode (DPM) feature. */
#define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL) /*!< Position of DPMENABLE field. */
#define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos) /*!< Bit mask of DPMENABLE field. */
#define QSPI_IFCONFIG0_DPMENABLE_Disable (0x0UL) /*!< Disable DPM feature. */
#define QSPI_IFCONFIG0_DPMENABLE_Enable (0x1UL) /*!< Enable DPM feature. */

/* Bit 6 : Addressing mode. */
#define QSPI_IFCONFIG0_ADDRMODE_Pos (6UL) /*!< Position of ADDRMODE field. */
#define QSPI_IFCONFIG0_ADDRMODE_Msk (0x1UL << QSPI_IFCONFIG0_ADDRMODE_Pos) /*!< Bit mask of ADDRMODE field. */
#define QSPI_IFCONFIG0_ADDRMODE_24BIT (0x0UL) /*!< 24-bit addressing. */
#define QSPI_IFCONFIG0_ADDRMODE_32BIT (0x1UL) /*!< 32-bit addressing. */

/* Bits 5..3 : Configure number of data lines and opcode used for writing. */
#define QSPI_IFCONFIG0_WRITEOC_Pos (3UL) /*!< Position of WRITEOC field. */
#define QSPI_IFCONFIG0_WRITEOC_Msk (0x7UL << QSPI_IFCONFIG0_WRITEOC_Pos) /*!< Bit mask of WRITEOC field. */
#define QSPI_IFCONFIG0_WRITEOC_PP (0x0UL) /*!< Single data line SPI. PP (opcode 0x02). */
#define QSPI_IFCONFIG0_WRITEOC_PP2O (0x1UL) /*!< Dual data line SPI. PP2O (opcode 0xA2). */
#define QSPI_IFCONFIG0_WRITEOC_PP4O (0x2UL) /*!< Quad data line SPI. PP4O (opcode 0x32). */
#define QSPI_IFCONFIG0_WRITEOC_PP4IO (0x3UL) /*!< Quad data line SPI. PP4IO (opcode 0x38). */

/* Bits 2..0 : Configure number of data lines and opcode used for reading. */
#define QSPI_IFCONFIG0_READOC_Pos (0UL) /*!< Position of READOC field. */
#define QSPI_IFCONFIG0_READOC_Msk (0x7UL << QSPI_IFCONFIG0_READOC_Pos) /*!< Bit mask of READOC field. */
#define QSPI_IFCONFIG0_READOC_FASTREAD (0x0UL) /*!< Single data line SPI. FAST_READ (opcode 0x0B). */
#define QSPI_IFCONFIG0_READOC_READ2O (0x1UL) /*!< Dual data line SPI. READ2O (opcode 0x3B). */
#define QSPI_IFCONFIG0_READOC_READ2IO (0x2UL) /*!< Dual data line SPI. READ2IO (opcode 0xBB). */
#define QSPI_IFCONFIG0_READOC_READ4O (0x3UL) /*!< Quad data line SPI. READ4O (opcode 0x6B). */
#define QSPI_IFCONFIG0_READOC_READ4IO (0x4UL) /*!< Quad data line SPI. READ4IO (opcode 0xEB). */

/* Register: QSPI_XIPEN */
/* Description: Enable Execute in Place operation. */

/* Bit 0 : Enable XIP AHB Slave interface and access to XIP memory range */
#define QSPI_XIPEN_XIPEN_Pos (0UL) /*!< Position of XIPEN field. */
#define QSPI_XIPEN_XIPEN_Msk (0x1UL << QSPI_XIPEN_XIPEN_Pos) /*!< Bit mask of XIPEN field. */
#define QSPI_XIPEN_XIPEN_Disable (0x0UL) /*!< Disable XIP interface */
#define QSPI_XIPEN_XIPEN_Enable (0x1UL) /*!< Enable XIP interface */

/* Register: QSPI_XIP_ENC_KEY0 */
/* Description: Bits 31:0 of XIP AES KEY */

/* Bits 31..0 : Bits 31:0 of XIP AES KEY */
#define QSPI_XIP_ENC_KEY0_KEY0_Pos (0UL) /*!< Position of KEY0 field. */
#define QSPI_XIP_ENC_KEY0_KEY0_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY0_KEY0_Pos) /*!< Bit mask of KEY0 field. */

/* Register: QSPI_XIP_ENC_KEY1 */
/* Description: Bits 63:32 of XIP AES KEY */

/* Bits 31..0 : Bits 63:32 of XIP AES KEY */
#define QSPI_XIP_ENC_KEY1_KEY1_Pos (0UL) /*!< Position of KEY1 field. */
#define QSPI_XIP_ENC_KEY1_KEY1_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY1_KEY1_Pos) /*!< Bit mask of KEY1 field. */

/* Register: QSPI_XIP_ENC_KEY2 */
/* Description: Bits 95:64 of XIP AES KEY */

/* Bits 31..0 : Bits 95:64 of XIP AES KEY */
#define QSPI_XIP_ENC_KEY2_KEY2_Pos (0UL) /*!< Position of KEY2 field. */
#define QSPI_XIP_ENC_KEY2_KEY2_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY2_KEY2_Pos) /*!< Bit mask of KEY2 field. */

/* Register: QSPI_XIP_ENC_KEY3 */
/* Description: Bits 127:96 of XIP AES KEY */

/* Bits 31..0 : Bits 127:96 of XIP AES KEY */
#define QSPI_XIP_ENC_KEY3_KEY3_Pos (0UL) /*!< Position of KEY3 field. */
#define QSPI_XIP_ENC_KEY3_KEY3_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY3_KEY3_Pos) /*!< Bit mask of KEY3 field. */

/* Register: QSPI_XIP_ENC_NONCE0 */
/* Description: Bits 31:0 of XIP NONCE */

/* Bits 31..0 : Bits 31:0 of XIP NONCE */
#define QSPI_XIP_ENC_NONCE0_NONCE0_Pos (0UL) /*!< Position of NONCE0 field. */
#define QSPI_XIP_ENC_NONCE0_NONCE0_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_NONCE0_NONCE0_Pos) /*!< Bit mask of NONCE0 field. */

/* Register: QSPI_XIP_ENC_NONCE1 */
/* Description: Bits 63:32 of XIP NONCE */

/* Bits 31..0 : Bits 63:32 of XIP NONCE */
#define QSPI_XIP_ENC_NONCE1_NONCE1_Pos (0UL) /*!< Position of NONCE1 field. */
#define QSPI_XIP_ENC_NONCE1_NONCE1_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_NONCE1_NONCE1_Pos) /*!< Bit mask of NONCE1 field. */

/* Register: QSPI_XIP_ENC_NONCE2 */
/* Description: Bits 95:64 of XIP NONCE */

/* Bits 31..0 : Bits 95:64 of XIP NONCE */
#define QSPI_XIP_ENC_NONCE2_NONCE2_Pos (0UL) /*!< Position of NONCE2 field. */
#define QSPI_XIP_ENC_NONCE2_NONCE2_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_NONCE2_NONCE2_Pos) /*!< Bit mask of NONCE2 field. */

/* Register: QSPI_XIP_ENC_ENABLE */
/* Description: Enable stream cipher for XIP */

/* Bit 0 : Enable or disable stream cipher for XIP */
#define QSPI_XIP_ENC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define QSPI_XIP_ENC_ENABLE_ENABLE_Msk (0x1UL << QSPI_XIP_ENC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define QSPI_XIP_ENC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable stream cipher for QSPI XIP */
#define QSPI_XIP_ENC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable stream cipher for QSPI XIP */

/* Register: QSPI_DMA_ENC_KEY0 */
/* Description: Bits 31:0 of DMA AES KEY */

/* Bits 31..0 : Bits 31:0 of DMA AES KEY */
#define QSPI_DMA_ENC_KEY0_KEY0_Pos (0UL) /*!< Position of KEY0 field. */
#define QSPI_DMA_ENC_KEY0_KEY0_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY0_KEY0_Pos) /*!< Bit mask of KEY0 field. */

/* Register: QSPI_DMA_ENC_KEY1 */
/* Description: Bits 63:32 of DMA AES KEY */

/* Bits 31..0 : Bits 63:32 of DMA AES KEY */
#define QSPI_DMA_ENC_KEY1_KEY1_Pos (0UL) /*!< Position of KEY1 field. */
#define QSPI_DMA_ENC_KEY1_KEY1_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY1_KEY1_Pos) /*!< Bit mask of KEY1 field. */

/* Register: QSPI_DMA_ENC_KEY2 */
/* Description: Bits 95:64 of DMA AES KEY */

/* Bits 31..0 : Bits 95:64 of DMA AES KEY */
#define QSPI_DMA_ENC_KEY2_KEY2_Pos (0UL) /*!< Position of KEY2 field. */
#define QSPI_DMA_ENC_KEY2_KEY2_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY2_KEY2_Pos) /*!< Bit mask of KEY2 field. */

/* Register: QSPI_DMA_ENC_KEY3 */
/* Description: Bits 127:96 of DMA AES KEY */

/* Bits 31..0 : Bits 127:96 of DMA AES KEY */
#define QSPI_DMA_ENC_KEY3_KEY3_Pos (0UL) /*!< Position of KEY3 field. */
#define QSPI_DMA_ENC_KEY3_KEY3_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY3_KEY3_Pos) /*!< Bit mask of KEY3 field. */

/* Register: QSPI_DMA_ENC_NONCE0 */
/* Description: Bits 31:0 of DMA NONCE */

/* Bits 31..0 : Bits 31:0 of DMA NONCE */
#define QSPI_DMA_ENC_NONCE0_NONCE0_Pos (0UL) /*!< Position of NONCE0 field. */
#define QSPI_DMA_ENC_NONCE0_NONCE0_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_NONCE0_NONCE0_Pos) /*!< Bit mask of NONCE0 field. */

/* Register: QSPI_DMA_ENC_NONCE1 */
/* Description: Bits 63:32 of DMA NONCE */

/* Bits 31..0 : Bits 63:32 of DMA NONCE */
#define QSPI_DMA_ENC_NONCE1_NONCE1_Pos (0UL) /*!< Position of NONCE1 field. */
#define QSPI_DMA_ENC_NONCE1_NONCE1_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_NONCE1_NONCE1_Pos) /*!< Bit mask of NONCE1 field. */

/* Register: QSPI_DMA_ENC_NONCE2 */
/* Description: Bits 95:64 of DMA NONCE */

/* Bits 31..0 : Bits 95:64 of DMA NONCE */
#define QSPI_DMA_ENC_NONCE2_NONCE2_Pos (0UL) /*!< Position of NONCE2 field. */
#define QSPI_DMA_ENC_NONCE2_NONCE2_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_NONCE2_NONCE2_Pos) /*!< Bit mask of NONCE2 field. */

/* Register: QSPI_DMA_ENC_ENABLE */
/* Description: Enable stream cipher for EasyDMA */

/* Bit 0 : Enable or disable stream cipher for EasyDMA */
#define QSPI_DMA_ENC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define QSPI_DMA_ENC_ENABLE_ENABLE_Msk (0x1UL << QSPI_DMA_ENC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define QSPI_DMA_ENC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable stream cipher for QSPI EasyDMA */
#define QSPI_DMA_ENC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable stream cipher for QSPI EasyDMA */

/* Register: QSPI_IFCONFIG1 */
/* Description: Interface configuration. */

/* Bits 31..28 : SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1)). */
#define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL) /*!< Position of SCKFREQ field. */
#define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos) /*!< Bit mask of SCKFREQ field. */

/* Bit 25 : Select SPI mode. */
#define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */
#define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */
#define QSPI_IFCONFIG1_SPIMODE_MODE0 (0x0UL) /*!< Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */
#define QSPI_IFCONFIG1_SPIMODE_MODE3 (0x1UL) /*!< Mode 3: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 1 (CPOL=1, CPHA=1). */

/* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */
#define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */
#define QSPI_IFCONFIG1_DPMEN_Msk (0x1UL << QSPI_IFCONFIG1_DPMEN_Pos) /*!< Bit mask of DPMEN field. */
#define QSPI_IFCONFIG1_DPMEN_Exit (0x0UL) /*!< Exit DPM. */
#define QSPI_IFCONFIG1_DPMEN_Enter (0x1UL) /*!< Enter DPM. */

/* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns). */
#define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */
#define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */

/* Register: QSPI_STATUS */
/* Description: Status register. */

/* Bits 31..24 : Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */
#define QSPI_STATUS_SREG_Pos (24UL) /*!< Position of SREG field. */
#define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos) /*!< Bit mask of SREG field. */

/* Bit 3 : Ready status. */
#define QSPI_STATUS_READY_Pos (3UL) /*!< Position of READY field. */
#define QSPI_STATUS_READY_Msk (0x1UL << QSPI_STATUS_READY_Pos) /*!< Bit mask of READY field. */
#define QSPI_STATUS_READY_BUSY (0x0UL) /*!< QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. */
#define QSPI_STATUS_READY_READY (0x1UL) /*!< QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. */

/* Bit 2 : Deep power-down mode (DPM) status of external flash. */
#define QSPI_STATUS_DPM_Pos (2UL) /*!< Position of DPM field. */
#define QSPI_STATUS_DPM_Msk (0x1UL << QSPI_STATUS_DPM_Pos) /*!< Bit mask of DPM field. */
#define QSPI_STATUS_DPM_Disabled (0x0UL) /*!< External flash is not in DPM. */
#define QSPI_STATUS_DPM_Enabled (0x1UL) /*!< External flash is in DPM. */

/* Register: QSPI_DPMDUR */
/* Description: Set the duration required to enter/exit deep power-down mode (DPM). */

/* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 31.25 ns. */
#define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */
#define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */

/* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 31.25 ns */
#define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */
#define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */

/* Register: QSPI_ADDRCONF */
/* Description: Extended address configuration. */

/* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */
#define QSPI_ADDRCONF_WREN_Pos (27UL) /*!< Position of WREN field. */
#define QSPI_ADDRCONF_WREN_Msk (0x1UL << QSPI_ADDRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
#define QSPI_ADDRCONF_WREN_Disable (0x0UL) /*!< Do not send WREN. */
#define QSPI_ADDRCONF_WREN_Enable (0x1UL) /*!< Send WREN. */

/* Bit 26 : Wait for write complete before sending command. */
#define QSPI_ADDRCONF_WIPWAIT_Pos (26UL) /*!< Position of WIPWAIT field. */
#define QSPI_ADDRCONF_WIPWAIT_Msk (0x1UL << QSPI_ADDRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
#define QSPI_ADDRCONF_WIPWAIT_Disable (0x0UL) /*!< No wait. */
#define QSPI_ADDRCONF_WIPWAIT_Enable (0x1UL) /*!< Wait. */

/* Bits 25..24 : Extended addressing mode. */
#define QSPI_ADDRCONF_MODE_Pos (24UL) /*!< Position of MODE field. */
#define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos) /*!< Bit mask of MODE field. */
#define QSPI_ADDRCONF_MODE_NoInstr (0x0UL) /*!< Do not send any instruction. */
#define QSPI_ADDRCONF_MODE_Opcode (0x1UL) /*!< Send opcode. */
#define QSPI_ADDRCONF_MODE_OpByte0 (0x2UL) /*!< Send opcode, BYTE0. */
#define QSPI_ADDRCONF_MODE_All (0x3UL) /*!< Send opcode, BYTE0, BYTE1. */

/* Bits 23..16 : Byte 1 following byte 0. */
#define QSPI_ADDRCONF_BYTE1_Pos (16UL) /*!< Position of BYTE1 field. */
#define QSPI_ADDRCONF_BYTE1_Msk (0xFFUL << QSPI_ADDRCONF_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */

/* Bits 15..8 : Byte 0 following opcode. */
#define QSPI_ADDRCONF_BYTE0_Pos (8UL) /*!< Position of BYTE0 field. */
#define QSPI_ADDRCONF_BYTE0_Msk (0xFFUL << QSPI_ADDRCONF_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */

/* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */
#define QSPI_ADDRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
#define QSPI_ADDRCONF_OPCODE_Msk (0xFFUL << QSPI_ADDRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */

/* Register: QSPI_CINSTRCONF */
/* Description: Custom instruction configuration register. */

/* Bit 17 : Stop (finalize) long frame transaction */
#define QSPI_CINSTRCONF_LFSTOP_Pos (17UL) /*!< Position of LFSTOP field. */
#define QSPI_CINSTRCONF_LFSTOP_Msk (0x1UL << QSPI_CINSTRCONF_LFSTOP_Pos) /*!< Bit mask of LFSTOP field. */
#define QSPI_CINSTRCONF_LFSTOP_Stop (0x1UL) /*!< Stop */

/* Bit 16 : Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. */
#define QSPI_CINSTRCONF_LFEN_Pos (16UL) /*!< Position of LFEN field. */
#define QSPI_CINSTRCONF_LFEN_Msk (0x1UL << QSPI_CINSTRCONF_LFEN_Pos) /*!< Bit mask of LFEN field. */
#define QSPI_CINSTRCONF_LFEN_Disable (0x0UL) /*!< Long frame mode disabled */
#define QSPI_CINSTRCONF_LFEN_Enable (0x1UL) /*!< Long frame mode enabled */

/* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */
#define QSPI_CINSTRCONF_WREN_Pos (15UL) /*!< Position of WREN field. */
#define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
#define QSPI_CINSTRCONF_WREN_Disable (0x0UL) /*!< Do not send WREN. */
#define QSPI_CINSTRCONF_WREN_Enable (0x1UL) /*!< Send WREN. */

/* Bit 14 : Wait for write complete before sending command. */
#define QSPI_CINSTRCONF_WIPWAIT_Pos (14UL) /*!< Position of WIPWAIT field. */
#define QSPI_CINSTRCONF_WIPWAIT_Msk (0x1UL << QSPI_CINSTRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
#define QSPI_CINSTRCONF_WIPWAIT_Disable (0x0UL) /*!< No wait. */
#define QSPI_CINSTRCONF_WIPWAIT_Enable (0x1UL) /*!< Wait. */

/* Bit 13 : Level of the IO3 pin (if connected) during transmission of custom instruction. */
#define QSPI_CINSTRCONF_LIO3_Pos (13UL) /*!< Position of LIO3 field. */
#define QSPI_CINSTRCONF_LIO3_Msk (0x1UL << QSPI_CINSTRCONF_LIO3_Pos) /*!< Bit mask of LIO3 field. */

/* Bit 12 : Level of the IO2 pin (if connected) during transmission of custom instruction. */
#define QSPI_CINSTRCONF_LIO2_Pos (12UL) /*!< Position of LIO2 field. */
#define QSPI_CINSTRCONF_LIO2_Msk (0x1UL << QSPI_CINSTRCONF_LIO2_Pos) /*!< Bit mask of LIO2 field. */

/* Bits 11..8 : Length of custom instruction in number of bytes. */
#define QSPI_CINSTRCONF_LENGTH_Pos (8UL) /*!< Position of LENGTH field. */
#define QSPI_CINSTRCONF_LENGTH_Msk (0xFUL << QSPI_CINSTRCONF_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
#define QSPI_CINSTRCONF_LENGTH_1B (0x1UL) /*!< Send opcode only. */
#define QSPI_CINSTRCONF_LENGTH_2B (0x2UL) /*!< Send opcode, CINSTRDAT0.BYTE0. */
#define QSPI_CINSTRCONF_LENGTH_3B (0x3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. */
#define QSPI_CINSTRCONF_LENGTH_4B (0x4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. */
#define QSPI_CINSTRCONF_LENGTH_5B (0x5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. */
#define QSPI_CINSTRCONF_LENGTH_6B (0x6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. */
#define QSPI_CINSTRCONF_LENGTH_7B (0x7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. */
#define QSPI_CINSTRCONF_LENGTH_8B (0x8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. */
#define QSPI_CINSTRCONF_LENGTH_9B (0x9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. */

/* Bits 7..0 : Opcode of Custom instruction. */
#define QSPI_CINSTRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
#define QSPI_CINSTRCONF_OPCODE_Msk (0xFFUL << QSPI_CINSTRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */

/* Register: QSPI_CINSTRDAT0 */
/* Description: Custom instruction data register 0. */

/* Bits 31..24 : Data byte 3 */
#define QSPI_CINSTRDAT0_BYTE3_Pos (24UL) /*!< Position of BYTE3 field. */
#define QSPI_CINSTRDAT0_BYTE3_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE3_Pos) /*!< Bit mask of BYTE3 field. */

/* Bits 23..16 : Data byte 2 */
#define QSPI_CINSTRDAT0_BYTE2_Pos (16UL) /*!< Position of BYTE2 field. */
#define QSPI_CINSTRDAT0_BYTE2_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE2_Pos) /*!< Bit mask of BYTE2 field. */

/* Bits 15..8 : Data byte 1 */
#define QSPI_CINSTRDAT0_BYTE1_Pos (8UL) /*!< Position of BYTE1 field. */
#define QSPI_CINSTRDAT0_BYTE1_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */

/* Bits 7..0 : Data byte 0 */
#define QSPI_CINSTRDAT0_BYTE0_Pos (0UL) /*!< Position of BYTE0 field. */
#define QSPI_CINSTRDAT0_BYTE0_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */

/* Register: QSPI_CINSTRDAT1 */
/* Description: Custom instruction data register 1. */

/* Bits 31..24 : Data byte 7 */
#define QSPI_CINSTRDAT1_BYTE7_Pos (24UL) /*!< Position of BYTE7 field. */
#define QSPI_CINSTRDAT1_BYTE7_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE7_Pos) /*!< Bit mask of BYTE7 field. */

/* Bits 23..16 : Data byte 6 */
#define QSPI_CINSTRDAT1_BYTE6_Pos (16UL) /*!< Position of BYTE6 field. */
#define QSPI_CINSTRDAT1_BYTE6_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE6_Pos) /*!< Bit mask of BYTE6 field. */

/* Bits 15..8 : Data byte 5 */
#define QSPI_CINSTRDAT1_BYTE5_Pos (8UL) /*!< Position of BYTE5 field. */
#define QSPI_CINSTRDAT1_BYTE5_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE5_Pos) /*!< Bit mask of BYTE5 field. */

/* Bits 7..0 : Data byte 4 */
#define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */
#define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */

/* Register: QSPI_IFTIMING */
/* Description: SPI interface timing. */

/* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK. */
#define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */
#define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */


/* Peripheral: REGULATORS */
/* Description: Voltage regulators 0 */

/* Register: REGULATORS_MAINREGSTATUS */
/* Description: Main supply status */

/* Bit 0 : VREGH status */
#define REGULATORS_MAINREGSTATUS_VREGH_Pos (0UL) /*!< Position of VREGH field. */
#define REGULATORS_MAINREGSTATUS_VREGH_Msk (0x1UL << REGULATORS_MAINREGSTATUS_VREGH_Pos) /*!< Bit mask of VREGH field. */
#define REGULATORS_MAINREGSTATUS_VREGH_Inactive (0x0UL) /*!< Normal voltage mode. Voltage supplied on VDD and VDDH. */
#define REGULATORS_MAINREGSTATUS_VREGH_Active (0x1UL) /*!< High voltage mode. Voltage supplied on VDDH. */

/* Register: REGULATORS_SYSTEMOFF */
/* Description: System OFF register */

/* Bit 0 : Enable System OFF mode */
#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enter (0x1UL) /*!< Enable System OFF mode */

/* Register: REGULATORS_POFCON */
/* Description: Power-fail comparator configuration */

/* Bits 11..8 : Power-fail comparator threshold setting for voltage supply on VDDH */
#define REGULATORS_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */
#define REGULATORS_POFCON_THRESHOLDVDDH_Msk (0xFUL << REGULATORS_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */
#define REGULATORS_POFCON_THRESHOLDVDDH_V27 (0x0UL) /*!< Set threshold to 2.7 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V28 (0x1UL) /*!< Set threshold to 2.8 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V29 (0x2UL) /*!< Set threshold to 2.9 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V30 (0x3UL) /*!< Set threshold to 3.0 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V31 (0x4UL) /*!< Set threshold to 3.1 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V32 (0x5UL) /*!< Set threshold to 3.2 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V33 (0x6UL) /*!< Set threshold to 3.3 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V34 (0x7UL) /*!< Set threshold to 3.4 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V35 (0x8UL) /*!< Set threshold to 3.5 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V36 (0x9UL) /*!< Set threshold to 3.6 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V37 (0xAUL) /*!< Set threshold to 3.7 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V38 (0xBUL) /*!< Set threshold to 3.8 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V39 (0xCUL) /*!< Set threshold to 3.9 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V40 (0xDUL) /*!< Set threshold to 4.0 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V41 (0xEUL) /*!< Set threshold to 4.1 V */
#define REGULATORS_POFCON_THRESHOLDVDDH_V42 (0xFUL) /*!< Set threshold to 4.2 V */

/* Bits 4..1 : Power-fail comparator threshold setting */
#define REGULATORS_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
#define REGULATORS_POFCON_THRESHOLD_Msk (0xFUL << REGULATORS_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
#define REGULATORS_POFCON_THRESHOLD_V19 (0x6UL) /*!< Set threshold to 1.9 V */
#define REGULATORS_POFCON_THRESHOLD_V20 (0x7UL) /*!< Set threshold to 2.0 V */
#define REGULATORS_POFCON_THRESHOLD_V21 (0x8UL) /*!< Set threshold to 2.1 V */
#define REGULATORS_POFCON_THRESHOLD_V22 (0x9UL) /*!< Set threshold to 2.2 V */
#define REGULATORS_POFCON_THRESHOLD_V23 (0xAUL) /*!< Set threshold to 2.3 V */
#define REGULATORS_POFCON_THRESHOLD_V24 (0xBUL) /*!< Set threshold to 2.4 V */
#define REGULATORS_POFCON_THRESHOLD_V25 (0xCUL) /*!< Set threshold to 2.5 V */
#define REGULATORS_POFCON_THRESHOLD_V26 (0xDUL) /*!< Set threshold to 2.6 V */
#define REGULATORS_POFCON_THRESHOLD_V27 (0xEUL) /*!< Set threshold to 2.7 V */
#define REGULATORS_POFCON_THRESHOLD_V28 (0xFUL) /*!< Set threshold to 2.8 V */

/* Bit 0 : Enable or disable power-fail comparator */
#define REGULATORS_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
#define REGULATORS_POFCON_POF_Msk (0x1UL << REGULATORS_POFCON_POF_Pos) /*!< Bit mask of POF field. */
#define REGULATORS_POFCON_POF_Disabled (0x0UL) /*!< Disable */
#define REGULATORS_POFCON_POF_Enabled (0x1UL) /*!< Enable */

/* Register: REGULATORS_VREGMAIN_DCDCEN */
/* Description: DC/DC enable register for VREGMAIN */

/* Bit 0 : Enable or disable DC/DC converter */
#define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
#define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
#define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Disabled (0x0UL) /*!< Disable */
#define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Enabled (0x1UL) /*!< Enable */

/* Register: REGULATORS_VREGRADIO_DCDCEN */
/* Description: DC/DC enable register for VREGRADIO */

/* Bit 0 : Enable or disable DC/DC converter */
#define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
#define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
#define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Disabled (0x0UL) /*!< Disable */
#define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Enabled (0x1UL) /*!< Enable */

/* Register: REGULATORS_VREGH_DCDCEN */
/* Description: DC/DC enable register for VREGH */

/* Bit 0 : Enable or disable DC/DC converter */
#define REGULATORS_VREGH_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
#define REGULATORS_VREGH_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_VREGH_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
#define REGULATORS_VREGH_DCDCEN_DCDCEN_Disabled (0x0UL) /*!< Disable */
#define REGULATORS_VREGH_DCDCEN_DCDCEN_Enabled (0x1UL) /*!< Enable */

/* Register: REGULATORS_VREGH_EXTSILENTEN */
/* Description: When VREGH is in DC/DC mode, enable VREGH silent mode to supply external components from VDD. Silent mode has lower voltage ripple. Silent mode is used when DC/DC is enabled, and is ignored in LDO mode. Disabling silent mode reduces current consumption in sleep. */

/* Bit 0 : Enable silent external DC/DC supply */
#define REGULATORS_VREGH_EXTSILENTEN_EXTSILENTEN_Pos (0UL) /*!< Position of EXTSILENTEN field. */
#define REGULATORS_VREGH_EXTSILENTEN_EXTSILENTEN_Msk (0x1UL << REGULATORS_VREGH_EXTSILENTEN_EXTSILENTEN_Pos) /*!< Bit mask of EXTSILENTEN field. */
#define REGULATORS_VREGH_EXTSILENTEN_EXTSILENTEN_Disabled (0x0UL) /*!< Disable */
#define REGULATORS_VREGH_EXTSILENTEN_EXTSILENTEN_Enabled (0x1UL) /*!< Enable */


/* Peripheral: RESET */
/* Description: Reset control 0 */

/* Register: RESET_RESETREAS */
/* Description: Reset reason */

/* Bit 26 : Reset after wakeup from System OFF mode due to VBUS rising into valid range */
#define RESET_RESETREAS_VBUS_Pos (26UL) /*!< Position of VBUS field. */
#define RESET_RESETREAS_VBUS_Msk (0x1UL << RESET_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */
#define RESET_RESETREAS_VBUS_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_VBUS_Detected (0x1UL) /*!< Detected */

/* Bit 25 : Reset from application watchdog timer 1 detected */
#define RESET_RESETREAS_DOG1_Pos (25UL) /*!< Position of DOG1 field. */
#define RESET_RESETREAS_DOG1_Msk (0x1UL << RESET_RESETREAS_DOG1_Pos) /*!< Bit mask of DOG1 field. */
#define RESET_RESETREAS_DOG1_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_DOG1_Detected (0x1UL) /*!< Detected */

/* Bit 24 : Reset after wakeup from System OFF mode due to NFC field being detected */
#define RESET_RESETREAS_NFC_Pos (24UL) /*!< Position of NFC field. */
#define RESET_RESETREAS_NFC_Msk (0x1UL << RESET_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
#define RESET_RESETREAS_NFC_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_NFC_Detected (0x1UL) /*!< Detected */

/* Bit 7 : Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode */
#define RESET_RESETREAS_DIF_Pos (7UL) /*!< Position of DIF field. */
#define RESET_RESETREAS_DIF_Msk (0x1UL << RESET_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
#define RESET_RESETREAS_DIF_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_DIF_Detected (0x1UL) /*!< Detected */

/* Bit 6 : Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP */
#define RESET_RESETREAS_LPCOMP_Pos (6UL) /*!< Position of LPCOMP field. */
#define RESET_RESETREAS_LPCOMP_Msk (0x1UL << RESET_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
#define RESET_RESETREAS_LPCOMP_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_LPCOMP_Detected (0x1UL) /*!< Detected */

/* Bit 5 : Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO */
#define RESET_RESETREAS_OFF_Pos (5UL) /*!< Position of OFF field. */
#define RESET_RESETREAS_OFF_Msk (0x1UL << RESET_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
#define RESET_RESETREAS_OFF_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_OFF_Detected (0x1UL) /*!< Detected */

/* Bit 4 : Reset from application CPU lockup detected */
#define RESET_RESETREAS_LOCKUP_Pos (4UL) /*!< Position of LOCKUP field. */
#define RESET_RESETREAS_LOCKUP_Msk (0x1UL << RESET_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
#define RESET_RESETREAS_LOCKUP_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_LOCKUP_Detected (0x1UL) /*!< Detected */

/* Bit 3 : Reset from application soft reset detected */
#define RESET_RESETREAS_SREQ_Pos (3UL) /*!< Position of SREQ field. */
#define RESET_RESETREAS_SREQ_Msk (0x1UL << RESET_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
#define RESET_RESETREAS_SREQ_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_SREQ_Detected (0x1UL) /*!< Detected */

/* Bit 2 : Reset from application CTRL-AP detected */
#define RESET_RESETREAS_CTRLAP_Pos (2UL) /*!< Position of CTRLAP field. */
#define RESET_RESETREAS_CTRLAP_Msk (0x1UL << RESET_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */
#define RESET_RESETREAS_CTRLAP_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_CTRLAP_Detected (0x1UL) /*!< Detected */

/* Bit 1 : Reset from application watchdog timer 0 detected */
#define RESET_RESETREAS_DOG0_Pos (1UL) /*!< Position of DOG0 field. */
#define RESET_RESETREAS_DOG0_Msk (0x1UL << RESET_RESETREAS_DOG0_Pos) /*!< Bit mask of DOG0 field. */
#define RESET_RESETREAS_DOG0_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_DOG0_Detected (0x1UL) /*!< Detected */

/* Bit 0 : Reset from pin reset detected */
#define RESET_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
#define RESET_RESETREAS_RESETPIN_Msk (0x1UL << RESET_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
#define RESET_RESETREAS_RESETPIN_NotDetected (0x0UL) /*!< Not detected */
#define RESET_RESETREAS_RESETPIN_Detected (0x1UL) /*!< Detected */

/* Register: RESET_NETWORK_FORCEOFF */
/* Description: Force network core off */

/* Bit 0 : Force network core off */
#define RESET_NETWORK_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
#define RESET_NETWORK_FORCEOFF_FORCEOFF_Msk (0x1UL << RESET_NETWORK_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
#define RESET_NETWORK_FORCEOFF_FORCEOFF_Release (0x0UL) /*!< Release Force-OFF */
#define RESET_NETWORK_FORCEOFF_FORCEOFF_Hold (0x1UL) /*!< Hold Force-OFF */


/* Peripheral: RTC */
/* Description: Real-time counter 0 */

/* Register: RTC_TASKS_START */
/* Description: Start RTC counter */

/* Bit 0 : Start RTC counter */
#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define RTC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */

/* Register: RTC_TASKS_STOP */
/* Description: Stop RTC counter */

/* Bit 0 : Stop RTC counter */
#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define RTC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: RTC_TASKS_CLEAR */
/* Description: Clear RTC counter */

/* Bit 0 : Clear RTC counter */
#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */

/* Register: RTC_TASKS_TRIGOVRFLW */
/* Description: Set counter to 0xFFFFF0 */

/* Bit 0 : Set counter to 0xFFFFF0 */
#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (0x1UL) /*!< Trigger task */

/* Register: RTC_TASKS_CAPTURE */
/* Description: Description collection: Capture RTC counter to CC[n] register */

/* Bit 0 : Capture RTC counter to CC[n] register */
#define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
#define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
#define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */

/* Register: RTC_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */

/* Bit 31 :   */
#define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define RTC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
#define RTC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: RTC_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define RTC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define RTC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: RTC_SUBSCRIBE_CLEAR */
/* Description: Subscribe configuration for task CLEAR */

/* Bit 31 :   */
#define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
#define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
#define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */
#define RTC_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
#define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: RTC_SUBSCRIBE_TRIGOVRFLW */
/* Description: Subscribe configuration for task TRIGOVRFLW */

/* Bit 31 :   */
#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */
#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0x0UL) /*!< Disable subscription */
#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */
#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: RTC_SUBSCRIBE_CAPTURE */
/* Description: Description collection: Subscribe configuration for task CAPTURE[n] */

/* Bit 31 :   */
#define RTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
#define RTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << RTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
#define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
#define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: RTC_EVENTS_TICK */
/* Description: Event on counter increment */

/* Bit 0 : Event on counter increment */
#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0x0UL) /*!< Event not generated */
#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (0x1UL) /*!< Event generated */

/* Register: RTC_EVENTS_OVRFLW */
/* Description: Event on counter overflow */

/* Bit 0 : Event on counter overflow */
#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0x0UL) /*!< Event not generated */
#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (0x1UL) /*!< Event generated */

/* Register: RTC_EVENTS_COMPARE */
/* Description: Description collection: Compare event on CC[n] match */

/* Bit 0 : Compare event on CC[n] match */
#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */
#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */

/* Register: RTC_PUBLISH_TICK */
/* Description: Publish configuration for event TICK */

/* Bit 31 :   */
#define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */
#define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */
#define RTC_PUBLISH_TICK_EN_Disabled (0x0UL) /*!< Disable publishing */
#define RTC_PUBLISH_TICK_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TICK will publish to */
#define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: RTC_PUBLISH_OVRFLW */
/* Description: Publish configuration for event OVRFLW */

/* Bit 31 :   */
#define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
#define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */
#define RTC_PUBLISH_OVRFLW_EN_Disabled (0x0UL) /*!< Disable publishing */
#define RTC_PUBLISH_OVRFLW_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event OVRFLW will publish to */
#define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: RTC_PUBLISH_COMPARE */
/* Description: Description collection: Publish configuration for event COMPARE[n] */

/* Bit 31 :   */
#define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
#define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
#define RTC_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */
#define RTC_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */
#define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: RTC_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
#define RTC_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
#define RTC_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
#define RTC_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
#define RTC_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
#define RTC_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
#define RTC_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
#define RTC_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
#define RTC_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
#define RTC_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
#define RTC_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
#define RTC_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
#define RTC_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
#define RTC_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
#define RTC_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
#define RTC_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
#define RTC_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: RTC_INTENSET */
/* Description: Enable interrupt */

/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */

/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */

/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */

/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_INTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENSET_OVRFLW_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event TICK */
#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_INTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENSET_TICK_Set (0x1UL) /*!< Enable */

/* Register: RTC_INTENCLR */
/* Description: Disable interrupt */

/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */

/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */

/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */

/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_INTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event TICK */
#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_INTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_INTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_INTENCLR_TICK_Clear (0x1UL) /*!< Disable */

/* Register: RTC_EVTEN */
/* Description: Enable or disable event routing */

/* Bit 19 : Enable or disable event routing for event COMPARE[3] */
#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTEN_COMPARE3_Disabled (0x0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE3_Enabled (0x1UL) /*!< Enable */

/* Bit 18 : Enable or disable event routing for event COMPARE[2] */
#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTEN_COMPARE2_Disabled (0x0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE2_Enabled (0x1UL) /*!< Enable */

/* Bit 17 : Enable or disable event routing for event COMPARE[1] */
#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTEN_COMPARE1_Disabled (0x0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE1_Enabled (0x1UL) /*!< Enable */

/* Bit 16 : Enable or disable event routing for event COMPARE[0] */
#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTEN_COMPARE0_Disabled (0x0UL) /*!< Disable */
#define RTC_EVTEN_COMPARE0_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable event routing for event OVRFLW */
#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTEN_OVRFLW_Disabled (0x0UL) /*!< Disable */
#define RTC_EVTEN_OVRFLW_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable event routing for event TICK */
#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTEN_TICK_Disabled (0x0UL) /*!< Disable */
#define RTC_EVTEN_TICK_Enabled (0x1UL) /*!< Enable */

/* Register: RTC_EVTENSET */
/* Description: Enable event routing */

/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE3_Set (0x1UL) /*!< Enable */

/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE2_Set (0x1UL) /*!< Enable */

/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE1_Set (0x1UL) /*!< Enable */

/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_COMPARE0_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable event routing for event OVRFLW */
#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_OVRFLW_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable event routing for event TICK */
#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENSET_TICK_Set (0x1UL) /*!< Enable */

/* Register: RTC_EVTENCLR */
/* Description: Disable event routing */

/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define RTC_EVTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */

/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define RTC_EVTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */

/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define RTC_EVTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */

/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define RTC_EVTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable event routing for event OVRFLW */
#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
#define RTC_EVTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable event routing for event TICK */
#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
#define RTC_EVTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */
#define RTC_EVTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */
#define RTC_EVTENCLR_TICK_Clear (0x1UL) /*!< Disable */

/* Register: RTC_COUNTER */
/* Description: Current counter value */

/* Bits 23..0 : Counter value */
#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */

/* Register: RTC_PRESCALER */
/* Description: 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. */

/* Bits 11..0 : Prescaler value */
#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */

/* Register: RTC_CC */
/* Description: Description collection: Compare register n */

/* Bits 23..0 : Compare value */
#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */


/* Peripheral: SAADC */
/* Description: Analog to Digital Converter 0 */

/* Register: SAADC_TASKS_START */
/* Description: Start the ADC and prepare the result buffer in RAM */

/* Bit 0 : Start the ADC and prepare the result buffer in RAM */
#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define SAADC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */

/* Register: SAADC_TASKS_SAMPLE */
/* Description: Take one ADC sample, if scan is enabled all channels are sampled */

/* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */

/* Register: SAADC_TASKS_STOP */
/* Description: Stop the ADC and terminate any ongoing conversion */

/* Bit 0 : Stop the ADC and terminate any ongoing conversion */
#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: SAADC_TASKS_CALIBRATEOFFSET */
/* Description: Starts offset auto-calibration */

/* Bit 0 : Starts offset auto-calibration */
#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (0x1UL) /*!< Trigger task */

/* Register: SAADC_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */

/* Bit 31 :   */
#define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
#define SAADC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_SUBSCRIBE_SAMPLE */
/* Description: Subscribe configuration for task SAMPLE */

/* Bit 31 :   */
#define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */
#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define SAADC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */
/* Description: Subscribe configuration for task CALIBRATEOFFSET */

/* Bit 31 :   */
#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0x0UL) /*!< Disable subscription */
#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */
#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_EVENTS_STARTED */
/* Description: The ADC has started */

/* Bit 0 : The ADC has started */
#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */

/* Register: SAADC_EVENTS_END */
/* Description: The ADC has filled up the Result buffer */

/* Bit 0 : The ADC has filled up the Result buffer */
#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
#define SAADC_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */

/* Register: SAADC_EVENTS_DONE */
/* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */

/* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */
#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */

/* Register: SAADC_EVENTS_RESULTDONE */
/* Description: A result is ready to get transferred to RAM */

/* Bit 0 : A result is ready to get transferred to RAM */
#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0x0UL) /*!< Event not generated */
#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (0x1UL) /*!< Event generated */

/* Register: SAADC_EVENTS_CALIBRATEDONE */
/* Description: Calibration is complete */

/* Bit 0 : Calibration is complete */
#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0x0UL) /*!< Event not generated */
#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (0x1UL) /*!< Event generated */

/* Register: SAADC_EVENTS_STOPPED */
/* Description: The ADC has stopped */

/* Bit 0 : The ADC has stopped */
#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */

/* Register: SAADC_EVENTS_CH_LIMITH */
/* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */

/* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0x0UL) /*!< Event not generated */
#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (0x1UL) /*!< Event generated */

/* Register: SAADC_EVENTS_CH_LIMITL */
/* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */

/* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0x0UL) /*!< Event not generated */
#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (0x1UL) /*!< Event generated */

/* Register: SAADC_PUBLISH_STARTED */
/* Description: Publish configuration for event STARTED */

/* Bit 31 :   */
#define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STARTED will publish to */
#define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_PUBLISH_END */
/* Description: Publish configuration for event END */

/* Bit 31 :   */
#define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event END will publish to */
#define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_PUBLISH_DONE */
/* Description: Publish configuration for event DONE */

/* Bit 31 :   */
#define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_PUBLISH_DONE_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_DONE_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event DONE will publish to */
#define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_PUBLISH_RESULTDONE */
/* Description: Publish configuration for event RESULTDONE */

/* Bit 31 :   */
#define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_RESULTDONE_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RESULTDONE will publish to */
#define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_PUBLISH_CALIBRATEDONE */
/* Description: Publish configuration for event CALIBRATEDONE */

/* Bit 31 :   */
#define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to */
#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */

/* Bit 31 :   */
#define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_PUBLISH_CH_LIMITH */
/* Description: Description cluster: Publish configuration for event CH[n].LIMITH */

/* Bit 31 :   */
#define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to */
#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_PUBLISH_CH_LIMITL */
/* Description: Description cluster: Publish configuration for event CH[n].LIMITL */

/* Bit 31 :   */
#define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */
#define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */
#define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to */
#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SAADC_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTEN_CH7LIMITL_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH7LIMITL_Enabled (0x1UL) /*!< Enable */

/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTEN_CH7LIMITH_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH7LIMITH_Enabled (0x1UL) /*!< Enable */

/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTEN_CH6LIMITL_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH6LIMITL_Enabled (0x1UL) /*!< Enable */

/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTEN_CH6LIMITH_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH6LIMITH_Enabled (0x1UL) /*!< Enable */

/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTEN_CH5LIMITL_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH5LIMITL_Enabled (0x1UL) /*!< Enable */

/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTEN_CH5LIMITH_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH5LIMITH_Enabled (0x1UL) /*!< Enable */

/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTEN_CH4LIMITL_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH4LIMITL_Enabled (0x1UL) /*!< Enable */

/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTEN_CH4LIMITH_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH4LIMITH_Enabled (0x1UL) /*!< Enable */

/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTEN_CH3LIMITL_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH3LIMITL_Enabled (0x1UL) /*!< Enable */

/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTEN_CH3LIMITH_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH3LIMITH_Enabled (0x1UL) /*!< Enable */

/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTEN_CH2LIMITL_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH2LIMITL_Enabled (0x1UL) /*!< Enable */

/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTEN_CH2LIMITH_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH2LIMITH_Enabled (0x1UL) /*!< Enable */

/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTEN_CH1LIMITL_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH1LIMITL_Enabled (0x1UL) /*!< Enable */

/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTEN_CH1LIMITH_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH1LIMITH_Enabled (0x1UL) /*!< Enable */

/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTEN_CH0LIMITL_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH0LIMITL_Enabled (0x1UL) /*!< Enable */

/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTEN_CH0LIMITH_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CH0LIMITH_Enabled (0x1UL) /*!< Enable */

/* Bit 5 : Enable or disable interrupt for event STOPPED */
#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */

/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTEN_CALIBRATEDONE_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_CALIBRATEDONE_Enabled (0x1UL) /*!< Enable */

/* Bit 3 : Enable or disable interrupt for event RESULTDONE */
#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTEN_RESULTDONE_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_RESULTDONE_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event DONE */
#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTEN_DONE_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_DONE_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event END */
#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTEN_END_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_END_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event STARTED */
#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */
#define SAADC_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */

/* Register: SAADC_INTENSET */
/* Description: Enable interrupt */

/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTENSET_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH7LIMITL_Set (0x1UL) /*!< Enable */

/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTENSET_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH7LIMITH_Set (0x1UL) /*!< Enable */

/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTENSET_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH6LIMITL_Set (0x1UL) /*!< Enable */

/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTENSET_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH6LIMITH_Set (0x1UL) /*!< Enable */

/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTENSET_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH5LIMITL_Set (0x1UL) /*!< Enable */

/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTENSET_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH5LIMITH_Set (0x1UL) /*!< Enable */

/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTENSET_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH4LIMITL_Set (0x1UL) /*!< Enable */

/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTENSET_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH4LIMITH_Set (0x1UL) /*!< Enable */

/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTENSET_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH3LIMITL_Set (0x1UL) /*!< Enable */

/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTENSET_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH3LIMITH_Set (0x1UL) /*!< Enable */

/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTENSET_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH2LIMITL_Set (0x1UL) /*!< Enable */

/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTENSET_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH2LIMITH_Set (0x1UL) /*!< Enable */

/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTENSET_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH1LIMITL_Set (0x1UL) /*!< Enable */

/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTENSET_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH1LIMITH_Set (0x1UL) /*!< Enable */

/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTENSET_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH0LIMITL_Set (0x1UL) /*!< Enable */

/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTENSET_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CH0LIMITH_Set (0x1UL) /*!< Enable */

/* Bit 5 : Write '1' to enable interrupt for event STOPPED */
#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_CALIBRATEDONE_Set (0x1UL) /*!< Enable */

/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTENSET_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_RESULTDONE_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event DONE */
#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_DONE_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event END */
#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_END_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event STARTED */
#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENSET_STARTED_Set (0x1UL) /*!< Enable */

/* Register: SAADC_INTENCLR */
/* Description: Disable interrupt */

/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
#define SAADC_INTENCLR_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH7LIMITL_Clear (0x1UL) /*!< Disable */

/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
#define SAADC_INTENCLR_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH7LIMITH_Clear (0x1UL) /*!< Disable */

/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
#define SAADC_INTENCLR_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH6LIMITL_Clear (0x1UL) /*!< Disable */

/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
#define SAADC_INTENCLR_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH6LIMITH_Clear (0x1UL) /*!< Disable */

/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
#define SAADC_INTENCLR_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH5LIMITL_Clear (0x1UL) /*!< Disable */

/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
#define SAADC_INTENCLR_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH5LIMITH_Clear (0x1UL) /*!< Disable */

/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
#define SAADC_INTENCLR_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH4LIMITL_Clear (0x1UL) /*!< Disable */

/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
#define SAADC_INTENCLR_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH4LIMITH_Clear (0x1UL) /*!< Disable */

/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
#define SAADC_INTENCLR_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH3LIMITL_Clear (0x1UL) /*!< Disable */

/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
#define SAADC_INTENCLR_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH3LIMITH_Clear (0x1UL) /*!< Disable */

/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
#define SAADC_INTENCLR_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH2LIMITL_Clear (0x1UL) /*!< Disable */

/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
#define SAADC_INTENCLR_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH2LIMITH_Clear (0x1UL) /*!< Disable */

/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
#define SAADC_INTENCLR_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH1LIMITL_Clear (0x1UL) /*!< Disable */

/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
#define SAADC_INTENCLR_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH1LIMITH_Clear (0x1UL) /*!< Disable */

/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
#define SAADC_INTENCLR_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH0LIMITL_Clear (0x1UL) /*!< Disable */

/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
#define SAADC_INTENCLR_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CH0LIMITH_Clear (0x1UL) /*!< Disable */

/* Bit 5 : Write '1' to disable interrupt for event STOPPED */
#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SAADC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_CALIBRATEDONE_Clear (0x1UL) /*!< Disable */

/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
#define SAADC_INTENCLR_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_RESULTDONE_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event DONE */
#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
#define SAADC_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event END */
#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SAADC_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_END_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event STARTED */
#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SAADC_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define SAADC_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define SAADC_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */

/* Register: SAADC_STATUS */
/* Description: Status */

/* Bit 0 : Status */
#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define SAADC_STATUS_STATUS_Ready (0x0UL) /*!< ADC is ready. No ongoing conversion. */
#define SAADC_STATUS_STATUS_Busy (0x1UL) /*!< ADC is busy. Single conversion in progress. */

/* Register: SAADC_ENABLE */
/* Description: Enable or disable ADC */

/* Bit 0 : Enable or disable ADC */
#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SAADC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable ADC */
#define SAADC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable ADC */

/* Register: SAADC_CH_PSELP */
/* Description: Description cluster: Input positive pin selection for CH[n] */

/* Bits 4..0 : Analog positive input channel */
#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
#define SAADC_CH_PSELP_PSELP_NC (0x00UL) /*!< Not connected */
#define SAADC_CH_PSELP_PSELP_AnalogInput0 (0x01UL) /*!< AIN0 */
#define SAADC_CH_PSELP_PSELP_AnalogInput1 (0x02UL) /*!< AIN1 */
#define SAADC_CH_PSELP_PSELP_AnalogInput2 (0x03UL) /*!< AIN2 */
#define SAADC_CH_PSELP_PSELP_AnalogInput3 (0x04UL) /*!< AIN3 */
#define SAADC_CH_PSELP_PSELP_AnalogInput4 (0x05UL) /*!< AIN4 */
#define SAADC_CH_PSELP_PSELP_AnalogInput5 (0x06UL) /*!< AIN5 */
#define SAADC_CH_PSELP_PSELP_AnalogInput6 (0x07UL) /*!< AIN6 */
#define SAADC_CH_PSELP_PSELP_AnalogInput7 (0x08UL) /*!< AIN7 */
#define SAADC_CH_PSELP_PSELP_VDD (0x09UL) /*!< VDD */
#define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */

/* Register: SAADC_CH_PSELN */
/* Description: Description cluster: Input negative pin selection for CH[n] */

/* Bits 4..0 : Analog negative input, enables differential channel */
#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
#define SAADC_CH_PSELN_PSELN_NC (0x00UL) /*!< Not connected */
#define SAADC_CH_PSELN_PSELN_AnalogInput0 (0x01UL) /*!< AIN0 */
#define SAADC_CH_PSELN_PSELN_AnalogInput1 (0x02UL) /*!< AIN1 */
#define SAADC_CH_PSELN_PSELN_AnalogInput2 (0x03UL) /*!< AIN2 */
#define SAADC_CH_PSELN_PSELN_AnalogInput3 (0x04UL) /*!< AIN3 */
#define SAADC_CH_PSELN_PSELN_AnalogInput4 (0x05UL) /*!< AIN4 */
#define SAADC_CH_PSELN_PSELN_AnalogInput5 (0x06UL) /*!< AIN5 */
#define SAADC_CH_PSELN_PSELN_AnalogInput6 (0x07UL) /*!< AIN6 */
#define SAADC_CH_PSELN_PSELN_AnalogInput7 (0x08UL) /*!< AIN7 */
#define SAADC_CH_PSELN_PSELN_VDD (0x09UL) /*!< VDD */
#define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */

/* Register: SAADC_CH_CONFIG */
/* Description: Description cluster: Input configuration for CH[n] */

/* Bit 24 : Enable burst mode */
#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
#define SAADC_CH_CONFIG_BURST_Disabled (0x0UL) /*!< Burst mode is disabled (normal operation) */
#define SAADC_CH_CONFIG_BURST_Enabled (0x1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */

/* Bit 20 : Enable differential mode */
#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
#define SAADC_CH_CONFIG_MODE_SE (0x0UL) /*!< Single-ended, PSELN will be ignored, negative input to ADC shorted to GND */
#define SAADC_CH_CONFIG_MODE_Diff (0x1UL) /*!< Differential */

/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
#define SAADC_CH_CONFIG_TACQ_3us (0x0UL) /*!< 3 us */
#define SAADC_CH_CONFIG_TACQ_5us (0x1UL) /*!< 5 us */
#define SAADC_CH_CONFIG_TACQ_10us (0x2UL) /*!< 10 us */
#define SAADC_CH_CONFIG_TACQ_15us (0x3UL) /*!< 15 us */
#define SAADC_CH_CONFIG_TACQ_20us (0x4UL) /*!< 20 us */
#define SAADC_CH_CONFIG_TACQ_40us (0x5UL) /*!< 40 us */

/* Bit 12 : Reference control */
#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
#define SAADC_CH_CONFIG_REFSEL_Internal (0x0UL) /*!< Internal reference (0.6 V) */
#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (0x1UL) /*!< VDD/4 as reference */

/* Bits 10..8 : Gain control */
#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0x0UL) /*!< 1/6 */
#define SAADC_CH_CONFIG_GAIN_Gain1_5 (0x1UL) /*!< 1/5 */
#define SAADC_CH_CONFIG_GAIN_Gain1_4 (0x2UL) /*!< 1/4 */
#define SAADC_CH_CONFIG_GAIN_Gain1_3 (0x3UL) /*!< 1/3 */
#define SAADC_CH_CONFIG_GAIN_Gain1_2 (0x4UL) /*!< 1/2 */
#define SAADC_CH_CONFIG_GAIN_Gain1 (0x5UL) /*!< 1 */
#define SAADC_CH_CONFIG_GAIN_Gain2 (0x6UL) /*!< 2 */
#define SAADC_CH_CONFIG_GAIN_Gain4 (0x7UL) /*!< 4 */

/* Bits 5..4 : Negative channel resistor control */
#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
#define SAADC_CH_CONFIG_RESN_Bypass (0x0UL) /*!< Bypass resistor ladder */
#define SAADC_CH_CONFIG_RESN_Pulldown (0x1UL) /*!< Pull-down to GND */
#define SAADC_CH_CONFIG_RESN_Pullup (0x2UL) /*!< Pull-up to VDD */
#define SAADC_CH_CONFIG_RESN_VDD1_2 (0x3UL) /*!< Set input at VDD/2 */

/* Bits 1..0 : Positive channel resistor control */
#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
#define SAADC_CH_CONFIG_RESP_Bypass (0x0UL) /*!< Bypass resistor ladder */
#define SAADC_CH_CONFIG_RESP_Pulldown (0x1UL) /*!< Pull-down to GND */
#define SAADC_CH_CONFIG_RESP_Pullup (0x2UL) /*!< Pull-up to VDD */
#define SAADC_CH_CONFIG_RESP_VDD1_2 (0x3UL) /*!< Set input at VDD/2 */

/* Register: SAADC_CH_LIMIT */
/* Description: Description cluster: High/low limits for event monitoring a channel */

/* Bits 31..16 : High level limit */
#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */

/* Bits 15..0 : Low level limit */
#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */

/* Register: SAADC_RESOLUTION */
/* Description: Resolution configuration */

/* Bits 2..0 : Set the resolution */
#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
#define SAADC_RESOLUTION_VAL_8bit (0x0UL) /*!< 8 bit */
#define SAADC_RESOLUTION_VAL_10bit (0x1UL) /*!< 10 bit */
#define SAADC_RESOLUTION_VAL_12bit (0x2UL) /*!< 12 bit */
#define SAADC_RESOLUTION_VAL_14bit (0x3UL) /*!< 14 bit */

/* Register: SAADC_OVERSAMPLE */
/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */

/* Bits 3..0 : Oversample control */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0x0UL) /*!< Bypass oversampling */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (0x1UL) /*!< Oversample 2x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (0x2UL) /*!< Oversample 4x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (0x3UL) /*!< Oversample 8x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (0x4UL) /*!< Oversample 16x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (0x5UL) /*!< Oversample 32x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (0x6UL) /*!< Oversample 64x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (0x7UL) /*!< Oversample 128x */
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (0x8UL) /*!< Oversample 256x */

/* Register: SAADC_SAMPLERATE */
/* Description: Controls normal or continuous sample rate */

/* Bit 12 : Select mode for sample rate control */
#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
#define SAADC_SAMPLERATE_MODE_Task (0x0UL) /*!< Rate is controlled from SAMPLE task */
#define SAADC_SAMPLERATE_MODE_Timers (0x1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */

/* Bits 10..0 : Capture and compare value; sample rate is 16 MHz/CC */
#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */

/* Register: SAADC_RESULT_PTR */
/* Description: Data pointer */

/* Bits 31..0 : Data pointer */
#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: SAADC_RESULT_MAXCNT */
/* Description: Maximum number of buffer words to transfer */

/* Bits 14..0 : Maximum number of buffer words to transfer */
#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: SAADC_RESULT_AMOUNT */
/* Description: Number of buffer words transferred since last START */

/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */


/* Peripheral: SPIM */
/* Description: Serial Peripheral Interface Master with EasyDMA 0 */

/* Register: SPIM_TASKS_START */
/* Description: Start SPI transaction */

/* Bit 0 : Start SPI transaction */
#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define SPIM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */

/* Register: SPIM_TASKS_STOP */
/* Description: Stop SPI transaction */

/* Bit 0 : Stop SPI transaction */
#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: SPIM_TASKS_SUSPEND */
/* Description: Suspend SPI transaction */

/* Bit 0 : Suspend SPI transaction */
#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */

/* Register: SPIM_TASKS_RESUME */
/* Description: Resume SPI transaction */

/* Bit 0 : Resume SPI transaction */
#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */

/* Register: SPIM_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */

/* Bit 31 :   */
#define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define SPIM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
#define SPIM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIM_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define SPIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define SPIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIM_SUBSCRIBE_SUSPEND */
/* Description: Subscribe configuration for task SUSPEND */

/* Bit 31 :   */
#define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
#define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */
#define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIM_SUBSCRIBE_RESUME */
/* Description: Subscribe configuration for task RESUME */

/* Bit 31 :   */
#define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
#define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */
#define SPIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
#define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIM_EVENTS_STOPPED */
/* Description: SPI transaction has stopped */

/* Bit 0 : SPI transaction has stopped */
#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */

/* Register: SPIM_EVENTS_ENDRX */
/* Description: End of RXD buffer reached */

/* Bit 0 : End of RXD buffer reached */
#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */

/* Register: SPIM_EVENTS_END */
/* Description: End of RXD buffer and TXD buffer reached */

/* Bit 0 : End of RXD buffer and TXD buffer reached */
#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
#define SPIM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */

/* Register: SPIM_EVENTS_ENDTX */
/* Description: End of TXD buffer reached */

/* Bit 0 : End of TXD buffer reached */
#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */
#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */

/* Register: SPIM_EVENTS_STARTED */
/* Description: Transaction started */

/* Bit 0 : Transaction started */
#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */

/* Register: SPIM_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */

/* Bit 31 :   */
#define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
#define SPIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIM_PUBLISH_ENDRX */
/* Description: Publish configuration for event ENDRX */

/* Bit 31 :   */
#define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
#define SPIM_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPIM_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDRX will publish to */
#define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIM_PUBLISH_END */
/* Description: Publish configuration for event END */

/* Bit 31 :   */
#define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
#define SPIM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPIM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event END will publish to */
#define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIM_PUBLISH_ENDTX */
/* Description: Publish configuration for event ENDTX */

/* Bit 31 :   */
#define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
#define SPIM_PUBLISH_ENDTX_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPIM_PUBLISH_ENDTX_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDTX will publish to */
#define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIM_PUBLISH_STARTED */
/* Description: Publish configuration for event STARTED */

/* Bit 31 :   */
#define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
#define SPIM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPIM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STARTED will publish to */
#define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIM_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 17 : Shortcut between event END and task START */
#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
#define SPIM_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */
#define SPIM_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: SPIM_INTENSET */
/* Description: Enable interrupt */

/* Bit 19 : Write '1' to enable interrupt for event STARTED */
#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SPIM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */

/* Bit 8 : Write '1' to enable interrupt for event ENDTX */
#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define SPIM_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */

/* Bit 6 : Write '1' to enable interrupt for event END */
#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SPIM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_END_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIM_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SPIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */

/* Register: SPIM_INTENCLR */
/* Description: Disable interrupt */

/* Bit 19 : Write '1' to disable interrupt for event STARTED */
#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define SPIM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */

/* Bit 8 : Write '1' to disable interrupt for event ENDTX */
#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define SPIM_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */

/* Bit 6 : Write '1' to disable interrupt for event END */
#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SPIM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_END_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIM_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define SPIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */

/* Register: SPIM_STALLSTAT */
/* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */

/* Bit 1 : Stall status for EasyDMA RAM writes */
#define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */
#define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */
#define SPIM_STALLSTAT_RX_NOSTALL (0x0UL) /*!< No stall */
#define SPIM_STALLSTAT_RX_STALL (0x1UL) /*!< A stall has occurred */

/* Bit 0 : Stall status for EasyDMA RAM reads */
#define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */
#define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */
#define SPIM_STALLSTAT_TX_NOSTALL (0x0UL) /*!< No stall */
#define SPIM_STALLSTAT_TX_STALL (0x1UL) /*!< A stall has occurred */

/* Register: SPIM_ENABLE */
/* Description: Enable SPIM */

/* Bits 3..0 : Enable or disable SPIM */
#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SPIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPIM */
#define SPIM_ENABLE_ENABLE_Enabled (0x7UL) /*!< Enable SPIM */

/* Register: SPIM_PSEL_SCK */
/* Description: Pin select for SCK */

/* Bit 31 : Connection */
#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
#define SPIM_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
#define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: SPIM_PSEL_MOSI */
/* Description: Pin select for MOSI signal */

/* Bit 31 : Connection */
#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */
#define SPIM_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
#define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: SPIM_PSEL_MISO */
/* Description: Pin select for MISO signal */

/* Bit 31 : Connection */
#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */
#define SPIM_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
#define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: SPIM_PSEL_CSN */
/* Description: Pin select for CSN */

/* Bit 31 : Connection */
#define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */
#define SPIM_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
#define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: SPIM_FREQUENCY */
/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */

/* Bits 31..0 : SPI master data rate */
#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
#define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */

/* Register: SPIM_RXD_PTR */
/* Description: Data pointer */

/* Bits 31..0 : Data pointer */
#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: SPIM_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */

/* Bits 15..0 : Maximum number of bytes in receive buffer */
#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: SPIM_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */

/* Bits 15..0 : Number of bytes transferred in the last transaction */
#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: SPIM_RXD_LIST */
/* Description: EasyDMA list type */

/* Bits 1..0 : List type */
#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define SPIM_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
#define SPIM_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */

/* Register: SPIM_TXD_PTR */
/* Description: Data pointer */

/* Bits 31..0 : Data pointer */
#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: SPIM_TXD_MAXCNT */
/* Description: Number of bytes in transmit buffer */

/* Bits 15..0 : Maximum number of bytes in transmit buffer */
#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: SPIM_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */

/* Bits 15..0 : Number of bytes transferred in the last transaction */
#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: SPIM_TXD_LIST */
/* Description: EasyDMA list type */

/* Bits 1..0 : List type */
#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define SPIM_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
#define SPIM_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */

/* Register: SPIM_CONFIG */
/* Description: Configuration register */

/* Bit 2 : Serial clock (SCK) polarity */
#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
#define SPIM_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */
#define SPIM_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */

/* Bit 1 : Serial clock (SCK) phase */
#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
#define SPIM_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
#define SPIM_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */

/* Bit 0 : Bit order */
#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
#define SPIM_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */
#define SPIM_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */

/* Register: SPIM_IFTIMING_RXDELAY */
/* Description: Sample delay for input serial data on MISO */

/* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */
#define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */
#define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */

/* Register: SPIM_IFTIMING_CSNDUR */
/* Description: Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. */

/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */
#define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */
#define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */

/* Register: SPIM_CSNPOL */
/* Description: Polarity of CSN output */

/* Bit 0 : Polarity of CSN output */
#define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */
#define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */
#define SPIM_CSNPOL_CSNPOL_LOW (0x0UL) /*!< Active low (idle state high) */
#define SPIM_CSNPOL_CSNPOL_HIGH (0x1UL) /*!< Active high (idle state low) */

/* Register: SPIM_PSELDCX */
/* Description: Pin select for DCX signal */

/* Bit 31 : Connection */
#define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSELDCX_CONNECT_Connected (0x0UL) /*!< Connect */
#define SPIM_PSELDCX_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */
#define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: SPIM_DCXCNT */
/* Description: DCX configuration */

/* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */
#define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */
#define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */

/* Register: SPIM_ORC */
/* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */

/* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */
#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */


/* Peripheral: SPIS */
/* Description: SPI Slave 0 */

/* Register: SPIS_TASKS_ACQUIRE */
/* Description: Acquire SPI semaphore */

/* Bit 0 : Acquire SPI semaphore */
#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (0x1UL) /*!< Trigger task */

/* Register: SPIS_TASKS_RELEASE */
/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */

/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (0x1UL) /*!< Trigger task */

/* Register: SPIS_SUBSCRIBE_ACQUIRE */
/* Description: Subscribe configuration for task ACQUIRE */

/* Bit 31 :   */
#define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */
#define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */
#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIS_SUBSCRIBE_RELEASE */
/* Description: Subscribe configuration for task RELEASE */

/* Bit 31 :   */
#define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */
#define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */
#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIS_EVENTS_END */
/* Description: Granted transaction completed */

/* Bit 0 : Granted transaction completed */
#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */
#define SPIS_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */

/* Register: SPIS_EVENTS_ENDRX */
/* Description: End of RXD buffer reached */

/* Bit 0 : End of RXD buffer reached */
#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */

/* Register: SPIS_EVENTS_ACQUIRED */
/* Description: Semaphore acquired */

/* Bit 0 : Semaphore acquired */
#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0x0UL) /*!< Event not generated */
#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (0x1UL) /*!< Event generated */

/* Register: SPIS_PUBLISH_END */
/* Description: Publish configuration for event END */

/* Bit 31 :   */
#define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
#define SPIS_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPIS_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event END will publish to */
#define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIS_PUBLISH_ENDRX */
/* Description: Publish configuration for event ENDRX */

/* Bit 31 :   */
#define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
#define SPIS_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPIS_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDRX will publish to */
#define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIS_PUBLISH_ACQUIRED */
/* Description: Publish configuration for event ACQUIRED */

/* Bit 31 :   */
#define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */
#define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */
#define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPIS_PUBLISH_ACQUIRED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ACQUIRED will publish to */
#define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPIS_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 2 : Shortcut between event END and task ACQUIRE */
#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
#define SPIS_SHORTS_END_ACQUIRE_Disabled (0x0UL) /*!< Disable shortcut */
#define SPIS_SHORTS_END_ACQUIRE_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: SPIS_INTENSET */
/* Description: Enable interrupt */

/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
#define SPIS_INTENSET_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIS_INTENSET_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIS_INTENSET_ACQUIRED_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIS_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIS_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIS_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event END */
#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
#define SPIS_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIS_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIS_INTENSET_END_Set (0x1UL) /*!< Enable */

/* Register: SPIS_INTENCLR */
/* Description: Disable interrupt */

/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
#define SPIS_INTENCLR_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIS_INTENCLR_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIS_INTENCLR_ACQUIRED_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIS_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIS_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIS_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event END */
#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
#define SPIS_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */
#define SPIS_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */
#define SPIS_INTENCLR_END_Clear (0x1UL) /*!< Disable */

/* Register: SPIS_SEMSTAT */
/* Description: Semaphore status register */

/* Bits 1..0 : Semaphore status */
#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
#define SPIS_SEMSTAT_SEMSTAT_Free (0x0UL) /*!< Semaphore is free */
#define SPIS_SEMSTAT_SEMSTAT_CPU (0x1UL) /*!< Semaphore is assigned to CPU */
#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x2UL) /*!< Semaphore is assigned to SPI slave */
#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */

/* Register: SPIS_STATUS */
/* Description: Status from last transaction */

/* Bit 1 : RX buffer overflow detected, and prevented */
#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
#define SPIS_STATUS_OVERFLOW_NotPresent (0x0UL) /*!< Read: error not present */
#define SPIS_STATUS_OVERFLOW_Present (0x1UL) /*!< Read: error present */
#define SPIS_STATUS_OVERFLOW_Clear (0x1UL) /*!< Write: clear error on writing '1' */

/* Bit 0 : TX buffer over-read detected, and prevented */
#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
#define SPIS_STATUS_OVERREAD_NotPresent (0x0UL) /*!< Read: error not present */
#define SPIS_STATUS_OVERREAD_Present (0x1UL) /*!< Read: error present */
#define SPIS_STATUS_OVERREAD_Clear (0x1UL) /*!< Write: clear error on writing '1' */

/* Register: SPIS_ENABLE */
/* Description: Enable SPI slave */

/* Bits 3..0 : Enable or disable SPI slave */
#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define SPIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPI slave */
#define SPIS_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable SPI slave */

/* Register: SPIS_PSEL_SCK */
/* Description: Pin select for SCK */

/* Bit 31 : Connection */
#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */
#define SPIS_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
#define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: SPIS_PSEL_MISO */
/* Description: Pin select for MISO signal */

/* Bit 31 : Connection */
#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */
#define SPIS_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
#define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: SPIS_PSEL_MOSI */
/* Description: Pin select for MOSI signal */

/* Bit 31 : Connection */
#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */
#define SPIS_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
#define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: SPIS_PSEL_CSN */
/* Description: Pin select for CSN signal */

/* Bit 31 : Connection */
#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIS_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */
#define SPIS_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
#define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: SPIS_RXD_PTR */
/* Description: RXD data pointer */

/* Bits 31..0 : RXD data pointer */
#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: SPIS_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */

/* Bits 15..0 : Maximum number of bytes in receive buffer */
#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: SPIS_RXD_AMOUNT */
/* Description: Number of bytes received in last granted transaction */

/* Bits 15..0 : Number of bytes received in the last granted transaction */
#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: SPIS_RXD_LIST */
/* Description: EasyDMA list type */

/* Bits 1..0 : List type */
#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define SPIS_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
#define SPIS_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */

/* Register: SPIS_TXD_PTR */
/* Description: TXD data pointer */

/* Bits 31..0 : TXD data pointer */
#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: SPIS_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */

/* Bits 15..0 : Maximum number of bytes in transmit buffer */
#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: SPIS_TXD_AMOUNT */
/* Description: Number of bytes transmitted in last granted transaction */

/* Bits 15..0 : Number of bytes transmitted in last granted transaction */
#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: SPIS_TXD_LIST */
/* Description: EasyDMA list type */

/* Bits 1..0 : List type */
#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define SPIS_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
#define SPIS_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */

/* Register: SPIS_CONFIG */
/* Description: Configuration register */

/* Bit 2 : Serial clock (SCK) polarity */
#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
#define SPIS_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */
#define SPIS_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */

/* Bit 1 : Serial clock (SCK) phase */
#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
#define SPIS_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
#define SPIS_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */

/* Bit 0 : Bit order */
#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
#define SPIS_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */
#define SPIS_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */

/* Register: SPIS_DEF */
/* Description: Default character. Character clocked out in case of an ignored transaction. */

/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */

/* Register: SPIS_ORC */
/* Description: Over-read character */

/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */


/* Peripheral: SPU */
/* Description: System protection unit */

/* Register: SPU_EVENTS_RAMACCERR */
/* Description: A security violation has been detected for the RAM memory space */

/* Bit 0 : A security violation has been detected for the RAM memory space */
#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL) /*!< Position of EVENTS_RAMACCERR field. */
#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos) /*!< Bit mask of EVENTS_RAMACCERR field. */
#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0x0UL) /*!< Event not generated */
#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (0x1UL) /*!< Event generated */

/* Register: SPU_EVENTS_FLASHACCERR */
/* Description: A security violation has been detected for the flash memory space */

/* Bit 0 : A security violation has been detected for the flash memory space */
#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL) /*!< Position of EVENTS_FLASHACCERR field. */
#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos) /*!< Bit mask of EVENTS_FLASHACCERR field. */
#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0x0UL) /*!< Event not generated */
#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (0x1UL) /*!< Event generated */

/* Register: SPU_EVENTS_PERIPHACCERR */
/* Description: A security violation has been detected on one or several peripherals */

/* Bit 0 : A security violation has been detected on one or several peripherals */
#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */
#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit mask of EVENTS_PERIPHACCERR field. */
#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0x0UL) /*!< Event not generated */
#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (0x1UL) /*!< Event generated */

/* Register: SPU_PUBLISH_RAMACCERR */
/* Description: Publish configuration for event RAMACCERR */

/* Bit 31 :   */
#define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL) /*!< Position of EN field. */
#define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos) /*!< Bit mask of EN field. */
#define SPU_PUBLISH_RAMACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPU_PUBLISH_RAMACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RAMACCERR will publish to */
#define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPU_PUBLISH_FLASHACCERR */
/* Description: Publish configuration for event FLASHACCERR */

/* Bit 31 :   */
#define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
#define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos) /*!< Bit mask of EN field. */
#define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPU_PUBLISH_FLASHACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to */
#define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPU_PUBLISH_PERIPHACCERR */
/* Description: Publish configuration for event PERIPHACCERR */

/* Bit 31 :   */
#define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
#define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos) /*!< Bit mask of EN field. */
#define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */
#define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to */
#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: SPU_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */
#define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
#define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
#define SPU_INTEN_PERIPHACCERR_Disabled (0x0UL) /*!< Disable */
#define SPU_INTEN_PERIPHACCERR_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event FLASHACCERR */
#define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
#define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
#define SPU_INTEN_FLASHACCERR_Disabled (0x0UL) /*!< Disable */
#define SPU_INTEN_FLASHACCERR_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event RAMACCERR */
#define SPU_INTEN_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
#define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
#define SPU_INTEN_RAMACCERR_Disabled (0x0UL) /*!< Disable */
#define SPU_INTEN_RAMACCERR_Enabled (0x1UL) /*!< Enable */

/* Register: SPU_INTENSET */
/* Description: Enable interrupt */

/* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */
#define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
#define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
#define SPU_INTENSET_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */
#define SPU_INTENSET_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */
#define SPU_INTENSET_PERIPHACCERR_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */
#define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
#define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
#define SPU_INTENSET_FLASHACCERR_Disabled (0x0UL) /*!< Read: Disabled */
#define SPU_INTENSET_FLASHACCERR_Enabled (0x1UL) /*!< Read: Enabled */
#define SPU_INTENSET_FLASHACCERR_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */
#define SPU_INTENSET_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
#define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
#define SPU_INTENSET_RAMACCERR_Disabled (0x0UL) /*!< Read: Disabled */
#define SPU_INTENSET_RAMACCERR_Enabled (0x1UL) /*!< Read: Enabled */
#define SPU_INTENSET_RAMACCERR_Set (0x1UL) /*!< Enable */

/* Register: SPU_INTENCLR */
/* Description: Disable interrupt */

/* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */
#define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
#define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
#define SPU_INTENCLR_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */
#define SPU_INTENCLR_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */
#define SPU_INTENCLR_PERIPHACCERR_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */
#define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
#define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
#define SPU_INTENCLR_FLASHACCERR_Disabled (0x0UL) /*!< Read: Disabled */
#define SPU_INTENCLR_FLASHACCERR_Enabled (0x1UL) /*!< Read: Enabled */
#define SPU_INTENCLR_FLASHACCERR_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */
#define SPU_INTENCLR_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
#define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
#define SPU_INTENCLR_RAMACCERR_Disabled (0x0UL) /*!< Read: Disabled */
#define SPU_INTENCLR_RAMACCERR_Enabled (0x1UL) /*!< Read: Enabled */
#define SPU_INTENCLR_RAMACCERR_Clear (0x1UL) /*!< Disable */

/* Register: SPU_CAP */
/* Description: Show implemented features for the current device */

/* Bit 0 : Show Arm TrustZone status */
#define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */
#define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */
#define SPU_CAP_TZM_NotAvailable (0x0UL) /*!< Arm TrustZone support not available */
#define SPU_CAP_TZM_Enabled (0x1UL) /*!< Arm TrustZone support is available */

/* Register: SPU_CPULOCK */
/* Description: Configure bits to lock down CPU features at runtime */

/* Bit 4 : Write '1' to prevent updating the secure SAU regions until the next reset */
#define SPU_CPULOCK_LOCKSAU_Pos (4UL) /*!< Position of LOCKSAU field. */
#define SPU_CPULOCK_LOCKSAU_Msk (0x1UL << SPU_CPULOCK_LOCKSAU_Pos) /*!< Bit mask of LOCKSAU field. */
#define SPU_CPULOCK_LOCKSAU_Unlocked (0x0UL) /*!< These registers can be updated */
#define SPU_CPULOCK_LOCKSAU_Locked (0x1UL) /*!< Disables writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor */

/* Bit 3 : Write '1' to prevent updating the Non-secure MPU regions until the next reset */
#define SPU_CPULOCK_LOCKNSMPU_Pos (3UL) /*!< Position of LOCKNSMPU field. */
#define SPU_CPULOCK_LOCKNSMPU_Msk (0x1UL << SPU_CPULOCK_LOCKNSMPU_Pos) /*!< Bit mask of LOCKNSMPU field. */
#define SPU_CPULOCK_LOCKNSMPU_Unlocked (0x0UL) /*!< These registers can be updated */
#define SPU_CPULOCK_LOCKNSMPU_Locked (0x1UL) /*!< Disables writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn from software or from a debug agent connected to the processor */

/* Bit 2 : Write '1' to prevent updating the secure MPU regions until the next reset */
#define SPU_CPULOCK_LOCKSMPU_Pos (2UL) /*!< Position of LOCKSMPU field. */
#define SPU_CPULOCK_LOCKSMPU_Msk (0x1UL << SPU_CPULOCK_LOCKSMPU_Pos) /*!< Bit mask of LOCKSMPU field. */
#define SPU_CPULOCK_LOCKSMPU_Unlocked (0x0UL) /*!< These registers can be updated */
#define SPU_CPULOCK_LOCKSMPU_Locked (0x1UL) /*!< Disables writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or from a debug agent connected to the processor in Secure state */

/* Bit 1 : Write '1' to prevent updating the non-secure vector table base address until the next reset */
#define SPU_CPULOCK_LOCKNSVTOR_Pos (1UL) /*!< Position of LOCKNSVTOR field. */
#define SPU_CPULOCK_LOCKNSVTOR_Msk (0x1UL << SPU_CPULOCK_LOCKNSVTOR_Pos) /*!< Bit mask of LOCKNSVTOR field. */
#define SPU_CPULOCK_LOCKNSVTOR_Unlocked (0x0UL) /*!< The address of the non-secure vector table can be updated */
#define SPU_CPULOCK_LOCKNSVTOR_Locked (0x1UL) /*!< The address of the non-secure vector table is locked */

/* Bit 0 : Write '1' to prevent updating the secure interrupt configuration until the next reset */
#define SPU_CPULOCK_LOCKSVTAIRCR_Pos (0UL) /*!< Position of LOCKSVTAIRCR field. */
#define SPU_CPULOCK_LOCKSVTAIRCR_Msk (0x1UL << SPU_CPULOCK_LOCKSVTAIRCR_Pos) /*!< Bit mask of LOCKSVTAIRCR field. */
#define SPU_CPULOCK_LOCKSVTAIRCR_Unlocked (0x0UL) /*!< These registers can be updated */
#define SPU_CPULOCK_LOCKSVTAIRCR_Locked (0x1UL) /*!< Disables writes to the VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS registers */

/* Register: SPU_EXTDOMAIN_PERM */
/* Description: Description cluster: Access  for bus access generated from the external domain n List capabilities of the external domain  n */

/* Bit 8 :   */
#define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
#define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
#define SPU_EXTDOMAIN_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */

/* Bit 4 : Peripheral security mapping */
#define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
#define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
#define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0x0UL) /*!< Bus accesses from this domain have the non-secure attribute set */
#define SPU_EXTDOMAIN_PERM_SECATTR_Secure (0x1UL) /*!< Bus accesses from this domain have secure attribute set */

/* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< The bus access from this external domain always have the non-secure attribute set */
#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (0x1UL) /*!< The bus access from this external domain always have the secure attribute set */
#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */

/* Register: SPU_DPPI_PERM */
/* Description: Description cluster: Select between secure and non-secure attribute  for the DPPI channels */

/* Bit 31 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL31_Pos (31UL) /*!< Position of CHANNEL31 field. */
#define SPU_DPPI_PERM_CHANNEL31_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL31_Pos) /*!< Bit mask of CHANNEL31 field. */
#define SPU_DPPI_PERM_CHANNEL31_NonSecure (0x0UL) /*!< Channel 31 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL31_Secure (0x1UL) /*!< Channel 31 has its secure attribute set */

/* Bit 30 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL30_Pos (30UL) /*!< Position of CHANNEL30 field. */
#define SPU_DPPI_PERM_CHANNEL30_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL30_Pos) /*!< Bit mask of CHANNEL30 field. */
#define SPU_DPPI_PERM_CHANNEL30_NonSecure (0x0UL) /*!< Channel 30 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL30_Secure (0x1UL) /*!< Channel 30 has its secure attribute set */

/* Bit 29 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL29_Pos (29UL) /*!< Position of CHANNEL29 field. */
#define SPU_DPPI_PERM_CHANNEL29_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL29_Pos) /*!< Bit mask of CHANNEL29 field. */
#define SPU_DPPI_PERM_CHANNEL29_NonSecure (0x0UL) /*!< Channel 29 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL29_Secure (0x1UL) /*!< Channel 29 has its secure attribute set */

/* Bit 28 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL28_Pos (28UL) /*!< Position of CHANNEL28 field. */
#define SPU_DPPI_PERM_CHANNEL28_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL28_Pos) /*!< Bit mask of CHANNEL28 field. */
#define SPU_DPPI_PERM_CHANNEL28_NonSecure (0x0UL) /*!< Channel 28 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL28_Secure (0x1UL) /*!< Channel 28 has its secure attribute set */

/* Bit 27 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL27_Pos (27UL) /*!< Position of CHANNEL27 field. */
#define SPU_DPPI_PERM_CHANNEL27_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL27_Pos) /*!< Bit mask of CHANNEL27 field. */
#define SPU_DPPI_PERM_CHANNEL27_NonSecure (0x0UL) /*!< Channel 27 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL27_Secure (0x1UL) /*!< Channel 27 has its secure attribute set */

/* Bit 26 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL26_Pos (26UL) /*!< Position of CHANNEL26 field. */
#define SPU_DPPI_PERM_CHANNEL26_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL26_Pos) /*!< Bit mask of CHANNEL26 field. */
#define SPU_DPPI_PERM_CHANNEL26_NonSecure (0x0UL) /*!< Channel 26 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL26_Secure (0x1UL) /*!< Channel 26 has its secure attribute set */

/* Bit 25 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL25_Pos (25UL) /*!< Position of CHANNEL25 field. */
#define SPU_DPPI_PERM_CHANNEL25_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL25_Pos) /*!< Bit mask of CHANNEL25 field. */
#define SPU_DPPI_PERM_CHANNEL25_NonSecure (0x0UL) /*!< Channel 25 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL25_Secure (0x1UL) /*!< Channel 25 has its secure attribute set */

/* Bit 24 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL24_Pos (24UL) /*!< Position of CHANNEL24 field. */
#define SPU_DPPI_PERM_CHANNEL24_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL24_Pos) /*!< Bit mask of CHANNEL24 field. */
#define SPU_DPPI_PERM_CHANNEL24_NonSecure (0x0UL) /*!< Channel 24 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL24_Secure (0x1UL) /*!< Channel 24 has its secure attribute set */

/* Bit 23 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL23_Pos (23UL) /*!< Position of CHANNEL23 field. */
#define SPU_DPPI_PERM_CHANNEL23_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL23_Pos) /*!< Bit mask of CHANNEL23 field. */
#define SPU_DPPI_PERM_CHANNEL23_NonSecure (0x0UL) /*!< Channel 23 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL23_Secure (0x1UL) /*!< Channel 23 has its secure attribute set */

/* Bit 22 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL22_Pos (22UL) /*!< Position of CHANNEL22 field. */
#define SPU_DPPI_PERM_CHANNEL22_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL22_Pos) /*!< Bit mask of CHANNEL22 field. */
#define SPU_DPPI_PERM_CHANNEL22_NonSecure (0x0UL) /*!< Channel 22 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL22_Secure (0x1UL) /*!< Channel 22 has its secure attribute set */

/* Bit 21 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL21_Pos (21UL) /*!< Position of CHANNEL21 field. */
#define SPU_DPPI_PERM_CHANNEL21_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL21_Pos) /*!< Bit mask of CHANNEL21 field. */
#define SPU_DPPI_PERM_CHANNEL21_NonSecure (0x0UL) /*!< Channel 21 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL21_Secure (0x1UL) /*!< Channel 21 has its secure attribute set */

/* Bit 20 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL20_Pos (20UL) /*!< Position of CHANNEL20 field. */
#define SPU_DPPI_PERM_CHANNEL20_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL20_Pos) /*!< Bit mask of CHANNEL20 field. */
#define SPU_DPPI_PERM_CHANNEL20_NonSecure (0x0UL) /*!< Channel 20 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL20_Secure (0x1UL) /*!< Channel 20 has its secure attribute set */

/* Bit 19 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL19_Pos (19UL) /*!< Position of CHANNEL19 field. */
#define SPU_DPPI_PERM_CHANNEL19_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL19_Pos) /*!< Bit mask of CHANNEL19 field. */
#define SPU_DPPI_PERM_CHANNEL19_NonSecure (0x0UL) /*!< Channel 19 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL19_Secure (0x1UL) /*!< Channel 19 has its secure attribute set */

/* Bit 18 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL18_Pos (18UL) /*!< Position of CHANNEL18 field. */
#define SPU_DPPI_PERM_CHANNEL18_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL18_Pos) /*!< Bit mask of CHANNEL18 field. */
#define SPU_DPPI_PERM_CHANNEL18_NonSecure (0x0UL) /*!< Channel 18 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL18_Secure (0x1UL) /*!< Channel 18 has its secure attribute set */

/* Bit 17 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL17_Pos (17UL) /*!< Position of CHANNEL17 field. */
#define SPU_DPPI_PERM_CHANNEL17_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL17_Pos) /*!< Bit mask of CHANNEL17 field. */
#define SPU_DPPI_PERM_CHANNEL17_NonSecure (0x0UL) /*!< Channel 17 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL17_Secure (0x1UL) /*!< Channel 17 has its secure attribute set */

/* Bit 16 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL16_Pos (16UL) /*!< Position of CHANNEL16 field. */
#define SPU_DPPI_PERM_CHANNEL16_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL16_Pos) /*!< Bit mask of CHANNEL16 field. */
#define SPU_DPPI_PERM_CHANNEL16_NonSecure (0x0UL) /*!< Channel 16 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL16_Secure (0x1UL) /*!< Channel 16 has its secure attribute set */

/* Bit 15 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */
#define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */
#define SPU_DPPI_PERM_CHANNEL15_NonSecure (0x0UL) /*!< Channel 15 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL15_Secure (0x1UL) /*!< Channel 15 has its secure attribute set */

/* Bit 14 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */
#define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */
#define SPU_DPPI_PERM_CHANNEL14_NonSecure (0x0UL) /*!< Channel 14 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL14_Secure (0x1UL) /*!< Channel 14 has its secure attribute set */

/* Bit 13 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */
#define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */
#define SPU_DPPI_PERM_CHANNEL13_NonSecure (0x0UL) /*!< Channel 13 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL13_Secure (0x1UL) /*!< Channel 13 has its secure attribute set */

/* Bit 12 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */
#define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */
#define SPU_DPPI_PERM_CHANNEL12_NonSecure (0x0UL) /*!< Channel 12 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL12_Secure (0x1UL) /*!< Channel 12 has its secure attribute set */

/* Bit 11 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */
#define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */
#define SPU_DPPI_PERM_CHANNEL11_NonSecure (0x0UL) /*!< Channel 11 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL11_Secure (0x1UL) /*!< Channel 11 has its secure attribute set */

/* Bit 10 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */
#define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */
#define SPU_DPPI_PERM_CHANNEL10_NonSecure (0x0UL) /*!< Channel 10 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL10_Secure (0x1UL) /*!< Channel 10 has its secure attribute set */

/* Bit 9 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */
#define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */
#define SPU_DPPI_PERM_CHANNEL9_NonSecure (0x0UL) /*!< Channel 9 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL9_Secure (0x1UL) /*!< Channel 9 has its secure attribute set */

/* Bit 8 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */
#define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */
#define SPU_DPPI_PERM_CHANNEL8_NonSecure (0x0UL) /*!< Channel 8 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL8_Secure (0x1UL) /*!< Channel 8 has its secure attribute set */

/* Bit 7 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */
#define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */
#define SPU_DPPI_PERM_CHANNEL7_NonSecure (0x0UL) /*!< Channel 7 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL7_Secure (0x1UL) /*!< Channel 7 has its secure attribute set */

/* Bit 6 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */
#define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */
#define SPU_DPPI_PERM_CHANNEL6_NonSecure (0x0UL) /*!< Channel 6 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL6_Secure (0x1UL) /*!< Channel 6 has its secure attribute set */

/* Bit 5 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */
#define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */
#define SPU_DPPI_PERM_CHANNEL5_NonSecure (0x0UL) /*!< Channel 5 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL5_Secure (0x1UL) /*!< Channel 5 has its secure attribute set */

/* Bit 4 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */
#define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */
#define SPU_DPPI_PERM_CHANNEL4_NonSecure (0x0UL) /*!< Channel 4 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL4_Secure (0x1UL) /*!< Channel 4 has its secure attribute set */

/* Bit 3 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */
#define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */
#define SPU_DPPI_PERM_CHANNEL3_NonSecure (0x0UL) /*!< Channel 3 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL3_Secure (0x1UL) /*!< Channel 3 has its secure attribute set */

/* Bit 2 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */
#define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */
#define SPU_DPPI_PERM_CHANNEL2_NonSecure (0x0UL) /*!< Channel 2 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL2_Secure (0x1UL) /*!< Channel 2 has its secure attribute set */

/* Bit 1 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */
#define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */
#define SPU_DPPI_PERM_CHANNEL1_NonSecure (0x0UL) /*!< Channel 1 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL1_Secure (0x1UL) /*!< Channel 1 has its secure attribute set */

/* Bit 0 : Select secure attribute */
#define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */
#define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */
#define SPU_DPPI_PERM_CHANNEL0_NonSecure (0x0UL) /*!< Channel 0 has its non-secure attribute set */
#define SPU_DPPI_PERM_CHANNEL0_Secure (0x1UL) /*!< Channel 0 has its secure attribute set */

/* Register: SPU_DPPI_LOCK */
/* Description: Description cluster: Prevent further modification of the corresponding PERM register */

/* Bit 0 :   */
#define SPU_DPPI_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
#define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define SPU_DPPI_LOCK_LOCK_Unlocked (0x0UL) /*!< DPPI[n].PERM register content can be changed */
#define SPU_DPPI_LOCK_LOCK_Locked (0x1UL) /*!< DPPI[n].PERM register can't be changed until next reset */

/* Register: SPU_GPIOPORT_PERM */
/* Description: Description cluster: Select between secure and non-secure attribute  for pins 0 to 31  of port n */

/* Bit 31 : Select secure attribute attribute for PIN 31. */
#define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
#define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos) /*!< Bit mask of PIN31 field. */
#define SPU_GPIOPORT_PERM_PIN31_NonSecure (0x0UL) /*!< Pin 31 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN31_Secure (0x1UL) /*!< Pin 31 has its secure attribute set */

/* Bit 30 : Select secure attribute attribute for PIN 30. */
#define SPU_GPIOPORT_PERM_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
#define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos) /*!< Bit mask of PIN30 field. */
#define SPU_GPIOPORT_PERM_PIN30_NonSecure (0x0UL) /*!< Pin 30 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN30_Secure (0x1UL) /*!< Pin 30 has its secure attribute set */

/* Bit 29 : Select secure attribute attribute for PIN 29. */
#define SPU_GPIOPORT_PERM_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
#define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos) /*!< Bit mask of PIN29 field. */
#define SPU_GPIOPORT_PERM_PIN29_NonSecure (0x0UL) /*!< Pin 29 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN29_Secure (0x1UL) /*!< Pin 29 has its secure attribute set */

/* Bit 28 : Select secure attribute attribute for PIN 28. */
#define SPU_GPIOPORT_PERM_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
#define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos) /*!< Bit mask of PIN28 field. */
#define SPU_GPIOPORT_PERM_PIN28_NonSecure (0x0UL) /*!< Pin 28 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN28_Secure (0x1UL) /*!< Pin 28 has its secure attribute set */

/* Bit 27 : Select secure attribute attribute for PIN 27. */
#define SPU_GPIOPORT_PERM_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
#define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos) /*!< Bit mask of PIN27 field. */
#define SPU_GPIOPORT_PERM_PIN27_NonSecure (0x0UL) /*!< Pin 27 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN27_Secure (0x1UL) /*!< Pin 27 has its secure attribute set */

/* Bit 26 : Select secure attribute attribute for PIN 26. */
#define SPU_GPIOPORT_PERM_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
#define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos) /*!< Bit mask of PIN26 field. */
#define SPU_GPIOPORT_PERM_PIN26_NonSecure (0x0UL) /*!< Pin 26 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN26_Secure (0x1UL) /*!< Pin 26 has its secure attribute set */

/* Bit 25 : Select secure attribute attribute for PIN 25. */
#define SPU_GPIOPORT_PERM_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
#define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos) /*!< Bit mask of PIN25 field. */
#define SPU_GPIOPORT_PERM_PIN25_NonSecure (0x0UL) /*!< Pin 25 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN25_Secure (0x1UL) /*!< Pin 25 has its secure attribute set */

/* Bit 24 : Select secure attribute attribute for PIN 24. */
#define SPU_GPIOPORT_PERM_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
#define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos) /*!< Bit mask of PIN24 field. */
#define SPU_GPIOPORT_PERM_PIN24_NonSecure (0x0UL) /*!< Pin 24 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN24_Secure (0x1UL) /*!< Pin 24 has its secure attribute set */

/* Bit 23 : Select secure attribute attribute for PIN 23. */
#define SPU_GPIOPORT_PERM_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
#define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos) /*!< Bit mask of PIN23 field. */
#define SPU_GPIOPORT_PERM_PIN23_NonSecure (0x0UL) /*!< Pin 23 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN23_Secure (0x1UL) /*!< Pin 23 has its secure attribute set */

/* Bit 22 : Select secure attribute attribute for PIN 22. */
#define SPU_GPIOPORT_PERM_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
#define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos) /*!< Bit mask of PIN22 field. */
#define SPU_GPIOPORT_PERM_PIN22_NonSecure (0x0UL) /*!< Pin 22 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN22_Secure (0x1UL) /*!< Pin 22 has its secure attribute set */

/* Bit 21 : Select secure attribute attribute for PIN 21. */
#define SPU_GPIOPORT_PERM_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
#define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos) /*!< Bit mask of PIN21 field. */
#define SPU_GPIOPORT_PERM_PIN21_NonSecure (0x0UL) /*!< Pin 21 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN21_Secure (0x1UL) /*!< Pin 21 has its secure attribute set */

/* Bit 20 : Select secure attribute attribute for PIN 20. */
#define SPU_GPIOPORT_PERM_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
#define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos) /*!< Bit mask of PIN20 field. */
#define SPU_GPIOPORT_PERM_PIN20_NonSecure (0x0UL) /*!< Pin 20 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN20_Secure (0x1UL) /*!< Pin 20 has its secure attribute set */

/* Bit 19 : Select secure attribute attribute for PIN 19. */
#define SPU_GPIOPORT_PERM_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
#define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos) /*!< Bit mask of PIN19 field. */
#define SPU_GPIOPORT_PERM_PIN19_NonSecure (0x0UL) /*!< Pin 19 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN19_Secure (0x1UL) /*!< Pin 19 has its secure attribute set */

/* Bit 18 : Select secure attribute attribute for PIN 18. */
#define SPU_GPIOPORT_PERM_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
#define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos) /*!< Bit mask of PIN18 field. */
#define SPU_GPIOPORT_PERM_PIN18_NonSecure (0x0UL) /*!< Pin 18 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN18_Secure (0x1UL) /*!< Pin 18 has its secure attribute set */

/* Bit 17 : Select secure attribute attribute for PIN 17. */
#define SPU_GPIOPORT_PERM_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
#define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos) /*!< Bit mask of PIN17 field. */
#define SPU_GPIOPORT_PERM_PIN17_NonSecure (0x0UL) /*!< Pin 17 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN17_Secure (0x1UL) /*!< Pin 17 has its secure attribute set */

/* Bit 16 : Select secure attribute attribute for PIN 16. */
#define SPU_GPIOPORT_PERM_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
#define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos) /*!< Bit mask of PIN16 field. */
#define SPU_GPIOPORT_PERM_PIN16_NonSecure (0x0UL) /*!< Pin 16 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN16_Secure (0x1UL) /*!< Pin 16 has its secure attribute set */

/* Bit 15 : Select secure attribute attribute for PIN 15. */
#define SPU_GPIOPORT_PERM_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
#define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos) /*!< Bit mask of PIN15 field. */
#define SPU_GPIOPORT_PERM_PIN15_NonSecure (0x0UL) /*!< Pin 15 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN15_Secure (0x1UL) /*!< Pin 15 has its secure attribute set */

/* Bit 14 : Select secure attribute attribute for PIN 14. */
#define SPU_GPIOPORT_PERM_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
#define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos) /*!< Bit mask of PIN14 field. */
#define SPU_GPIOPORT_PERM_PIN14_NonSecure (0x0UL) /*!< Pin 14 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN14_Secure (0x1UL) /*!< Pin 14 has its secure attribute set */

/* Bit 13 : Select secure attribute attribute for PIN 13. */
#define SPU_GPIOPORT_PERM_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
#define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos) /*!< Bit mask of PIN13 field. */
#define SPU_GPIOPORT_PERM_PIN13_NonSecure (0x0UL) /*!< Pin 13 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN13_Secure (0x1UL) /*!< Pin 13 has its secure attribute set */

/* Bit 12 : Select secure attribute attribute for PIN 12. */
#define SPU_GPIOPORT_PERM_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
#define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos) /*!< Bit mask of PIN12 field. */
#define SPU_GPIOPORT_PERM_PIN12_NonSecure (0x0UL) /*!< Pin 12 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN12_Secure (0x1UL) /*!< Pin 12 has its secure attribute set */

/* Bit 11 : Select secure attribute attribute for PIN 11. */
#define SPU_GPIOPORT_PERM_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
#define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos) /*!< Bit mask of PIN11 field. */
#define SPU_GPIOPORT_PERM_PIN11_NonSecure (0x0UL) /*!< Pin 11 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN11_Secure (0x1UL) /*!< Pin 11 has its secure attribute set */

/* Bit 10 : Select secure attribute attribute for PIN 10. */
#define SPU_GPIOPORT_PERM_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
#define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos) /*!< Bit mask of PIN10 field. */
#define SPU_GPIOPORT_PERM_PIN10_NonSecure (0x0UL) /*!< Pin 10 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN10_Secure (0x1UL) /*!< Pin 10 has its secure attribute set */

/* Bit 9 : Select secure attribute attribute for PIN 9. */
#define SPU_GPIOPORT_PERM_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
#define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos) /*!< Bit mask of PIN9 field. */
#define SPU_GPIOPORT_PERM_PIN9_NonSecure (0x0UL) /*!< Pin 9 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN9_Secure (0x1UL) /*!< Pin 9 has its secure attribute set */

/* Bit 8 : Select secure attribute attribute for PIN 8. */
#define SPU_GPIOPORT_PERM_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
#define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos) /*!< Bit mask of PIN8 field. */
#define SPU_GPIOPORT_PERM_PIN8_NonSecure (0x0UL) /*!< Pin 8 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN8_Secure (0x1UL) /*!< Pin 8 has its secure attribute set */

/* Bit 7 : Select secure attribute attribute for PIN 7. */
#define SPU_GPIOPORT_PERM_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
#define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos) /*!< Bit mask of PIN7 field. */
#define SPU_GPIOPORT_PERM_PIN7_NonSecure (0x0UL) /*!< Pin 7 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN7_Secure (0x1UL) /*!< Pin 7 has its secure attribute set */

/* Bit 6 : Select secure attribute attribute for PIN 6. */
#define SPU_GPIOPORT_PERM_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
#define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos) /*!< Bit mask of PIN6 field. */
#define SPU_GPIOPORT_PERM_PIN6_NonSecure (0x0UL) /*!< Pin 6 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN6_Secure (0x1UL) /*!< Pin 6 has its secure attribute set */

/* Bit 5 : Select secure attribute attribute for PIN 5. */
#define SPU_GPIOPORT_PERM_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
#define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos) /*!< Bit mask of PIN5 field. */
#define SPU_GPIOPORT_PERM_PIN5_NonSecure (0x0UL) /*!< Pin 5 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN5_Secure (0x1UL) /*!< Pin 5 has its secure attribute set */

/* Bit 4 : Select secure attribute attribute for PIN 4. */
#define SPU_GPIOPORT_PERM_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
#define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos) /*!< Bit mask of PIN4 field. */
#define SPU_GPIOPORT_PERM_PIN4_NonSecure (0x0UL) /*!< Pin 4 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN4_Secure (0x1UL) /*!< Pin 4 has its secure attribute set */

/* Bit 3 : Select secure attribute attribute for PIN 3. */
#define SPU_GPIOPORT_PERM_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
#define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos) /*!< Bit mask of PIN3 field. */
#define SPU_GPIOPORT_PERM_PIN3_NonSecure (0x0UL) /*!< Pin 3 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN3_Secure (0x1UL) /*!< Pin 3 has its secure attribute set */

/* Bit 2 : Select secure attribute attribute for PIN 2. */
#define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
#define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos) /*!< Bit mask of PIN2 field. */
#define SPU_GPIOPORT_PERM_PIN2_NonSecure (0x0UL) /*!< Pin 2 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN2_Secure (0x1UL) /*!< Pin 2 has its secure attribute set */

/* Bit 1 : Select secure attribute attribute for PIN 1. */
#define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
#define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos) /*!< Bit mask of PIN1 field. */
#define SPU_GPIOPORT_PERM_PIN1_NonSecure (0x0UL) /*!< Pin 1 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN1_Secure (0x1UL) /*!< Pin 1 has its secure attribute set */

/* Bit 0 : Select secure attribute attribute for PIN 0. */
#define SPU_GPIOPORT_PERM_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
#define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos) /*!< Bit mask of PIN0 field. */
#define SPU_GPIOPORT_PERM_PIN0_NonSecure (0x0UL) /*!< Pin 0 has its non-secure attribute set */
#define SPU_GPIOPORT_PERM_PIN0_Secure (0x1UL) /*!< Pin 0 has its secure attribute set */

/* Register: SPU_GPIOPORT_LOCK */
/* Description: Description cluster: Prevent further modification of the corresponding PERM register */

/* Bit 0 :   */
#define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
#define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0x0UL) /*!< GPIOPORT[n].PERM register content can be changed */
#define SPU_GPIOPORT_LOCK_LOCK_Locked (0x1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */

/* Register: SPU_FLASHNSC_REGION */
/* Description: Description cluster: Define which flash region can contain the non-secure callable (NSC) region n */

/* Bit 8 :   */
#define SPU_FLASHNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
#define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define SPU_FLASHNSC_REGION_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
#define SPU_FLASHNSC_REGION_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */

/* Bits 5..0 : Region number */
#define SPU_FLASHNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
#define SPU_FLASHNSC_REGION_REGION_Msk (0x3FUL << SPU_FLASHNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */

/* Register: SPU_FLASHNSC_SIZE */
/* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */

/* Bit 8 :   */
#define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
#define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
#define SPU_FLASHNSC_SIZE_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */

/* Bits 3..0 : Size of the non-secure callable (NSC) region n */
#define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
#define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
#define SPU_FLASHNSC_SIZE_SIZE_Disabled (0x0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
#define SPU_FLASHNSC_SIZE_SIZE_32 (0x1UL) /*!< The region n is defined as non-secure callable with size 32 bytes */
#define SPU_FLASHNSC_SIZE_SIZE_64 (0x2UL) /*!< The region n is defined as non-secure callable with size 64 bytes */
#define SPU_FLASHNSC_SIZE_SIZE_128 (0x3UL) /*!< The region n is defined as non-secure callable with size 128 bytes */
#define SPU_FLASHNSC_SIZE_SIZE_256 (0x4UL) /*!< The region n is defined as non-secure callable with size 256 bytes */
#define SPU_FLASHNSC_SIZE_SIZE_512 (0x5UL) /*!< The region n is defined as non-secure callable with size 512 bytes */
#define SPU_FLASHNSC_SIZE_SIZE_1024 (0x6UL) /*!< The region n is defined as non-secure callable with size 1024 bytes */
#define SPU_FLASHNSC_SIZE_SIZE_2048 (0x7UL) /*!< The region n is defined as non-secure callable with size 2048 bytes */
#define SPU_FLASHNSC_SIZE_SIZE_4096 (0x8UL) /*!< The region n is defined as non-secure callable with size 4096 bytes */

/* Register: SPU_RAMNSC_REGION */
/* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */

/* Bit 8 :   */
#define SPU_RAMNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
#define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define SPU_RAMNSC_REGION_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
#define SPU_RAMNSC_REGION_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */

/* Bits 5..0 : Region number */
#define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
#define SPU_RAMNSC_REGION_REGION_Msk (0x3FUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */

/* Register: SPU_RAMNSC_SIZE */
/* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */

/* Bit 8 :   */
#define SPU_RAMNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
#define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define SPU_RAMNSC_SIZE_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
#define SPU_RAMNSC_SIZE_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */

/* Bits 3..0 : Size of the non-secure callable (NSC) region n */
#define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
#define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
#define SPU_RAMNSC_SIZE_SIZE_Disabled (0x0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
#define SPU_RAMNSC_SIZE_SIZE_32 (0x1UL) /*!< The region n is defined as non-secure callable with size 32 bytes */
#define SPU_RAMNSC_SIZE_SIZE_64 (0x2UL) /*!< The region n is defined as non-secure callable with size 64 bytes */
#define SPU_RAMNSC_SIZE_SIZE_128 (0x3UL) /*!< The region n is defined as non-secure callable with size 128 bytes */
#define SPU_RAMNSC_SIZE_SIZE_256 (0x4UL) /*!< The region n is defined as non-secure callable with size 256 bytes */
#define SPU_RAMNSC_SIZE_SIZE_512 (0x5UL) /*!< The region n is defined as non-secure callable with size 512 bytes */
#define SPU_RAMNSC_SIZE_SIZE_1024 (0x6UL) /*!< The region n is defined as non-secure callable with size 1024 bytes */
#define SPU_RAMNSC_SIZE_SIZE_2048 (0x7UL) /*!< The region n is defined as non-secure callable with size 2048 bytes */
#define SPU_RAMNSC_SIZE_SIZE_4096 (0x8UL) /*!< The region n is defined as non-secure callable with size 4096 bytes */

/* Register: SPU_FLASHREGION_PERM */
/* Description: Description cluster: Access permissions for flash region n */

/* Bit 8 :   */
#define SPU_FLASHREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
#define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define SPU_FLASHREGION_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
#define SPU_FLASHREGION_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */

/* Bit 4 : Security attribute for flash region n */
#define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
#define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
#define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0x0UL) /*!< Flash region n security attribute is non-secure */
#define SPU_FLASHREGION_PERM_SECATTR_Secure (0x1UL) /*!< Flash region n security attribute is secure */

/* Bit 2 : Configure read permissions for flash region n */
#define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
#define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
#define SPU_FLASHREGION_PERM_READ_Disable (0x0UL) /*!< Block read operation from flash region n */
#define SPU_FLASHREGION_PERM_READ_Enable (0x1UL) /*!< Allow read operation from flash region n */

/* Bit 1 : Configure write permission for flash region n */
#define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
#define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define SPU_FLASHREGION_PERM_WRITE_Disable (0x0UL) /*!< Block write operation to region n */
#define SPU_FLASHREGION_PERM_WRITE_Enable (0x1UL) /*!< Allow write operation to region n */

/* Bit 0 : Configure instruction fetch permissions from flash region n */
#define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
#define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
#define SPU_FLASHREGION_PERM_EXECUTE_Disable (0x0UL) /*!< Block instruction fetches from flash region n */
#define SPU_FLASHREGION_PERM_EXECUTE_Enable (0x1UL) /*!< Allow instruction fetches from flash region n */

/* Register: SPU_RAMREGION_PERM */
/* Description: Description cluster: Access permissions for RAM region n */

/* Bit 8 :   */
#define SPU_RAMREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
#define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define SPU_RAMREGION_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
#define SPU_RAMREGION_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */

/* Bit 4 : Security attribute for RAM region n */
#define SPU_RAMREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
#define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
#define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0x0UL) /*!< RAM region n security attribute is non-secure */
#define SPU_RAMREGION_PERM_SECATTR_Secure (0x1UL) /*!< RAM region n security attribute is secure */

/* Bit 2 : Configure read permissions for RAM region n */
#define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
#define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
#define SPU_RAMREGION_PERM_READ_Disable (0x0UL) /*!< Block read operation from RAM region n */
#define SPU_RAMREGION_PERM_READ_Enable (0x1UL) /*!< Allow read operation from RAM region n */

/* Bit 1 : Configure write permission for RAM region n */
#define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
#define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define SPU_RAMREGION_PERM_WRITE_Disable (0x0UL) /*!< Block write operation to RAM region n */
#define SPU_RAMREGION_PERM_WRITE_Enable (0x1UL) /*!< Allow write operation to RAM region n */

/* Bit 0 : Configure instruction fetch permissions from RAM region n */
#define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
#define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
#define SPU_RAMREGION_PERM_EXECUTE_Disable (0x0UL) /*!< Block instruction fetches from RAM region n */
#define SPU_RAMREGION_PERM_EXECUTE_Enable (0x1UL) /*!< Allow instruction fetches from RAM region n */

/* Register: SPU_PERIPHID_PERM */
/* Description: Description cluster: List capabilities and access permissions for the peripheral with ID n */

/* Bit 31 : Indicate if a peripheral is present with ID n */
#define SPU_PERIPHID_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */
#define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */
#define SPU_PERIPHID_PERM_PRESENT_NotPresent (0x0UL) /*!< Peripheral is not present */
#define SPU_PERIPHID_PERM_PRESENT_IsPresent (0x1UL) /*!< Peripheral is present */

/* Bit 8 :   */
#define SPU_PERIPHID_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
#define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
#define SPU_PERIPHID_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */
#define SPU_PERIPHID_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */

/* Bit 5 : Security attribution for the DMA transfer */
#define SPU_PERIPHID_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */
#define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */
#define SPU_PERIPHID_PERM_DMASEC_NonSecure (0x0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */
#define SPU_PERIPHID_PERM_DMASEC_Secure (0x1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */

/* Bit 4 : Peripheral security mapping */
#define SPU_PERIPHID_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
#define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
#define SPU_PERIPHID_PERM_SECATTR_NonSecure (0x0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */
#define SPU_PERIPHID_PERM_SECATTR_Secure (0x1UL) /*!< Peripheral is mapped in secure peripheral address space */

/* Bits 3..2 : Indicates if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */
#define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */
#define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */
#define SPU_PERIPHID_PERM_DMA_NoDMA (0x0UL) /*!< Peripheral has no DMA capability */
#define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (0x1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */
#define SPU_PERIPHID_PERM_DMA_SeparateAttribute (0x2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */

/* Bits 1..0 : Define configuration capabilities for Arm TrustZone Cortex-M secure attribute */
#define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
#define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
#define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< This peripheral is always accessible as a non-secure peripheral */
#define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (0x1UL) /*!< This peripheral is always accessible as a secure peripheral */
#define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */
#define SPU_PERIPHID_PERM_SECUREMAPPING_Split (0x3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */


/* Peripheral: TAD */
/* Description: Trace and debug control */

/* Register: TAD_CLOCKSTART */
/* Description: Start all trace and debug clocks. */

/* Bit 0 :   */
#define TAD_CLOCKSTART_START_Pos (0UL) /*!< Position of START field. */
#define TAD_CLOCKSTART_START_Msk (0x1UL << TAD_CLOCKSTART_START_Pos) /*!< Bit mask of START field. */
#define TAD_CLOCKSTART_START_Start (0x1UL) /*!< Start all trace and debug clocks. */

/* Register: TAD_CLOCKSTOP */
/* Description: Stop all trace and debug clocks. */

/* Bit 0 :   */
#define TAD_CLOCKSTOP_STOP_Pos (0UL) /*!< Position of STOP field. */
#define TAD_CLOCKSTOP_STOP_Msk (0x1UL << TAD_CLOCKSTOP_STOP_Pos) /*!< Bit mask of STOP field. */
#define TAD_CLOCKSTOP_STOP_Stop (0x1UL) /*!< Stop all trace and debug clocks. */

/* Register: TAD_ENABLE */
/* Description: Enable debug domain and aquire selected GPIOs */

/* Bit 0 :   */
#define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define TAD_ENABLE_ENABLE_DISABLED (0x0UL) /*!< Disable debug domain and release selected GPIOs */
#define TAD_ENABLE_ENABLE_ENABLED (0x1UL) /*!< Enable debug domain and aquire selected GPIOs */

/* Register: TAD_PSEL_TRACECLK */
/* Description: Pin configuration for TRACECLK */

/* Bit 31 : Connection */
#define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TAD_PSEL_TRACECLK_CONNECT_Connected (0x0UL) /*!< Connect */
#define TAD_PSEL_TRACECLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bits 4..0 : Pin number */
#define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */
#define TAD_PSEL_TRACECLK_PIN_Traceclk (0x0CUL) /*!< TRACECLK pin */

/* Register: TAD_PSEL_TRACEDATA0 */
/* Description: Pin configuration for TRACEDATA[0] */

/* Bit 31 : Connection */
#define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0x0UL) /*!< Connect */
#define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bits 4..0 : Pin number */
#define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */
#define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (0x0BUL) /*!< TRACEDATA0 pin */

/* Register: TAD_PSEL_TRACEDATA1 */
/* Description: Pin configuration for TRACEDATA[1] */

/* Bit 31 : Connection */
#define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0x0UL) /*!< Connect */
#define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bits 4..0 : Pin number */
#define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */
#define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (0x0AUL) /*!< TRACEDATA1 pin */

/* Register: TAD_PSEL_TRACEDATA2 */
/* Description: Pin configuration for TRACEDATA[2] */

/* Bit 31 : Connection */
#define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0x0UL) /*!< Connect */
#define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bits 4..0 : Pin number */
#define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */
#define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (0x09UL) /*!< TRACEDATA2 pin */

/* Register: TAD_PSEL_TRACEDATA3 */
/* Description: Pin configuration for TRACEDATA[3] */

/* Bit 31 : Connection */
#define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0x0UL) /*!< Connect */
#define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bits 4..0 : Pin number */
#define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */
#define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (0x08UL) /*!< TRACEDATA3 pin */

/* Register: TAD_TRACEPORTSPEED */
/* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */

/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */
#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_64MHz (0x0UL) /*!< Trace Port clock is: 64MHz */
#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0x1UL) /*!< Trace Port clock is: 32MHz */
#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (0x2UL) /*!< Trace Port clock is: 16MHz */
#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (0x3UL) /*!< Trace Port clock is: 8MHz */


/* Peripheral: TIMER */
/* Description: Timer/Counter 0 */

/* Register: TIMER_TASKS_START */
/* Description: Start Timer */

/* Bit 0 : Start Timer */
#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define TIMER_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */

/* Register: TIMER_TASKS_STOP */
/* Description: Stop Timer */

/* Bit 0 : Stop Timer */
#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: TIMER_TASKS_COUNT */
/* Description: Increment Timer (Counter mode only) */

/* Bit 0 : Increment Timer (Counter mode only) */
#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (0x1UL) /*!< Trigger task */

/* Register: TIMER_TASKS_CLEAR */
/* Description: Clear time */

/* Bit 0 : Clear time */
#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */

/* Register: TIMER_TASKS_SHUTDOWN */
/* Description: Deprecated register - Shut down timer */

/* Bit 0 : Deprecated field -  Shut down timer */
#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (0x1UL) /*!< Trigger task */

/* Register: TIMER_TASKS_CAPTURE */
/* Description: Description collection: Capture Timer value to CC[n] register */

/* Bit 0 : Capture Timer value to CC[n] register */
#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */

/* Register: TIMER_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */

/* Bit 31 :   */
#define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define TIMER_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TIMER_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define TIMER_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TIMER_SUBSCRIBE_COUNT */
/* Description: Subscribe configuration for task COUNT */

/* Bit 31 :   */
#define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */
#define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */
#define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_COUNT_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task COUNT will subscribe to */
#define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TIMER_SUBSCRIBE_CLEAR */
/* Description: Subscribe configuration for task CLEAR */

/* Bit 31 :   */
#define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
#define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
#define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TIMER_SUBSCRIBE_SHUTDOWN */
/* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */

/* Bit 31 :   */
#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */
#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */
#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */
#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TIMER_SUBSCRIBE_CAPTURE */
/* Description: Description collection: Subscribe configuration for task CAPTURE[n] */

/* Bit 31 :   */
#define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
#define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
#define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TIMER_EVENTS_COMPARE */
/* Description: Description collection: Compare event on CC[n] match */

/* Bit 0 : Compare event on CC[n] match */
#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */
#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */

/* Register: TIMER_PUBLISH_COMPARE */
/* Description: Description collection: Publish configuration for event COMPARE[n] */

/* Bit 31 :   */
#define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
#define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
#define TIMER_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TIMER_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */
#define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TIMER_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 21 : Shortcut between event COMPARE[5] and task STOP */
#define TIMER_SHORTS_COMPARE5_STOP_Pos (21UL) /*!< Position of COMPARE5_STOP field. */
#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE5_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 20 : Shortcut between event COMPARE[4] and task STOP */
#define TIMER_SHORTS_COMPARE4_STOP_Pos (20UL) /*!< Position of COMPARE4_STOP field. */
#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE4_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 19 : Shortcut between event COMPARE[3] and task STOP */
#define TIMER_SHORTS_COMPARE3_STOP_Pos (19UL) /*!< Position of COMPARE3_STOP field. */
#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE3_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 18 : Shortcut between event COMPARE[2] and task STOP */
#define TIMER_SHORTS_COMPARE2_STOP_Pos (18UL) /*!< Position of COMPARE2_STOP field. */
#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE2_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 17 : Shortcut between event COMPARE[1] and task STOP */
#define TIMER_SHORTS_COMPARE1_STOP_Pos (17UL) /*!< Position of COMPARE1_STOP field. */
#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE1_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 16 : Shortcut between event COMPARE[0] and task STOP */
#define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL) /*!< Position of COMPARE0_STOP field. */
#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE0_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */
#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: TIMER_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 21 : Enable or disable interrupt for event COMPARE[5] */
#define TIMER_INTEN_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
#define TIMER_INTEN_COMPARE5_Msk (0x1UL << TIMER_INTEN_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
#define TIMER_INTEN_COMPARE5_Disabled (0x0UL) /*!< Disable */
#define TIMER_INTEN_COMPARE5_Enabled (0x1UL) /*!< Enable */

/* Bit 20 : Enable or disable interrupt for event COMPARE[4] */
#define TIMER_INTEN_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
#define TIMER_INTEN_COMPARE4_Msk (0x1UL << TIMER_INTEN_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
#define TIMER_INTEN_COMPARE4_Disabled (0x0UL) /*!< Disable */
#define TIMER_INTEN_COMPARE4_Enabled (0x1UL) /*!< Enable */

/* Bit 19 : Enable or disable interrupt for event COMPARE[3] */
#define TIMER_INTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define TIMER_INTEN_COMPARE3_Msk (0x1UL << TIMER_INTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define TIMER_INTEN_COMPARE3_Disabled (0x0UL) /*!< Disable */
#define TIMER_INTEN_COMPARE3_Enabled (0x1UL) /*!< Enable */

/* Bit 18 : Enable or disable interrupt for event COMPARE[2] */
#define TIMER_INTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define TIMER_INTEN_COMPARE2_Msk (0x1UL << TIMER_INTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define TIMER_INTEN_COMPARE2_Disabled (0x0UL) /*!< Disable */
#define TIMER_INTEN_COMPARE2_Enabled (0x1UL) /*!< Enable */

/* Bit 17 : Enable or disable interrupt for event COMPARE[1] */
#define TIMER_INTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define TIMER_INTEN_COMPARE1_Msk (0x1UL << TIMER_INTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define TIMER_INTEN_COMPARE1_Disabled (0x0UL) /*!< Disable */
#define TIMER_INTEN_COMPARE1_Enabled (0x1UL) /*!< Enable */

/* Bit 16 : Enable or disable interrupt for event COMPARE[0] */
#define TIMER_INTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define TIMER_INTEN_COMPARE0_Disabled (0x0UL) /*!< Disable */
#define TIMER_INTEN_COMPARE0_Enabled (0x1UL) /*!< Enable */

/* Register: TIMER_INTENSET */
/* Description: Enable interrupt */

/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
#define TIMER_INTENSET_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE5_Set (0x1UL) /*!< Enable */

/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
#define TIMER_INTENSET_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE4_Set (0x1UL) /*!< Enable */

/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define TIMER_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */

/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define TIMER_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */

/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define TIMER_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */

/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define TIMER_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */

/* Register: TIMER_INTENCLR */
/* Description: Disable interrupt */

/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
#define TIMER_INTENCLR_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE5_Clear (0x1UL) /*!< Disable */

/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
#define TIMER_INTENCLR_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE4_Clear (0x1UL) /*!< Disable */

/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
#define TIMER_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */

/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
#define TIMER_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */

/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
#define TIMER_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */

/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
#define TIMER_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */
#define TIMER_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */

/* Register: TIMER_MODE */
/* Description: Timer mode selection */

/* Bits 1..0 : Timer mode */
#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define TIMER_MODE_MODE_Timer (0x0UL) /*!< Select Timer mode */
#define TIMER_MODE_MODE_Counter (0x1UL) /*!< Deprecated enumerator -  Select Counter mode */
#define TIMER_MODE_MODE_LowPowerCounter (0x2UL) /*!< Select Low Power Counter mode */

/* Register: TIMER_BITMODE */
/* Description: Configure the number of bits used by the TIMER */

/* Bits 1..0 : Timer bit width */
#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
#define TIMER_BITMODE_BITMODE_16Bit (0x0UL) /*!< 16 bit timer bit width */
#define TIMER_BITMODE_BITMODE_08Bit (0x1UL) /*!< 8 bit timer bit width */
#define TIMER_BITMODE_BITMODE_24Bit (0x2UL) /*!< 24 bit timer bit width */
#define TIMER_BITMODE_BITMODE_32Bit (0x3UL) /*!< 32 bit timer bit width */

/* Register: TIMER_PRESCALER */
/* Description: Timer prescaler register */

/* Bits 3..0 : Prescaler value */
#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */

/* Register: TIMER_CC */
/* Description: Description collection: Capture/Compare register n */

/* Bits 31..0 : Capture/Compare value */
#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */

/* Register: TIMER_ONESHOTEN */
/* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */

/* Bit 0 : Enable one-shot operation */
#define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */
#define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */
#define TIMER_ONESHOTEN_ONESHOTEN_Disable (0x0UL) /*!< Disable one-shot operation */
#define TIMER_ONESHOTEN_ONESHOTEN_Enable (0x1UL) /*!< Enable one-shot operation */


/* Peripheral: TWIM */
/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */

/* Register: TWIM_TASKS_STARTRX */
/* Description: Start TWI receive sequence */

/* Bit 0 : Start TWI receive sequence */
#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */

/* Register: TWIM_TASKS_STARTTX */
/* Description: Start TWI transmit sequence */

/* Bit 0 : Start TWI transmit sequence */
#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */

/* Register: TWIM_TASKS_STOP */
/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */

/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: TWIM_TASKS_SUSPEND */
/* Description: Suspend TWI transaction */

/* Bit 0 : Suspend TWI transaction */
#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */

/* Register: TWIM_TASKS_RESUME */
/* Description: Resume TWI transaction */

/* Bit 0 : Resume TWI transaction */
#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */

/* Register: TWIM_SUBSCRIBE_STARTRX */
/* Description: Subscribe configuration for task STARTRX */

/* Bit 31 :   */
#define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_SUBSCRIBE_STARTTX */
/* Description: Subscribe configuration for task STARTTX */

/* Bit 31 :   */
#define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TWIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_SUBSCRIBE_SUSPEND */
/* Description: Subscribe configuration for task SUSPEND */

/* Bit 31 :   */
#define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_SUBSCRIBE_RESUME */
/* Description: Subscribe configuration for task RESUME */

/* Bit 31 :   */
#define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TWIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
#define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_EVENTS_STOPPED */
/* Description: TWI stopped */

/* Bit 0 : TWI stopped */
#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */

/* Register: TWIM_EVENTS_ERROR */
/* Description: TWI error */

/* Bit 0 : TWI error */
#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */

/* Register: TWIM_EVENTS_SUSPENDED */
/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */

/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (0x1UL) /*!< Event generated */

/* Register: TWIM_EVENTS_RXSTARTED */
/* Description: Receive sequence started */

/* Bit 0 : Receive sequence started */
#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: TWIM_EVENTS_TXSTARTED */
/* Description: Transmit sequence started */

/* Bit 0 : Transmit sequence started */
#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: TWIM_EVENTS_LASTRX */
/* Description: Byte boundary, starting to receive the last byte */

/* Bit 0 : Byte boundary, starting to receive the last byte */
#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (0x1UL) /*!< Event generated */

/* Register: TWIM_EVENTS_LASTTX */
/* Description: Byte boundary, starting to transmit the last byte */

/* Bit 0 : Byte boundary, starting to transmit the last byte */
#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (0x1UL) /*!< Event generated */

/* Register: TWIM_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */

/* Bit 31 :   */
#define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_PUBLISH_ERROR */
/* Description: Publish configuration for event ERROR */

/* Bit 31 :   */
#define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ERROR will publish to */
#define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_PUBLISH_SUSPENDED */
/* Description: Publish configuration for event SUSPENDED */

/* Bit 31 :   */
#define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_SUSPENDED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event SUSPENDED will publish to */
#define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_PUBLISH_RXSTARTED */
/* Description: Publish configuration for event RXSTARTED */

/* Bit 31 :   */
#define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
#define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_PUBLISH_TXSTARTED */
/* Description: Publish configuration for event TXSTARTED */

/* Bit 31 :   */
#define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
#define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_PUBLISH_LASTRX */
/* Description: Publish configuration for event LASTRX */

/* Bit 31 :   */
#define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_PUBLISH_LASTRX_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_LASTRX_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event LASTRX will publish to */
#define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_PUBLISH_LASTTX */
/* Description: Publish configuration for event LASTTX */

/* Bit 31 :   */
#define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */
#define TWIM_PUBLISH_LASTTX_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIM_PUBLISH_LASTTX_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event LASTTX will publish to */
#define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIM_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 12 : Shortcut between event LASTRX and task STOP */
#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
#define TWIM_SHORTS_LASTRX_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTRX_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 10 : Shortcut between event LASTRX and task STARTTX */
#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0x0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 9 : Shortcut between event LASTTX and task STOP */
#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
#define TWIM_SHORTS_LASTTX_STOP_Disabled (0x0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_STOP_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 7 : Shortcut between event LASTTX and task STARTRX */
#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */
#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: TWIM_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 24 : Enable or disable interrupt for event LASTTX */
#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTEN_LASTTX_Disabled (0x0UL) /*!< Disable */
#define TWIM_INTEN_LASTTX_Enabled (0x1UL) /*!< Enable */

/* Bit 23 : Enable or disable interrupt for event LASTRX */
#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTEN_LASTRX_Disabled (0x0UL) /*!< Disable */
#define TWIM_INTEN_LASTRX_Enabled (0x1UL) /*!< Enable */

/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */
#define TWIM_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */
#define TWIM_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 18 : Enable or disable interrupt for event SUSPENDED */
#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWIM_INTEN_SUSPENDED_Disabled (0x0UL) /*!< Disable */
#define TWIM_INTEN_SUSPENDED_Enabled (0x1UL) /*!< Enable */

/* Bit 9 : Enable or disable interrupt for event ERROR */
#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
#define TWIM_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event STOPPED */
#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
#define TWIM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */

/* Register: TWIM_INTENSET */
/* Description: Enable interrupt */

/* Bit 24 : Write '1' to enable interrupt for event LASTTX */
#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTENSET_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_LASTTX_Set (0x1UL) /*!< Enable */

/* Bit 23 : Write '1' to enable interrupt for event LASTRX */
#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTENSET_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_LASTRX_Set (0x1UL) /*!< Enable */

/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */

/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */

/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWIM_INTENSET_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_SUSPENDED_Set (0x1UL) /*!< Enable */

/* Bit 9 : Write '1' to enable interrupt for event ERROR */
#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_ERROR_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */

/* Register: TWIM_INTENCLR */
/* Description: Disable interrupt */

/* Bit 24 : Write '1' to disable interrupt for event LASTTX */
#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
#define TWIM_INTENCLR_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_LASTTX_Clear (0x1UL) /*!< Disable */

/* Bit 23 : Write '1' to disable interrupt for event LASTRX */
#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
#define TWIM_INTENCLR_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_LASTRX_Clear (0x1UL) /*!< Disable */

/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIM_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */

/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIM_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */

/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
#define TWIM_INTENCLR_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_SUSPENDED_Clear (0x1UL) /*!< Disable */

/* Bit 9 : Write '1' to disable interrupt for event ERROR */
#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIM_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */

/* Register: TWIM_ERRORSRC */
/* Description: Error source */

/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
#define TWIM_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */
#define TWIM_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */

/* Bit 1 : NACK received after sending the address (write '1' to clear) */
#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
#define TWIM_ERRORSRC_ANACK_NotReceived (0x0UL) /*!< Error did not occur */
#define TWIM_ERRORSRC_ANACK_Received (0x1UL) /*!< Error occurred */

/* Bit 0 : Overrun error */
#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define TWIM_ERRORSRC_OVERRUN_NotReceived (0x0UL) /*!< Error did not occur */
#define TWIM_ERRORSRC_OVERRUN_Received (0x1UL) /*!< Error occurred */

/* Register: TWIM_ENABLE */
/* Description: Enable TWIM */

/* Bits 3..0 : Enable or disable TWIM */
#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define TWIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIM */
#define TWIM_ENABLE_ENABLE_Enabled (0x6UL) /*!< Enable TWIM */

/* Register: TWIM_PSEL_SCL */
/* Description: Pin select for SCL signal */

/* Bit 31 : Connection */
#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIM_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */
#define TWIM_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
#define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: TWIM_PSEL_SDA */
/* Description: Pin select for SDA signal */

/* Bit 31 : Connection */
#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIM_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */
#define TWIM_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
#define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: TWIM_FREQUENCY */
/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */

/* Bits 31..0 : TWI master clock frequency */
#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
#define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL) /*!< 1000 kbps */

/* Register: TWIM_RXD_PTR */
/* Description: Data pointer */

/* Bits 31..0 : Data pointer */
#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: TWIM_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */

/* Bits 15..0 : Maximum number of bytes in receive buffer */
#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: TWIM_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */

/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: TWIM_RXD_LIST */
/* Description: EasyDMA list type */

/* Bits 2..0 : List type */
#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define TWIM_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
#define TWIM_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */

/* Register: TWIM_TXD_PTR */
/* Description: Data pointer */

/* Bits 31..0 : Data pointer */
#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: TWIM_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */

/* Bits 15..0 : Maximum number of bytes in transmit buffer */
#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: TWIM_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */

/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: TWIM_TXD_LIST */
/* Description: EasyDMA list type */

/* Bits 2..0 : List type */
#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define TWIM_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
#define TWIM_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */

/* Register: TWIM_ADDRESS */
/* Description: Address used in the TWI transfer */

/* Bits 6..0 : Address used in the TWI transfer */
#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */


/* Peripheral: TWIS */
/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */

/* Register: TWIS_TASKS_STOP */
/* Description: Stop TWI transaction */

/* Bit 0 : Stop TWI transaction */
#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: TWIS_TASKS_SUSPEND */
/* Description: Suspend TWI transaction */

/* Bit 0 : Suspend TWI transaction */
#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */

/* Register: TWIS_TASKS_RESUME */
/* Description: Resume TWI transaction */

/* Bit 0 : Resume TWI transaction */
#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */

/* Register: TWIS_TASKS_PREPARERX */
/* Description: Prepare the TWI slave to respond to a write command */

/* Bit 0 : Prepare the TWI slave to respond to a write command */
#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (0x1UL) /*!< Trigger task */

/* Register: TWIS_TASKS_PREPARETX */
/* Description: Prepare the TWI slave to respond to a read command */

/* Bit 0 : Prepare the TWI slave to respond to a read command */
#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (0x1UL) /*!< Trigger task */

/* Register: TWIS_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TWIS_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_SUBSCRIBE_SUSPEND */
/* Description: Subscribe configuration for task SUSPEND */

/* Bit 31 :   */
#define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_SUBSCRIBE_RESUME */
/* Description: Subscribe configuration for task RESUME */

/* Bit 31 :   */
#define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TWIS_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
#define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_SUBSCRIBE_PREPARERX */
/* Description: Subscribe configuration for task PREPARERX */

/* Bit 31 :   */
#define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */
#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_SUBSCRIBE_PREPARETX */
/* Description: Subscribe configuration for task PREPARETX */

/* Bit 31 :   */
#define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0x0UL) /*!< Disable subscription */
#define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */
#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_EVENTS_STOPPED */
/* Description: TWI stopped */

/* Bit 0 : TWI stopped */
#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */

/* Register: TWIS_EVENTS_ERROR */
/* Description: TWI error */

/* Bit 0 : TWI error */
#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */

/* Register: TWIS_EVENTS_RXSTARTED */
/* Description: Receive sequence started */

/* Bit 0 : Receive sequence started */
#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: TWIS_EVENTS_TXSTARTED */
/* Description: Transmit sequence started */

/* Bit 0 : Transmit sequence started */
#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: TWIS_EVENTS_WRITE */
/* Description: Write command received */

/* Bit 0 : Write command received */
#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (0x1UL) /*!< Event generated */

/* Register: TWIS_EVENTS_READ */
/* Description: Read command received */

/* Bit 0 : Read command received */
#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0x0UL) /*!< Event not generated */
#define TWIS_EVENTS_READ_EVENTS_READ_Generated (0x1UL) /*!< Event generated */

/* Register: TWIS_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */

/* Bit 31 :   */
#define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_PUBLISH_ERROR */
/* Description: Publish configuration for event ERROR */

/* Bit 31 :   */
#define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ERROR will publish to */
#define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_PUBLISH_RXSTARTED */
/* Description: Publish configuration for event RXSTARTED */

/* Bit 31 :   */
#define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
#define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_PUBLISH_TXSTARTED */
/* Description: Publish configuration for event TXSTARTED */

/* Bit 31 :   */
#define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
#define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_PUBLISH_WRITE */
/* Description: Publish configuration for event WRITE */

/* Bit 31 :   */
#define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_PUBLISH_WRITE_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_WRITE_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event WRITE will publish to */
#define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_PUBLISH_READ */
/* Description: Publish configuration for event READ */

/* Bit 31 :   */
#define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */
#define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */
#define TWIS_PUBLISH_READ_EN_Disabled (0x0UL) /*!< Disable publishing */
#define TWIS_PUBLISH_READ_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event READ will publish to */
#define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: TWIS_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 14 : Shortcut between event READ and task SUSPEND */
#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
#define TWIS_SHORTS_READ_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
#define TWIS_SHORTS_READ_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 13 : Shortcut between event WRITE and task SUSPEND */
#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */
#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: TWIS_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 26 : Enable or disable interrupt for event READ */
#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTEN_READ_Disabled (0x0UL) /*!< Disable */
#define TWIS_INTEN_READ_Enabled (0x1UL) /*!< Enable */

/* Bit 25 : Enable or disable interrupt for event WRITE */
#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTEN_WRITE_Disabled (0x0UL) /*!< Disable */
#define TWIS_INTEN_WRITE_Enabled (0x1UL) /*!< Enable */

/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */
#define TWIS_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */
#define TWIS_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 9 : Enable or disable interrupt for event ERROR */
#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
#define TWIS_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event STOPPED */
#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */
#define TWIS_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */

/* Register: TWIS_INTENSET */
/* Description: Enable interrupt */

/* Bit 26 : Write '1' to enable interrupt for event READ */
#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTENSET_READ_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_READ_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_READ_Set (0x1UL) /*!< Enable */

/* Bit 25 : Write '1' to enable interrupt for event WRITE */
#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTENSET_WRITE_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_WRITE_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_WRITE_Set (0x1UL) /*!< Enable */

/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */

/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */

/* Bit 9 : Write '1' to enable interrupt for event ERROR */
#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_ERROR_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */

/* Register: TWIS_INTENCLR */
/* Description: Disable interrupt */

/* Bit 26 : Write '1' to disable interrupt for event READ */
#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
#define TWIS_INTENCLR_READ_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_READ_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_READ_Clear (0x1UL) /*!< Disable */

/* Bit 25 : Write '1' to disable interrupt for event WRITE */
#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define TWIS_INTENCLR_WRITE_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_WRITE_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_WRITE_Clear (0x1UL) /*!< Disable */

/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define TWIS_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */

/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define TWIS_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */

/* Bit 9 : Write '1' to disable interrupt for event ERROR */
#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define TWIS_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define TWIS_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define TWIS_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define TWIS_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */

/* Register: TWIS_ERRORSRC */
/* Description: Error source */

/* Bit 3 : TX buffer over-read detected, and prevented */
#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
#define TWIS_ERRORSRC_OVERREAD_NotDetected (0x0UL) /*!< Error did not occur */
#define TWIS_ERRORSRC_OVERREAD_Detected (0x1UL) /*!< Error occurred */

/* Bit 2 : NACK sent after receiving a data byte */
#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
#define TWIS_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */
#define TWIS_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */

/* Bit 0 : RX buffer overflow detected, and prevented */
#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0x0UL) /*!< Error did not occur */
#define TWIS_ERRORSRC_OVERFLOW_Detected (0x1UL) /*!< Error occurred */

/* Register: TWIS_MATCH */
/* Description: Status register indicating which address had a match */

/* Bit 0 : Indication of which address in ADDRESS that matched the incoming address */
#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */

/* Register: TWIS_ENABLE */
/* Description: Enable TWIS */

/* Bits 3..0 : Enable or disable TWIS */
#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define TWIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIS */
#define TWIS_ENABLE_ENABLE_Enabled (0x9UL) /*!< Enable TWIS */

/* Register: TWIS_PSEL_SCL */
/* Description: Pin select for SCL signal */

/* Bit 31 : Connection */
#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIS_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */
#define TWIS_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
#define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: TWIS_PSEL_SDA */
/* Description: Pin select for SDA signal */

/* Bit 31 : Connection */
#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define TWIS_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */
#define TWIS_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
#define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: TWIS_RXD_PTR */
/* Description: RXD Data pointer */

/* Bits 31..0 : RXD Data pointer */
#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: TWIS_RXD_MAXCNT */
/* Description: Maximum number of bytes in RXD buffer */

/* Bits 15..0 : Maximum number of bytes in RXD buffer */
#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: TWIS_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last RXD transaction */

/* Bits 15..0 : Number of bytes transferred in the last RXD transaction */
#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: TWIS_RXD_LIST */
/* Description: EasyDMA list type */

/* Bits 1..0 : List type */
#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define TWIS_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
#define TWIS_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */

/* Register: TWIS_TXD_PTR */
/* Description: TXD Data pointer */

/* Bits 31..0 : TXD Data pointer */
#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: TWIS_TXD_MAXCNT */
/* Description: Maximum number of bytes in TXD buffer */

/* Bits 15..0 : Maximum number of bytes in TXD buffer */
#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: TWIS_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last TXD transaction */

/* Bits 15..0 : Number of bytes transferred in the last TXD transaction */
#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: TWIS_TXD_LIST */
/* Description: EasyDMA list type */

/* Bits 1..0 : List type */
#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
#define TWIS_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */
#define TWIS_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */

/* Register: TWIS_ADDRESS */
/* Description: Description collection: TWI slave address n */

/* Bits 6..0 : TWI slave address */
#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */

/* Register: TWIS_CONFIG */
/* Description: Configuration register for the address match mechanism */

/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
#define TWIS_CONFIG_ADDRESS1_Disabled (0x0UL) /*!< Disabled */
#define TWIS_CONFIG_ADDRESS1_Enabled (0x1UL) /*!< Enabled */

/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
#define TWIS_CONFIG_ADDRESS0_Disabled (0x0UL) /*!< Disabled */
#define TWIS_CONFIG_ADDRESS0_Enabled (0x1UL) /*!< Enabled */

/* Register: TWIS_ORC */
/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */

/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */


/* Peripheral: UARTE */
/* Description: UART with EasyDMA 0 */

/* Register: UARTE_TASKS_STARTRX */
/* Description: Start UART receiver */

/* Bit 0 : Start UART receiver */
#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */

/* Register: UARTE_TASKS_STOPRX */
/* Description: Stop UART receiver */

/* Bit 0 : Stop UART receiver */
#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (0x1UL) /*!< Trigger task */

/* Register: UARTE_TASKS_STARTTX */
/* Description: Start UART transmitter */

/* Bit 0 : Start UART transmitter */
#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */

/* Register: UARTE_TASKS_STOPTX */
/* Description: Stop UART transmitter */

/* Bit 0 : Stop UART transmitter */
#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (0x1UL) /*!< Trigger task */

/* Register: UARTE_TASKS_FLUSHRX */
/* Description: Flush RX FIFO into RX buffer */

/* Bit 0 : Flush RX FIFO into RX buffer */
#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (0x1UL) /*!< Trigger task */

/* Register: UARTE_SUBSCRIBE_STARTRX */
/* Description: Subscribe configuration for task STARTRX */

/* Bit 31 :   */
#define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0x0UL) /*!< Disable subscription */
#define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_SUBSCRIBE_STOPRX */
/* Description: Subscribe configuration for task STOPRX */

/* Bit 31 :   */
#define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0x0UL) /*!< Disable subscription */
#define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */
#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_SUBSCRIBE_STARTTX */
/* Description: Subscribe configuration for task STARTTX */

/* Bit 31 :   */
#define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription */
#define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_SUBSCRIBE_STOPTX */
/* Description: Subscribe configuration for task STOPTX */

/* Bit 31 :   */
#define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0x0UL) /*!< Disable subscription */
#define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */
#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_SUBSCRIBE_FLUSHRX */
/* Description: Subscribe configuration for task FLUSHRX */

/* Bit 31 :   */
#define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0x0UL) /*!< Disable subscription */
#define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */
#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_EVENTS_CTS */
/* Description: CTS is activated (set low). Clear To Send. */

/* Bit 0 : CTS is activated (set low). Clear To Send. */
#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_EVENTS_NCTS */
/* Description: CTS is deactivated (set high). Not Clear To Send. */

/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_EVENTS_RXDRDY */
/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */

/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_EVENTS_ENDRX */
/* Description: Receive buffer is filled up */

/* Bit 0 : Receive buffer is filled up */
#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_EVENTS_TXDRDY */
/* Description: Data sent from TXD */

/* Bit 0 : Data sent from TXD */
#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_EVENTS_ENDTX */
/* Description: Last TX byte transmitted */

/* Bit 0 : Last TX byte transmitted */
#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_EVENTS_ERROR */
/* Description: Error detected */

/* Bit 0 : Error detected */
#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_EVENTS_RXTO */
/* Description: Receiver timeout */

/* Bit 0 : Receiver timeout */
#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_EVENTS_RXSTARTED */
/* Description: UART receiver has started */

/* Bit 0 : UART receiver has started */
#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_EVENTS_TXSTARTED */
/* Description: UART transmitter has started */

/* Bit 0 : UART transmitter has started */
#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_EVENTS_TXSTOPPED */
/* Description: Transmitter stopped */

/* Bit 0 : Transmitter stopped */
#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */
#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (0x1UL) /*!< Event generated */

/* Register: UARTE_PUBLISH_CTS */
/* Description: Publish configuration for event CTS */

/* Bit 31 :   */
#define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_CTS_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_CTS_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event CTS will publish to */
#define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_PUBLISH_NCTS */
/* Description: Publish configuration for event NCTS */

/* Bit 31 :   */
#define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_NCTS_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_NCTS_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event NCTS will publish to */
#define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_PUBLISH_RXDRDY */
/* Description: Publish configuration for event RXDRDY */

/* Bit 31 :   */
#define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_RXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_RXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RXDRDY will publish to */
#define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_PUBLISH_ENDRX */
/* Description: Publish configuration for event ENDRX */

/* Bit 31 :   */
#define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDRX will publish to */
#define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_PUBLISH_TXDRDY */
/* Description: Publish configuration for event TXDRDY */

/* Bit 31 :   */
#define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_TXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_TXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TXDRDY will publish to */
#define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_PUBLISH_ENDTX */
/* Description: Publish configuration for event ENDTX */

/* Bit 31 :   */
#define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_ENDTX_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_ENDTX_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDTX will publish to */
#define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_PUBLISH_ERROR */
/* Description: Publish configuration for event ERROR */

/* Bit 31 :   */
#define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ERROR will publish to */
#define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_PUBLISH_RXTO */
/* Description: Publish configuration for event RXTO */

/* Bit 31 :   */
#define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_RXTO_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_RXTO_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RXTO will publish to */
#define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_PUBLISH_RXSTARTED */
/* Description: Publish configuration for event RXSTARTED */

/* Bit 31 :   */
#define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */
#define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_PUBLISH_TXSTARTED */
/* Description: Publish configuration for event TXSTARTED */

/* Bit 31 :   */
#define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */
#define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_PUBLISH_TXSTOPPED */
/* Description: Publish configuration for event TXSTOPPED */

/* Bit 31 :   */
#define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
#define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */
#define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to */
#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: UARTE_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 6 : Shortcut between event ENDRX and task STOPRX */
#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0x0UL) /*!< Disable shortcut */
#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 5 : Shortcut between event ENDRX and task STARTRX */
#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */
#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: UARTE_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTEN_TXSTOPPED_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_TXSTOPPED_Enabled (0x1UL) /*!< Enable */

/* Bit 20 : Enable or disable interrupt for event TXSTARTED */
#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 19 : Enable or disable interrupt for event RXSTARTED */
#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 17 : Enable or disable interrupt for event RXTO */
#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTEN_RXTO_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_RXTO_Enabled (0x1UL) /*!< Enable */

/* Bit 9 : Enable or disable interrupt for event ERROR */
#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */

/* Bit 8 : Enable or disable interrupt for event ENDTX */
#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTEN_ENDTX_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_ENDTX_Enabled (0x1UL) /*!< Enable */

/* Bit 7 : Enable or disable interrupt for event TXDRDY */
#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UARTE_INTEN_TXDRDY_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_TXDRDY_Enabled (0x1UL) /*!< Enable */

/* Bit 4 : Enable or disable interrupt for event ENDRX */
#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTEN_ENDRX_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_ENDRX_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event RXDRDY */
#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UARTE_INTEN_RXDRDY_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_RXDRDY_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event NCTS */
#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTEN_NCTS_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_NCTS_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event CTS */
#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTEN_CTS_Disabled (0x0UL) /*!< Disable */
#define UARTE_INTEN_CTS_Enabled (0x1UL) /*!< Enable */

/* Register: UARTE_INTENSET */
/* Description: Enable interrupt */

/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTENSET_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXSTOPPED_Set (0x1UL) /*!< Enable */

/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */

/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */

/* Bit 17 : Write '1' to enable interrupt for event RXTO */
#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTENSET_RXTO_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXTO_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXTO_Set (0x1UL) /*!< Enable */

/* Bit 9 : Write '1' to enable interrupt for event ERROR */
#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ERROR_Set (0x1UL) /*!< Enable */

/* Bit 8 : Write '1' to enable interrupt for event ENDTX */
#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */

/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UARTE_INTENSET_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_TXDRDY_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event ENDRX */
#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UARTE_INTENSET_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_RXDRDY_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event NCTS */
#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTENSET_NCTS_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_NCTS_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_NCTS_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event CTS */
#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTENSET_CTS_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENSET_CTS_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENSET_CTS_Set (0x1UL) /*!< Enable */

/* Register: UARTE_INTENCLR */
/* Description: Disable interrupt */

/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
#define UARTE_INTENCLR_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXSTOPPED_Clear (0x1UL) /*!< Disable */

/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
#define UARTE_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */

/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
#define UARTE_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */

/* Bit 17 : Write '1' to disable interrupt for event RXTO */
#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
#define UARTE_INTENCLR_RXTO_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXTO_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXTO_Clear (0x1UL) /*!< Disable */

/* Bit 9 : Write '1' to disable interrupt for event ERROR */
#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
#define UARTE_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */

/* Bit 8 : Write '1' to disable interrupt for event ENDTX */
#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
#define UARTE_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */

/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
#define UARTE_INTENCLR_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_TXDRDY_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event ENDRX */
#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define UARTE_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
#define UARTE_INTENCLR_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_RXDRDY_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event NCTS */
#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
#define UARTE_INTENCLR_NCTS_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_NCTS_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_NCTS_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event CTS */
#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
#define UARTE_INTENCLR_CTS_Disabled (0x0UL) /*!< Read: Disabled */
#define UARTE_INTENCLR_CTS_Enabled (0x1UL) /*!< Read: Enabled */
#define UARTE_INTENCLR_CTS_Clear (0x1UL) /*!< Disable */

/* Register: UARTE_ERRORSRC */
/* Description: Error source */

/* Bit 3 : Break condition */
#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
#define UARTE_ERRORSRC_BREAK_NotPresent (0x0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_BREAK_Present (0x1UL) /*!< Read: error present */

/* Bit 2 : Framing error occurred */
#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
#define UARTE_ERRORSRC_FRAMING_NotPresent (0x0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_FRAMING_Present (0x1UL) /*!< Read: error present */

/* Bit 1 : Parity error */
#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define UARTE_ERRORSRC_PARITY_NotPresent (0x0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_PARITY_Present (0x1UL) /*!< Read: error present */

/* Bit 0 : Overrun error */
#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define UARTE_ERRORSRC_OVERRUN_NotPresent (0x0UL) /*!< Read: error not present */
#define UARTE_ERRORSRC_OVERRUN_Present (0x1UL) /*!< Read: error present */

/* Register: UARTE_ENABLE */
/* Description: Enable UART */

/* Bits 3..0 : Enable or disable UARTE */
#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define UARTE_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable UARTE */
#define UARTE_ENABLE_ENABLE_Enabled (0x8UL) /*!< Enable UARTE */

/* Register: UARTE_PSEL_RTS */
/* Description: Pin select for RTS signal */

/* Bit 31 : Connection */
#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_RTS_CONNECT_Connected (0x0UL) /*!< Connect */
#define UARTE_PSEL_RTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
#define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: UARTE_PSEL_TXD */
/* Description: Pin select for TXD signal */

/* Bit 31 : Connection */
#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_TXD_CONNECT_Connected (0x0UL) /*!< Connect */
#define UARTE_PSEL_TXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
#define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: UARTE_PSEL_CTS */
/* Description: Pin select for CTS signal */

/* Bit 31 : Connection */
#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_CTS_CONNECT_Connected (0x0UL) /*!< Connect */
#define UARTE_PSEL_CTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
#define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: UARTE_PSEL_RXD */
/* Description: Pin select for RXD signal */

/* Bit 31 : Connection */
#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define UARTE_PSEL_RXD_CONNECT_Connected (0x0UL) /*!< Connect */
#define UARTE_PSEL_RXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */

/* Bit 5 : Port number */
#define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
#define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */

/* Bits 4..0 : Pin number */
#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */

/* Register: UARTE_BAUDRATE */
/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */

/* Bits 31..0 : Baud rate */
#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */

/* Register: UARTE_RXD_PTR */
/* Description: Data pointer */

/* Bits 31..0 : Data pointer */
#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: UARTE_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */

/* Bits 15..0 : Maximum number of bytes in receive buffer */
#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: UARTE_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */

/* Bits 15..0 : Number of bytes transferred in the last transaction */
#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: UARTE_TXD_PTR */
/* Description: Data pointer */

/* Bits 31..0 : Data pointer */
#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: UARTE_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */

/* Bits 15..0 : Maximum number of bytes in transmit buffer */
#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: UARTE_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */

/* Bits 15..0 : Number of bytes transferred in the last transaction */
#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: UARTE_CONFIG */
/* Description: Configuration of parity and hardware flow control */

/* Bit 8 : Even or odd parity type */
#define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
#define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
#define UARTE_CONFIG_PARITYTYPE_Even (0x0UL) /*!< Even parity */
#define UARTE_CONFIG_PARITYTYPE_Odd (0x1UL) /*!< Odd parity */

/* Bit 4 : Stop bits */
#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
#define UARTE_CONFIG_STOP_One (0x0UL) /*!< One stop bit */
#define UARTE_CONFIG_STOP_Two (0x1UL) /*!< Two stop bits */

/* Bits 3..1 : Parity */
#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */

/* Bit 0 : Hardware flow control */
#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
#define UARTE_CONFIG_HWFC_Disabled (0x0UL) /*!< Disabled */
#define UARTE_CONFIG_HWFC_Enabled (0x1UL) /*!< Enabled */


/* Peripheral: UICR */
/* Description: User Information Configuration Registers User information configuration registers */

/* Register: UICR_APPROTECT */
/* Description: Access port protection */

/* Bits 31..0 : Blocks debugger read/write access to all CPU registers and
          memory mapped addresses. */
#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
#define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
#define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
#define UICR_APPROTECT_PALL_Unprotected (0x50FA50FAUL) /*!< Unprotected */

/* Register: UICR_VREGHVOUT */
/* Description: Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP. */

/* Bits 2..0 : VREGH regulator output voltage. */
#define UICR_VREGHVOUT_VREGHVOUT_Pos (0UL) /*!< Position of VREGHVOUT field. */
#define UICR_VREGHVOUT_VREGHVOUT_Msk (0x7UL << UICR_VREGHVOUT_VREGHVOUT_Pos) /*!< Bit mask of VREGHVOUT field. */
#define UICR_VREGHVOUT_VREGHVOUT_1V8 (0x0UL) /*!< 1.8 V */
#define UICR_VREGHVOUT_VREGHVOUT_2V1 (0x1UL) /*!< 2.1 V */
#define UICR_VREGHVOUT_VREGHVOUT_2V4 (0x2UL) /*!< 2.4 V */
#define UICR_VREGHVOUT_VREGHVOUT_2V7 (0x3UL) /*!< 2.7 V */
#define UICR_VREGHVOUT_VREGHVOUT_3V0 (0x4UL) /*!< 3.0 V */
#define UICR_VREGHVOUT_VREGHVOUT_3V3 (0x5UL) /*!< 3.3 V */
#define UICR_VREGHVOUT_VREGHVOUT_DEFAULT (0x7UL) /*!< Default voltage: 1.8 V */

/* Register: UICR_HFXOCNT */
/* Description: HFXO startup counter */

/* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */
#define UICR_HFXOCNT_HFXOCNT_Pos (0UL) /*!< Position of HFXOCNT field. */
#define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos) /*!< Bit mask of HFXOCNT field. */
#define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0x00UL) /*!< Min debounce time = (0*64 us + 0.5 us) */
#define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (0xFEUL) /*!< Max debounce time = (254*64 us + 0.5 us) */
#define UICR_HFXOCNT_HFXOCNT_DefaultDebounceTime (0xFFUL) /*!< Default debounce time for erased UICR = 4*64 us + 0.5 us */

/* Register: UICR_SECUREAPPROTECT */
/* Description: Secure access port protection */

/* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure memory
        mapped addresses. */
#define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
#define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
#define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
#define UICR_SECUREAPPROTECT_PALL_Unprotected (0x50FA50FAUL) /*!< Unprotected */

/* Register: UICR_ERASEPROTECT */
/* Description: Erase protection */

/* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. */
#define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
#define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
#define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
#define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */

/* Register: UICR_TINSTANCE */
/* Description: SW-DP Target instance */

/* Bits 31..28 : TINSTANCE bits are negated and used in the SW-DP DLPIDR.TINSTANCE field. E.g. 0xF in this field is translated to 0x0 in DLPIDR.TINSTANCE field. */
#define UICR_TINSTANCE_TINSTANCE_Pos (28UL) /*!< Position of TINSTANCE field. */
#define UICR_TINSTANCE_TINSTANCE_Msk (0xFUL << UICR_TINSTANCE_TINSTANCE_Pos) /*!< Bit mask of TINSTANCE field. */

/* Register: UICR_NFCPINS */
/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */

/* Bit 0 : Setting of pins dedicated to NFC functionality */
#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
#define UICR_NFCPINS_PROTECT_Disabled (0x0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
#define UICR_NFCPINS_PROTECT_NFC (0x1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */

/* Register: UICR_OTP */
/* Description: Description collection: One time programmable memory */

/* Bits 31..16 : Upper half word */
#define UICR_OTP_UPPER_Pos (16UL) /*!< Position of UPPER field. */
#define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos) /*!< Bit mask of UPPER field. */

/* Bits 15..0 : Lower half word */
#define UICR_OTP_LOWER_Pos (0UL) /*!< Position of LOWER field. */
#define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos) /*!< Bit mask of LOWER field. */

/* Register: UICR_KEYSLOT_CONFIG_DEST */
/* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3])
          will be pushed by KMU. Note that this address must match that of a peripherals
          APB mapped write-only key registers, else the KMU can push this key value into
          an address range which the CPU can potentially read. */

/* Bits 31..0 : Secure APB destination address */
#define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */
#define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos) /*!< Bit mask of DEST field. */

/* Register: UICR_KEYSLOT_CONFIG_PERM */
/* Description: Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. */

/* Bit 16 : Revocation state for the key slot */
#define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */
#define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos) /*!< Bit mask of STATE field. */
#define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0x0UL) /*!< Key value registers can no longer be read or pushed */
#define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (0x1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */

/* Bit 2 : Push permission for key slot */
#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */
#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos) /*!< Bit mask of PUSH field. */
#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0x0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */
#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (0x1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */

/* Bit 1 : Read permission for key slot */
#define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */
#define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */
#define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0x0UL) /*!< Disable read from key value registers */
#define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (0x1UL) /*!< Enable read from key value registers */

/* Bit 0 : Write permission for key slot */
#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL) /*!< Position of WRITE field. */
#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0x0UL) /*!< Disable write to the key value registers */
#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (0x1UL) /*!< Enable write to the key value registers */

/* Register: UICR_KEYSLOT_KEY_VALUE */
/* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */

/* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot */
#define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
#define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */


/* Peripheral: USBD */
/* Description: Universal serial bus device 0 */

/* Register: USBD_TASKS_STARTEPIN */
/* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */

/* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */
#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */
#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (0x1UL) /*!< Trigger task */

/* Register: USBD_TASKS_STARTISOIN */
/* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */

/* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */
#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */
#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (0x1UL) /*!< Trigger task */

/* Register: USBD_TASKS_STARTEPOUT */
/* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */

/* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */
#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */
#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (0x1UL) /*!< Trigger task */

/* Register: USBD_TASKS_STARTISOOUT */
/* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */

/* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */
#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */
#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (0x1UL) /*!< Trigger task */

/* Register: USBD_TASKS_EP0RCVOUT */
/* Description: Allows OUT data stage on control endpoint 0 */

/* Bit 0 : Allows OUT data stage on control endpoint 0 */
#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */
#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */
#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (0x1UL) /*!< Trigger task */

/* Register: USBD_TASKS_EP0STATUS */
/* Description: Allows status stage on control endpoint 0 */

/* Bit 0 : Allows status stage on control endpoint 0 */
#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */
#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */
#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (0x1UL) /*!< Trigger task */

/* Register: USBD_TASKS_EP0STALL */
/* Description: Stalls data and status stage on control endpoint 0 */

/* Bit 0 : Stalls data and status stage on control endpoint 0 */
#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */
#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */
#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (0x1UL) /*!< Trigger task */

/* Register: USBD_TASKS_DPDMDRIVE */
/* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */

/* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */
#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */
#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */
#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (0x1UL) /*!< Trigger task */

/* Register: USBD_TASKS_DPDMNODRIVE */
/* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */

/* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */
#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */
#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */
#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (0x1UL) /*!< Trigger task */

/* Register: USBD_SUBSCRIBE_STARTEPIN */
/* Description: Description collection: Subscribe configuration for task STARTEPIN[n] */

/* Bit 31 :   */
#define USBD_SUBSCRIBE_STARTEPIN_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_SUBSCRIBE_STARTEPIN_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTEPIN_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_SUBSCRIBE_STARTEPIN_EN_Disabled (0x0UL) /*!< Disable subscription */
#define USBD_SUBSCRIBE_STARTEPIN_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STARTEPIN[n] will subscribe to */
#define USBD_SUBSCRIBE_STARTEPIN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_SUBSCRIBE_STARTEPIN_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTEPIN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_SUBSCRIBE_STARTISOIN */
/* Description: Subscribe configuration for task STARTISOIN */

/* Bit 31 :   */
#define USBD_SUBSCRIBE_STARTISOIN_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_SUBSCRIBE_STARTISOIN_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTISOIN_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_SUBSCRIBE_STARTISOIN_EN_Disabled (0x0UL) /*!< Disable subscription */
#define USBD_SUBSCRIBE_STARTISOIN_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STARTISOIN will subscribe to */
#define USBD_SUBSCRIBE_STARTISOIN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_SUBSCRIBE_STARTISOIN_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTISOIN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_SUBSCRIBE_STARTEPOUT */
/* Description: Description collection: Subscribe configuration for task STARTEPOUT[n] */

/* Bit 31 :   */
#define USBD_SUBSCRIBE_STARTEPOUT_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_SUBSCRIBE_STARTEPOUT_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTEPOUT_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_SUBSCRIBE_STARTEPOUT_EN_Disabled (0x0UL) /*!< Disable subscription */
#define USBD_SUBSCRIBE_STARTEPOUT_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STARTEPOUT[n] will subscribe to */
#define USBD_SUBSCRIBE_STARTEPOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_SUBSCRIBE_STARTEPOUT_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTEPOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_SUBSCRIBE_STARTISOOUT */
/* Description: Subscribe configuration for task STARTISOOUT */

/* Bit 31 :   */
#define USBD_SUBSCRIBE_STARTISOOUT_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_SUBSCRIBE_STARTISOOUT_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTISOOUT_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_SUBSCRIBE_STARTISOOUT_EN_Disabled (0x0UL) /*!< Disable subscription */
#define USBD_SUBSCRIBE_STARTISOOUT_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STARTISOOUT will subscribe to */
#define USBD_SUBSCRIBE_STARTISOOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_SUBSCRIBE_STARTISOOUT_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTISOOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_SUBSCRIBE_EP0RCVOUT */
/* Description: Subscribe configuration for task EP0RCVOUT */

/* Bit 31 :   */
#define USBD_SUBSCRIBE_EP0RCVOUT_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_SUBSCRIBE_EP0RCVOUT_EN_Msk (0x1UL << USBD_SUBSCRIBE_EP0RCVOUT_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_SUBSCRIBE_EP0RCVOUT_EN_Disabled (0x0UL) /*!< Disable subscription */
#define USBD_SUBSCRIBE_EP0RCVOUT_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task EP0RCVOUT will subscribe to */
#define USBD_SUBSCRIBE_EP0RCVOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_SUBSCRIBE_EP0RCVOUT_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_EP0RCVOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_SUBSCRIBE_EP0STATUS */
/* Description: Subscribe configuration for task EP0STATUS */

/* Bit 31 :   */
#define USBD_SUBSCRIBE_EP0STATUS_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_SUBSCRIBE_EP0STATUS_EN_Msk (0x1UL << USBD_SUBSCRIBE_EP0STATUS_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_SUBSCRIBE_EP0STATUS_EN_Disabled (0x0UL) /*!< Disable subscription */
#define USBD_SUBSCRIBE_EP0STATUS_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task EP0STATUS will subscribe to */
#define USBD_SUBSCRIBE_EP0STATUS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_SUBSCRIBE_EP0STATUS_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_EP0STATUS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_SUBSCRIBE_EP0STALL */
/* Description: Subscribe configuration for task EP0STALL */

/* Bit 31 :   */
#define USBD_SUBSCRIBE_EP0STALL_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_SUBSCRIBE_EP0STALL_EN_Msk (0x1UL << USBD_SUBSCRIBE_EP0STALL_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_SUBSCRIBE_EP0STALL_EN_Disabled (0x0UL) /*!< Disable subscription */
#define USBD_SUBSCRIBE_EP0STALL_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task EP0STALL will subscribe to */
#define USBD_SUBSCRIBE_EP0STALL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_SUBSCRIBE_EP0STALL_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_EP0STALL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_SUBSCRIBE_DPDMDRIVE */
/* Description: Subscribe configuration for task DPDMDRIVE */

/* Bit 31 :   */
#define USBD_SUBSCRIBE_DPDMDRIVE_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_SUBSCRIBE_DPDMDRIVE_EN_Msk (0x1UL << USBD_SUBSCRIBE_DPDMDRIVE_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_SUBSCRIBE_DPDMDRIVE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define USBD_SUBSCRIBE_DPDMDRIVE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task DPDMDRIVE will subscribe to */
#define USBD_SUBSCRIBE_DPDMDRIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_SUBSCRIBE_DPDMDRIVE_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_DPDMDRIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_SUBSCRIBE_DPDMNODRIVE */
/* Description: Subscribe configuration for task DPDMNODRIVE */

/* Bit 31 :   */
#define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Msk (0x1UL << USBD_SUBSCRIBE_DPDMNODRIVE_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Disabled (0x0UL) /*!< Disable subscription */
#define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task DPDMNODRIVE will subscribe to */
#define USBD_SUBSCRIBE_DPDMNODRIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_SUBSCRIBE_DPDMNODRIVE_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_DPDMNODRIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_EVENTS_USBRESET */
/* Description: Signals that a USB reset condition has been detected on USB lines */

/* Bit 0 : Signals that a USB reset condition has been detected on USB lines */
#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */
#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */
#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_EVENTS_STARTED */
/* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */

/* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
#define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
#define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
#define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_EVENTS_ENDEPIN */
/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */

/* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */
#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */
#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_EVENTS_EP0DATADONE */
/* Description: An acknowledged data transfer has taken place on the control endpoint */

/* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */
#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */
#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */
#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_EVENTS_ENDISOIN */
/* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */

/* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */
#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */
#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_EVENTS_ENDEPOUT */
/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */

/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */
#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */
#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_EVENTS_ENDISOOUT */
/* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */

/* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */
#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */
#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_EVENTS_SOF */
/* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */

/* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */
#define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */
#define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */
#define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_SOF_EVENTS_SOF_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_EVENTS_USBEVENT */
/* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */

/* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */
#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */
#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_EVENTS_EP0SETUP */
/* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */

/* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */
#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */
#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */
#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_EVENTS_EPDATA */
/* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */

/* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */
#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */
#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0x0UL) /*!< Event not generated */
#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (0x1UL) /*!< Event generated */

/* Register: USBD_PUBLISH_USBRESET */
/* Description: Publish configuration for event USBRESET */

/* Bit 31 :   */
#define USBD_PUBLISH_USBRESET_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_USBRESET_EN_Msk (0x1UL << USBD_PUBLISH_USBRESET_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_USBRESET_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_USBRESET_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event USBRESET will publish to */
#define USBD_PUBLISH_USBRESET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_USBRESET_CHIDX_Msk (0xFFUL << USBD_PUBLISH_USBRESET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_PUBLISH_STARTED */
/* Description: Publish configuration for event STARTED */

/* Bit 31 :   */
#define USBD_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_STARTED_EN_Msk (0x1UL << USBD_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STARTED will publish to */
#define USBD_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << USBD_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_PUBLISH_ENDEPIN */
/* Description: Description collection: Publish configuration for event ENDEPIN[n] */

/* Bit 31 :   */
#define USBD_PUBLISH_ENDEPIN_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_ENDEPIN_EN_Msk (0x1UL << USBD_PUBLISH_ENDEPIN_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_ENDEPIN_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_ENDEPIN_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDEPIN[n] will publish to */
#define USBD_PUBLISH_ENDEPIN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_ENDEPIN_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDEPIN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_PUBLISH_EP0DATADONE */
/* Description: Publish configuration for event EP0DATADONE */

/* Bit 31 :   */
#define USBD_PUBLISH_EP0DATADONE_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_EP0DATADONE_EN_Msk (0x1UL << USBD_PUBLISH_EP0DATADONE_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_EP0DATADONE_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_EP0DATADONE_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event EP0DATADONE will publish to */
#define USBD_PUBLISH_EP0DATADONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_EP0DATADONE_CHIDX_Msk (0xFFUL << USBD_PUBLISH_EP0DATADONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_PUBLISH_ENDISOIN */
/* Description: Publish configuration for event ENDISOIN */

/* Bit 31 :   */
#define USBD_PUBLISH_ENDISOIN_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_ENDISOIN_EN_Msk (0x1UL << USBD_PUBLISH_ENDISOIN_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_ENDISOIN_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_ENDISOIN_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDISOIN will publish to */
#define USBD_PUBLISH_ENDISOIN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_ENDISOIN_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDISOIN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_PUBLISH_ENDEPOUT */
/* Description: Description collection: Publish configuration for event ENDEPOUT[n] */

/* Bit 31 :   */
#define USBD_PUBLISH_ENDEPOUT_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_ENDEPOUT_EN_Msk (0x1UL << USBD_PUBLISH_ENDEPOUT_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_ENDEPOUT_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_ENDEPOUT_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDEPOUT[n] will publish to */
#define USBD_PUBLISH_ENDEPOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_ENDEPOUT_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDEPOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_PUBLISH_ENDISOOUT */
/* Description: Publish configuration for event ENDISOOUT */

/* Bit 31 :   */
#define USBD_PUBLISH_ENDISOOUT_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_ENDISOOUT_EN_Msk (0x1UL << USBD_PUBLISH_ENDISOOUT_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_ENDISOOUT_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_ENDISOOUT_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event ENDISOOUT will publish to */
#define USBD_PUBLISH_ENDISOOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_ENDISOOUT_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDISOOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_PUBLISH_SOF */
/* Description: Publish configuration for event SOF */

/* Bit 31 :   */
#define USBD_PUBLISH_SOF_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_SOF_EN_Msk (0x1UL << USBD_PUBLISH_SOF_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_SOF_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_SOF_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event SOF will publish to */
#define USBD_PUBLISH_SOF_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_SOF_CHIDX_Msk (0xFFUL << USBD_PUBLISH_SOF_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_PUBLISH_USBEVENT */
/* Description: Publish configuration for event USBEVENT */

/* Bit 31 :   */
#define USBD_PUBLISH_USBEVENT_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_USBEVENT_EN_Msk (0x1UL << USBD_PUBLISH_USBEVENT_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_USBEVENT_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_USBEVENT_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event USBEVENT will publish to */
#define USBD_PUBLISH_USBEVENT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_USBEVENT_CHIDX_Msk (0xFFUL << USBD_PUBLISH_USBEVENT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_PUBLISH_EP0SETUP */
/* Description: Publish configuration for event EP0SETUP */

/* Bit 31 :   */
#define USBD_PUBLISH_EP0SETUP_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_EP0SETUP_EN_Msk (0x1UL << USBD_PUBLISH_EP0SETUP_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_EP0SETUP_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_EP0SETUP_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event EP0SETUP will publish to */
#define USBD_PUBLISH_EP0SETUP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_EP0SETUP_CHIDX_Msk (0xFFUL << USBD_PUBLISH_EP0SETUP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_PUBLISH_EPDATA */
/* Description: Publish configuration for event EPDATA */

/* Bit 31 :   */
#define USBD_PUBLISH_EPDATA_EN_Pos (31UL) /*!< Position of EN field. */
#define USBD_PUBLISH_EPDATA_EN_Msk (0x1UL << USBD_PUBLISH_EPDATA_EN_Pos) /*!< Bit mask of EN field. */
#define USBD_PUBLISH_EPDATA_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBD_PUBLISH_EPDATA_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event EPDATA will publish to */
#define USBD_PUBLISH_EPDATA_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBD_PUBLISH_EPDATA_CHIDX_Msk (0xFFUL << USBD_PUBLISH_EPDATA_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBD_SHORTS */
/* Description: Shortcuts between local events and tasks */

/* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */
#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */
#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */
#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0x0UL) /*!< Disable shortcut */
#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */
#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */
#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */
#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0x0UL) /*!< Disable shortcut */
#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */
#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */
#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */
#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0x0UL) /*!< Disable shortcut */
#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */
#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */
#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */
#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0x0UL) /*!< Disable shortcut */
#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (0x1UL) /*!< Enable shortcut */

/* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */
#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */
#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */
#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0x0UL) /*!< Disable shortcut */
#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (0x1UL) /*!< Enable shortcut */

/* Register: USBD_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 24 : Enable or disable interrupt for event EPDATA */
#define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
#define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
#define USBD_INTEN_EPDATA_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_EPDATA_Enabled (0x1UL) /*!< Enable */

/* Bit 23 : Enable or disable interrupt for event EP0SETUP */
#define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
#define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
#define USBD_INTEN_EP0SETUP_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_EP0SETUP_Enabled (0x1UL) /*!< Enable */

/* Bit 22 : Enable or disable interrupt for event USBEVENT */
#define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
#define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
#define USBD_INTEN_USBEVENT_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_USBEVENT_Enabled (0x1UL) /*!< Enable */

/* Bit 21 : Enable or disable interrupt for event SOF */
#define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */
#define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */
#define USBD_INTEN_SOF_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_SOF_Enabled (0x1UL) /*!< Enable */

/* Bit 20 : Enable or disable interrupt for event ENDISOOUT */
#define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
#define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
#define USBD_INTEN_ENDISOOUT_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDISOOUT_Enabled (0x1UL) /*!< Enable */

/* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */
#define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
#define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
#define USBD_INTEN_ENDEPOUT7_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPOUT7_Enabled (0x1UL) /*!< Enable */

/* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */
#define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
#define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
#define USBD_INTEN_ENDEPOUT6_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPOUT6_Enabled (0x1UL) /*!< Enable */

/* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */
#define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
#define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
#define USBD_INTEN_ENDEPOUT5_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPOUT5_Enabled (0x1UL) /*!< Enable */

/* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */
#define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
#define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
#define USBD_INTEN_ENDEPOUT4_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPOUT4_Enabled (0x1UL) /*!< Enable */

/* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */
#define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
#define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
#define USBD_INTEN_ENDEPOUT3_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPOUT3_Enabled (0x1UL) /*!< Enable */

/* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */
#define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
#define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
#define USBD_INTEN_ENDEPOUT2_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPOUT2_Enabled (0x1UL) /*!< Enable */

/* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */
#define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
#define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
#define USBD_INTEN_ENDEPOUT1_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPOUT1_Enabled (0x1UL) /*!< Enable */

/* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */
#define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
#define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
#define USBD_INTEN_ENDEPOUT0_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPOUT0_Enabled (0x1UL) /*!< Enable */

/* Bit 11 : Enable or disable interrupt for event ENDISOIN */
#define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
#define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
#define USBD_INTEN_ENDISOIN_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDISOIN_Enabled (0x1UL) /*!< Enable */

/* Bit 10 : Enable or disable interrupt for event EP0DATADONE */
#define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
#define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
#define USBD_INTEN_EP0DATADONE_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_EP0DATADONE_Enabled (0x1UL) /*!< Enable */

/* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */
#define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
#define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
#define USBD_INTEN_ENDEPIN7_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPIN7_Enabled (0x1UL) /*!< Enable */

/* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */
#define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
#define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
#define USBD_INTEN_ENDEPIN6_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPIN6_Enabled (0x1UL) /*!< Enable */

/* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */
#define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
#define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
#define USBD_INTEN_ENDEPIN5_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPIN5_Enabled (0x1UL) /*!< Enable */

/* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */
#define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
#define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
#define USBD_INTEN_ENDEPIN4_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPIN4_Enabled (0x1UL) /*!< Enable */

/* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */
#define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
#define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
#define USBD_INTEN_ENDEPIN3_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPIN3_Enabled (0x1UL) /*!< Enable */

/* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */
#define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
#define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
#define USBD_INTEN_ENDEPIN2_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPIN2_Enabled (0x1UL) /*!< Enable */

/* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */
#define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
#define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
#define USBD_INTEN_ENDEPIN1_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPIN1_Enabled (0x1UL) /*!< Enable */

/* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */
#define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
#define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
#define USBD_INTEN_ENDEPIN0_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_ENDEPIN0_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event STARTED */
#define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */
#define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define USBD_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event USBRESET */
#define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
#define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
#define USBD_INTEN_USBRESET_Disabled (0x0UL) /*!< Disable */
#define USBD_INTEN_USBRESET_Enabled (0x1UL) /*!< Enable */

/* Register: USBD_INTENSET */
/* Description: Enable interrupt */

/* Bit 24 : Write '1' to enable interrupt for event EPDATA */
#define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
#define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
#define USBD_INTENSET_EPDATA_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_EPDATA_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_EPDATA_Set (0x1UL) /*!< Enable */

/* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */
#define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
#define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
#define USBD_INTENSET_EP0SETUP_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_EP0SETUP_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_EP0SETUP_Set (0x1UL) /*!< Enable */

/* Bit 22 : Write '1' to enable interrupt for event USBEVENT */
#define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
#define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
#define USBD_INTENSET_USBEVENT_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_USBEVENT_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_USBEVENT_Set (0x1UL) /*!< Enable */

/* Bit 21 : Write '1' to enable interrupt for event SOF */
#define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */
#define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */
#define USBD_INTENSET_SOF_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_SOF_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_SOF_Set (0x1UL) /*!< Enable */

/* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */
#define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
#define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
#define USBD_INTENSET_ENDISOOUT_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDISOOUT_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDISOOUT_Set (0x1UL) /*!< Enable */

/* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */
#define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
#define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
#define USBD_INTENSET_ENDEPOUT7_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPOUT7_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPOUT7_Set (0x1UL) /*!< Enable */

/* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */
#define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
#define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
#define USBD_INTENSET_ENDEPOUT6_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPOUT6_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPOUT6_Set (0x1UL) /*!< Enable */

/* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */
#define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
#define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
#define USBD_INTENSET_ENDEPOUT5_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPOUT5_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPOUT5_Set (0x1UL) /*!< Enable */

/* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */
#define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
#define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
#define USBD_INTENSET_ENDEPOUT4_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPOUT4_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPOUT4_Set (0x1UL) /*!< Enable */

/* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */
#define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
#define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
#define USBD_INTENSET_ENDEPOUT3_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPOUT3_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPOUT3_Set (0x1UL) /*!< Enable */

/* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */
#define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
#define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
#define USBD_INTENSET_ENDEPOUT2_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPOUT2_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPOUT2_Set (0x1UL) /*!< Enable */

/* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */
#define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
#define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
#define USBD_INTENSET_ENDEPOUT1_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPOUT1_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPOUT1_Set (0x1UL) /*!< Enable */

/* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */
#define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
#define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
#define USBD_INTENSET_ENDEPOUT0_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPOUT0_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPOUT0_Set (0x1UL) /*!< Enable */

/* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */
#define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
#define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
#define USBD_INTENSET_ENDISOIN_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDISOIN_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDISOIN_Set (0x1UL) /*!< Enable */

/* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */
#define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
#define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
#define USBD_INTENSET_EP0DATADONE_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_EP0DATADONE_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_EP0DATADONE_Set (0x1UL) /*!< Enable */

/* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */
#define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
#define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
#define USBD_INTENSET_ENDEPIN7_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPIN7_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPIN7_Set (0x1UL) /*!< Enable */

/* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */
#define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
#define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
#define USBD_INTENSET_ENDEPIN6_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPIN6_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPIN6_Set (0x1UL) /*!< Enable */

/* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */
#define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
#define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
#define USBD_INTENSET_ENDEPIN5_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPIN5_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPIN5_Set (0x1UL) /*!< Enable */

/* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */
#define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
#define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
#define USBD_INTENSET_ENDEPIN4_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPIN4_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPIN4_Set (0x1UL) /*!< Enable */

/* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */
#define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
#define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
#define USBD_INTENSET_ENDEPIN3_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPIN3_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPIN3_Set (0x1UL) /*!< Enable */

/* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */
#define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
#define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
#define USBD_INTENSET_ENDEPIN2_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPIN2_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPIN2_Set (0x1UL) /*!< Enable */

/* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */
#define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
#define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
#define USBD_INTENSET_ENDEPIN1_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPIN1_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPIN1_Set (0x1UL) /*!< Enable */

/* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */
#define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
#define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
#define USBD_INTENSET_ENDEPIN0_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_ENDEPIN0_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_ENDEPIN0_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event STARTED */
#define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */
#define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define USBD_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_STARTED_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event USBRESET */
#define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
#define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
#define USBD_INTENSET_USBRESET_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENSET_USBRESET_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENSET_USBRESET_Set (0x1UL) /*!< Enable */

/* Register: USBD_INTENCLR */
/* Description: Disable interrupt */

/* Bit 24 : Write '1' to disable interrupt for event EPDATA */
#define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
#define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
#define USBD_INTENCLR_EPDATA_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_EPDATA_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_EPDATA_Clear (0x1UL) /*!< Disable */

/* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */
#define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
#define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
#define USBD_INTENCLR_EP0SETUP_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_EP0SETUP_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_EP0SETUP_Clear (0x1UL) /*!< Disable */

/* Bit 22 : Write '1' to disable interrupt for event USBEVENT */
#define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
#define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
#define USBD_INTENCLR_USBEVENT_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_USBEVENT_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_USBEVENT_Clear (0x1UL) /*!< Disable */

/* Bit 21 : Write '1' to disable interrupt for event SOF */
#define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */
#define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */
#define USBD_INTENCLR_SOF_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_SOF_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_SOF_Clear (0x1UL) /*!< Disable */

/* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */
#define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
#define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
#define USBD_INTENCLR_ENDISOOUT_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDISOOUT_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDISOOUT_Clear (0x1UL) /*!< Disable */

/* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */
#define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
#define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
#define USBD_INTENCLR_ENDEPOUT7_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPOUT7_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPOUT7_Clear (0x1UL) /*!< Disable */

/* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */
#define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
#define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
#define USBD_INTENCLR_ENDEPOUT6_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPOUT6_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPOUT6_Clear (0x1UL) /*!< Disable */

/* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */
#define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
#define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
#define USBD_INTENCLR_ENDEPOUT5_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPOUT5_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPOUT5_Clear (0x1UL) /*!< Disable */

/* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */
#define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
#define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
#define USBD_INTENCLR_ENDEPOUT4_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPOUT4_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPOUT4_Clear (0x1UL) /*!< Disable */

/* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */
#define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
#define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
#define USBD_INTENCLR_ENDEPOUT3_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPOUT3_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPOUT3_Clear (0x1UL) /*!< Disable */

/* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */
#define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
#define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
#define USBD_INTENCLR_ENDEPOUT2_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPOUT2_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPOUT2_Clear (0x1UL) /*!< Disable */

/* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */
#define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
#define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
#define USBD_INTENCLR_ENDEPOUT1_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPOUT1_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPOUT1_Clear (0x1UL) /*!< Disable */

/* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */
#define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
#define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
#define USBD_INTENCLR_ENDEPOUT0_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPOUT0_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPOUT0_Clear (0x1UL) /*!< Disable */

/* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */
#define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
#define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
#define USBD_INTENCLR_ENDISOIN_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDISOIN_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDISOIN_Clear (0x1UL) /*!< Disable */

/* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */
#define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
#define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
#define USBD_INTENCLR_EP0DATADONE_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_EP0DATADONE_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_EP0DATADONE_Clear (0x1UL) /*!< Disable */

/* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */
#define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
#define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
#define USBD_INTENCLR_ENDEPIN7_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPIN7_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPIN7_Clear (0x1UL) /*!< Disable */

/* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */
#define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
#define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
#define USBD_INTENCLR_ENDEPIN6_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPIN6_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPIN6_Clear (0x1UL) /*!< Disable */

/* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */
#define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
#define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
#define USBD_INTENCLR_ENDEPIN5_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPIN5_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPIN5_Clear (0x1UL) /*!< Disable */

/* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */
#define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
#define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
#define USBD_INTENCLR_ENDEPIN4_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPIN4_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPIN4_Clear (0x1UL) /*!< Disable */

/* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */
#define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
#define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
#define USBD_INTENCLR_ENDEPIN3_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPIN3_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPIN3_Clear (0x1UL) /*!< Disable */

/* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */
#define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
#define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
#define USBD_INTENCLR_ENDEPIN2_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPIN2_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPIN2_Clear (0x1UL) /*!< Disable */

/* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */
#define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
#define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
#define USBD_INTENCLR_ENDEPIN1_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPIN1_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPIN1_Clear (0x1UL) /*!< Disable */

/* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */
#define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
#define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
#define USBD_INTENCLR_ENDEPIN0_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_ENDEPIN0_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_ENDEPIN0_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event STARTED */
#define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */
#define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
#define USBD_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event USBRESET */
#define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
#define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
#define USBD_INTENCLR_USBRESET_Disabled (0x0UL) /*!< Read: Disabled */
#define USBD_INTENCLR_USBRESET_Enabled (0x1UL) /*!< Read: Enabled */
#define USBD_INTENCLR_USBRESET_Clear (0x1UL) /*!< Disable */

/* Register: USBD_EVENTCAUSE */
/* Description: Details on what caused the USBEVENT event */

/* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */
#define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */
#define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */
#define USBD_EVENTCAUSE_READY_NotDetected (0x0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */
#define USBD_EVENTCAUSE_READY_Ready (0x1UL) /*!< USBD peripheral is ready */

/* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */
#define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */
#define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */
#define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0x0UL) /*!< Wake up not allowed */
#define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (0x1UL) /*!< Wake up allowed */

/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */
#define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */
#define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */
#define USBD_EVENTCAUSE_RESUME_NotDetected (0x0UL) /*!< Resume not detected */
#define USBD_EVENTCAUSE_RESUME_Detected (0x1UL) /*!< Resume detected */

/* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */
#define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */
#define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */
#define USBD_EVENTCAUSE_SUSPEND_NotDetected (0x0UL) /*!< Suspend not detected */
#define USBD_EVENTCAUSE_SUSPEND_Detected (0x1UL) /*!< Suspend detected */

/* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */
#define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */
#define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */
#define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0x0UL) /*!< No error detected */
#define USBD_EVENTCAUSE_ISOOUTCRC_Detected (0x1UL) /*!< Error detected */

/* Register: USBD_HALTED_EPIN */
/* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */

/* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
#define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
#define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
#define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0x0000UL) /*!< Endpoint is not halted */
#define USBD_HALTED_EPIN_GETSTATUS_Halted (0x0001UL) /*!< Endpoint is halted */

/* Register: USBD_HALTED_EPOUT */
/* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */

/* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
#define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
#define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
#define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0x0000UL) /*!< Endpoint is not halted */
#define USBD_HALTED_EPOUT_GETSTATUS_Halted (0x0001UL) /*!< Endpoint is halted */

/* Register: USBD_EPSTATUS */
/* Description: Provides information on which endpoint's EasyDMA registers have been captured */

/* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */
#define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */
#define USBD_EPSTATUS_EPOUT8_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPOUT8_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
#define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
#define USBD_EPSTATUS_EPOUT7_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPOUT7_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
#define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
#define USBD_EPSTATUS_EPOUT6_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPOUT6_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
#define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
#define USBD_EPSTATUS_EPOUT5_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPOUT5_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
#define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
#define USBD_EPSTATUS_EPOUT4_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPOUT4_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
#define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
#define USBD_EPSTATUS_EPOUT3_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPOUT3_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
#define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
#define USBD_EPSTATUS_EPOUT2_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPOUT2_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
#define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
#define USBD_EPSTATUS_EPOUT1_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPOUT1_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */
#define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */
#define USBD_EPSTATUS_EPOUT0_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPOUT0_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */
#define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */
#define USBD_EPSTATUS_EPIN8_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPIN8_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
#define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
#define USBD_EPSTATUS_EPIN7_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPIN7_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
#define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
#define USBD_EPSTATUS_EPIN6_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPIN6_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
#define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
#define USBD_EPSTATUS_EPIN5_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPIN5_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
#define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
#define USBD_EPSTATUS_EPIN4_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPIN4_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
#define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
#define USBD_EPSTATUS_EPIN3_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPIN3_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
#define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
#define USBD_EPSTATUS_EPIN2_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPIN2_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
#define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
#define USBD_EPSTATUS_EPIN1_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPIN1_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
#define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */
#define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */
#define USBD_EPSTATUS_EPIN0_NoData (0x0UL) /*!< EasyDMA registers have not been captured for this endpoint */
#define USBD_EPSTATUS_EPIN0_DataDone (0x1UL) /*!< EasyDMA registers have been captured for this endpoint */

/* Register: USBD_EPDATASTATUS */
/* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */

/* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
#define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
#define USBD_EPDATASTATUS_EPOUT7_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPOUT7_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
#define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
#define USBD_EPDATASTATUS_EPOUT6_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPOUT6_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
#define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
#define USBD_EPDATASTATUS_EPOUT5_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPOUT5_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
#define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
#define USBD_EPDATASTATUS_EPOUT4_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPOUT4_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
#define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
#define USBD_EPDATASTATUS_EPOUT3_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPOUT3_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
#define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
#define USBD_EPDATASTATUS_EPOUT2_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPOUT2_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
#define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
#define USBD_EPDATASTATUS_EPOUT1_NotStarted (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPOUT1_Started (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
#define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
#define USBD_EPDATASTATUS_EPIN7_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPIN7_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
#define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
#define USBD_EPDATASTATUS_EPIN6_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPIN6_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
#define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
#define USBD_EPDATASTATUS_EPIN5_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPIN5_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
#define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
#define USBD_EPDATASTATUS_EPIN4_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPIN4_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
#define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
#define USBD_EPDATASTATUS_EPIN3_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPIN3_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
#define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
#define USBD_EPDATASTATUS_EPIN2_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPIN2_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
#define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
#define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
#define USBD_EPDATASTATUS_EPIN1_NotDone (0x0UL) /*!< No acknowledged data transfer on this endpoint */
#define USBD_EPDATASTATUS_EPIN1_DataDone (0x1UL) /*!< Acknowledged data transfer on this endpoint has occurred */

/* Register: USBD_USBADDR */
/* Description: Device USB address */

/* Bits 6..0 : Device USB address */
#define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
#define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */

/* Register: USBD_BMREQUESTTYPE */
/* Description: SETUP data, byte 0, bmRequestType */

/* Bit 7 : Data transfer direction */
#define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */
#define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */
#define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0x0UL) /*!< Host-to-device */
#define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (0x1UL) /*!< Device-to-host */

/* Bits 6..5 : Data transfer type */
#define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */
#define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */
#define USBD_BMREQUESTTYPE_TYPE_Standard (0x0UL) /*!< Standard */
#define USBD_BMREQUESTTYPE_TYPE_Class (0x1UL) /*!< Class */
#define USBD_BMREQUESTTYPE_TYPE_Vendor (0x2UL) /*!< Vendor */

/* Bits 4..0 : Data transfer type */
#define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */
#define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */
#define USBD_BMREQUESTTYPE_RECIPIENT_Device (0x00UL) /*!< Device */
#define USBD_BMREQUESTTYPE_RECIPIENT_Interface (0x01UL) /*!< Interface */
#define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (0x02UL) /*!< Endpoint */
#define USBD_BMREQUESTTYPE_RECIPIENT_Other (0x03UL) /*!< Other */

/* Register: USBD_BREQUEST */
/* Description: SETUP data, byte 1, bRequest */

/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */
#define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */
#define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */
#define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0x00UL) /*!< Standard request GET_STATUS */
#define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (0x01UL) /*!< Standard request CLEAR_FEATURE */
#define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (0x03UL) /*!< Standard request SET_FEATURE */
#define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (0x05UL) /*!< Standard request SET_ADDRESS */
#define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (0x06UL) /*!< Standard request GET_DESCRIPTOR */
#define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (0x07UL) /*!< Standard request SET_DESCRIPTOR */
#define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (0x08UL) /*!< Standard request GET_CONFIGURATION */
#define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (0x09UL) /*!< Standard request SET_CONFIGURATION */
#define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (0x0AUL) /*!< Standard request GET_INTERFACE */
#define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (0x0BUL) /*!< Standard request SET_INTERFACE */
#define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (0x0CUL) /*!< Standard request SYNCH_FRAME */

/* Register: USBD_WVALUEL */
/* Description: SETUP data, byte 2, LSB of wValue */

/* Bits 7..0 : SETUP data, byte 2, LSB of wValue */
#define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */
#define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */

/* Register: USBD_WVALUEH */
/* Description: SETUP data, byte 3, MSB of wValue */

/* Bits 7..0 : SETUP data, byte 3, MSB of wValue */
#define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */
#define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */

/* Register: USBD_WINDEXL */
/* Description: SETUP data, byte 4, LSB of wIndex */

/* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */
#define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */
#define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */

/* Register: USBD_WINDEXH */
/* Description: SETUP data, byte 5, MSB of wIndex */

/* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */
#define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */
#define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */

/* Register: USBD_WLENGTHL */
/* Description: SETUP data, byte 6, LSB of wLength */

/* Bits 7..0 : SETUP data, byte 6, LSB of wLength */
#define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */
#define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */

/* Register: USBD_WLENGTHH */
/* Description: SETUP data, byte 7, MSB of wLength */

/* Bits 7..0 : SETUP data, byte 7, MSB of wLength */
#define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */
#define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */

/* Register: USBD_SIZE_EPOUT */
/* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */

/* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */
#define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
#define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */

/* Register: USBD_SIZE_ISOOUT */
/* Description: Number of bytes received last on this ISO OUT data endpoint */

/* Bit 16 : Zero-length data packet received */
#define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */
#define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */
#define USBD_SIZE_ISOOUT_ZERO_Normal (0x0UL) /*!< No zero-length data received, use value in SIZE */
#define USBD_SIZE_ISOOUT_ZERO_ZeroData (0x1UL) /*!< Zero-length data received, ignore value in SIZE */

/* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */
#define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
#define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */

/* Register: USBD_ENABLE */
/* Description: Enable USB */

/* Bit 0 : Enable USB */
#define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define USBD_ENABLE_ENABLE_Disabled (0x0UL) /*!< USB peripheral is disabled */
#define USBD_ENABLE_ENABLE_Enabled (0x1UL) /*!< USB peripheral is enabled */

/* Register: USBD_USBPULLUP */
/* Description: Control of the USB pull-up */

/* Bit 0 : Control of the USB pull-up on the D+ line */
#define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */
#define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define USBD_USBPULLUP_CONNECT_Disabled (0x0UL) /*!< Pull-up is disconnected */
#define USBD_USBPULLUP_CONNECT_Enabled (0x1UL) /*!< Pull-up is connected to D+ */

/* Register: USBD_DPDMVALUE */
/* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */

/* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */
#define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */
#define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */
#define USBD_DPDMVALUE_STATE_Resume (0x01UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */
#define USBD_DPDMVALUE_STATE_J (0x02UL) /*!< D+ forced high, D- forced low (J state) */
#define USBD_DPDMVALUE_STATE_K (0x04UL) /*!< D+ forced low, D- forced high (K state) */

/* Register: USBD_DTOGGLE */
/* Description: Data toggle control and status */

/* Bits 9..8 : Data toggle value */
#define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */
#define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */
#define USBD_DTOGGLE_VALUE_Nop (0x0UL) /*!< No action on data toggle when writing the register with this value */
#define USBD_DTOGGLE_VALUE_Data0 (0x1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */
#define USBD_DTOGGLE_VALUE_Data1 (0x2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */

/* Bit 7 : Selects IN or OUT endpoint */
#define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */
#define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */
#define USBD_DTOGGLE_IO_Out (0x0UL) /*!< Selects OUT endpoint */
#define USBD_DTOGGLE_IO_In (0x1UL) /*!< Selects IN endpoint */

/* Bits 2..0 : Select bulk endpoint number */
#define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */
#define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */

/* Register: USBD_EPINEN */
/* Description: Endpoint IN enable */

/* Bit 8 : Enable ISO IN endpoint */
#define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */
#define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */
#define USBD_EPINEN_ISOIN_Disable (0x0UL) /*!< Disable ISO IN endpoint 8 */
#define USBD_EPINEN_ISOIN_Enable (0x1UL) /*!< Enable ISO IN endpoint 8 */

/* Bit 7 : Enable IN endpoint 7 */
#define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */
#define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */
#define USBD_EPINEN_IN7_Disable (0x0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */
#define USBD_EPINEN_IN7_Enable (0x1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */

/* Bit 6 : Enable IN endpoint 6 */
#define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */
#define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */
#define USBD_EPINEN_IN6_Disable (0x0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
#define USBD_EPINEN_IN6_Enable (0x1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */

/* Bit 5 : Enable IN endpoint 5 */
#define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */
#define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */
#define USBD_EPINEN_IN5_Disable (0x0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
#define USBD_EPINEN_IN5_Enable (0x1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */

/* Bit 4 : Enable IN endpoint 4 */
#define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */
#define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */
#define USBD_EPINEN_IN4_Disable (0x0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
#define USBD_EPINEN_IN4_Enable (0x1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */

/* Bit 3 : Enable IN endpoint 3 */
#define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */
#define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */
#define USBD_EPINEN_IN3_Disable (0x0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
#define USBD_EPINEN_IN3_Enable (0x1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */

/* Bit 2 : Enable IN endpoint 2 */
#define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
#define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */
#define USBD_EPINEN_IN2_Disable (0x0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
#define USBD_EPINEN_IN2_Enable (0x1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */

/* Bit 1 : Enable IN endpoint 1 */
#define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */
#define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */
#define USBD_EPINEN_IN1_Disable (0x0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
#define USBD_EPINEN_IN1_Enable (0x1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */

/* Bit 0 : Enable IN endpoint 0 */
#define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */
#define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */
#define USBD_EPINEN_IN0_Disable (0x0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
#define USBD_EPINEN_IN0_Enable (0x1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */

/* Register: USBD_EPOUTEN */
/* Description: Endpoint OUT enable */

/* Bit 8 : Enable ISO OUT endpoint 8 */
#define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */
#define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */
#define USBD_EPOUTEN_ISOOUT_Disable (0x0UL) /*!< Disable ISO OUT endpoint 8 */
#define USBD_EPOUTEN_ISOOUT_Enable (0x1UL) /*!< Enable ISO OUT endpoint 8 */

/* Bit 7 : Enable OUT endpoint 7 */
#define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */
#define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */
#define USBD_EPOUTEN_OUT7_Disable (0x0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
#define USBD_EPOUTEN_OUT7_Enable (0x1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */

/* Bit 6 : Enable OUT endpoint 6 */
#define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */
#define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */
#define USBD_EPOUTEN_OUT6_Disable (0x0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
#define USBD_EPOUTEN_OUT6_Enable (0x1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */

/* Bit 5 : Enable OUT endpoint 5 */
#define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */
#define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */
#define USBD_EPOUTEN_OUT5_Disable (0x0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
#define USBD_EPOUTEN_OUT5_Enable (0x1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */

/* Bit 4 : Enable OUT endpoint 4 */
#define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */
#define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */
#define USBD_EPOUTEN_OUT4_Disable (0x0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
#define USBD_EPOUTEN_OUT4_Enable (0x1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */

/* Bit 3 : Enable OUT endpoint 3 */
#define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */
#define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */
#define USBD_EPOUTEN_OUT3_Disable (0x0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
#define USBD_EPOUTEN_OUT3_Enable (0x1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */

/* Bit 2 : Enable OUT endpoint 2 */
#define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
#define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */
#define USBD_EPOUTEN_OUT2_Disable (0x0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
#define USBD_EPOUTEN_OUT2_Enable (0x1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */

/* Bit 1 : Enable OUT endpoint 1 */
#define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */
#define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */
#define USBD_EPOUTEN_OUT1_Disable (0x0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
#define USBD_EPOUTEN_OUT1_Enable (0x1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */

/* Bit 0 : Enable OUT endpoint 0 */
#define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */
#define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */
#define USBD_EPOUTEN_OUT0_Disable (0x0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
#define USBD_EPOUTEN_OUT0_Enable (0x1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */

/* Register: USBD_EPSTALL */
/* Description: STALL endpoints */

/* Bit 8 : Stall selected endpoint */
#define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */
#define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */
#define USBD_EPSTALL_STALL_UnStall (0x0UL) /*!< Don't stall selected endpoint */
#define USBD_EPSTALL_STALL_Stall (0x1UL) /*!< Stall selected endpoint */

/* Bit 7 : Selects IN or OUT endpoint */
#define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */
#define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */
#define USBD_EPSTALL_IO_Out (0x0UL) /*!< Selects OUT endpoint */
#define USBD_EPSTALL_IO_In (0x1UL) /*!< Selects IN endpoint */

/* Bits 2..0 : Select endpoint number */
#define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */
#define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */

/* Register: USBD_ISOSPLIT */
/* Description: Controls the split of ISO buffers */

/* Bits 15..0 : Controls the split of ISO buffers */
#define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */
#define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */
#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */
#define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */

/* Register: USBD_FRAMECNTR */
/* Description: Returns the current value of the start of frame counter */

/* Bits 10..0 : Returns the current value of the start of frame counter */
#define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */
#define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */

/* Register: USBD_LOWPOWER */
/* Description: Controls USBD peripheral Low-power mode during USB suspend */

/* Bit 0 : Controls USBD peripheral Low-power mode during USB suspend */
#define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */
#define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */
#define USBD_LOWPOWER_LOWPOWER_ForceNormal (0x0UL) /*!< Software must write this value to exit Low-power mode and before performing a remote wake-up */
#define USBD_LOWPOWER_LOWPOWER_LowPower (0x1UL) /*!< Software must write this value to enter Low-power mode after DMA and software have finished interacting with the USB peripheral */

/* Register: USBD_ISOINCONFIG */
/* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */

/* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
#define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */
#define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */
#define USBD_ISOINCONFIG_RESPONSE_NoResp (0x0UL) /*!< Endpoint does not respond in that case */
#define USBD_ISOINCONFIG_RESPONSE_ZeroData (0x1UL) /*!< Endpoint responds with a zero-length data packet in that case */

/* Register: USBD_EPIN_PTR */
/* Description: Description cluster: Data pointer */

/* Bits 31..0 : Data pointer */
#define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: USBD_EPIN_MAXCNT */
/* Description: Description cluster: Maximum number of bytes to transfer */

/* Bits 6..0 : Maximum number of bytes to transfer */
#define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: USBD_EPIN_AMOUNT */
/* Description: Description cluster: Number of bytes transferred in the last transaction */

/* Bits 6..0 : Number of bytes transferred in the last transaction */
#define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: USBD_ISOIN_PTR */
/* Description: Data pointer */

/* Bits 31..0 : Data pointer */
#define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: USBD_ISOIN_MAXCNT */
/* Description: Maximum number of bytes to transfer */

/* Bits 9..0 : Maximum number of bytes to transfer */
#define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: USBD_ISOIN_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */

/* Bits 9..0 : Number of bytes transferred in the last transaction */
#define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: USBD_EPOUT_PTR */
/* Description: Description cluster: Data pointer */

/* Bits 31..0 : Data pointer */
#define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: USBD_EPOUT_MAXCNT */
/* Description: Description cluster: Maximum number of bytes to transfer */

/* Bits 6..0 : Maximum number of bytes to transfer */
#define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: USBD_EPOUT_AMOUNT */
/* Description: Description cluster: Number of bytes transferred in the last transaction */

/* Bits 6..0 : Number of bytes transferred in the last transaction */
#define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */

/* Register: USBD_ISOOUT_PTR */
/* Description: Data pointer */

/* Bits 31..0 : Data pointer */
#define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
#define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */

/* Register: USBD_ISOOUT_MAXCNT */
/* Description: Maximum number of bytes to transfer */

/* Bits 9..0 : Maximum number of bytes to transfer */
#define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */

/* Register: USBD_ISOOUT_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */

/* Bits 9..0 : Number of bytes transferred in the last transaction */
#define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */


/* Peripheral: USBREG */
/* Description: USB Regulator 0 */

/* Register: USBREG_EVENTS_USBDETECTED */
/* Description: Voltage supply detected on VBUS */

/* Bit 0 : Voltage supply detected on VBUS */
#define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */
#define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */
#define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0x0UL) /*!< Event not generated */
#define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (0x1UL) /*!< Event generated */

/* Register: USBREG_EVENTS_USBREMOVED */
/* Description: Voltage supply removed from VBUS */

/* Bit 0 : Voltage supply removed from VBUS */
#define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */
#define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */
#define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0x0UL) /*!< Event not generated */
#define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (0x1UL) /*!< Event generated */

/* Register: USBREG_EVENTS_USBPWRRDY */
/* Description: USB 3.3 V supply ready */

/* Bit 0 : USB 3.3 V supply ready */
#define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */
#define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */
#define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0x0UL) /*!< Event not generated */
#define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (0x1UL) /*!< Event generated */

/* Register: USBREG_PUBLISH_USBDETECTED */
/* Description: Publish configuration for event USBDETECTED */

/* Bit 31 :   */
#define USBREG_PUBLISH_USBDETECTED_EN_Pos (31UL) /*!< Position of EN field. */
#define USBREG_PUBLISH_USBDETECTED_EN_Msk (0x1UL << USBREG_PUBLISH_USBDETECTED_EN_Pos) /*!< Bit mask of EN field. */
#define USBREG_PUBLISH_USBDETECTED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBREG_PUBLISH_USBDETECTED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event USBDETECTED will publish to */
#define USBREG_PUBLISH_USBDETECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBREG_PUBLISH_USBDETECTED_CHIDX_Msk (0xFFUL << USBREG_PUBLISH_USBDETECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBREG_PUBLISH_USBREMOVED */
/* Description: Publish configuration for event USBREMOVED */

/* Bit 31 :   */
#define USBREG_PUBLISH_USBREMOVED_EN_Pos (31UL) /*!< Position of EN field. */
#define USBREG_PUBLISH_USBREMOVED_EN_Msk (0x1UL << USBREG_PUBLISH_USBREMOVED_EN_Pos) /*!< Bit mask of EN field. */
#define USBREG_PUBLISH_USBREMOVED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBREG_PUBLISH_USBREMOVED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event USBREMOVED will publish to */
#define USBREG_PUBLISH_USBREMOVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBREG_PUBLISH_USBREMOVED_CHIDX_Msk (0xFFUL << USBREG_PUBLISH_USBREMOVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBREG_PUBLISH_USBPWRRDY */
/* Description: Publish configuration for event USBPWRRDY */

/* Bit 31 :   */
#define USBREG_PUBLISH_USBPWRRDY_EN_Pos (31UL) /*!< Position of EN field. */
#define USBREG_PUBLISH_USBPWRRDY_EN_Msk (0x1UL << USBREG_PUBLISH_USBPWRRDY_EN_Pos) /*!< Bit mask of EN field. */
#define USBREG_PUBLISH_USBPWRRDY_EN_Disabled (0x0UL) /*!< Disable publishing */
#define USBREG_PUBLISH_USBPWRRDY_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event USBPWRRDY will publish to */
#define USBREG_PUBLISH_USBPWRRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define USBREG_PUBLISH_USBPWRRDY_CHIDX_Msk (0xFFUL << USBREG_PUBLISH_USBPWRRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: USBREG_INTEN */
/* Description: Enable or disable interrupt */

/* Bit 2 : Enable or disable interrupt for event USBPWRRDY */
#define USBREG_INTEN_USBPWRRDY_Pos (2UL) /*!< Position of USBPWRRDY field. */
#define USBREG_INTEN_USBPWRRDY_Msk (0x1UL << USBREG_INTEN_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
#define USBREG_INTEN_USBPWRRDY_Disabled (0x0UL) /*!< Disable */
#define USBREG_INTEN_USBPWRRDY_Enabled (0x1UL) /*!< Enable */

/* Bit 1 : Enable or disable interrupt for event USBREMOVED */
#define USBREG_INTEN_USBREMOVED_Pos (1UL) /*!< Position of USBREMOVED field. */
#define USBREG_INTEN_USBREMOVED_Msk (0x1UL << USBREG_INTEN_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
#define USBREG_INTEN_USBREMOVED_Disabled (0x0UL) /*!< Disable */
#define USBREG_INTEN_USBREMOVED_Enabled (0x1UL) /*!< Enable */

/* Bit 0 : Enable or disable interrupt for event USBDETECTED */
#define USBREG_INTEN_USBDETECTED_Pos (0UL) /*!< Position of USBDETECTED field. */
#define USBREG_INTEN_USBDETECTED_Msk (0x1UL << USBREG_INTEN_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
#define USBREG_INTEN_USBDETECTED_Disabled (0x0UL) /*!< Disable */
#define USBREG_INTEN_USBDETECTED_Enabled (0x1UL) /*!< Enable */

/* Register: USBREG_INTENSET */
/* Description: Enable interrupt */

/* Bit 2 : Write '1' to enable interrupt for event USBPWRRDY */
#define USBREG_INTENSET_USBPWRRDY_Pos (2UL) /*!< Position of USBPWRRDY field. */
#define USBREG_INTENSET_USBPWRRDY_Msk (0x1UL << USBREG_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
#define USBREG_INTENSET_USBPWRRDY_Disabled (0x0UL) /*!< Read: Disabled */
#define USBREG_INTENSET_USBPWRRDY_Enabled (0x1UL) /*!< Read: Enabled */
#define USBREG_INTENSET_USBPWRRDY_Set (0x1UL) /*!< Enable */

/* Bit 1 : Write '1' to enable interrupt for event USBREMOVED */
#define USBREG_INTENSET_USBREMOVED_Pos (1UL) /*!< Position of USBREMOVED field. */
#define USBREG_INTENSET_USBREMOVED_Msk (0x1UL << USBREG_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
#define USBREG_INTENSET_USBREMOVED_Disabled (0x0UL) /*!< Read: Disabled */
#define USBREG_INTENSET_USBREMOVED_Enabled (0x1UL) /*!< Read: Enabled */
#define USBREG_INTENSET_USBREMOVED_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event USBDETECTED */
#define USBREG_INTENSET_USBDETECTED_Pos (0UL) /*!< Position of USBDETECTED field. */
#define USBREG_INTENSET_USBDETECTED_Msk (0x1UL << USBREG_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
#define USBREG_INTENSET_USBDETECTED_Disabled (0x0UL) /*!< Read: Disabled */
#define USBREG_INTENSET_USBDETECTED_Enabled (0x1UL) /*!< Read: Enabled */
#define USBREG_INTENSET_USBDETECTED_Set (0x1UL) /*!< Enable */

/* Register: USBREG_INTENCLR */
/* Description: Disable interrupt */

/* Bit 2 : Write '1' to disable interrupt for event USBPWRRDY */
#define USBREG_INTENCLR_USBPWRRDY_Pos (2UL) /*!< Position of USBPWRRDY field. */
#define USBREG_INTENCLR_USBPWRRDY_Msk (0x1UL << USBREG_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
#define USBREG_INTENCLR_USBPWRRDY_Disabled (0x0UL) /*!< Read: Disabled */
#define USBREG_INTENCLR_USBPWRRDY_Enabled (0x1UL) /*!< Read: Enabled */
#define USBREG_INTENCLR_USBPWRRDY_Clear (0x1UL) /*!< Disable */

/* Bit 1 : Write '1' to disable interrupt for event USBREMOVED */
#define USBREG_INTENCLR_USBREMOVED_Pos (1UL) /*!< Position of USBREMOVED field. */
#define USBREG_INTENCLR_USBREMOVED_Msk (0x1UL << USBREG_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
#define USBREG_INTENCLR_USBREMOVED_Disabled (0x0UL) /*!< Read: Disabled */
#define USBREG_INTENCLR_USBREMOVED_Enabled (0x1UL) /*!< Read: Enabled */
#define USBREG_INTENCLR_USBREMOVED_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event USBDETECTED */
#define USBREG_INTENCLR_USBDETECTED_Pos (0UL) /*!< Position of USBDETECTED field. */
#define USBREG_INTENCLR_USBDETECTED_Msk (0x1UL << USBREG_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
#define USBREG_INTENCLR_USBDETECTED_Disabled (0x0UL) /*!< Read: Disabled */
#define USBREG_INTENCLR_USBDETECTED_Enabled (0x1UL) /*!< Read: Enabled */
#define USBREG_INTENCLR_USBDETECTED_Clear (0x1UL) /*!< Disable */

/* Register: USBREG_USBREGSTATUS */
/* Description: USB supply status */

/* Bit 1 : USB supply output settling time elapsed */
#define USBREG_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */
#define USBREG_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << USBREG_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */
#define USBREG_USBREGSTATUS_OUTPUTRDY_NotReady (0x0UL) /*!< USBREG output settling time not elapsed */
#define USBREG_USBREGSTATUS_OUTPUTRDY_Ready (0x1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */

/* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */
#define USBREG_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */
#define USBREG_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << USBREG_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */
#define USBREG_USBREGSTATUS_VBUSDETECT_NoVbus (0x0UL) /*!< VBUS voltage below valid threshold */
#define USBREG_USBREGSTATUS_VBUSDETECT_VbusPresent (0x1UL) /*!< VBUS voltage above valid threshold */


/* Peripheral: VMC */
/* Description: Volatile Memory controller 0 */

/* Register: VMC_RAM_POWER */
/* Description: Description cluster: RAM[n] power control register */

/* Bit 31 : Keep retention on RAM section S15 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
#define VMC_RAM_POWER_S15RETENTION_Msk (0x1UL << VMC_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
#define VMC_RAM_POWER_S15RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S15RETENTION_On (0x1UL) /*!< On */

/* Bit 30 : Keep retention on RAM section S14 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
#define VMC_RAM_POWER_S14RETENTION_Msk (0x1UL << VMC_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
#define VMC_RAM_POWER_S14RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S14RETENTION_On (0x1UL) /*!< On */

/* Bit 29 : Keep retention on RAM section S13 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
#define VMC_RAM_POWER_S13RETENTION_Msk (0x1UL << VMC_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
#define VMC_RAM_POWER_S13RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S13RETENTION_On (0x1UL) /*!< On */

/* Bit 28 : Keep retention on RAM section S12 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
#define VMC_RAM_POWER_S12RETENTION_Msk (0x1UL << VMC_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
#define VMC_RAM_POWER_S12RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S12RETENTION_On (0x1UL) /*!< On */

/* Bit 27 : Keep retention on RAM section S11 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
#define VMC_RAM_POWER_S11RETENTION_Msk (0x1UL << VMC_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
#define VMC_RAM_POWER_S11RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S11RETENTION_On (0x1UL) /*!< On */

/* Bit 26 : Keep retention on RAM section S10 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
#define VMC_RAM_POWER_S10RETENTION_Msk (0x1UL << VMC_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
#define VMC_RAM_POWER_S10RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S10RETENTION_On (0x1UL) /*!< On */

/* Bit 25 : Keep retention on RAM section S9 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
#define VMC_RAM_POWER_S9RETENTION_Msk (0x1UL << VMC_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
#define VMC_RAM_POWER_S9RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S9RETENTION_On (0x1UL) /*!< On */

/* Bit 24 : Keep retention on RAM section S8 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
#define VMC_RAM_POWER_S8RETENTION_Msk (0x1UL << VMC_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
#define VMC_RAM_POWER_S8RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S8RETENTION_On (0x1UL) /*!< On */

/* Bit 23 : Keep retention on RAM section S7 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
#define VMC_RAM_POWER_S7RETENTION_Msk (0x1UL << VMC_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
#define VMC_RAM_POWER_S7RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S7RETENTION_On (0x1UL) /*!< On */

/* Bit 22 : Keep retention on RAM section S6 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
#define VMC_RAM_POWER_S6RETENTION_Msk (0x1UL << VMC_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
#define VMC_RAM_POWER_S6RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S6RETENTION_On (0x1UL) /*!< On */

/* Bit 21 : Keep retention on RAM section S5 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
#define VMC_RAM_POWER_S5RETENTION_Msk (0x1UL << VMC_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
#define VMC_RAM_POWER_S5RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S5RETENTION_On (0x1UL) /*!< On */

/* Bit 20 : Keep retention on RAM section S4 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
#define VMC_RAM_POWER_S4RETENTION_Msk (0x1UL << VMC_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
#define VMC_RAM_POWER_S4RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S4RETENTION_On (0x1UL) /*!< On */

/* Bit 19 : Keep retention on RAM section S3 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
#define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
#define VMC_RAM_POWER_S3RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S3RETENTION_On (0x1UL) /*!< On */

/* Bit 18 : Keep retention on RAM section S2 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
#define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
#define VMC_RAM_POWER_S2RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S2RETENTION_On (0x1UL) /*!< On */

/* Bit 17 : Keep retention on RAM section S1 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
#define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
#define VMC_RAM_POWER_S1RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S1RETENTION_On (0x1UL) /*!< On */

/* Bit 16 : Keep retention on RAM section S0 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
#define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define VMC_RAM_POWER_S0RETENTION_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S0RETENTION_On (0x1UL) /*!< On */

/* Bit 15 : Keep RAM section S15 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
#define VMC_RAM_POWER_S15POWER_Msk (0x1UL << VMC_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
#define VMC_RAM_POWER_S15POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S15POWER_On (0x1UL) /*!< On */

/* Bit 14 : Keep RAM section S14 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
#define VMC_RAM_POWER_S14POWER_Msk (0x1UL << VMC_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
#define VMC_RAM_POWER_S14POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S14POWER_On (0x1UL) /*!< On */

/* Bit 13 : Keep RAM section S13 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
#define VMC_RAM_POWER_S13POWER_Msk (0x1UL << VMC_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
#define VMC_RAM_POWER_S13POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S13POWER_On (0x1UL) /*!< On */

/* Bit 12 : Keep RAM section S12 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
#define VMC_RAM_POWER_S12POWER_Msk (0x1UL << VMC_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
#define VMC_RAM_POWER_S12POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S12POWER_On (0x1UL) /*!< On */

/* Bit 11 : Keep RAM section S11 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
#define VMC_RAM_POWER_S11POWER_Msk (0x1UL << VMC_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
#define VMC_RAM_POWER_S11POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S11POWER_On (0x1UL) /*!< On */

/* Bit 10 : Keep RAM section S10 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
#define VMC_RAM_POWER_S10POWER_Msk (0x1UL << VMC_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
#define VMC_RAM_POWER_S10POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S10POWER_On (0x1UL) /*!< On */

/* Bit 9 : Keep RAM section S9 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
#define VMC_RAM_POWER_S9POWER_Msk (0x1UL << VMC_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
#define VMC_RAM_POWER_S9POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S9POWER_On (0x1UL) /*!< On */

/* Bit 8 : Keep RAM section S8 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
#define VMC_RAM_POWER_S8POWER_Msk (0x1UL << VMC_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
#define VMC_RAM_POWER_S8POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S8POWER_On (0x1UL) /*!< On */

/* Bit 7 : Keep RAM section S7 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
#define VMC_RAM_POWER_S7POWER_Msk (0x1UL << VMC_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
#define VMC_RAM_POWER_S7POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S7POWER_On (0x1UL) /*!< On */

/* Bit 6 : Keep RAM section S6 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
#define VMC_RAM_POWER_S6POWER_Msk (0x1UL << VMC_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
#define VMC_RAM_POWER_S6POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S6POWER_On (0x1UL) /*!< On */

/* Bit 5 : Keep RAM section S5 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
#define VMC_RAM_POWER_S5POWER_Msk (0x1UL << VMC_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
#define VMC_RAM_POWER_S5POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S5POWER_On (0x1UL) /*!< On */

/* Bit 4 : Keep RAM section S4 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
#define VMC_RAM_POWER_S4POWER_Msk (0x1UL << VMC_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
#define VMC_RAM_POWER_S4POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S4POWER_On (0x1UL) /*!< On */

/* Bit 3 : Keep RAM section S3 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
#define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
#define VMC_RAM_POWER_S3POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S3POWER_On (0x1UL) /*!< On */

/* Bit 2 : Keep RAM section S2 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
#define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
#define VMC_RAM_POWER_S2POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S2POWER_On (0x1UL) /*!< On */

/* Bit 1 : Keep RAM section S1 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define VMC_RAM_POWER_S1POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S1POWER_On (0x1UL) /*!< On */

/* Bit 0 : Keep RAM section S0 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define VMC_RAM_POWER_S0POWER_Off (0x0UL) /*!< Off */
#define VMC_RAM_POWER_S0POWER_On (0x1UL) /*!< On */

/* Register: VMC_RAM_POWERSET */
/* Description: Description cluster: RAM[n] power control set register */

/* Bit 31 : Keep retention on RAM section S15 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
#define VMC_RAM_POWERSET_S15RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
#define VMC_RAM_POWERSET_S15RETENTION_On (0x1UL) /*!< On */

/* Bit 30 : Keep retention on RAM section S14 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
#define VMC_RAM_POWERSET_S14RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
#define VMC_RAM_POWERSET_S14RETENTION_On (0x1UL) /*!< On */

/* Bit 29 : Keep retention on RAM section S13 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
#define VMC_RAM_POWERSET_S13RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
#define VMC_RAM_POWERSET_S13RETENTION_On (0x1UL) /*!< On */

/* Bit 28 : Keep retention on RAM section S12 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
#define VMC_RAM_POWERSET_S12RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
#define VMC_RAM_POWERSET_S12RETENTION_On (0x1UL) /*!< On */

/* Bit 27 : Keep retention on RAM section S11 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
#define VMC_RAM_POWERSET_S11RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
#define VMC_RAM_POWERSET_S11RETENTION_On (0x1UL) /*!< On */

/* Bit 26 : Keep retention on RAM section S10 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
#define VMC_RAM_POWERSET_S10RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
#define VMC_RAM_POWERSET_S10RETENTION_On (0x1UL) /*!< On */

/* Bit 25 : Keep retention on RAM section S9 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
#define VMC_RAM_POWERSET_S9RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
#define VMC_RAM_POWERSET_S9RETENTION_On (0x1UL) /*!< On */

/* Bit 24 : Keep retention on RAM section S8 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
#define VMC_RAM_POWERSET_S8RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
#define VMC_RAM_POWERSET_S8RETENTION_On (0x1UL) /*!< On */

/* Bit 23 : Keep retention on RAM section S7 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
#define VMC_RAM_POWERSET_S7RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
#define VMC_RAM_POWERSET_S7RETENTION_On (0x1UL) /*!< On */

/* Bit 22 : Keep retention on RAM section S6 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
#define VMC_RAM_POWERSET_S6RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
#define VMC_RAM_POWERSET_S6RETENTION_On (0x1UL) /*!< On */

/* Bit 21 : Keep retention on RAM section S5 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
#define VMC_RAM_POWERSET_S5RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
#define VMC_RAM_POWERSET_S5RETENTION_On (0x1UL) /*!< On */

/* Bit 20 : Keep retention on RAM section S4 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
#define VMC_RAM_POWERSET_S4RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
#define VMC_RAM_POWERSET_S4RETENTION_On (0x1UL) /*!< On */

/* Bit 19 : Keep retention on RAM section S3 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
#define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
#define VMC_RAM_POWERSET_S3RETENTION_On (0x1UL) /*!< On */

/* Bit 18 : Keep retention on RAM section S2 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
#define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
#define VMC_RAM_POWERSET_S2RETENTION_On (0x1UL) /*!< On */

/* Bit 17 : Keep retention on RAM section S1 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
#define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
#define VMC_RAM_POWERSET_S1RETENTION_On (0x1UL) /*!< On */

/* Bit 16 : Keep retention on RAM section S0 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
#define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define VMC_RAM_POWERSET_S0RETENTION_On (0x1UL) /*!< On */

/* Bit 15 : Keep RAM section S15 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
#define VMC_RAM_POWERSET_S15POWER_Msk (0x1UL << VMC_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
#define VMC_RAM_POWERSET_S15POWER_On (0x1UL) /*!< On */

/* Bit 14 : Keep RAM section S14 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
#define VMC_RAM_POWERSET_S14POWER_Msk (0x1UL << VMC_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
#define VMC_RAM_POWERSET_S14POWER_On (0x1UL) /*!< On */

/* Bit 13 : Keep RAM section S13 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
#define VMC_RAM_POWERSET_S13POWER_Msk (0x1UL << VMC_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
#define VMC_RAM_POWERSET_S13POWER_On (0x1UL) /*!< On */

/* Bit 12 : Keep RAM section S12 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
#define VMC_RAM_POWERSET_S12POWER_Msk (0x1UL << VMC_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
#define VMC_RAM_POWERSET_S12POWER_On (0x1UL) /*!< On */

/* Bit 11 : Keep RAM section S11 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
#define VMC_RAM_POWERSET_S11POWER_Msk (0x1UL << VMC_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
#define VMC_RAM_POWERSET_S11POWER_On (0x1UL) /*!< On */

/* Bit 10 : Keep RAM section S10 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
#define VMC_RAM_POWERSET_S10POWER_Msk (0x1UL << VMC_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
#define VMC_RAM_POWERSET_S10POWER_On (0x1UL) /*!< On */

/* Bit 9 : Keep RAM section S9 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
#define VMC_RAM_POWERSET_S9POWER_Msk (0x1UL << VMC_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
#define VMC_RAM_POWERSET_S9POWER_On (0x1UL) /*!< On */

/* Bit 8 : Keep RAM section S8 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
#define VMC_RAM_POWERSET_S8POWER_Msk (0x1UL << VMC_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
#define VMC_RAM_POWERSET_S8POWER_On (0x1UL) /*!< On */

/* Bit 7 : Keep RAM section S7 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
#define VMC_RAM_POWERSET_S7POWER_Msk (0x1UL << VMC_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
#define VMC_RAM_POWERSET_S7POWER_On (0x1UL) /*!< On */

/* Bit 6 : Keep RAM section S6 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
#define VMC_RAM_POWERSET_S6POWER_Msk (0x1UL << VMC_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
#define VMC_RAM_POWERSET_S6POWER_On (0x1UL) /*!< On */

/* Bit 5 : Keep RAM section S5 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
#define VMC_RAM_POWERSET_S5POWER_Msk (0x1UL << VMC_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
#define VMC_RAM_POWERSET_S5POWER_On (0x1UL) /*!< On */

/* Bit 4 : Keep RAM section S4 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
#define VMC_RAM_POWERSET_S4POWER_Msk (0x1UL << VMC_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
#define VMC_RAM_POWERSET_S4POWER_On (0x1UL) /*!< On */

/* Bit 3 : Keep RAM section S3 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
#define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
#define VMC_RAM_POWERSET_S3POWER_On (0x1UL) /*!< On */

/* Bit 2 : Keep RAM section S2 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
#define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
#define VMC_RAM_POWERSET_S2POWER_On (0x1UL) /*!< On */

/* Bit 1 : Keep RAM section S1 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define VMC_RAM_POWERSET_S1POWER_On (0x1UL) /*!< On */

/* Bit 0 : Keep RAM section S0 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define VMC_RAM_POWERSET_S0POWER_On (0x1UL) /*!< On */

/* Register: VMC_RAM_POWERCLR */
/* Description: Description cluster: RAM[n] power control clear register */

/* Bit 31 : Keep retention on RAM section S15 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
#define VMC_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
#define VMC_RAM_POWERCLR_S15RETENTION_Off (0x1UL) /*!< Off */

/* Bit 30 : Keep retention on RAM section S14 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
#define VMC_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
#define VMC_RAM_POWERCLR_S14RETENTION_Off (0x1UL) /*!< Off */

/* Bit 29 : Keep retention on RAM section S13 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
#define VMC_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
#define VMC_RAM_POWERCLR_S13RETENTION_Off (0x1UL) /*!< Off */

/* Bit 28 : Keep retention on RAM section S12 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
#define VMC_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
#define VMC_RAM_POWERCLR_S12RETENTION_Off (0x1UL) /*!< Off */

/* Bit 27 : Keep retention on RAM section S11 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
#define VMC_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
#define VMC_RAM_POWERCLR_S11RETENTION_Off (0x1UL) /*!< Off */

/* Bit 26 : Keep retention on RAM section S10 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
#define VMC_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
#define VMC_RAM_POWERCLR_S10RETENTION_Off (0x1UL) /*!< Off */

/* Bit 25 : Keep retention on RAM section S9 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
#define VMC_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
#define VMC_RAM_POWERCLR_S9RETENTION_Off (0x1UL) /*!< Off */

/* Bit 24 : Keep retention on RAM section S8 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
#define VMC_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
#define VMC_RAM_POWERCLR_S8RETENTION_Off (0x1UL) /*!< Off */

/* Bit 23 : Keep retention on RAM section S7 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
#define VMC_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
#define VMC_RAM_POWERCLR_S7RETENTION_Off (0x1UL) /*!< Off */

/* Bit 22 : Keep retention on RAM section S6 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
#define VMC_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
#define VMC_RAM_POWERCLR_S6RETENTION_Off (0x1UL) /*!< Off */

/* Bit 21 : Keep retention on RAM section S5 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
#define VMC_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
#define VMC_RAM_POWERCLR_S5RETENTION_Off (0x1UL) /*!< Off */

/* Bit 20 : Keep retention on RAM section S4 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
#define VMC_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
#define VMC_RAM_POWERCLR_S4RETENTION_Off (0x1UL) /*!< Off */

/* Bit 19 : Keep retention on RAM section S3 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
#define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
#define VMC_RAM_POWERCLR_S3RETENTION_Off (0x1UL) /*!< Off */

/* Bit 18 : Keep retention on RAM section S2 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
#define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
#define VMC_RAM_POWERCLR_S2RETENTION_Off (0x1UL) /*!< Off */

/* Bit 17 : Keep retention on RAM section S1 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
#define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
#define VMC_RAM_POWERCLR_S1RETENTION_Off (0x1UL) /*!< Off */

/* Bit 16 : Keep retention on RAM section S0 of RAM[n] when RAM section is switched off */
#define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
#define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
#define VMC_RAM_POWERCLR_S0RETENTION_Off (0x1UL) /*!< Off */

/* Bit 15 : Keep RAM section S15 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
#define VMC_RAM_POWERCLR_S15POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
#define VMC_RAM_POWERCLR_S15POWER_Off (0x1UL) /*!< Off */

/* Bit 14 : Keep RAM section S14 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
#define VMC_RAM_POWERCLR_S14POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
#define VMC_RAM_POWERCLR_S14POWER_Off (0x1UL) /*!< Off */

/* Bit 13 : Keep RAM section S13 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
#define VMC_RAM_POWERCLR_S13POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
#define VMC_RAM_POWERCLR_S13POWER_Off (0x1UL) /*!< Off */

/* Bit 12 : Keep RAM section S12 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
#define VMC_RAM_POWERCLR_S12POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
#define VMC_RAM_POWERCLR_S12POWER_Off (0x1UL) /*!< Off */

/* Bit 11 : Keep RAM section S11 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
#define VMC_RAM_POWERCLR_S11POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
#define VMC_RAM_POWERCLR_S11POWER_Off (0x1UL) /*!< Off */

/* Bit 10 : Keep RAM section S10 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
#define VMC_RAM_POWERCLR_S10POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
#define VMC_RAM_POWERCLR_S10POWER_Off (0x1UL) /*!< Off */

/* Bit 9 : Keep RAM section S9 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
#define VMC_RAM_POWERCLR_S9POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
#define VMC_RAM_POWERCLR_S9POWER_Off (0x1UL) /*!< Off */

/* Bit 8 : Keep RAM section S8 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
#define VMC_RAM_POWERCLR_S8POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
#define VMC_RAM_POWERCLR_S8POWER_Off (0x1UL) /*!< Off */

/* Bit 7 : Keep RAM section S7 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
#define VMC_RAM_POWERCLR_S7POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
#define VMC_RAM_POWERCLR_S7POWER_Off (0x1UL) /*!< Off */

/* Bit 6 : Keep RAM section S6 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
#define VMC_RAM_POWERCLR_S6POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
#define VMC_RAM_POWERCLR_S6POWER_Off (0x1UL) /*!< Off */

/* Bit 5 : Keep RAM section S5 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
#define VMC_RAM_POWERCLR_S5POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
#define VMC_RAM_POWERCLR_S5POWER_Off (0x1UL) /*!< Off */

/* Bit 4 : Keep RAM section S4 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
#define VMC_RAM_POWERCLR_S4POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
#define VMC_RAM_POWERCLR_S4POWER_Off (0x1UL) /*!< Off */

/* Bit 3 : Keep RAM section S3 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
#define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
#define VMC_RAM_POWERCLR_S3POWER_Off (0x1UL) /*!< Off */

/* Bit 2 : Keep RAM section S2 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
#define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
#define VMC_RAM_POWERCLR_S2POWER_Off (0x1UL) /*!< Off */

/* Bit 1 : Keep RAM section S1 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
#define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
#define VMC_RAM_POWERCLR_S1POWER_Off (0x1UL) /*!< Off */

/* Bit 0 : Keep RAM section S0 of RAM[n] on or off in System ON mode */
#define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
#define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
#define VMC_RAM_POWERCLR_S0POWER_Off (0x1UL) /*!< Off */


/* Peripheral: WDT */
/* Description: Watchdog Timer 0 */

/* Register: WDT_TASKS_START */
/* Description: Start WDT */

/* Bit 0 : Start WDT */
#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
#define WDT_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */

/* Register: WDT_TASKS_STOP */
/* Description: Stop WDT */

/* Bit 0 : Stop WDT */
#define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
#define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
#define WDT_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */

/* Register: WDT_SUBSCRIBE_START */
/* Description: Subscribe configuration for task START */

/* Bit 31 :   */
#define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
#define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
#define WDT_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */
#define WDT_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task START will subscribe to */
#define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: WDT_SUBSCRIBE_STOP */
/* Description: Subscribe configuration for task STOP */

/* Bit 31 :   */
#define WDT_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
#define WDT_SUBSCRIBE_STOP_EN_Msk (0x1UL << WDT_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
#define WDT_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */
#define WDT_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */

/* Bits 7..0 : DPPI channel that task STOP will subscribe to */
#define WDT_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define WDT_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: WDT_EVENTS_TIMEOUT */
/* Description: Watchdog timeout */

/* Bit 0 : Watchdog timeout */
#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0x0UL) /*!< Event not generated */
#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (0x1UL) /*!< Event generated */

/* Register: WDT_EVENTS_STOPPED */
/* Description: Watchdog stopped */

/* Bit 0 : Watchdog stopped */
#define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
#define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
#define WDT_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */
#define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */

/* Register: WDT_PUBLISH_TIMEOUT */
/* Description: Publish configuration for event TIMEOUT */

/* Bit 31 :   */
#define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */
#define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */
#define WDT_PUBLISH_TIMEOUT_EN_Disabled (0x0UL) /*!< Disable publishing */
#define WDT_PUBLISH_TIMEOUT_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event TIMEOUT will publish to */
#define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: WDT_PUBLISH_STOPPED */
/* Description: Publish configuration for event STOPPED */

/* Bit 31 :   */
#define WDT_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
#define WDT_PUBLISH_STOPPED_EN_Msk (0x1UL << WDT_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
#define WDT_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */
#define WDT_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */

/* Bits 7..0 : DPPI channel that event STOPPED will publish to */
#define WDT_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
#define WDT_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << WDT_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */

/* Register: WDT_INTENSET */
/* Description: Enable interrupt */

/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define WDT_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define WDT_INTENSET_STOPPED_Msk (0x1UL << WDT_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define WDT_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define WDT_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define WDT_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
#define WDT_INTENSET_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */
#define WDT_INTENSET_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */
#define WDT_INTENSET_TIMEOUT_Set (0x1UL) /*!< Enable */

/* Register: WDT_INTENCLR */
/* Description: Disable interrupt */

/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define WDT_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define WDT_INTENCLR_STOPPED_Msk (0x1UL << WDT_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define WDT_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define WDT_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define WDT_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
#define WDT_INTENCLR_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */
#define WDT_INTENCLR_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */
#define WDT_INTENCLR_TIMEOUT_Clear (0x1UL) /*!< Disable */

/* Register: WDT_NMIENSET */
/* Description: Enable interrupt */

/* Bit 1 : Write '1' to enable interrupt for event STOPPED */
#define WDT_NMIENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define WDT_NMIENSET_STOPPED_Msk (0x1UL << WDT_NMIENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define WDT_NMIENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define WDT_NMIENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define WDT_NMIENSET_STOPPED_Set (0x1UL) /*!< Enable */

/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
#define WDT_NMIENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
#define WDT_NMIENSET_TIMEOUT_Msk (0x1UL << WDT_NMIENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
#define WDT_NMIENSET_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */
#define WDT_NMIENSET_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */
#define WDT_NMIENSET_TIMEOUT_Set (0x1UL) /*!< Enable */

/* Register: WDT_NMIENCLR */
/* Description: Disable interrupt */

/* Bit 1 : Write '1' to disable interrupt for event STOPPED */
#define WDT_NMIENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
#define WDT_NMIENCLR_STOPPED_Msk (0x1UL << WDT_NMIENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
#define WDT_NMIENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */
#define WDT_NMIENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */
#define WDT_NMIENCLR_STOPPED_Clear (0x1UL) /*!< Disable */

/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
#define WDT_NMIENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
#define WDT_NMIENCLR_TIMEOUT_Msk (0x1UL << WDT_NMIENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
#define WDT_NMIENCLR_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */
#define WDT_NMIENCLR_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */
#define WDT_NMIENCLR_TIMEOUT_Clear (0x1UL) /*!< Disable */

/* Register: WDT_RUNSTATUS */
/* Description: Run status */

/* Bit 0 : Indicates whether or not WDT is running */
#define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */
#define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */
#define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0x0UL) /*!< Watchdog is not running */
#define WDT_RUNSTATUS_RUNSTATUSWDT_Running (0x1UL) /*!< Watchdog is running */

/* Register: WDT_REQSTATUS */
/* Description: Request status */

/* Bit 7 : Request status for RR[7] register */
#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
#define WDT_REQSTATUS_RR7_DisabledOrRequested (0x0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (0x1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */

/* Bit 6 : Request status for RR[6] register */
#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
#define WDT_REQSTATUS_RR6_DisabledOrRequested (0x0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (0x1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */

/* Bit 5 : Request status for RR[5] register */
#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
#define WDT_REQSTATUS_RR5_DisabledOrRequested (0x0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (0x1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */

/* Bit 4 : Request status for RR[4] register */
#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
#define WDT_REQSTATUS_RR4_DisabledOrRequested (0x0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (0x1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */

/* Bit 3 : Request status for RR[3] register */
#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
#define WDT_REQSTATUS_RR3_DisabledOrRequested (0x0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (0x1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */

/* Bit 2 : Request status for RR[2] register */
#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
#define WDT_REQSTATUS_RR2_DisabledOrRequested (0x0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (0x1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */

/* Bit 1 : Request status for RR[1] register */
#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
#define WDT_REQSTATUS_RR1_DisabledOrRequested (0x0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (0x1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */

/* Bit 0 : Request status for RR[0] register */
#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
#define WDT_REQSTATUS_RR0_DisabledOrRequested (0x0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (0x1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */

/* Register: WDT_CRV */
/* Description: Counter reload value */

/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */

/* Register: WDT_RREN */
/* Description: Enable register for reload request registers */

/* Bit 7 : Enable or disable RR[7] register */
#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
#define WDT_RREN_RR7_Disabled (0x0UL) /*!< Disable RR[7] register */
#define WDT_RREN_RR7_Enabled (0x1UL) /*!< Enable RR[7] register */

/* Bit 6 : Enable or disable RR[6] register */
#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
#define WDT_RREN_RR6_Disabled (0x0UL) /*!< Disable RR[6] register */
#define WDT_RREN_RR6_Enabled (0x1UL) /*!< Enable RR[6] register */

/* Bit 5 : Enable or disable RR[5] register */
#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
#define WDT_RREN_RR5_Disabled (0x0UL) /*!< Disable RR[5] register */
#define WDT_RREN_RR5_Enabled (0x1UL) /*!< Enable RR[5] register */

/* Bit 4 : Enable or disable RR[4] register */
#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
#define WDT_RREN_RR4_Disabled (0x0UL) /*!< Disable RR[4] register */
#define WDT_RREN_RR4_Enabled (0x1UL) /*!< Enable RR[4] register */

/* Bit 3 : Enable or disable RR[3] register */
#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
#define WDT_RREN_RR3_Disabled (0x0UL) /*!< Disable RR[3] register */
#define WDT_RREN_RR3_Enabled (0x1UL) /*!< Enable RR[3] register */

/* Bit 2 : Enable or disable RR[2] register */
#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
#define WDT_RREN_RR2_Disabled (0x0UL) /*!< Disable RR[2] register */
#define WDT_RREN_RR2_Enabled (0x1UL) /*!< Enable RR[2] register */

/* Bit 1 : Enable or disable RR[1] register */
#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
#define WDT_RREN_RR1_Disabled (0x0UL) /*!< Disable RR[1] register */
#define WDT_RREN_RR1_Enabled (0x1UL) /*!< Enable RR[1] register */

/* Bit 0 : Enable or disable RR[0] register */
#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
#define WDT_RREN_RR0_Disabled (0x0UL) /*!< Disable RR[0] register */
#define WDT_RREN_RR0_Enabled (0x1UL) /*!< Enable RR[0] register */

/* Register: WDT_CONFIG */
/* Description: Configuration register */

/* Bit 6 : Allow stopping WDT */
#define WDT_CONFIG_STOPEN_Pos (6UL) /*!< Position of STOPEN field. */
#define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos) /*!< Bit mask of STOPEN field. */
#define WDT_CONFIG_STOPEN_Disable (0x0UL) /*!< Do not allow stopping WDT */
#define WDT_CONFIG_STOPEN_Enable (0x1UL) /*!< Allow stopping WDT */

/* Bit 3 : Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger */
#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
#define WDT_CONFIG_HALT_Pause (0x0UL) /*!< Pause WDT while the CPU is halted by the debugger */
#define WDT_CONFIG_HALT_Run (0x1UL) /*!< Keep WDT running while the CPU is halted by the debugger */

/* Bit 0 : Configure WDT to either be paused, or kept running, while the CPU is sleeping */
#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
#define WDT_CONFIG_SLEEP_Pause (0x0UL) /*!< Pause WDT while the CPU is sleeping */
#define WDT_CONFIG_SLEEP_Run (0x1UL) /*!< Keep WDT running while the CPU is sleeping */

/* Register: WDT_TSEN */
/* Description: Task stop enable */

/* Bits 31..0 : Allow stopping WDT */
#define WDT_TSEN_TSEN_Pos (0UL) /*!< Position of TSEN field. */
#define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos) /*!< Bit mask of TSEN field. */
#define WDT_TSEN_TSEN_Enable (0x6E524635UL) /*!< Value to allow stopping WDT */

/* Register: WDT_RR */
/* Description: Description collection: Reload request n */

/* Bits 31..0 : Reload request register */
#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */


/*lint --flb "Leave library region" */
#endif