1 /*
2 * Copyright (c) 2021 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRFY_PWM_H__
35 #define NRFY_PWM_H__
36
37 #include <nrfx.h>
38 #include <hal/nrf_pwm.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 NRFY_STATIC_INLINE bool __nrfy_internal_pwm_event_handle(NRF_PWM_Type * p_reg,
45 uint32_t mask,
46 nrf_pwm_event_t event,
47 uint32_t * p_evt_mask);
48
49 NRFY_STATIC_INLINE uint32_t __nrfy_internal_pwm_events_process(NRF_PWM_Type * p_reg, uint32_t mask);
50
51 NRFY_STATIC_INLINE void __nrfy_internal_pwm_event_enabled_clear(NRF_PWM_Type * p_reg,
52 uint32_t mask,
53 nrf_pwm_event_t event);
54
55 /**
56 * @defgroup nrfy_pwm PWM HALY
57 * @{
58 * @ingroup nrf_pwm
59 * @brief Hardware access layer with cache and barrier support for managing the PWM peripheral.
60 */
61
62 /** @brief PWM configuration structure. */
63 typedef struct
64 {
65 uint32_t output_pins[NRF_PWM_CHANNEL_COUNT]; ///< Pin numbers for individual output channels (optional).
66 /**< Use @ref NRF_PWM_PIN_NOT_CONNECTED
67 * if a given output channel is not needed. */
68 uint16_t top_value; ///< Value up to which the pulse generator counter counts.
69 nrf_pwm_clk_t base_clock; ///< Base clock frequency.
70 nrf_pwm_mode_t count_mode; ///< Operating mode of the pulse generator counter.
71 nrf_pwm_dec_load_t load_mode; ///< Mode of loading sequence data from RAM.
72 nrf_pwm_dec_step_t step_mode; ///< Mode of advancing the active sequence.
73 bool skip_psel_cfg; ///< Skip pin selection configuration.
74 /**< When set to true, the driver does not modify
75 * pin select registers in the peripheral.
76 * Those registers are supposed to be set up
77 * externally before the driver is initialized.
78 * @note When both GPIO configuration and pin
79 * selection are to be skipped, the structure
80 * fields that specify pins can be omitted,
81 * as they are ignored anyway. */
82 } nrfy_pwm_config_t;
83
84 /**
85 * @brief Function for configuring the PWM.
86 *
87 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
88 * @param[in] p_config Pointer to the peripheral configuration structure.
89 */
nrfy_pwm_periph_configure(NRF_PWM_Type * p_reg,nrfy_pwm_config_t const * p_config)90 NRFY_STATIC_INLINE void nrfy_pwm_periph_configure(NRF_PWM_Type * p_reg,
91 nrfy_pwm_config_t const * p_config)
92 {
93 if (!p_config->skip_psel_cfg)
94 {
95 nrf_pwm_pins_set(p_reg, p_config->output_pins);
96 }
97 nrf_pwm_configure(p_reg, p_config->base_clock, p_config->count_mode, p_config->top_value);
98 nrf_pwm_decoder_set(p_reg, p_config->load_mode, p_config->step_mode);
99 nrf_barrier_w();
100 }
101
102 /**
103 * @brief Function for initializing the specified PWM interrupts.
104 *
105 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
106 * @param[in] mask Mask of interrupts to be initialized.
107 * @param[in] irq_priority Interrupt priority.
108 * @param[in] enable True if interrupts are to be enabled, false otherwise.
109 */
nrfy_pwm_int_init(NRF_PWM_Type * p_reg,uint32_t mask,uint8_t irq_priority,bool enable)110 NRFY_STATIC_INLINE void nrfy_pwm_int_init(NRF_PWM_Type * p_reg,
111 uint32_t mask,
112 uint8_t irq_priority,
113 bool enable)
114 {
115 __nrfy_internal_pwm_event_enabled_clear(p_reg, mask, NRF_PWM_EVENT_LOOPSDONE);
116 __nrfy_internal_pwm_event_enabled_clear(p_reg, mask, NRF_PWM_EVENT_SEQEND0);
117 __nrfy_internal_pwm_event_enabled_clear(p_reg, mask, NRF_PWM_EVENT_SEQEND1);
118 __nrfy_internal_pwm_event_enabled_clear(p_reg, mask, NRF_PWM_EVENT_STOPPED);
119 __nrfy_internal_pwm_event_enabled_clear(p_reg, mask, NRF_PWM_EVENT_SEQSTARTED0);
120 __nrfy_internal_pwm_event_enabled_clear(p_reg, mask, NRF_PWM_EVENT_SEQSTARTED1);
121 __nrfy_internal_pwm_event_enabled_clear(p_reg, mask, NRF_PWM_EVENT_PWMPERIODEND);
122 nrf_barrier_w();
123
124 NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_reg), irq_priority);
125 NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_reg));
126
127 if (enable)
128 {
129 nrf_pwm_int_enable(p_reg, mask);
130 }
131 nrf_barrier_w();
132 }
133
134 /**
135 * @brief Function for uninitializing the PWM interrupts.
136 *
137 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
138 */
nrfy_pwm_int_uninit(NRF_PWM_Type * p_reg)139 NRFY_STATIC_INLINE void nrfy_pwm_int_uninit(NRF_PWM_Type * p_reg)
140 {
141 NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_reg));
142 nrf_barrier_w();
143 }
144
145 /**
146 * @brief Function for processing the specified PWM events.
147 *
148 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
149 * @param[in] mask Mask of events to be processed, created by @ref NRFY_EVENT_TO_INT_BITMASK.
150 *
151 * @return Mask of events that were generated and processed.
152 * To be checked against the result of @ref NRFY_EVENT_TO_INT_BITMASK().
153 */
nrfy_pwm_events_process(NRF_PWM_Type * p_reg,uint32_t mask)154 NRFY_STATIC_INLINE uint32_t nrfy_pwm_events_process(NRF_PWM_Type * p_reg, uint32_t mask)
155 {
156 nrf_barrier_r();
157 uint32_t evt_mask = __nrfy_internal_pwm_events_process(p_reg, mask);
158 nrf_barrier_w();
159 return evt_mask;
160 }
161
162 /**
163 * @brief Function for starting the PWM sequence.
164 *
165 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
166 * @param[in] seq_id Sequence index.
167 * @param[in] wait True if the sequence is to be blocking, false otherwise.
168 */
nrfy_pwm_start(NRF_PWM_Type * p_reg,uint8_t seq_id,bool wait)169 NRFY_STATIC_INLINE void nrfy_pwm_start(NRF_PWM_Type * p_reg,
170 uint8_t seq_id,
171 bool wait)
172 {
173 nrf_pwm_task_trigger(p_reg, nrf_pwm_seqstart_task_get(seq_id));
174
175 if (wait)
176 {
177 nrf_barrier_w();
178 uint32_t evt_mask = NRFY_EVENT_TO_INT_BITMASK(nrf_pwm_seqend_event_get(seq_id));
179 while (!__nrfy_internal_pwm_events_process(p_reg, evt_mask))
180 {}
181 }
182 nrf_barrier_w();
183 }
184
185 /**
186 * @brief Function for aborting the ongoing PWM sequence.
187 *
188 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
189 * @param[in] wait True if the abort is to be blocking, false otherwise.
190 */
nrfy_pwm_abort(NRF_PWM_Type * p_reg,bool wait)191 NRFY_STATIC_INLINE void nrfy_pwm_abort(NRF_PWM_Type * p_reg, bool wait)
192 {
193 nrf_pwm_task_trigger(p_reg, NRF_PWM_TASK_STOP);
194
195 if (wait)
196 {
197 nrf_barrier_w();
198 uint32_t evt_mask = NRFY_EVENT_TO_INT_BITMASK(NRF_PWM_EVENT_STOPPED);
199 while (!__nrfy_internal_pwm_events_process(p_reg, evt_mask))
200 {}
201 (void)__nrfy_internal_pwm_events_process(p_reg,
202 NRFY_EVENT_TO_INT_BITMASK(NRF_PWM_EVENT_SEQEND0) |
203 NRFY_EVENT_TO_INT_BITMASK(NRF_PWM_EVENT_SEQEND1));
204 }
205 nrf_barrier_w();
206 }
207
208 /** @refhal{nrf_pwm_task_trigger} */
nrfy_pwm_task_trigger(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)209 NRFY_STATIC_INLINE void nrfy_pwm_task_trigger(NRF_PWM_Type * p_reg,
210 nrf_pwm_task_t task)
211 {
212 nrf_pwm_task_trigger(p_reg, task);
213 nrf_barrier_w();
214 }
215
216 /** @refhal{nrf_pwm_task_address_get} */
nrfy_pwm_task_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_task_t task)217 NRFY_STATIC_INLINE uint32_t nrfy_pwm_task_address_get(NRF_PWM_Type const * p_reg,
218 nrf_pwm_task_t task)
219 {
220 return nrf_pwm_task_address_get(p_reg, task);
221 }
222
223 /** @refhal{nrf_pwm_event_clear} */
nrfy_pwm_event_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)224 NRFY_STATIC_INLINE void nrfy_pwm_event_clear(NRF_PWM_Type * p_reg,
225 nrf_pwm_event_t event)
226 {
227 nrf_pwm_event_clear(p_reg, event);
228 nrf_barrier_w();
229 }
230
231 /** @refhal{nrf_pwm_event_check} */
nrfy_pwm_event_check(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)232 NRFY_STATIC_INLINE bool nrfy_pwm_event_check(NRF_PWM_Type const * p_reg,
233 nrf_pwm_event_t event)
234 {
235 nrf_barrier_r();
236 bool ret = nrf_pwm_event_check(p_reg, event);
237 nrf_barrier_r();
238 return ret;
239 }
240
241 /** @refhal{nrf_pwm_event_address_get} */
nrfy_pwm_event_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)242 NRFY_STATIC_INLINE uint32_t nrfy_pwm_event_address_get(NRF_PWM_Type const * p_reg,
243 nrf_pwm_event_t event)
244 {
245 return nrf_pwm_event_address_get(p_reg, event);
246 }
247
248 /** @refhal{nrf_pwm_shorts_enable} */
nrfy_pwm_shorts_enable(NRF_PWM_Type * p_reg,uint32_t mask)249 NRFY_STATIC_INLINE void nrfy_pwm_shorts_enable(NRF_PWM_Type * p_reg,
250 uint32_t mask)
251 {
252 nrf_pwm_shorts_enable(p_reg, mask);
253 nrf_barrier_w();
254 }
255
256 /** @refhal{nrf_pwm_shorts_disable} */
nrfy_pwm_shorts_disable(NRF_PWM_Type * p_reg,uint32_t mask)257 NRFY_STATIC_INLINE void nrfy_pwm_shorts_disable(NRF_PWM_Type * p_reg,
258 uint32_t mask)
259 {
260 nrf_pwm_shorts_disable(p_reg, mask);
261 nrf_barrier_w();
262 }
263
264 /** @refhal{nrf_pwm_shorts_set} */
nrfy_pwm_shorts_set(NRF_PWM_Type * p_reg,uint32_t mask)265 NRFY_STATIC_INLINE void nrfy_pwm_shorts_set(NRF_PWM_Type * p_reg,
266 uint32_t mask)
267 {
268 nrf_pwm_shorts_set(p_reg, mask);
269 nrf_barrier_w();
270 }
271
272 /** @refhal{nrf_pwm_int_enable} */
nrfy_pwm_int_enable(NRF_PWM_Type * p_reg,uint32_t mask)273 NRFY_STATIC_INLINE void nrfy_pwm_int_enable(NRF_PWM_Type * p_reg,
274 uint32_t mask)
275 {
276 nrf_pwm_int_enable(p_reg, mask);
277 nrf_barrier_w();
278 }
279
280 /** @refhal{nrf_pwm_int_disable} */
nrfy_pwm_int_disable(NRF_PWM_Type * p_reg,uint32_t mask)281 NRFY_STATIC_INLINE void nrfy_pwm_int_disable(NRF_PWM_Type * p_reg,
282 uint32_t mask)
283 {
284 nrf_pwm_int_disable(p_reg, mask);
285 nrf_barrier_w();
286 }
287
288 /** @refhal{nrf_pwm_int_set} */
nrfy_pwm_int_set(NRF_PWM_Type * p_reg,uint32_t mask)289 NRFY_STATIC_INLINE void nrfy_pwm_int_set(NRF_PWM_Type * p_reg,
290 uint32_t mask)
291 {
292 nrf_pwm_int_set(p_reg, mask);
293 nrf_barrier_w();
294 }
295
296 /** @refhal{nrf_pwm_int_enable_check} */
nrfy_pwm_int_enable_check(NRF_PWM_Type const * p_reg,uint32_t mask)297 NRFY_STATIC_INLINE uint32_t nrfy_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask)
298 {
299 nrf_barrier_rw();
300 uint32_t ret = nrf_pwm_int_enable_check(p_reg, mask);
301 nrf_barrier_r();
302 return ret;
303 }
304
305 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
306 /** @refhal{nrf_pwm_subscribe_set} */
nrfy_pwm_subscribe_set(NRF_PWM_Type * p_reg,nrf_pwm_task_t task,uint8_t channel)307 NRFY_STATIC_INLINE void nrfy_pwm_subscribe_set(NRF_PWM_Type * p_reg,
308 nrf_pwm_task_t task,
309 uint8_t channel)
310 {
311 nrf_pwm_subscribe_set(p_reg, task, channel);
312 nrf_barrier_w();
313 }
314
315 /** @refhal{nrf_pwm_subscribe_clear} */
nrfy_pwm_subscribe_clear(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)316 NRFY_STATIC_INLINE void nrfy_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
317 nrf_pwm_task_t task)
318 {
319 nrf_pwm_subscribe_clear(p_reg, task);
320 nrf_barrier_w();
321 }
322
323 /** @refhal{nrf_pwm_publish_set} */
nrfy_pwm_publish_set(NRF_PWM_Type * p_reg,nrf_pwm_event_t event,uint8_t channel)324 NRFY_STATIC_INLINE void nrfy_pwm_publish_set(NRF_PWM_Type * p_reg,
325 nrf_pwm_event_t event,
326 uint8_t channel)
327 {
328 nrf_pwm_publish_set(p_reg, event, channel);
329 nrf_barrier_w();
330 }
331
332 /** @refhal{nrf_pwm_publish_clear} */
nrfy_pwm_publish_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)333 NRFY_STATIC_INLINE void nrfy_pwm_publish_clear(NRF_PWM_Type * p_reg,
334 nrf_pwm_event_t event)
335 {
336 nrf_pwm_publish_clear(p_reg, event);
337 nrf_barrier_w();
338 }
339 #endif
340
341 /** @refhal{nrf_pwm_enable} */
nrfy_pwm_enable(NRF_PWM_Type * p_reg)342 NRFY_STATIC_INLINE void nrfy_pwm_enable(NRF_PWM_Type * p_reg)
343 {
344 nrf_pwm_enable(p_reg);
345 nrf_barrier_w();
346 }
347
348 /** @refhal{nrf_pwm_disable} */
nrfy_pwm_disable(NRF_PWM_Type * p_reg)349 NRFY_STATIC_INLINE void nrfy_pwm_disable(NRF_PWM_Type * p_reg)
350 {
351 nrf_pwm_disable(p_reg);
352 nrf_barrier_w();
353 }
354
355 /** @refhal{nrf_pwm_enable_check} */
nrfy_pwm_enable_check(NRF_PWM_Type * p_reg)356 NRFY_STATIC_INLINE bool nrfy_pwm_enable_check(NRF_PWM_Type * p_reg)
357 {
358 nrf_barrier_rw();
359 bool enabled = nrf_pwm_enable_check(p_reg);
360 nrf_barrier_r();
361 return enabled;
362 }
363
364 /** @refhal{nrf_pwm_pins_set} */
nrfy_pwm_pins_set(NRF_PWM_Type * p_reg,uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])365 NRFY_STATIC_INLINE void nrfy_pwm_pins_set(NRF_PWM_Type * p_reg,
366 uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])
367 {
368 nrf_pwm_pins_set(p_reg, out_pins);
369 nrf_barrier_w();
370 }
371
372 /** @refhal{nrf_pwm_pin_get} */
nrfy_pwm_pin_get(NRF_PWM_Type const * p_reg,uint8_t channel)373 NRFY_STATIC_INLINE uint32_t nrfy_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel)
374 {
375 nrf_barrier_rw();
376 uint32_t ret = nrf_pwm_pin_get(p_reg, channel);
377 nrf_barrier_r();
378 return ret;
379 }
380
381 /** @refhal{nrf_pwm_configure} */
nrfy_pwm_configure(NRF_PWM_Type * p_reg,nrf_pwm_clk_t base_clock,nrf_pwm_mode_t mode,uint16_t top_value)382 NRFY_STATIC_INLINE void nrfy_pwm_configure(NRF_PWM_Type * p_reg,
383 nrf_pwm_clk_t base_clock,
384 nrf_pwm_mode_t mode,
385 uint16_t top_value)
386 {
387 nrf_pwm_configure(p_reg, base_clock, mode, top_value);
388 nrf_barrier_w();
389 }
390
391 /** @refhal{nrf_pwm_sequence_set} */
nrfy_pwm_sequence_set(NRF_PWM_Type * p_reg,uint8_t seq_id,nrf_pwm_sequence_t const * p_seq)392 NRFY_STATIC_INLINE void nrfy_pwm_sequence_set(NRF_PWM_Type * p_reg,
393 uint8_t seq_id,
394 nrf_pwm_sequence_t const * p_seq)
395 {
396 NRFY_CACHE_WB(p_seq->values.p_raw, p_seq->length);
397 nrf_pwm_sequence_set(p_reg, seq_id, p_seq);
398 nrf_barrier_w();
399 }
400
401 /** @refhal{nrf_pwm_decoder_set} */
nrfy_pwm_decoder_set(NRF_PWM_Type * p_reg,nrf_pwm_dec_load_t dec_load,nrf_pwm_dec_step_t dec_step)402 NRFY_STATIC_INLINE void nrfy_pwm_decoder_set(NRF_PWM_Type * p_reg,
403 nrf_pwm_dec_load_t dec_load,
404 nrf_pwm_dec_step_t dec_step)
405 {
406 nrf_pwm_decoder_set(p_reg, dec_load, dec_step);
407 nrf_barrier_w();
408 }
409
410 /** @refhal{nrf_pwm_loop_set} */
nrfy_pwm_loop_set(NRF_PWM_Type * p_reg,uint16_t loop_count)411 NRFY_STATIC_INLINE void nrfy_pwm_loop_set(NRF_PWM_Type * p_reg, uint16_t loop_count)
412 {
413 nrf_pwm_loop_set(p_reg, loop_count);
414 nrf_barrier_w();
415 }
416
417 /** @refhal{nrf_pwm_seqstart_task_get} */
nrfy_pwm_seqstart_task_get(uint8_t seq_id)418 NRFY_STATIC_INLINE nrf_pwm_task_t nrfy_pwm_seqstart_task_get(uint8_t seq_id)
419 {
420 return nrf_pwm_seqstart_task_get(seq_id);
421 }
422
423 /** @refhal{nrf_pwm_seqend_event_get} */
nrfy_pwm_seqend_event_get(uint8_t seq_id)424 NRFY_STATIC_INLINE nrf_pwm_event_t nrfy_pwm_seqend_event_get(uint8_t seq_id)
425 {
426 return nrf_pwm_seqend_event_get(seq_id);
427 }
428
429 /** @} */
430
__nrfy_internal_pwm_event_handle(NRF_PWM_Type * p_reg,uint32_t mask,nrf_pwm_event_t event,uint32_t * p_evt_mask)431 NRFY_STATIC_INLINE bool __nrfy_internal_pwm_event_handle(NRF_PWM_Type * p_reg,
432 uint32_t mask,
433 nrf_pwm_event_t event,
434 uint32_t * p_evt_mask)
435 {
436 if ((mask & NRFY_EVENT_TO_INT_BITMASK(event)) && nrf_pwm_event_check(p_reg, event))
437 {
438 nrf_barrier_r();
439 nrf_pwm_event_clear(p_reg, event);
440 if (p_evt_mask)
441 {
442 *p_evt_mask |= NRFY_EVENT_TO_INT_BITMASK(event);
443 }
444 return true;
445 }
446 return false;
447 }
448
__nrfy_internal_pwm_events_process(NRF_PWM_Type * p_reg,uint32_t mask)449 NRFY_STATIC_INLINE uint32_t __nrfy_internal_pwm_events_process(NRF_PWM_Type * p_reg, uint32_t mask)
450 {
451 uint32_t evt_mask = 0;
452
453 (void)__nrfy_internal_pwm_event_handle(p_reg, mask, NRF_PWM_EVENT_SEQEND0, &evt_mask);
454 (void)__nrfy_internal_pwm_event_handle(p_reg, mask, NRF_PWM_EVENT_SEQEND1, &evt_mask);
455 (void)__nrfy_internal_pwm_event_handle(p_reg, mask, NRF_PWM_EVENT_LOOPSDONE, &evt_mask);
456 (void)__nrfy_internal_pwm_event_handle(p_reg, mask, NRF_PWM_EVENT_STOPPED, &evt_mask);
457 (void)__nrfy_internal_pwm_event_handle(p_reg, mask, NRF_PWM_EVENT_SEQSTARTED0, &evt_mask);
458 (void)__nrfy_internal_pwm_event_handle(p_reg, mask, NRF_PWM_EVENT_SEQSTARTED1, &evt_mask);
459 (void)__nrfy_internal_pwm_event_handle(p_reg, mask, NRF_PWM_EVENT_PWMPERIODEND, &evt_mask);
460
461 return evt_mask;
462 }
463
__nrfy_internal_pwm_event_enabled_clear(NRF_PWM_Type * p_reg,uint32_t mask,nrf_pwm_event_t event)464 NRFY_STATIC_INLINE void __nrfy_internal_pwm_event_enabled_clear(NRF_PWM_Type * p_reg,
465 uint32_t mask,
466 nrf_pwm_event_t event)
467 {
468 if (mask & NRFY_EVENT_TO_INT_BITMASK(event))
469 {
470 nrf_pwm_event_clear(p_reg, event);
471 }
472 }
473
474 #ifdef __cplusplus
475 }
476 #endif
477
478 #endif // NRFY_PWM_H__
479
